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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / rtx / synopsys / script / user_cfg.scr
CommitLineData
86530b38
AT		 1source -echo -verbose $dv_root/design/sys/synopsys/script/project_io_cfg.scr
2
3set rtl_files {\
4libs/cl/cl_rtl_ext.v
5libs/cl/cl_a1/cl_a1.behV
6libs/cl/cl_u1/cl_u1.behV
7libs/cl/cl_dp1/cl_dp1.behV
8libs/cl/cl_sc1/cl_sc1.behV
9libs/cl/cl_mc1/cl_mc1.v
10
11libs/clk/rtl/clkgen_rtx_io2x.v
12libs/clk/rtl/clkgen_rtx_io.v
13
14libs/clk/n2_clk_clstr_hdr_cust_l/n2_clk_clstr_hdr_cust/rtl/n2_clk_clstr_hdr_cust.v
15libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io_cust/rtl/n2_clk_rtx_io_cust.v
16libs/clk/n2_clk_pgrid_cust_l/n2_clk_rtx_io2x_cust/rtl/n2_clk_rtx_io2x_cust.v
17
18libs/n2sram/dp/n2_niu_dp_512x152s_cust_l/n2_niu_dp_512x152s_cust/rtl/n2_niu_dp_512x152s_cust.v
19libs/n2sram/dp/n2_niu_dp_1024x152s_cust_l/n2_niu_dp_1024x152s_cust/rtl/n2_niu_dp_1024x152s_cust.v
20libs/n2sram/sp/n2_niu_sp_4096x9s_cust_l/n2_niu_sp_4096x9s_cust/rtl/n2_niu_sp_4096x9s_cust.v
21
22libs/n2sram/compiler/physical/n2_com_dp_128x42s_cust_l/n2_com_dp_128x42s_cust/rtl/n2_com_dp_128x42s_cust.v
23libs/n2sram/compiler/physical/n2_com_dp_64x148s_cust_l/n2_com_dp_64x148s_cust/rtl/n2_com_dp_64x148s_cust.v
24libs/n2sram/cams/n2_niu_tc_128x200s_cust_l/n2_niu_tc_128x200s_cust/rtl/n2_niu_tc_128x200s_cust.v
25
26design/sys/iop/niu/rtl/df1.v
27design/sys/iop/niu/rtl/dffe.v
28design/sys/iop/niu/rtl/dffr.v
29design/sys/iop/niu/rtl/dffre.v
30
31design/sys/iop/niu/rtl/niu_ram_64_146.v
32design/sys/iop/niu/rtl/niu_ram_1024_146.v
33design/sys/iop/niu/rtl/niu_ram_1024_152.v
34design/sys/iop/niu/rtl/niu_cam_128x200.v
35design/sys/iop/niu/rtl/niu_ram_s_4096x9.v
36design/sys/iop/niu/rtl/niu_ram_128_42.v
37design/sys/iop/niu/rtl/niu_ram_64x146.v
38design/sys/iop/niu/rtl/niu_ram_1024x152.v
39design/sys/iop/niu/rtl/niu_ram_512_146.v
40
41design/sys/iop/niu/rtl/timescale.v
42design/sys/iop/niu/rtl/niu_65data_ecc_check.v
43design/sys/iop/niu/rtl/niu_65data_ecc_generate.v
44design/sys/iop/niu/rtl/niu_65data_ecc_generate_w_err_injection.v
45design/sys/iop/niu/rtl/niu_65data_ecc_correct.v
46design/sys/iop/niu/rtl/niu_64data_ecc_check.v
47design/sys/iop/niu/rtl/niu_64data_ecc_generate.v
48design/sys/iop/niu/rtl/niu_dff.v
49design/sys/iop/niu/rtl/reset_buffer.v
50
51design/sys/iop/niu/rtl/niu_mb1.v
52design/sys/iop/niu/rtl/niu_mb2.v
53design/sys/iop/niu/rtl/niu_mb3.v
54design/sys/iop/niu/rtl/niu_mb4.v
55design/sys/iop/niu/rtl/niu_mb5.v
56design/sys/iop/niu/rtl/niu_mb6.v
57design/sys/iop/niu/rtl/niu_mb7.v
58design/sys/iop/niu/rtl/niu_zcp.h
59design/sys/iop/niu/rtl/niu_scam.h
60design/sys/iop/niu/rtl/fflp.h
61
62design/sys/iop/niu/rtl/niu_rxc.v
63design/sys/iop/niu/rtl/niu_scam_ary.v
64design/sys/iop/niu/rtl/niu_scam_ctl.v
65design/sys/iop/niu/rtl/niu_scam_enc.v
66design/sys/iop/niu/rtl/niu_scam_lib.v
67design/sys/iop/niu/rtl/niu_scam_pre.v
68design/sys/iop/niu/rtl/niu_tcam.v
69design/sys/iop/niu/rtl/niu_ipp.h
70design/sys/iop/niu/rtl/niu_ipp_1ke.v
71design/sys/iop/niu/rtl/niu_ipp_dat_fifo_1ke.v
72design/sys/iop/niu/rtl/niu_ipp_dmc_checker.v
73design/sys/iop/niu/rtl/niu_ipp_ffl_arbiter.v
74design/sys/iop/niu/rtl/niu_ipp_hdr_fifo.v
75design/sys/iop/niu/rtl/niu_ipp_lib.v
76design/sys/iop/niu/rtl/niu_ipp_load.v
77design/sys/iop/niu/rtl/niu_ipp_pkt_dsc.v
78design/sys/iop/niu/rtl/niu_ipp_slv.v
79design/sys/iop/niu/rtl/niu_ipp_sum_ctrl.v
80design/sys/iop/niu/rtl/niu_ipp_sum_data.v
81design/sys/iop/niu/rtl/niu_ipp_sum_lib.v
82design/sys/iop/niu/rtl/niu_ipp_sum_unit.v
83design/sys/iop/niu/rtl/niu_ipp_sum_lib.h
84design/sys/iop/niu/rtl/niu_ipp_top.v
85design/sys/iop/niu/rtl/niu_ipp_unload_ctl_1ke.v
86design/sys/iop/niu/rtl/niu_ipp_unload_dat.v
87
88design/sys/iop/niu/rtl/fflp.h
89design/sys/iop/niu/rtl/fflp.v
90design/sys/iop/niu/rtl/fflp_cam_ram.v
91design/sys/iop/niu/rtl/fflp_cam_sched.v
92design/sys/iop/niu/rtl/fflp_cam_srch.v
93design/sys/iop/niu/rtl/fflp_cam_srch_sm.v
94design/sys/iop/niu/rtl/fflp_fcram_arb.v
95design/sys/iop/niu/rtl/fflp_fcram_cntl.v
96design/sys/iop/niu/rtl/fflp_fcram_cntl_sm.v
97design/sys/iop/niu/rtl/fflp_fcram_fwd_arb.v
98design/sys/iop/niu/rtl/fflp_fcram_sched.v
99design/sys/iop/niu/rtl/fflp_fcram_top.v
100design/sys/iop/niu/rtl/fflp_fwd_mstr.v
101design/sys/iop/niu/rtl/fflp_hdr.v
102design/sys/iop/niu/rtl/fflp_flow_fifo.v
103design/sys/iop/niu/rtl/fflp_hdr_cntl.v
104design/sys/iop/niu/rtl/fflp_hdr_dp.v
105design/sys/iop/niu/rtl/fflp_hdr_fifo.v
106design/sys/iop/niu/rtl/fflp_merge_func.v
107design/sys/iop/niu/rtl/fflp_pio_if.v
108design/sys/iop/niu/rtl/fflp_ram_cntl.v
109design/sys/iop/niu/rtl/fflp_CRC32_D64.v
110design/sys/iop/niu/rtl/fflp_CRC16_D64.v
111design/sys/iop/niu/rtl/fflp_hash_func.v
112design/sys/iop/niu/rtl/fflp_sync2fc_clk.v
113design/sys/iop/niu/rtl/fflp_sync2sys_clk.v
114
115design/sys/iop/niu/rtl/niu_zcp.h
116design/sys/iop/niu/rtl/niu_zcp.v
117design/sys/iop/niu/rtl/niu_zcp_fflp_intf.v
118design/sys/iop/niu/rtl/niu_zcp_ififo_sm.v
119design/sys/iop/niu/rtl/niu_zcp_ififo.v
120design/sys/iop/niu/rtl/niu_zcp_cfifo8KB.v
121design/sys/iop/niu/rtl/niu_zcp_tt.v
122design/sys/iop/niu/rtl/niu_zcp_tt_sm.v
123design/sys/iop/niu/rtl/niu_zcp_slv.v
124design/sys/iop/niu/rtl/niu_zcp_ram_access_sm.v
125design/sys/iop/niu/rtl/niu_zcp_handle_decoder.v
126design/sys/iop/niu/rtl/niu_zcp_macros.v
127design/sys/iop/niu/rtl/niu_zcp_reset_gen.v
128design/sys/iop/niu/rtl/niu_zcp_debug.v
129
130design/sys/iop/niu/rtl/txc_defines.h
131design/sys/iop/niu/rtl/niu_txc.v
132design/sys/iop/niu/rtl/niu_txc_ControlRegs.v
133design/sys/iop/niu/rtl/niu_txc_dataFetch.v
134design/sys/iop/niu/rtl/niu_txc_drr_arbiter.v
135design/sys/iop/niu/rtl/niu_txc_drr_context.v
136design/sys/iop/niu/rtl/niu_txc_drr_engine.v
137design/sys/iop/niu/rtl/niu_txc_ecc_engine.v
138design/sys/iop/niu/rtl/niu_txc_ecc_correct.v
139design/sys/iop/niu/rtl/niu_txc_ecc_generate.v
140design/sys/iop/niu/rtl/niu_txc_ecc_syndrome.v
141design/sys/iop/niu/rtl/niu_txc_mac_transfer.v
142design/sys/iop/niu/rtl/niu_txc_packetAssy.v
143design/sys/iop/niu/rtl/niu_txc_packetEngine.v
144design/sys/iop/niu/rtl/niu_txc_portRequest.v
145design/sys/iop/niu/rtl/niu_txc_portRegisters.v
146design/sys/iop/niu/rtl/niu_txc_reAligner.v
147design/sys/iop/niu/rtl/niu_txc_RegisterControl.v
148design/sys/iop/niu/rtl/niu_txc_dmaRegisters.v
149design/sys/iop/niu/rtl/niu_txc_reg_defines.h
150design/sys/iop/niu/rtl/niu_txc_Reset.v
151design/sys/iop/niu/rtl/niu_txc_debug.v
152design/sys/iop/niu/rtl/niu_txc_tdmc_ifc.v
153design/sys/iop/niu/rtl/niu_txc_tdmc_context.v
154design/sys/iop/niu/rtl/niu_txc_mac_ifc.v
155design/sys/iop/niu/rtl/niu_txc_meta_resp_ifc.v
156design/sys/iop/niu/rtl/niu_txc_tdmc_error.v
157design/sys/iop/niu/rtl/niu_txc_clkbuf.v
158
159design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p0_ctl.v
160design/sys/iop/rtx/rtl/rtx_n2_efuhdr1a_p1_ctl.v
161design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p0_ctl.v
162design/sys/iop/rtx/rtl/rtx_n2_efuhdr1b_p1_ctl.v
163design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p0_ctl.v
164design/sys/iop/rtx/rtl/rtx_n2_efuhdr3_p1_ctl.v
165design/sys/iop/rtx/rtl/rtx_n2_efuhdr6_ctl.v
166design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p0_ctl.v
167design/sys/iop/rtx/rtl/rtx_n2_efuhdr7_p1_ctl.v
168design/sys/iop/rtx/rtl/clkgen_rtx.v
169design/sys/iop/rtx/rtl/clkgen2x_rtx.v
170design/sys/iop/rtx/rtl/rtx_dmo_mux.v
171design/sys/iop/rtx/rtl/rtx.v
172}
173
174set link_library [concat $link_library \
175 dw_foundation.sldb \
176]
177
178
179set mix_files {}
180set top_module rtx
181
182set include_paths {\
183}
184
185set black_box_libs {}
186set black_box_designs {}
187set mem_libs {}
188
189set dont_touch_modules {\
190n2_niu_dp_1024x152s_cust \
191n2_niu_dp_512x152s_cust \
192n2_niu_sp_4096x9s_cust \
193n2_com_dp_64x148s_cust \
194n2_com_dp_128x42s_cust \
195n2_niu_tc_128x200s_cust \
196}
197
198set compile_effort "medium"
199
200set compile_flatten_all 1
201
202set compile_no_new_cells_at_top_level false
203
204set default_clk cmp_gclk_c0_rtx
205set default_clk_freq 1500
206set default_setup_skew 0.0
207set default_hold_skew 0.0
208set default_clk_transition 0.05
209set clk_list { \
210 { cmp_gclk_c0_rtx 1500.0 0.000 0.000 0.05} \
211}
212
213set ideal_net_list {}
214set false_path_list {}
215set enforce_input_fanout_one 0
216set allow_outport_drive_innodes 1
217set skip_scan 0
218set add_lockup_latch false
219set chain_count 1
220set scanin_port_list {}
221set scanout_port_list {}
222set scanenable_port global_shift_enable
223set has_test_stub 1
224set scanenable_pin test_stub_no_bist/se
225set long_chain_so_0_net long_chain_so_0
226set short_chain_so_0_net short_chain_so_0
227set so_0_net so_0
228set insert_extra_lockup_latch 0
229set extra_lockup_latch_clk_list {}
Full OpenSPARC design & verification tarball including full HDL.