Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sii_ild_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sii_ild_dp ( | |
36 | sii_l2t_req, | |
37 | sii_l2b_ecc, | |
38 | ilc_ild_de_sel, | |
39 | ilc_ild_ldhdr, | |
40 | ilc_ild_addr_h, | |
41 | ilc_ild_addr_lo, | |
42 | ilc_ild_hdr_sel, | |
43 | ilc_ild_cyc_sel, | |
44 | ilc_ild_newhdr, | |
45 | ild_ilc_curhdr, | |
46 | ildq_ild_dout, | |
47 | ipcc_data_out, | |
48 | l2clk, | |
49 | scan_in, | |
50 | scan_out, | |
51 | tcu_scan_en, | |
52 | tcu_aclk, | |
53 | tcu_bclk, | |
54 | tcu_pce_ov, | |
55 | tcu_clk_stop, | |
56 | sii_mb0_wdata, | |
57 | sii_mb0_ild_fail); | |
58 | wire [1:0] cmp_err; | |
59 | wire [1:0] sii_mb0_ild_fail_l; | |
60 | wire ff_sii_mb0_ild_fail_scanin; | |
61 | wire ff_sii_mb0_ild_fail_scanout; | |
62 | wire ff_sii_mb0_wdata_rrr_scanin; | |
63 | wire ff_sii_mb0_wdata_rrr_scanout; | |
64 | wire [7:0] sii_mb0_wdata_rr; | |
65 | wire [7:0] sii_mb0_wdata_rrr; | |
66 | wire ff_sii_mb0_wdata_rr_scanin; | |
67 | wire ff_sii_mb0_wdata_rr_scanout; | |
68 | wire [7:0] sii_mb0_wdata_r; | |
69 | wire ff_sii_mb0_wdata_r_scanin; | |
70 | wire ff_sii_mb0_wdata_r_scanout; | |
71 | wire [31:0] mb_data; | |
72 | wire se; | |
73 | wire siclk; | |
74 | wire soclk; | |
75 | wire pce_ov; | |
76 | wire stop; | |
77 | wire ilc_ild_de_sel_cyc_unused; | |
78 | wire [1:0] ilc_ild_de_sel_cyc; | |
79 | wire [13:0] ildq_ild_ecc; | |
80 | wire [63:0] ildq_ild_data; | |
81 | wire [69:0] ild_curhdr_ecc; | |
82 | wire [6:0] hdr_ecc; | |
83 | wire ff_sii_l2b_ecc_scanin; | |
84 | wire ff_sii_l2b_ecc_scanout; | |
85 | wire [6:0] sii_l2b_ecc_hdr; | |
86 | wire sii_l2b_ecc_unused; | |
87 | wire sii_l2b_ecc_hdr_unused; | |
88 | wire [6:0] sii_l2b_ecc_l; | |
89 | wire sii_l2b_ecc_l_unused; | |
90 | wire ff_sii_l2t_req_scanin; | |
91 | wire ff_sii_l2t_req_scanout; | |
92 | wire [31:0] sii_l2t_req_l; | |
93 | wire [69:0] sii_l2t_hdr0; | |
94 | wire [69:0] sii_l2t_hdr1; | |
95 | wire [69:0] sii_l2t_hdr2; | |
96 | wire [69:0] sii_l2t_hdr3; | |
97 | wire [69:0] ipcc_data_out_buff; | |
98 | wire ff_sii_l2t_hdr0_scanin; | |
99 | wire ff_sii_l2t_hdr0_scanout; | |
100 | wire ff_sii_l2t_hdr1_scanin; | |
101 | wire ff_sii_l2t_hdr1_scanout; | |
102 | wire ff_sii_l2t_hdr2_scanin; | |
103 | wire ff_sii_l2t_hdr2_scanout; | |
104 | wire ff_sii_l2t_hdr3_scanin; | |
105 | wire ff_sii_l2t_hdr3_scanout; | |
106 | ||
107 | ||
108 | output [31:0] sii_l2t_req; | |
109 | output [6:0] sii_l2b_ecc; | |
110 | ||
111 | //------inter-submodule signals------- | |
112 | ||
113 | input [1:0] ilc_ild_de_sel; | |
114 | input [3:0] ilc_ild_ldhdr; // load into the hdr register | |
115 | input [3:0] ilc_ild_addr_h; // select the header register | |
116 | input [3:0] ilc_ild_addr_lo; // select the header register | |
117 | input [1:0] ilc_ild_hdr_sel; // select hdr cycle 1 or 2 | |
118 | input [1:0] ilc_ild_cyc_sel; | |
119 | input [63:0] ilc_ild_newhdr; // l2 formatted header | |
120 | output [63:0] ild_ilc_curhdr; // current transaction hdr | |
121 | ||
122 | //-------from data path ----------- | |
123 | input [81:0] ildq_ild_dout; // from the queue for data | |
124 | input [69:0] ipcc_data_out; // partial from data bus for header | |
125 | ||
126 | input l2clk; | |
127 | input scan_in; | |
128 | output scan_out; | |
129 | ||
130 | input tcu_scan_en; | |
131 | input tcu_aclk; | |
132 | input tcu_bclk; | |
133 | input tcu_pce_ov; | |
134 | input tcu_clk_stop; | |
135 | ||
136 | input [7:0] sii_mb0_wdata; | |
137 | output [1:0] sii_mb0_ild_fail; | |
138 | ||
139 | //************************************************************************ | |
140 | // MBIST COMPARATOR SECTIONS | |
141 | //************************************************************************ | |
142 | ||
143 | sii_ild_dpinv_macro__width_2 inv_fail | |
144 | ( | |
145 | .din (cmp_err[1:0]), | |
146 | .dout(sii_mb0_ild_fail_l[1:0]) | |
147 | ); | |
148 | ||
149 | sii_ild_dpmsff_macro__stack_2c__width_2 ff_sii_mb0_ild_fail | |
150 | ( | |
151 | .scan_in(ff_sii_mb0_ild_fail_scanin), | |
152 | .scan_out(ff_sii_mb0_ild_fail_scanout), | |
153 | .din (sii_mb0_ild_fail_l[1:0]), | |
154 | .clk (l2clk), | |
155 | .dout (sii_mb0_ild_fail[1:0]), | |
156 | .en (1'b1), | |
157 | .se(se), | |
158 | .siclk(siclk), | |
159 | .soclk(soclk), | |
160 | .pce_ov(pce_ov), | |
161 | .stop(stop) | |
162 | ) ; | |
163 | ||
164 | sii_ild_dpmsff_macro__stack_8c__width_8 ff_sii_mb0_wdata_rrr | |
165 | ( | |
166 | .scan_in(ff_sii_mb0_wdata_rrr_scanin), | |
167 | .scan_out(ff_sii_mb0_wdata_rrr_scanout), | |
168 | .din (sii_mb0_wdata_rr[7:0]), | |
169 | .clk (l2clk), | |
170 | .dout (sii_mb0_wdata_rrr[7:0]), | |
171 | .en (1'b1), | |
172 | .se(se), | |
173 | .siclk(siclk), | |
174 | .soclk(soclk), | |
175 | .pce_ov(pce_ov), | |
176 | .stop(stop) | |
177 | ) ; | |
178 | ||
179 | sii_ild_dpmsff_macro__stack_8c__width_8 ff_sii_mb0_wdata_rr | |
180 | ( | |
181 | .scan_in(ff_sii_mb0_wdata_rr_scanin), | |
182 | .scan_out(ff_sii_mb0_wdata_rr_scanout), | |
183 | .din (sii_mb0_wdata_r[7:0]), | |
184 | .clk (l2clk), | |
185 | .dout (sii_mb0_wdata_rr[7:0]), | |
186 | .en (1'b1), | |
187 | .se(se), | |
188 | .siclk(siclk), | |
189 | .soclk(soclk), | |
190 | .pce_ov(pce_ov), | |
191 | .stop(stop) | |
192 | ) ; | |
193 | ||
194 | sii_ild_dpmsff_macro__stack_8c__width_8 ff_sii_mb0_wdata_r | |
195 | ( | |
196 | .scan_in(ff_sii_mb0_wdata_r_scanin), | |
197 | .scan_out(ff_sii_mb0_wdata_r_scanout), | |
198 | .din (sii_mb0_wdata[7:0]), | |
199 | .clk (l2clk), | |
200 | .dout (sii_mb0_wdata_r[7:0]), | |
201 | .en (1'b1), | |
202 | .se(se), | |
203 | .siclk(siclk), | |
204 | .soclk(soclk), | |
205 | .pce_ov(pce_ov), | |
206 | .stop(stop) | |
207 | ) ; | |
208 | ||
209 | assign mb_data[31:0] = {14'b0, sii_mb0_wdata_rrr[1:0], {2{sii_mb0_wdata_rrr[7:0]}}}; | |
210 | ||
211 | sii_ild_dpcmp_macro__dcmp_8x__width_32 cmp_81_64 ( | |
212 | .din0 ({14'b0, ildq_ild_dout[81:64]}), | |
213 | .din1 (mb_data[31:0]), | |
214 | .dout (cmp_err[1]) | |
215 | ); | |
216 | ||
217 | sii_ild_dpcmp_macro__dcmp_8x__width_64 cmp_63_0 ( | |
218 | .din0 (ildq_ild_dout[63:0]), | |
219 | .din1 ({8{sii_mb0_wdata_rrr[7:0]}}), | |
220 | .dout (cmp_err[0]) | |
221 | ); | |
222 | ||
223 | //************************************************************************ | |
224 | // SCAN CONNECTIONS | |
225 | //************************************************************************ | |
226 | assign se = tcu_scan_en; | |
227 | assign siclk = tcu_aclk; | |
228 | assign soclk = tcu_bclk; | |
229 | assign pce_ov = tcu_pce_ov; | |
230 | assign stop = tcu_clk_stop; | |
231 | assign ilc_ild_de_sel_cyc_unused = ilc_ild_de_sel_cyc[0]; | |
232 | ||
233 | //assign parity[3:0] = ildq_ild_dout[81:78]; | |
234 | assign ildq_ild_ecc[6:0] = ildq_ild_dout[70:64]; | |
235 | assign ildq_ild_ecc[13:7] = ildq_ild_dout[77:71]; | |
236 | assign ildq_ild_data[63:0] = ildq_ild_dout[63:0]; | |
237 | assign ild_ilc_curhdr[63:0] = ild_curhdr_ecc[63:0]; | |
238 | assign hdr_ecc[6:0] = {1'b0 , ild_curhdr_ecc[69:64]}; | |
239 | ||
240 | sii_ild_dpmsff_macro__stack_8c__width_8 ff_sii_l2b_ecc | |
241 | ( | |
242 | .scan_in(ff_sii_l2b_ecc_scanin), | |
243 | .scan_out(ff_sii_l2b_ecc_scanout), | |
244 | .din ({1'b0, sii_l2b_ecc_hdr[6:0]} ), | |
245 | .clk (l2clk), | |
246 | .dout ({sii_l2b_ecc_unused, sii_l2b_ecc[6:0]}), | |
247 | .en (1'b1), | |
248 | .se(se), | |
249 | .siclk(siclk), | |
250 | .soclk(soclk), | |
251 | .pce_ov(pce_ov), | |
252 | .stop(stop) | |
253 | ) ; | |
254 | ||
255 | sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8 mux_sii_l2b_ecc_hdr | |
256 | ( | |
257 | .dout ({sii_l2b_ecc_hdr_unused, sii_l2b_ecc_hdr[6:0]}) , | |
258 | .din0 ({1'b0, hdr_ecc[6:0]}), | |
259 | .din1 ({1'b0, sii_l2b_ecc_l[6:0]}), | |
260 | .sel0 (ilc_ild_cyc_sel[0]), | |
261 | .sel1 (ilc_ild_cyc_sel[1]) | |
262 | ||
263 | ); | |
264 | ||
265 | sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8 mux_sii_l2b_ecc | |
266 | ( | |
267 | .dout ({sii_l2b_ecc_l_unused, sii_l2b_ecc_l[6:0]}) , | |
268 | .din0 ({1'b0, ildq_ild_ecc[6:0]}), | |
269 | .din1 ({1'b0, ildq_ild_ecc[13:7]}), | |
270 | .sel0 (ilc_ild_de_sel[0]), | |
271 | .sel1 (ilc_ild_de_sel[1]) | |
272 | ); | |
273 | ||
274 | sii_ild_dpmsff_macro__dmsff_32x__stack_32c__width_32 ff_sii_l2t_req | |
275 | ( | |
276 | .scan_in(ff_sii_l2t_req_scanin), | |
277 | .scan_out(ff_sii_l2t_req_scanout), | |
278 | .din (sii_l2t_req_l[31:0]), | |
279 | .clk (l2clk), | |
280 | .dout (sii_l2t_req[31:0]), | |
281 | .en (1'b1), | |
282 | .se(se), | |
283 | .siclk(siclk), | |
284 | .soclk(soclk), | |
285 | .pce_ov(pce_ov), | |
286 | .stop(stop) | |
287 | ) ; | |
288 | ||
289 | ||
290 | //****************************************** | |
291 | // L2T REQ combine muxes | |
292 | //****************************************** | |
293 | sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_32l__width_32 mux_sii_l2t_req | |
294 | ( | |
295 | .dout (sii_l2t_req_l[31:0]), | |
296 | .din0 (ilc_ild_newhdr[31:0]), | |
297 | .din1 (ilc_ild_newhdr[63:32]), | |
298 | .din2 (ildq_ild_data[31:0]), | |
299 | .din3 (ildq_ild_data[63:32]), | |
300 | .sel0 (ilc_ild_hdr_sel[0]), | |
301 | .sel1 (ilc_ild_hdr_sel[1]), | |
302 | .sel2 (ilc_ild_de_sel_cyc[0]), | |
303 | .sel3 (ilc_ild_de_sel_cyc[1]) | |
304 | ); | |
305 | ||
306 | sii_ild_dpand_macro__left_0__ports_2__stack_4r__width_2 and_data_cyc_sel | |
307 | ( | |
308 | .din0 ({ilc_ild_de_sel[1], ilc_ild_de_sel[0]}), | |
309 | .din1 ({ilc_ild_cyc_sel[1], ilc_ild_cyc_sel[1]}), | |
310 | .dout ({ilc_ild_de_sel_cyc[1], ilc_ild_de_sel_cyc[0]} ) | |
311 | ); | |
312 | ||
313 | ||
314 | //****************************************** | |
315 | // HEADER section | |
316 | //****************************************** | |
317 | //mux_macro mux_ild_ilc_curhdr_h (width=36,ports=4,mux=aonpe,stack=36r,buffsel=none,dmux=8x) | |
318 | sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_36r__width_36 mux_ild_ilc_curhdr_h | |
319 | ( | |
320 | .dout (ild_curhdr_ecc[69:34]), | |
321 | .din0 (sii_l2t_hdr0[69:34]), | |
322 | .din1 (sii_l2t_hdr1[69:34]), | |
323 | .din2 (sii_l2t_hdr2[69:34]), | |
324 | .din3 (sii_l2t_hdr3[69:34]), | |
325 | .sel0 (ilc_ild_addr_h[0]), | |
326 | .sel1 (ilc_ild_addr_h[1]), | |
327 | .sel2 (ilc_ild_addr_h[2]), | |
328 | .sel3 (ilc_ild_addr_h[3]) | |
329 | ); | |
330 | ||
331 | //mux_macro mux_ild_ilc_curhdr_l (width=34,ports=4,mux=aonpe,stack=34l,buffsel=none,dmux=8x) | |
332 | sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_34l__width_34 mux_ild_ilc_curhdr_l | |
333 | ( | |
334 | .dout (ild_curhdr_ecc[33:0]), | |
335 | .din0 (sii_l2t_hdr0[33:0]), | |
336 | .din1 (sii_l2t_hdr1[33:0]), | |
337 | .din2 (sii_l2t_hdr2[33:0]), | |
338 | .din3 (sii_l2t_hdr3[33:0]), | |
339 | .sel0 (ilc_ild_addr_lo[0]), | |
340 | .sel1 (ilc_ild_addr_lo[1]), | |
341 | .sel2 (ilc_ild_addr_lo[2]), | |
342 | .sel3 (ilc_ild_addr_lo[3]) | |
343 | ); | |
344 | ||
345 | sii_ild_dpbuff_macro__dbuff_16x__stack_34c__width_34 buff_ipcc_data_out_h | |
346 | ( | |
347 | .dout (ipcc_data_out_buff[69:36]), | |
348 | .din (ipcc_data_out[69:36]) | |
349 | ); | |
350 | ||
351 | sii_ild_dpbuff_macro__dbuff_16x__stack_36c__width_36 buff_ipcc_data_out_l | |
352 | ( | |
353 | .dout (ipcc_data_out_buff[35:0]), | |
354 | .din (ipcc_data_out[35:0]) | |
355 | ); | |
356 | ||
357 | ||
358 | sii_ild_dpmsff_macro__stack_70c__width_70 ff_sii_l2t_hdr0 | |
359 | ( | |
360 | .scan_in(ff_sii_l2t_hdr0_scanin), | |
361 | .scan_out(ff_sii_l2t_hdr0_scanout), | |
362 | .din (ipcc_data_out_buff[69:0]), | |
363 | .clk (l2clk), | |
364 | .dout (sii_l2t_hdr0[69:0]), | |
365 | .en (ilc_ild_ldhdr[0]), | |
366 | .se(se), | |
367 | .siclk(siclk), | |
368 | .soclk(soclk), | |
369 | .pce_ov(pce_ov), | |
370 | .stop(stop) | |
371 | ) ; | |
372 | ||
373 | sii_ild_dpmsff_macro__stack_70c__width_70 ff_sii_l2t_hdr1 | |
374 | ( | |
375 | .scan_in(ff_sii_l2t_hdr1_scanin), | |
376 | .scan_out(ff_sii_l2t_hdr1_scanout), | |
377 | .din (ipcc_data_out_buff[69:0]), | |
378 | .clk (l2clk), | |
379 | .dout (sii_l2t_hdr1[69:0]), | |
380 | .en (ilc_ild_ldhdr[1]), | |
381 | .se(se), | |
382 | .siclk(siclk), | |
383 | .soclk(soclk), | |
384 | .pce_ov(pce_ov), | |
385 | .stop(stop) | |
386 | ); | |
387 | ||
388 | sii_ild_dpmsff_macro__stack_70c__width_70 ff_sii_l2t_hdr2 | |
389 | ( | |
390 | .scan_in(ff_sii_l2t_hdr2_scanin), | |
391 | .scan_out(ff_sii_l2t_hdr2_scanout), | |
392 | .din (ipcc_data_out_buff[69:0]), | |
393 | .clk (l2clk), | |
394 | .dout (sii_l2t_hdr2[69:0]), | |
395 | .en (ilc_ild_ldhdr[2]), | |
396 | .se(se), | |
397 | .siclk(siclk), | |
398 | .soclk(soclk), | |
399 | .pce_ov(pce_ov), | |
400 | .stop(stop) | |
401 | ); | |
402 | ||
403 | sii_ild_dpmsff_macro__stack_70c__width_70 ff_sii_l2t_hdr3 | |
404 | ( | |
405 | .scan_in(ff_sii_l2t_hdr3_scanin), | |
406 | .scan_out(ff_sii_l2t_hdr3_scanout), | |
407 | .din (ipcc_data_out_buff[69:0]), | |
408 | .clk (l2clk), | |
409 | .dout (sii_l2t_hdr3[69:0]), | |
410 | .en (ilc_ild_ldhdr[3]), | |
411 | .se(se), | |
412 | .siclk(siclk), | |
413 | .soclk(soclk), | |
414 | .pce_ov(pce_ov), | |
415 | .stop(stop) | |
416 | ); | |
417 | ||
418 | ||
419 | // fixscan start: | |
420 | assign ff_sii_mb0_ild_fail_scanin = scan_in ; | |
421 | assign ff_sii_mb0_wdata_rrr_scanin = ff_sii_mb0_ild_fail_scanout; | |
422 | assign ff_sii_mb0_wdata_rr_scanin = ff_sii_mb0_wdata_rrr_scanout; | |
423 | assign ff_sii_mb0_wdata_r_scanin = ff_sii_mb0_wdata_rr_scanout; | |
424 | assign ff_sii_l2b_ecc_scanin = ff_sii_mb0_wdata_r_scanout; | |
425 | assign ff_sii_l2t_req_scanin = ff_sii_l2b_ecc_scanout ; | |
426 | assign ff_sii_l2t_hdr0_scanin = ff_sii_l2t_req_scanout ; | |
427 | assign ff_sii_l2t_hdr1_scanin = ff_sii_l2t_hdr0_scanout ; | |
428 | assign ff_sii_l2t_hdr2_scanin = ff_sii_l2t_hdr1_scanout ; | |
429 | assign ff_sii_l2t_hdr3_scanin = ff_sii_l2t_hdr2_scanout ; | |
430 | assign scan_out = ff_sii_l2t_hdr3_scanout ; | |
431 | // fixscan end: | |
432 | endmodule | |
433 | ||
434 | ||
435 | // | |
436 | // invert macro | |
437 | // | |
438 | // | |
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | module sii_ild_dpinv_macro__width_2 ( | |
445 | din, | |
446 | dout); | |
447 | input [1:0] din; | |
448 | output [1:0] dout; | |
449 | ||
450 | ||
451 | ||
452 | ||
453 | ||
454 | ||
455 | inv #(2) d0_0 ( | |
456 | .in(din[1:0]), | |
457 | .out(dout[1:0]) | |
458 | ); | |
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | endmodule | |
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | // any PARAMS parms go into naming of macro | |
479 | ||
480 | module sii_ild_dpmsff_macro__stack_2c__width_2 ( | |
481 | din, | |
482 | clk, | |
483 | en, | |
484 | se, | |
485 | scan_in, | |
486 | siclk, | |
487 | soclk, | |
488 | pce_ov, | |
489 | stop, | |
490 | dout, | |
491 | scan_out); | |
492 | wire l1clk; | |
493 | wire siclk_out; | |
494 | wire soclk_out; | |
495 | wire [0:0] so; | |
496 | ||
497 | input [1:0] din; | |
498 | ||
499 | ||
500 | input clk; | |
501 | input en; | |
502 | input se; | |
503 | input scan_in; | |
504 | input siclk; | |
505 | input soclk; | |
506 | input pce_ov; | |
507 | input stop; | |
508 | ||
509 | ||
510 | ||
511 | output [1:0] dout; | |
512 | ||
513 | ||
514 | output scan_out; | |
515 | ||
516 | ||
517 | ||
518 | ||
519 | cl_dp1_l1hdr_8x c0_0 ( | |
520 | .l2clk(clk), | |
521 | .pce(en), | |
522 | .aclk(siclk), | |
523 | .bclk(soclk), | |
524 | .l1clk(l1clk), | |
525 | .se(se), | |
526 | .pce_ov(pce_ov), | |
527 | .stop(stop), | |
528 | .siclk_out(siclk_out), | |
529 | .soclk_out(soclk_out) | |
530 | ); | |
531 | dff #(2) d0_0 ( | |
532 | .l1clk(l1clk), | |
533 | .siclk(siclk_out), | |
534 | .soclk(soclk_out), | |
535 | .d(din[1:0]), | |
536 | .si({scan_in,so[0:0]}), | |
537 | .so({so[0:0],scan_out}), | |
538 | .q(dout[1:0]) | |
539 | ); | |
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | endmodule | |
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | // any PARAMS parms go into naming of macro | |
575 | ||
576 | module sii_ild_dpmsff_macro__stack_8c__width_8 ( | |
577 | din, | |
578 | clk, | |
579 | en, | |
580 | se, | |
581 | scan_in, | |
582 | siclk, | |
583 | soclk, | |
584 | pce_ov, | |
585 | stop, | |
586 | dout, | |
587 | scan_out); | |
588 | wire l1clk; | |
589 | wire siclk_out; | |
590 | wire soclk_out; | |
591 | wire [6:0] so; | |
592 | ||
593 | input [7:0] din; | |
594 | ||
595 | ||
596 | input clk; | |
597 | input en; | |
598 | input se; | |
599 | input scan_in; | |
600 | input siclk; | |
601 | input soclk; | |
602 | input pce_ov; | |
603 | input stop; | |
604 | ||
605 | ||
606 | ||
607 | output [7:0] dout; | |
608 | ||
609 | ||
610 | output scan_out; | |
611 | ||
612 | ||
613 | ||
614 | ||
615 | cl_dp1_l1hdr_8x c0_0 ( | |
616 | .l2clk(clk), | |
617 | .pce(en), | |
618 | .aclk(siclk), | |
619 | .bclk(soclk), | |
620 | .l1clk(l1clk), | |
621 | .se(se), | |
622 | .pce_ov(pce_ov), | |
623 | .stop(stop), | |
624 | .siclk_out(siclk_out), | |
625 | .soclk_out(soclk_out) | |
626 | ); | |
627 | dff #(8) d0_0 ( | |
628 | .l1clk(l1clk), | |
629 | .siclk(siclk_out), | |
630 | .soclk(soclk_out), | |
631 | .d(din[7:0]), | |
632 | .si({scan_in,so[6:0]}), | |
633 | .so({so[6:0],scan_out}), | |
634 | .q(dout[7:0]) | |
635 | ); | |
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | endmodule | |
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | // | |
667 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
668 | // | |
669 | // | |
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | module sii_ild_dpcmp_macro__dcmp_8x__width_32 ( | |
676 | din0, | |
677 | din1, | |
678 | dout); | |
679 | input [31:0] din0; | |
680 | input [31:0] din1; | |
681 | output dout; | |
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | cmp #(32) m0_0 ( | |
689 | .in0(din0[31:0]), | |
690 | .in1(din1[31:0]), | |
691 | .out(dout) | |
692 | ); | |
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | ||
699 | ||
700 | ||
701 | ||
702 | ||
703 | endmodule | |
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | // | |
710 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
711 | // | |
712 | // | |
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | module sii_ild_dpcmp_macro__dcmp_8x__width_64 ( | |
719 | din0, | |
720 | din1, | |
721 | dout); | |
722 | input [63:0] din0; | |
723 | input [63:0] din1; | |
724 | output dout; | |
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | cmp #(64) m0_0 ( | |
732 | .in0(din0[63:0]), | |
733 | .in1(din1[63:0]), | |
734 | .out(dout) | |
735 | ); | |
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | endmodule | |
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
753 | // also for pass-gate with decoder | |
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | // any PARAMS parms go into naming of macro | |
760 | ||
761 | module sii_ild_dpmux_macro__mux_aonpe__ports_2__stack_32r__width_8 ( | |
762 | din0, | |
763 | sel0, | |
764 | din1, | |
765 | sel1, | |
766 | dout); | |
767 | wire buffout0; | |
768 | wire buffout1; | |
769 | ||
770 | input [7:0] din0; | |
771 | input sel0; | |
772 | input [7:0] din1; | |
773 | input sel1; | |
774 | output [7:0] dout; | |
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | cl_dp1_muxbuff2_8x c0_0 ( | |
781 | .in0(sel0), | |
782 | .in1(sel1), | |
783 | .out0(buffout0), | |
784 | .out1(buffout1) | |
785 | ); | |
786 | mux2s #(8) d0_0 ( | |
787 | .sel0(buffout0), | |
788 | .sel1(buffout1), | |
789 | .in0(din0[7:0]), | |
790 | .in1(din1[7:0]), | |
791 | .dout(dout[7:0]) | |
792 | ); | |
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | ||
799 | ||
800 | ||
801 | ||
802 | ||
803 | ||
804 | ||
805 | ||
806 | endmodule | |
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | // any PARAMS parms go into naming of macro | |
814 | ||
815 | module sii_ild_dpmsff_macro__dmsff_32x__stack_32c__width_32 ( | |
816 | din, | |
817 | clk, | |
818 | en, | |
819 | se, | |
820 | scan_in, | |
821 | siclk, | |
822 | soclk, | |
823 | pce_ov, | |
824 | stop, | |
825 | dout, | |
826 | scan_out); | |
827 | wire l1clk; | |
828 | wire siclk_out; | |
829 | wire soclk_out; | |
830 | wire [30:0] so; | |
831 | ||
832 | input [31:0] din; | |
833 | ||
834 | ||
835 | input clk; | |
836 | input en; | |
837 | input se; | |
838 | input scan_in; | |
839 | input siclk; | |
840 | input soclk; | |
841 | input pce_ov; | |
842 | input stop; | |
843 | ||
844 | ||
845 | ||
846 | output [31:0] dout; | |
847 | ||
848 | ||
849 | output scan_out; | |
850 | ||
851 | ||
852 | ||
853 | ||
854 | cl_dp1_l1hdr_8x c0_0 ( | |
855 | .l2clk(clk), | |
856 | .pce(en), | |
857 | .aclk(siclk), | |
858 | .bclk(soclk), | |
859 | .l1clk(l1clk), | |
860 | .se(se), | |
861 | .pce_ov(pce_ov), | |
862 | .stop(stop), | |
863 | .siclk_out(siclk_out), | |
864 | .soclk_out(soclk_out) | |
865 | ); | |
866 | dff #(32) d0_0 ( | |
867 | .l1clk(l1clk), | |
868 | .siclk(siclk_out), | |
869 | .soclk(soclk_out), | |
870 | .d(din[31:0]), | |
871 | .si({scan_in,so[30:0]}), | |
872 | .so({so[30:0],scan_out}), | |
873 | .q(dout[31:0]) | |
874 | ); | |
875 | ||
876 | ||
877 | ||
878 | ||
879 | ||
880 | ||
881 | ||
882 | ||
883 | ||
884 | ||
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | endmodule | |
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
906 | // also for pass-gate with decoder | |
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | // any PARAMS parms go into naming of macro | |
913 | ||
914 | module sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_32l__width_32 ( | |
915 | din0, | |
916 | sel0, | |
917 | din1, | |
918 | sel1, | |
919 | din2, | |
920 | sel2, | |
921 | din3, | |
922 | sel3, | |
923 | dout); | |
924 | wire buffout0; | |
925 | wire buffout1; | |
926 | wire buffout2; | |
927 | wire buffout3; | |
928 | ||
929 | input [31:0] din0; | |
930 | input sel0; | |
931 | input [31:0] din1; | |
932 | input sel1; | |
933 | input [31:0] din2; | |
934 | input sel2; | |
935 | input [31:0] din3; | |
936 | input sel3; | |
937 | output [31:0] dout; | |
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | cl_dp1_muxbuff4_8x c0_0 ( | |
944 | .in0(sel0), | |
945 | .in1(sel1), | |
946 | .in2(sel2), | |
947 | .in3(sel3), | |
948 | .out0(buffout0), | |
949 | .out1(buffout1), | |
950 | .out2(buffout2), | |
951 | .out3(buffout3) | |
952 | ); | |
953 | mux4s #(32) d0_0 ( | |
954 | .sel0(buffout0), | |
955 | .sel1(buffout1), | |
956 | .sel2(buffout2), | |
957 | .sel3(buffout3), | |
958 | .in0(din0[31:0]), | |
959 | .in1(din1[31:0]), | |
960 | .in2(din2[31:0]), | |
961 | .in3(din3[31:0]), | |
962 | .dout(dout[31:0]) | |
963 | ); | |
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | ||
973 | ||
974 | ||
975 | ||
976 | ||
977 | endmodule | |
978 | ||
979 | ||
980 | // | |
981 | // and macro for ports = 2,3,4 | |
982 | // | |
983 | // | |
984 | ||
985 | ||
986 | ||
987 | ||
988 | ||
989 | module sii_ild_dpand_macro__left_0__ports_2__stack_4r__width_2 ( | |
990 | din0, | |
991 | din1, | |
992 | dout); | |
993 | input [1:0] din0; | |
994 | input [1:0] din1; | |
995 | output [1:0] dout; | |
996 | ||
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | and2 #(2) d0_0 ( | |
1003 | .in0(din0[1:0]), | |
1004 | .in1(din1[1:0]), | |
1005 | .out(dout[1:0]) | |
1006 | ); | |
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | endmodule | |
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1023 | // also for pass-gate with decoder | |
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | // any PARAMS parms go into naming of macro | |
1030 | ||
1031 | module sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_36r__width_36 ( | |
1032 | din0, | |
1033 | sel0, | |
1034 | din1, | |
1035 | sel1, | |
1036 | din2, | |
1037 | sel2, | |
1038 | din3, | |
1039 | sel3, | |
1040 | dout); | |
1041 | wire buffout0; | |
1042 | wire buffout1; | |
1043 | wire buffout2; | |
1044 | wire buffout3; | |
1045 | ||
1046 | input [35:0] din0; | |
1047 | input sel0; | |
1048 | input [35:0] din1; | |
1049 | input sel1; | |
1050 | input [35:0] din2; | |
1051 | input sel2; | |
1052 | input [35:0] din3; | |
1053 | input sel3; | |
1054 | output [35:0] dout; | |
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | cl_dp1_muxbuff4_8x c0_0 ( | |
1061 | .in0(sel0), | |
1062 | .in1(sel1), | |
1063 | .in2(sel2), | |
1064 | .in3(sel3), | |
1065 | .out0(buffout0), | |
1066 | .out1(buffout1), | |
1067 | .out2(buffout2), | |
1068 | .out3(buffout3) | |
1069 | ); | |
1070 | mux4s #(36) d0_0 ( | |
1071 | .sel0(buffout0), | |
1072 | .sel1(buffout1), | |
1073 | .sel2(buffout2), | |
1074 | .sel3(buffout3), | |
1075 | .in0(din0[35:0]), | |
1076 | .in1(din1[35:0]), | |
1077 | .in2(din2[35:0]), | |
1078 | .in3(din3[35:0]), | |
1079 | .dout(dout[35:0]) | |
1080 | ); | |
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | endmodule | |
1095 | ||
1096 | ||
1097 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1098 | // also for pass-gate with decoder | |
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | // any PARAMS parms go into naming of macro | |
1105 | ||
1106 | module sii_ild_dpmux_macro__dmux_8x__mux_aonpe__ports_4__stack_34l__width_34 ( | |
1107 | din0, | |
1108 | sel0, | |
1109 | din1, | |
1110 | sel1, | |
1111 | din2, | |
1112 | sel2, | |
1113 | din3, | |
1114 | sel3, | |
1115 | dout); | |
1116 | wire buffout0; | |
1117 | wire buffout1; | |
1118 | wire buffout2; | |
1119 | wire buffout3; | |
1120 | ||
1121 | input [33:0] din0; | |
1122 | input sel0; | |
1123 | input [33:0] din1; | |
1124 | input sel1; | |
1125 | input [33:0] din2; | |
1126 | input sel2; | |
1127 | input [33:0] din3; | |
1128 | input sel3; | |
1129 | output [33:0] dout; | |
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | cl_dp1_muxbuff4_8x c0_0 ( | |
1136 | .in0(sel0), | |
1137 | .in1(sel1), | |
1138 | .in2(sel2), | |
1139 | .in3(sel3), | |
1140 | .out0(buffout0), | |
1141 | .out1(buffout1), | |
1142 | .out2(buffout2), | |
1143 | .out3(buffout3) | |
1144 | ); | |
1145 | mux4s #(34) d0_0 ( | |
1146 | .sel0(buffout0), | |
1147 | .sel1(buffout1), | |
1148 | .sel2(buffout2), | |
1149 | .sel3(buffout3), | |
1150 | .in0(din0[33:0]), | |
1151 | .in1(din1[33:0]), | |
1152 | .in2(din2[33:0]), | |
1153 | .in3(din3[33:0]), | |
1154 | .dout(dout[33:0]) | |
1155 | ); | |
1156 | ||
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | endmodule | |
1170 | ||
1171 | ||
1172 | // | |
1173 | // buff macro | |
1174 | // | |
1175 | // | |
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | ||
1181 | module sii_ild_dpbuff_macro__dbuff_16x__stack_34c__width_34 ( | |
1182 | din, | |
1183 | dout); | |
1184 | input [33:0] din; | |
1185 | output [33:0] dout; | |
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | buff #(34) d0_0 ( | |
1193 | .in(din[33:0]), | |
1194 | .out(dout[33:0]) | |
1195 | ); | |
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | endmodule | |
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | ||
1210 | // | |
1211 | // buff macro | |
1212 | // | |
1213 | // | |
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | module sii_ild_dpbuff_macro__dbuff_16x__stack_36c__width_36 ( | |
1220 | din, | |
1221 | dout); | |
1222 | input [35:0] din; | |
1223 | output [35:0] dout; | |
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | buff #(36) d0_0 ( | |
1231 | .in(din[35:0]), | |
1232 | .out(dout[35:0]) | |
1233 | ); | |
1234 | ||
1235 | ||
1236 | ||
1237 | ||
1238 | ||
1239 | ||
1240 | ||
1241 | ||
1242 | endmodule | |
1243 | ||
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | ||
1252 | // any PARAMS parms go into naming of macro | |
1253 | ||
1254 | module sii_ild_dpmsff_macro__stack_70c__width_70 ( | |
1255 | din, | |
1256 | clk, | |
1257 | en, | |
1258 | se, | |
1259 | scan_in, | |
1260 | siclk, | |
1261 | soclk, | |
1262 | pce_ov, | |
1263 | stop, | |
1264 | dout, | |
1265 | scan_out); | |
1266 | wire l1clk; | |
1267 | wire siclk_out; | |
1268 | wire soclk_out; | |
1269 | wire [68:0] so; | |
1270 | ||
1271 | input [69:0] din; | |
1272 | ||
1273 | ||
1274 | input clk; | |
1275 | input en; | |
1276 | input se; | |
1277 | input scan_in; | |
1278 | input siclk; | |
1279 | input soclk; | |
1280 | input pce_ov; | |
1281 | input stop; | |
1282 | ||
1283 | ||
1284 | ||
1285 | output [69:0] dout; | |
1286 | ||
1287 | ||
1288 | output scan_out; | |
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | cl_dp1_l1hdr_8x c0_0 ( | |
1294 | .l2clk(clk), | |
1295 | .pce(en), | |
1296 | .aclk(siclk), | |
1297 | .bclk(soclk), | |
1298 | .l1clk(l1clk), | |
1299 | .se(se), | |
1300 | .pce_ov(pce_ov), | |
1301 | .stop(stop), | |
1302 | .siclk_out(siclk_out), | |
1303 | .soclk_out(soclk_out) | |
1304 | ); | |
1305 | dff #(70) d0_0 ( | |
1306 | .l1clk(l1clk), | |
1307 | .siclk(siclk_out), | |
1308 | .soclk(soclk_out), | |
1309 | .d(din[69:0]), | |
1310 | .si({scan_in,so[68:0]}), | |
1311 | .so({so[68:0],scan_out}), | |
1312 | .q(dout[69:0]) | |
1313 | ); | |
1314 | ||
1315 | ||
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | endmodule | |
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 |