Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sii_ipcc_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sii_ipcc_dp ( | |
36 | ipcc_data_all0, | |
37 | ipcc_data_all1, | |
38 | ipcc_data_all2, | |
39 | ipcc_data_all3, | |
40 | sii_mb1_read_data, | |
41 | ipcc_dp_par_data, | |
42 | curhdr, | |
43 | data_sel, | |
44 | gnt0_r_m, | |
45 | hdr_data_sel, | |
46 | new_c, | |
47 | data_parity_err, | |
48 | newhdr_l2, | |
49 | newhdr_nc, | |
50 | ipdohq0_dout, | |
51 | ipdbhq0_dout, | |
52 | ipdohq1_dout, | |
53 | ipdbhq1_dout, | |
54 | ipdodq0_dout, | |
55 | ipdbdq0_dout, | |
56 | ipdodq1_dout, | |
57 | ipdbdq1_dout, | |
58 | tcu_hdr, | |
59 | tcu_data, | |
60 | tcu_be_par, | |
61 | scan_in, | |
62 | scan_out, | |
63 | l2clk, | |
64 | tcu_muxtest, | |
65 | tcu_dectest, | |
66 | tcu_scan_en, | |
67 | tcu_aclk, | |
68 | tcu_bclk, | |
69 | tcu_pce_ov, | |
70 | tcu_clk_stop, | |
71 | sii_mb0_wdata, | |
72 | sii_mb0_run); | |
73 | wire se; | |
74 | wire siclk; | |
75 | wire soclk; | |
76 | wire pce_ov; | |
77 | wire stop; | |
78 | wire muxtst; | |
79 | wire test; | |
80 | wire [81:0] mbist0_wdata; | |
81 | wire [7:0] sii_mb0_wdata_r; | |
82 | wire [81:0] ipcc_data_func; | |
83 | wire [13:0] newbe_par_rr; | |
84 | wire [13:0] ipcc_ecc_r; | |
85 | wire [71:0] ipcc_data_out_r; | |
86 | wire [83:0] ipcc_data_out_m; | |
87 | wire [16:0] new_be_r; | |
88 | wire [13:0] newbe_par_r; | |
89 | wire [63:0] newdata_r; | |
90 | wire [1:0] ipcc_data_out_m_unused; | |
91 | wire [89:0] ipcc_data_all; | |
92 | wire ff_ipcc_data_out_scanin; | |
93 | wire ff_ipcc_data_out_scanout; | |
94 | wire [71:0] ipcc_data_out; | |
95 | wire not_hdr_data_sel; | |
96 | wire hdr_not_curhdr_58; | |
97 | wire hdr_curhdr_58; | |
98 | wire not_curhdr_58; | |
99 | wire [71:0] curhdr_i; | |
100 | wire [71:0] curhdr_l_buf; | |
101 | wire ff_curhdri_scanin; | |
102 | wire ff_curhdri_scanout; | |
103 | wire [71:0] curhdr_l; | |
104 | wire [4:0] gnt_pri; | |
105 | wire [3:0] not_gnt0_r_m; | |
106 | wire not_gnt0_2; | |
107 | wire ff_newdata_scanin; | |
108 | wire ff_newdata_scanout; | |
109 | wire [63:0] newdata; | |
110 | wire [63:0] newdata_tmp; | |
111 | wire [13:0] be_par7; | |
112 | wire [13:0] be_par6; | |
113 | wire [13:0] be_par5; | |
114 | wire [13:0] be_par4; | |
115 | wire [13:0] be_par3; | |
116 | wire [13:0] be_par2; | |
117 | wire [13:0] be_par1; | |
118 | wire [13:0] be_par0; | |
119 | wire ff_newbe_par_scanin; | |
120 | wire ff_newbe_par_scanout; | |
121 | wire [13:0] newbe_par; | |
122 | wire ff_newbe_par_rr_scanin; | |
123 | wire ff_newbe_par_rr_scanout; | |
124 | wire ff_mb0_wdata_scanin; | |
125 | wire ff_mb0_wdata_scanout; | |
126 | wire [7:0] sii_mb0_wdata_buf; | |
127 | wire [13:0] ipcc_ecc; | |
128 | wire [13:0] new_ecc; | |
129 | wire [6:0] ecch; | |
130 | wire [3:0] xor_ecc_h_l; | |
131 | wire [6:0] eccl; | |
132 | wire [31:0] eccd_h; | |
133 | wire [31:0] eccd_l; | |
134 | wire [8:0] eccd_h_0_l; | |
135 | wire [8:0] eccd_h_0_r; | |
136 | wire [8:0] eccd_h_0_l1; | |
137 | wire [3:0] eccd_h_0_l2; | |
138 | wire [1:0] eccd_h_0_l3; | |
139 | wire [8:0] eccd_h_1_l; | |
140 | wire [8:0] eccd_h_1_r; | |
141 | wire [8:0] eccd_h_1_l1; | |
142 | wire [3:0] eccd_h_1_l2; | |
143 | wire [1:0] eccd_h_1_l3; | |
144 | wire [8:0] eccd_h_2_l; | |
145 | wire [8:0] eccd_h_2_r; | |
146 | wire [8:0] eccd_h_2_l1; | |
147 | wire [3:0] eccd_h_2_l2; | |
148 | wire [1:0] eccd_h_2_l3; | |
149 | wire [6:0] eccd_h_3_l; | |
150 | wire [6:0] eccd_h_3_r; | |
151 | wire [6:0] eccd_h_3_l1; | |
152 | wire [3:0] eccd_h_3_l2; | |
153 | wire [1:0] eccd_h_3_l3; | |
154 | wire [6:0] eccd_h_4_l; | |
155 | wire [6:0] eccd_h_4_r; | |
156 | wire [6:0] eccd_h_4_l1; | |
157 | wire [3:0] eccd_h_4_l2; | |
158 | wire [1:0] eccd_h_4_l3; | |
159 | wire [2:0] eccd_h_5_l1; | |
160 | wire [8:0] eccd_h_6_l; | |
161 | wire [8:0] eccd_h_6_r; | |
162 | wire [8:0] eccd_h_6_l1; | |
163 | wire [3:0] eccd_h_6_l2; | |
164 | wire [1:0] eccd_h_6_l3; | |
165 | wire [8:0] eccd_l_0_l; | |
166 | wire [8:0] eccd_l_0_r; | |
167 | wire [8:0] eccd_l_0_l1; | |
168 | wire [3:0] eccd_l_0_l2; | |
169 | wire [1:0] eccd_l_0_l3; | |
170 | wire [8:0] eccd_l_1_l; | |
171 | wire [8:0] eccd_l_1_r; | |
172 | wire [8:0] eccd_l_1_l1; | |
173 | wire [3:0] eccd_l_1_l2; | |
174 | wire [1:0] eccd_l_1_l3; | |
175 | wire [8:0] eccd_l_2_l; | |
176 | wire [8:0] eccd_l_2_r; | |
177 | wire [8:0] eccd_l_2_l1; | |
178 | wire [3:0] eccd_l_2_l2; | |
179 | wire [1:0] eccd_l_2_l3; | |
180 | wire [6:0] eccd_l_3_l; | |
181 | wire [6:0] eccd_l_3_r; | |
182 | wire [6:0] eccd_l_3_l1; | |
183 | wire [3:0] eccd_l_3_l2; | |
184 | wire [1:0] eccd_l_3_l3; | |
185 | wire [6:0] eccd_l_4_l; | |
186 | wire [6:0] eccd_l_4_r; | |
187 | wire [6:0] eccd_l_4_l1; | |
188 | wire [3:0] eccd_l_4_l2; | |
189 | wire [1:0] eccd_l_4_l3; | |
190 | wire [2:0] eccd_l_5_l1; | |
191 | wire [8:0] eccd_l_6_l; | |
192 | wire [8:0] eccd_l_6_r; | |
193 | wire [8:0] eccd_l_6_l1; | |
194 | wire [3:0] eccd_l_6_l2; | |
195 | wire [1:0] eccd_l_6_l3; | |
196 | wire [13:0] newbe_par1; | |
197 | wire ff_newbe_scanin; | |
198 | wire ff_newbe_scanout; | |
199 | wire [17:0] new_be; | |
200 | wire new_be_unused; | |
201 | wire ff_ipcc_ecc_scanin; | |
202 | wire ff_ipcc_ecc_scanout; | |
203 | ||
204 | ||
205 | output [89:0] ipcc_data_all0; | |
206 | output [89:0] ipcc_data_all1; | |
207 | output [89:0] ipcc_data_all2; | |
208 | output [89:0] ipcc_data_all3; | |
209 | output [77:0] sii_mb1_read_data; | |
210 | output [84:0] ipcc_dp_par_data; | |
211 | output [71:0] curhdr; | |
212 | ||
213 | //------inter-submodule signals------- | |
214 | ||
215 | input [2:0] data_sel; | |
216 | input [4:0] gnt0_r_m; | |
217 | input hdr_data_sel; | |
218 | input [5:0] new_c; | |
219 | input data_parity_err; | |
220 | ||
221 | //-------from data path ----------- | |
222 | input [63:0] newhdr_l2; // header for l2 | |
223 | input [63:0] newhdr_nc; // header for ncu | |
224 | input [71:0] ipdohq0_dout; | |
225 | input [71:0] ipdbhq0_dout; | |
226 | input [71:0] ipdohq1_dout; | |
227 | input [71:0] ipdbhq1_dout; | |
228 | input [152:0] ipdodq0_dout; | |
229 | input [152:0] ipdbdq0_dout; | |
230 | input [152:0] ipdodq1_dout; | |
231 | input [152:0] ipdbdq1_dout; | |
232 | input [71:0] tcu_hdr; | |
233 | input [63:0] tcu_data; | |
234 | input [11:0] tcu_be_par; | |
235 | ||
236 | ||
237 | input scan_in; | |
238 | output scan_out; | |
239 | ||
240 | input l2clk; | |
241 | input tcu_muxtest; | |
242 | input tcu_dectest; | |
243 | input tcu_scan_en; | |
244 | input tcu_aclk; | |
245 | input tcu_bclk; | |
246 | input tcu_pce_ov; | |
247 | input tcu_clk_stop; | |
248 | input [7:0] sii_mb0_wdata; | |
249 | input sii_mb0_run; | |
250 | ||
251 | //************************************************************************ | |
252 | // SCAN CONNECTIONS | |
253 | //************************************************************************ | |
254 | assign se = tcu_scan_en; | |
255 | assign siclk = tcu_aclk; | |
256 | assign soclk = tcu_bclk; | |
257 | assign pce_ov = tcu_pce_ov; | |
258 | assign stop = tcu_clk_stop; | |
259 | assign muxtst = tcu_muxtest; | |
260 | assign test = tcu_dectest; | |
261 | ||
262 | //************************************************************************ | |
263 | // MBIST SECTION | |
264 | //************************************************************************ | |
265 | ||
266 | assign mbist0_wdata[81:0] = {sii_mb0_wdata_r[1:0],sii_mb0_wdata_r[7:0], | |
267 | sii_mb0_wdata_r[7:0],sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0], | |
268 | sii_mb0_wdata_r[7:0],sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0], | |
269 | sii_mb0_wdata_r[7:0],sii_mb0_wdata_r[7:0], sii_mb0_wdata_r[7:0]}; | |
270 | ||
271 | assign ipcc_data_func[81:0] = {newbe_par_rr[3:0], ipcc_ecc_r[13:0], ipcc_data_out_r[63:0]}; | |
272 | ||
273 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64 mux_ipcc_data_63_0 | |
274 | ( | |
275 | .dout(ipcc_data_out_m[63:0]), | |
276 | .din0(mbist0_wdata[63:0]), | |
277 | .din1(ipcc_data_func[63:0]), | |
278 | .sel0(sii_mb0_run) | |
279 | ); | |
280 | ||
281 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_20c__width_20 mux_ipcc_data_81_64 | |
282 | ( | |
283 | .dout(ipcc_data_out_m[83:64]), | |
284 | .din0({2'b00, mbist0_wdata[81:64]}), | |
285 | .din1({2'b00,ipcc_data_func[81:64]}), | |
286 | .sel0(sii_mb0_run) | |
287 | ); | |
288 | ||
289 | assign sii_mb1_read_data[77:0] = {newbe_par_rr[13:0],ipcc_data_out_r[63:0]}; | |
290 | assign ipcc_dp_par_data[84:0] = {new_be_r[16:0], newbe_par_r[3:0], newdata_r[63:0]}; | |
291 | assign ipcc_data_out_m_unused[1:0] = ipcc_data_out_m[83:82]; | |
292 | ||
293 | //************************************************************************ | |
294 | // MUXES SECTION | |
295 | //************************************************************************ | |
296 | assign ipcc_data_all[89:0] = {newbe_par_rr[11:4], ipcc_data_out_m[81:0]}; | |
297 | ||
298 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46 buff_ipcc_data_all0_45_0 | |
299 | ( | |
300 | .dout (ipcc_data_all0[45:0]), | |
301 | .din (ipcc_data_all[45:0]) | |
302 | ); | |
303 | ||
304 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44 buff_ipcc_data_all0_89_46 | |
305 | ( | |
306 | .dout (ipcc_data_all0[89:46]), | |
307 | .din (ipcc_data_all[89:46]) | |
308 | ); | |
309 | ||
310 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46 buff_ipcc_data_all1_45_0 | |
311 | ( | |
312 | .dout (ipcc_data_all1[45:0]), | |
313 | .din (ipcc_data_all[45:0]) | |
314 | ); | |
315 | ||
316 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44 buff_ipcc_data_all1_89_46 | |
317 | ( | |
318 | .dout (ipcc_data_all1[89:46]), | |
319 | .din (ipcc_data_all[89:46]) | |
320 | ); | |
321 | ||
322 | ||
323 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46 buff_ipcc_data_all2_45_0 | |
324 | ( | |
325 | .dout (ipcc_data_all2[45:0]), | |
326 | .din (ipcc_data_all[45:0]) | |
327 | ); | |
328 | ||
329 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44 buff_ipcc_data_all2_89_46 | |
330 | ( | |
331 | .dout (ipcc_data_all2[89:46]), | |
332 | .din (ipcc_data_all[89:46]) | |
333 | ); | |
334 | ||
335 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46 buff_ipcc_data_all3_45_0 | |
336 | ( | |
337 | .dout (ipcc_data_all3[45:0]), | |
338 | .din (ipcc_data_all[45:0]) | |
339 | ); | |
340 | ||
341 | sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44 buff_ipcc_data_all3_89_46 | |
342 | ( | |
343 | .dout (ipcc_data_all3[89:46]), | |
344 | .din (ipcc_data_all[89:46]) | |
345 | ); | |
346 | ||
347 | ||
348 | sii_ipcc_dpmsff_macro__stack_72c__width_72 ff_ipcc_data_out | |
349 | ( | |
350 | .scan_in(ff_ipcc_data_out_scanin), | |
351 | .scan_out(ff_ipcc_data_out_scanout), | |
352 | .din (ipcc_data_out[71:0]), | |
353 | .clk (l2clk), | |
354 | .en (1'b1), | |
355 | .dout (ipcc_data_out_r[71:0]), | |
356 | .se(se), | |
357 | .siclk(siclk), | |
358 | .soclk(soclk), | |
359 | .pce_ov(pce_ov), | |
360 | .stop(stop) | |
361 | ) ; | |
362 | // | |
363 | //In order to combine the mux_ipcc_data_out and mux_newhdr, it need | |
364 | // to be split to 2 muxes because of the width are different. | |
365 | ||
366 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_8c__width_8 mux_ipcc_data_out_71_64 | |
367 | ( | |
368 | .dout (ipcc_data_out[71:64]) , | |
369 | .din1 (newbe_par_r[7:0]), | |
370 | .din0 (curhdr[71:64]), | |
371 | .sel0 (hdr_data_sel) | |
372 | ) ; | |
373 | ||
374 | sii_ipcc_dpmux_macro__mux_pgnpe__ports_3__stack_64c__width_64 mux_ipcc_data_out_63_0 | |
375 | ( | |
376 | .dout (ipcc_data_out[63:0]) , | |
377 | .din2 (newdata_r[63:0]), | |
378 | .din1 (newhdr_nc[63:0]), | |
379 | .din0 (newhdr_l2[63:0]), | |
380 | .sel2 (not_hdr_data_sel), | |
381 | .sel1 (hdr_not_curhdr_58), | |
382 | .sel0 (hdr_curhdr_58), | |
383 | .muxtst(muxtst) | |
384 | ) ; | |
385 | ||
386 | //inv_macro inv_curhdr_58 (width = 1, stack=1r) | |
387 | // ( | |
388 | // .din (curhdr[58]), | |
389 | // .dout (not_curhdr_58) | |
390 | // ); | |
391 | ||
392 | sii_ipcc_dpinv_macro__stack_2r__width_2 inv_hdr_data_sel_curhdr58 | |
393 | ( | |
394 | .din ({hdr_data_sel, curhdr[58]}), | |
395 | .dout ({not_hdr_data_sel,not_curhdr_58}) | |
396 | ); | |
397 | ||
398 | ||
399 | sii_ipcc_dpand_macro__left_0__ports_2__stack_2r__width_2 and_hdr_sel | |
400 | ( | |
401 | .din0 ({hdr_data_sel, hdr_data_sel}), | |
402 | .din1 ({curhdr[58], not_curhdr_58}), | |
403 | .dout ({hdr_curhdr_58, hdr_not_curhdr_58} ) | |
404 | ); | |
405 | ||
406 | ||
407 | //mux_macro mux_ipcc_data_out (width=72, ports=2, mux=pgpe, stack=72c) | |
408 | // ( | |
409 | // .dout (ipcc_data_out[71:0]) , | |
410 | // .din1 ({newbe_par_r[7:0], newdata_r[63:0]}), | |
411 | // .din0 ({curhdr[71:64], newhdr[63:0]}), | |
412 | // .sel0 (hdr_data_sel) | |
413 | // ) ; | |
414 | ||
415 | //mux_macro mux_newhdr (width=64, ports=2, mux=pgpe, stack=64c) | |
416 | // ( | |
417 | // .dout (newhdr[63:0]) , | |
418 | // .din1 (newhdr_nc[63:0]), | |
419 | // .din0 (newhdr_l2[63:0]), | |
420 | // .sel0 (curhdr[58]) | |
421 | // ) ; | |
422 | ||
423 | sii_ipcc_dpinv_macro__stack_72r__width_72 inv_curhdr | |
424 | ( | |
425 | .din (curhdr_i[71:0]), | |
426 | .dout (curhdr[71:0]) | |
427 | ); | |
428 | ||
429 | sii_ipcc_dpmsffi_macro__stack_72c__width_72 ff_curhdri | |
430 | ( | |
431 | .din (curhdr_l_buf[71:0]), | |
432 | .scan_in(ff_curhdri_scanin), | |
433 | .scan_out(ff_curhdri_scanout), | |
434 | .clk (l2clk), | |
435 | .en (1'b1), | |
436 | .dout_l (curhdr_i[71:0]), | |
437 | .se(se), | |
438 | .siclk(siclk), | |
439 | .soclk(soclk), | |
440 | .pce_ov(pce_ov), | |
441 | .stop(stop) | |
442 | ) ; | |
443 | ||
444 | sii_ipcc_dpbuff_macro__minbuff_1__width_8 buf_curhdr_72_64 | |
445 | ( | |
446 | .din (curhdr_l[71:64]), | |
447 | .dout (curhdr_l_buf[71:64]) | |
448 | ); | |
449 | ||
450 | sii_ipcc_dpbuff_macro__minbuff_1__width_64 buf_curhdr_63_0 | |
451 | ( | |
452 | .din (curhdr_l[63:0]), | |
453 | .dout (curhdr_l_buf[63:0]) | |
454 | ); | |
455 | ||
456 | // Put priority encoder before pass gate mux for dft purpose | |
457 | assign gnt_pri[0] = gnt0_r_m[0]; | |
458 | sii_ipcc_dpinv_macro__left_0__stack_4r__width_4 inv_gnt0_r_m | |
459 | ( | |
460 | .din (gnt0_r_m[3:0]), | |
461 | .dout (not_gnt0_r_m[3:0]) | |
462 | ); | |
463 | ||
464 | sii_ipcc_dpnor_macro__left_0__ports_3__stack_2r__width_1 nor_gnt0_2 | |
465 | ( | |
466 | .din0 (gnt0_r_m[0]), | |
467 | .din1 (gnt0_r_m[1]), | |
468 | .din2 (gnt0_r_m[2]), | |
469 | .dout (not_gnt0_2) | |
470 | ||
471 | ); | |
472 | ||
473 | ||
474 | sii_ipcc_dpand_macro__left_0__ports_2__stack_4r__width_1 and_gnt1 | |
475 | ( | |
476 | .din0 (not_gnt0_r_m[0]), | |
477 | .din1 (gnt0_r_m[1]), | |
478 | .dout (gnt_pri[1]) | |
479 | ); | |
480 | ||
481 | sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1 and_gnt2 | |
482 | ( | |
483 | .din0 (not_gnt0_r_m[0]), | |
484 | .din1 (not_gnt0_r_m[1]), | |
485 | .din2 (gnt0_r_m[2]), | |
486 | .dout (gnt_pri[2]) | |
487 | ); | |
488 | ||
489 | sii_ipcc_dpand_macro__left_0__ports_4__stack_4r__width_1 and_gnt3 | |
490 | ( | |
491 | .din0 (not_gnt0_r_m[0]), | |
492 | .din1 (not_gnt0_r_m[1]), | |
493 | .din2 (not_gnt0_r_m[2]), | |
494 | .din3 (gnt0_r_m[3]), | |
495 | .dout (gnt_pri[3]) | |
496 | ); | |
497 | ||
498 | sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1 and_gnt4 | |
499 | ( | |
500 | .din0 (not_gnt0_2), | |
501 | .din1 (not_gnt0_r_m[3]), | |
502 | // N2- Bug 111258, AT: .din2 (gnt0_r_m[4]), | |
503 | .din2 (1'b1), // N2+ Bug 111258, AT | |
504 | .dout (gnt_pri[4]) | |
505 | ); | |
506 | ||
507 | sii_ipcc_dpmux_macro__mux_pgnpe__ports_5__stack_72c__width_72 mux_curhdr | |
508 | ( | |
509 | .dout (curhdr_l[71:0]) , | |
510 | .din4 (tcu_hdr[71:0]), | |
511 | .din3 (ipdohq0_dout[71:0]), | |
512 | .din2 (ipdbhq0_dout[71:0]), | |
513 | .din1 (ipdohq1_dout[71:0]), | |
514 | .din0 (ipdbhq1_dout[71:0]), | |
515 | .sel4 (gnt_pri[4]), | |
516 | .sel3 (gnt_pri[3]), | |
517 | .sel2 (gnt_pri[2]), | |
518 | .sel1 (gnt_pri[1]), | |
519 | .sel0 (gnt_pri[0]), | |
520 | .muxtst(muxtst) | |
521 | ) ; | |
522 | ||
523 | sii_ipcc_dpmsff_macro__stack_64c__width_64 ff_newdata | |
524 | ( | |
525 | .scan_in(ff_newdata_scanin), | |
526 | .scan_out(ff_newdata_scanout), | |
527 | .din (newdata[63:0]), | |
528 | .clk (l2clk), | |
529 | .en (1'b1), | |
530 | .dout (newdata_r[63:0]), | |
531 | .se(se), | |
532 | .siclk(siclk), | |
533 | .soclk(soclk), | |
534 | .pce_ov(pce_ov), | |
535 | .stop(stop) | |
536 | ) ; | |
537 | ||
538 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64 mux_newdata | |
539 | ( | |
540 | .dout (newdata[63:0]) , | |
541 | .din1 (newdata_tmp[63:0]), | |
542 | .din0 (tcu_data[63:0]), | |
543 | .sel0 (gnt0_r_m[4]) | |
544 | ) ; | |
545 | ||
546 | sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_64c__width_64 mux_newdata_tmp | |
547 | ( | |
548 | .dout (newdata_tmp[63:0]) , | |
549 | .din7 (ipdodq0_dout[127:64]), | |
550 | .din6 (ipdodq0_dout[63:0]), | |
551 | .din5 (ipdbdq0_dout[127:64]), | |
552 | .din4 (ipdbdq0_dout[63:0]), | |
553 | .din3 (ipdodq1_dout[127:64]), | |
554 | .din2 (ipdodq1_dout[63:0]), | |
555 | .din1 (ipdbdq1_dout[127:64]), | |
556 | .din0 (ipdbdq1_dout[63:0]), | |
557 | .sel (data_sel[2:0]), | |
558 | .muxtst(muxtst), | |
559 | .test(test) | |
560 | ) ; | |
561 | ||
562 | assign be_par7[13:0] = {1'b0, ipdodq0_dout[152], ipdodq0_dout[143:136],ipdodq0_dout[151:148]}; | |
563 | assign be_par6[13:0] = {2'b0, ipdodq0_dout[135:128],ipdodq0_dout[147:144]}; | |
564 | assign be_par5[13:0] = {1'b0, ipdbdq0_dout[152], ipdbdq0_dout[143:136],ipdbdq0_dout[151:148]}; | |
565 | assign be_par4[13:0] = {2'b0, ipdbdq0_dout[135:128],ipdbdq0_dout[147:144]}; | |
566 | assign be_par3[13:0] = {1'b0, ipdodq1_dout[152], ipdodq1_dout[143:136],ipdodq1_dout[151:148]}; | |
567 | assign be_par2[13:0] = {2'b0, ipdodq1_dout[135:128],ipdodq1_dout[147:144]}; | |
568 | assign be_par1[13:0] = {1'b0, ipdbdq1_dout[152], ipdbdq1_dout[143:136],ipdbdq1_dout[151:148]}; | |
569 | assign be_par0[13:0] = {2'b0, ipdbdq1_dout[135:128],ipdbdq1_dout[147:144]}; | |
570 | ||
571 | ||
572 | sii_ipcc_dpmsff_macro__stack_14c__width_14 ff_newbe_par | |
573 | ( | |
574 | .scan_in(ff_newbe_par_scanin), | |
575 | .scan_out(ff_newbe_par_scanout), | |
576 | .din (newbe_par[13:0]), | |
577 | .clk (l2clk), | |
578 | .dout (newbe_par_r[13:0]), | |
579 | .en (1'b1), | |
580 | .se(se), | |
581 | .siclk(siclk), | |
582 | .soclk(soclk), | |
583 | .pce_ov(pce_ov), | |
584 | .stop(stop) | |
585 | ) ; | |
586 | ||
587 | sii_ipcc_dpmsff_macro__stack_14c__width_14 ff_newbe_par_rr | |
588 | ( | |
589 | .scan_in(ff_newbe_par_rr_scanin), | |
590 | .scan_out(ff_newbe_par_rr_scanout), | |
591 | .din ({newbe_par_r[13:8], ipcc_data_out[71:64]}), | |
592 | .clk (l2clk), | |
593 | .dout (newbe_par_rr[13:0]), | |
594 | .en (1'b1), | |
595 | .se(se), | |
596 | .siclk(siclk), | |
597 | .soclk(soclk), | |
598 | .pce_ov(pce_ov), | |
599 | .stop(stop) | |
600 | ) ; | |
601 | ||
602 | sii_ipcc_dpmsff_macro__stack_8c__width_8 ff_mb0_wdata | |
603 | ( | |
604 | .scan_in(ff_mb0_wdata_scanin), | |
605 | .scan_out(ff_mb0_wdata_scanout), | |
606 | .din (sii_mb0_wdata_buf[7:0]), | |
607 | .clk (l2clk), | |
608 | .dout (sii_mb0_wdata_r[7:0]), | |
609 | .en (1'b1), | |
610 | .se(se), | |
611 | .siclk(siclk), | |
612 | .soclk(soclk), | |
613 | .pce_ov(pce_ov), | |
614 | .stop(stop) | |
615 | ) ; | |
616 | ||
617 | sii_ipcc_dpbuff_macro__minbuff_1__stack_8r__width_8 buf_sii_mb0_wdata | |
618 | ( | |
619 | .din (sii_mb0_wdata[7:0]), | |
620 | .dout (sii_mb0_wdata_buf[7:0]) | |
621 | ); | |
622 | ||
623 | ||
624 | //--------------------------------------------------------------------- | |
625 | // MUX SELECT ECC | |
626 | //--------------------------------------------------------------------- | |
627 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14 mux_ipcc_ecc | |
628 | ( | |
629 | .dout (ipcc_ecc[13:0]) , | |
630 | .din1 (new_ecc[13:0]), | |
631 | .din0 ({8'b0, new_c[5:0]}), | |
632 | .sel0 (hdr_data_sel) | |
633 | ) ; | |
634 | ||
635 | assign new_ecc[13:0] = {ecch[6:2], xor_ecc_h_l[3:2], eccl[6:2], xor_ecc_h_l[1:0]}; | |
636 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecc | |
637 | ( | |
638 | .din0 ({ecch[1:0], eccl[1:0]}), | |
639 | .din1 ({data_parity_err, data_parity_err, data_parity_err, data_parity_err}), | |
640 | .dout (xor_ecc_h_l[3:0]) | |
641 | ); | |
642 | ||
643 | //--------------------------------------------------------------------- | |
644 | // DATA ECC GENERATION LOGIC | |
645 | //--------------------------------------------------------------------- | |
646 | assign eccd_h[31:0] = ipcc_dp_par_data[63:32]; | |
647 | assign eccd_l[31:0] = ipcc_dp_par_data[31:0]; | |
648 | ||
649 | assign eccd_h_0_l = {eccd_h[0], eccd_h[3], eccd_h[6], eccd_h[10], eccd_h[13], | |
650 | eccd_h[17], eccd_h[21], eccd_h[25], eccd_h[28]}; | |
651 | ||
652 | assign eccd_h_0_r = {eccd_h[1], eccd_h[4], eccd_h[8], eccd_h[11], eccd_h[15], | |
653 | eccd_h[19], eccd_h[23], eccd_h[26], eccd_h[30]}; | |
654 | ||
655 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_ecch_0_l1 ( | |
656 | .din0 (eccd_h_0_l[8:0]), | |
657 | .din1 (eccd_h_0_r[8:0]), | |
658 | .dout (eccd_h_0_l1[8:0]) | |
659 | ); | |
660 | ||
661 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_0_l2 ( | |
662 | .din0 (eccd_h_0_l1[3:0]), | |
663 | .din1 (eccd_h_0_l1[7:4]), | |
664 | .dout (eccd_h_0_l2[3:0]) | |
665 | ); | |
666 | ||
667 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_0_l3 ( | |
668 | .din0 (eccd_h_0_l2[1:0]), | |
669 | .din1 (eccd_h_0_l2[3:2]), | |
670 | .dout (eccd_h_0_l3[1:0]) | |
671 | ); | |
672 | ||
673 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_ecch_0_l4 ( | |
674 | .din0 (eccd_h_0_l3[0]), | |
675 | .din1 (eccd_h_0_l3[1]), | |
676 | .din2 (eccd_h_0_l1[8]), | |
677 | .dout (ecch[0]) | |
678 | ); | |
679 | ||
680 | assign eccd_h_1_l = {eccd_h[0], eccd_h[3], eccd_h[6], eccd_h[10], eccd_h[13], | |
681 | eccd_h[17], eccd_h[21], eccd_h[25], eccd_h[28]}; | |
682 | ||
683 | assign eccd_h_1_r = {eccd_h[2], eccd_h[5], eccd_h[9], eccd_h[12], eccd_h[16], | |
684 | eccd_h[20], eccd_h[24], eccd_h[27], eccd_h[31]}; | |
685 | ||
686 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_ecch_1_l1 ( | |
687 | .din0 (eccd_h_1_l[8:0]), | |
688 | .din1 (eccd_h_1_r[8:0]), | |
689 | .dout (eccd_h_1_l1[8:0]) | |
690 | ); | |
691 | ||
692 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_1_l2 ( | |
693 | .din0 (eccd_h_1_l1[3:0]), | |
694 | .din1 (eccd_h_1_l1[7:4]), | |
695 | .dout (eccd_h_1_l2[3:0]) | |
696 | ); | |
697 | ||
698 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_1_l3 ( | |
699 | .din0 (eccd_h_1_l2[1:0]), | |
700 | .din1 (eccd_h_1_l2[3:2]), | |
701 | .dout (eccd_h_1_l3[1:0]) | |
702 | ); | |
703 | ||
704 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_ecch_1_l4 ( | |
705 | .din0 (eccd_h_1_l3[0]), | |
706 | .din1 (eccd_h_1_l3[1]), | |
707 | .din2 (eccd_h_1_l1[8]), | |
708 | .dout (ecch[1]) | |
709 | ); | |
710 | ||
711 | assign eccd_h_2_l = {eccd_h[1], eccd_h[3], eccd_h[8], eccd_h[10], eccd_h[15], | |
712 | eccd_h[17], eccd_h[23], eccd_h[25], eccd_h[30]}; | |
713 | ||
714 | assign eccd_h_2_r = {eccd_h[2], eccd_h[7], eccd_h[9], eccd_h[14], eccd_h[16], | |
715 | eccd_h[22], eccd_h[24], eccd_h[29], eccd_h[31]}; | |
716 | ||
717 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_ecch_2_l1 ( | |
718 | .din0 (eccd_h_2_l[8:0]), | |
719 | .din1 (eccd_h_2_r[8:0]), | |
720 | .dout (eccd_h_2_l1[8:0]) | |
721 | ); | |
722 | ||
723 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_2_l2 ( | |
724 | .din0 (eccd_h_2_l1[3:0]), | |
725 | .din1 (eccd_h_2_l1[7:4]), | |
726 | .dout (eccd_h_2_l2[3:0]) | |
727 | ); | |
728 | ||
729 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_2_l3 ( | |
730 | .din0 (eccd_h_2_l2[1:0]), | |
731 | .din1 (eccd_h_2_l2[3:2]), | |
732 | .dout (eccd_h_2_l3[1:0]) | |
733 | ); | |
734 | ||
735 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_ecch_2_l4 ( | |
736 | .din0 (eccd_h_2_l3[0]), | |
737 | .din1 (eccd_h_2_l3[1]), | |
738 | .din2 (eccd_h_2_l1[8]), | |
739 | .dout (ecch[2]) | |
740 | ); | |
741 | ||
742 | assign eccd_h_3_l = {eccd_h[4], eccd_h[6], eccd_h[8], eccd_h[10], eccd_h[19], | |
743 | eccd_h[21], eccd_h[23]}; | |
744 | ||
745 | assign eccd_h_3_r = {eccd_h[5], eccd_h[7], eccd_h[9], eccd_h[18], eccd_h[20], | |
746 | eccd_h[22], eccd_h[24]}; | |
747 | ||
748 | sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7 xor_ecch_3_l1 ( | |
749 | .din0 (eccd_h_3_l[6:0]), | |
750 | .din1 (eccd_h_3_r[6:0]), | |
751 | .dout (eccd_h_3_l1[6:0]) | |
752 | ); | |
753 | ||
754 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_3_l2 ( | |
755 | .din0 (eccd_h_3_l1[3:0]), | |
756 | .din1 ({eccd_h_3_l1[6:4],eccd_h[25]}), | |
757 | .dout (eccd_h_3_l2[3:0]) | |
758 | ); | |
759 | ||
760 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_3_l3 ( | |
761 | .din0 (eccd_h_3_l2[1:0]), | |
762 | .din1 (eccd_h_3_l2[3:2]), | |
763 | .dout (eccd_h_3_l3[1:0]) | |
764 | ); | |
765 | ||
766 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1 xor_ecch_3_l4 ( | |
767 | .din0 (eccd_h_3_l3[0]), | |
768 | .din1 (eccd_h_3_l3[1]), | |
769 | .dout (ecch[3]) | |
770 | ); | |
771 | ||
772 | ||
773 | assign eccd_h_4_l = {eccd_h[11], eccd_h[13], eccd_h[15], eccd_h[17], eccd_h[19], | |
774 | eccd_h[21], eccd_h[23]}; | |
775 | ||
776 | assign eccd_h_4_r = {eccd_h[12], eccd_h[14], eccd_h[16], eccd_h[18], eccd_h[20], | |
777 | eccd_h[22], eccd_h[24]}; | |
778 | ||
779 | sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7 xor_ecch_4_l1 ( | |
780 | .din0 (eccd_h_4_l[6:0]), | |
781 | .din1 (eccd_h_4_r[6:0]), | |
782 | .dout (eccd_h_4_l1[6:0]) | |
783 | ); | |
784 | ||
785 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_4_l2 ( | |
786 | .din0 (eccd_h_4_l1[3:0]), | |
787 | .din1 ({eccd_h_4_l1[6:4],eccd_h[25]}), | |
788 | .dout (eccd_h_4_l2[3:0]) | |
789 | ); | |
790 | ||
791 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_4_l3 ( | |
792 | .din0 (eccd_h_4_l2[1:0]), | |
793 | .din1 (eccd_h_4_l2[3:2]), | |
794 | .dout (eccd_h_4_l3[1:0]) | |
795 | ); | |
796 | ||
797 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1 xor_ecch_4_l4 ( | |
798 | .din0 (eccd_h_4_l3[0]), | |
799 | .din1 (eccd_h_4_l3[1]), | |
800 | .dout (ecch[4]) | |
801 | ); | |
802 | ||
803 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3 xor_ecch_5_l1 ( | |
804 | .din0 ({eccd_h[26], eccd_h[28], eccd_h[30]}), | |
805 | .din1 ({eccd_h[27], eccd_h[29], eccd_h[31]}), | |
806 | .dout (eccd_h_5_l1[2:0]) | |
807 | ); | |
808 | ||
809 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_ecch_5_l4 ( | |
810 | .din0 (eccd_h_5_l1[0]), | |
811 | .din1 (eccd_h_5_l1[1]), | |
812 | .din2 (eccd_h_5_l1[2]), | |
813 | .dout (ecch[5]) | |
814 | ); | |
815 | ||
816 | assign eccd_h_6_l = {eccd_h[0], eccd_h[1], eccd_h[2], eccd_h[4], eccd_h[5], | |
817 | eccd_h[7], eccd_h[10], eccd_h[11], eccd_h[12]}; | |
818 | ||
819 | assign eccd_h_6_r = {eccd_h[14], eccd_h[17], eccd_h[18], eccd_h[21], eccd_h[23], | |
820 | eccd_h[24], eccd_h[26], eccd_h[27], eccd_h[29]}; | |
821 | ||
822 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_ecch_6_l1 ( | |
823 | .din0 (eccd_h_6_l[8:0]), | |
824 | .din1 (eccd_h_6_r[8:0]), | |
825 | .dout (eccd_h_6_l1[8:0]) | |
826 | ); | |
827 | ||
828 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_ecch_6_l2 ( | |
829 | .din0 (eccd_h_6_l1[3:0]), | |
830 | .din1 (eccd_h_6_l1[7:4]), | |
831 | .dout (eccd_h_6_l2[3:0]) | |
832 | ); | |
833 | ||
834 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_ecch_6_l3 ( | |
835 | .din0 (eccd_h_6_l2[1:0]), | |
836 | .din1 (eccd_h_6_l2[3:2]), | |
837 | .dout (eccd_h_6_l3[1:0]) | |
838 | ); | |
839 | ||
840 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_ecch_6_l4 ( | |
841 | .din0 (eccd_h_6_l3[0]), | |
842 | .din1 (eccd_h_6_l3[1]), | |
843 | .din2 (eccd_h_6_l1[8]), | |
844 | .dout (ecch[6]) | |
845 | ); | |
846 | ||
847 | //--------------------------------------------------------------------- | |
848 | ||
849 | assign eccd_l_0_l = {eccd_l[0], eccd_l[3], eccd_l[6], eccd_l[10], eccd_l[13], | |
850 | eccd_l[17], eccd_l[21], eccd_l[25], eccd_l[28]}; | |
851 | ||
852 | assign eccd_l_0_r = {eccd_l[1], eccd_l[4], eccd_l[8], eccd_l[11], eccd_l[15], | |
853 | eccd_l[19], eccd_l[23], eccd_l[26], eccd_l[30]}; | |
854 | ||
855 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_eccl_0_l1 ( | |
856 | .din0 (eccd_l_0_l[8:0]), | |
857 | .din1 (eccd_l_0_r[8:0]), | |
858 | .dout (eccd_l_0_l1[8:0]) | |
859 | ); | |
860 | ||
861 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_eccl_0_l2 ( | |
862 | .din0 (eccd_l_0_l1[3:0]), | |
863 | .din1 (eccd_l_0_l1[7:4]), | |
864 | .dout (eccd_l_0_l2[3:0]) | |
865 | ); | |
866 | ||
867 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_eccl_0_l3 ( | |
868 | .din0 (eccd_l_0_l2[1:0]), | |
869 | .din1 (eccd_l_0_l2[3:2]), | |
870 | .dout (eccd_l_0_l3[1:0]) | |
871 | ); | |
872 | ||
873 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_eccl_0_l4 ( | |
874 | .din0 (eccd_l_0_l3[0]), | |
875 | .din1 (eccd_l_0_l3[1]), | |
876 | .din2 (eccd_l_0_l1[8]), | |
877 | .dout (eccl[0]) | |
878 | ); | |
879 | ||
880 | assign eccd_l_1_l = {eccd_l[0], eccd_l[3], eccd_l[6], eccd_l[10], eccd_l[13], | |
881 | eccd_l[17], eccd_l[21], eccd_l[25], eccd_l[28]}; | |
882 | ||
883 | assign eccd_l_1_r = {eccd_l[2], eccd_l[5], eccd_l[9], eccd_l[12], eccd_l[16], | |
884 | eccd_l[20], eccd_l[24], eccd_l[27], eccd_l[31]}; | |
885 | ||
886 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_eccl_1_l1 ( | |
887 | .din0 (eccd_l_1_l[8:0]), | |
888 | .din1 (eccd_l_1_r[8:0]), | |
889 | .dout (eccd_l_1_l1[8:0]) | |
890 | ); | |
891 | ||
892 | sii_ipcc_dpxor_macro__ports_2__stack_8r__width_4 xor_eccl_1_l2 ( | |
893 | .din0 (eccd_l_1_l1[3:0]), | |
894 | .din1 (eccd_l_1_l1[7:4]), | |
895 | .dout (eccd_l_1_l2[3:0]) | |
896 | ); | |
897 | ||
898 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_2 xor_eccl_1_l3 ( | |
899 | .din0 (eccd_l_1_l2[1:0]), | |
900 | .din1 (eccd_l_1_l2[3:2]), | |
901 | .dout (eccd_l_1_l3[1:0]) | |
902 | ); | |
903 | ||
904 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_eccl_1_l4 ( | |
905 | .din0 (eccd_l_1_l3[0]), | |
906 | .din1 (eccd_l_1_l3[1]), | |
907 | .din2 (eccd_l_1_l1[8]), | |
908 | .dout (eccl[1]) | |
909 | ); | |
910 | ||
911 | assign eccd_l_2_l = {eccd_l[1], eccd_l[3], eccd_l[8], eccd_l[10], eccd_l[15], | |
912 | eccd_l[17], eccd_l[23], eccd_l[25], eccd_l[30]}; | |
913 | ||
914 | assign eccd_l_2_r = {eccd_l[2], eccd_l[7], eccd_l[9], eccd_l[14], eccd_l[16], | |
915 | eccd_l[22], eccd_l[24], eccd_l[29], eccd_l[31]}; | |
916 | ||
917 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_eccl_2_l1 ( | |
918 | .din0 (eccd_l_2_l[8:0]), | |
919 | .din1 (eccd_l_2_r[8:0]), | |
920 | .dout (eccd_l_2_l1[8:0]) | |
921 | ); | |
922 | ||
923 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_eccl_2_l2 ( | |
924 | .din0 (eccd_l_2_l1[3:0]), | |
925 | .din1 (eccd_l_2_l1[7:4]), | |
926 | .dout (eccd_l_2_l2[3:0]) | |
927 | ); | |
928 | ||
929 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_eccl_2_l3 ( | |
930 | .din0 (eccd_l_2_l2[1:0]), | |
931 | .din1 (eccd_l_2_l2[3:2]), | |
932 | .dout (eccd_l_2_l3[1:0]) | |
933 | ); | |
934 | ||
935 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_eccl_2_l4 ( | |
936 | .din0 (eccd_l_2_l3[0]), | |
937 | .din1 (eccd_l_2_l3[1]), | |
938 | .din2 (eccd_l_2_l1[8]), | |
939 | .dout (eccl[2]) | |
940 | ); | |
941 | ||
942 | assign eccd_l_3_l = {eccd_l[4], eccd_l[6], eccd_l[8], eccd_l[10], eccd_l[19], | |
943 | eccd_l[21], eccd_l[23]}; | |
944 | ||
945 | assign eccd_l_3_r = {eccd_l[5], eccd_l[7], eccd_l[9], eccd_l[18], eccd_l[20], | |
946 | eccd_l[22], eccd_l[24]}; | |
947 | ||
948 | sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7 xor_eccl_3_l1 ( | |
949 | .din0 (eccd_l_3_l[6:0]), | |
950 | .din1 (eccd_l_3_r[6:0]), | |
951 | .dout (eccd_l_3_l1[6:0]) | |
952 | ); | |
953 | ||
954 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_eccl_3_l2 ( | |
955 | .din0 (eccd_l_3_l1[3:0]), | |
956 | .din1 ({eccd_l_3_l1[6:4],eccd_l[25]}), | |
957 | .dout (eccd_l_3_l2[3:0]) | |
958 | ); | |
959 | ||
960 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_eccl_3_l3 ( | |
961 | .din0 (eccd_l_3_l2[1:0]), | |
962 | .din1 (eccd_l_3_l2[3:2]), | |
963 | .dout (eccd_l_3_l3[1:0]) | |
964 | ); | |
965 | ||
966 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1 xor_eccl_3_l4 ( | |
967 | .din0 (eccd_l_3_l3[0]), | |
968 | .din1 (eccd_l_3_l3[1]), | |
969 | .dout (eccl[3]) | |
970 | ); | |
971 | ||
972 | ||
973 | assign eccd_l_4_l = {eccd_l[11], eccd_l[13], eccd_l[15], eccd_l[17], eccd_l[19], | |
974 | eccd_l[21], eccd_l[23]}; | |
975 | ||
976 | assign eccd_l_4_r = {eccd_l[12], eccd_l[14], eccd_l[16], eccd_l[18], eccd_l[20], | |
977 | eccd_l[22], eccd_l[24]}; | |
978 | ||
979 | sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7 xor_eccl_4_l1 ( | |
980 | .din0 (eccd_l_4_l[6:0]), | |
981 | .din1 (eccd_l_4_r[6:0]), | |
982 | .dout (eccd_l_4_l1[6:0]) | |
983 | ); | |
984 | ||
985 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_eccl_4_l2 ( | |
986 | .din0 (eccd_l_4_l1[3:0]), | |
987 | .din1 ({eccd_l_4_l1[6:4],eccd_l[25]}), | |
988 | .dout (eccd_l_4_l2[3:0]) | |
989 | ); | |
990 | ||
991 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_eccl_4_l3 ( | |
992 | .din0 (eccd_l_4_l2[1:0]), | |
993 | .din1 (eccd_l_4_l2[3:2]), | |
994 | .dout (eccd_l_4_l3[1:0]) | |
995 | ); | |
996 | ||
997 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1 xor_eccl_4_l4 ( | |
998 | .din0 (eccd_l_4_l3[0]), | |
999 | .din1 (eccd_l_4_l3[1]), | |
1000 | .dout (eccl[4]) | |
1001 | ); | |
1002 | ||
1003 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3 xor_eccl_5_l1 ( | |
1004 | .din0 ({eccd_l[26], eccd_l[28], eccd_l[30]}), | |
1005 | .din1 ({eccd_l[27], eccd_l[29], eccd_l[31]}), | |
1006 | .dout (eccd_l_5_l1[2:0]) | |
1007 | ); | |
1008 | ||
1009 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_eccl_5_l4 ( | |
1010 | .din0 (eccd_l_5_l1[0]), | |
1011 | .din1 (eccd_l_5_l1[1]), | |
1012 | .din2 (eccd_l_5_l1[2]), | |
1013 | .dout (eccl[5]) | |
1014 | ); | |
1015 | ||
1016 | assign eccd_l_6_l = {eccd_l[0], eccd_l[1], eccd_l[2], eccd_l[4], eccd_l[5], | |
1017 | eccd_l[7], eccd_l[10], eccd_l[11], eccd_l[12]}; | |
1018 | ||
1019 | assign eccd_l_6_r = {eccd_l[14], eccd_l[17], eccd_l[18], eccd_l[21], eccd_l[23], | |
1020 | eccd_l[24], eccd_l[26], eccd_l[27], eccd_l[29]}; | |
1021 | ||
1022 | sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 xor_eccl_6_l1 ( | |
1023 | .din0 (eccd_l_6_l[8:0]), | |
1024 | .din1 (eccd_l_6_r[8:0]), | |
1025 | .dout (eccd_l_6_l1[8:0]) | |
1026 | ); | |
1027 | ||
1028 | sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 xor_eccl_6_l2 ( | |
1029 | .din0 (eccd_l_6_l1[3:0]), | |
1030 | .din1 (eccd_l_6_l1[7:4]), | |
1031 | .dout (eccd_l_6_l2[3:0]) | |
1032 | ); | |
1033 | ||
1034 | sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 xor_eccl_6_l3 ( | |
1035 | .din0 (eccd_l_6_l2[1:0]), | |
1036 | .din1 (eccd_l_6_l2[3:2]), | |
1037 | .dout (eccd_l_6_l3[1:0]) | |
1038 | ); | |
1039 | ||
1040 | sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 xor_eccl_6_l4 ( | |
1041 | .din0 (eccd_l_6_l3[0]), | |
1042 | .din1 (eccd_l_6_l3[1]), | |
1043 | .din2 (eccd_l_6_l1[8]), | |
1044 | .dout (eccl[6]) | |
1045 | ); | |
1046 | ||
1047 | ||
1048 | //--------------------------------------------------------------------- | |
1049 | // DATA PARITY GENERATION LOGIC | |
1050 | //--------------------------------------------------------------------- | |
1051 | ||
1052 | sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14 mux_newbe_par | |
1053 | ( | |
1054 | .dout (newbe_par[13:0]) , | |
1055 | .din1 (newbe_par1[13:0]), | |
1056 | .din0 ({2'b0, tcu_be_par[11:0]}), | |
1057 | .sel0 (gnt0_r_m[4]) | |
1058 | ) ; | |
1059 | ||
1060 | sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_14c__width_14 mux_newbe_par1 | |
1061 | ( | |
1062 | .dout (newbe_par1[13:0]) , | |
1063 | .din7 (be_par7[13:0]), | |
1064 | .din6 (be_par6[13:0]), | |
1065 | .din5 (be_par5[13:0]), | |
1066 | .din4 (be_par4[13:0]), | |
1067 | .din3 (be_par3[13:0]), | |
1068 | .din2 (be_par2[13:0]), | |
1069 | .din1 (be_par1[13:0]), | |
1070 | .din0 (be_par0[13:0]), | |
1071 | .sel (data_sel[2:0]), | |
1072 | .muxtst(muxtst), | |
1073 | .test(test) | |
1074 | ) ; | |
1075 | ||
1076 | sii_ipcc_dpmsff_macro__stack_18c__width_18 ff_newbe | |
1077 | ( | |
1078 | .scan_in(ff_newbe_scanin), | |
1079 | .scan_out(ff_newbe_scanout), | |
1080 | .din (new_be[17:0]), | |
1081 | .clk (l2clk), | |
1082 | .en (1'b1), | |
1083 | .dout ({new_be_unused, new_be_r[16:0]}), | |
1084 | .se(se), | |
1085 | .siclk(siclk), | |
1086 | .soclk(soclk), | |
1087 | .pce_ov(pce_ov), | |
1088 | .stop(stop) | |
1089 | ) ; | |
1090 | ||
1091 | sii_ipcc_dpmux_macro__mux_pgdec__ports_4__stack_18c__width_18 mux_newbe | |
1092 | ( | |
1093 | .dout (new_be[17:0]) , | |
1094 | .din3 ({1'b0, ipdodq0_dout[152], be_par7[11:4], be_par6[11:4]}), | |
1095 | .din2 ({1'b0, ipdbdq0_dout[152], be_par5[11:4], be_par4[11:4]}), | |
1096 | .din1 ({1'b0, ipdodq1_dout[152], be_par3[11:4], be_par2[11:4]}), | |
1097 | .din0 ({1'b0, ipdbdq1_dout[152], be_par1[11:4], be_par0[11:4]}), | |
1098 | .sel (data_sel[2:1]), | |
1099 | .muxtst(muxtst), | |
1100 | .test(test) | |
1101 | ) ; | |
1102 | ||
1103 | sii_ipcc_dpmsff_macro__stack_14c__width_14 ff_ipcc_ecc | |
1104 | ( | |
1105 | .scan_in(ff_ipcc_ecc_scanin), | |
1106 | .scan_out(ff_ipcc_ecc_scanout), | |
1107 | .din (ipcc_ecc[13:0]), | |
1108 | .clk (l2clk), | |
1109 | .en (1'b1), | |
1110 | .dout (ipcc_ecc_r[13:0]), | |
1111 | .se(se), | |
1112 | .siclk(siclk), | |
1113 | .soclk(soclk), | |
1114 | .pce_ov(pce_ov), | |
1115 | .stop(stop) | |
1116 | ) ; | |
1117 | ||
1118 | // fixscan start: | |
1119 | assign ff_ipcc_data_out_scanin = scan_in ; | |
1120 | assign ff_curhdri_scanin = ff_ipcc_data_out_scanout ; | |
1121 | assign ff_newdata_scanin = ff_curhdri_scanout ; | |
1122 | assign ff_newbe_par_scanin = ff_newdata_scanout ; | |
1123 | assign ff_newbe_par_rr_scanin = ff_newbe_par_scanout ; | |
1124 | assign ff_mb0_wdata_scanin = ff_newbe_par_rr_scanout ; | |
1125 | assign ff_newbe_scanin = ff_mb0_wdata_scanout ; | |
1126 | assign ff_ipcc_ecc_scanin = ff_newbe_scanout ; | |
1127 | assign scan_out = ff_ipcc_ecc_scanout ; | |
1128 | // fixscan end: | |
1129 | endmodule | |
1130 | ||
1131 | ||
1132 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1133 | // also for pass-gate with decoder | |
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | // any PARAMS parms go into naming of macro | |
1140 | ||
1141 | module sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_64c__width_64 ( | |
1142 | din0, | |
1143 | din1, | |
1144 | sel0, | |
1145 | dout); | |
1146 | wire psel0_unused; | |
1147 | wire psel1; | |
1148 | ||
1149 | input [63:0] din0; | |
1150 | input [63:0] din1; | |
1151 | input sel0; | |
1152 | output [63:0] dout; | |
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | cl_dp1_penc2_8x c0_0 ( | |
1159 | .sel0(sel0), | |
1160 | .psel0(psel0_unused), | |
1161 | .psel1(psel1) | |
1162 | ); | |
1163 | ||
1164 | mux2e #(64) d0_0 ( | |
1165 | .sel(psel1), | |
1166 | .in0(din0[63:0]), | |
1167 | .in1(din1[63:0]), | |
1168 | .dout(dout[63:0]) | |
1169 | ); | |
1170 | ||
1171 | ||
1172 | ||
1173 | ||
1174 | ||
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | endmodule | |
1184 | ||
1185 | ||
1186 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1187 | // also for pass-gate with decoder | |
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | ||
1193 | // any PARAMS parms go into naming of macro | |
1194 | ||
1195 | module sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_20c__width_20 ( | |
1196 | din0, | |
1197 | din1, | |
1198 | sel0, | |
1199 | dout); | |
1200 | wire psel0_unused; | |
1201 | wire psel1; | |
1202 | ||
1203 | input [19:0] din0; | |
1204 | input [19:0] din1; | |
1205 | input sel0; | |
1206 | output [19:0] dout; | |
1207 | ||
1208 | ||
1209 | ||
1210 | ||
1211 | ||
1212 | cl_dp1_penc2_8x c0_0 ( | |
1213 | .sel0(sel0), | |
1214 | .psel0(psel0_unused), | |
1215 | .psel1(psel1) | |
1216 | ); | |
1217 | ||
1218 | mux2e #(20) d0_0 ( | |
1219 | .sel(psel1), | |
1220 | .in0(din0[19:0]), | |
1221 | .in1(din1[19:0]), | |
1222 | .dout(dout[19:0]) | |
1223 | ); | |
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | ||
1236 | ||
1237 | endmodule | |
1238 | ||
1239 | ||
1240 | // | |
1241 | // buff macro | |
1242 | // | |
1243 | // | |
1244 | ||
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | module sii_ipcc_dpbuff_macro__dbuff_48x__stack_46c__width_46 ( | |
1250 | din, | |
1251 | dout); | |
1252 | input [45:0] din; | |
1253 | output [45:0] dout; | |
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | buff #(46) d0_0 ( | |
1261 | .in(din[45:0]), | |
1262 | .out(dout[45:0]) | |
1263 | ); | |
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | endmodule | |
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | // | |
1279 | // buff macro | |
1280 | // | |
1281 | // | |
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | module sii_ipcc_dpbuff_macro__dbuff_48x__stack_44c__width_44 ( | |
1288 | din, | |
1289 | dout); | |
1290 | input [43:0] din; | |
1291 | output [43:0] dout; | |
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | buff #(44) d0_0 ( | |
1299 | .in(din[43:0]), | |
1300 | .out(dout[43:0]) | |
1301 | ); | |
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | ||
1307 | ||
1308 | ||
1309 | ||
1310 | endmodule | |
1311 | ||
1312 | ||
1313 | ||
1314 | ||
1315 | ||
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | // any PARAMS parms go into naming of macro | |
1321 | ||
1322 | module sii_ipcc_dpmsff_macro__stack_72c__width_72 ( | |
1323 | din, | |
1324 | clk, | |
1325 | en, | |
1326 | se, | |
1327 | scan_in, | |
1328 | siclk, | |
1329 | soclk, | |
1330 | pce_ov, | |
1331 | stop, | |
1332 | dout, | |
1333 | scan_out); | |
1334 | wire l1clk; | |
1335 | wire siclk_out; | |
1336 | wire soclk_out; | |
1337 | wire [70:0] so; | |
1338 | ||
1339 | input [71:0] din; | |
1340 | ||
1341 | ||
1342 | input clk; | |
1343 | input en; | |
1344 | input se; | |
1345 | input scan_in; | |
1346 | input siclk; | |
1347 | input soclk; | |
1348 | input pce_ov; | |
1349 | input stop; | |
1350 | ||
1351 | ||
1352 | ||
1353 | output [71:0] dout; | |
1354 | ||
1355 | ||
1356 | output scan_out; | |
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | cl_dp1_l1hdr_8x c0_0 ( | |
1362 | .l2clk(clk), | |
1363 | .pce(en), | |
1364 | .aclk(siclk), | |
1365 | .bclk(soclk), | |
1366 | .l1clk(l1clk), | |
1367 | .se(se), | |
1368 | .pce_ov(pce_ov), | |
1369 | .stop(stop), | |
1370 | .siclk_out(siclk_out), | |
1371 | .soclk_out(soclk_out) | |
1372 | ); | |
1373 | dff #(72) d0_0 ( | |
1374 | .l1clk(l1clk), | |
1375 | .siclk(siclk_out), | |
1376 | .soclk(soclk_out), | |
1377 | .d(din[71:0]), | |
1378 | .si({scan_in,so[70:0]}), | |
1379 | .so({so[70:0],scan_out}), | |
1380 | .q(dout[71:0]) | |
1381 | ); | |
1382 | ||
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | endmodule | |
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1413 | // also for pass-gate with decoder | |
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | // any PARAMS parms go into naming of macro | |
1420 | ||
1421 | module sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_8c__width_8 ( | |
1422 | din0, | |
1423 | din1, | |
1424 | sel0, | |
1425 | dout); | |
1426 | wire psel0_unused; | |
1427 | wire psel1; | |
1428 | ||
1429 | input [7:0] din0; | |
1430 | input [7:0] din1; | |
1431 | input sel0; | |
1432 | output [7:0] dout; | |
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | cl_dp1_penc2_8x c0_0 ( | |
1439 | .sel0(sel0), | |
1440 | .psel0(psel0_unused), | |
1441 | .psel1(psel1) | |
1442 | ); | |
1443 | ||
1444 | mux2e #(8) d0_0 ( | |
1445 | .sel(psel1), | |
1446 | .in0(din0[7:0]), | |
1447 | .in1(din1[7:0]), | |
1448 | .dout(dout[7:0]) | |
1449 | ); | |
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | endmodule | |
1464 | ||
1465 | ||
1466 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1467 | // also for pass-gate with decoder | |
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | // any PARAMS parms go into naming of macro | |
1474 | ||
1475 | module sii_ipcc_dpmux_macro__mux_pgnpe__ports_3__stack_64c__width_64 ( | |
1476 | din0, | |
1477 | sel0, | |
1478 | din1, | |
1479 | sel1, | |
1480 | din2, | |
1481 | sel2, | |
1482 | muxtst, | |
1483 | dout); | |
1484 | wire buffout0; | |
1485 | wire buffout1; | |
1486 | wire buffout2; | |
1487 | ||
1488 | input [63:0] din0; | |
1489 | input sel0; | |
1490 | input [63:0] din1; | |
1491 | input sel1; | |
1492 | input [63:0] din2; | |
1493 | input sel2; | |
1494 | input muxtst; | |
1495 | output [63:0] dout; | |
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | cl_dp1_muxbuff3_8x c0_0 ( | |
1502 | .in0(sel0), | |
1503 | .in1(sel1), | |
1504 | .in2(sel2), | |
1505 | .out0(buffout0), | |
1506 | .out1(buffout1), | |
1507 | .out2(buffout2) | |
1508 | ); | |
1509 | mux3 #(64) d0_0 ( | |
1510 | .sel0(buffout0), | |
1511 | .sel1(buffout1), | |
1512 | .sel2(buffout2), | |
1513 | .in0(din0[63:0]), | |
1514 | .in1(din1[63:0]), | |
1515 | .in2(din2[63:0]), | |
1516 | .dout(dout[63:0]), | |
1517 | .muxtst(muxtst) | |
1518 | ); | |
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | endmodule | |
1533 | ||
1534 | ||
1535 | // | |
1536 | // invert macro | |
1537 | // | |
1538 | // | |
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | module sii_ipcc_dpinv_macro__stack_2r__width_2 ( | |
1545 | din, | |
1546 | dout); | |
1547 | input [1:0] din; | |
1548 | output [1:0] dout; | |
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | inv #(2) d0_0 ( | |
1556 | .in(din[1:0]), | |
1557 | .out(dout[1:0]) | |
1558 | ); | |
1559 | ||
1560 | ||
1561 | ||
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | ||
1567 | ||
1568 | endmodule | |
1569 | ||
1570 | ||
1571 | ||
1572 | ||
1573 | ||
1574 | // | |
1575 | // and macro for ports = 2,3,4 | |
1576 | // | |
1577 | // | |
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | module sii_ipcc_dpand_macro__left_0__ports_2__stack_2r__width_2 ( | |
1584 | din0, | |
1585 | din1, | |
1586 | dout); | |
1587 | input [1:0] din0; | |
1588 | input [1:0] din1; | |
1589 | output [1:0] dout; | |
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 | and2 #(2) d0_0 ( | |
1597 | .in0(din0[1:0]), | |
1598 | .in1(din1[1:0]), | |
1599 | .out(dout[1:0]) | |
1600 | ); | |
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | endmodule | |
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | // | |
1617 | // invert macro | |
1618 | // | |
1619 | // | |
1620 | ||
1621 | ||
1622 | ||
1623 | ||
1624 | ||
1625 | module sii_ipcc_dpinv_macro__stack_72r__width_72 ( | |
1626 | din, | |
1627 | dout); | |
1628 | input [71:0] din; | |
1629 | output [71:0] dout; | |
1630 | ||
1631 | ||
1632 | ||
1633 | ||
1634 | ||
1635 | ||
1636 | inv #(72) d0_0 ( | |
1637 | .in(din[71:0]), | |
1638 | .out(dout[71:0]) | |
1639 | ); | |
1640 | ||
1641 | ||
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | endmodule | |
1650 | ||
1651 | ||
1652 | ||
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | // any PARAMS parms go into naming of macro | |
1660 | ||
1661 | module sii_ipcc_dpmsffi_macro__stack_72c__width_72 ( | |
1662 | din, | |
1663 | clk, | |
1664 | en, | |
1665 | se, | |
1666 | scan_in, | |
1667 | siclk, | |
1668 | soclk, | |
1669 | pce_ov, | |
1670 | stop, | |
1671 | dout_l, | |
1672 | scan_out); | |
1673 | wire l1clk; | |
1674 | wire siclk_out; | |
1675 | wire soclk_out; | |
1676 | wire [70:0] so; | |
1677 | ||
1678 | input [71:0] din; | |
1679 | ||
1680 | ||
1681 | input clk; | |
1682 | input en; | |
1683 | input se; | |
1684 | input scan_in; | |
1685 | input siclk; | |
1686 | input soclk; | |
1687 | input pce_ov; | |
1688 | input stop; | |
1689 | ||
1690 | ||
1691 | ||
1692 | output [71:0] dout_l; | |
1693 | ||
1694 | ||
1695 | output scan_out; | |
1696 | ||
1697 | ||
1698 | ||
1699 | ||
1700 | cl_dp1_l1hdr_8x c0_0 ( | |
1701 | .l2clk(clk), | |
1702 | .pce(en), | |
1703 | .aclk(siclk), | |
1704 | .bclk(soclk), | |
1705 | .l1clk(l1clk), | |
1706 | .se(se), | |
1707 | .pce_ov(pce_ov), | |
1708 | .stop(stop), | |
1709 | .siclk_out(siclk_out), | |
1710 | .soclk_out(soclk_out) | |
1711 | ); | |
1712 | msffi_dp #(72) d0_0 ( | |
1713 | .l1clk(l1clk), | |
1714 | .siclk(siclk_out), | |
1715 | .soclk(soclk_out), | |
1716 | .d(din[71:0]), | |
1717 | .si({scan_in,so[70:0]}), | |
1718 | .so({so[70:0],scan_out}), | |
1719 | .q_l(dout_l[71:0]) | |
1720 | ); | |
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | ||
1729 | ||
1730 | ||
1731 | ||
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | endmodule | |
1741 | ||
1742 | ||
1743 | ||
1744 | ||
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | // | |
1751 | // buff macro | |
1752 | // | |
1753 | // | |
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | module sii_ipcc_dpbuff_macro__minbuff_1__width_8 ( | |
1760 | din, | |
1761 | dout); | |
1762 | input [7:0] din; | |
1763 | output [7:0] dout; | |
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | ||
1770 | buff #(8) d0_0 ( | |
1771 | .in(din[7:0]), | |
1772 | .out(dout[7:0]) | |
1773 | ); | |
1774 | ||
1775 | ||
1776 | ||
1777 | ||
1778 | ||
1779 | ||
1780 | ||
1781 | ||
1782 | endmodule | |
1783 | ||
1784 | ||
1785 | ||
1786 | ||
1787 | ||
1788 | // | |
1789 | // buff macro | |
1790 | // | |
1791 | // | |
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | module sii_ipcc_dpbuff_macro__minbuff_1__width_64 ( | |
1798 | din, | |
1799 | dout); | |
1800 | input [63:0] din; | |
1801 | output [63:0] dout; | |
1802 | ||
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | buff #(64) d0_0 ( | |
1809 | .in(din[63:0]), | |
1810 | .out(dout[63:0]) | |
1811 | ); | |
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | ||
1820 | endmodule | |
1821 | ||
1822 | ||
1823 | ||
1824 | ||
1825 | ||
1826 | // | |
1827 | // invert macro | |
1828 | // | |
1829 | // | |
1830 | ||
1831 | ||
1832 | ||
1833 | ||
1834 | ||
1835 | module sii_ipcc_dpinv_macro__left_0__stack_4r__width_4 ( | |
1836 | din, | |
1837 | dout); | |
1838 | input [3:0] din; | |
1839 | output [3:0] dout; | |
1840 | ||
1841 | ||
1842 | ||
1843 | ||
1844 | ||
1845 | ||
1846 | inv #(4) d0_0 ( | |
1847 | .in(din[3:0]), | |
1848 | .out(dout[3:0]) | |
1849 | ); | |
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | ||
1856 | ||
1857 | ||
1858 | ||
1859 | endmodule | |
1860 | ||
1861 | ||
1862 | ||
1863 | ||
1864 | ||
1865 | // | |
1866 | // nor macro for ports = 2,3 | |
1867 | // | |
1868 | // | |
1869 | ||
1870 | ||
1871 | ||
1872 | ||
1873 | ||
1874 | module sii_ipcc_dpnor_macro__left_0__ports_3__stack_2r__width_1 ( | |
1875 | din0, | |
1876 | din1, | |
1877 | din2, | |
1878 | dout); | |
1879 | input [0:0] din0; | |
1880 | input [0:0] din1; | |
1881 | input [0:0] din2; | |
1882 | output [0:0] dout; | |
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | nor3 #(1) d0_0 ( | |
1890 | .in0(din0[0:0]), | |
1891 | .in1(din1[0:0]), | |
1892 | .in2(din2[0:0]), | |
1893 | .out(dout[0:0]) | |
1894 | ); | |
1895 | ||
1896 | ||
1897 | ||
1898 | ||
1899 | ||
1900 | ||
1901 | ||
1902 | endmodule | |
1903 | ||
1904 | ||
1905 | ||
1906 | ||
1907 | ||
1908 | // | |
1909 | // and macro for ports = 2,3,4 | |
1910 | // | |
1911 | // | |
1912 | ||
1913 | ||
1914 | ||
1915 | ||
1916 | ||
1917 | module sii_ipcc_dpand_macro__left_0__ports_2__stack_4r__width_1 ( | |
1918 | din0, | |
1919 | din1, | |
1920 | dout); | |
1921 | input [0:0] din0; | |
1922 | input [0:0] din1; | |
1923 | output [0:0] dout; | |
1924 | ||
1925 | ||
1926 | ||
1927 | ||
1928 | ||
1929 | ||
1930 | and2 #(1) d0_0 ( | |
1931 | .in0(din0[0:0]), | |
1932 | .in1(din1[0:0]), | |
1933 | .out(dout[0:0]) | |
1934 | ); | |
1935 | ||
1936 | ||
1937 | ||
1938 | ||
1939 | ||
1940 | ||
1941 | ||
1942 | ||
1943 | ||
1944 | endmodule | |
1945 | ||
1946 | ||
1947 | ||
1948 | ||
1949 | ||
1950 | // | |
1951 | // and macro for ports = 2,3,4 | |
1952 | // | |
1953 | // | |
1954 | ||
1955 | ||
1956 | ||
1957 | ||
1958 | ||
1959 | module sii_ipcc_dpand_macro__left_0__ports_3__stack_4r__width_1 ( | |
1960 | din0, | |
1961 | din1, | |
1962 | din2, | |
1963 | dout); | |
1964 | input [0:0] din0; | |
1965 | input [0:0] din1; | |
1966 | input [0:0] din2; | |
1967 | output [0:0] dout; | |
1968 | ||
1969 | ||
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | and3 #(1) d0_0 ( | |
1975 | .in0(din0[0:0]), | |
1976 | .in1(din1[0:0]), | |
1977 | .in2(din2[0:0]), | |
1978 | .out(dout[0:0]) | |
1979 | ); | |
1980 | ||
1981 | ||
1982 | ||
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | ||
1988 | ||
1989 | endmodule | |
1990 | ||
1991 | ||
1992 | ||
1993 | ||
1994 | ||
1995 | // | |
1996 | // and macro for ports = 2,3,4 | |
1997 | // | |
1998 | // | |
1999 | ||
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | module sii_ipcc_dpand_macro__left_0__ports_4__stack_4r__width_1 ( | |
2005 | din0, | |
2006 | din1, | |
2007 | din2, | |
2008 | din3, | |
2009 | dout); | |
2010 | input [0:0] din0; | |
2011 | input [0:0] din1; | |
2012 | input [0:0] din2; | |
2013 | input [0:0] din3; | |
2014 | output [0:0] dout; | |
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | ||
2021 | and4 #(1) d0_0 ( | |
2022 | .in0(din0[0:0]), | |
2023 | .in1(din1[0:0]), | |
2024 | .in2(din2[0:0]), | |
2025 | .in3(din3[0:0]), | |
2026 | .out(dout[0:0]) | |
2027 | ); | |
2028 | ||
2029 | ||
2030 | ||
2031 | ||
2032 | ||
2033 | ||
2034 | ||
2035 | ||
2036 | ||
2037 | endmodule | |
2038 | ||
2039 | ||
2040 | ||
2041 | ||
2042 | ||
2043 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2044 | // also for pass-gate with decoder | |
2045 | ||
2046 | ||
2047 | ||
2048 | ||
2049 | ||
2050 | // any PARAMS parms go into naming of macro | |
2051 | ||
2052 | module sii_ipcc_dpmux_macro__mux_pgnpe__ports_5__stack_72c__width_72 ( | |
2053 | din0, | |
2054 | sel0, | |
2055 | din1, | |
2056 | sel1, | |
2057 | din2, | |
2058 | sel2, | |
2059 | din3, | |
2060 | sel3, | |
2061 | din4, | |
2062 | sel4, | |
2063 | muxtst, | |
2064 | dout); | |
2065 | wire buffout0; | |
2066 | wire buffout1; | |
2067 | wire buffout2; | |
2068 | wire buffout3; | |
2069 | wire buffout4; | |
2070 | ||
2071 | input [71:0] din0; | |
2072 | input sel0; | |
2073 | input [71:0] din1; | |
2074 | input sel1; | |
2075 | input [71:0] din2; | |
2076 | input sel2; | |
2077 | input [71:0] din3; | |
2078 | input sel3; | |
2079 | input [71:0] din4; | |
2080 | input sel4; | |
2081 | input muxtst; | |
2082 | output [71:0] dout; | |
2083 | ||
2084 | ||
2085 | ||
2086 | ||
2087 | ||
2088 | cl_dp1_muxbuff5_8x c0_0 ( | |
2089 | .in0(sel0), | |
2090 | .in1(sel1), | |
2091 | .in2(sel2), | |
2092 | .in3(sel3), | |
2093 | .in4(sel4), | |
2094 | .out0(buffout0), | |
2095 | .out1(buffout1), | |
2096 | .out2(buffout2), | |
2097 | .out3(buffout3), | |
2098 | .out4(buffout4) | |
2099 | ); | |
2100 | mux5 #(72) d0_0 ( | |
2101 | .sel0(buffout0), | |
2102 | .sel1(buffout1), | |
2103 | .sel2(buffout2), | |
2104 | .sel3(buffout3), | |
2105 | .sel4(buffout4), | |
2106 | .in0(din0[71:0]), | |
2107 | .in1(din1[71:0]), | |
2108 | .in2(din2[71:0]), | |
2109 | .in3(din3[71:0]), | |
2110 | .in4(din4[71:0]), | |
2111 | .dout(dout[71:0]), | |
2112 | .muxtst(muxtst) | |
2113 | ); | |
2114 | ||
2115 | ||
2116 | ||
2117 | ||
2118 | ||
2119 | ||
2120 | ||
2121 | ||
2122 | ||
2123 | ||
2124 | ||
2125 | ||
2126 | ||
2127 | endmodule | |
2128 | ||
2129 | ||
2130 | ||
2131 | ||
2132 | ||
2133 | ||
2134 | // any PARAMS parms go into naming of macro | |
2135 | ||
2136 | module sii_ipcc_dpmsff_macro__stack_64c__width_64 ( | |
2137 | din, | |
2138 | clk, | |
2139 | en, | |
2140 | se, | |
2141 | scan_in, | |
2142 | siclk, | |
2143 | soclk, | |
2144 | pce_ov, | |
2145 | stop, | |
2146 | dout, | |
2147 | scan_out); | |
2148 | wire l1clk; | |
2149 | wire siclk_out; | |
2150 | wire soclk_out; | |
2151 | wire [62:0] so; | |
2152 | ||
2153 | input [63:0] din; | |
2154 | ||
2155 | ||
2156 | input clk; | |
2157 | input en; | |
2158 | input se; | |
2159 | input scan_in; | |
2160 | input siclk; | |
2161 | input soclk; | |
2162 | input pce_ov; | |
2163 | input stop; | |
2164 | ||
2165 | ||
2166 | ||
2167 | output [63:0] dout; | |
2168 | ||
2169 | ||
2170 | output scan_out; | |
2171 | ||
2172 | ||
2173 | ||
2174 | ||
2175 | cl_dp1_l1hdr_8x c0_0 ( | |
2176 | .l2clk(clk), | |
2177 | .pce(en), | |
2178 | .aclk(siclk), | |
2179 | .bclk(soclk), | |
2180 | .l1clk(l1clk), | |
2181 | .se(se), | |
2182 | .pce_ov(pce_ov), | |
2183 | .stop(stop), | |
2184 | .siclk_out(siclk_out), | |
2185 | .soclk_out(soclk_out) | |
2186 | ); | |
2187 | dff #(64) d0_0 ( | |
2188 | .l1clk(l1clk), | |
2189 | .siclk(siclk_out), | |
2190 | .soclk(soclk_out), | |
2191 | .d(din[63:0]), | |
2192 | .si({scan_in,so[62:0]}), | |
2193 | .so({so[62:0],scan_out}), | |
2194 | .q(dout[63:0]) | |
2195 | ); | |
2196 | ||
2197 | ||
2198 | ||
2199 | ||
2200 | ||
2201 | ||
2202 | ||
2203 | ||
2204 | ||
2205 | ||
2206 | ||
2207 | ||
2208 | ||
2209 | ||
2210 | ||
2211 | ||
2212 | ||
2213 | ||
2214 | ||
2215 | ||
2216 | endmodule | |
2217 | ||
2218 | ||
2219 | ||
2220 | ||
2221 | ||
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2227 | // also for pass-gate with decoder | |
2228 | ||
2229 | ||
2230 | ||
2231 | ||
2232 | ||
2233 | // any PARAMS parms go into naming of macro | |
2234 | ||
2235 | module sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_64c__width_64 ( | |
2236 | din0, | |
2237 | din1, | |
2238 | din2, | |
2239 | din3, | |
2240 | din4, | |
2241 | din5, | |
2242 | din6, | |
2243 | din7, | |
2244 | sel, | |
2245 | muxtst, | |
2246 | test, | |
2247 | dout); | |
2248 | wire psel0; | |
2249 | wire psel1; | |
2250 | wire psel2; | |
2251 | wire psel3; | |
2252 | wire psel4; | |
2253 | wire psel5; | |
2254 | wire psel6; | |
2255 | wire psel7; | |
2256 | ||
2257 | input [63:0] din0; | |
2258 | input [63:0] din1; | |
2259 | input [63:0] din2; | |
2260 | input [63:0] din3; | |
2261 | input [63:0] din4; | |
2262 | input [63:0] din5; | |
2263 | input [63:0] din6; | |
2264 | input [63:0] din7; | |
2265 | input [2:0] sel; | |
2266 | input muxtst; | |
2267 | input test; | |
2268 | output [63:0] dout; | |
2269 | ||
2270 | ||
2271 | ||
2272 | ||
2273 | ||
2274 | cl_dp1_pdec8_8x c0_0 ( | |
2275 | .sel0(sel[0]), | |
2276 | .sel1(sel[1]), | |
2277 | .sel2(sel[2]), | |
2278 | .psel0(psel0), | |
2279 | .psel1(psel1), | |
2280 | .psel2(psel2), | |
2281 | .psel3(psel3), | |
2282 | .psel4(psel4), | |
2283 | .psel5(psel5), | |
2284 | .psel6(psel6), | |
2285 | .psel7(psel7), | |
2286 | .test(test) | |
2287 | ); | |
2288 | ||
2289 | mux8 #(64) d0_0 ( | |
2290 | .sel0(psel0), | |
2291 | .sel1(psel1), | |
2292 | .sel2(psel2), | |
2293 | .sel3(psel3), | |
2294 | .sel4(psel4), | |
2295 | .sel5(psel5), | |
2296 | .sel6(psel6), | |
2297 | .sel7(psel7), | |
2298 | .in0(din0[63:0]), | |
2299 | .in1(din1[63:0]), | |
2300 | .in2(din2[63:0]), | |
2301 | .in3(din3[63:0]), | |
2302 | .in4(din4[63:0]), | |
2303 | .in5(din5[63:0]), | |
2304 | .in6(din6[63:0]), | |
2305 | .in7(din7[63:0]), | |
2306 | .dout(dout[63:0]), | |
2307 | .muxtst(muxtst) | |
2308 | ); | |
2309 | ||
2310 | ||
2311 | ||
2312 | ||
2313 | ||
2314 | ||
2315 | ||
2316 | ||
2317 | ||
2318 | ||
2319 | ||
2320 | ||
2321 | ||
2322 | endmodule | |
2323 | ||
2324 | ||
2325 | ||
2326 | ||
2327 | ||
2328 | ||
2329 | // any PARAMS parms go into naming of macro | |
2330 | ||
2331 | module sii_ipcc_dpmsff_macro__stack_14c__width_14 ( | |
2332 | din, | |
2333 | clk, | |
2334 | en, | |
2335 | se, | |
2336 | scan_in, | |
2337 | siclk, | |
2338 | soclk, | |
2339 | pce_ov, | |
2340 | stop, | |
2341 | dout, | |
2342 | scan_out); | |
2343 | wire l1clk; | |
2344 | wire siclk_out; | |
2345 | wire soclk_out; | |
2346 | wire [12:0] so; | |
2347 | ||
2348 | input [13:0] din; | |
2349 | ||
2350 | ||
2351 | input clk; | |
2352 | input en; | |
2353 | input se; | |
2354 | input scan_in; | |
2355 | input siclk; | |
2356 | input soclk; | |
2357 | input pce_ov; | |
2358 | input stop; | |
2359 | ||
2360 | ||
2361 | ||
2362 | output [13:0] dout; | |
2363 | ||
2364 | ||
2365 | output scan_out; | |
2366 | ||
2367 | ||
2368 | ||
2369 | ||
2370 | cl_dp1_l1hdr_8x c0_0 ( | |
2371 | .l2clk(clk), | |
2372 | .pce(en), | |
2373 | .aclk(siclk), | |
2374 | .bclk(soclk), | |
2375 | .l1clk(l1clk), | |
2376 | .se(se), | |
2377 | .pce_ov(pce_ov), | |
2378 | .stop(stop), | |
2379 | .siclk_out(siclk_out), | |
2380 | .soclk_out(soclk_out) | |
2381 | ); | |
2382 | dff #(14) d0_0 ( | |
2383 | .l1clk(l1clk), | |
2384 | .siclk(siclk_out), | |
2385 | .soclk(soclk_out), | |
2386 | .d(din[13:0]), | |
2387 | .si({scan_in,so[12:0]}), | |
2388 | .so({so[12:0],scan_out}), | |
2389 | .q(dout[13:0]) | |
2390 | ); | |
2391 | ||
2392 | ||
2393 | ||
2394 | ||
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | ||
2402 | ||
2403 | ||
2404 | ||
2405 | ||
2406 | ||
2407 | ||
2408 | ||
2409 | ||
2410 | ||
2411 | endmodule | |
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | ||
2422 | ||
2423 | ||
2424 | ||
2425 | // any PARAMS parms go into naming of macro | |
2426 | ||
2427 | module sii_ipcc_dpmsff_macro__stack_8c__width_8 ( | |
2428 | din, | |
2429 | clk, | |
2430 | en, | |
2431 | se, | |
2432 | scan_in, | |
2433 | siclk, | |
2434 | soclk, | |
2435 | pce_ov, | |
2436 | stop, | |
2437 | dout, | |
2438 | scan_out); | |
2439 | wire l1clk; | |
2440 | wire siclk_out; | |
2441 | wire soclk_out; | |
2442 | wire [6:0] so; | |
2443 | ||
2444 | input [7:0] din; | |
2445 | ||
2446 | ||
2447 | input clk; | |
2448 | input en; | |
2449 | input se; | |
2450 | input scan_in; | |
2451 | input siclk; | |
2452 | input soclk; | |
2453 | input pce_ov; | |
2454 | input stop; | |
2455 | ||
2456 | ||
2457 | ||
2458 | output [7:0] dout; | |
2459 | ||
2460 | ||
2461 | output scan_out; | |
2462 | ||
2463 | ||
2464 | ||
2465 | ||
2466 | cl_dp1_l1hdr_8x c0_0 ( | |
2467 | .l2clk(clk), | |
2468 | .pce(en), | |
2469 | .aclk(siclk), | |
2470 | .bclk(soclk), | |
2471 | .l1clk(l1clk), | |
2472 | .se(se), | |
2473 | .pce_ov(pce_ov), | |
2474 | .stop(stop), | |
2475 | .siclk_out(siclk_out), | |
2476 | .soclk_out(soclk_out) | |
2477 | ); | |
2478 | dff #(8) d0_0 ( | |
2479 | .l1clk(l1clk), | |
2480 | .siclk(siclk_out), | |
2481 | .soclk(soclk_out), | |
2482 | .d(din[7:0]), | |
2483 | .si({scan_in,so[6:0]}), | |
2484 | .so({so[6:0],scan_out}), | |
2485 | .q(dout[7:0]) | |
2486 | ); | |
2487 | ||
2488 | ||
2489 | ||
2490 | ||
2491 | ||
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | ||
2497 | ||
2498 | ||
2499 | ||
2500 | ||
2501 | ||
2502 | ||
2503 | ||
2504 | ||
2505 | ||
2506 | ||
2507 | endmodule | |
2508 | ||
2509 | ||
2510 | ||
2511 | ||
2512 | ||
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | // | |
2518 | // buff macro | |
2519 | // | |
2520 | // | |
2521 | ||
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | module sii_ipcc_dpbuff_macro__minbuff_1__stack_8r__width_8 ( | |
2527 | din, | |
2528 | dout); | |
2529 | input [7:0] din; | |
2530 | output [7:0] dout; | |
2531 | ||
2532 | ||
2533 | ||
2534 | ||
2535 | ||
2536 | ||
2537 | buff #(8) d0_0 ( | |
2538 | .in(din[7:0]), | |
2539 | .out(dout[7:0]) | |
2540 | ); | |
2541 | ||
2542 | ||
2543 | ||
2544 | ||
2545 | ||
2546 | ||
2547 | ||
2548 | ||
2549 | endmodule | |
2550 | ||
2551 | ||
2552 | ||
2553 | ||
2554 | ||
2555 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2556 | // also for pass-gate with decoder | |
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | // any PARAMS parms go into naming of macro | |
2563 | ||
2564 | module sii_ipcc_dpmux_macro__mux_pgpe__ports_2__stack_14c__width_14 ( | |
2565 | din0, | |
2566 | din1, | |
2567 | sel0, | |
2568 | dout); | |
2569 | wire psel0_unused; | |
2570 | wire psel1; | |
2571 | ||
2572 | input [13:0] din0; | |
2573 | input [13:0] din1; | |
2574 | input sel0; | |
2575 | output [13:0] dout; | |
2576 | ||
2577 | ||
2578 | ||
2579 | ||
2580 | ||
2581 | cl_dp1_penc2_8x c0_0 ( | |
2582 | .sel0(sel0), | |
2583 | .psel0(psel0_unused), | |
2584 | .psel1(psel1) | |
2585 | ); | |
2586 | ||
2587 | mux2e #(14) d0_0 ( | |
2588 | .sel(psel1), | |
2589 | .in0(din0[13:0]), | |
2590 | .in1(din1[13:0]), | |
2591 | .dout(dout[13:0]) | |
2592 | ); | |
2593 | ||
2594 | ||
2595 | ||
2596 | ||
2597 | ||
2598 | ||
2599 | ||
2600 | ||
2601 | ||
2602 | ||
2603 | ||
2604 | ||
2605 | ||
2606 | endmodule | |
2607 | ||
2608 | ||
2609 | // | |
2610 | // xor macro for ports = 2,3 | |
2611 | // | |
2612 | // | |
2613 | ||
2614 | ||
2615 | ||
2616 | ||
2617 | ||
2618 | module sii_ipcc_dpxor_macro__ports_2__stack_4r__width_4 ( | |
2619 | din0, | |
2620 | din1, | |
2621 | dout); | |
2622 | input [3:0] din0; | |
2623 | input [3:0] din1; | |
2624 | output [3:0] dout; | |
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | ||
2630 | xor2 #(4) d0_0 ( | |
2631 | .in0(din0[3:0]), | |
2632 | .in1(din1[3:0]), | |
2633 | .out(dout[3:0]) | |
2634 | ); | |
2635 | ||
2636 | ||
2637 | ||
2638 | ||
2639 | ||
2640 | ||
2641 | ||
2642 | ||
2643 | endmodule | |
2644 | ||
2645 | ||
2646 | ||
2647 | ||
2648 | ||
2649 | // | |
2650 | // xor macro for ports = 2,3 | |
2651 | // | |
2652 | // | |
2653 | ||
2654 | ||
2655 | ||
2656 | ||
2657 | ||
2658 | module sii_ipcc_dpxor_macro__ports_2__stack_10r__width_9 ( | |
2659 | din0, | |
2660 | din1, | |
2661 | dout); | |
2662 | input [8:0] din0; | |
2663 | input [8:0] din1; | |
2664 | output [8:0] dout; | |
2665 | ||
2666 | ||
2667 | ||
2668 | ||
2669 | ||
2670 | xor2 #(9) d0_0 ( | |
2671 | .in0(din0[8:0]), | |
2672 | .in1(din1[8:0]), | |
2673 | .out(dout[8:0]) | |
2674 | ); | |
2675 | ||
2676 | ||
2677 | ||
2678 | ||
2679 | ||
2680 | ||
2681 | ||
2682 | ||
2683 | endmodule | |
2684 | ||
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | // | |
2690 | // xor macro for ports = 2,3 | |
2691 | // | |
2692 | // | |
2693 | ||
2694 | ||
2695 | ||
2696 | ||
2697 | ||
2698 | module sii_ipcc_dpxor_macro__ports_2__stack_2r__width_2 ( | |
2699 | din0, | |
2700 | din1, | |
2701 | dout); | |
2702 | input [1:0] din0; | |
2703 | input [1:0] din1; | |
2704 | output [1:0] dout; | |
2705 | ||
2706 | ||
2707 | ||
2708 | ||
2709 | ||
2710 | xor2 #(2) d0_0 ( | |
2711 | .in0(din0[1:0]), | |
2712 | .in1(din1[1:0]), | |
2713 | .out(dout[1:0]) | |
2714 | ); | |
2715 | ||
2716 | ||
2717 | ||
2718 | ||
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | endmodule | |
2724 | ||
2725 | ||
2726 | ||
2727 | ||
2728 | ||
2729 | // | |
2730 | // xor macro for ports = 2,3 | |
2731 | // | |
2732 | // | |
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | ||
2738 | module sii_ipcc_dpxor_macro__ports_3__stack_2r__width_1 ( | |
2739 | din0, | |
2740 | din1, | |
2741 | din2, | |
2742 | dout); | |
2743 | input [0:0] din0; | |
2744 | input [0:0] din1; | |
2745 | input [0:0] din2; | |
2746 | output [0:0] dout; | |
2747 | ||
2748 | ||
2749 | ||
2750 | ||
2751 | ||
2752 | xor3 #(1) d0_0 ( | |
2753 | .in0(din0[0:0]), | |
2754 | .in1(din1[0:0]), | |
2755 | .in2(din2[0:0]), | |
2756 | .out(dout[0:0]) | |
2757 | ); | |
2758 | ||
2759 | ||
2760 | ||
2761 | ||
2762 | ||
2763 | ||
2764 | ||
2765 | ||
2766 | endmodule | |
2767 | ||
2768 | ||
2769 | ||
2770 | ||
2771 | ||
2772 | // | |
2773 | // xor macro for ports = 2,3 | |
2774 | // | |
2775 | // | |
2776 | ||
2777 | ||
2778 | ||
2779 | ||
2780 | ||
2781 | module sii_ipcc_dpxor_macro__ports_2__stack_8r__width_7 ( | |
2782 | din0, | |
2783 | din1, | |
2784 | dout); | |
2785 | input [6:0] din0; | |
2786 | input [6:0] din1; | |
2787 | output [6:0] dout; | |
2788 | ||
2789 | ||
2790 | ||
2791 | ||
2792 | ||
2793 | xor2 #(7) d0_0 ( | |
2794 | .in0(din0[6:0]), | |
2795 | .in1(din1[6:0]), | |
2796 | .out(dout[6:0]) | |
2797 | ); | |
2798 | ||
2799 | ||
2800 | ||
2801 | ||
2802 | ||
2803 | ||
2804 | ||
2805 | ||
2806 | endmodule | |
2807 | ||
2808 | ||
2809 | ||
2810 | ||
2811 | ||
2812 | // | |
2813 | // xor macro for ports = 2,3 | |
2814 | // | |
2815 | // | |
2816 | ||
2817 | ||
2818 | ||
2819 | ||
2820 | ||
2821 | module sii_ipcc_dpxor_macro__ports_2__stack_2r__width_1 ( | |
2822 | din0, | |
2823 | din1, | |
2824 | dout); | |
2825 | input [0:0] din0; | |
2826 | input [0:0] din1; | |
2827 | output [0:0] dout; | |
2828 | ||
2829 | ||
2830 | ||
2831 | ||
2832 | ||
2833 | xor2 #(1) d0_0 ( | |
2834 | .in0(din0[0:0]), | |
2835 | .in1(din1[0:0]), | |
2836 | .out(dout[0:0]) | |
2837 | ); | |
2838 | ||
2839 | ||
2840 | ||
2841 | ||
2842 | ||
2843 | ||
2844 | ||
2845 | ||
2846 | endmodule | |
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | // | |
2853 | // xor macro for ports = 2,3 | |
2854 | // | |
2855 | // | |
2856 | ||
2857 | ||
2858 | ||
2859 | ||
2860 | ||
2861 | module sii_ipcc_dpxor_macro__ports_2__stack_4r__width_3 ( | |
2862 | din0, | |
2863 | din1, | |
2864 | dout); | |
2865 | input [2:0] din0; | |
2866 | input [2:0] din1; | |
2867 | output [2:0] dout; | |
2868 | ||
2869 | ||
2870 | ||
2871 | ||
2872 | ||
2873 | xor2 #(3) d0_0 ( | |
2874 | .in0(din0[2:0]), | |
2875 | .in1(din1[2:0]), | |
2876 | .out(dout[2:0]) | |
2877 | ); | |
2878 | ||
2879 | ||
2880 | ||
2881 | ||
2882 | ||
2883 | ||
2884 | ||
2885 | ||
2886 | endmodule | |
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | // | |
2893 | // xor macro for ports = 2,3 | |
2894 | // | |
2895 | // | |
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | module sii_ipcc_dpxor_macro__ports_2__stack_8r__width_4 ( | |
2902 | din0, | |
2903 | din1, | |
2904 | dout); | |
2905 | input [3:0] din0; | |
2906 | input [3:0] din1; | |
2907 | output [3:0] dout; | |
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | xor2 #(4) d0_0 ( | |
2914 | .in0(din0[3:0]), | |
2915 | .in1(din1[3:0]), | |
2916 | .out(dout[3:0]) | |
2917 | ); | |
2918 | ||
2919 | ||
2920 | ||
2921 | ||
2922 | ||
2923 | ||
2924 | ||
2925 | ||
2926 | endmodule | |
2927 | ||
2928 | ||
2929 | ||
2930 | ||
2931 | ||
2932 | // | |
2933 | // xor macro for ports = 2,3 | |
2934 | // | |
2935 | // | |
2936 | ||
2937 | ||
2938 | ||
2939 | ||
2940 | ||
2941 | module sii_ipcc_dpxor_macro__ports_2__stack_4r__width_2 ( | |
2942 | din0, | |
2943 | din1, | |
2944 | dout); | |
2945 | input [1:0] din0; | |
2946 | input [1:0] din1; | |
2947 | output [1:0] dout; | |
2948 | ||
2949 | ||
2950 | ||
2951 | ||
2952 | ||
2953 | xor2 #(2) d0_0 ( | |
2954 | .in0(din0[1:0]), | |
2955 | .in1(din1[1:0]), | |
2956 | .out(dout[1:0]) | |
2957 | ); | |
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | ||
2963 | ||
2964 | ||
2965 | ||
2966 | endmodule | |
2967 | ||
2968 | ||
2969 | ||
2970 | ||
2971 | ||
2972 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2973 | // also for pass-gate with decoder | |
2974 | ||
2975 | ||
2976 | ||
2977 | ||
2978 | ||
2979 | // any PARAMS parms go into naming of macro | |
2980 | ||
2981 | module sii_ipcc_dpmux_macro__mux_pgdec__ports_8__stack_14c__width_14 ( | |
2982 | din0, | |
2983 | din1, | |
2984 | din2, | |
2985 | din3, | |
2986 | din4, | |
2987 | din5, | |
2988 | din6, | |
2989 | din7, | |
2990 | sel, | |
2991 | muxtst, | |
2992 | test, | |
2993 | dout); | |
2994 | wire psel0; | |
2995 | wire psel1; | |
2996 | wire psel2; | |
2997 | wire psel3; | |
2998 | wire psel4; | |
2999 | wire psel5; | |
3000 | wire psel6; | |
3001 | wire psel7; | |
3002 | ||
3003 | input [13:0] din0; | |
3004 | input [13:0] din1; | |
3005 | input [13:0] din2; | |
3006 | input [13:0] din3; | |
3007 | input [13:0] din4; | |
3008 | input [13:0] din5; | |
3009 | input [13:0] din6; | |
3010 | input [13:0] din7; | |
3011 | input [2:0] sel; | |
3012 | input muxtst; | |
3013 | input test; | |
3014 | output [13:0] dout; | |
3015 | ||
3016 | ||
3017 | ||
3018 | ||
3019 | ||
3020 | cl_dp1_pdec8_8x c0_0 ( | |
3021 | .sel0(sel[0]), | |
3022 | .sel1(sel[1]), | |
3023 | .sel2(sel[2]), | |
3024 | .psel0(psel0), | |
3025 | .psel1(psel1), | |
3026 | .psel2(psel2), | |
3027 | .psel3(psel3), | |
3028 | .psel4(psel4), | |
3029 | .psel5(psel5), | |
3030 | .psel6(psel6), | |
3031 | .psel7(psel7), | |
3032 | .test(test) | |
3033 | ); | |
3034 | ||
3035 | mux8 #(14) d0_0 ( | |
3036 | .sel0(psel0), | |
3037 | .sel1(psel1), | |
3038 | .sel2(psel2), | |
3039 | .sel3(psel3), | |
3040 | .sel4(psel4), | |
3041 | .sel5(psel5), | |
3042 | .sel6(psel6), | |
3043 | .sel7(psel7), | |
3044 | .in0(din0[13:0]), | |
3045 | .in1(din1[13:0]), | |
3046 | .in2(din2[13:0]), | |
3047 | .in3(din3[13:0]), | |
3048 | .in4(din4[13:0]), | |
3049 | .in5(din5[13:0]), | |
3050 | .in6(din6[13:0]), | |
3051 | .in7(din7[13:0]), | |
3052 | .dout(dout[13:0]), | |
3053 | .muxtst(muxtst) | |
3054 | ); | |
3055 | ||
3056 | ||
3057 | ||
3058 | ||
3059 | ||
3060 | ||
3061 | ||
3062 | ||
3063 | ||
3064 | ||
3065 | ||
3066 | ||
3067 | ||
3068 | endmodule | |
3069 | ||
3070 | ||
3071 | ||
3072 | ||
3073 | ||
3074 | ||
3075 | // any PARAMS parms go into naming of macro | |
3076 | ||
3077 | module sii_ipcc_dpmsff_macro__stack_18c__width_18 ( | |
3078 | din, | |
3079 | clk, | |
3080 | en, | |
3081 | se, | |
3082 | scan_in, | |
3083 | siclk, | |
3084 | soclk, | |
3085 | pce_ov, | |
3086 | stop, | |
3087 | dout, | |
3088 | scan_out); | |
3089 | wire l1clk; | |
3090 | wire siclk_out; | |
3091 | wire soclk_out; | |
3092 | wire [16:0] so; | |
3093 | ||
3094 | input [17:0] din; | |
3095 | ||
3096 | ||
3097 | input clk; | |
3098 | input en; | |
3099 | input se; | |
3100 | input scan_in; | |
3101 | input siclk; | |
3102 | input soclk; | |
3103 | input pce_ov; | |
3104 | input stop; | |
3105 | ||
3106 | ||
3107 | ||
3108 | output [17:0] dout; | |
3109 | ||
3110 | ||
3111 | output scan_out; | |
3112 | ||
3113 | ||
3114 | ||
3115 | ||
3116 | cl_dp1_l1hdr_8x c0_0 ( | |
3117 | .l2clk(clk), | |
3118 | .pce(en), | |
3119 | .aclk(siclk), | |
3120 | .bclk(soclk), | |
3121 | .l1clk(l1clk), | |
3122 | .se(se), | |
3123 | .pce_ov(pce_ov), | |
3124 | .stop(stop), | |
3125 | .siclk_out(siclk_out), | |
3126 | .soclk_out(soclk_out) | |
3127 | ); | |
3128 | dff #(18) d0_0 ( | |
3129 | .l1clk(l1clk), | |
3130 | .siclk(siclk_out), | |
3131 | .soclk(soclk_out), | |
3132 | .d(din[17:0]), | |
3133 | .si({scan_in,so[16:0]}), | |
3134 | .so({so[16:0],scan_out}), | |
3135 | .q(dout[17:0]) | |
3136 | ); | |
3137 | ||
3138 | ||
3139 | ||
3140 | ||
3141 | ||
3142 | ||
3143 | ||
3144 | ||
3145 | ||
3146 | ||
3147 | ||
3148 | ||
3149 | ||
3150 | ||
3151 | ||
3152 | ||
3153 | ||
3154 | ||
3155 | ||
3156 | ||
3157 | endmodule | |
3158 | ||
3159 | ||
3160 | ||
3161 | ||
3162 | ||
3163 | ||
3164 | ||
3165 | ||
3166 | ||
3167 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3168 | // also for pass-gate with decoder | |
3169 | ||
3170 | ||
3171 | ||
3172 | ||
3173 | ||
3174 | // any PARAMS parms go into naming of macro | |
3175 | ||
3176 | module sii_ipcc_dpmux_macro__mux_pgdec__ports_4__stack_18c__width_18 ( | |
3177 | din0, | |
3178 | din1, | |
3179 | din2, | |
3180 | din3, | |
3181 | sel, | |
3182 | muxtst, | |
3183 | test, | |
3184 | dout); | |
3185 | wire psel0; | |
3186 | wire psel1; | |
3187 | wire psel2; | |
3188 | wire psel3; | |
3189 | ||
3190 | input [17:0] din0; | |
3191 | input [17:0] din1; | |
3192 | input [17:0] din2; | |
3193 | input [17:0] din3; | |
3194 | input [1:0] sel; | |
3195 | input muxtst; | |
3196 | input test; | |
3197 | output [17:0] dout; | |
3198 | ||
3199 | ||
3200 | ||
3201 | ||
3202 | ||
3203 | cl_dp1_pdec4_8x c0_0 ( | |
3204 | .sel0(sel[0]), | |
3205 | .sel1(sel[1]), | |
3206 | .psel0(psel0), | |
3207 | .psel1(psel1), | |
3208 | .psel2(psel2), | |
3209 | .psel3(psel3), | |
3210 | .test(test) | |
3211 | ); | |
3212 | ||
3213 | mux4 #(18) d0_0 ( | |
3214 | .sel0(psel0), | |
3215 | .sel1(psel1), | |
3216 | .sel2(psel2), | |
3217 | .sel3(psel3), | |
3218 | .in0(din0[17:0]), | |
3219 | .in1(din1[17:0]), | |
3220 | .in2(din2[17:0]), | |
3221 | .in3(din3[17:0]), | |
3222 | .dout(dout[17:0]), | |
3223 | .muxtst(muxtst) | |
3224 | ); | |
3225 | ||
3226 | ||
3227 | ||
3228 | ||
3229 | ||
3230 | ||
3231 | ||
3232 | ||
3233 | ||
3234 | ||
3235 | ||
3236 | ||
3237 | ||
3238 | endmodule | |
3239 |