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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sio_mb0_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sio_mb0_ctl ( | |
36 | sio_mb0_run, | |
37 | sio_mb0_old_addr, | |
38 | sio_mb0_wdata, | |
39 | sio_mb0_sel_l1, | |
40 | sio_mb0_sel_l2, | |
41 | sio_mb0_old0x_wr_en, | |
42 | sio_mb0_old0x_rd_en, | |
43 | sio_mb0_old1x_wr_en, | |
44 | sio_mb0_old1x_rd_en, | |
45 | sio_mb0_old2x_wr_en, | |
46 | sio_mb0_old2x_rd_en, | |
47 | sio_mb0_old3x_wr_en, | |
48 | sio_mb0_old3x_rd_en, | |
49 | sio_mb0_old4x_wr_en, | |
50 | sio_mb0_old4x_rd_en, | |
51 | sio_mb0_old5x_wr_en, | |
52 | sio_mb0_old5x_rd_en, | |
53 | sio_mb0_old6x_wr_en, | |
54 | sio_mb0_old6x_rd_en, | |
55 | sio_mb0_old7x_wr_en, | |
56 | sio_mb0_old7x_rd_en, | |
57 | sio_mb0_done, | |
58 | sio_mb0_fail, | |
59 | scan_out, | |
60 | l2clk, | |
61 | tcu_scan_en, | |
62 | scan_in, | |
63 | tcu_aclk, | |
64 | tcu_bclk, | |
65 | tcu_pce_ov, | |
66 | tcu_clk_stop, | |
67 | tcu_sio_mb0_start, | |
68 | sio_mb0_bisi_mode, | |
69 | sio_mb0_user_mode, | |
70 | read_data_top, | |
71 | read_data_bot); | |
72 | wire se; | |
73 | wire siclk; | |
74 | wire soclk; | |
75 | wire pce_ov; | |
76 | wire stop; | |
77 | wire l1clk; | |
78 | wire config_reg_scanin; | |
79 | wire config_reg_scanout; | |
80 | wire [7:0] config_in; | |
81 | wire [7:0] config_out; | |
82 | wire start_transition; | |
83 | wire reset_engine; | |
84 | wire mbist_user_loop_mode; | |
85 | wire mbist_done; | |
86 | wire run; | |
87 | wire bisi; | |
88 | wire user_mode; | |
89 | wire user_data_mode; | |
90 | wire user_addr_mode; | |
91 | wire user_loop_mode; | |
92 | wire ten_n_mode; | |
93 | wire mbist_user_data_mode; | |
94 | wire mbist_user_addr_mode; | |
95 | wire mbist_ten_n_mode; | |
96 | wire user_data_reg_scanin; | |
97 | wire user_data_reg_scanout; | |
98 | wire [7:0] user_data_in; | |
99 | wire [7:0] user_data_out; | |
100 | wire user_start_addr_reg_scanin; | |
101 | wire user_start_addr_reg_scanout; | |
102 | wire [4:0] user_start_addr_in; | |
103 | wire [4:0] user_start_addr; | |
104 | wire user_stop_addr_reg_scanin; | |
105 | wire user_stop_addr_reg_scanout; | |
106 | wire [4:0] user_stop_addr_in; | |
107 | wire [4:0] user_stop_addr; | |
108 | wire user_incr_addr_reg_scanin; | |
109 | wire user_incr_addr_reg_scanout; | |
110 | wire [4:0] user_incr_addr_in; | |
111 | wire [4:0] user_incr_addr; | |
112 | wire user_array_sel_reg_scanin; | |
113 | wire user_array_sel_reg_scanout; | |
114 | wire [2:0] user_array_sel_in; | |
115 | wire [2:0] user_array_sel; | |
116 | wire user_bisi_wr_reg_scanin; | |
117 | wire user_bisi_wr_reg_scanout; | |
118 | wire user_bisi_wr_mode_in; | |
119 | wire user_bisi_wr_mode; | |
120 | wire user_bisi_rd_reg_scanin; | |
121 | wire user_bisi_rd_reg_scanout; | |
122 | wire user_bisi_rd_mode_in; | |
123 | wire user_bisi_rd_mode; | |
124 | wire mbist_user_bisi_wr_mode; | |
125 | wire mbist_user_bisi_wr_rd_mode; | |
126 | wire start_transition_reg_scanin; | |
127 | wire start_transition_reg_scanout; | |
128 | wire start_transition_piped; | |
129 | wire run_reg_scanin; | |
130 | wire run_reg_scanout; | |
131 | wire run1_reg_scanin; | |
132 | wire run1_reg_scanout; | |
133 | wire run1_in; | |
134 | wire run1_out; | |
135 | wire run2_reg_scanin; | |
136 | wire run2_reg_scanout; | |
137 | wire run2_in; | |
138 | wire run2_out; | |
139 | wire run_piped3; | |
140 | wire msb; | |
141 | wire addr_reg_scanin; | |
142 | wire addr_reg_scanout; | |
143 | wire [4:0] mbist_address; | |
144 | wire wdata_reg_scanin; | |
145 | wire wdata_reg_scanout; | |
146 | wire [7:0] mbist_wdata; | |
147 | wire rd_wr_en_reg0_scanin; | |
148 | wire rd_wr_en_reg0_scanout; | |
149 | wire mbist_old0x_wr_en; | |
150 | wire mbist_old0x_rd_en; | |
151 | wire rd_wr_en_reg1_scanin; | |
152 | wire rd_wr_en_reg1_scanout; | |
153 | wire mbist_old1x_wr_en; | |
154 | wire mbist_old1x_rd_en; | |
155 | wire rd_wr_en_reg2_scanin; | |
156 | wire rd_wr_en_reg2_scanout; | |
157 | wire mbist_old2x_wr_en; | |
158 | wire mbist_old2x_rd_en; | |
159 | wire rd_wr_en_reg3_scanin; | |
160 | wire rd_wr_en_reg3_scanout; | |
161 | wire mbist_old3x_wr_en; | |
162 | wire mbist_old3x_rd_en; | |
163 | wire rd_wr_en_reg4_scanin; | |
164 | wire rd_wr_en_reg4_scanout; | |
165 | wire mbist_old4x_wr_en; | |
166 | wire mbist_old4x_rd_en; | |
167 | wire rd_wr_en_reg5_scanin; | |
168 | wire rd_wr_en_reg5_scanout; | |
169 | wire mbist_old5x_wr_en; | |
170 | wire mbist_old5x_rd_en; | |
171 | wire rd_wr_en_reg6_scanin; | |
172 | wire rd_wr_en_reg6_scanout; | |
173 | wire mbist_old6x_wr_en; | |
174 | wire mbist_old6x_rd_en; | |
175 | wire rd_wr_en_reg7_scanin; | |
176 | wire rd_wr_en_reg7_scanout; | |
177 | wire mbist_old7x_wr_en; | |
178 | wire mbist_old7x_rd_en; | |
179 | wire sio_mb0_fail_reg_scanin; | |
180 | wire sio_mb0_fail_reg_scanout; | |
181 | wire fail; | |
182 | wire sio_mb0_done_reg_scanin; | |
183 | wire sio_mb0_done_reg_scanout; | |
184 | wire [67:0] read_data; | |
185 | wire sio_mb0_sel_l3; | |
186 | wire read_data_pipe_reg_scanin; | |
187 | wire read_data_pipe_reg_scanout; | |
188 | wire [67:0] read_data_pipe; | |
189 | wire control_reg_scanin; | |
190 | wire control_reg_scanout; | |
191 | wire [19:0] control_in; | |
192 | wire [19:0] control_out; | |
193 | wire bisi_wr_rd; | |
194 | wire [2:0] array_sel; | |
195 | wire [1:0] data_control; | |
196 | wire address_mix; | |
197 | wire [3:0] march_element; | |
198 | wire [4:0] array_address; | |
199 | wire upaddress_march; | |
200 | wire [2:0] read_write_control; | |
201 | wire five_cycle_march; | |
202 | wire one_cycle_march; | |
203 | wire increment_addr; | |
204 | wire [4:0] start_addr; | |
205 | wire [4:0] next_array_address; | |
206 | wire next_upaddr_march; | |
207 | wire next_downaddr_march; | |
208 | wire [4:0] stop_addr; | |
209 | wire [5:0] overflow_addr; | |
210 | wire [4:0] incr_addr; | |
211 | wire overflow; | |
212 | wire [5:0] compare_addr; | |
213 | wire [4:0] add; | |
214 | wire [4:0] adj_address; | |
215 | wire increment_march_elem; | |
216 | wire [2:0] next_array_sel; | |
217 | wire [1:0] next_data_control; | |
218 | wire next_address_mix; | |
219 | wire [3:0] next_march_element; | |
220 | wire array_write; | |
221 | wire array_read; | |
222 | wire true_data; | |
223 | wire [7:0] data_pattern; | |
224 | wire done_counter_reg_scanin; | |
225 | wire done_counter_reg_scanout; | |
226 | wire [2:0] done_counter_in; | |
227 | wire [2:0] done_counter_out; | |
228 | wire old0x_sel; | |
229 | wire old1x_sel; | |
230 | wire old2x_sel; | |
231 | wire old3x_sel; | |
232 | wire old4x_sel; | |
233 | wire old5x_sel; | |
234 | wire old6x_sel; | |
235 | wire old7x_sel; | |
236 | wire data_pipe_reg1_scanin; | |
237 | wire data_pipe_reg1_scanout; | |
238 | wire [7:0] data_pipe_reg1_in; | |
239 | wire [7:0] data_pipe_out1; | |
240 | wire data_pipe_reg2_scanin; | |
241 | wire data_pipe_reg2_scanout; | |
242 | wire [7:0] data_pipe_reg2_in; | |
243 | wire [7:0] data_pipe_out2; | |
244 | wire data_pipe_reg3_scanin; | |
245 | wire data_pipe_reg3_scanout; | |
246 | wire [7:0] data_pipe_reg3_in; | |
247 | wire [7:0] data_pipe_out3; | |
248 | wire data_pipe_reg4_scanin; | |
249 | wire data_pipe_reg4_scanout; | |
250 | wire [7:0] data_pipe_reg4_in; | |
251 | wire [7:0] data_pipe_out4; | |
252 | wire [7:0] sio_old_piped_data; | |
253 | wire ren_pipe_reg1_scanin; | |
254 | wire ren_pipe_reg1_scanout; | |
255 | wire ren_pipe_reg1_in; | |
256 | wire ren_pipe_out1; | |
257 | wire ren_pipe_reg2_scanin; | |
258 | wire ren_pipe_reg2_scanout; | |
259 | wire ren_pipe_reg2_in; | |
260 | wire ren_pipe_out2; | |
261 | wire ren_pipe_reg3_scanin; | |
262 | wire ren_pipe_reg3_scanout; | |
263 | wire ren_pipe_reg3_in; | |
264 | wire ren_pipe_out3; | |
265 | wire ren_pipe_reg4_scanin; | |
266 | wire ren_pipe_reg4_scanout; | |
267 | wire ren_pipe_reg4_in; | |
268 | wire ren_pipe_out4; | |
269 | wire ren_pipe_reg5_scanin; | |
270 | wire ren_pipe_reg5_scanout; | |
271 | wire ren_pipe_reg5_in; | |
272 | wire ren_pipe_out5; | |
273 | wire sio_old_piped_ren; | |
274 | wire ary_sel_pipe_reg1_scanin; | |
275 | wire ary_sel_pipe_reg1_scanout; | |
276 | wire [2:0] ary_sel_pipe_reg1_in; | |
277 | wire [2:0] ary_sel_pipe_out1; | |
278 | wire ary_sel_pipe_reg2_scanin; | |
279 | wire ary_sel_pipe_reg2_scanout; | |
280 | wire [2:0] ary_sel_pipe_reg2_in; | |
281 | wire [2:0] ary_sel_pipe_out2; | |
282 | wire ary_sel_pipe_reg3_scanin; | |
283 | wire ary_sel_pipe_reg3_scanout; | |
284 | wire [2:0] ary_sel_pipe_reg3_in; | |
285 | wire [2:0] ary_sel_pipe_out3; | |
286 | wire ary_sel_pipe_reg4_scanin; | |
287 | wire ary_sel_pipe_reg4_scanout; | |
288 | wire [2:0] ary_sel_pipe_reg4_in; | |
289 | wire [2:0] ary_sel_pipe_out4; | |
290 | wire ary_sel_pipe_reg5_scanin; | |
291 | wire ary_sel_pipe_reg5_scanout; | |
292 | wire [2:0] ary_sel_pipe_reg5_in; | |
293 | wire [2:0] ary_sel_pipe_out5; | |
294 | wire [2:0] piped_array_sel; | |
295 | wire old0x_sel_piped; | |
296 | wire old1x_sel_piped; | |
297 | wire old2x_sel_piped; | |
298 | wire old3x_sel_piped; | |
299 | wire old4x_sel_piped; | |
300 | wire old5x_sel_piped; | |
301 | wire old6x_sel_piped; | |
302 | wire old7x_sel_piped; | |
303 | wire spares_scanin; | |
304 | wire spares_scanout; | |
305 | wire fail_reg_scanin; | |
306 | wire fail_reg_scanout; | |
307 | wire [7:0] fail_reg_in; | |
308 | wire [7:0] fail_reg_out; | |
309 | wire qual_sio_old7x_fail; | |
310 | wire qual_sio_old6x_fail; | |
311 | wire qual_sio_old5x_fail; | |
312 | wire qual_sio_old4x_fail; | |
313 | wire qual_sio_old3x_fail; | |
314 | wire qual_sio_old2x_fail; | |
315 | wire qual_sio_old1x_fail; | |
316 | wire qual_sio_old0x_fail; | |
317 | wire fail_detect; | |
318 | wire fail_detect_lo; | |
319 | wire fail_detect_hi; | |
320 | ||
321 | ||
322 | ||
323 | output sio_mb0_run; | |
324 | ||
325 | output [4:0] sio_mb0_old_addr; | |
326 | output [7:0] sio_mb0_wdata; | |
327 | ||
328 | output sio_mb0_sel_l1; // To select 1x over 0x, 3x over 2x, 5x over 4x, 7x over 6x. | |
329 | output sio_mb0_sel_l2; // To select RHS old's over LHS. | |
330 | ||
331 | output sio_mb0_old0x_wr_en; | |
332 | output sio_mb0_old0x_rd_en; | |
333 | ||
334 | output sio_mb0_old1x_wr_en; | |
335 | output sio_mb0_old1x_rd_en; | |
336 | ||
337 | output sio_mb0_old2x_wr_en; | |
338 | output sio_mb0_old2x_rd_en; | |
339 | ||
340 | output sio_mb0_old3x_wr_en; | |
341 | output sio_mb0_old3x_rd_en; | |
342 | ||
343 | output sio_mb0_old4x_wr_en; | |
344 | output sio_mb0_old4x_rd_en; | |
345 | ||
346 | output sio_mb0_old5x_wr_en; | |
347 | output sio_mb0_old5x_rd_en; | |
348 | ||
349 | output sio_mb0_old6x_wr_en; | |
350 | output sio_mb0_old6x_rd_en; | |
351 | ||
352 | output sio_mb0_old7x_wr_en; | |
353 | output sio_mb0_old7x_rd_en; | |
354 | ||
355 | output sio_mb0_done; | |
356 | output sio_mb0_fail; | |
357 | output scan_out; | |
358 | ||
359 | input l2clk; | |
360 | input tcu_scan_en; | |
361 | input scan_in; | |
362 | input tcu_aclk; | |
363 | input tcu_bclk; | |
364 | input tcu_pce_ov; | |
365 | input tcu_clk_stop; | |
366 | ||
367 | input tcu_sio_mb0_start; | |
368 | input sio_mb0_bisi_mode; | |
369 | input sio_mb0_user_mode; | |
370 | ||
371 | input [67:0] read_data_top; | |
372 | input [67:0] read_data_bot; | |
373 | ||
374 | ||
375 | /////////////////////////////////////// | |
376 | // Scan chain connections | |
377 | /////////////////////////////////////// | |
378 | // scan renames | |
379 | assign se = tcu_scan_en; | |
380 | assign siclk = tcu_aclk; | |
381 | assign soclk = tcu_bclk; | |
382 | assign pce_ov = tcu_pce_ov; | |
383 | assign stop = tcu_clk_stop; | |
384 | // end scan | |
385 | ||
386 | sio_mb0_ctl_l1clkhdr_ctl_macro clkgen ( | |
387 | .l2clk (l2clk ), | |
388 | .l1en (1'b1 ), | |
389 | .l1clk (l1clk), | |
390 | .pce_ov(pce_ov), | |
391 | .stop(stop), | |
392 | .se(se) | |
393 | ); | |
394 | ||
395 | // ///////////////////////////////////////////////////////////////////////////// | |
396 | // | |
397 | // MBIST Config Register | |
398 | // | |
399 | // ///////////////////////////////////////////////////////////////////////////// | |
400 | // | |
401 | // A low to high transition on mbist_start will reset and start the engine. | |
402 | // mbist_start must remain active high for the duration of MBIST. | |
403 | // If mbist_start deasserts the engine will stop but not reset. | |
404 | // Once MBIST has completed mbist_done will assert and the fail status | |
405 | // signals will be valid. | |
406 | // To run MBIST again the mbist_start signal must transition low then high. | |
407 | // | |
408 | // Loop on Address will disable the address mix function. | |
409 | // | |
410 | // ///////////////////////////////////////////////////////////////////////////// | |
411 | ||
412 | ||
413 | sio_mb0_ctl_msff_ctl_macro__width_8 config_reg ( | |
414 | .scan_in(config_reg_scanin), | |
415 | .scan_out(config_reg_scanout), | |
416 | .din ( config_in[7:0] ), | |
417 | .dout ( config_out[7:0] ), | |
418 | .l1clk(l1clk), | |
419 | .siclk(siclk), | |
420 | .soclk(soclk)); | |
421 | ||
422 | assign config_in[0] = tcu_sio_mb0_start; | |
423 | assign config_in[1] = config_out[0]; | |
424 | assign start_transition = config_out[0] & ~config_out[1]; | |
425 | assign reset_engine = start_transition | (mbist_user_loop_mode & mbist_done); | |
426 | // assign run = config_out[1] & ~mbist_done; | |
427 | // assign run = config_out[1] & (mbist_user_loop_mode | ~mbist_done); | |
428 | assign run = config_out[0] & config_out[1]; // 9/19/05 run to follow start only! | |
429 | ||
430 | assign config_in[2] = start_transition ? sio_mb0_bisi_mode: config_out[2]; | |
431 | assign bisi = config_out[2]; | |
432 | ||
433 | assign config_in[3] = start_transition ? sio_mb0_user_mode: config_out[3]; | |
434 | assign user_mode = config_out[3]; | |
435 | ||
436 | assign config_in[4] = config_out[4]; | |
437 | assign user_data_mode = config_out[4]; | |
438 | ||
439 | assign config_in[5] = config_out[5]; | |
440 | assign user_addr_mode = config_out[5]; | |
441 | ||
442 | assign config_in[6] = config_out[6]; | |
443 | assign user_loop_mode = config_out[6]; | |
444 | ||
445 | assign config_in[7] = config_out[7]; | |
446 | assign ten_n_mode = config_out[7]; | |
447 | ||
448 | ||
449 | assign mbist_user_data_mode = user_mode & user_data_mode; | |
450 | assign mbist_user_addr_mode = user_mode & user_addr_mode; | |
451 | assign mbist_user_loop_mode = user_mode & user_loop_mode; | |
452 | assign mbist_ten_n_mode = user_mode & ten_n_mode; | |
453 | ||
454 | ||
455 | sio_mb0_ctl_msff_ctl_macro__width_8 user_data_reg ( | |
456 | .scan_in(user_data_reg_scanin), | |
457 | .scan_out(user_data_reg_scanout), | |
458 | .din ( user_data_in[7:0] ), | |
459 | .dout ( user_data_out[7:0] ), | |
460 | .l1clk(l1clk), | |
461 | .siclk(siclk), | |
462 | .soclk(soclk)); | |
463 | ||
464 | ||
465 | assign user_data_in[7:0] = user_data_out[7:0]; | |
466 | ||
467 | ||
468 | // Defining User start, stop, and increment addresses. | |
469 | ||
470 | sio_mb0_ctl_msff_ctl_macro__width_5 user_start_addr_reg ( | |
471 | .scan_in(user_start_addr_reg_scanin), | |
472 | .scan_out(user_start_addr_reg_scanout), | |
473 | .din ( user_start_addr_in[4:0] ), | |
474 | .dout ( user_start_addr[4:0] ), | |
475 | .l1clk(l1clk), | |
476 | .siclk(siclk), | |
477 | .soclk(soclk)); | |
478 | ||
479 | assign user_start_addr_in[4:0] = user_start_addr[4:0]; | |
480 | ||
481 | sio_mb0_ctl_msff_ctl_macro__width_5 user_stop_addr_reg ( | |
482 | .scan_in(user_stop_addr_reg_scanin), | |
483 | .scan_out(user_stop_addr_reg_scanout), | |
484 | .din ( user_stop_addr_in[4:0] ), | |
485 | .dout ( user_stop_addr[4:0] ), | |
486 | .l1clk(l1clk), | |
487 | .siclk(siclk), | |
488 | .soclk(soclk)); | |
489 | ||
490 | assign user_stop_addr_in[4:0] = user_stop_addr[4:0]; | |
491 | ||
492 | ||
493 | sio_mb0_ctl_msff_ctl_macro__width_5 user_incr_addr_reg ( | |
494 | .scan_in(user_incr_addr_reg_scanin), | |
495 | .scan_out(user_incr_addr_reg_scanout), | |
496 | .din ( user_incr_addr_in[4:0] ), | |
497 | .dout ( user_incr_addr[4:0] ), | |
498 | .l1clk(l1clk), | |
499 | .siclk(siclk), | |
500 | .soclk(soclk)); | |
501 | ||
502 | assign user_incr_addr_in[4:0] = user_incr_addr[4:0]; | |
503 | ||
504 | // Defining User array_sel. | |
505 | ||
506 | sio_mb0_ctl_msff_ctl_macro__width_3 user_array_sel_reg ( | |
507 | .scan_in(user_array_sel_reg_scanin), | |
508 | .scan_out(user_array_sel_reg_scanout), | |
509 | .din ( user_array_sel_in[2:0] ), | |
510 | .dout ( user_array_sel[2:0] ), | |
511 | .l1clk(l1clk), | |
512 | .siclk(siclk), | |
513 | .soclk(soclk)); | |
514 | ||
515 | assign user_array_sel_in[2:0] = user_array_sel[2:0]; | |
516 | ||
517 | // Defining user_bisi write and read registers | |
518 | ||
519 | sio_mb0_ctl_msff_ctl_macro__width_1 user_bisi_wr_reg ( | |
520 | .scan_in(user_bisi_wr_reg_scanin), | |
521 | .scan_out(user_bisi_wr_reg_scanout), | |
522 | .din ( user_bisi_wr_mode_in ), | |
523 | .dout ( user_bisi_wr_mode ), | |
524 | .l1clk(l1clk), | |
525 | .siclk(siclk), | |
526 | .soclk(soclk)); | |
527 | ||
528 | assign user_bisi_wr_mode_in = user_bisi_wr_mode; | |
529 | ||
530 | sio_mb0_ctl_msff_ctl_macro__width_1 user_bisi_rd_reg ( | |
531 | .scan_in(user_bisi_rd_reg_scanin), | |
532 | .scan_out(user_bisi_rd_reg_scanout), | |
533 | .din ( user_bisi_rd_mode_in ), | |
534 | .dout ( user_bisi_rd_mode ), | |
535 | .l1clk(l1clk), | |
536 | .siclk(siclk), | |
537 | .soclk(soclk)); | |
538 | ||
539 | assign user_bisi_rd_mode_in = user_bisi_rd_mode; | |
540 | ||
541 | assign mbist_user_bisi_wr_mode = user_mode & bisi & user_bisi_wr_mode & ~user_bisi_rd_mode; | |
542 | // assign mbist_user_bisi_rd_mode = user_mode & bisi & user_bisi_rd_mode & ~user_bisi_wr_mode; | |
543 | ||
544 | assign mbist_user_bisi_wr_rd_mode = user_mode & bisi & | |
545 | ((user_bisi_wr_mode & user_bisi_rd_mode) | | |
546 | (~user_bisi_wr_mode & ~user_bisi_rd_mode)); | |
547 | ||
548 | //////////////////////////////////////////////////////////////////////////////// | |
549 | // Piping start_transition | |
550 | //////////////////////////////////////////////////////////////////////////////// | |
551 | ||
552 | sio_mb0_ctl_msff_ctl_macro__width_1 start_transition_reg ( | |
553 | .scan_in(start_transition_reg_scanin), | |
554 | .scan_out(start_transition_reg_scanout), | |
555 | .din ( start_transition ), | |
556 | .dout ( start_transition_piped ), | |
557 | .l1clk(l1clk), | |
558 | .siclk(siclk), | |
559 | .soclk(soclk)); | |
560 | ||
561 | //////////////////////////////////////////////////////////////////////////////// | |
562 | // Staging run for 3 cycles | |
563 | //////////////////////////////////////////////////////////////////////////////// | |
564 | ||
565 | sio_mb0_ctl_msff_ctl_macro__width_1 run_reg ( | |
566 | .scan_in(run_reg_scanin), | |
567 | .scan_out(run_reg_scanout), | |
568 | .din ( run ), | |
569 | .dout ( sio_mb0_run ), | |
570 | .l1clk(l1clk), | |
571 | .siclk(siclk), | |
572 | .soclk(soclk)); | |
573 | ||
574 | //Adding 2 extra pipeline stages to run to delay the start of mbist for 3 cycles. | |
575 | sio_mb0_ctl_msff_ctl_macro__width_1 run1_reg ( | |
576 | .scan_in(run1_reg_scanin), | |
577 | .scan_out(run1_reg_scanout), | |
578 | .din ( run1_in ), | |
579 | .dout ( run1_out ), | |
580 | .l1clk(l1clk), | |
581 | .siclk(siclk), | |
582 | .soclk(soclk)); | |
583 | ||
584 | assign run1_in = reset_engine ? 1'b0: sio_mb0_run; | |
585 | ||
586 | sio_mb0_ctl_msff_ctl_macro__width_1 run2_reg ( | |
587 | .scan_in(run2_reg_scanin), | |
588 | .scan_out(run2_reg_scanout), | |
589 | .din ( run2_in ), | |
590 | .dout ( run2_out ), | |
591 | .l1clk(l1clk), | |
592 | .siclk(siclk), | |
593 | .soclk(soclk)); | |
594 | ||
595 | assign run2_in = reset_engine ? 1'b0: run1_out; | |
596 | // assign run_piped3 = run2_out & run; | |
597 | assign run_piped3 = config_out[0] & run2_out & ~msb; | |
598 | ||
599 | ||
600 | ||
601 | // ///////////////////////////////////////////////////////////////////////////// | |
602 | // Pipelining mbist outputs and inputs. | |
603 | // ///////////////////////////////////////////////////////////////////////////// | |
604 | ||
605 | sio_mb0_ctl_msff_ctl_macro__width_5 addr_reg ( | |
606 | .scan_in(addr_reg_scanin), | |
607 | .scan_out(addr_reg_scanout), | |
608 | .din ( mbist_address[4:0] ), | |
609 | .dout ( sio_mb0_old_addr[4:0] ), | |
610 | .l1clk(l1clk), | |
611 | .siclk(siclk), | |
612 | .soclk(soclk)); | |
613 | ||
614 | sio_mb0_ctl_msff_ctl_macro__width_8 wdata_reg ( | |
615 | .scan_in(wdata_reg_scanin), | |
616 | .scan_out(wdata_reg_scanout), | |
617 | .din ( mbist_wdata[7:0] ), | |
618 | .dout ( sio_mb0_wdata[7:0] ), | |
619 | .l1clk(l1clk), | |
620 | .siclk(siclk), | |
621 | .soclk(soclk)); | |
622 | ||
623 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg0 ( | |
624 | .scan_in(rd_wr_en_reg0_scanin), | |
625 | .scan_out(rd_wr_en_reg0_scanout), | |
626 | .din ( {mbist_old0x_wr_en, mbist_old0x_rd_en} ), | |
627 | .dout ( {sio_mb0_old0x_wr_en, sio_mb0_old0x_rd_en} ), | |
628 | .l1clk(l1clk), | |
629 | .siclk(siclk), | |
630 | .soclk(soclk)); | |
631 | ||
632 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg1 ( | |
633 | .scan_in(rd_wr_en_reg1_scanin), | |
634 | .scan_out(rd_wr_en_reg1_scanout), | |
635 | .din ( {mbist_old1x_wr_en, mbist_old1x_rd_en} ), | |
636 | .dout ( {sio_mb0_old1x_wr_en, sio_mb0_old1x_rd_en} ), | |
637 | .l1clk(l1clk), | |
638 | .siclk(siclk), | |
639 | .soclk(soclk)); | |
640 | ||
641 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg2 ( | |
642 | .scan_in(rd_wr_en_reg2_scanin), | |
643 | .scan_out(rd_wr_en_reg2_scanout), | |
644 | .din ( {mbist_old2x_wr_en, mbist_old2x_rd_en} ), | |
645 | .dout ( {sio_mb0_old2x_wr_en, sio_mb0_old2x_rd_en} ), | |
646 | .l1clk(l1clk), | |
647 | .siclk(siclk), | |
648 | .soclk(soclk)); | |
649 | ||
650 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg3 ( | |
651 | .scan_in(rd_wr_en_reg3_scanin), | |
652 | .scan_out(rd_wr_en_reg3_scanout), | |
653 | .din ( {mbist_old3x_wr_en, mbist_old3x_rd_en} ), | |
654 | .dout ( {sio_mb0_old3x_wr_en, sio_mb0_old3x_rd_en} ), | |
655 | .l1clk(l1clk), | |
656 | .siclk(siclk), | |
657 | .soclk(soclk)); | |
658 | ||
659 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg4 ( | |
660 | .scan_in(rd_wr_en_reg4_scanin), | |
661 | .scan_out(rd_wr_en_reg4_scanout), | |
662 | .din ( {mbist_old4x_wr_en, mbist_old4x_rd_en} ), | |
663 | .dout ( {sio_mb0_old4x_wr_en, sio_mb0_old4x_rd_en} ), | |
664 | .l1clk(l1clk), | |
665 | .siclk(siclk), | |
666 | .soclk(soclk)); | |
667 | ||
668 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg5 ( | |
669 | .scan_in(rd_wr_en_reg5_scanin), | |
670 | .scan_out(rd_wr_en_reg5_scanout), | |
671 | .din ( {mbist_old5x_wr_en, mbist_old5x_rd_en} ), | |
672 | .dout ( {sio_mb0_old5x_wr_en, sio_mb0_old5x_rd_en} ), | |
673 | .l1clk(l1clk), | |
674 | .siclk(siclk), | |
675 | .soclk(soclk)); | |
676 | ||
677 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg6 ( | |
678 | .scan_in(rd_wr_en_reg6_scanin), | |
679 | .scan_out(rd_wr_en_reg6_scanout), | |
680 | .din ( {mbist_old6x_wr_en, mbist_old6x_rd_en} ), | |
681 | .dout ( {sio_mb0_old6x_wr_en, sio_mb0_old6x_rd_en} ), | |
682 | .l1clk(l1clk), | |
683 | .siclk(siclk), | |
684 | .soclk(soclk)); | |
685 | ||
686 | sio_mb0_ctl_msff_ctl_macro__width_2 rd_wr_en_reg7 ( | |
687 | .scan_in(rd_wr_en_reg7_scanin), | |
688 | .scan_out(rd_wr_en_reg7_scanout), | |
689 | .din ( {mbist_old7x_wr_en, mbist_old7x_rd_en} ), | |
690 | .dout ( {sio_mb0_old7x_wr_en, sio_mb0_old7x_rd_en} ), | |
691 | .l1clk(l1clk), | |
692 | .siclk(siclk), | |
693 | .soclk(soclk)); | |
694 | ||
695 | // Flopping the done and fail | |
696 | ||
697 | sio_mb0_ctl_msff_ctl_macro__width_1 sio_mb0_fail_reg ( | |
698 | .scan_in(sio_mb0_fail_reg_scanin), | |
699 | .scan_out(sio_mb0_fail_reg_scanout), | |
700 | .din ( fail ), | |
701 | .dout ( sio_mb0_fail ), | |
702 | .l1clk(l1clk), | |
703 | .siclk(siclk), | |
704 | .soclk(soclk)); | |
705 | ||
706 | sio_mb0_ctl_msff_ctl_macro__width_1 sio_mb0_done_reg ( | |
707 | .scan_in(sio_mb0_done_reg_scanin), | |
708 | .scan_out(sio_mb0_done_reg_scanout), | |
709 | .din ( mbist_done ), | |
710 | .dout ( sio_mb0_done ), | |
711 | .l1clk(l1clk), | |
712 | .siclk(siclk), | |
713 | .soclk(soclk)); | |
714 | ||
715 | // Selecting and Pipelining the read_data | |
716 | ||
717 | assign read_data[67:0] = sio_mb0_sel_l3 ? read_data_bot[67:0] : read_data_top[67:0]; | |
718 | ||
719 | sio_mb0_ctl_msff_ctl_macro__width_68 read_data_pipe_reg ( | |
720 | .scan_in(read_data_pipe_reg_scanin), | |
721 | .scan_out(read_data_pipe_reg_scanout), | |
722 | .din ( read_data[67:0] ), | |
723 | .dout ( read_data_pipe[67:0] ), | |
724 | .l1clk(l1clk), | |
725 | .siclk(siclk), | |
726 | .soclk(soclk)); | |
727 | ||
728 | ||
729 | // ///////////////////////////////////////////////////////////////////////////// | |
730 | // | |
731 | // MBIST Control Register | |
732 | // | |
733 | // ///////////////////////////////////////////////////////////////////////////// | |
734 | // Remove Address mix disable before delivery | |
735 | // ///////////////////////////////////////////////////////////////////////////// | |
736 | ||
737 | sio_mb0_ctl_msff_ctl_macro__width_20 control_reg ( | |
738 | .scan_in(control_reg_scanin), | |
739 | .scan_out(control_reg_scanout), | |
740 | .din ( control_in[19:0] ), | |
741 | .dout ( control_out[19:0] ), | |
742 | .l1clk(l1clk), | |
743 | .siclk(siclk), | |
744 | .soclk(soclk)); | |
745 | ||
746 | assign msb = control_out[19]; | |
747 | assign bisi_wr_rd = (bisi & ~user_mode) | mbist_user_bisi_wr_rd_mode ? control_out[18] : 1'b1; | |
748 | assign array_sel[2:0] = user_mode ? user_array_sel[2:0] : control_out[17:15]; | |
749 | assign data_control[1:0] = control_out[14:13]; | |
750 | assign address_mix = ( bisi | mbist_user_addr_mode) ? 1'b0: control_out[12]; | |
751 | assign march_element[3:0] = control_out[11:8]; | |
752 | assign array_address[4:0] = upaddress_march ? control_out[7:3] : ~control_out[7:3]; | |
753 | assign read_write_control[2:0] = ~five_cycle_march ? {2'b11, control_out[0]} : | |
754 | control_out[2:0]; | |
755 | ||
756 | ||
757 | assign control_in[2:0] = reset_engine ? 3'b0: | |
758 | ~run_piped3 ? control_out[2:0]: | |
759 | (five_cycle_march && (read_write_control[2:0] == 3'b100)) ? 3'b000: | |
760 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) ? 3'b000: | |
761 | control_out[2:0] + 3'b001; | |
762 | ||
763 | assign increment_addr = (five_cycle_march && (read_write_control[2:0] == 3'b100)) || | |
764 | (one_cycle_march && (read_write_control[2:0] == 3'b110)) || | |
765 | (read_write_control[2:0] == 3'b111); | |
766 | ||
767 | // start_transition_piped was added to have the correct start_addr at the start | |
768 | // of mbist during user_addr_mode | |
769 | assign control_in[7:3] = start_transition_piped || reset_engine ? start_addr[4:0]: | |
770 | ~run_piped3 || ~increment_addr ? control_out[7:3]: | |
771 | next_array_address[4:0]; | |
772 | ||
773 | assign next_array_address[4:0] = next_upaddr_march ? start_addr[4:0]: | |
774 | next_downaddr_march ? ~stop_addr[4:0]: | |
775 | (overflow_addr[4:0]); // array_addr + incr_addr | |
776 | ||
777 | assign start_addr[4:0] = mbist_user_addr_mode ? user_start_addr[4:0] : 5'b00000; | |
778 | assign stop_addr[4:0] = mbist_user_addr_mode ? user_stop_addr[4:0] : 5'b11111; | |
779 | assign incr_addr[4:0] = mbist_user_addr_mode ? user_incr_addr[4:0] : 5'b00001; | |
780 | ||
781 | assign overflow_addr[5:0] = {1'b0,control_out[7:3]} + {1'b0,incr_addr[4:0]}; | |
782 | assign overflow = compare_addr[5:0] < overflow_addr[5:0]; | |
783 | ||
784 | assign compare_addr[5:0] = upaddress_march ? {1'b0, stop_addr[4:0]} : | |
785 | {1'b0, ~start_addr[4:0]}; | |
786 | ||
787 | assign next_upaddr_march = ( (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
788 | (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h5) || | |
789 | (march_element[3:0] == 4'h8) ) && overflow; | |
790 | ||
791 | assign next_downaddr_march = ( (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h7) || | |
792 | (march_element[3:0] == 4'h3) || (march_element[3:0] == 4'h4) ) && | |
793 | overflow; | |
794 | ||
795 | ||
796 | ||
797 | assign add[4:0] = five_cycle_march && ( (read_write_control[2:0] == 3'h1) || | |
798 | (read_write_control[2:0] == 3'h3)) ? | |
799 | adj_address[4:0]: array_address[4:0]; | |
800 | ||
801 | assign adj_address[4:0] = { array_address[4:2], ~array_address[1], array_address[0] }; | |
802 | assign mbist_address[4:0] = address_mix ? {add[0],add[4],add[3],add[2],add[1]}: // fast bank | |
803 | add[4:0]; | |
804 | ||
805 | // Definition of the rest of the control register | |
806 | assign increment_march_elem = increment_addr && overflow; | |
807 | ||
808 | assign control_in[19:8] = reset_engine ? 12'b0: | |
809 | ~run_piped3 ? control_out[19:8]: | |
810 | {msb, bisi_wr_rd, next_array_sel[2:0], next_data_control[1:0], next_address_mix, next_march_element[3:0]} | |
811 | + {11'b0, increment_march_elem}; | |
812 | ||
813 | assign next_array_sel[2:0] = user_mode ? 3'b111: control_out[17:15]; | |
814 | assign next_data_control[1:0] = (bisi || (mbist_user_data_mode && (data_control[1:0] == 2'b00))) ? 2'b11: | |
815 | data_control[1:0]; | |
816 | assign next_address_mix = ( bisi | mbist_user_addr_mode) ? 1'b1 : address_mix; | |
817 | ||
818 | // Modified next_march_element to remove a possible long path. | |
819 | // Incorporated ten_n_mode! | |
820 | assign next_march_element[3:0] = ( bisi || | |
821 | (mbist_ten_n_mode && (march_element[3:0] == 4'b0101)) || | |
822 | ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
823 | && overflow ? 4'b1111: march_element[3:0]; | |
824 | ||
825 | // assign next_march_element[3:0] = (bisi || ((march_element[3:0] == 4'b1000) && (read_write_control[2:0] == 3'b100)) ) | |
826 | // && overflow ? 4'b1111: march_element[3:0]; | |
827 | ||
828 | ||
829 | assign array_write = ~run_piped3 ? 1'b0: | |
830 | five_cycle_march ? (read_write_control[2:0] == 3'h0) || | |
831 | (read_write_control[2:0] == 3'h1) || | |
832 | (read_write_control[2:0] == 3'h4): | |
833 | (~five_cycle_march & ~one_cycle_march) ? read_write_control[0]: | |
834 | ( ((march_element[3:0] == 4'h0) & (~bisi || ~bisi_wr_rd || mbist_user_bisi_wr_mode)) || (march_element[3:0] == 4'h7)); | |
835 | ||
836 | assign array_read = ~array_write && run_piped3; // && ~initialize; | |
837 | // assign mbist_done = msb; | |
838 | ||
839 | assign mbist_wdata[7:0] = true_data ? data_pattern[7:0]: ~data_pattern[7:0]; | |
840 | ||
841 | ||
842 | // assign second_time_through = ~loop_on_address && address_mix; | |
843 | // assign initialize = (march_element[3:0] == 4'b0000) && ~second_time_through; | |
844 | ||
845 | ||
846 | // assign four_cycle_march = (march_element[3:0] == 3'h6) || (march_element[3:0] == 3'h7); | |
847 | assign five_cycle_march = (march_element[3:0] == 4'h6) || (march_element[3:0] == 4'h8); | |
848 | assign one_cycle_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h5) || | |
849 | (march_element[3:0] == 4'h7); | |
850 | ||
851 | assign upaddress_march = (march_element[3:0] == 4'h0) || (march_element[3:0] == 4'h1) || | |
852 | (march_element[3:0] == 4'h2) || (march_element[3:0] == 4'h6) || | |
853 | (march_element[3:0] == 4'h7); | |
854 | ||
855 | // assign true_data = read_write_control[1] ^ ~march_element[0]; | |
856 | ||
857 | assign true_data = (five_cycle_march && (march_element[3:0] == 4'h6)) ? | |
858 | ((read_write_control[2:0] == 3'h0) || (read_write_control[2:0] == 3'h2)): | |
859 | (five_cycle_march && (march_element[3:0] == 4'h8)) ? | |
860 | ((read_write_control[2:0] == 3'h1) || | |
861 | (read_write_control[2:0] == 3'h3) || (read_write_control[2:0] == 3'h4)): | |
862 | one_cycle_march ? (march_element[3:0] == 4'h7): | |
863 | ~(read_write_control[0] ^ march_element[0]); | |
864 | ||
865 | ||
866 | assign data_pattern[7:0] = (bisi & mbist_user_data_mode) ? ~user_data_out[7:0]: | |
867 | mbist_user_data_mode ? user_data_out[7:0]: | |
868 | bisi ? 8'hFF: // true_data function will invert to 8'h00 | |
869 | (data_control[1:0] == 2'h0) ? 8'hAA: | |
870 | (data_control[1:0] == 2'h1) ? 8'h99: | |
871 | (data_control[1:0] == 2'h2) ? 8'hCC: | |
872 | 8'h00; | |
873 | ||
874 | ||
875 | ///////////////////////////////////////////////////////////////////////// | |
876 | // Creating the mbist_done signal | |
877 | ///////////////////////////////////////////////////////////////////////// | |
878 | // Delaying mbist_done 8 clock signals after msb going high, to provide | |
879 | // a generic solution for done going high after the last fail has come back! | |
880 | ||
881 | sio_mb0_ctl_msff_ctl_macro__width_3 done_counter_reg ( | |
882 | .scan_in(done_counter_reg_scanin), | |
883 | .scan_out(done_counter_reg_scanout), | |
884 | .din ( done_counter_in[2:0] ), | |
885 | .dout ( done_counter_out[2:0] ), | |
886 | .l1clk(l1clk), | |
887 | .siclk(siclk), | |
888 | .soclk(soclk)); | |
889 | ||
890 | // config_out[1] is AND'ed to force mbist_done low 2 cycles after mbist_start | |
891 | // goes low. | |
892 | ||
893 | assign mbist_done = (&done_counter_out[2:0] == 1'b1) & config_out[1]; | |
894 | assign done_counter_in[2:0] = reset_engine ? 3'b000: | |
895 | msb & ~mbist_done & config_out[1] ? done_counter_out[2:0] + 3'b001: | |
896 | done_counter_out[2:0]; | |
897 | ||
898 | ||
899 | ///////////////////////////////////////////////////////////////////////// | |
900 | // Creating the select lines and enable signals. | |
901 | ///////////////////////////////////////////////////////////////////////// | |
902 | ||
903 | assign old0x_sel = ~array_sel[2] & ~array_sel[1] & ~array_sel[0]; | |
904 | assign old1x_sel = ~array_sel[2] & ~array_sel[1] & array_sel[0]; | |
905 | ||
906 | assign old2x_sel = ~array_sel[2] & array_sel[1] & ~array_sel[0]; | |
907 | assign old3x_sel = ~array_sel[2] & array_sel[1] & array_sel[0]; | |
908 | ||
909 | assign old4x_sel = array_sel[2] & ~array_sel[1] & ~array_sel[0]; | |
910 | assign old5x_sel = array_sel[2] & ~array_sel[1] & array_sel[0]; | |
911 | ||
912 | assign old6x_sel = array_sel[2] & array_sel[1] & ~array_sel[0]; | |
913 | assign old7x_sel = array_sel[2] & array_sel[1] & array_sel[0]; | |
914 | ||
915 | // assign sel_l1 = array_sel[0]; | |
916 | // assign sel_l2 = array_sel[2]; | |
917 | // assign sel_l3 = array_sel[1]; | |
918 | ||
919 | assign mbist_old0x_rd_en = old0x_sel && array_read; | |
920 | assign mbist_old0x_wr_en = old0x_sel && array_write; | |
921 | //Kept this as a sample! | |
922 | // assign mbist_old0x_wr_en = (old0x_sel || bisi) && array_write; | |
923 | ||
924 | assign mbist_old1x_rd_en = old1x_sel && array_read; | |
925 | assign mbist_old1x_wr_en = old1x_sel && array_write; | |
926 | ||
927 | assign mbist_old2x_rd_en = old2x_sel && array_read; | |
928 | assign mbist_old2x_wr_en = old2x_sel && array_write; | |
929 | ||
930 | assign mbist_old3x_rd_en = old3x_sel && array_read; | |
931 | assign mbist_old3x_wr_en = old3x_sel && array_write; | |
932 | ||
933 | assign mbist_old4x_rd_en = old4x_sel && array_read; | |
934 | assign mbist_old4x_wr_en = old4x_sel && array_write; | |
935 | ||
936 | assign mbist_old5x_rd_en = old5x_sel && array_read; | |
937 | assign mbist_old5x_wr_en = old5x_sel && array_write; | |
938 | ||
939 | assign mbist_old6x_rd_en = old6x_sel && array_read; | |
940 | assign mbist_old6x_wr_en = old6x_sel && array_write; | |
941 | ||
942 | assign mbist_old7x_rd_en = old7x_sel && array_read; | |
943 | assign mbist_old7x_wr_en = old7x_sel && array_write; | |
944 | ||
945 | ||
946 | // ///////////////////////////////////////////////////////////////////////////// | |
947 | // Pipeline for Address, wdata, Read_en, select lines | |
948 | // ///////////////////////////////////////////////////////////////////////////// | |
949 | ||
950 | ||
951 | sio_mb0_ctl_msff_ctl_macro__width_8 data_pipe_reg1 ( | |
952 | .scan_in(data_pipe_reg1_scanin), | |
953 | .scan_out(data_pipe_reg1_scanout), | |
954 | .din ( data_pipe_reg1_in[7:0] ), | |
955 | .dout ( data_pipe_out1[7:0] ), | |
956 | .l1clk(l1clk), | |
957 | .siclk(siclk), | |
958 | .soclk(soclk)); | |
959 | ||
960 | sio_mb0_ctl_msff_ctl_macro__width_8 data_pipe_reg2 ( | |
961 | .scan_in(data_pipe_reg2_scanin), | |
962 | .scan_out(data_pipe_reg2_scanout), | |
963 | .din ( data_pipe_reg2_in[7:0] ), | |
964 | .dout ( data_pipe_out2[7:0] ), | |
965 | .l1clk(l1clk), | |
966 | .siclk(siclk), | |
967 | .soclk(soclk)); | |
968 | ||
969 | sio_mb0_ctl_msff_ctl_macro__width_8 data_pipe_reg3 ( | |
970 | .scan_in(data_pipe_reg3_scanin), | |
971 | .scan_out(data_pipe_reg3_scanout), | |
972 | .din ( data_pipe_reg3_in[7:0] ), | |
973 | .dout ( data_pipe_out3[7:0] ), | |
974 | .l1clk(l1clk), | |
975 | .siclk(siclk), | |
976 | .soclk(soclk)); | |
977 | ||
978 | sio_mb0_ctl_msff_ctl_macro__width_8 data_pipe_reg4 ( | |
979 | .scan_in(data_pipe_reg4_scanin), | |
980 | .scan_out(data_pipe_reg4_scanout), | |
981 | .din ( data_pipe_reg4_in[7:0] ), | |
982 | .dout ( data_pipe_out4[7:0] ), | |
983 | .l1clk(l1clk), | |
984 | .siclk(siclk), | |
985 | .soclk(soclk)); | |
986 | ||
987 | assign data_pipe_reg1_in[7:0] = reset_engine ? 8'h00: sio_mb0_wdata[7:0]; | |
988 | assign data_pipe_reg2_in[7:0] = reset_engine ? 8'h00: data_pipe_out1[7:0]; | |
989 | assign data_pipe_reg3_in[7:0] = reset_engine ? 8'h00: data_pipe_out2[7:0]; | |
990 | assign data_pipe_reg4_in[7:0] = reset_engine ? 8'h00: data_pipe_out3[7:0]; | |
991 | ||
992 | assign sio_old_piped_data[7:0] = data_pipe_out4[7:0]; | |
993 | ||
994 | sio_mb0_ctl_msff_ctl_macro__width_1 ren_pipe_reg1 ( | |
995 | .scan_in(ren_pipe_reg1_scanin), | |
996 | .scan_out(ren_pipe_reg1_scanout), | |
997 | .din ( ren_pipe_reg1_in ), | |
998 | .dout ( ren_pipe_out1 ), | |
999 | .l1clk(l1clk), | |
1000 | .siclk(siclk), | |
1001 | .soclk(soclk)); | |
1002 | ||
1003 | sio_mb0_ctl_msff_ctl_macro__width_1 ren_pipe_reg2 ( | |
1004 | .scan_in(ren_pipe_reg2_scanin), | |
1005 | .scan_out(ren_pipe_reg2_scanout), | |
1006 | .din ( ren_pipe_reg2_in ), | |
1007 | .dout ( ren_pipe_out2 ), | |
1008 | .l1clk(l1clk), | |
1009 | .siclk(siclk), | |
1010 | .soclk(soclk)); | |
1011 | ||
1012 | sio_mb0_ctl_msff_ctl_macro__width_1 ren_pipe_reg3 ( | |
1013 | .scan_in(ren_pipe_reg3_scanin), | |
1014 | .scan_out(ren_pipe_reg3_scanout), | |
1015 | .din ( ren_pipe_reg3_in ), | |
1016 | .dout ( ren_pipe_out3 ), | |
1017 | .l1clk(l1clk), | |
1018 | .siclk(siclk), | |
1019 | .soclk(soclk)); | |
1020 | ||
1021 | sio_mb0_ctl_msff_ctl_macro__width_1 ren_pipe_reg4 ( | |
1022 | .scan_in(ren_pipe_reg4_scanin), | |
1023 | .scan_out(ren_pipe_reg4_scanout), | |
1024 | .din ( ren_pipe_reg4_in ), | |
1025 | .dout ( ren_pipe_out4 ), | |
1026 | .l1clk(l1clk), | |
1027 | .siclk(siclk), | |
1028 | .soclk(soclk)); | |
1029 | ||
1030 | sio_mb0_ctl_msff_ctl_macro__width_1 ren_pipe_reg5 ( | |
1031 | .scan_in(ren_pipe_reg5_scanin), | |
1032 | .scan_out(ren_pipe_reg5_scanout), | |
1033 | .din ( ren_pipe_reg5_in ), | |
1034 | .dout ( ren_pipe_out5 ), | |
1035 | .l1clk(l1clk), | |
1036 | .siclk(siclk), | |
1037 | .soclk(soclk)); | |
1038 | ||
1039 | assign ren_pipe_reg1_in = reset_engine ? 1'b0: array_read; | |
1040 | assign ren_pipe_reg2_in = reset_engine ? 1'b0: ren_pipe_out1; | |
1041 | assign ren_pipe_reg3_in = reset_engine ? 1'b0: ren_pipe_out2; | |
1042 | assign ren_pipe_reg4_in = reset_engine ? 1'b0: ren_pipe_out3; | |
1043 | assign ren_pipe_reg5_in = reset_engine ? 1'b0: ren_pipe_out4; | |
1044 | assign sio_old_piped_ren = ren_pipe_out5; | |
1045 | ||
1046 | //array_sel | |
1047 | sio_mb0_ctl_msff_ctl_macro__width_3 ary_sel_pipe_reg1 ( | |
1048 | .scan_in(ary_sel_pipe_reg1_scanin), | |
1049 | .scan_out(ary_sel_pipe_reg1_scanout), | |
1050 | .din ( ary_sel_pipe_reg1_in[2:0] ), | |
1051 | .dout ( ary_sel_pipe_out1[2:0] ), | |
1052 | .l1clk(l1clk), | |
1053 | .siclk(siclk), | |
1054 | .soclk(soclk)); | |
1055 | ||
1056 | sio_mb0_ctl_msff_ctl_macro__width_3 ary_sel_pipe_reg2 ( | |
1057 | .scan_in(ary_sel_pipe_reg2_scanin), | |
1058 | .scan_out(ary_sel_pipe_reg2_scanout), | |
1059 | .din ( ary_sel_pipe_reg2_in[2:0] ), | |
1060 | .dout ( ary_sel_pipe_out2[2:0] ), | |
1061 | .l1clk(l1clk), | |
1062 | .siclk(siclk), | |
1063 | .soclk(soclk)); | |
1064 | ||
1065 | sio_mb0_ctl_msff_ctl_macro__width_3 ary_sel_pipe_reg3 ( | |
1066 | .scan_in(ary_sel_pipe_reg3_scanin), | |
1067 | .scan_out(ary_sel_pipe_reg3_scanout), | |
1068 | .din ( ary_sel_pipe_reg3_in[2:0] ), | |
1069 | .dout ( ary_sel_pipe_out3[2:0] ), | |
1070 | .l1clk(l1clk), | |
1071 | .siclk(siclk), | |
1072 | .soclk(soclk)); | |
1073 | ||
1074 | sio_mb0_ctl_msff_ctl_macro__width_3 ary_sel_pipe_reg4 ( | |
1075 | .scan_in(ary_sel_pipe_reg4_scanin), | |
1076 | .scan_out(ary_sel_pipe_reg4_scanout), | |
1077 | .din ( ary_sel_pipe_reg4_in[2:0] ), | |
1078 | .dout ( ary_sel_pipe_out4[2:0] ), | |
1079 | .l1clk(l1clk), | |
1080 | .siclk(siclk), | |
1081 | .soclk(soclk)); | |
1082 | ||
1083 | sio_mb0_ctl_msff_ctl_macro__width_3 ary_sel_pipe_reg5 ( | |
1084 | .scan_in(ary_sel_pipe_reg5_scanin), | |
1085 | .scan_out(ary_sel_pipe_reg5_scanout), | |
1086 | .din ( ary_sel_pipe_reg5_in[2:0] ), | |
1087 | .dout ( ary_sel_pipe_out5[2:0] ), | |
1088 | .l1clk(l1clk), | |
1089 | .siclk(siclk), | |
1090 | .soclk(soclk)); | |
1091 | ||
1092 | assign ary_sel_pipe_reg1_in[2:0] = reset_engine ? 3'h0: array_sel[2:0]; | |
1093 | assign ary_sel_pipe_reg2_in[2:0] = reset_engine ? 3'h0: ary_sel_pipe_out1[2:0]; | |
1094 | assign ary_sel_pipe_reg3_in[2:0] = reset_engine ? 3'h0: ary_sel_pipe_out2[2:0]; | |
1095 | assign ary_sel_pipe_reg4_in[2:0] = reset_engine ? 3'h0: ary_sel_pipe_out3[2:0]; | |
1096 | assign ary_sel_pipe_reg5_in[2:0] = reset_engine ? 3'h0: ary_sel_pipe_out4[2:0]; | |
1097 | assign piped_array_sel[2:0] = ary_sel_pipe_out5[2:0]; | |
1098 | ||
1099 | assign sio_mb0_sel_l1 = ~ary_sel_pipe_out3[0]; | |
1100 | assign sio_mb0_sel_l2 = ~ary_sel_pipe_out3[2]; | |
1101 | assign sio_mb0_sel_l3 = ary_sel_pipe_out4[1]; // After the 2nd mux, there is another level | |
1102 | // of flop, therefore one more stage on sel_l3! | |
1103 | ||
1104 | assign old0x_sel_piped = ~piped_array_sel[2] & ~piped_array_sel[1] & ~piped_array_sel[0]; | |
1105 | assign old1x_sel_piped = ~piped_array_sel[2] & ~piped_array_sel[1] & piped_array_sel[0]; | |
1106 | ||
1107 | assign old2x_sel_piped = ~piped_array_sel[2] & piped_array_sel[1] & ~piped_array_sel[0]; | |
1108 | assign old3x_sel_piped = ~piped_array_sel[2] & piped_array_sel[1] & piped_array_sel[0]; | |
1109 | ||
1110 | assign old4x_sel_piped = piped_array_sel[2] & ~piped_array_sel[1] & ~piped_array_sel[0]; | |
1111 | assign old5x_sel_piped = piped_array_sel[2] & ~piped_array_sel[1] & piped_array_sel[0]; | |
1112 | ||
1113 | assign old6x_sel_piped = piped_array_sel[2] & piped_array_sel[1] & ~piped_array_sel[0]; | |
1114 | assign old7x_sel_piped = piped_array_sel[2] & piped_array_sel[1] & piped_array_sel[0]; | |
1115 | ||
1116 | // ///////////////////////////////////////////////////////////////////////////// | |
1117 | // Spare gates | |
1118 | // ///////////////////////////////////////////////////////////////////////////// | |
1119 | ||
1120 | sio_mb0_ctl_spare_ctl_macro__num_3 spares ( | |
1121 | .scan_in(spares_scanin), | |
1122 | .scan_out(spares_scanout), | |
1123 | .l1clk (l1clk), | |
1124 | .siclk(siclk), | |
1125 | .soclk(soclk) | |
1126 | ); | |
1127 | ||
1128 | ||
1129 | // ///////////////////////////////////////////////////////////////////////////// | |
1130 | // Shared Fail Detection | |
1131 | // ///////////////////////////////////////////////////////////////////////////// | |
1132 | // 05/07/05: Updated to meet these new features: | |
1133 | // 1.When mbist_done signal is asserted when it completes all the | |
1134 | // tests, it also need to assert static membist fail signal if | |
1135 | // there were any failures during the tests. | |
1136 | // 2.The mbist_fail signal won't be sticky bit from membist | |
1137 | // engine. The TCU will make it sticky fail bit as needed. | |
1138 | ||
1139 | ||
1140 | sio_mb0_ctl_msff_ctl_macro__width_8 fail_reg ( | |
1141 | .scan_in(fail_reg_scanin), | |
1142 | .scan_out(fail_reg_scanout), | |
1143 | .din ( fail_reg_in[7:0] ), | |
1144 | .dout ( fail_reg_out[7:0] ), | |
1145 | .l1clk(l1clk), | |
1146 | .siclk(siclk), | |
1147 | .soclk(soclk)); | |
1148 | ||
1149 | ||
1150 | assign fail_reg_in[7:0] = reset_engine ? 8'b0: {qual_sio_old7x_fail,qual_sio_old6x_fail,qual_sio_old5x_fail,qual_sio_old4x_fail,qual_sio_old3x_fail,qual_sio_old2x_fail,qual_sio_old1x_fail,qual_sio_old0x_fail} | fail_reg_out[7:0]; | |
1151 | ||
1152 | ||
1153 | assign qual_sio_old0x_fail = fail_detect && old0x_sel_piped; | |
1154 | assign qual_sio_old1x_fail = fail_detect && old1x_sel_piped; | |
1155 | assign qual_sio_old2x_fail = fail_detect && old2x_sel_piped; | |
1156 | assign qual_sio_old3x_fail = fail_detect && old3x_sel_piped; | |
1157 | assign qual_sio_old4x_fail = fail_detect && old4x_sel_piped; | |
1158 | assign qual_sio_old5x_fail = fail_detect && old5x_sel_piped; | |
1159 | assign qual_sio_old6x_fail = fail_detect && old6x_sel_piped; | |
1160 | assign qual_sio_old7x_fail = fail_detect && old7x_sel_piped; | |
1161 | ||
1162 | assign fail = mbist_done ? |fail_reg_out[7:0] : | |
1163 | qual_sio_old7x_fail | qual_sio_old6x_fail | qual_sio_old5x_fail | qual_sio_old4x_fail | | |
1164 | qual_sio_old3x_fail | qual_sio_old2x_fail | qual_sio_old1x_fail | qual_sio_old0x_fail; | |
1165 | ||
1166 | ||
1167 | assign fail_detect_lo = (({ sio_old_piped_data[1:0], {4{sio_old_piped_data[7:0]}} } != read_data_pipe[33:0]) && sio_old_piped_ren); | |
1168 | assign fail_detect_hi = (({ sio_old_piped_data[1:0], {4{sio_old_piped_data[7:0]}} } != read_data_pipe[67:34]) && sio_old_piped_ren); | |
1169 | ||
1170 | assign fail_detect = fail_detect_lo | fail_detect_hi; | |
1171 | ||
1172 | ||
1173 | ||
1174 | ||
1175 | // fixscan start: | |
1176 | assign config_reg_scanin = scan_in ; | |
1177 | assign user_data_reg_scanin = config_reg_scanout ; | |
1178 | assign user_start_addr_reg_scanin = user_data_reg_scanout ; | |
1179 | assign user_stop_addr_reg_scanin = user_start_addr_reg_scanout; | |
1180 | assign user_incr_addr_reg_scanin = user_stop_addr_reg_scanout; | |
1181 | assign user_array_sel_reg_scanin = user_incr_addr_reg_scanout; | |
1182 | assign user_bisi_wr_reg_scanin = user_array_sel_reg_scanout; | |
1183 | assign user_bisi_rd_reg_scanin = user_bisi_wr_reg_scanout ; | |
1184 | assign start_transition_reg_scanin = user_bisi_rd_reg_scanout ; | |
1185 | assign run_reg_scanin = start_transition_reg_scanout; | |
1186 | assign run1_reg_scanin = run_reg_scanout ; | |
1187 | assign run2_reg_scanin = run1_reg_scanout ; | |
1188 | assign addr_reg_scanin = run2_reg_scanout ; | |
1189 | assign wdata_reg_scanin = addr_reg_scanout ; | |
1190 | assign rd_wr_en_reg0_scanin = wdata_reg_scanout ; | |
1191 | assign rd_wr_en_reg1_scanin = rd_wr_en_reg0_scanout ; | |
1192 | assign rd_wr_en_reg2_scanin = rd_wr_en_reg1_scanout ; | |
1193 | assign rd_wr_en_reg3_scanin = rd_wr_en_reg2_scanout ; | |
1194 | assign rd_wr_en_reg4_scanin = rd_wr_en_reg3_scanout ; | |
1195 | assign rd_wr_en_reg5_scanin = rd_wr_en_reg4_scanout ; | |
1196 | assign rd_wr_en_reg6_scanin = rd_wr_en_reg5_scanout ; | |
1197 | assign rd_wr_en_reg7_scanin = rd_wr_en_reg6_scanout ; | |
1198 | assign sio_mb0_fail_reg_scanin = rd_wr_en_reg7_scanout ; | |
1199 | assign sio_mb0_done_reg_scanin = sio_mb0_fail_reg_scanout ; | |
1200 | assign read_data_pipe_reg_scanin = sio_mb0_done_reg_scanout ; | |
1201 | assign control_reg_scanin = read_data_pipe_reg_scanout; | |
1202 | assign done_counter_reg_scanin = control_reg_scanout ; | |
1203 | assign data_pipe_reg1_scanin = done_counter_reg_scanout ; | |
1204 | assign data_pipe_reg2_scanin = data_pipe_reg1_scanout ; | |
1205 | assign data_pipe_reg3_scanin = data_pipe_reg2_scanout ; | |
1206 | assign data_pipe_reg4_scanin = data_pipe_reg3_scanout ; | |
1207 | assign ren_pipe_reg1_scanin = data_pipe_reg4_scanout ; | |
1208 | assign ren_pipe_reg2_scanin = ren_pipe_reg1_scanout ; | |
1209 | assign ren_pipe_reg3_scanin = ren_pipe_reg2_scanout ; | |
1210 | assign ren_pipe_reg4_scanin = ren_pipe_reg3_scanout ; | |
1211 | assign ren_pipe_reg5_scanin = ren_pipe_reg4_scanout ; | |
1212 | assign ary_sel_pipe_reg1_scanin = ren_pipe_reg5_scanout ; | |
1213 | assign ary_sel_pipe_reg2_scanin = ary_sel_pipe_reg1_scanout; | |
1214 | assign ary_sel_pipe_reg3_scanin = ary_sel_pipe_reg2_scanout; | |
1215 | assign ary_sel_pipe_reg4_scanin = ary_sel_pipe_reg3_scanout; | |
1216 | assign ary_sel_pipe_reg5_scanin = ary_sel_pipe_reg4_scanout; | |
1217 | assign spares_scanin = ary_sel_pipe_reg5_scanout; | |
1218 | assign fail_reg_scanin = spares_scanout ; | |
1219 | assign scan_out = fail_reg_scanout ; | |
1220 | // fixscan end: | |
1221 | endmodule // sio_mb0_ctl | |
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | // any PARAMS parms go into naming of macro | |
1229 | ||
1230 | module sio_mb0_ctl_l1clkhdr_ctl_macro ( | |
1231 | l2clk, | |
1232 | l1en, | |
1233 | pce_ov, | |
1234 | stop, | |
1235 | se, | |
1236 | l1clk); | |
1237 | ||
1238 | ||
1239 | input l2clk; | |
1240 | input l1en; | |
1241 | input pce_ov; | |
1242 | input stop; | |
1243 | input se; | |
1244 | output l1clk; | |
1245 | ||
1246 | ||
1247 | ||
1248 | ||
1249 | ||
1250 | cl_sc1_l1hdr_8x c_0 ( | |
1251 | ||
1252 | ||
1253 | .l2clk(l2clk), | |
1254 | .pce(l1en), | |
1255 | .l1clk(l1clk), | |
1256 | .se(se), | |
1257 | .pce_ov(pce_ov), | |
1258 | .stop(stop) | |
1259 | ); | |
1260 | ||
1261 | ||
1262 | ||
1263 | endmodule | |
1264 | ||
1265 | ||
1266 | ||
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | // any PARAMS parms go into naming of macro | |
1278 | ||
1279 | module sio_mb0_ctl_msff_ctl_macro__width_8 ( | |
1280 | din, | |
1281 | l1clk, | |
1282 | scan_in, | |
1283 | siclk, | |
1284 | soclk, | |
1285 | dout, | |
1286 | scan_out); | |
1287 | wire [7:0] fdin; | |
1288 | wire [6:0] so; | |
1289 | ||
1290 | input [7:0] din; | |
1291 | input l1clk; | |
1292 | input scan_in; | |
1293 | ||
1294 | ||
1295 | input siclk; | |
1296 | input soclk; | |
1297 | ||
1298 | output [7:0] dout; | |
1299 | output scan_out; | |
1300 | assign fdin[7:0] = din[7:0]; | |
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | ||
1306 | ||
1307 | dff #(8) d0_0 ( | |
1308 | .l1clk(l1clk), | |
1309 | .siclk(siclk), | |
1310 | .soclk(soclk), | |
1311 | .d(fdin[7:0]), | |
1312 | .si({scan_in,so[6:0]}), | |
1313 | .so({so[6:0],scan_out}), | |
1314 | .q(dout[7:0]) | |
1315 | ); | |
1316 | ||
1317 | ||
1318 | ||
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | endmodule | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | // any PARAMS parms go into naming of macro | |
1343 | ||
1344 | module sio_mb0_ctl_msff_ctl_macro__width_5 ( | |
1345 | din, | |
1346 | l1clk, | |
1347 | scan_in, | |
1348 | siclk, | |
1349 | soclk, | |
1350 | dout, | |
1351 | scan_out); | |
1352 | wire [4:0] fdin; | |
1353 | wire [3:0] so; | |
1354 | ||
1355 | input [4:0] din; | |
1356 | input l1clk; | |
1357 | input scan_in; | |
1358 | ||
1359 | ||
1360 | input siclk; | |
1361 | input soclk; | |
1362 | ||
1363 | output [4:0] dout; | |
1364 | output scan_out; | |
1365 | assign fdin[4:0] = din[4:0]; | |
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | ||
1371 | ||
1372 | dff #(5) d0_0 ( | |
1373 | .l1clk(l1clk), | |
1374 | .siclk(siclk), | |
1375 | .soclk(soclk), | |
1376 | .d(fdin[4:0]), | |
1377 | .si({scan_in,so[3:0]}), | |
1378 | .so({so[3:0],scan_out}), | |
1379 | .q(dout[4:0]) | |
1380 | ); | |
1381 | ||
1382 | ||
1383 | ||
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | endmodule | |
1394 | ||
1395 | ||
1396 | ||
1397 | ||
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | // any PARAMS parms go into naming of macro | |
1408 | ||
1409 | module sio_mb0_ctl_msff_ctl_macro__width_3 ( | |
1410 | din, | |
1411 | l1clk, | |
1412 | scan_in, | |
1413 | siclk, | |
1414 | soclk, | |
1415 | dout, | |
1416 | scan_out); | |
1417 | wire [2:0] fdin; | |
1418 | wire [1:0] so; | |
1419 | ||
1420 | input [2:0] din; | |
1421 | input l1clk; | |
1422 | input scan_in; | |
1423 | ||
1424 | ||
1425 | input siclk; | |
1426 | input soclk; | |
1427 | ||
1428 | output [2:0] dout; | |
1429 | output scan_out; | |
1430 | assign fdin[2:0] = din[2:0]; | |
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | dff #(3) d0_0 ( | |
1438 | .l1clk(l1clk), | |
1439 | .siclk(siclk), | |
1440 | .soclk(soclk), | |
1441 | .d(fdin[2:0]), | |
1442 | .si({scan_in,so[1:0]}), | |
1443 | .so({so[1:0],scan_out}), | |
1444 | .q(dout[2:0]) | |
1445 | ); | |
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | endmodule | |
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | // any PARAMS parms go into naming of macro | |
1473 | ||
1474 | module sio_mb0_ctl_msff_ctl_macro__width_1 ( | |
1475 | din, | |
1476 | l1clk, | |
1477 | scan_in, | |
1478 | siclk, | |
1479 | soclk, | |
1480 | dout, | |
1481 | scan_out); | |
1482 | wire [0:0] fdin; | |
1483 | ||
1484 | input [0:0] din; | |
1485 | input l1clk; | |
1486 | input scan_in; | |
1487 | ||
1488 | ||
1489 | input siclk; | |
1490 | input soclk; | |
1491 | ||
1492 | output [0:0] dout; | |
1493 | output scan_out; | |
1494 | assign fdin[0:0] = din[0:0]; | |
1495 | ||
1496 | ||
1497 | ||
1498 | ||
1499 | ||
1500 | ||
1501 | dff #(1) d0_0 ( | |
1502 | .l1clk(l1clk), | |
1503 | .siclk(siclk), | |
1504 | .soclk(soclk), | |
1505 | .d(fdin[0:0]), | |
1506 | .si(scan_in), | |
1507 | .so(scan_out), | |
1508 | .q(dout[0:0]) | |
1509 | ); | |
1510 | ||
1511 | ||
1512 | ||
1513 | ||
1514 | ||
1515 | ||
1516 | ||
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | endmodule | |
1523 | ||
1524 | ||
1525 | ||
1526 | ||
1527 | ||
1528 | ||
1529 | ||
1530 | ||
1531 | ||
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | // any PARAMS parms go into naming of macro | |
1537 | ||
1538 | module sio_mb0_ctl_msff_ctl_macro__width_2 ( | |
1539 | din, | |
1540 | l1clk, | |
1541 | scan_in, | |
1542 | siclk, | |
1543 | soclk, | |
1544 | dout, | |
1545 | scan_out); | |
1546 | wire [1:0] fdin; | |
1547 | wire [0:0] so; | |
1548 | ||
1549 | input [1:0] din; | |
1550 | input l1clk; | |
1551 | input scan_in; | |
1552 | ||
1553 | ||
1554 | input siclk; | |
1555 | input soclk; | |
1556 | ||
1557 | output [1:0] dout; | |
1558 | output scan_out; | |
1559 | assign fdin[1:0] = din[1:0]; | |
1560 | ||
1561 | ||
1562 | ||
1563 | ||
1564 | ||
1565 | ||
1566 | dff #(2) d0_0 ( | |
1567 | .l1clk(l1clk), | |
1568 | .siclk(siclk), | |
1569 | .soclk(soclk), | |
1570 | .d(fdin[1:0]), | |
1571 | .si({scan_in,so[0:0]}), | |
1572 | .so({so[0:0],scan_out}), | |
1573 | .q(dout[1:0]) | |
1574 | ); | |
1575 | ||
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | endmodule | |
1588 | ||
1589 | ||
1590 | ||
1591 | ||
1592 | ||
1593 | ||
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | // any PARAMS parms go into naming of macro | |
1602 | ||
1603 | module sio_mb0_ctl_msff_ctl_macro__width_68 ( | |
1604 | din, | |
1605 | l1clk, | |
1606 | scan_in, | |
1607 | siclk, | |
1608 | soclk, | |
1609 | dout, | |
1610 | scan_out); | |
1611 | wire [67:0] fdin; | |
1612 | wire [66:0] so; | |
1613 | ||
1614 | input [67:0] din; | |
1615 | input l1clk; | |
1616 | input scan_in; | |
1617 | ||
1618 | ||
1619 | input siclk; | |
1620 | input soclk; | |
1621 | ||
1622 | output [67:0] dout; | |
1623 | output scan_out; | |
1624 | assign fdin[67:0] = din[67:0]; | |
1625 | ||
1626 | ||
1627 | ||
1628 | ||
1629 | ||
1630 | ||
1631 | dff #(68) d0_0 ( | |
1632 | .l1clk(l1clk), | |
1633 | .siclk(siclk), | |
1634 | .soclk(soclk), | |
1635 | .d(fdin[67:0]), | |
1636 | .si({scan_in,so[66:0]}), | |
1637 | .so({so[66:0],scan_out}), | |
1638 | .q(dout[67:0]) | |
1639 | ); | |
1640 | ||
1641 | ||
1642 | ||
1643 | ||
1644 | ||
1645 | ||
1646 | ||
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | ||
1652 | endmodule | |
1653 | ||
1654 | ||
1655 | ||
1656 | ||
1657 | ||
1658 | ||
1659 | ||
1660 | ||
1661 | ||
1662 | ||
1663 | ||
1664 | ||
1665 | ||
1666 | // any PARAMS parms go into naming of macro | |
1667 | ||
1668 | module sio_mb0_ctl_msff_ctl_macro__width_20 ( | |
1669 | din, | |
1670 | l1clk, | |
1671 | scan_in, | |
1672 | siclk, | |
1673 | soclk, | |
1674 | dout, | |
1675 | scan_out); | |
1676 | wire [19:0] fdin; | |
1677 | wire [18:0] so; | |
1678 | ||
1679 | input [19:0] din; | |
1680 | input l1clk; | |
1681 | input scan_in; | |
1682 | ||
1683 | ||
1684 | input siclk; | |
1685 | input soclk; | |
1686 | ||
1687 | output [19:0] dout; | |
1688 | output scan_out; | |
1689 | assign fdin[19:0] = din[19:0]; | |
1690 | ||
1691 | ||
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 | dff #(20) d0_0 ( | |
1697 | .l1clk(l1clk), | |
1698 | .siclk(siclk), | |
1699 | .soclk(soclk), | |
1700 | .d(fdin[19:0]), | |
1701 | .si({scan_in,so[18:0]}), | |
1702 | .so({so[18:0],scan_out}), | |
1703 | .q(dout[19:0]) | |
1704 | ); | |
1705 | ||
1706 | ||
1707 | ||
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | endmodule | |
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | ||
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | // Description: Spare gate macro for control blocks | |
1728 | // | |
1729 | // Param num controls the number of times the macro is added | |
1730 | // flops=0 can be used to use only combination spare logic | |
1731 | ||
1732 | ||
1733 | module sio_mb0_ctl_spare_ctl_macro__num_3 ( | |
1734 | l1clk, | |
1735 | scan_in, | |
1736 | siclk, | |
1737 | soclk, | |
1738 | scan_out); | |
1739 | wire si_0; | |
1740 | wire so_0; | |
1741 | wire spare0_flop_unused; | |
1742 | wire spare0_buf_32x_unused; | |
1743 | wire spare0_nand3_8x_unused; | |
1744 | wire spare0_inv_8x_unused; | |
1745 | wire spare0_aoi22_4x_unused; | |
1746 | wire spare0_buf_8x_unused; | |
1747 | wire spare0_oai22_4x_unused; | |
1748 | wire spare0_inv_16x_unused; | |
1749 | wire spare0_nand2_16x_unused; | |
1750 | wire spare0_nor3_4x_unused; | |
1751 | wire spare0_nand2_8x_unused; | |
1752 | wire spare0_buf_16x_unused; | |
1753 | wire spare0_nor2_16x_unused; | |
1754 | wire spare0_inv_32x_unused; | |
1755 | wire si_1; | |
1756 | wire so_1; | |
1757 | wire spare1_flop_unused; | |
1758 | wire spare1_buf_32x_unused; | |
1759 | wire spare1_nand3_8x_unused; | |
1760 | wire spare1_inv_8x_unused; | |
1761 | wire spare1_aoi22_4x_unused; | |
1762 | wire spare1_buf_8x_unused; | |
1763 | wire spare1_oai22_4x_unused; | |
1764 | wire spare1_inv_16x_unused; | |
1765 | wire spare1_nand2_16x_unused; | |
1766 | wire spare1_nor3_4x_unused; | |
1767 | wire spare1_nand2_8x_unused; | |
1768 | wire spare1_buf_16x_unused; | |
1769 | wire spare1_nor2_16x_unused; | |
1770 | wire spare1_inv_32x_unused; | |
1771 | wire si_2; | |
1772 | wire so_2; | |
1773 | wire spare2_flop_unused; | |
1774 | wire spare2_buf_32x_unused; | |
1775 | wire spare2_nand3_8x_unused; | |
1776 | wire spare2_inv_8x_unused; | |
1777 | wire spare2_aoi22_4x_unused; | |
1778 | wire spare2_buf_8x_unused; | |
1779 | wire spare2_oai22_4x_unused; | |
1780 | wire spare2_inv_16x_unused; | |
1781 | wire spare2_nand2_16x_unused; | |
1782 | wire spare2_nor3_4x_unused; | |
1783 | wire spare2_nand2_8x_unused; | |
1784 | wire spare2_buf_16x_unused; | |
1785 | wire spare2_nor2_16x_unused; | |
1786 | wire spare2_inv_32x_unused; | |
1787 | ||
1788 | ||
1789 | input l1clk; | |
1790 | input scan_in; | |
1791 | input siclk; | |
1792 | input soclk; | |
1793 | output scan_out; | |
1794 | ||
1795 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1796 | .siclk(siclk), | |
1797 | .soclk(soclk), | |
1798 | .si(si_0), | |
1799 | .so(so_0), | |
1800 | .d(1'b0), | |
1801 | .q(spare0_flop_unused)); | |
1802 | assign si_0 = scan_in; | |
1803 | ||
1804 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1805 | .out(spare0_buf_32x_unused)); | |
1806 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1807 | .in1(1'b1), | |
1808 | .in2(1'b1), | |
1809 | .out(spare0_nand3_8x_unused)); | |
1810 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1811 | .out(spare0_inv_8x_unused)); | |
1812 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1813 | .in01(1'b1), | |
1814 | .in10(1'b1), | |
1815 | .in11(1'b1), | |
1816 | .out(spare0_aoi22_4x_unused)); | |
1817 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1818 | .out(spare0_buf_8x_unused)); | |
1819 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1820 | .in01(1'b1), | |
1821 | .in10(1'b1), | |
1822 | .in11(1'b1), | |
1823 | .out(spare0_oai22_4x_unused)); | |
1824 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1825 | .out(spare0_inv_16x_unused)); | |
1826 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1827 | .in1(1'b1), | |
1828 | .out(spare0_nand2_16x_unused)); | |
1829 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1830 | .in1(1'b0), | |
1831 | .in2(1'b0), | |
1832 | .out(spare0_nor3_4x_unused)); | |
1833 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1834 | .in1(1'b1), | |
1835 | .out(spare0_nand2_8x_unused)); | |
1836 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1837 | .out(spare0_buf_16x_unused)); | |
1838 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1839 | .in1(1'b0), | |
1840 | .out(spare0_nor2_16x_unused)); | |
1841 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1842 | .out(spare0_inv_32x_unused)); | |
1843 | ||
1844 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1845 | .siclk(siclk), | |
1846 | .soclk(soclk), | |
1847 | .si(si_1), | |
1848 | .so(so_1), | |
1849 | .d(1'b0), | |
1850 | .q(spare1_flop_unused)); | |
1851 | assign si_1 = so_0; | |
1852 | ||
1853 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1854 | .out(spare1_buf_32x_unused)); | |
1855 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1856 | .in1(1'b1), | |
1857 | .in2(1'b1), | |
1858 | .out(spare1_nand3_8x_unused)); | |
1859 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1860 | .out(spare1_inv_8x_unused)); | |
1861 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1862 | .in01(1'b1), | |
1863 | .in10(1'b1), | |
1864 | .in11(1'b1), | |
1865 | .out(spare1_aoi22_4x_unused)); | |
1866 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1867 | .out(spare1_buf_8x_unused)); | |
1868 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1869 | .in01(1'b1), | |
1870 | .in10(1'b1), | |
1871 | .in11(1'b1), | |
1872 | .out(spare1_oai22_4x_unused)); | |
1873 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1874 | .out(spare1_inv_16x_unused)); | |
1875 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1876 | .in1(1'b1), | |
1877 | .out(spare1_nand2_16x_unused)); | |
1878 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1879 | .in1(1'b0), | |
1880 | .in2(1'b0), | |
1881 | .out(spare1_nor3_4x_unused)); | |
1882 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1883 | .in1(1'b1), | |
1884 | .out(spare1_nand2_8x_unused)); | |
1885 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1886 | .out(spare1_buf_16x_unused)); | |
1887 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1888 | .in1(1'b0), | |
1889 | .out(spare1_nor2_16x_unused)); | |
1890 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1891 | .out(spare1_inv_32x_unused)); | |
1892 | ||
1893 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
1894 | .siclk(siclk), | |
1895 | .soclk(soclk), | |
1896 | .si(si_2), | |
1897 | .so(so_2), | |
1898 | .d(1'b0), | |
1899 | .q(spare2_flop_unused)); | |
1900 | assign si_2 = so_1; | |
1901 | ||
1902 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
1903 | .out(spare2_buf_32x_unused)); | |
1904 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
1905 | .in1(1'b1), | |
1906 | .in2(1'b1), | |
1907 | .out(spare2_nand3_8x_unused)); | |
1908 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
1909 | .out(spare2_inv_8x_unused)); | |
1910 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
1911 | .in01(1'b1), | |
1912 | .in10(1'b1), | |
1913 | .in11(1'b1), | |
1914 | .out(spare2_aoi22_4x_unused)); | |
1915 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
1916 | .out(spare2_buf_8x_unused)); | |
1917 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
1918 | .in01(1'b1), | |
1919 | .in10(1'b1), | |
1920 | .in11(1'b1), | |
1921 | .out(spare2_oai22_4x_unused)); | |
1922 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
1923 | .out(spare2_inv_16x_unused)); | |
1924 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
1925 | .in1(1'b1), | |
1926 | .out(spare2_nand2_16x_unused)); | |
1927 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
1928 | .in1(1'b0), | |
1929 | .in2(1'b0), | |
1930 | .out(spare2_nor3_4x_unused)); | |
1931 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
1932 | .in1(1'b1), | |
1933 | .out(spare2_nand2_8x_unused)); | |
1934 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
1935 | .out(spare2_buf_16x_unused)); | |
1936 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
1937 | .in1(1'b0), | |
1938 | .out(spare2_nor2_16x_unused)); | |
1939 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
1940 | .out(spare2_inv_32x_unused)); | |
1941 | assign scan_out = so_2; | |
1942 | ||
1943 | ||
1944 | ||
1945 | endmodule | |
1946 |