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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: sio_old_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module sio_old_dp ( | |
36 | l2clk, | |
37 | din, | |
38 | parity, | |
39 | ue, | |
40 | olc_oldue_check_clrerr, | |
41 | olc_oldue_check_en, | |
42 | olc_oldue_wr_en, | |
43 | olc_oldue_rd_addr, | |
44 | oldhq_dout_r_bit, | |
45 | oldhq_dout_s_bit, | |
46 | olddq0_dout, | |
47 | olddq1_dout, | |
48 | olc_old_selhdr, | |
49 | olc_oldue_selfwd, | |
50 | olc_oldue_pass_late_ue, | |
51 | old_opd_data, | |
52 | olc_oldhq_wr_en, | |
53 | olc_oldhq_rd_addr, | |
54 | oldhq_din, | |
55 | ojc_old_jtagsr_en, | |
56 | ojc_old_wr_en, | |
57 | old_opcc_jtag, | |
58 | sio_mbi_run, | |
59 | sio_mbi_old_addr, | |
60 | sio_mbi_old_wdata, | |
61 | sio_mbi_oldx_wr_en, | |
62 | sio_mbi_oldx_rd_en, | |
63 | olc_old_olddqx0_wr_en, | |
64 | olc_old_olddqx0_rd_en, | |
65 | olc_old_olddqx0_waddr, | |
66 | olc_old_olddqx0_raddr, | |
67 | olc_old_olddqx1_wr_en, | |
68 | olc_old_olddqx1_rd_en, | |
69 | olc_old_olddqx1_waddr, | |
70 | olc_old_olddqx1_raddr, | |
71 | old_olddqx0_wr_en, | |
72 | old_olddqx0_rd_en, | |
73 | old_olddqx0_waddr, | |
74 | old_olddqx0_raddr, | |
75 | old_olddqx0_din, | |
76 | old_olddqx1_wr_en, | |
77 | old_olddqx1_rd_en, | |
78 | old_olddqx1_waddr, | |
79 | old_olddqx1_raddr, | |
80 | old_olddqx1_din, | |
81 | tcu_muxtest, | |
82 | tcu_dectest, | |
83 | tcu_scan_en, | |
84 | scan_in, | |
85 | tcu_aclk, | |
86 | tcu_bclk, | |
87 | tcu_pce_ov, | |
88 | tcu_clk_stop, | |
89 | scan_out); | |
90 | wire muxtst; | |
91 | wire test; | |
92 | wire se; | |
93 | wire siclk; | |
94 | wire soclk; | |
95 | wire pce_ov; | |
96 | wire stop; | |
97 | wire [33:0] olddqx0_din; | |
98 | wire [33:0] olddqx1_din; | |
99 | wire dff_in_sol0_scanin; | |
100 | wire dff_in_sol0_scanout; | |
101 | wire ue_sol0; | |
102 | wire parity1_sol0; | |
103 | wire parity0_sol0; | |
104 | wire [31:0] in_sol0; | |
105 | wire paritygen1_sol0; | |
106 | wire paritygen0_sol0; | |
107 | wire perr1_sol0; | |
108 | wire perr0_sol0; | |
109 | wire passperr_sol0; | |
110 | wire perr_sol1; | |
111 | wire olderr_sol0; | |
112 | wire setperr_sol0; | |
113 | wire perr_sol0; | |
114 | wire eff_perr_sol1_scanin; | |
115 | wire eff_perr_sol1_scanout; | |
116 | wire ue0_wren_sol1; | |
117 | wire ue1_wren_sol1; | |
118 | wire ue2_wren_sol1; | |
119 | wire ue3_wren_sol1; | |
120 | wire eff_ue0_sol2_scanin; | |
121 | wire eff_ue0_sol2_scanout; | |
122 | wire ue0_sol2; | |
123 | wire eff_ue1_sol2_scanin; | |
124 | wire eff_ue1_sol2_scanout; | |
125 | wire ue1_sol2; | |
126 | wire eff_ue2_sol2_scanin; | |
127 | wire eff_ue2_sol2_scanout; | |
128 | wire ue2_sol2; | |
129 | wire eff_ue3_sol2_scanin; | |
130 | wire eff_ue3_sol2_scanout; | |
131 | wire ue3_sol2; | |
132 | wire ue41_out; | |
133 | wire ue_out; | |
134 | wire ue_h_l; | |
135 | wire [5:0] hqsyndromeout; | |
136 | wire [5:0] hqctageccout; | |
137 | wire hqraseout; | |
138 | wire hqrout; | |
139 | wire [15:0] hqtagout; | |
140 | wire [25:0] oldhq_dout; | |
141 | wire [24:0] mem0; | |
142 | wire [24:0] mem1; | |
143 | wire [24:0] mem2; | |
144 | wire [24:0] mem3; | |
145 | wire oldhq_dout_e_bit; | |
146 | wire ff_hqout_scanin; | |
147 | wire ff_hqout_scanout; | |
148 | wire [5:0] ctag_syndrome; | |
149 | wire hqwe0; | |
150 | wire hqwe1; | |
151 | wire hqwe2; | |
152 | wire hqwe3; | |
153 | wire ff_hqmem0_scanin; | |
154 | wire ff_hqmem0_scanout; | |
155 | wire mem0_unused; | |
156 | wire ff_hqmem1_scanin; | |
157 | wire ff_hqmem1_scanout; | |
158 | wire mem1_unused; | |
159 | wire ff_hqmem2_scanin; | |
160 | wire ff_hqmem2_scanout; | |
161 | wire mem2_unused; | |
162 | wire ff_hqmem3_scanin; | |
163 | wire ff_hqmem3_scanout; | |
164 | wire mem3_unused; | |
165 | wire eff_jtagsr_h_scanin; | |
166 | wire eff_jtagsr_h_scanout; | |
167 | wire [63:0] in_jtag; | |
168 | wire [63:0] out_jtag; | |
169 | wire eff_jtagsr_scanin; | |
170 | wire eff_jtagsr_scanout; | |
171 | wire [63:0] in_jtag_temp; | |
172 | ||
173 | ||
174 | input l2clk; | |
175 | input [31:0] din; // from l2b...goes to mbist muxes and flops for sol0 stage | |
176 | input [1:0] parity; | |
177 | input ue; | |
178 | input olc_oldue_check_clrerr; // start of parity checking -- clear out any prior error state | |
179 | input olc_oldue_check_en; // flop-enable for the parity error accumulator | |
180 | input [3:0] olc_oldue_wr_en; // write enable for UE fifo | |
181 | ||
182 | input [1:0] olc_oldue_rd_addr; // read pointer for UE fifo | |
183 | output oldhq_dout_r_bit; // header out {read} | |
184 | output oldhq_dout_s_bit; // header out {source=dmu} | |
185 | input [33:0] olddq0_dout; // least significant bits of data cycle | |
186 | input [33:0] olddq1_dout; // most significant bits of data cycle | |
187 | input olc_old_selhdr; // select header not data as outputs | |
188 | input olc_oldue_selfwd; // selects the accumulated ue instead of the set of 4 ue flops | |
189 | input olc_oldue_pass_late_ue; // | |
190 | output [64:0] old_opd_data; | |
191 | ||
192 | ||
193 | input [3:0] olc_oldhq_wr_en; // write-enable | |
194 | input [ 1:0] olc_oldhq_rd_addr; // read-addr | |
195 | input [24:0] oldhq_din; // header datain - {ctagecc[5:0], ras_ue, read, dmu, id[15:0]} | |
196 | ||
197 | input ojc_old_jtagsr_en; // either store the jtag read data or | |
198 | // shift.... | |
199 | // shift bits [n:1] into [n-1:0] | |
200 | // shift in a 0 to the tail [n] | |
201 | ||
202 | input [1:0] ojc_old_wr_en; // store the jtag read data, | |
203 | // [1]=push 8Bytes to head(63:32), [0]=push 8Bytes to tail | |
204 | ||
205 | output old_opcc_jtag; // lsb of jtag shift register | |
206 | ||
207 | input sio_mbi_run; | |
208 | input [4:0] sio_mbi_old_addr; | |
209 | input [7:0] sio_mbi_old_wdata; | |
210 | input sio_mbi_oldx_wr_en; | |
211 | input sio_mbi_oldx_rd_en; | |
212 | ||
213 | input olc_old_olddqx0_wr_en; | |
214 | input olc_old_olddqx0_rd_en; | |
215 | input [4:0] olc_old_olddqx0_waddr; | |
216 | input [4:0] olc_old_olddqx0_raddr; | |
217 | ||
218 | ||
219 | ||
220 | input olc_old_olddqx1_wr_en; | |
221 | input olc_old_olddqx1_rd_en; | |
222 | input [4:0] olc_old_olddqx1_waddr; | |
223 | input [4:0] olc_old_olddqx1_raddr; | |
224 | ||
225 | output old_olddqx0_wr_en; | |
226 | output old_olddqx0_rd_en; | |
227 | output [4:0] old_olddqx0_waddr; | |
228 | output [4:0] old_olddqx0_raddr; | |
229 | output [33:0] old_olddqx0_din; | |
230 | ||
231 | output old_olddqx1_wr_en; | |
232 | output old_olddqx1_rd_en; | |
233 | output [4:0] old_olddqx1_waddr; | |
234 | output [4:0] old_olddqx1_raddr; | |
235 | output [33:0] old_olddqx1_din; | |
236 | ||
237 | input tcu_muxtest; | |
238 | input tcu_dectest; | |
239 | input tcu_scan_en; | |
240 | ||
241 | input scan_in; | |
242 | input tcu_aclk; | |
243 | input tcu_bclk; | |
244 | input tcu_pce_ov; | |
245 | input tcu_clk_stop; | |
246 | output scan_out; | |
247 | ||
248 | /////////////////////////////////////// | |
249 | // Scan chain connections | |
250 | /////////////////////////////////////// | |
251 | // scan renames | |
252 | assign muxtst = tcu_muxtest; | |
253 | assign test = tcu_dectest; | |
254 | assign se = tcu_scan_en; | |
255 | ||
256 | assign siclk = tcu_aclk; | |
257 | assign soclk = tcu_bclk; | |
258 | assign pce_ov = tcu_pce_ov; | |
259 | assign stop = tcu_clk_stop; | |
260 | // end scan | |
261 | ||
262 | assign olddqx0_din[33:0] = {1'b0, ue, din[31:0]}; | |
263 | assign olddqx1_din[33:0] = {1'b0, ue, din[31:0]}; | |
264 | ||
265 | /////////////////////////////////////// | |
266 | // | |
267 | // BEGIN MUXES for MBIST | |
268 | // | |
269 | /////////////////////////////////////// | |
270 | sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 mx21_mbi_olddqx0 ( | |
271 | .dout ({old_olddqx0_wr_en, | |
272 | old_olddqx0_rd_en, | |
273 | old_olddqx0_waddr[4:0], | |
274 | old_olddqx0_raddr[4:0], | |
275 | old_olddqx0_din[33:0]}), | |
276 | ||
277 | .din0 ({sio_mbi_oldx_wr_en, | |
278 | sio_mbi_oldx_rd_en, | |
279 | sio_mbi_old_addr[4:0], | |
280 | sio_mbi_old_addr[4:0], | |
281 | {sio_mbi_old_wdata[1:0], {4{sio_mbi_old_wdata[7:0]}}}}), | |
282 | ||
283 | .din1 ({olc_old_olddqx0_wr_en, | |
284 | olc_old_olddqx0_rd_en, | |
285 | olc_old_olddqx0_waddr[4:0], | |
286 | olc_old_olddqx0_raddr[4:0], | |
287 | olddqx0_din[33:0]}), | |
288 | ||
289 | .sel0 (sio_mbi_run) | |
290 | ); | |
291 | ||
292 | sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 mx21_mbi_olddqx1 ( | |
293 | .dout ({old_olddqx1_wr_en, | |
294 | old_olddqx1_rd_en, | |
295 | old_olddqx1_waddr[4:0], | |
296 | old_olddqx1_raddr[4:0], | |
297 | old_olddqx1_din[33:0]}), | |
298 | ||
299 | .din0 ({sio_mbi_oldx_wr_en, | |
300 | sio_mbi_oldx_rd_en, | |
301 | sio_mbi_old_addr[4:0], | |
302 | sio_mbi_old_addr[4:0], | |
303 | {sio_mbi_old_wdata[1:0], {4{sio_mbi_old_wdata[7:0]}}}}), | |
304 | ||
305 | .din1 ({olc_old_olddqx1_wr_en, | |
306 | olc_old_olddqx1_rd_en, | |
307 | olc_old_olddqx1_waddr[4:0], | |
308 | olc_old_olddqx1_raddr[4:0], | |
309 | olddqx1_din[33:0]}), | |
310 | ||
311 | .sel0 (sio_mbi_run) | |
312 | ); | |
313 | ||
314 | /////////////////////////////////////// | |
315 | // | |
316 | // END MUXES for MBIST | |
317 | // | |
318 | /////////////////////////////////////// | |
319 | ||
320 | /////////////////////////////////////// | |
321 | // | |
322 | // CAPTURE FLOPS for parity, ue and din | |
323 | // -- sol0 cycle | |
324 | // | |
325 | /////////////////////////////////////// | |
326 | ||
327 | ||
328 | sio_old_dp_msff_macro__stack_64c__width_35 dff_in_sol0 ( | |
329 | .scan_in(dff_in_sol0_scanin), | |
330 | .scan_out(dff_in_sol0_scanout), | |
331 | .clk (l2clk), | |
332 | .din ({ue, parity[1:0],din[31:0]}), | |
333 | .dout ({ue_sol0,parity1_sol0, parity0_sol0,in_sol0[31:0]}), | |
334 | .en (1'b1), | |
335 | .se(se), | |
336 | .siclk(siclk), | |
337 | .soclk(soclk), | |
338 | .pce_ov(pce_ov), | |
339 | .stop(stop) | |
340 | ); | |
341 | ||
342 | ||
343 | /////////////////////////////////////// | |
344 | // | |
345 | // DATA PARITY GENERATION for checking | |
346 | // | |
347 | /////////////////////////////////////// | |
348 | ||
349 | sio_old_dp_prty_macro__width_16 prty_pgen1_sol0 ( | |
350 | .din (in_sol0[31:16]), | |
351 | .dout (paritygen1_sol0) | |
352 | ); | |
353 | ||
354 | sio_old_dp_prty_macro__width_16 prty_pgen0_sol0 ( | |
355 | .din (in_sol0[15: 0]), | |
356 | .dout (paritygen0_sol0) | |
357 | ); | |
358 | ||
359 | ||
360 | /////////////////////////////////////// | |
361 | // | |
362 | // DATA PARITY COMPARISON | |
363 | // | |
364 | /////////////////////////////////////// | |
365 | ||
366 | ||
367 | sio_old_dp_xor_macro__left_1__stack_4r__width_1 xr2_perr1_sol0 ( | |
368 | .din0 (paritygen1_sol0), | |
369 | .din1 (parity1_sol0), | |
370 | .dout (perr1_sol0) | |
371 | ); | |
372 | ||
373 | sio_old_dp_xor_macro__left_0__stack_4r__width_1 xr2_perr0_sol0 ( | |
374 | .din0 (paritygen0_sol0), | |
375 | .din1 (parity0_sol0), | |
376 | .dout (perr0_sol0) | |
377 | ); | |
378 | ||
379 | ||
380 | ||
381 | /////////////////////////////////////// | |
382 | // | |
383 | // DATA Parity error logging CONTROL | |
384 | // | |
385 | /////////////////////////////////////// | |
386 | ||
387 | ||
388 | sio_old_dp_inv_macro__left_0__stack_4r__width_1 inv_passperr_sol0 ( | |
389 | .din (olc_oldue_check_clrerr), | |
390 | .dout (passperr_sol0) | |
391 | ); | |
392 | ||
393 | sio_old_dp_nand_macro__left_0__stack_4r__width_1 nd2_olderr_sol0 ( | |
394 | .din0 (passperr_sol0), | |
395 | .din1 (perr_sol1), | |
396 | .dout (olderr_sol0) | |
397 | ); | |
398 | ||
399 | sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1 nr3_setperr_sol0 ( | |
400 | .din0 (perr1_sol0), | |
401 | .din1 (perr0_sol0), | |
402 | .din2 (ue_sol0), | |
403 | .dout (setperr_sol0) | |
404 | ); | |
405 | ||
406 | sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1 nd2_perr_sol0 ( | |
407 | .din0 (setperr_sol0), | |
408 | .din1 (olderr_sol0), | |
409 | .dout (perr_sol0) | |
410 | ); | |
411 | ||
412 | /////////////////////////////////////// | |
413 | // | |
414 | // DATA Parity error RESULT FLOP | |
415 | // | |
416 | /////////////////////////////////////// | |
417 | ||
418 | ||
419 | ||
420 | sio_old_dp_msff_macro__left_0__stack_4r__width_1 eff_perr_sol1 ( | |
421 | .scan_in(eff_perr_sol1_scanin), | |
422 | .scan_out(eff_perr_sol1_scanout), | |
423 | .clk (l2clk), | |
424 | .din (perr_sol0), | |
425 | .dout (perr_sol1), | |
426 | .en (olc_oldue_check_en), | |
427 | .se(se), | |
428 | .siclk(siclk), | |
429 | .soclk(soclk), | |
430 | .pce_ov(pce_ov), | |
431 | .stop(stop) | |
432 | ); | |
433 | ||
434 | ||
435 | ||
436 | /////////////////////////////////////// | |
437 | // | |
438 | // Uncorrectable Error (UE of datachunks) | |
439 | // FIFO MADE from FLOPS | |
440 | // | |
441 | /////////////////////////////////////// | |
442 | ||
443 | assign ue0_wren_sol1 = olc_oldue_wr_en[0]; | |
444 | assign ue1_wren_sol1 = olc_oldue_wr_en[1]; | |
445 | assign ue2_wren_sol1 = olc_oldue_wr_en[2]; | |
446 | assign ue3_wren_sol1 = olc_oldue_wr_en[3]; | |
447 | ||
448 | sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue0_sol2 ( | |
449 | .scan_in(eff_ue0_sol2_scanin), | |
450 | .scan_out(eff_ue0_sol2_scanout), | |
451 | .clk (l2clk), | |
452 | .din (perr_sol1), | |
453 | .dout (ue0_sol2), | |
454 | .en (ue0_wren_sol1), | |
455 | .se(se), | |
456 | .siclk(siclk), | |
457 | .soclk(soclk), | |
458 | .pce_ov(pce_ov), | |
459 | .stop(stop) | |
460 | ); | |
461 | ||
462 | sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue1_sol2 ( | |
463 | .scan_in(eff_ue1_sol2_scanin), | |
464 | .scan_out(eff_ue1_sol2_scanout), | |
465 | .clk (l2clk), | |
466 | .din (perr_sol1), | |
467 | .dout (ue1_sol2), | |
468 | .en (ue1_wren_sol1), | |
469 | .se(se), | |
470 | .siclk(siclk), | |
471 | .soclk(soclk), | |
472 | .pce_ov(pce_ov), | |
473 | .stop(stop) | |
474 | ); | |
475 | ||
476 | sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue2_sol2 ( | |
477 | .scan_in(eff_ue2_sol2_scanin), | |
478 | .scan_out(eff_ue2_sol2_scanout), | |
479 | .clk (l2clk), | |
480 | .din (perr_sol1), | |
481 | .dout (ue2_sol2), | |
482 | .en (ue2_wren_sol1), | |
483 | .se(se), | |
484 | .siclk(siclk), | |
485 | .soclk(soclk), | |
486 | .pce_ov(pce_ov), | |
487 | .stop(stop) | |
488 | ); | |
489 | ||
490 | ||
491 | sio_old_dp_msff_macro__left_0__stack_2r__width_1 eff_ue3_sol2 ( | |
492 | .scan_in(eff_ue3_sol2_scanin), | |
493 | .scan_out(eff_ue3_sol2_scanout), | |
494 | .clk (l2clk), | |
495 | .din (perr_sol1), | |
496 | .dout (ue3_sol2), | |
497 | .en (ue3_wren_sol1), | |
498 | .se(se), | |
499 | .siclk(siclk), | |
500 | .soclk(soclk), | |
501 | .pce_ov(pce_ov), | |
502 | .stop(stop) | |
503 | ); | |
504 | ||
505 | ||
506 | // 4:1 mux for reading out ue ff | |
507 | ||
508 | sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1 mx41_ue41out ( | |
509 | .dout (ue41_out), | |
510 | .din0 (ue0_sol2), | |
511 | .din1 (ue1_sol2), | |
512 | .din2 (ue2_sol2), | |
513 | .din3 (ue3_sol2), | |
514 | .sel (olc_oldue_rd_addr[1:0]), | |
515 | .muxtst(muxtst), | |
516 | .test(test) | |
517 | ); | |
518 | ||
519 | // mux_macro mx21_hdrueout (width=1, stack=2r, mux=pgpe, ports=2) ( | |
520 | // .dout (ue_out), | |
521 | // .din0 (perr_sol1), | |
522 | // .din1 (ue41_out), | |
523 | // .sel0 (olc_oldue_selfwd) | |
524 | // ); | |
525 | ||
526 | assign ue_out = olc_oldue_pass_late_ue; | |
527 | ||
528 | ||
529 | /////////////////////////////////////// | |
530 | // | |
531 | // OLD DP OUTPUT MUX for data to opd | |
532 | // | |
533 | /////////////////////////////////////// | |
534 | // | |
535 | // output mux between header and payload | |
536 | // | |
537 | /////////////////////////////////////// | |
538 | ||
539 | assign old_opd_data[64:32] ={ue_h_l, olddq0_dout[31:0]}; | |
540 | ||
541 | sio_old_dp_or_macro__stack_2l__width_1 or_ue ( | |
542 | .dout (ue_h_l), | |
543 | .din0 (olddq0_dout[32]), | |
544 | .din1 (olddq1_dout[32]) | |
545 | ); | |
546 | ||
547 | sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32 mx21_old_opd_data ( | |
548 | .dout (old_opd_data[31:0]), | |
549 | .din0 ({hqsyndromeout[5:0], hqctageccout[5:0], hqraseout, 1'b0, hqrout, ue_out, hqtagout[15:0]}), | |
550 | .din1 ({olddq1_dout[31:0]}), | |
551 | .sel0 (olc_old_selhdr) | |
552 | ); | |
553 | ||
554 | ||
555 | ||
556 | /////////////////////////////////////// | |
557 | // | |
558 | // HEADER QUEUE (HQ) | |
559 | // FIFO MADE from FLOPS | |
560 | // with an output flop on fifo | |
561 | // | |
562 | // entry : msb:lsb = {ctagecc[5:0], ras_ue, | |
563 | // read, src, ctag[15:0]} | |
564 | /////////////////////////////////////// | |
565 | ||
566 | // | |
567 | // read select of hq | |
568 | // | |
569 | sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26 hqout ( | |
570 | .dout (oldhq_dout[25:0]), | |
571 | .din0 ({1'b0, mem0[24:0]}), | |
572 | .din1 ({1'b0, mem1[24:0]}), | |
573 | .din2 ({1'b0, mem2[24:0]}), | |
574 | .din3 ({1'b0, mem3[24:0]}), | |
575 | .sel (olc_oldhq_rd_addr[1:0]), | |
576 | .muxtst(muxtst), | |
577 | .test(test) | |
578 | ); | |
579 | ||
580 | assign oldhq_dout_r_bit = oldhq_dout[17]; // header out {read} | |
581 | assign oldhq_dout_s_bit = oldhq_dout[16]; // header out {source=dmu} | |
582 | assign oldhq_dout_e_bit = oldhq_dout[18]; // header out {E bit = l2[21]} | |
583 | ||
584 | // FLOP THIS TO LINE UP THE HQ and PAYLOAD QUEUE READ PIPELINE | |
585 | // and so we can look ahead in the header generation logic | |
586 | ||
587 | sio_old_dp_msff_macro__stack_32l__width_30 ff_hqout ( | |
588 | .scan_in(ff_hqout_scanin), | |
589 | .scan_out(ff_hqout_scanout), | |
590 | .clk (l2clk), | |
591 | .din ({ctag_syndrome[5:0], oldhq_dout[24:19], oldhq_dout[18], oldhq_dout[17], oldhq_dout[15:0]}), | |
592 | .dout ({hqsyndromeout[5:0], hqctageccout[5:0], hqraseout, hqrout, hqtagout[15:0]}), | |
593 | .en (1'b1), | |
594 | .se(se), | |
595 | .siclk(siclk), | |
596 | .soclk(soclk), | |
597 | .pce_ov(pce_ov), | |
598 | .stop(stop) | |
599 | ); | |
600 | ||
601 | ||
602 | assign hqwe0 = olc_oldhq_wr_en[0]; | |
603 | assign hqwe1 = olc_oldhq_wr_en[1]; | |
604 | assign hqwe2 = olc_oldhq_wr_en[2]; | |
605 | assign hqwe3 = olc_oldhq_wr_en[3]; | |
606 | ||
607 | ||
608 | ///////////////////////////////////////////////////// | |
609 | // Array Flops | |
610 | ///////////////////////////////////////////////////// | |
611 | ||
612 | sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem0 ( | |
613 | .scan_in(ff_hqmem0_scanin), | |
614 | .scan_out(ff_hqmem0_scanout), | |
615 | .clk (l2clk), | |
616 | .din ({1'b0, oldhq_din[24:0]}), | |
617 | .dout ({mem0_unused, mem0[24:0]}), | |
618 | .en (hqwe0), | |
619 | .se(se), | |
620 | .siclk(siclk), | |
621 | .soclk(soclk), | |
622 | .pce_ov(pce_ov), | |
623 | .stop(stop) | |
624 | ); | |
625 | ||
626 | sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem1 ( | |
627 | .scan_in(ff_hqmem1_scanin), | |
628 | .scan_out(ff_hqmem1_scanout), | |
629 | .clk (l2clk), | |
630 | .din ({1'b0, oldhq_din[24:0]}), | |
631 | .dout ({mem1_unused, mem1[24:0]}), | |
632 | .en (hqwe1), | |
633 | .se(se), | |
634 | .siclk(siclk), | |
635 | .soclk(soclk), | |
636 | .pce_ov(pce_ov), | |
637 | .stop(stop) | |
638 | ); | |
639 | ||
640 | sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem2 ( | |
641 | .scan_in(ff_hqmem2_scanin), | |
642 | .scan_out(ff_hqmem2_scanout), | |
643 | .clk (l2clk), | |
644 | .din ({1'b0, oldhq_din[24:0]}), | |
645 | .dout ({mem2_unused, mem2[24:0]}), | |
646 | .en (hqwe2), | |
647 | .se(se), | |
648 | .siclk(siclk), | |
649 | .soclk(soclk), | |
650 | .pce_ov(pce_ov), | |
651 | .stop(stop) | |
652 | ); | |
653 | ||
654 | sio_old_dp_msff_macro__stack_26l__width_26 ff_hqmem3 ( | |
655 | .scan_in(ff_hqmem3_scanin), | |
656 | .scan_out(ff_hqmem3_scanout), | |
657 | .clk (l2clk), | |
658 | .din ({1'b0, oldhq_din[24:0]}), | |
659 | .dout ({mem3_unused, mem3[24:0]}), | |
660 | .en (hqwe3), | |
661 | .se(se), | |
662 | .siclk(siclk), | |
663 | .soclk(soclk), | |
664 | .pce_ov(pce_ov), | |
665 | .stop(stop) | |
666 | ); | |
667 | ||
668 | ||
669 | ///////////////////////////////////////////////////// | |
670 | // | |
671 | // SHIFT REGISTERS for JTAG READ | |
672 | // | |
673 | ///////////////////////////////////////////////////// | |
674 | ||
675 | sio_old_dp_msff_macro__stack_32l__width_32 eff_jtagsr_h ( | |
676 | .scan_in(eff_jtagsr_h_scanin), | |
677 | .scan_out(eff_jtagsr_h_scanout), | |
678 | .clk (l2clk), | |
679 | .din (in_jtag[63:32]), | |
680 | .dout (out_jtag[63:32]), | |
681 | .en (ojc_old_jtagsr_en), | |
682 | .se(se), | |
683 | .siclk(siclk), | |
684 | .soclk(soclk), | |
685 | .pce_ov(pce_ov), | |
686 | .stop(stop) | |
687 | ); | |
688 | ||
689 | sio_old_dp_msff_macro__stack_32l__width_32 eff_jtagsr_l ( | |
690 | .scan_in(eff_jtagsr_scanin), | |
691 | .scan_out(eff_jtagsr_scanout), | |
692 | .clk (l2clk), | |
693 | .din (in_jtag[31:0]), | |
694 | .dout (out_jtag[31:0]), | |
695 | .en (ojc_old_jtagsr_en), | |
696 | .se(se), | |
697 | .siclk(siclk), | |
698 | .soclk(soclk), | |
699 | .pce_ov(pce_ov), | |
700 | .stop(stop) | |
701 | ); | |
702 | ||
703 | // format we get from l2 for 1st 2 cycle are | |
704 | // cycle 0 : in_sol0[31:0] = {B0[7:0], B1[7:0], B2[7:0], B3[7:0]} | |
705 | // cycle 1 : in_sol0[31:0] = {B4[7:0], B5[7:0], B6[7:0], B7[7:0]} | |
706 | ||
707 | // this gets loaded as | |
708 | // we[0] : in_jtag[63:32] = in_sol0[31:0] = {B0[7:0], B1[7:0], B2[7:0], B3[7:0]} | |
709 | // we[1] : in_jtag[31: 0] = in_sol0[31:0] = {B4[7:0], B5[7:0], B6[7:0], B7[7:0]} | |
710 | ||
711 | // during shift operation, the lsb is removed and everything from msb is shifted | |
712 | // downward and the msb gets a 0 | |
713 | // in_jtag[63:0] <= {1'b0, out_jtag[63:1]} ; | |
714 | ||
715 | // assign in_jtag[31: 0] = ojc_old_wr_en[1] ? in_sol0[31:0] : ( | |
716 | // out_jtag[32:1]); | |
717 | // assign in_jtag[63:32] = ojc_old_wr_en[0] ? in_sol0[31:0] : ( | |
718 | // ojc_old_wr_en[1] ? out_jtag[63:32] : {1'b0, outjtag[63:33]); | |
719 | // | |
720 | sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_in_jtag_temp ( | |
721 | .dout ({in_jtag[63:32], in_jtag[31:0]}), | |
722 | .din0 ({in_sol0[31:0], 32'h00000000}), | |
723 | .din1 ({in_jtag_temp[63:32], in_jtag_temp[31:0]}), | |
724 | .sel0 (ojc_old_wr_en[0]) | |
725 | ); | |
726 | ||
727 | sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 mx21_in_jtag ( | |
728 | .dout ({in_jtag_temp[63:32], in_jtag_temp[31:0]}), | |
729 | .din0 ({out_jtag[63:32], in_sol0[31:0]}), | |
730 | .din1 ({1'b0, out_jtag[63:33], out_jtag[32:1]}), | |
731 | .sel0 (ojc_old_wr_en[1]) | |
732 | ); | |
733 | ||
734 | assign old_opcc_jtag = out_jtag[0]; | |
735 | ||
736 | ///////////////////////////////////////////////////// | |
737 | // | |
738 | // CTAG ECC Generation (syndrome generation) | |
739 | // | |
740 | ///////////////////////////////////////////////////// | |
741 | ||
742 | // original c bits generated | |
743 | // c0 = [0] ^ [1] ^ [3] ^ [4] ^ [6] ^ [8] ^ [10] ^ [11] ^ [13] ^ [15] | |
744 | // c1 = [0] ^ [2] ^ [3] ^ [5] ^ [6] ^ [9] ^ [10] ^ [12] ^ [13] | |
745 | // c2 = [1] ^ [2] ^ [3] ^ [7] ^ [8] ^ [9] ^ [10] ^ [14] ^ [15] | |
746 | // c3 = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10] | |
747 | // c4 = [11] ^ [12] ^ [13] ^ [14] ^ [15] | |
748 | // c5 = [0] ^ [1] ^ [2] ^ [3] ^ c0 ^ c1 ^ c2 | |
749 | ||
750 | ||
751 | // s0 = [0] ^ [1] ^ [3] ^ [4] ^ [6] ^ [8] ^ [10] ^ [11] ^ [13] ^ [15] ^ c[0] | |
752 | // s1 = [0] ^ [2] ^ [3] ^ [5] ^ [6] ^ [9] ^ [10] ^ [12] ^ [13] ^ c[1] | |
753 | // s2 = [1] ^ [2] ^ [3] ^ [7] ^ [8] ^ [9] ^ [10] ^ [14] ^ [15] ^ c[2] | |
754 | // s3 = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10] ^ c[3] | |
755 | // s4 = [11] ^ [12] ^ [13] ^ [14] ^ [15] ^ c[4] | |
756 | // s5*= [0] ^ [1] ^ [2] ^ [3] ^ [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ | |
757 | // [10] ^ [11] ^ [12] ^ [13] ^ [14] ^ [15] ^ c[0] ^ c[1] ^ c[2] ^ c[3] ^ c[4] ^ c[5] | |
758 | // | |
759 | // note that implementing s5* as (22 terms) would be expensive timing and area wise... | |
760 | // so if s5 = s3 ^ s4 | |
761 | // = [4] ^ [5] ^ [6] ^ [7] ^ [8] ^ [9] ^ [10] ^ [11] ^ [12] ^ [13] ^ [14] ^ [15] | |
762 | // ^ c[3] ^ c[4] | |
763 | // | |
764 | // or s5* = s3 ^ s4 ^ [0] ^ [1] ^ [2] ^ [3] ^ [4] | |
765 | // ^ c[0] ^ c[1] ^ c[2] ^ c[5] | |
766 | // | |
767 | // we could save some gates | |
768 | ||
769 | // really 11 wide | |
770 | sio_old_dp_prty_macro__width_16 ctag_syndrome0 ( | |
771 | .din ({5'b00000, | |
772 | oldhq_dout[0], oldhq_dout[1] , oldhq_dout[3] , oldhq_dout[4] , | |
773 | oldhq_dout[6] , oldhq_dout[8] , oldhq_dout[10] , oldhq_dout[11] , | |
774 | oldhq_dout[13] , oldhq_dout[15] , oldhq_dout[19]} | |
775 | ), | |
776 | .dout (ctag_syndrome[0]) | |
777 | ); | |
778 | ||
779 | // really 10 wide | |
780 | sio_old_dp_prty_macro__width_16 ctag_syndrome1 ( | |
781 | .din ({6'b000000, | |
782 | oldhq_dout[0], oldhq_dout[2] , oldhq_dout[3] , oldhq_dout[5] , | |
783 | oldhq_dout[6] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[12] , | |
784 | oldhq_dout[13] , oldhq_dout[20]} | |
785 | ), | |
786 | .dout (ctag_syndrome[1]) | |
787 | ); | |
788 | ||
789 | // really 10 wide | |
790 | sio_old_dp_prty_macro__width_16 ctag_syndrome2 ( | |
791 | .din ({6'b000000, | |
792 | oldhq_dout[1], oldhq_dout[2] , oldhq_dout[3] , oldhq_dout[7] , | |
793 | oldhq_dout[8] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[14] , | |
794 | oldhq_dout[15] , oldhq_dout[21]} | |
795 | ), | |
796 | .dout (ctag_syndrome[2]) | |
797 | ); | |
798 | ||
799 | sio_old_dp_prty_macro__width_8 ctag_syndrome3 ( | |
800 | .din ({oldhq_dout[4], oldhq_dout[5] , oldhq_dout[6] , oldhq_dout[7] , | |
801 | oldhq_dout[8] , oldhq_dout[9] , oldhq_dout[10] , oldhq_dout[22]} | |
802 | ), | |
803 | .dout (ctag_syndrome[3]) | |
804 | ); | |
805 | ||
806 | // really 6 wide | |
807 | sio_old_dp_prty_macro__width_8 ctag_syndrome4 ( | |
808 | .din ({2'b00, | |
809 | oldhq_dout[11], oldhq_dout[12] , oldhq_dout[13] , oldhq_dout[14] , | |
810 | oldhq_dout[15] , oldhq_dout[23]} | |
811 | ), | |
812 | .dout (ctag_syndrome[4]) | |
813 | ); | |
814 | ||
815 | // really 11 wide | |
816 | sio_old_dp_prty_macro__width_16 ctag_syndrome5 ( | |
817 | .din ({5'b00000, | |
818 | oldhq_dout[0], oldhq_dout[1] , oldhq_dout[2] , oldhq_dout[3] , | |
819 | oldhq_dout[4] , oldhq_dout[24], oldhq_dout[21], oldhq_dout[20], | |
820 | oldhq_dout[19], ctag_syndrome[4], ctag_syndrome[3]} | |
821 | ), | |
822 | .dout (ctag_syndrome[5]) | |
823 | ); | |
824 | ||
825 | ||
826 | // fixscan start: | |
827 | assign dff_in_sol0_scanin = scan_in ; | |
828 | assign eff_perr_sol1_scanin = dff_in_sol0_scanout ; | |
829 | assign eff_ue0_sol2_scanin = eff_perr_sol1_scanout ; | |
830 | assign eff_ue1_sol2_scanin = eff_ue0_sol2_scanout ; | |
831 | assign eff_ue2_sol2_scanin = eff_ue1_sol2_scanout ; | |
832 | assign eff_ue3_sol2_scanin = eff_ue2_sol2_scanout ; | |
833 | assign ff_hqout_scanin = eff_ue3_sol2_scanout ; | |
834 | assign ff_hqmem0_scanin = ff_hqout_scanout ; | |
835 | assign ff_hqmem1_scanin = ff_hqmem0_scanout ; | |
836 | assign ff_hqmem2_scanin = ff_hqmem1_scanout ; | |
837 | assign ff_hqmem3_scanin = ff_hqmem2_scanout ; | |
838 | assign eff_jtagsr_h_scanin = ff_hqmem3_scanout ; | |
839 | assign eff_jtagsr_scanin = eff_jtagsr_h_scanout ; | |
840 | assign scan_out = eff_jtagsr_scanout ; | |
841 | // fixscan end: | |
842 | endmodule // sio_old_dp | |
843 | ||
844 | ||
845 | ||
846 | ||
847 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
848 | // also for pass-gate with decoder | |
849 | ||
850 | ||
851 | ||
852 | ||
853 | ||
854 | // any PARAMS parms go into naming of macro | |
855 | ||
856 | module sio_old_dp_mux_macro__mux_aope__ports_2__stack_46r__width_46 ( | |
857 | din0, | |
858 | din1, | |
859 | sel0, | |
860 | dout); | |
861 | wire psel0; | |
862 | wire psel1; | |
863 | ||
864 | input [45:0] din0; | |
865 | input [45:0] din1; | |
866 | input sel0; | |
867 | output [45:0] dout; | |
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | cl_dp1_penc2_8x c0_0 ( | |
874 | .sel0(sel0), | |
875 | .psel0(psel0), | |
876 | .psel1(psel1) | |
877 | ); | |
878 | ||
879 | mux2s #(46) d0_0 ( | |
880 | .sel0(psel0), | |
881 | .sel1(psel1), | |
882 | .in0(din0[45:0]), | |
883 | .in1(din1[45:0]), | |
884 | .dout(dout[45:0]) | |
885 | ); | |
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | endmodule | |
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | // any PARAMS parms go into naming of macro | |
907 | ||
908 | module sio_old_dp_msff_macro__stack_64c__width_35 ( | |
909 | din, | |
910 | clk, | |
911 | en, | |
912 | se, | |
913 | scan_in, | |
914 | siclk, | |
915 | soclk, | |
916 | pce_ov, | |
917 | stop, | |
918 | dout, | |
919 | scan_out); | |
920 | wire l1clk; | |
921 | wire siclk_out; | |
922 | wire soclk_out; | |
923 | wire [33:0] so; | |
924 | ||
925 | input [34:0] din; | |
926 | ||
927 | ||
928 | input clk; | |
929 | input en; | |
930 | input se; | |
931 | input scan_in; | |
932 | input siclk; | |
933 | input soclk; | |
934 | input pce_ov; | |
935 | input stop; | |
936 | ||
937 | ||
938 | ||
939 | output [34:0] dout; | |
940 | ||
941 | ||
942 | output scan_out; | |
943 | ||
944 | ||
945 | ||
946 | ||
947 | cl_dp1_l1hdr_8x c0_0 ( | |
948 | .l2clk(clk), | |
949 | .pce(en), | |
950 | .aclk(siclk), | |
951 | .bclk(soclk), | |
952 | .l1clk(l1clk), | |
953 | .se(se), | |
954 | .pce_ov(pce_ov), | |
955 | .stop(stop), | |
956 | .siclk_out(siclk_out), | |
957 | .soclk_out(soclk_out) | |
958 | ); | |
959 | dff #(35) d0_0 ( | |
960 | .l1clk(l1clk), | |
961 | .siclk(siclk_out), | |
962 | .soclk(soclk_out), | |
963 | .d(din[34:0]), | |
964 | .si({scan_in,so[33:0]}), | |
965 | .so({so[33:0],scan_out}), | |
966 | .q(dout[34:0]) | |
967 | ); | |
968 | ||
969 | ||
970 | ||
971 | ||
972 | ||
973 | ||
974 | ||
975 | ||
976 | ||
977 | ||
978 | ||
979 | ||
980 | ||
981 | ||
982 | ||
983 | ||
984 | ||
985 | ||
986 | ||
987 | ||
988 | endmodule | |
989 | ||
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | ||
998 | // | |
999 | // parity macro (even parity) | |
1000 | // | |
1001 | // | |
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | module sio_old_dp_prty_macro__width_16 ( | |
1008 | din, | |
1009 | dout); | |
1010 | input [15:0] din; | |
1011 | output dout; | |
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | prty #(16) m0_0 ( | |
1020 | .in(din[15:0]), | |
1021 | .out(dout) | |
1022 | ); | |
1023 | ||
1024 | ||
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | ||
1033 | endmodule | |
1034 | ||
1035 | ||
1036 | ||
1037 | ||
1038 | ||
1039 | // | |
1040 | // xor macro for ports = 2,3 | |
1041 | // | |
1042 | // | |
1043 | ||
1044 | ||
1045 | ||
1046 | ||
1047 | ||
1048 | module sio_old_dp_xor_macro__left_1__stack_4r__width_1 ( | |
1049 | din0, | |
1050 | din1, | |
1051 | dout); | |
1052 | input [0:0] din0; | |
1053 | input [0:0] din1; | |
1054 | output [0:0] dout; | |
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | xor2 #(1) d0_0 ( | |
1061 | .in0(din0[0:0]), | |
1062 | .in1(din1[0:0]), | |
1063 | .out(dout[0:0]) | |
1064 | ); | |
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | endmodule | |
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | // | |
1080 | // xor macro for ports = 2,3 | |
1081 | // | |
1082 | // | |
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | module sio_old_dp_xor_macro__left_0__stack_4r__width_1 ( | |
1089 | din0, | |
1090 | din1, | |
1091 | dout); | |
1092 | input [0:0] din0; | |
1093 | input [0:0] din1; | |
1094 | output [0:0] dout; | |
1095 | ||
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | xor2 #(1) d0_0 ( | |
1101 | .in0(din0[0:0]), | |
1102 | .in1(din1[0:0]), | |
1103 | .out(dout[0:0]) | |
1104 | ); | |
1105 | ||
1106 | ||
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | ||
1113 | endmodule | |
1114 | ||
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | // | |
1120 | // invert macro | |
1121 | // | |
1122 | // | |
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | module sio_old_dp_inv_macro__left_0__stack_4r__width_1 ( | |
1129 | din, | |
1130 | dout); | |
1131 | input [0:0] din; | |
1132 | output [0:0] dout; | |
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | inv #(1) d0_0 ( | |
1140 | .in(din[0:0]), | |
1141 | .out(dout[0:0]) | |
1142 | ); | |
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | endmodule | |
1153 | ||
1154 | ||
1155 | ||
1156 | ||
1157 | ||
1158 | // | |
1159 | // nand macro for ports = 2,3,4 | |
1160 | // | |
1161 | // | |
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | module sio_old_dp_nand_macro__left_0__stack_4r__width_1 ( | |
1168 | din0, | |
1169 | din1, | |
1170 | dout); | |
1171 | input [0:0] din0; | |
1172 | input [0:0] din1; | |
1173 | output [0:0] dout; | |
1174 | ||
1175 | ||
1176 | ||
1177 | ||
1178 | ||
1179 | ||
1180 | nand2 #(1) d0_0 ( | |
1181 | .in0(din0[0:0]), | |
1182 | .in1(din1[0:0]), | |
1183 | .out(dout[0:0]) | |
1184 | ); | |
1185 | ||
1186 | ||
1187 | ||
1188 | ||
1189 | ||
1190 | ||
1191 | ||
1192 | ||
1193 | ||
1194 | endmodule | |
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | // | |
1201 | // nor macro for ports = 2,3 | |
1202 | // | |
1203 | // | |
1204 | ||
1205 | ||
1206 | ||
1207 | ||
1208 | ||
1209 | module sio_old_dp_nor_macro__left_0__ports_3__stack_4r__width_1 ( | |
1210 | din0, | |
1211 | din1, | |
1212 | din2, | |
1213 | dout); | |
1214 | input [0:0] din0; | |
1215 | input [0:0] din1; | |
1216 | input [0:0] din2; | |
1217 | output [0:0] dout; | |
1218 | ||
1219 | ||
1220 | ||
1221 | ||
1222 | ||
1223 | ||
1224 | nor3 #(1) d0_0 ( | |
1225 | .in0(din0[0:0]), | |
1226 | .in1(din1[0:0]), | |
1227 | .in2(din2[0:0]), | |
1228 | .out(dout[0:0]) | |
1229 | ); | |
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | ||
1235 | ||
1236 | ||
1237 | endmodule | |
1238 | ||
1239 | ||
1240 | ||
1241 | ||
1242 | ||
1243 | // | |
1244 | // nand macro for ports = 2,3,4 | |
1245 | // | |
1246 | // | |
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | ||
1252 | module sio_old_dp_nand_macro__left_0__ports_2__stack_4r__width_1 ( | |
1253 | din0, | |
1254 | din1, | |
1255 | dout); | |
1256 | input [0:0] din0; | |
1257 | input [0:0] din1; | |
1258 | output [0:0] dout; | |
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | ||
1264 | ||
1265 | nand2 #(1) d0_0 ( | |
1266 | .in0(din0[0:0]), | |
1267 | .in1(din1[0:0]), | |
1268 | .out(dout[0:0]) | |
1269 | ); | |
1270 | ||
1271 | ||
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | endmodule | |
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | ||
1286 | ||
1287 | ||
1288 | ||
1289 | // any PARAMS parms go into naming of macro | |
1290 | ||
1291 | module sio_old_dp_msff_macro__left_0__stack_4r__width_1 ( | |
1292 | din, | |
1293 | clk, | |
1294 | en, | |
1295 | se, | |
1296 | scan_in, | |
1297 | siclk, | |
1298 | soclk, | |
1299 | pce_ov, | |
1300 | stop, | |
1301 | dout, | |
1302 | scan_out); | |
1303 | wire l1clk; | |
1304 | wire siclk_out; | |
1305 | wire soclk_out; | |
1306 | ||
1307 | input [0:0] din; | |
1308 | ||
1309 | ||
1310 | input clk; | |
1311 | input en; | |
1312 | input se; | |
1313 | input scan_in; | |
1314 | input siclk; | |
1315 | input soclk; | |
1316 | input pce_ov; | |
1317 | input stop; | |
1318 | ||
1319 | ||
1320 | ||
1321 | output [0:0] dout; | |
1322 | ||
1323 | ||
1324 | output scan_out; | |
1325 | ||
1326 | ||
1327 | ||
1328 | ||
1329 | cl_dp1_l1hdr_8x c0_0 ( | |
1330 | .l2clk(clk), | |
1331 | .pce(en), | |
1332 | .aclk(siclk), | |
1333 | .bclk(soclk), | |
1334 | .l1clk(l1clk), | |
1335 | .se(se), | |
1336 | .pce_ov(pce_ov), | |
1337 | .stop(stop), | |
1338 | .siclk_out(siclk_out), | |
1339 | .soclk_out(soclk_out) | |
1340 | ); | |
1341 | dff #(1) d0_0 ( | |
1342 | .l1clk(l1clk), | |
1343 | .siclk(siclk_out), | |
1344 | .soclk(soclk_out), | |
1345 | .d(din[0:0]), | |
1346 | .si(scan_in), | |
1347 | .so(scan_out), | |
1348 | .q(dout[0:0]) | |
1349 | ); | |
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | ||
1369 | ||
1370 | endmodule | |
1371 | ||
1372 | ||
1373 | ||
1374 | ||
1375 | ||
1376 | ||
1377 | ||
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | ||
1384 | // any PARAMS parms go into naming of macro | |
1385 | ||
1386 | module sio_old_dp_msff_macro__left_0__stack_2r__width_1 ( | |
1387 | din, | |
1388 | clk, | |
1389 | en, | |
1390 | se, | |
1391 | scan_in, | |
1392 | siclk, | |
1393 | soclk, | |
1394 | pce_ov, | |
1395 | stop, | |
1396 | dout, | |
1397 | scan_out); | |
1398 | wire l1clk; | |
1399 | wire siclk_out; | |
1400 | wire soclk_out; | |
1401 | ||
1402 | input [0:0] din; | |
1403 | ||
1404 | ||
1405 | input clk; | |
1406 | input en; | |
1407 | input se; | |
1408 | input scan_in; | |
1409 | input siclk; | |
1410 | input soclk; | |
1411 | input pce_ov; | |
1412 | input stop; | |
1413 | ||
1414 | ||
1415 | ||
1416 | output [0:0] dout; | |
1417 | ||
1418 | ||
1419 | output scan_out; | |
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | cl_dp1_l1hdr_8x c0_0 ( | |
1425 | .l2clk(clk), | |
1426 | .pce(en), | |
1427 | .aclk(siclk), | |
1428 | .bclk(soclk), | |
1429 | .l1clk(l1clk), | |
1430 | .se(se), | |
1431 | .pce_ov(pce_ov), | |
1432 | .stop(stop), | |
1433 | .siclk_out(siclk_out), | |
1434 | .soclk_out(soclk_out) | |
1435 | ); | |
1436 | dff #(1) d0_0 ( | |
1437 | .l1clk(l1clk), | |
1438 | .siclk(siclk_out), | |
1439 | .soclk(soclk_out), | |
1440 | .d(din[0:0]), | |
1441 | .si(scan_in), | |
1442 | .so(scan_out), | |
1443 | .q(dout[0:0]) | |
1444 | ); | |
1445 | ||
1446 | ||
1447 | ||
1448 | ||
1449 | ||
1450 | ||
1451 | ||
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | ||
1460 | ||
1461 | ||
1462 | ||
1463 | ||
1464 | ||
1465 | endmodule | |
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1476 | // also for pass-gate with decoder | |
1477 | ||
1478 | ||
1479 | ||
1480 | ||
1481 | ||
1482 | // any PARAMS parms go into naming of macro | |
1483 | ||
1484 | module sio_old_dp_mux_macro__left_0__mux_pgdec__ports_4__stack_2r__width_1 ( | |
1485 | din0, | |
1486 | din1, | |
1487 | din2, | |
1488 | din3, | |
1489 | sel, | |
1490 | muxtst, | |
1491 | test, | |
1492 | dout); | |
1493 | wire psel0; | |
1494 | wire psel1; | |
1495 | wire psel2; | |
1496 | wire psel3; | |
1497 | ||
1498 | input [0:0] din0; | |
1499 | input [0:0] din1; | |
1500 | input [0:0] din2; | |
1501 | input [0:0] din3; | |
1502 | input [1:0] sel; | |
1503 | input muxtst; | |
1504 | input test; | |
1505 | output [0:0] dout; | |
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | cl_dp1_pdec4_8x c0_0 ( | |
1512 | .sel0(sel[0]), | |
1513 | .sel1(sel[1]), | |
1514 | .psel0(psel0), | |
1515 | .psel1(psel1), | |
1516 | .psel2(psel2), | |
1517 | .psel3(psel3), | |
1518 | .test(test) | |
1519 | ); | |
1520 | ||
1521 | mux4 #(1) d0_0 ( | |
1522 | .sel0(psel0), | |
1523 | .sel1(psel1), | |
1524 | .sel2(psel2), | |
1525 | .sel3(psel3), | |
1526 | .in0(din0[0:0]), | |
1527 | .in1(din1[0:0]), | |
1528 | .in2(din2[0:0]), | |
1529 | .in3(din3[0:0]), | |
1530 | .dout(dout[0:0]), | |
1531 | .muxtst(muxtst) | |
1532 | ); | |
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | ||
1545 | ||
1546 | endmodule | |
1547 | ||
1548 | ||
1549 | // | |
1550 | // or macro for ports = 2,3 | |
1551 | // | |
1552 | // | |
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | module sio_old_dp_or_macro__stack_2l__width_1 ( | |
1559 | din0, | |
1560 | din1, | |
1561 | dout); | |
1562 | input [0:0] din0; | |
1563 | input [0:0] din1; | |
1564 | output [0:0] dout; | |
1565 | ||
1566 | ||
1567 | ||
1568 | ||
1569 | ||
1570 | ||
1571 | or2 #(1) d0_0 ( | |
1572 | .in0(din0[0:0]), | |
1573 | .in1(din1[0:0]), | |
1574 | .out(dout[0:0]) | |
1575 | ); | |
1576 | ||
1577 | ||
1578 | ||
1579 | ||
1580 | ||
1581 | ||
1582 | ||
1583 | ||
1584 | ||
1585 | endmodule | |
1586 | ||
1587 | ||
1588 | ||
1589 | ||
1590 | ||
1591 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1592 | // also for pass-gate with decoder | |
1593 | ||
1594 | ||
1595 | ||
1596 | ||
1597 | ||
1598 | // any PARAMS parms go into naming of macro | |
1599 | ||
1600 | module sio_old_dp_mux_macro__mux_pgpe__ports_2__stack_32l__width_32 ( | |
1601 | din0, | |
1602 | din1, | |
1603 | sel0, | |
1604 | dout); | |
1605 | wire psel0_unused; | |
1606 | wire psel1; | |
1607 | ||
1608 | input [31:0] din0; | |
1609 | input [31:0] din1; | |
1610 | input sel0; | |
1611 | output [31:0] dout; | |
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | cl_dp1_penc2_8x c0_0 ( | |
1618 | .sel0(sel0), | |
1619 | .psel0(psel0_unused), | |
1620 | .psel1(psel1) | |
1621 | ); | |
1622 | ||
1623 | mux2e #(32) d0_0 ( | |
1624 | .sel(psel1), | |
1625 | .in0(din0[31:0]), | |
1626 | .in1(din1[31:0]), | |
1627 | .dout(dout[31:0]) | |
1628 | ); | |
1629 | ||
1630 | ||
1631 | ||
1632 | ||
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | ||
1639 | ||
1640 | ||
1641 | ||
1642 | endmodule | |
1643 | ||
1644 | ||
1645 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1646 | // also for pass-gate with decoder | |
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | ||
1652 | // any PARAMS parms go into naming of macro | |
1653 | ||
1654 | module sio_old_dp_mux_macro__mux_pgdec__ports_4__stack_26l__width_26 ( | |
1655 | din0, | |
1656 | din1, | |
1657 | din2, | |
1658 | din3, | |
1659 | sel, | |
1660 | muxtst, | |
1661 | test, | |
1662 | dout); | |
1663 | wire psel0; | |
1664 | wire psel1; | |
1665 | wire psel2; | |
1666 | wire psel3; | |
1667 | ||
1668 | input [25:0] din0; | |
1669 | input [25:0] din1; | |
1670 | input [25:0] din2; | |
1671 | input [25:0] din3; | |
1672 | input [1:0] sel; | |
1673 | input muxtst; | |
1674 | input test; | |
1675 | output [25:0] dout; | |
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | cl_dp1_pdec4_8x c0_0 ( | |
1682 | .sel0(sel[0]), | |
1683 | .sel1(sel[1]), | |
1684 | .psel0(psel0), | |
1685 | .psel1(psel1), | |
1686 | .psel2(psel2), | |
1687 | .psel3(psel3), | |
1688 | .test(test) | |
1689 | ); | |
1690 | ||
1691 | mux4 #(26) d0_0 ( | |
1692 | .sel0(psel0), | |
1693 | .sel1(psel1), | |
1694 | .sel2(psel2), | |
1695 | .sel3(psel3), | |
1696 | .in0(din0[25:0]), | |
1697 | .in1(din1[25:0]), | |
1698 | .in2(din2[25:0]), | |
1699 | .in3(din3[25:0]), | |
1700 | .dout(dout[25:0]), | |
1701 | .muxtst(muxtst) | |
1702 | ); | |
1703 | ||
1704 | ||
1705 | ||
1706 | ||
1707 | ||
1708 | ||
1709 | ||
1710 | ||
1711 | ||
1712 | ||
1713 | ||
1714 | ||
1715 | ||
1716 | endmodule | |
1717 | ||
1718 | ||
1719 | ||
1720 | ||
1721 | ||
1722 | ||
1723 | // any PARAMS parms go into naming of macro | |
1724 | ||
1725 | module sio_old_dp_msff_macro__stack_32l__width_30 ( | |
1726 | din, | |
1727 | clk, | |
1728 | en, | |
1729 | se, | |
1730 | scan_in, | |
1731 | siclk, | |
1732 | soclk, | |
1733 | pce_ov, | |
1734 | stop, | |
1735 | dout, | |
1736 | scan_out); | |
1737 | wire l1clk; | |
1738 | wire siclk_out; | |
1739 | wire soclk_out; | |
1740 | wire [28:0] so; | |
1741 | ||
1742 | input [29:0] din; | |
1743 | ||
1744 | ||
1745 | input clk; | |
1746 | input en; | |
1747 | input se; | |
1748 | input scan_in; | |
1749 | input siclk; | |
1750 | input soclk; | |
1751 | input pce_ov; | |
1752 | input stop; | |
1753 | ||
1754 | ||
1755 | ||
1756 | output [29:0] dout; | |
1757 | ||
1758 | ||
1759 | output scan_out; | |
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | cl_dp1_l1hdr_8x c0_0 ( | |
1765 | .l2clk(clk), | |
1766 | .pce(en), | |
1767 | .aclk(siclk), | |
1768 | .bclk(soclk), | |
1769 | .l1clk(l1clk), | |
1770 | .se(se), | |
1771 | .pce_ov(pce_ov), | |
1772 | .stop(stop), | |
1773 | .siclk_out(siclk_out), | |
1774 | .soclk_out(soclk_out) | |
1775 | ); | |
1776 | dff #(30) d0_0 ( | |
1777 | .l1clk(l1clk), | |
1778 | .siclk(siclk_out), | |
1779 | .soclk(soclk_out), | |
1780 | .d(din[29:0]), | |
1781 | .si({scan_in,so[28:0]}), | |
1782 | .so({so[28:0],scan_out}), | |
1783 | .q(dout[29:0]) | |
1784 | ); | |
1785 | ||
1786 | ||
1787 | ||
1788 | ||
1789 | ||
1790 | ||
1791 | ||
1792 | ||
1793 | ||
1794 | ||
1795 | ||
1796 | ||
1797 | ||
1798 | ||
1799 | ||
1800 | ||
1801 | ||
1802 | ||
1803 | ||
1804 | ||
1805 | endmodule | |
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | // any PARAMS parms go into naming of macro | |
1820 | ||
1821 | module sio_old_dp_msff_macro__stack_26l__width_26 ( | |
1822 | din, | |
1823 | clk, | |
1824 | en, | |
1825 | se, | |
1826 | scan_in, | |
1827 | siclk, | |
1828 | soclk, | |
1829 | pce_ov, | |
1830 | stop, | |
1831 | dout, | |
1832 | scan_out); | |
1833 | wire l1clk; | |
1834 | wire siclk_out; | |
1835 | wire soclk_out; | |
1836 | wire [24:0] so; | |
1837 | ||
1838 | input [25:0] din; | |
1839 | ||
1840 | ||
1841 | input clk; | |
1842 | input en; | |
1843 | input se; | |
1844 | input scan_in; | |
1845 | input siclk; | |
1846 | input soclk; | |
1847 | input pce_ov; | |
1848 | input stop; | |
1849 | ||
1850 | ||
1851 | ||
1852 | output [25:0] dout; | |
1853 | ||
1854 | ||
1855 | output scan_out; | |
1856 | ||
1857 | ||
1858 | ||
1859 | ||
1860 | cl_dp1_l1hdr_8x c0_0 ( | |
1861 | .l2clk(clk), | |
1862 | .pce(en), | |
1863 | .aclk(siclk), | |
1864 | .bclk(soclk), | |
1865 | .l1clk(l1clk), | |
1866 | .se(se), | |
1867 | .pce_ov(pce_ov), | |
1868 | .stop(stop), | |
1869 | .siclk_out(siclk_out), | |
1870 | .soclk_out(soclk_out) | |
1871 | ); | |
1872 | dff #(26) d0_0 ( | |
1873 | .l1clk(l1clk), | |
1874 | .siclk(siclk_out), | |
1875 | .soclk(soclk_out), | |
1876 | .d(din[25:0]), | |
1877 | .si({scan_in,so[24:0]}), | |
1878 | .so({so[24:0],scan_out}), | |
1879 | .q(dout[25:0]) | |
1880 | ); | |
1881 | ||
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | ||
1896 | ||
1897 | ||
1898 | ||
1899 | ||
1900 | ||
1901 | endmodule | |
1902 | ||
1903 | ||
1904 | ||
1905 | ||
1906 | ||
1907 | ||
1908 | ||
1909 | ||
1910 | ||
1911 | ||
1912 | ||
1913 | ||
1914 | ||
1915 | // any PARAMS parms go into naming of macro | |
1916 | ||
1917 | module sio_old_dp_msff_macro__stack_32l__width_32 ( | |
1918 | din, | |
1919 | clk, | |
1920 | en, | |
1921 | se, | |
1922 | scan_in, | |
1923 | siclk, | |
1924 | soclk, | |
1925 | pce_ov, | |
1926 | stop, | |
1927 | dout, | |
1928 | scan_out); | |
1929 | wire l1clk; | |
1930 | wire siclk_out; | |
1931 | wire soclk_out; | |
1932 | wire [30:0] so; | |
1933 | ||
1934 | input [31:0] din; | |
1935 | ||
1936 | ||
1937 | input clk; | |
1938 | input en; | |
1939 | input se; | |
1940 | input scan_in; | |
1941 | input siclk; | |
1942 | input soclk; | |
1943 | input pce_ov; | |
1944 | input stop; | |
1945 | ||
1946 | ||
1947 | ||
1948 | output [31:0] dout; | |
1949 | ||
1950 | ||
1951 | output scan_out; | |
1952 | ||
1953 | ||
1954 | ||
1955 | ||
1956 | cl_dp1_l1hdr_8x c0_0 ( | |
1957 | .l2clk(clk), | |
1958 | .pce(en), | |
1959 | .aclk(siclk), | |
1960 | .bclk(soclk), | |
1961 | .l1clk(l1clk), | |
1962 | .se(se), | |
1963 | .pce_ov(pce_ov), | |
1964 | .stop(stop), | |
1965 | .siclk_out(siclk_out), | |
1966 | .soclk_out(soclk_out) | |
1967 | ); | |
1968 | dff #(32) d0_0 ( | |
1969 | .l1clk(l1clk), | |
1970 | .siclk(siclk_out), | |
1971 | .soclk(soclk_out), | |
1972 | .d(din[31:0]), | |
1973 | .si({scan_in,so[30:0]}), | |
1974 | .so({so[30:0],scan_out}), | |
1975 | .q(dout[31:0]) | |
1976 | ); | |
1977 | ||
1978 | ||
1979 | ||
1980 | ||
1981 | ||
1982 | ||
1983 | ||
1984 | ||
1985 | ||
1986 | ||
1987 | ||
1988 | ||
1989 | ||
1990 | ||
1991 | ||
1992 | ||
1993 | ||
1994 | ||
1995 | ||
1996 | ||
1997 | endmodule | |
1998 | ||
1999 | ||
2000 | ||
2001 | ||
2002 | ||
2003 | ||
2004 | ||
2005 | ||
2006 | ||
2007 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2008 | // also for pass-gate with decoder | |
2009 | ||
2010 | ||
2011 | ||
2012 | ||
2013 | ||
2014 | // any PARAMS parms go into naming of macro | |
2015 | ||
2016 | module sio_old_dp_mux_macro__mux_aope__ports_2__stack_64c__width_64 ( | |
2017 | din0, | |
2018 | din1, | |
2019 | sel0, | |
2020 | dout); | |
2021 | wire psel0; | |
2022 | wire psel1; | |
2023 | ||
2024 | input [63:0] din0; | |
2025 | input [63:0] din1; | |
2026 | input sel0; | |
2027 | output [63:0] dout; | |
2028 | ||
2029 | ||
2030 | ||
2031 | ||
2032 | ||
2033 | cl_dp1_penc2_8x c0_0 ( | |
2034 | .sel0(sel0), | |
2035 | .psel0(psel0), | |
2036 | .psel1(psel1) | |
2037 | ); | |
2038 | ||
2039 | mux2s #(64) d0_0 ( | |
2040 | .sel0(psel0), | |
2041 | .sel1(psel1), | |
2042 | .in0(din0[63:0]), | |
2043 | .in1(din1[63:0]), | |
2044 | .dout(dout[63:0]) | |
2045 | ); | |
2046 | ||
2047 | ||
2048 | ||
2049 | ||
2050 | ||
2051 | ||
2052 | ||
2053 | ||
2054 | ||
2055 | ||
2056 | ||
2057 | ||
2058 | ||
2059 | endmodule | |
2060 | ||
2061 | ||
2062 | // | |
2063 | // parity macro (even parity) | |
2064 | // | |
2065 | // | |
2066 | ||
2067 | ||
2068 | ||
2069 | ||
2070 | ||
2071 | module sio_old_dp_prty_macro__width_8 ( | |
2072 | din, | |
2073 | dout); | |
2074 | input [7:0] din; | |
2075 | output dout; | |
2076 | ||
2077 | ||
2078 | ||
2079 | ||
2080 | ||
2081 | ||
2082 | ||
2083 | prty #(8) m0_0 ( | |
2084 | .in(din[7:0]), | |
2085 | .out(dout) | |
2086 | ); | |
2087 | ||
2088 | ||
2089 | ||
2090 | ||
2091 | ||
2092 | ||
2093 | ||
2094 | ||
2095 | ||
2096 | ||
2097 | endmodule | |
2098 | ||
2099 | ||
2100 | ||
2101 |