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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fgu_fdd_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module fgu_fdd_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | scan_out, | |
43 | div_clken_rep0, | |
44 | fad_rs1_fmt_fx1_rep01, | |
45 | fad_rs2_fmt_fx1_rep01, | |
46 | fac_div_valid_fx1_rep0, | |
47 | fac_divq_valid_fx1_rep0, | |
48 | fdc_asign_lth, | |
49 | fdc_bsign_lth, | |
50 | fdc_bsign_lth_, | |
51 | fdc_pe_cycle3, | |
52 | fdc_pe_cmux_sel, | |
53 | fdc_pe_smux_sel, | |
54 | fdc_pe_xsht_ctl, | |
55 | fdc_ie_fsqrt_valid_even, | |
56 | fdc_ie_fsqrt_valid_even_, | |
57 | fdc_ie_fsqrt_valid_odd, | |
58 | fdc_ie_fsqrt_valid_odd_, | |
59 | fdc_ie_rmux_sel, | |
60 | fdc_ie_dmux_sel, | |
61 | fdc_flt_increment, | |
62 | fdc_pte_clasel, | |
63 | fdc_pte_csa_cin, | |
64 | fdc_pte_cycle2, | |
65 | fdc_emin_lth, | |
66 | fdc_pte_qsel, | |
67 | fdc_pte_stall_, | |
68 | fdc_flt_round, | |
69 | fdc_idiv_ctl, | |
70 | fdc_fdx_cin_in, | |
71 | fdc_qsel00, | |
72 | fdc_qsel1, | |
73 | fdc_q_in, | |
74 | fdc_qm1_in, | |
75 | fdd_result, | |
76 | fdd_pte_cla_early_b63, | |
77 | fdd_pe_clth, | |
78 | fdd_cla_zero32_, | |
79 | fdd_cla_zero64_, | |
80 | fdd_fdx_din0, | |
81 | fdd_fdx_din1, | |
82 | fdd_fdx_cin64, | |
83 | fdd_fdq00_10_sum, | |
84 | fdd_fdq00_10_carry, | |
85 | fdd_fdq1p_sum, | |
86 | fdd_fdq1p_carry, | |
87 | fdd_fdq1n_sum, | |
88 | fdd_fdq1n_carry); | |
89 | wire stop; | |
90 | wire se; | |
91 | wire pce_ov; | |
92 | wire siclk; | |
93 | wire soclk; | |
94 | wire q_rs1_ff_scanin; | |
95 | wire q_rs1_ff_scanout; | |
96 | wire [63:0] q_rs1_fx1; | |
97 | wire q_rs2_ff_scanin; | |
98 | wire q_rs2_ff_scanout; | |
99 | wire [63:0] q_rs2_fx1; | |
100 | wire ipe_clth_scanin; | |
101 | wire ipe_clth_scanout; | |
102 | wire [63:0] pe_xsht1; | |
103 | wire ipe_slth_scanin; | |
104 | wire ipe_slth_scanout; | |
105 | wire [63:0] pe_slth; | |
106 | wire [63:0] pe_xsht0; | |
107 | wire bsign_buff0; | |
108 | wire bsign_buff1; | |
109 | wire [65:0] pe_divisor; | |
110 | wire [65:0] pe_aop_sh; | |
111 | wire [65:0] sum_new; | |
112 | wire [65:0] divisor_new; | |
113 | wire engine_start; | |
114 | wire engine_start_; | |
115 | wire ie_s00lth_scanin; | |
116 | wire ie_s00lth_scanout; | |
117 | wire [64:0] s21; | |
118 | wire [65:1] s1; | |
119 | wire [64:0] s20; | |
120 | wire [65:0] s0; | |
121 | wire ie_c00lth_scanin; | |
122 | wire ie_c00lth_scanout; | |
123 | wire [64:1] c21; | |
124 | wire [65:2] c1; | |
125 | wire [64:1] c20; | |
126 | wire [65:2] c0; | |
127 | wire [65:0] d2_00_in; | |
128 | wire [65:0] d1; | |
129 | wire [65:0] sqe_cnt1; | |
130 | wire [65:0] d2_p1_in; | |
131 | wire [65:0] flip1; | |
132 | wire [65:0] d2_m1xor; | |
133 | wire [65:0] d2_m1_in; | |
134 | wire ie_d00lth_scanin; | |
135 | wire ie_d00lth_scanout; | |
136 | wire [65:0] d0; | |
137 | wire [64:0] sqe_cnt13; | |
138 | wire [64:0] effd2_p1_p1in; | |
139 | wire [64:0] sqe_cnt3; | |
140 | wire [64:0] effd2_00_p1in; | |
141 | wire [64:0] effd2_m1_p1in; | |
142 | wire [64:0] effd2_xx_p1in; | |
143 | wire ie_d00lthp1_scanin; | |
144 | wire ie_d00lthp1_scanout; | |
145 | wire [64:0] effd0_p1_; | |
146 | wire [64:0] sqe_cnt23; | |
147 | wire [64:0] effd2_p1_m1in; | |
148 | wire [64:0] sqe_cnt123; | |
149 | wire [64:0] effd2_00_m1in; | |
150 | wire [64:0] effd2_m1_m1in; | |
151 | wire ie_d00lthm1_scanin; | |
152 | wire ie_d00lthm1_scanout; | |
153 | wire [64:0] effd0_m1; | |
154 | wire ie_csa11_unused; | |
155 | wire [64:1] c11; | |
156 | wire [64:0] s11; | |
157 | wire ie_csa10_unused; | |
158 | wire [64:1] c10; | |
159 | wire [64:0] s10; | |
160 | wire [65:0] d1_00_in; | |
161 | wire [65:0] sqe_cnt0; | |
162 | wire [65:0] d1_p1_in; | |
163 | wire [65:0] flip0; | |
164 | wire [65:0] d1_m1xor; | |
165 | wire [65:0] d1_m1_in; | |
166 | wire [65:0] sqe_cnt02; | |
167 | wire [64:0] effd1_p1_p1in; | |
168 | wire [64:0] sqe_cnt2; | |
169 | wire [64:0] effd1_00_p1in; | |
170 | wire [64:0] effd1_m1_p1in; | |
171 | wire [64:0] effd1_p1_; | |
172 | wire [64:0] sqe_cnt12; | |
173 | wire [64:0] effd1_p1_m1in; | |
174 | wire [65:0] sqe_cnt012; | |
175 | wire [64:0] effd1_00_m1in; | |
176 | wire [64:0] effd1_m1_m1in; | |
177 | wire [64:0] effd1_m1; | |
178 | wire ie_csa21_unused; | |
179 | wire ie_csa20_unused; | |
180 | wire [65:0] q_lth; | |
181 | wire [65:2] q_in; | |
182 | wire ie_qlth_scanin; | |
183 | wire ie_qlth_scanout; | |
184 | wire [65:0] qm1_lth; | |
185 | wire [65:2] qm1_in; | |
186 | wire ie_qm1lth_scanin; | |
187 | wire ie_qm1lth_scanout; | |
188 | wire [65:1] qm1_lth_; | |
189 | wire [65:2] pte_q; | |
190 | wire [65:2] pte_qm1_; | |
191 | wire ipte_csa_unused; | |
192 | wire [63:1] pte_carry; | |
193 | wire [63:0] pte_sum; | |
194 | wire ipte_clalth0_scanin; | |
195 | wire ipte_clalth0_scanout; | |
196 | wire [63:0] pte_cla; | |
197 | wire [64:0] pte_clalth0; | |
198 | wire ipte_clalth1_scanin; | |
199 | wire ipte_clalth1_scanout; | |
200 | wire [64:0] pte_clalth1; | |
201 | wire pte_cla_cout; | |
202 | wire ipte_result_scanin; | |
203 | wire ipte_result_scanout; | |
204 | wire isqe_cnt_scanin; | |
205 | wire isqe_cnt_scanout; | |
206 | wire [65:0] sqe_cnt2_; | |
207 | wire [65:0] sqe_cnt0_; | |
208 | wire isqe_flip_scanin; | |
209 | wire isqe_flip_scanout; | |
210 | wire [65:0] sqe_cnt1_; | |
211 | wire [65:1] sqe_cnt01; | |
212 | ||
213 | ||
214 | // *** globals *** | |
215 | input l2clk; | |
216 | input scan_in; | |
217 | input tcu_pce_ov; // scan signals | |
218 | input spc_aclk; | |
219 | input spc_bclk; | |
220 | input tcu_scan_en; | |
221 | output scan_out; | |
222 | ||
223 | input div_clken_rep0; // div clken | |
224 | ||
225 | input [63:0] fad_rs1_fmt_fx1_rep01; | |
226 | input [63:0] fad_rs2_fmt_fx1_rep01; | |
227 | ||
228 | input fac_div_valid_fx1_rep0; // div_valid divq_valid | action | |
229 | input fac_divq_valid_fx1_rep0;// --------- ---------- | --------------------------------------- | |
230 | // 1 0 | start divide from FX1 RS1/RS2/control | |
231 | // 0 1 | load queue from FX1 RS1/RS2/control | |
232 | // 1 1 | start divide from queue RS1/RS2/control | |
233 | ||
234 | // *** locals *** | |
235 | input fdc_asign_lth; | |
236 | input fdc_bsign_lth; | |
237 | input fdc_bsign_lth_; | |
238 | input fdc_pe_cycle3; | |
239 | input fdc_pe_cmux_sel; | |
240 | input [2:0] fdc_pe_smux_sel; | |
241 | input [5:0] fdc_pe_xsht_ctl; | |
242 | input fdc_ie_fsqrt_valid_even; | |
243 | input fdc_ie_fsqrt_valid_even_; | |
244 | input fdc_ie_fsqrt_valid_odd; | |
245 | input fdc_ie_fsqrt_valid_odd_; | |
246 | input [4:0] fdc_ie_rmux_sel; | |
247 | input [2:0] fdc_ie_dmux_sel; | |
248 | input fdc_flt_increment; | |
249 | input [1:0] fdc_pte_clasel; | |
250 | input fdc_pte_csa_cin; | |
251 | input fdc_pte_cycle2; | |
252 | input fdc_emin_lth; | |
253 | input [2:0] fdc_pte_qsel; | |
254 | input fdc_pte_stall_; | |
255 | ||
256 | input [1:0] fdc_flt_round; | |
257 | input [4:0] fdc_idiv_ctl; // 3210 [4] = integer | |
258 | // ---- | |
259 | // 0001 : 8000 0000 0000 0000 | |
260 | // 0010 : FFFF FFFF 8000 0000 | |
261 | // 0100 : 0000 0000 7FFF FFFF | |
262 | // 1000 : 0000 0000 FFFF FFFF | |
263 | ||
264 | ||
265 | input fdc_fdx_cin_in; | |
266 | input [2:0] fdc_qsel00; | |
267 | input [2:0] fdc_qsel1; | |
268 | ||
269 | input [1:0] fdc_q_in; | |
270 | input [1:0] fdc_qm1_in; | |
271 | ||
272 | ||
273 | // *** globals *** | |
274 | output [63:0] fdd_result; | |
275 | output fdd_pte_cla_early_b63; | |
276 | ||
277 | ||
278 | // *** locals *** | |
279 | output [63:0] fdd_pe_clth; | |
280 | output fdd_cla_zero32_; | |
281 | output fdd_cla_zero64_; | |
282 | ||
283 | output fdd_fdx_din0; | |
284 | output fdd_fdx_din1; | |
285 | output fdd_fdx_cin64; | |
286 | ||
287 | output [4:0] fdd_fdq00_10_sum; | |
288 | output [4:0] fdd_fdq00_10_carry; | |
289 | output [3:0] fdd_fdq1p_sum; | |
290 | output [3:0] fdd_fdq1p_carry; | |
291 | output [3:0] fdd_fdq1n_sum; | |
292 | output [3:0] fdd_fdq1n_carry; | |
293 | ||
294 | ||
295 | ||
296 | // scan renames | |
297 | assign stop = 1'b0; | |
298 | // end scan | |
299 | ||
300 | fgu_fdd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_4 test_rep0 ( | |
301 | .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}), | |
302 | .dout({se, pce_ov, siclk, soclk })); | |
303 | ||
304 | ||
305 | ||
306 | // * * * * * * * * * * * 2nd Thread Group Queue * * * * * * * * * * | |
307 | ||
308 | ||
309 | fgu_fdd_dp_msff_macro__stack_66c__width_64 q_rs1_ff ( | |
310 | .scan_in(q_rs1_ff_scanin), | |
311 | .scan_out(q_rs1_ff_scanout), | |
312 | .clk ( l2clk ), | |
313 | .en ( fac_divq_valid_fx1_rep0 ), | |
314 | .din ( fad_rs1_fmt_fx1_rep01[63:0]), | |
315 | .dout( q_rs1_fx1[63:0] ), | |
316 | .se(se), | |
317 | .siclk(siclk), | |
318 | .soclk(soclk), | |
319 | .pce_ov(pce_ov), | |
320 | .stop(stop)); | |
321 | ||
322 | ||
323 | fgu_fdd_dp_msff_macro__stack_66c__width_64 q_rs2_ff ( | |
324 | .scan_in(q_rs2_ff_scanin), | |
325 | .scan_out(q_rs2_ff_scanout), | |
326 | .clk ( l2clk ), | |
327 | .en ( fac_divq_valid_fx1_rep0 ), | |
328 | .din ( fad_rs2_fmt_fx1_rep01[63:0]), | |
329 | .dout( q_rs2_fx1[63:0] ), | |
330 | .se(se), | |
331 | .siclk(siclk), | |
332 | .soclk(soclk), | |
333 | .pce_ov(pce_ov), | |
334 | .stop(stop)); | |
335 | ||
336 | ||
337 | ||
338 | // * * * * * * * * * * * Integer "pre-engine" * * * * * * * * * * * | |
339 | ||
340 | ||
341 | fgu_fdd_dp_msff_macro__mux_aope__ports_3__stack_66c__width_64 ipe_clth ( | |
342 | .scan_in(ipe_clth_scanin), | |
343 | .scan_out(ipe_clth_scanout), | |
344 | .clk ( l2clk ), | |
345 | .en ( div_clken_rep0 ), // powerdown pin | |
346 | .din0( pe_xsht1[63:0] ), | |
347 | .din1( fad_rs2_fmt_fx1_rep01[63:0]), | |
348 | .din2( q_rs2_fx1[63:0] ), | |
349 | .sel0( fdc_pe_cmux_sel ), | |
350 | .sel1( fdc_pe_smux_sel[2] ), | |
351 | .dout( fdd_pe_clth[63:0] ), | |
352 | .se(se), | |
353 | .siclk(siclk), | |
354 | .soclk(soclk), | |
355 | .pce_ov(pce_ov), | |
356 | .stop(stop)); | |
357 | ||
358 | ||
359 | fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_64 ipe_slth ( | |
360 | .scan_in(ipe_slth_scanin), | |
361 | .scan_out(ipe_slth_scanout), | |
362 | .clk ( l2clk ), | |
363 | .en ( div_clken_rep0 ), // powerdown pin | |
364 | .din0({fdd_pe_clth[62:0],1'b0 }), | |
365 | .din1( fdd_pe_clth[63:0] ), | |
366 | .din2( fad_rs1_fmt_fx1_rep01[63:0]), | |
367 | .din3( q_rs1_fx1[63:0] ), | |
368 | .sel0( fdc_pe_smux_sel[0] ), | |
369 | .sel1( fdc_pe_smux_sel[1] ), | |
370 | .sel2( fdc_pe_smux_sel[2] ), | |
371 | .dout( pe_slth[63:0] ), | |
372 | .se(se), | |
373 | .siclk(siclk), | |
374 | .soclk(soclk), | |
375 | .pce_ov(pce_ov), | |
376 | .stop(stop)); | |
377 | ||
378 | ||
379 | fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64 ipe_xsht0 ( | |
380 | .din0( pe_slth[63:0] ), | |
381 | .din1({pe_slth[55:0],{ 8{1'b0}}}), | |
382 | .din2({pe_slth[47:0],{16{1'b0}}}), | |
383 | .din3({pe_slth[39:0],{24{1'b0}}}), | |
384 | .din4({pe_slth[31:0],{32{1'b0}}}), | |
385 | .din5({pe_slth[23:0],{40{1'b0}}}), | |
386 | .din6({pe_slth[15:0],{48{1'b0}}}), | |
387 | .din7({pe_slth[7:0],{56{1'b0}}}), | |
388 | .sel ( fdc_pe_xsht_ctl[5:3] ), | |
389 | .dout( pe_xsht0[63:0] )); | |
390 | ||
391 | ||
392 | fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64 ipe_xsht1 ( | |
393 | .din0( pe_xsht0[63:0] ), | |
394 | .din1({pe_xsht0[62:0],{1{1'b0}}}), | |
395 | .din2({pe_xsht0[61:0],{2{1'b0}}}), | |
396 | .din3({pe_xsht0[60:0],{3{1'b0}}}), | |
397 | .din4({pe_xsht0[59:0],{4{1'b0}}}), | |
398 | .din5({pe_xsht0[58:0],{5{1'b0}}}), | |
399 | .din6({pe_xsht0[57:0],{6{1'b0}}}), | |
400 | .din7({pe_xsht0[56:0],{7{1'b0}}}), | |
401 | .sel ( fdc_pe_xsht_ctl[2:0] ), | |
402 | .dout( pe_xsht1[63:0] )); | |
403 | ||
404 | ||
405 | // Floorplan Info - install "ipe_bsign_buf" in clock bay of "ipe_divxor" | |
406 | ||
407 | fgu_fdd_dp_buff_macro__stack_66c__width_2 ipe_bsign_buf ( | |
408 | .din ({2{fdc_bsign_lth} }), | |
409 | .dout({bsign_buff0,bsign_buff1 })); | |
410 | ||
411 | fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_64 ipe_divxor ( | |
412 | .din0( fdd_pe_clth[63:0] ), | |
413 | .din1({{32{bsign_buff0}},{32{bsign_buff1}}}), | |
414 | .dout( pe_divisor[63:0] )); | |
415 | ||
416 | assign pe_aop_sh[65:0] = {{2{fdc_asign_lth}},pe_xsht1[63:0]}; | |
417 | assign pe_divisor[65:64] = 2'b00; | |
418 | ||
419 | ||
420 | ||
421 | // * * * * * * * * * * * Interface to engine * * * * * * * * * * * | |
422 | ||
423 | ||
424 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_5__stack_66c__width_66 ie_rmux ( | |
425 | .din0( pe_aop_sh[65:0] ), // integer | |
426 | .din1({{4'b0001},fad_rs2_fmt_fx1_rep01[62:11],{10{1'b0}}}), // float sqrt | |
427 | .din2({{3'b001 },fad_rs1_fmt_fx1_rep01[62:11],{11{1'b0}}}), // float div | |
428 | .din3({{4'b0001},q_rs2_fx1[62:11] ,{10{1'b0}}}), // float sqrt | |
429 | .din4({{3'b001 },q_rs1_fx1[62:11] ,{11{1'b0}}}), // float div | |
430 | .sel0( fdc_ie_rmux_sel[0] ), | |
431 | .sel1( fdc_ie_rmux_sel[1] ), | |
432 | .sel2( fdc_ie_rmux_sel[2] ), | |
433 | .sel3( fdc_ie_rmux_sel[3] ), | |
434 | .sel4( fdc_ie_rmux_sel[4] ), | |
435 | .dout( sum_new[65:0] )); | |
436 | ||
437 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66 ie_dmux ( | |
438 | .din0( pe_divisor[65:0] ), // integer | |
439 | .din1({{3'b001 },fad_rs2_fmt_fx1_rep01[62:11],{11{1'b0}}}), // float div | |
440 | .din2({{3'b001 },q_rs2_fx1[62:11] ,{11{1'b0}}}), // float div | |
441 | .sel0( fdc_ie_dmux_sel[0] ), | |
442 | .sel1( fdc_ie_dmux_sel[1] ), | |
443 | .sel2( fdc_ie_dmux_sel[2] ), | |
444 | .dout( divisor_new[65:0] )); | |
445 | ||
446 | ||
447 | ||
448 | // * * * * * * * * * * * * * * "engine" * * * * * * * * * * * * * * | |
449 | ||
450 | fgu_fdd_dp_or_macro__ports_2__width_1 ie_engstart_or ( | |
451 | .din0( fac_div_valid_fx1_rep0 ), | |
452 | .din1( fdc_pe_cycle3 ), | |
453 | .dout( engine_start )); | |
454 | ||
455 | fgu_fdd_dp_nor_macro__ports_2__width_1 ie_engstart_nor ( | |
456 | .din0( fac_div_valid_fx1_rep0 ), | |
457 | .din1( fdc_pe_cycle3 ), | |
458 | .dout( engine_start_ )); | |
459 | ||
460 | ||
461 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66 ie_s00lth ( | |
462 | .scan_in(ie_s00lth_scanin), | |
463 | .scan_out(ie_s00lth_scanout), | |
464 | .clk ( l2clk ), | |
465 | .en ( div_clken_rep0 ), // powerdown pin | |
466 | .din0({s21[64:0],1'b0 }), | |
467 | .din1({s1[64:1] ,2'b00 }), | |
468 | .din2({s20[64:0],1'b0 }), | |
469 | .din3( sum_new[65:0] ), // PR(i+1) = PR(i) - qD; | |
470 | .sel0( fdc_qsel1[0] ), // PR + D -> therefore q = -1 | |
471 | .sel1( fdc_qsel1[1] ), | |
472 | .sel2( fdc_qsel1[2] ), // PR - D -> therefore q = +1 | |
473 | .sel3( engine_start ), | |
474 | .dout( s0[65:0] ), | |
475 | .se(se), | |
476 | .siclk(siclk), | |
477 | .soclk(soclk), | |
478 | .pce_ov(pce_ov), | |
479 | .stop(stop)); | |
480 | ||
481 | ||
482 | ||
483 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_64 ie_c00lth ( | |
484 | .scan_in(ie_c00lth_scanin), | |
485 | .scan_out(ie_c00lth_scanout), | |
486 | .clk ( l2clk ), | |
487 | .en ( div_clken_rep0 ), // powerdown pin | |
488 | .din0( c21[64:1] ), | |
489 | .din1({c1[64:2] ,1'b0 }), | |
490 | .din2( c20[64:1] ), | |
491 | .din3({64{1'b0} }), // PR(i+1) = PR(i) - qD; | |
492 | .sel0( fdc_qsel1[0] ), // PR + D -> therefore q = -1 | |
493 | .sel1( fdc_qsel1[1] ), | |
494 | .sel2( fdc_qsel1[2] ), // PR - D -> therefore q = +1 | |
495 | .sel3( engine_start ), | |
496 | .dout( c0[65:2] ), | |
497 | .se(se), | |
498 | .siclk(siclk), | |
499 | .soclk(soclk), | |
500 | .pce_ov(pce_ov), | |
501 | .stop(stop)); | |
502 | ||
503 | ||
504 | ||
505 | //assign d2_p1_in[65:0] = d1[65:0] | sqe_cnt1[65:0]; | |
506 | assign d2_00_in[65:0] = d1[65:0] ; | |
507 | //assign d2_m1_in[65:0] = (d1[65:0] ^ flip1[65:0]) | sqe_cnt1[65:0]; | |
508 | ||
509 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 ie_d00lth_p1or ( | |
510 | .din0( d1[65:0] ), | |
511 | .din1( sqe_cnt1[65:0] ), | |
512 | .dout( d2_p1_in[65:0] )); | |
513 | ||
514 | fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66 ie_d00lth_m1xor ( | |
515 | .din0( d1[65:0] ), | |
516 | .din1( flip1[65:0] ), | |
517 | .dout( d2_m1xor[65:0] )); | |
518 | ||
519 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 ie_d00lth_m1or ( | |
520 | .din0( d2_m1xor[65:0] ), | |
521 | .din1( sqe_cnt1[65:0] ), | |
522 | .dout( d2_m1_in[65:0] )); | |
523 | ||
524 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66 ie_d00lth ( | |
525 | .scan_in(ie_d00lth_scanin), | |
526 | .scan_out(ie_d00lth_scanout), | |
527 | .clk ( l2clk ), | |
528 | .en ( div_clken_rep0 ), // powerdown pin | |
529 | .din0( d2_m1_in[65:0] ), | |
530 | .din1( d2_00_in[65:0] ), | |
531 | .din2( d2_p1_in[65:0] ), | |
532 | .din3( divisor_new[65:0] ), | |
533 | .sel0( fdc_qsel1[0] ), | |
534 | .sel1( fdc_qsel1[1] ), | |
535 | .sel2( fdc_qsel1[2] ), | |
536 | .sel3( engine_start ), | |
537 | .dout( d0[65:0] ), | |
538 | .se(se), | |
539 | .siclk(siclk), | |
540 | .soclk(soclk), | |
541 | .pce_ov(pce_ov), | |
542 | .stop(stop)); | |
543 | ||
544 | // assign effd0_00[65:0] = d0[65:0]; Not used | |
545 | ||
546 | ||
547 | // Post-LTH version of the logic | |
548 | // assign effd0_p1_[65:0] = ~( d0[65:0] | sqe_cnt1[65:0]); | |
549 | ||
550 | // Pre-LTH version of the logic | |
551 | // assign effd2_p1_p1in = ~( ( d1 | cnt1 ) | cnt3); | |
552 | // assign effd2_00_p1in = ~( ( d1 ) | cnt3); | |
553 | // assign effd1_m1_p1in = ~( ((d1 ^ flip1) | cnt1) | cnt3); | |
554 | ||
555 | // assign effd2_p1_p1in[65:0] = ~( d1[65:0] | sqe_cnt13[65:0]); | |
556 | // assign effd2_00_p1in[65:0] = ~( d1[65:0] | sqe_cnt3[65:0] ); | |
557 | // assign effd2_m1_p1in[65:0] = ~((d1[65:0] ^ flip1[65:0]) | sqe_cnt13[65:0]); | |
558 | // assign effd2_xx_p1in[65:0] = ~(divisor_new[65:0] | {2'b00,fdc_ie_fsqrt_valid_odd,fdc_ie_fsqrt_valid_even,{62{1'b0}}}); | |
559 | ||
560 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d00lthp1_p1nor ( | |
561 | .din0( d1[64:0] ), | |
562 | .din1( sqe_cnt13[64:0] ), | |
563 | .dout( effd2_p1_p1in[64:0] )); | |
564 | ||
565 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d00lthp1_00nor ( | |
566 | .din0( d1[64:0] ), | |
567 | .din1( sqe_cnt3[64:0] ), | |
568 | .dout( effd2_00_p1in[64:0] )); | |
569 | ||
570 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d00lthp1_m1nor ( | |
571 | .din0( d2_m1xor[64:0] ), | |
572 | .din1( sqe_cnt13[64:0] ), | |
573 | .dout( effd2_m1_p1in[64:0] )); | |
574 | ||
575 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d00lthp1_xxnor ( | |
576 | .din0( divisor_new[64:0] ), | |
577 | .din1({1'b0,fdc_ie_fsqrt_valid_odd,fdc_ie_fsqrt_valid_even,{62{1'b0}}}), | |
578 | .dout( effd2_xx_p1in[64:0] )); | |
579 | ||
580 | ||
581 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65 ie_d00lthp1 ( | |
582 | .scan_in(ie_d00lthp1_scanin), | |
583 | .scan_out(ie_d00lthp1_scanout), | |
584 | .clk ( l2clk ), | |
585 | .en ( div_clken_rep0 ), // powerdown pin | |
586 | .din0( effd2_m1_p1in[64:0] ), | |
587 | .din1( effd2_00_p1in[64:0] ), | |
588 | .din2( effd2_p1_p1in[64:0] ), | |
589 | .din3( effd2_xx_p1in[64:0] ), | |
590 | .sel0( fdc_qsel1[0] ), | |
591 | .sel1( fdc_qsel1[1] ), | |
592 | .sel2( fdc_qsel1[2] ), | |
593 | .sel3( engine_start ), | |
594 | .dout( effd0_p1_[64:0] ), | |
595 | .se(se), | |
596 | .siclk(siclk), | |
597 | .soclk(soclk), | |
598 | .pce_ov(pce_ov), | |
599 | .stop(stop)); | |
600 | ||
601 | ||
602 | ||
603 | // Post-LTH version of the logic | |
604 | // assign effd0_m1[65:0] = (d0[65:0] ^ (flip0[65:0] | sqe_cnt0[65:0])) | sqe_cnt1[65:0]; | |
605 | // assign effd0_m1[65:0] = (d0[65:0] ^ flip0[65:0] ) | sqe_cnt01[65:0]; d0 has no overlap w/ cnt0 | |
606 | ||
607 | // Pre-LTH version of the logic | |
608 | // assign effd2_p1_m1in = ( (d1 | cnt1) ^ flip2 ) | cnt2 | cnt3; flip2 = cnt1; for p1 select | |
609 | // assign effd2_p1_m1in = ( (d1 | cnt1) ^ cnt1 ) | cnt2 | cnt3; d1 has no overlap w/ cnt1 | |
610 | // assign effd2_p1_m1in = ( d1 ) | cnt2 | cnt3; | |
611 | ||
612 | // assign effd1_00_m1in = ( d1 ^ flip2 ) | cnt2 | cnt3; flip2 = flip1 | cnt1; for 00 select | |
613 | // assign effd1_00_m1in = ( d1 ^ (flip1 | cnt1) | cnt2 | cnt3; d1 has no overlap w/ cnt1 | |
614 | // assign effd1_00_m1in = ( d1 ^ flip1 ) | cnt1 | cnt2 | cnt3; | |
615 | ||
616 | // assign effd1_m1_m1in = ( ((d1 ^ flip1) | cnt1) ^ flip2) | cnt2 | cnt3; flip2 = cnt1; for m1 select | |
617 | // assign effd1_m1_m1in = ( ((d1 ^ flip1) | cnt1) ^ cnt1 ) | cnt2 | cnt3; d1 has no overlap w/ cnt1 | |
618 | // assign effd1_m1_m1in = ( ((d1 ^ flip1) ) | cnt2 | cnt3; | |
619 | ||
620 | // assign effd2_p1_m1in[65:0] = d1[65:0] | sqe_cnt23[65:0] ; | |
621 | // assign effd2_00_m1in[65:0] = (d1[65:0] ^ flip1[65:0]) | sqe_cnt123[65:0]; | |
622 | // assign effd2_m1_m1in[65:0] = (d1[65:0] ^ flip1[65:0]) | sqe_cnt23[65:0] ; | |
623 | ||
624 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d00lthm1_p1or ( | |
625 | .din0( d1[64:0] ), | |
626 | .din1( sqe_cnt23[64:0] ), | |
627 | .dout( effd2_p1_m1in[64:0] )); | |
628 | ||
629 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d00lthm1_00or ( | |
630 | .din0( d2_m1xor[64:0] ), | |
631 | .din1( sqe_cnt123[64:0] ), | |
632 | .dout( effd2_00_m1in[64:0] )); | |
633 | ||
634 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d00lthm1_m1or ( | |
635 | .din0( d2_m1xor[64:0] ), | |
636 | .din1( sqe_cnt23[64:0] ), | |
637 | .dout( effd2_m1_m1in[64:0] )); | |
638 | ||
639 | ||
640 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65 ie_d00lthm1 ( | |
641 | .scan_in(ie_d00lthm1_scanin), | |
642 | .scan_out(ie_d00lthm1_scanout), | |
643 | .clk ( l2clk ), | |
644 | .en ( div_clken_rep0 ), // powerdown pin | |
645 | .din0( effd2_m1_m1in[64:0] ), | |
646 | .din1( effd2_00_m1in[64:0] ), | |
647 | .din2( effd2_p1_m1in[64:0] ), | |
648 | .din3( divisor_new[64:0] ), | |
649 | .sel0( fdc_qsel1[0] ), | |
650 | .sel1( fdc_qsel1[1] ), | |
651 | .sel2( fdc_qsel1[2] ), | |
652 | .sel3( engine_start ), | |
653 | .dout( effd0_m1[64:0] ), | |
654 | .se(se), | |
655 | .siclk(siclk), | |
656 | .soclk(soclk), | |
657 | .pce_ov(pce_ov), | |
658 | .stop(stop)); | |
659 | ||
660 | ||
661 | ||
662 | // fgu_fdq_cust ie_qslc00 ( | |
663 | // .sum ( s0[65:62] ), | |
664 | // .carry( c0[65:62] ), | |
665 | // .fdq_qip1 ( qsel00[2:0] )); // q(i+1) == +1, 0, -1 | |
666 | ||
667 | ||
668 | fgu_fdd_dp_csa32_macro__stack_66c__width_65 ie_csa11 ( | |
669 | .i0 ( s0[64:0] ), | |
670 | .i1 ({c0[64:2],1'b0,fdc_bsign_lth }), | |
671 | .i2 ( effd0_m1[64:0] ), | |
672 | .carry({ie_csa11_unused,c11[64:1] }), | |
673 | .sum ( s11[64:0] )); | |
674 | ||
675 | ||
676 | fgu_fdd_dp_csa32_macro__stack_66c__width_65 ie_csa10 ( | |
677 | .i0 ( s0[64:0] ), | |
678 | .i1 ({c0[64:2],1'b0,fdc_bsign_lth_}), | |
679 | .i2 ( effd0_p1_[64:0] ), | |
680 | .carry({ie_csa10_unused,c10[64:1] }), | |
681 | .sum ( s10[64:0] )); | |
682 | ||
683 | ||
684 | fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_65 ie_s1mux ( | |
685 | .din0( s11[64:0] ), | |
686 | .din1( s0[64:0] ), | |
687 | .din2( s10[64:0] ), | |
688 | .sel0( fdc_qsel00[0] ), | |
689 | .sel1( fdc_qsel00[1] ), | |
690 | .sel2( fdc_qsel00[2] ), | |
691 | .dout( s1[65:1] )); | |
692 | ||
693 | fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_64 ie_c1mux ( | |
694 | .din0( c11[64:1] ), | |
695 | .din1({c0[64:2],1'b0 }), | |
696 | .din2( c10[64:1] ), | |
697 | .sel0( fdc_qsel00[0] ), | |
698 | .sel1( fdc_qsel00[1] ), | |
699 | .sel2( fdc_qsel00[2] ), | |
700 | .dout( c1[65:2] )); | |
701 | ||
702 | ||
703 | // assign d1_p1_in[65:0] = d0[65:0] | sqe_cnt0[65:0]; | |
704 | assign d1_00_in[65:0] = d0[65:0] ; | |
705 | // assign d1_m1_in[65:0] = (d0[65:0] ^ flip0[65:0]) | sqe_cnt0[65:0]; | |
706 | ||
707 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 ie_d1mux_p1or ( | |
708 | .din0( d0[65:0] ), | |
709 | .din1( sqe_cnt0[65:0] ), | |
710 | .dout( d1_p1_in[65:0] )); | |
711 | ||
712 | fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66 ie_d1mux_m1xor ( | |
713 | .din0( d0[65:0] ), | |
714 | .din1( flip0[65:0] ), | |
715 | .dout( d1_m1xor[65:0] )); | |
716 | ||
717 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 ie_d1mux_m1or ( | |
718 | .din0( d1_m1xor[65:0] ), | |
719 | .din1( sqe_cnt0[65:0] ), | |
720 | .dout( d1_m1_in[65:0] )); | |
721 | ||
722 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66 ie_d1mux ( | |
723 | .din0( d1_m1_in[65:0] ), | |
724 | .din1( d1_00_in[65:0] ), | |
725 | .din2( d1_p1_in[65:0] ), | |
726 | .sel0( fdc_qsel00[0] ), | |
727 | .sel1( fdc_qsel00[1] ), | |
728 | .sel2( fdc_qsel00[2] ), | |
729 | .dout( d1[65:0] )); | |
730 | ||
731 | // assign effd1_00[65:0] = d1[65:0]; Not used | |
732 | ||
733 | ||
734 | // Post-MUX version of the logic | |
735 | // assign effd1_p1_[65:0] = ~( d1[65:0] | sqe_cnt2[65:1]); | |
736 | ||
737 | // assign effd1_p1_p1in[65:0] = ~( d0[65:0] | sqe_cnt02[65:0]); | |
738 | // assign effd1_00_p1in[65:0] = ~( d0[65:0] | sqe_cnt2[65:0] ); | |
739 | // assign effd1_m1_p1in[65:0] = ~((d0[65:0] ^ flip0[65:0]) | sqe_cnt02[65:0]); | |
740 | ||
741 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d1muxp1_p1nor ( | |
742 | .din0( d0[64:0] ), | |
743 | .din1( sqe_cnt02[64:0] ), | |
744 | .dout( effd1_p1_p1in[64:0] )); | |
745 | ||
746 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d1muxp1_00nor ( | |
747 | .din0( d0[64:0] ), | |
748 | .din1( sqe_cnt2[64:0] ), | |
749 | .dout( effd1_00_p1in[64:0] )); | |
750 | ||
751 | fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ie_d1muxp1_m1nor ( | |
752 | .din0( d1_m1xor[64:0] ), | |
753 | .din1( sqe_cnt02[64:0] ), | |
754 | .dout( effd1_m1_p1in[64:0] )); | |
755 | ||
756 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65 ie_d1muxp1 ( | |
757 | .din0( effd1_m1_p1in[64:0] ), | |
758 | .din1( effd1_00_p1in[64:0] ), | |
759 | .din2( effd1_p1_p1in[64:0] ), | |
760 | .sel0( fdc_qsel00[0] ), | |
761 | .sel1( fdc_qsel00[1] ), | |
762 | .sel2( fdc_qsel00[2] ), | |
763 | .dout( effd1_p1_[64:0] )); | |
764 | ||
765 | ||
766 | ||
767 | // Post-MUX version of the logic | |
768 | // assign effd1_m1[65:0] = (d1[65:0] ^ (flip1[65:0] | sqe_cnt1[65:0])) | sqe_cnt2[65:1] ; | |
769 | ||
770 | // Pre-MUX intermediate version of logic (see 'effd2_XX_m1in' for simplication details) | |
771 | // assign effd1_p1_m1in = ( (d0 | sqe_cnt0) ^ (flip1 | sqe_cnt1)) | sqe_cnt2; | |
772 | // assign effd1_00_m1in = ( d0 ^ (flip1 | sqe_cnt1)) | sqe_cnt2; | |
773 | // assign effd1_m1_m1in = (((d0 ^ flip0) | sqe_cnt0) ^ (flip1 | sqe_cnt1)) | sqe_cnt2; | |
774 | ||
775 | // assign effd1_p1_m1in[65:0] = d0[65:0] | sqe_cnt12[65:0] ; | |
776 | // assign effd1_00_m1in[65:0] = (d0[65:0] ^ flip0[65:0]) | sqe_cnt012[65:0]; | |
777 | // assign effd1_m1_m1in[65:0] = (d0[65:0] ^ flip0[65:0]) | sqe_cnt12[65:0] ; | |
778 | ||
779 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d1muxm1_p1or ( | |
780 | .din0( d0[64:0] ), | |
781 | .din1( sqe_cnt12[64:0] ), | |
782 | .dout( effd1_p1_m1in[64:0] )); | |
783 | ||
784 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d1muxm1_00or ( | |
785 | .din0( d1_m1xor[64:0] ), | |
786 | .din1( sqe_cnt012[64:0] ), | |
787 | .dout( effd1_00_m1in[64:0] )); | |
788 | ||
789 | fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ie_d1muxm1_m1or ( | |
790 | .din0( d1_m1xor[64:0] ), | |
791 | .din1( sqe_cnt12[64:0] ), | |
792 | .dout( effd1_m1_m1in[64:0] )); | |
793 | ||
794 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65 ie_d1muxm1 ( | |
795 | .din0( effd1_m1_m1in[64:0] ), | |
796 | .din1( effd1_00_m1in[64:0] ), | |
797 | .din2( effd1_p1_m1in[64:0] ), | |
798 | .sel0( fdc_qsel00[0] ), | |
799 | .sel1( fdc_qsel00[1] ), | |
800 | .sel2( fdc_qsel00[2] ), | |
801 | .dout( effd1_m1[64:0] )); | |
802 | ||
803 | ||
804 | ||
805 | ||
806 | // fgu_fdq_cust ie_qslc1p ( | |
807 | // .sum ( s11[64:61] ), | |
808 | // .carry ( c11[64:61] ), | |
809 | // .fdq_qip1 ( qsel1p[2:0] )); // q(i+1) == +1, 0, -1 | |
810 | ||
811 | // fgu_fdq_cust ie_qslc10 ( | |
812 | // .sum ( s0_buf[64:61] ), | |
813 | // .carry ( c0_buf[64:61] ), | |
814 | // .fdq_qip1 ( qsel10[2:0] )); // q(i+1) == +1, 0, -1 | |
815 | ||
816 | // fgu_fdq_cust ie_qslc1n ( | |
817 | // .sum ( s10[64:61] ), | |
818 | // .carry ( c10[64:61] ), | |
819 | // .fdq_qip1 ( qsel1n[2:0] )); // q(i+1) == +1, 0, -1 | |
820 | ||
821 | ||
822 | assign fdd_fdq00_10_sum[4:0] = s0[65:61]; | |
823 | assign fdd_fdq00_10_carry[4:0] = c0[65:61]; | |
824 | ||
825 | assign fdd_fdq1p_sum[3:0] = s11[64:61]; | |
826 | assign fdd_fdq1p_carry[3:0] = c11[64:61]; | |
827 | ||
828 | assign fdd_fdq1n_sum[3:0] = s10[64:61]; | |
829 | assign fdd_fdq1n_carry[3:0] = c10[64:61]; | |
830 | ||
831 | ||
832 | ||
833 | ||
834 | // Timing change : 7-17-02 | |
835 | // | |
836 | // and_macro ie_qslc00a (width=3,ports=2,stack=66c) ( | |
837 | // .din0 ( fdc_qsel00[2:0] ), | |
838 | // .din1 ({3{engine_start_ }}), | |
839 | // .dout ( gated_qsel00[2:0] )); | |
840 | // | |
841 | // mux_macro ie_qslcmux (width=3,ports=3,mux=aonpe,buffsel=none,stack=66c) ( | |
842 | // .din0( qsel1p[2:0] ), | |
843 | // .din1( qsel10[2:0] ), | |
844 | // .din2( qsel1n[2:0] ), // PR(i+1) = PR(i) - qD; | |
845 | // .sel0( gated_qsel00[0] ), // PR + D -> therefore q = -1 | |
846 | // .sel1( gated_qsel00[1] ), | |
847 | // .sel2( gated_qsel00[2] ), // PR - D -> therefore q = +1 | |
848 | // .dout( qsel1[2:0] )); | |
849 | ||
850 | ||
851 | fgu_fdd_dp_csa32_macro__stack_66c__width_65 ie_csa21 ( | |
852 | .i0 ({s1[64:1],1'b0 }), | |
853 | .i1 ({c1[64:2],1'b0,fdc_bsign_lth }), | |
854 | .i2 ( effd1_m1[64:0] ), | |
855 | .carry({ie_csa21_unused,c21[64:1] }), | |
856 | .sum ( s21[64:0] )); | |
857 | ||
858 | ||
859 | fgu_fdd_dp_csa32_macro__stack_66c__width_65 ie_csa20 ( | |
860 | .i0 ({s1[64:1],1'b0 }), | |
861 | .i1 ({c1[64:2],1'b0,fdc_bsign_lth_}), | |
862 | .i2 ( effd1_p1_[64:0] ), | |
863 | .carry({ie_csa20_unused,c20[64:1] }), | |
864 | .sum ( s20[64:0] )); | |
865 | ||
866 | ||
867 | ||
868 | ||
869 | // During pte_cycle[3], an extra shift will occur in both q_lth and qm1_lth. | |
870 | // Both latches are made 2-bits wider so no data is lost. | |
871 | ||
872 | ||
873 | // Floorplan note : pack "ie_qmuxh" and "ie_qmuxl" on same row | |
874 | ||
875 | fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 ie_qmuxh ( | |
876 | .din0({64{1'b0} }), | |
877 | .din1( q_lth[63:0] ), | |
878 | .sel0( engine_start ), | |
879 | .dout( q_in[65:2] )); | |
880 | ||
881 | ||
882 | ||
883 | ||
884 | fgu_fdd_dp_msff_macro__stack_66c__width_66 ie_qlth ( | |
885 | .scan_in(ie_qlth_scanin), | |
886 | .scan_out(ie_qlth_scanout), | |
887 | .clk ( l2clk ), | |
888 | .en ( div_clken_rep0 ), // powerdown pin | |
889 | .din ({q_in[65:2],fdc_q_in[1:0]}), | |
890 | .dout( q_lth[65:0] ), | |
891 | .se(se), | |
892 | .siclk(siclk), | |
893 | .soclk(soclk), | |
894 | .pce_ov(pce_ov), | |
895 | .stop(stop)); | |
896 | ||
897 | ||
898 | fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 ie_qm1muxh ( | |
899 | .din0({64{1'b0} }), | |
900 | .din1( qm1_lth[63:0] ), | |
901 | .sel0( engine_start ), | |
902 | .dout( qm1_in[65:2] )); | |
903 | ||
904 | ||
905 | fgu_fdd_dp_msff_macro__stack_66c__width_66 ie_qm1lth ( | |
906 | .scan_in(ie_qm1lth_scanin), | |
907 | .scan_out(ie_qm1lth_scanout), | |
908 | .clk ( l2clk ), | |
909 | .en ( div_clken_rep0 ), // powerdown pin | |
910 | .din ({qm1_in[65:2],fdc_qm1_in[1:0]}), | |
911 | .dout( qm1_lth[65:0] ), | |
912 | .se(se), | |
913 | .siclk(siclk), | |
914 | .soclk(soclk), | |
915 | .pce_ov(pce_ov), | |
916 | .stop(stop)); | |
917 | ||
918 | fgu_fdd_dp_inv_macro__stack_66c__width_65 ie_qm1inv ( | |
919 | .din ( qm1_lth[65:1] ), | |
920 | .dout( qm1_lth_[65:1] )); | |
921 | ||
922 | ||
923 | ||
924 | // * * * * * * * * * * * * * * "post-engine" * * * * * * * * * * * * * * | |
925 | ||
926 | // The CIN to the adder for the R = Q - Qm1 cycle is very confusing. | |
927 | // For positive operands it is fairly straight forward. When we | |
928 | // invert Qm1, we should add the CIN to create the 2's complement. | |
929 | // However, when the final remainder is negative, the Q is one too | |
930 | // large. To correct for this, we need to add one to Qm1 before | |
931 | // we compute the final result. By withholding the CIN, we effectively | |
932 | // make Qm1 appear one larger than what we originally logged. | |
933 | // | |
934 | // For a negative B operand, the situation is more complicated. | |
935 | // When the final remainder is positive, we need to add the CIN | |
936 | // so that R = Q - Qm1 is computed correctly. For a negative | |
937 | // remainder, not only do we need to add the CIN for the 2's | |
938 | // complement of Qm1, but we must also add a one to the Q. | |
939 | // Remember that the logging of the quotient digits is reversed | |
940 | // for a negative B operand. So, when the final remainder is | |
941 | // negative, that means that Qm1 is one larger than is should have | |
942 | // been. To correct, we need to add one to the Q to correct. | |
943 | // | |
944 | // Notice the the table has a symmetry around the A operand. | |
945 | // The correction method (adding one to Q or to Qm1) becomes | |
946 | // reversed when A is negative. | |
947 | // | |
948 | // The table below will summarize. ('->' is a correction row) | |
949 | // | |
950 | // Sign of Sign of Sign of | Zero Method | |
951 | // A B Remainder | Remainder Action | CSA Cin | |
952 | // -------------------------------|-------------------|----------- | |
953 | // 0 0 0 | add 1 | 0 1 | |
954 | // -> 0 0 1 | add 0 | 0 0 | |
955 | // 0 1 0 | add 1 | 1 0 | |
956 | // -> 0 1 1 | add 2 | 1 1 | |
957 | // 1 0 0 | yes add 1 | 1 0 | |
958 | // -> 1 0 0 | no add 2 | 1 1 | |
959 | // 1 0 1 | add 1 | 1 0 | |
960 | // 1 1 0 | yes add 1 | 0 1 | |
961 | // -> 1 1 0 | no add 0 | 0 0 | |
962 | // 1 1 1 | add 1 | 0 1 | |
963 | ||
964 | ||
965 | fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64 ipte_qmux ( | |
966 | .din0( q_lth[65:2] ), // INT even ndp | |
967 | .din1( q_lth[64:1] ), // INT odd ndq correction | |
968 | .din2({q_lth[55:1],{ 9{1'b0}} }), // FLT DP | |
969 | .din3({q_lth[27:2],{38{1'b0}} }), // FLT SP | |
970 | .sel0( fdc_pte_qsel[0] ), | |
971 | .sel1( fdc_pte_qsel[1] ), | |
972 | .sel2( fdc_pte_qsel[2] ), | |
973 | .dout( pte_q[65:2] )); | |
974 | ||
975 | fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64 ipte_qm1mux ( | |
976 | .din0( qm1_lth_[65:2] ), // INT even ndq | |
977 | .din1( qm1_lth_[64:1] ), // INT odd ndq correction | |
978 | .din2({qm1_lth_[55:1],{ 9{1'b1}}}), // FLT DP | |
979 | .din3({qm1_lth_[27:2],{38{1'b1}}}), // FLT SP | |
980 | .sel0( fdc_pte_qsel[0] ), | |
981 | .sel1( fdc_pte_qsel[1] ), | |
982 | .sel2( fdc_pte_qsel[2] ), | |
983 | .dout( pte_qm1_[65:2] )); | |
984 | ||
985 | fgu_fdd_dp_csa32_macro__stack_66c__width_64 ipte_csa ( | |
986 | .i0 ( pte_q[65:2] ), | |
987 | .i1 ( pte_qm1_[65:2] ), | |
988 | .i2 ({{63{1'b0}}, fdc_pte_csa_cin }), | |
989 | .carry({ipte_csa_unused,pte_carry[63:1]}), | |
990 | .sum ( pte_sum[63:0] )); | |
991 | ||
992 | ||
993 | fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_65 ipte_clalth0 ( | |
994 | .scan_in(ipte_clalth0_scanin), | |
995 | .scan_out(ipte_clalth0_scanout), | |
996 | .clk ( l2clk ), | |
997 | .en ( div_clken_rep0 ), // powerdown pin | |
998 | .din0( s0[65:1] ), | |
999 | .din1( s1[65:1] ), // odd ndq correction | |
1000 | .din2({1'b0,pte_sum[63:0]} ), // append cin=1 for Q-Qm1 to din1 | |
1001 | .din3({1'b0,pte_cla[63:0]} ), | |
1002 | .din4({1'b0,pte_cla[63:0]} ), | |
1003 | .din5({1'b0,pte_cla[62:0],1'b0} ), | |
1004 | .sel0( fdc_pte_clasel[0] ), | |
1005 | .sel1( fdc_pte_clasel[1] ), | |
1006 | .sel2( fdc_pte_cycle2 ), | |
1007 | .sel3( pte_cla[63] ), | |
1008 | .sel4( fdc_emin_lth ), | |
1009 | .dout( pte_clalth0[64:0] ), | |
1010 | .se(se), | |
1011 | .siclk(siclk), | |
1012 | .soclk(soclk), | |
1013 | .pce_ov(pce_ov), | |
1014 | .stop(stop)); | |
1015 | ||
1016 | ||
1017 | fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_65 ipte_clalth1 ( | |
1018 | .scan_in(ipte_clalth1_scanin), | |
1019 | .scan_out(ipte_clalth1_scanout), | |
1020 | .clk ( l2clk ), | |
1021 | .en ( div_clken_rep0 ), // powerdown pin | |
1022 | .din0({c0[65:2],1'b0} ), | |
1023 | .din1({c1[65:2],1'b0} ), // odd ndq correction | |
1024 | .din2({1'b0,pte_carry[63:1], | |
1025 | fdc_fdx_cin_in} ), | |
1026 | .din3({{24{1'b0}}, | |
1027 | fdc_flt_round[1], | |
1028 | {28{1'b0}}, | |
1029 | fdc_flt_round[0], | |
1030 | {11{1'b0}}} ), | |
1031 | .sel0( fdc_pte_clasel[0] ), | |
1032 | .sel1( fdc_pte_clasel[1] ), | |
1033 | .sel2( fdc_pte_cycle2 ), | |
1034 | .dout( pte_clalth1[64:0] ), | |
1035 | .se(se), | |
1036 | .siclk(siclk), | |
1037 | .soclk(soclk), | |
1038 | .pce_ov(pce_ov), | |
1039 | .stop(stop)); | |
1040 | ||
1041 | ||
1042 | ||
1043 | // hnb_fg_claz65 fpd_cla ( | |
1044 | // .din0 ( pte_clalth0[64:0] ), | |
1045 | // .din1 ({pte_clalth1[64:1],1'b0}), | |
1046 | // .cin ( pte_cin ), | |
1047 | // .asign ( fdc_asign_lth ), | |
1048 | // .bsign ( fdc_bsign_lth ), | |
1049 | // .cin_enable( fdc_pte_cycle2 ), | |
1050 | // .pte_cla ( pte_cla[64:0] ), | |
1051 | // .pte_zdetect( pte_zerodetect ), | |
1052 | // .pte_cin_in ( pte_cin_in )); | |
1053 | ||
1054 | ||
1055 | fgu_fdd_dp_cla_macro__width_64 ipte_cla ( | |
1056 | .din0 ( pte_clalth0[63:0] ), | |
1057 | .din1 ( pte_clalth1[63:0] ), | |
1058 | .cin ( 1'b0 ), | |
1059 | .dout ( pte_cla[63:0] ), | |
1060 | .cout ( pte_cla_cout )); | |
1061 | ||
1062 | fgu_fdd_dp_and_macro__ports_2__stack_66c__width_1 ipte_cla63_and ( | |
1063 | .din0 ( pte_cla[63] ), | |
1064 | .din1 ( fdc_flt_increment ), | |
1065 | .dout ( fdd_pte_cla_early_b63 )); | |
1066 | ||
1067 | cl_dp1_zdt64_8x ipte_claz ( | |
1068 | .din0 ( pte_clalth0[63:0] ), | |
1069 | .din1 ( pte_clalth1[63:0] ), | |
1070 | .cin ( 1'b0 ), | |
1071 | .zdt_z32_ ( fdd_cla_zero32_ ), | |
1072 | .zdt_z64_ ( fdd_cla_zero64_ )); | |
1073 | ||
1074 | // fgu_fdx_cust ipte_cla65 ( | |
1075 | // .din0 ( pte_clalth0[64] ), | |
1076 | // .din1 ( pte_clalth1[64] ), | |
1077 | // .cin64 ( pte_cla_cout ), | |
1078 | // .asign ( fdc_asign_lth ), | |
1079 | // .bsign ( fdc_bsign_lth ), | |
1080 | // .cin_enable( fdc_pte_cycle2 ), | |
1081 | // .z64_l ( fdd_cla_zero64_ ), | |
1082 | // .fdx_cin_in( pte_cin_in )); | |
1083 | ||
1084 | ||
1085 | assign fdd_fdx_din0 = pte_clalth0[64]; | |
1086 | assign fdd_fdx_din1 = pte_clalth1[64]; | |
1087 | assign fdd_fdx_cin64 = pte_cla_cout; | |
1088 | ||
1089 | ||
1090 | ||
1091 | fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_64 ipte_result ( | |
1092 | .scan_in(ipte_result_scanin), | |
1093 | .scan_out(ipte_result_scanout), | |
1094 | .clk ( l2clk ), | |
1095 | .en ( fdc_pte_stall_ ), // powerdown pin | |
1096 | .din0( 64'h8000000000000000 ), | |
1097 | .din1( 64'hffffffff80000000 ), | |
1098 | .din2( 64'h000000007fffffff ), | |
1099 | .din3( 64'h00000000ffffffff ), | |
1100 | .din4({fdd_result[62:0],1'b0} ), | |
1101 | .din5( pte_cla[63:0] ), | |
1102 | .sel0( fdc_idiv_ctl[0] ), | |
1103 | .sel1( fdc_idiv_ctl[1] ), | |
1104 | .sel2( fdc_idiv_ctl[2] ), | |
1105 | .sel3( fdc_idiv_ctl[3] ), | |
1106 | .sel4( fdc_idiv_ctl[4] ), | |
1107 | .dout( fdd_result[63:0] ), | |
1108 | .se(se), | |
1109 | .siclk(siclk), | |
1110 | .soclk(soclk), | |
1111 | .pce_ov(pce_ov), | |
1112 | .stop(stop)); | |
1113 | ||
1114 | ||
1115 | ||
1116 | // * * * * * * * * * * * * * * square root * * * * * * * * * * * * * * | |
1117 | ||
1118 | // The CNT bit represents where the newest effective divisor digit will go. | |
1119 | // For divide instruction, this latch will be all 0's and the original divisor | |
1120 | // will remain unchanged. | |
1121 | // The 'flip' register allows us to quickly compute the effect of a "-1" at position | |
1122 | // "i" will have on the next effective divisor. | |
1123 | ||
1124 | // Define cnt(i) == single bit ON with position "i"; | |
1125 | // Q(0) == 0; | |
1126 | // flip(0) == 0; | |
1127 | ||
1128 | // for "+1" -> Q(i+1) = Q(i) | cnt(i); | |
1129 | // flip(i+1) = cnt(i) ; | |
1130 | ||
1131 | // for "-1" -> Q(i+1) = (Q(i) ^ flip(i)) | cnt(i); | |
1132 | // flip(i+1) = cnt(i) ; | |
1133 | ||
1134 | // for " 0" -> Q(i+1) = Q(i) ; | |
1135 | // flip(i+1) = cnt(i) | flip(i) ; | |
1136 | ||
1137 | ||
1138 | // Example : let i = 000000001 | |
1139 | // let Q = 011010000 | |
1140 | // then flip = 000011110 | |
1141 | // | |
1142 | // if we get a "-1" at i, then | |
1143 | // Q = (Q ^ flip) | cnt | |
1144 | // Q = 011001111; this is the same as a "-1" at "i" added to Q | |
1145 | ||
1146 | fgu_fdd_dp_msff_macro__mux_aope__ports_2__stack_66c__width_66 isqe_cnt ( | |
1147 | .scan_in(isqe_cnt_scanin), | |
1148 | .scan_out(isqe_cnt_scanout), | |
1149 | .clk ( l2clk ), | |
1150 | .en ( div_clken_rep0 ), // powerdown pin | |
1151 | .din0({1'b1, | |
1152 | fdc_ie_fsqrt_valid_odd_, | |
1153 | fdc_ie_fsqrt_valid_even_, | |
1154 | {63{1'b1}} }), | |
1155 | .din1( sqe_cnt2_[65:0] ), | |
1156 | .sel0( engine_start ), // | |
1157 | .dout( sqe_cnt0_[65:0] ), | |
1158 | .se(se), | |
1159 | .siclk(siclk), | |
1160 | .soclk(soclk), | |
1161 | .pce_ov(pce_ov), | |
1162 | .stop(stop)); | |
1163 | ||
1164 | fgu_fdd_dp_inv_macro__stack_66c__width_66 isqe_cntinv ( | |
1165 | .din ( sqe_cnt0_[65:0] ), | |
1166 | .dout( sqe_cnt0[65:0] )); | |
1167 | ||
1168 | ||
1169 | fgu_fdd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 isqe_flip ( | |
1170 | .scan_in(isqe_flip_scanin), | |
1171 | .scan_out(isqe_flip_scanout), | |
1172 | .clk ( l2clk ), | |
1173 | .en ( div_clken_rep0 ), // powerdown pin | |
1174 | .din0( flip1[65:0] ), | |
1175 | .din1( sqe_cnt1[65:0] ), | |
1176 | .sel0( fdc_qsel1[1] ), | |
1177 | .sel1( engine_start_ ), // mux output == flip2 | |
1178 | .dout( flip0[65:0] ), | |
1179 | .se(se), | |
1180 | .siclk(siclk), | |
1181 | .soclk(soclk), | |
1182 | .pce_ov(pce_ov), | |
1183 | .stop(stop)); | |
1184 | ||
1185 | ||
1186 | // assign flip1[65:0] = sqe_cnt0[65:0] | | |
1187 | // ({66{fdc_qsel00[1]}} & flip0[65:0]); | |
1188 | ||
1189 | // assign flip2[65:0] = sqe_cnt1[65:0] | | |
1190 | // ({66{qsel1[1]}} & flip1[65:0]); | |
1191 | ||
1192 | fgu_fdd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_66 isqe_flip1 ( | |
1193 | .din0( flip0[65:0] ), | |
1194 | .din1( sqe_cnt0[65:0] ), | |
1195 | .sel0( fdc_qsel00[1] ), | |
1196 | .sel1( 1'b1 ), | |
1197 | .dout( flip1[65:0] )); | |
1198 | ||
1199 | ||
1200 | assign sqe_cnt1[65:0] = {1'b0 ,sqe_cnt0[65:1]}; | |
1201 | assign sqe_cnt2[64:0] = {1'b0 ,sqe_cnt0[65:2]}; | |
1202 | assign sqe_cnt3[64:0] = {2'b00 ,sqe_cnt0[65:3]}; | |
1203 | ||
1204 | assign sqe_cnt1_[65:0] = {1'b1 ,sqe_cnt0_[65:1]}; | |
1205 | assign sqe_cnt2_[65:0] = {2'b11 ,sqe_cnt0_[65:2]}; | |
1206 | // assign sqe_cnt3_[65:0] = {3'b111,sqe_cnt0_[65:3]}; | |
1207 | ||
1208 | // assign sqe_cnt012[65:0] = sqe_cnt0[65:0] | sqe_cnt1[65:0] | sqe_cnt2[65:0] ; | |
1209 | // assign sqe_cnt01[65:0] = sqe_cnt0[65:0] | sqe_cnt1[65:0] ; | |
1210 | // assign sqe_cnt02[65:0] = sqe_cnt0[65:0] | sqe_cnt2[65:0] ; | |
1211 | // assign sqe_cnt12[65:0] = sqe_cnt1[65:0] | sqe_cnt2[65:0] ; | |
1212 | // assign sqe_cnt123[65:0] = sqe_cnt1[65:0] | sqe_cnt2[65:0] | sqe_cnt3[65:0]; | |
1213 | // assign sqe_cnt13[65:0] = sqe_cnt1[65:0] | sqe_cnt3[65:0]; | |
1214 | // assign sqe_cnt23[65:0] = sqe_cnt2[65:0] | sqe_cnt3[65:0]; | |
1215 | ||
1216 | ||
1217 | fgu_fdd_dp_nand_macro__ports_3__stack_66c__width_66 isqe_cnt012 ( | |
1218 | .din0( sqe_cnt0_[65:0] ), | |
1219 | .din1( sqe_cnt1_[65:0] ), | |
1220 | .din2( sqe_cnt2_[65:0] ), | |
1221 | .dout( sqe_cnt012[65:0] )); | |
1222 | ||
1223 | fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_65 isqe_cnt01 ( | |
1224 | .din0( sqe_cnt0_[65:1] ), | |
1225 | .din1( sqe_cnt1_[65:1] ), | |
1226 | .dout( sqe_cnt01[65:1] )); | |
1227 | ||
1228 | fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_66 isqe_cnt02 ( | |
1229 | .din0( sqe_cnt0_[65:0] ), | |
1230 | .din1( sqe_cnt2_[65:0] ), | |
1231 | .dout( sqe_cnt02[65:0] )); | |
1232 | ||
1233 | assign sqe_cnt12[64:0] = sqe_cnt01[65:1]; | |
1234 | assign sqe_cnt123[64:0] = sqe_cnt012[65:1]; | |
1235 | assign sqe_cnt13[64:0] = sqe_cnt02[65:1]; | |
1236 | assign sqe_cnt23[64:0] = {1'b0 ,sqe_cnt01[65:2]}; | |
1237 | ||
1238 | ||
1239 | ||
1240 | // * * * * * * * * * * * * * * square root * * * * * * * * * * * * * * | |
1241 | // | |
1242 | // Float Square Root Example | |
1243 | // | |
1244 | // see ~co132877/design/doc/fsqrt_examples for additional examples | |
1245 | // | |
1246 | // Notes : | |
1247 | // | |
1248 | // 1. PR(i+1) = 2PR(i) - q(i+1) * Dnew | |
1249 | // 2. Dnew = 2*Q(i) + q(i+1) * 2^-(i+1) | |
1250 | // 3. Q(i) == estimate of sqrt(RB) after ith iteration | |
1251 | // 4. PR(0) == RB | |
1252 | // 5. Q(0) == 0 | |
1253 | // | |
1254 | // | |
1255 | // Example 1 : RB = 1.1000 0000 0000 (PR kept in non-redundant form) | |
1256 | // | |
1257 | // RD = sqrt(RB) = 1.0011 1001 1000 1000 ... (from architectural simulator) | |
1258 | // | |
1259 | // | |
1260 | // i divisor qslc engine Q// Qm1 | |
1261 | // - ------------------------ ---- ------------------------ --------------- | |
1262 | // v | |
1263 | // 1 00.0 1000 0000 0000 0000 +1 00.0 1100 0000 0000 0000 1. | |
1264 | // +11.1 1000 0000 0000 0000 -0. | |
1265 | // ------------------------ -- | |
1266 | // 00.0 0100 0000 0000 0000 1. | |
1267 | // | |
1268 | // v | |
1269 | // 2 00.1 0100 0000 0000 0000 +1 00.0 1000 0000 0000 0000 1.1 | |
1270 | // +11.0 1100 0000 0000 0000 -0.0 | |
1271 | // ------------------------ --- | |
1272 | // 11.1 0100 0000 0000 0000 1.1 | |
1273 | // | |
1274 | // v | |
1275 | // 3 00.1 10m0 0000 0000 0000 -1 11.0 1000 0000 0000 0000 1.10 | |
1276 | // 00.1 0110 0000 0000 0000 +00.1 0110 0000 0000 0000 -0.01 | |
1277 | // ------------------------ ---- | |
1278 | // 11.1 1110 0000 0000 0000 1.01 | |
1279 | // | |
1280 | // v | |
1281 | // 4 00.1 0100 0000 0000 0000 0 11.1 1100 0000 0000 0000 1.100 | |
1282 | // +00.0 0000 0000 0000 0000 -0.010 | |
1283 | // ------------------------ ----- | |
1284 | // 11.1 1100 0000 0000 0000 1.010 | |
1285 | // | |
1286 | // v | |
1287 | // 5 00.1 0100 0000 0000 0000 0 11.1 1000 0000 0000 0000 1.1000 | |
1288 | // +00.0 0000 0000 0000 0000 -0.0100 | |
1289 | // ------------------------ ------ | |
1290 | // 11.1 1000 0000 0000 0000 1.0100 | |
1291 | // | |
1292 | // v | |
1293 | // 6 00.1 0100 0m00 0000 0000 -1 11.1 0000 0000 0000 0000 1.1000 0 | |
1294 | // 00.1 0011 1100 0000 0000 +00.1 0011 1100 0000 0000 -0.0100 1 | |
1295 | // ------------------------ -------- | |
1296 | // 00.0 0011 1100 0000 0000 1.0011 1 | |
1297 | // | |
1298 | // v | |
1299 | // 7 00.1 0011 1000 0000 0000 0 00.0 0111 1000 0000 0000 1.1000 00 | |
1300 | // +00.0 0000 0000 0000 0000 -0.0100 10 | |
1301 | // ------------------------ --------- | |
1302 | // 00.0 0111 1000 0000 0000 1.0011 10 | |
1303 | // | |
1304 | // v | |
1305 | // 8 00.1 0011 1001 0000 0000 +1 00.0 1111 0000 0000 0000 1.1000 001 | |
1306 | // +11.0 1100 0111 0000 0000 -0.0100 100 | |
1307 | // ------------------------ ---------- | |
1308 | // 11.1 1011 0111 0000 0000 1.0011 101 | |
1309 | // | |
1310 | // v | |
1311 | // 9 00.1 0011 1010 m000 0000 -1 11.1 0110 1110 0000 0000 1.1000 0010 | |
1312 | // 00.1 0011 1001 1000 0000 +00.1 0011 1001 1000 0000 -0.0100 1001 | |
1313 | // ------------------------ ----------- | |
1314 | // 00.0 1010 0111 1000 0000 1.0011 1001 | |
1315 | // | |
1316 | // v | |
1317 | // 10 00.1 0011 1001 0100 0000 +1 00.1 0100 1111 0000 0000 1.1000 0010 1 | |
1318 | // +11.0 1100 0110 1100 0000 -0.0100 1001 0 | |
1319 | // ------------------------ ------------- | |
1320 | // 00.0 0001 0101 1100 0000 1.0011 1001 1 | |
1321 | // | |
1322 | // v | |
1323 | // 11 00.1 0011 1001 1000 0000 0 00.0 0010 1011 1000 0000 1.1000 0010 10 | |
1324 | // +00.0 0000 0000 0000 0000 -0.0100 1001 00 | |
1325 | // ------------------------ -------------- | |
1326 | // 00.0 0010 1011 1000 0000 1.0011 1001 10 | |
1327 | // | |
1328 | // v | |
1329 | // 12 00.1 0011 1001 1000 0000 0 00.0 0101 0111 0000 0000 1.1000 0010 100 | |
1330 | // +00.0 0000 0000 0000 0000 -0.0100 1001 000 | |
1331 | // ------------------------ --------------- | |
1332 | // 00.0 0101 0111 0000 0000 1.0011 1001 100 | |
1333 | // | |
1334 | // v | |
1335 | // 13 00.1 0011 1001 1000 1000 +1 00.0 1010 1110 0000 0000 1.1000 0010 1001 | |
1336 | // +11.0 1100 0110 0111 1000 -0.0100 1001 0000 | |
1337 | // ------------------------ ---------------- | |
1338 | // 11.1 0111 0100 0111 1000 1.0011 1001 1001 | |
1339 | // | |
1340 | // v | |
1341 | // 14 00.1 0011 1001 1001 0m00 -1 11.0 1110 1000 1111 0000 1.1000 0010 1001 0 | |
1342 | // 00.1 0011 1001 1000 1100 +00.1 0011 1001 1000 1100 -0.0100 1001 0000 1 | |
1343 | // ------------------------ ------------------ | |
1344 | // 00.0 0011 0010 0111 1100 1.0011 1001 1000 1 | |
1345 | // | |
1346 | // | |
1347 | // RD = sqrt(RB) = 1.0011 1001 1000 1000 ... | |
1348 | // | |
1349 | // END EXAMPLE | |
1350 | ||
1351 | ||
1352 | // fixscan start: | |
1353 | assign q_rs1_ff_scanin = scan_in ; | |
1354 | assign q_rs2_ff_scanin = q_rs1_ff_scanout ; | |
1355 | assign ipe_clth_scanin = q_rs2_ff_scanout ; | |
1356 | assign ipe_slth_scanin = ipe_clth_scanout ; | |
1357 | assign ie_s00lth_scanin = ipe_slth_scanout ; | |
1358 | assign ie_c00lth_scanin = ie_s00lth_scanout ; | |
1359 | assign ie_d00lth_scanin = ie_c00lth_scanout ; | |
1360 | assign ie_d00lthp1_scanin = ie_d00lth_scanout ; | |
1361 | assign ie_d00lthm1_scanin = ie_d00lthp1_scanout ; | |
1362 | assign ie_qlth_scanin = ie_d00lthm1_scanout ; | |
1363 | assign ie_qm1lth_scanin = ie_qlth_scanout ; | |
1364 | assign ipte_clalth0_scanin = ie_qm1lth_scanout ; | |
1365 | assign ipte_clalth1_scanin = ipte_clalth0_scanout ; | |
1366 | assign ipte_result_scanin = ipte_clalth1_scanout ; | |
1367 | assign isqe_cnt_scanin = ipte_result_scanout ; | |
1368 | assign isqe_flip_scanin = isqe_cnt_scanout ; | |
1369 | assign scan_out = isqe_flip_scanout ; | |
1370 | // fixscan end: | |
1371 | endmodule | |
1372 | ||
1373 | ||
1374 | // | |
1375 | // buff macro | |
1376 | // | |
1377 | // | |
1378 | ||
1379 | ||
1380 | ||
1381 | ||
1382 | ||
1383 | module fgu_fdd_dp_buff_macro__dbuff_32x__rep_1__stack_66c__width_4 ( | |
1384 | din, | |
1385 | dout); | |
1386 | input [3:0] din; | |
1387 | output [3:0] dout; | |
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | ||
1394 | buff #(4) d0_0 ( | |
1395 | .in(din[3:0]), | |
1396 | .out(dout[3:0]) | |
1397 | ); | |
1398 | ||
1399 | ||
1400 | ||
1401 | ||
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | endmodule | |
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | // any PARAMS parms go into naming of macro | |
1417 | ||
1418 | module fgu_fdd_dp_msff_macro__stack_66c__width_64 ( | |
1419 | din, | |
1420 | clk, | |
1421 | en, | |
1422 | se, | |
1423 | scan_in, | |
1424 | siclk, | |
1425 | soclk, | |
1426 | pce_ov, | |
1427 | stop, | |
1428 | dout, | |
1429 | scan_out); | |
1430 | wire l1clk; | |
1431 | wire siclk_out; | |
1432 | wire soclk_out; | |
1433 | wire [62:0] so; | |
1434 | ||
1435 | input [63:0] din; | |
1436 | ||
1437 | ||
1438 | input clk; | |
1439 | input en; | |
1440 | input se; | |
1441 | input scan_in; | |
1442 | input siclk; | |
1443 | input soclk; | |
1444 | input pce_ov; | |
1445 | input stop; | |
1446 | ||
1447 | ||
1448 | ||
1449 | output [63:0] dout; | |
1450 | ||
1451 | ||
1452 | output scan_out; | |
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | cl_dp1_l1hdr_8x c0_0 ( | |
1458 | .l2clk(clk), | |
1459 | .pce(en), | |
1460 | .aclk(siclk), | |
1461 | .bclk(soclk), | |
1462 | .l1clk(l1clk), | |
1463 | .se(se), | |
1464 | .pce_ov(pce_ov), | |
1465 | .stop(stop), | |
1466 | .siclk_out(siclk_out), | |
1467 | .soclk_out(soclk_out) | |
1468 | ); | |
1469 | dff #(64) d0_0 ( | |
1470 | .l1clk(l1clk), | |
1471 | .siclk(siclk_out), | |
1472 | .soclk(soclk_out), | |
1473 | .d(din[63:0]), | |
1474 | .si({scan_in,so[62:0]}), | |
1475 | .so({so[62:0],scan_out}), | |
1476 | .q(dout[63:0]) | |
1477 | ); | |
1478 | ||
1479 | ||
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ||
1489 | ||
1490 | ||
1491 | ||
1492 | ||
1493 | ||
1494 | ||
1495 | ||
1496 | ||
1497 | ||
1498 | endmodule | |
1499 | ||
1500 | ||
1501 | ||
1502 | ||
1503 | ||
1504 | ||
1505 | ||
1506 | ||
1507 | ||
1508 | ||
1509 | ||
1510 | ||
1511 | ||
1512 | // any PARAMS parms go into naming of macro | |
1513 | ||
1514 | module fgu_fdd_dp_msff_macro__mux_aope__ports_3__stack_66c__width_64 ( | |
1515 | din0, | |
1516 | din1, | |
1517 | din2, | |
1518 | sel0, | |
1519 | sel1, | |
1520 | clk, | |
1521 | en, | |
1522 | se, | |
1523 | scan_in, | |
1524 | siclk, | |
1525 | soclk, | |
1526 | pce_ov, | |
1527 | stop, | |
1528 | dout, | |
1529 | scan_out); | |
1530 | wire psel0; | |
1531 | wire psel1; | |
1532 | wire psel2; | |
1533 | wire [63:0] muxout; | |
1534 | wire l1clk; | |
1535 | wire siclk_out; | |
1536 | wire soclk_out; | |
1537 | wire [62:0] so; | |
1538 | ||
1539 | input [63:0] din0; | |
1540 | input [63:0] din1; | |
1541 | input [63:0] din2; | |
1542 | input sel0; | |
1543 | input sel1; | |
1544 | ||
1545 | ||
1546 | input clk; | |
1547 | input en; | |
1548 | input se; | |
1549 | input scan_in; | |
1550 | input siclk; | |
1551 | input soclk; | |
1552 | input pce_ov; | |
1553 | input stop; | |
1554 | ||
1555 | ||
1556 | ||
1557 | output [63:0] dout; | |
1558 | ||
1559 | ||
1560 | output scan_out; | |
1561 | ||
1562 | ||
1563 | ||
1564 | ||
1565 | cl_dp1_penc3_8x c1_0 ( | |
1566 | .test(1'b1), | |
1567 | .sel0(sel0), | |
1568 | .sel1(sel1), | |
1569 | .psel0(psel0), | |
1570 | .psel1(psel1), | |
1571 | .psel2(psel2) | |
1572 | ); | |
1573 | ||
1574 | mux3s #(64) d1_0 ( | |
1575 | .sel0(psel0), | |
1576 | .sel1(psel1), | |
1577 | .sel2(psel2), | |
1578 | .in0(din0[63:0]), | |
1579 | .in1(din1[63:0]), | |
1580 | .in2(din2[63:0]), | |
1581 | .dout(muxout[63:0]) | |
1582 | ); | |
1583 | cl_dp1_l1hdr_8x c0_0 ( | |
1584 | .l2clk(clk), | |
1585 | .pce(en), | |
1586 | .aclk(siclk), | |
1587 | .bclk(soclk), | |
1588 | .l1clk(l1clk), | |
1589 | .se(se), | |
1590 | .pce_ov(pce_ov), | |
1591 | .stop(stop), | |
1592 | .siclk_out(siclk_out), | |
1593 | .soclk_out(soclk_out) | |
1594 | ); | |
1595 | dff #(64) d0_0 ( | |
1596 | .l1clk(l1clk), | |
1597 | .siclk(siclk_out), | |
1598 | .soclk(soclk_out), | |
1599 | .d(muxout[63:0]), | |
1600 | .si({scan_in,so[62:0]}), | |
1601 | .so({so[62:0],scan_out}), | |
1602 | .q(dout[63:0]) | |
1603 | ); | |
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | ||
1610 | ||
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 | ||
1623 | ||
1624 | endmodule | |
1625 | ||
1626 | ||
1627 | ||
1628 | ||
1629 | ||
1630 | ||
1631 | ||
1632 | ||
1633 | ||
1634 | ||
1635 | ||
1636 | ||
1637 | ||
1638 | // any PARAMS parms go into naming of macro | |
1639 | ||
1640 | module fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_64 ( | |
1641 | din0, | |
1642 | din1, | |
1643 | din2, | |
1644 | din3, | |
1645 | sel0, | |
1646 | sel1, | |
1647 | sel2, | |
1648 | clk, | |
1649 | en, | |
1650 | se, | |
1651 | scan_in, | |
1652 | siclk, | |
1653 | soclk, | |
1654 | pce_ov, | |
1655 | stop, | |
1656 | dout, | |
1657 | scan_out); | |
1658 | wire psel0; | |
1659 | wire psel1; | |
1660 | wire psel2; | |
1661 | wire psel3; | |
1662 | wire [63:0] muxout; | |
1663 | wire l1clk; | |
1664 | wire siclk_out; | |
1665 | wire soclk_out; | |
1666 | wire [62:0] so; | |
1667 | ||
1668 | input [63:0] din0; | |
1669 | input [63:0] din1; | |
1670 | input [63:0] din2; | |
1671 | input [63:0] din3; | |
1672 | input sel0; | |
1673 | input sel1; | |
1674 | input sel2; | |
1675 | ||
1676 | ||
1677 | input clk; | |
1678 | input en; | |
1679 | input se; | |
1680 | input scan_in; | |
1681 | input siclk; | |
1682 | input soclk; | |
1683 | input pce_ov; | |
1684 | input stop; | |
1685 | ||
1686 | ||
1687 | ||
1688 | output [63:0] dout; | |
1689 | ||
1690 | ||
1691 | output scan_out; | |
1692 | ||
1693 | ||
1694 | ||
1695 | ||
1696 | cl_dp1_penc4_8x c1_0 ( | |
1697 | .test(1'b1), | |
1698 | .sel0(sel0), | |
1699 | .sel1(sel1), | |
1700 | .sel2(sel2), | |
1701 | .psel0(psel0), | |
1702 | .psel1(psel1), | |
1703 | .psel2(psel2), | |
1704 | .psel3(psel3) | |
1705 | ); | |
1706 | ||
1707 | mux4s #(64) d1_0 ( | |
1708 | .sel0(psel0), | |
1709 | .sel1(psel1), | |
1710 | .sel2(psel2), | |
1711 | .sel3(psel3), | |
1712 | .in0(din0[63:0]), | |
1713 | .in1(din1[63:0]), | |
1714 | .in2(din2[63:0]), | |
1715 | .in3(din3[63:0]), | |
1716 | .dout(muxout[63:0]) | |
1717 | ); | |
1718 | cl_dp1_l1hdr_8x c0_0 ( | |
1719 | .l2clk(clk), | |
1720 | .pce(en), | |
1721 | .aclk(siclk), | |
1722 | .bclk(soclk), | |
1723 | .l1clk(l1clk), | |
1724 | .se(se), | |
1725 | .pce_ov(pce_ov), | |
1726 | .stop(stop), | |
1727 | .siclk_out(siclk_out), | |
1728 | .soclk_out(soclk_out) | |
1729 | ); | |
1730 | dff #(64) d0_0 ( | |
1731 | .l1clk(l1clk), | |
1732 | .siclk(siclk_out), | |
1733 | .soclk(soclk_out), | |
1734 | .d(muxout[63:0]), | |
1735 | .si({scan_in,so[62:0]}), | |
1736 | .so({so[62:0],scan_out}), | |
1737 | .q(dout[63:0]) | |
1738 | ); | |
1739 | ||
1740 | ||
1741 | ||
1742 | ||
1743 | ||
1744 | ||
1745 | ||
1746 | ||
1747 | ||
1748 | ||
1749 | ||
1750 | ||
1751 | ||
1752 | ||
1753 | ||
1754 | ||
1755 | ||
1756 | ||
1757 | ||
1758 | ||
1759 | endmodule | |
1760 | ||
1761 | ||
1762 | ||
1763 | ||
1764 | ||
1765 | ||
1766 | ||
1767 | ||
1768 | ||
1769 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1770 | // also for pass-gate with decoder | |
1771 | ||
1772 | ||
1773 | ||
1774 | ||
1775 | ||
1776 | // any PARAMS parms go into naming of macro | |
1777 | ||
1778 | module fgu_fdd_dp_mux_macro__mux_aodec__ports_8__stack_66c__width_64 ( | |
1779 | din0, | |
1780 | din1, | |
1781 | din2, | |
1782 | din3, | |
1783 | din4, | |
1784 | din5, | |
1785 | din6, | |
1786 | din7, | |
1787 | sel, | |
1788 | dout); | |
1789 | wire psel0; | |
1790 | wire psel1; | |
1791 | wire psel2; | |
1792 | wire psel3; | |
1793 | wire psel4; | |
1794 | wire psel5; | |
1795 | wire psel6; | |
1796 | wire psel7; | |
1797 | ||
1798 | input [63:0] din0; | |
1799 | input [63:0] din1; | |
1800 | input [63:0] din2; | |
1801 | input [63:0] din3; | |
1802 | input [63:0] din4; | |
1803 | input [63:0] din5; | |
1804 | input [63:0] din6; | |
1805 | input [63:0] din7; | |
1806 | input [2:0] sel; | |
1807 | output [63:0] dout; | |
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | cl_dp1_pdec8_8x c0_0 ( | |
1814 | .test(1'b1), | |
1815 | .sel0(sel[0]), | |
1816 | .sel1(sel[1]), | |
1817 | .sel2(sel[2]), | |
1818 | .psel0(psel0), | |
1819 | .psel1(psel1), | |
1820 | .psel2(psel2), | |
1821 | .psel3(psel3), | |
1822 | .psel4(psel4), | |
1823 | .psel5(psel5), | |
1824 | .psel6(psel6), | |
1825 | .psel7(psel7) | |
1826 | ); | |
1827 | ||
1828 | mux8s #(64) d0_0 ( | |
1829 | .sel0(psel0), | |
1830 | .sel1(psel1), | |
1831 | .sel2(psel2), | |
1832 | .sel3(psel3), | |
1833 | .sel4(psel4), | |
1834 | .sel5(psel5), | |
1835 | .sel6(psel6), | |
1836 | .sel7(psel7), | |
1837 | .in0(din0[63:0]), | |
1838 | .in1(din1[63:0]), | |
1839 | .in2(din2[63:0]), | |
1840 | .in3(din3[63:0]), | |
1841 | .in4(din4[63:0]), | |
1842 | .in5(din5[63:0]), | |
1843 | .in6(din6[63:0]), | |
1844 | .in7(din7[63:0]), | |
1845 | .dout(dout[63:0]) | |
1846 | ); | |
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | ||
1853 | ||
1854 | ||
1855 | ||
1856 | ||
1857 | ||
1858 | ||
1859 | ||
1860 | endmodule | |
1861 | ||
1862 | ||
1863 | // | |
1864 | // buff macro | |
1865 | // | |
1866 | // | |
1867 | ||
1868 | ||
1869 | ||
1870 | ||
1871 | ||
1872 | module fgu_fdd_dp_buff_macro__stack_66c__width_2 ( | |
1873 | din, | |
1874 | dout); | |
1875 | input [1:0] din; | |
1876 | output [1:0] dout; | |
1877 | ||
1878 | ||
1879 | ||
1880 | ||
1881 | ||
1882 | ||
1883 | buff #(2) d0_0 ( | |
1884 | .in(din[1:0]), | |
1885 | .out(dout[1:0]) | |
1886 | ); | |
1887 | ||
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | ||
1894 | ||
1895 | endmodule | |
1896 | ||
1897 | ||
1898 | ||
1899 | ||
1900 | ||
1901 | // | |
1902 | // xor macro for ports = 2,3 | |
1903 | // | |
1904 | // | |
1905 | ||
1906 | ||
1907 | ||
1908 | ||
1909 | ||
1910 | module fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_64 ( | |
1911 | din0, | |
1912 | din1, | |
1913 | dout); | |
1914 | input [63:0] din0; | |
1915 | input [63:0] din1; | |
1916 | output [63:0] dout; | |
1917 | ||
1918 | ||
1919 | ||
1920 | ||
1921 | ||
1922 | xor2 #(64) d0_0 ( | |
1923 | .in0(din0[63:0]), | |
1924 | .in1(din1[63:0]), | |
1925 | .out(dout[63:0]) | |
1926 | ); | |
1927 | ||
1928 | ||
1929 | ||
1930 | ||
1931 | ||
1932 | ||
1933 | ||
1934 | ||
1935 | endmodule | |
1936 | ||
1937 | ||
1938 | ||
1939 | ||
1940 | ||
1941 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1942 | // also for pass-gate with decoder | |
1943 | ||
1944 | ||
1945 | ||
1946 | ||
1947 | ||
1948 | // any PARAMS parms go into naming of macro | |
1949 | ||
1950 | module fgu_fdd_dp_mux_macro__mux_aonpe__ports_5__stack_66c__width_66 ( | |
1951 | din0, | |
1952 | sel0, | |
1953 | din1, | |
1954 | sel1, | |
1955 | din2, | |
1956 | sel2, | |
1957 | din3, | |
1958 | sel3, | |
1959 | din4, | |
1960 | sel4, | |
1961 | dout); | |
1962 | wire buffout0; | |
1963 | wire buffout1; | |
1964 | wire buffout2; | |
1965 | wire buffout3; | |
1966 | wire buffout4; | |
1967 | ||
1968 | input [65:0] din0; | |
1969 | input sel0; | |
1970 | input [65:0] din1; | |
1971 | input sel1; | |
1972 | input [65:0] din2; | |
1973 | input sel2; | |
1974 | input [65:0] din3; | |
1975 | input sel3; | |
1976 | input [65:0] din4; | |
1977 | input sel4; | |
1978 | output [65:0] dout; | |
1979 | ||
1980 | ||
1981 | ||
1982 | ||
1983 | ||
1984 | cl_dp1_muxbuff5_8x c0_0 ( | |
1985 | .in0(sel0), | |
1986 | .in1(sel1), | |
1987 | .in2(sel2), | |
1988 | .in3(sel3), | |
1989 | .in4(sel4), | |
1990 | .out0(buffout0), | |
1991 | .out1(buffout1), | |
1992 | .out2(buffout2), | |
1993 | .out3(buffout3), | |
1994 | .out4(buffout4) | |
1995 | ); | |
1996 | mux5s #(66) d0_0 ( | |
1997 | .sel0(buffout0), | |
1998 | .sel1(buffout1), | |
1999 | .sel2(buffout2), | |
2000 | .sel3(buffout3), | |
2001 | .sel4(buffout4), | |
2002 | .in0(din0[65:0]), | |
2003 | .in1(din1[65:0]), | |
2004 | .in2(din2[65:0]), | |
2005 | .in3(din3[65:0]), | |
2006 | .in4(din4[65:0]), | |
2007 | .dout(dout[65:0]) | |
2008 | ); | |
2009 | ||
2010 | ||
2011 | ||
2012 | ||
2013 | ||
2014 | ||
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | ||
2021 | ||
2022 | endmodule | |
2023 | ||
2024 | ||
2025 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2026 | // also for pass-gate with decoder | |
2027 | ||
2028 | ||
2029 | ||
2030 | ||
2031 | ||
2032 | // any PARAMS parms go into naming of macro | |
2033 | ||
2034 | module fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_66 ( | |
2035 | din0, | |
2036 | sel0, | |
2037 | din1, | |
2038 | sel1, | |
2039 | din2, | |
2040 | sel2, | |
2041 | dout); | |
2042 | wire buffout0; | |
2043 | wire buffout1; | |
2044 | wire buffout2; | |
2045 | ||
2046 | input [65:0] din0; | |
2047 | input sel0; | |
2048 | input [65:0] din1; | |
2049 | input sel1; | |
2050 | input [65:0] din2; | |
2051 | input sel2; | |
2052 | output [65:0] dout; | |
2053 | ||
2054 | ||
2055 | ||
2056 | ||
2057 | ||
2058 | cl_dp1_muxbuff3_8x c0_0 ( | |
2059 | .in0(sel0), | |
2060 | .in1(sel1), | |
2061 | .in2(sel2), | |
2062 | .out0(buffout0), | |
2063 | .out1(buffout1), | |
2064 | .out2(buffout2) | |
2065 | ); | |
2066 | mux3s #(66) d0_0 ( | |
2067 | .sel0(buffout0), | |
2068 | .sel1(buffout1), | |
2069 | .sel2(buffout2), | |
2070 | .in0(din0[65:0]), | |
2071 | .in1(din1[65:0]), | |
2072 | .in2(din2[65:0]), | |
2073 | .dout(dout[65:0]) | |
2074 | ); | |
2075 | ||
2076 | ||
2077 | ||
2078 | ||
2079 | ||
2080 | ||
2081 | ||
2082 | ||
2083 | ||
2084 | ||
2085 | ||
2086 | ||
2087 | ||
2088 | endmodule | |
2089 | ||
2090 | ||
2091 | // | |
2092 | // or macro for ports = 2,3 | |
2093 | // | |
2094 | // | |
2095 | ||
2096 | ||
2097 | ||
2098 | ||
2099 | ||
2100 | module fgu_fdd_dp_or_macro__ports_2__width_1 ( | |
2101 | din0, | |
2102 | din1, | |
2103 | dout); | |
2104 | input [0:0] din0; | |
2105 | input [0:0] din1; | |
2106 | output [0:0] dout; | |
2107 | ||
2108 | ||
2109 | ||
2110 | ||
2111 | ||
2112 | ||
2113 | or2 #(1) d0_0 ( | |
2114 | .in0(din0[0:0]), | |
2115 | .in1(din1[0:0]), | |
2116 | .out(dout[0:0]) | |
2117 | ); | |
2118 | ||
2119 | ||
2120 | ||
2121 | ||
2122 | ||
2123 | ||
2124 | ||
2125 | ||
2126 | ||
2127 | endmodule | |
2128 | ||
2129 | ||
2130 | ||
2131 | ||
2132 | ||
2133 | // | |
2134 | // nor macro for ports = 2,3 | |
2135 | // | |
2136 | // | |
2137 | ||
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | module fgu_fdd_dp_nor_macro__ports_2__width_1 ( | |
2143 | din0, | |
2144 | din1, | |
2145 | dout); | |
2146 | input [0:0] din0; | |
2147 | input [0:0] din1; | |
2148 | output [0:0] dout; | |
2149 | ||
2150 | ||
2151 | ||
2152 | ||
2153 | ||
2154 | ||
2155 | nor2 #(1) d0_0 ( | |
2156 | .in0(din0[0:0]), | |
2157 | .in1(din1[0:0]), | |
2158 | .out(dout[0:0]) | |
2159 | ); | |
2160 | ||
2161 | ||
2162 | ||
2163 | ||
2164 | ||
2165 | ||
2166 | ||
2167 | endmodule | |
2168 | ||
2169 | ||
2170 | ||
2171 | ||
2172 | ||
2173 | ||
2174 | ||
2175 | ||
2176 | ||
2177 | // any PARAMS parms go into naming of macro | |
2178 | ||
2179 | module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_66 ( | |
2180 | din0, | |
2181 | sel0, | |
2182 | din1, | |
2183 | sel1, | |
2184 | din2, | |
2185 | sel2, | |
2186 | din3, | |
2187 | sel3, | |
2188 | clk, | |
2189 | en, | |
2190 | se, | |
2191 | scan_in, | |
2192 | siclk, | |
2193 | soclk, | |
2194 | pce_ov, | |
2195 | stop, | |
2196 | dout, | |
2197 | scan_out); | |
2198 | wire buffout0; | |
2199 | wire buffout1; | |
2200 | wire buffout2; | |
2201 | wire buffout3; | |
2202 | wire [65:0] muxout; | |
2203 | wire l1clk; | |
2204 | wire siclk_out; | |
2205 | wire soclk_out; | |
2206 | wire [64:0] so; | |
2207 | ||
2208 | input [65:0] din0; | |
2209 | input sel0; | |
2210 | input [65:0] din1; | |
2211 | input sel1; | |
2212 | input [65:0] din2; | |
2213 | input sel2; | |
2214 | input [65:0] din3; | |
2215 | input sel3; | |
2216 | ||
2217 | ||
2218 | input clk; | |
2219 | input en; | |
2220 | input se; | |
2221 | input scan_in; | |
2222 | input siclk; | |
2223 | input soclk; | |
2224 | input pce_ov; | |
2225 | input stop; | |
2226 | ||
2227 | ||
2228 | ||
2229 | output [65:0] dout; | |
2230 | ||
2231 | ||
2232 | output scan_out; | |
2233 | ||
2234 | ||
2235 | ||
2236 | ||
2237 | cl_dp1_muxbuff4_8x c1_0 ( | |
2238 | .in0(sel0), | |
2239 | .in1(sel1), | |
2240 | .in2(sel2), | |
2241 | .in3(sel3), | |
2242 | .out0(buffout0), | |
2243 | .out1(buffout1), | |
2244 | .out2(buffout2), | |
2245 | .out3(buffout3) | |
2246 | ); | |
2247 | mux4s #(66) d1_0 ( | |
2248 | .sel0(buffout0), | |
2249 | .sel1(buffout1), | |
2250 | .sel2(buffout2), | |
2251 | .sel3(buffout3), | |
2252 | .in0(din0[65:0]), | |
2253 | .in1(din1[65:0]), | |
2254 | .in2(din2[65:0]), | |
2255 | .in3(din3[65:0]), | |
2256 | .dout(muxout[65:0]) | |
2257 | ); | |
2258 | cl_dp1_l1hdr_8x c0_0 ( | |
2259 | .l2clk(clk), | |
2260 | .pce(en), | |
2261 | .aclk(siclk), | |
2262 | .bclk(soclk), | |
2263 | .l1clk(l1clk), | |
2264 | .se(se), | |
2265 | .pce_ov(pce_ov), | |
2266 | .stop(stop), | |
2267 | .siclk_out(siclk_out), | |
2268 | .soclk_out(soclk_out) | |
2269 | ); | |
2270 | dff #(66) d0_0 ( | |
2271 | .l1clk(l1clk), | |
2272 | .siclk(siclk_out), | |
2273 | .soclk(soclk_out), | |
2274 | .d(muxout[65:0]), | |
2275 | .si({scan_in,so[64:0]}), | |
2276 | .so({so[64:0],scan_out}), | |
2277 | .q(dout[65:0]) | |
2278 | ); | |
2279 | ||
2280 | ||
2281 | ||
2282 | ||
2283 | ||
2284 | ||
2285 | ||
2286 | ||
2287 | ||
2288 | ||
2289 | ||
2290 | ||
2291 | ||
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | endmodule | |
2300 | ||
2301 | ||
2302 | ||
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | ||
2308 | ||
2309 | ||
2310 | ||
2311 | ||
2312 | ||
2313 | // any PARAMS parms go into naming of macro | |
2314 | ||
2315 | module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_64 ( | |
2316 | din0, | |
2317 | sel0, | |
2318 | din1, | |
2319 | sel1, | |
2320 | din2, | |
2321 | sel2, | |
2322 | din3, | |
2323 | sel3, | |
2324 | clk, | |
2325 | en, | |
2326 | se, | |
2327 | scan_in, | |
2328 | siclk, | |
2329 | soclk, | |
2330 | pce_ov, | |
2331 | stop, | |
2332 | dout, | |
2333 | scan_out); | |
2334 | wire buffout0; | |
2335 | wire buffout1; | |
2336 | wire buffout2; | |
2337 | wire buffout3; | |
2338 | wire [63:0] muxout; | |
2339 | wire l1clk; | |
2340 | wire siclk_out; | |
2341 | wire soclk_out; | |
2342 | wire [62:0] so; | |
2343 | ||
2344 | input [63:0] din0; | |
2345 | input sel0; | |
2346 | input [63:0] din1; | |
2347 | input sel1; | |
2348 | input [63:0] din2; | |
2349 | input sel2; | |
2350 | input [63:0] din3; | |
2351 | input sel3; | |
2352 | ||
2353 | ||
2354 | input clk; | |
2355 | input en; | |
2356 | input se; | |
2357 | input scan_in; | |
2358 | input siclk; | |
2359 | input soclk; | |
2360 | input pce_ov; | |
2361 | input stop; | |
2362 | ||
2363 | ||
2364 | ||
2365 | output [63:0] dout; | |
2366 | ||
2367 | ||
2368 | output scan_out; | |
2369 | ||
2370 | ||
2371 | ||
2372 | ||
2373 | cl_dp1_muxbuff4_8x c1_0 ( | |
2374 | .in0(sel0), | |
2375 | .in1(sel1), | |
2376 | .in2(sel2), | |
2377 | .in3(sel3), | |
2378 | .out0(buffout0), | |
2379 | .out1(buffout1), | |
2380 | .out2(buffout2), | |
2381 | .out3(buffout3) | |
2382 | ); | |
2383 | mux4s #(64) d1_0 ( | |
2384 | .sel0(buffout0), | |
2385 | .sel1(buffout1), | |
2386 | .sel2(buffout2), | |
2387 | .sel3(buffout3), | |
2388 | .in0(din0[63:0]), | |
2389 | .in1(din1[63:0]), | |
2390 | .in2(din2[63:0]), | |
2391 | .in3(din3[63:0]), | |
2392 | .dout(muxout[63:0]) | |
2393 | ); | |
2394 | cl_dp1_l1hdr_8x c0_0 ( | |
2395 | .l2clk(clk), | |
2396 | .pce(en), | |
2397 | .aclk(siclk), | |
2398 | .bclk(soclk), | |
2399 | .l1clk(l1clk), | |
2400 | .se(se), | |
2401 | .pce_ov(pce_ov), | |
2402 | .stop(stop), | |
2403 | .siclk_out(siclk_out), | |
2404 | .soclk_out(soclk_out) | |
2405 | ); | |
2406 | dff #(64) d0_0 ( | |
2407 | .l1clk(l1clk), | |
2408 | .siclk(siclk_out), | |
2409 | .soclk(soclk_out), | |
2410 | .d(muxout[63:0]), | |
2411 | .si({scan_in,so[62:0]}), | |
2412 | .so({so[62:0],scan_out}), | |
2413 | .q(dout[63:0]) | |
2414 | ); | |
2415 | ||
2416 | ||
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | ||
2422 | ||
2423 | ||
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | ||
2429 | ||
2430 | ||
2431 | ||
2432 | ||
2433 | ||
2434 | ||
2435 | endmodule | |
2436 | ||
2437 | ||
2438 | ||
2439 | ||
2440 | ||
2441 | ||
2442 | ||
2443 | ||
2444 | ||
2445 | // | |
2446 | // or macro for ports = 2,3 | |
2447 | // | |
2448 | // | |
2449 | ||
2450 | ||
2451 | ||
2452 | ||
2453 | ||
2454 | module fgu_fdd_dp_or_macro__ports_2__stack_66c__width_66 ( | |
2455 | din0, | |
2456 | din1, | |
2457 | dout); | |
2458 | input [65:0] din0; | |
2459 | input [65:0] din1; | |
2460 | output [65:0] dout; | |
2461 | ||
2462 | ||
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | or2 #(66) d0_0 ( | |
2468 | .in0(din0[65:0]), | |
2469 | .in1(din1[65:0]), | |
2470 | .out(dout[65:0]) | |
2471 | ); | |
2472 | ||
2473 | ||
2474 | ||
2475 | ||
2476 | ||
2477 | ||
2478 | ||
2479 | ||
2480 | ||
2481 | endmodule | |
2482 | ||
2483 | ||
2484 | ||
2485 | ||
2486 | ||
2487 | // | |
2488 | // xor macro for ports = 2,3 | |
2489 | // | |
2490 | // | |
2491 | ||
2492 | ||
2493 | ||
2494 | ||
2495 | ||
2496 | module fgu_fdd_dp_xor_macro__ports_2__stack_66c__width_66 ( | |
2497 | din0, | |
2498 | din1, | |
2499 | dout); | |
2500 | input [65:0] din0; | |
2501 | input [65:0] din1; | |
2502 | output [65:0] dout; | |
2503 | ||
2504 | ||
2505 | ||
2506 | ||
2507 | ||
2508 | xor2 #(66) d0_0 ( | |
2509 | .in0(din0[65:0]), | |
2510 | .in1(din1[65:0]), | |
2511 | .out(dout[65:0]) | |
2512 | ); | |
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | ||
2518 | ||
2519 | ||
2520 | ||
2521 | endmodule | |
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | ||
2527 | // | |
2528 | // nor macro for ports = 2,3 | |
2529 | // | |
2530 | // | |
2531 | ||
2532 | ||
2533 | ||
2534 | ||
2535 | ||
2536 | module fgu_fdd_dp_nor_macro__ports_2__stack_66c__width_65 ( | |
2537 | din0, | |
2538 | din1, | |
2539 | dout); | |
2540 | input [64:0] din0; | |
2541 | input [64:0] din1; | |
2542 | output [64:0] dout; | |
2543 | ||
2544 | ||
2545 | ||
2546 | ||
2547 | ||
2548 | ||
2549 | nor2 #(65) d0_0 ( | |
2550 | .in0(din0[64:0]), | |
2551 | .in1(din1[64:0]), | |
2552 | .out(dout[64:0]) | |
2553 | ); | |
2554 | ||
2555 | ||
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | endmodule | |
2562 | ||
2563 | ||
2564 | ||
2565 | ||
2566 | ||
2567 | ||
2568 | ||
2569 | ||
2570 | ||
2571 | // any PARAMS parms go into naming of macro | |
2572 | ||
2573 | module fgu_fdd_dp_msff_macro__mux_aonpe__ports_4__stack_66c__width_65 ( | |
2574 | din0, | |
2575 | sel0, | |
2576 | din1, | |
2577 | sel1, | |
2578 | din2, | |
2579 | sel2, | |
2580 | din3, | |
2581 | sel3, | |
2582 | clk, | |
2583 | en, | |
2584 | se, | |
2585 | scan_in, | |
2586 | siclk, | |
2587 | soclk, | |
2588 | pce_ov, | |
2589 | stop, | |
2590 | dout, | |
2591 | scan_out); | |
2592 | wire buffout0; | |
2593 | wire buffout1; | |
2594 | wire buffout2; | |
2595 | wire buffout3; | |
2596 | wire [64:0] muxout; | |
2597 | wire l1clk; | |
2598 | wire siclk_out; | |
2599 | wire soclk_out; | |
2600 | wire [63:0] so; | |
2601 | ||
2602 | input [64:0] din0; | |
2603 | input sel0; | |
2604 | input [64:0] din1; | |
2605 | input sel1; | |
2606 | input [64:0] din2; | |
2607 | input sel2; | |
2608 | input [64:0] din3; | |
2609 | input sel3; | |
2610 | ||
2611 | ||
2612 | input clk; | |
2613 | input en; | |
2614 | input se; | |
2615 | input scan_in; | |
2616 | input siclk; | |
2617 | input soclk; | |
2618 | input pce_ov; | |
2619 | input stop; | |
2620 | ||
2621 | ||
2622 | ||
2623 | output [64:0] dout; | |
2624 | ||
2625 | ||
2626 | output scan_out; | |
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | cl_dp1_muxbuff4_8x c1_0 ( | |
2632 | .in0(sel0), | |
2633 | .in1(sel1), | |
2634 | .in2(sel2), | |
2635 | .in3(sel3), | |
2636 | .out0(buffout0), | |
2637 | .out1(buffout1), | |
2638 | .out2(buffout2), | |
2639 | .out3(buffout3) | |
2640 | ); | |
2641 | mux4s #(65) d1_0 ( | |
2642 | .sel0(buffout0), | |
2643 | .sel1(buffout1), | |
2644 | .sel2(buffout2), | |
2645 | .sel3(buffout3), | |
2646 | .in0(din0[64:0]), | |
2647 | .in1(din1[64:0]), | |
2648 | .in2(din2[64:0]), | |
2649 | .in3(din3[64:0]), | |
2650 | .dout(muxout[64:0]) | |
2651 | ); | |
2652 | cl_dp1_l1hdr_8x c0_0 ( | |
2653 | .l2clk(clk), | |
2654 | .pce(en), | |
2655 | .aclk(siclk), | |
2656 | .bclk(soclk), | |
2657 | .l1clk(l1clk), | |
2658 | .se(se), | |
2659 | .pce_ov(pce_ov), | |
2660 | .stop(stop), | |
2661 | .siclk_out(siclk_out), | |
2662 | .soclk_out(soclk_out) | |
2663 | ); | |
2664 | dff #(65) d0_0 ( | |
2665 | .l1clk(l1clk), | |
2666 | .siclk(siclk_out), | |
2667 | .soclk(soclk_out), | |
2668 | .d(muxout[64:0]), | |
2669 | .si({scan_in,so[63:0]}), | |
2670 | .so({so[63:0],scan_out}), | |
2671 | .q(dout[64:0]) | |
2672 | ); | |
2673 | ||
2674 | ||
2675 | ||
2676 | ||
2677 | ||
2678 | ||
2679 | ||
2680 | ||
2681 | ||
2682 | ||
2683 | ||
2684 | ||
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | ||
2690 | ||
2691 | ||
2692 | ||
2693 | endmodule | |
2694 | ||
2695 | ||
2696 | ||
2697 | ||
2698 | ||
2699 | ||
2700 | ||
2701 | ||
2702 | ||
2703 | // | |
2704 | // or macro for ports = 2,3 | |
2705 | // | |
2706 | // | |
2707 | ||
2708 | ||
2709 | ||
2710 | ||
2711 | ||
2712 | module fgu_fdd_dp_or_macro__ports_2__stack_66c__width_65 ( | |
2713 | din0, | |
2714 | din1, | |
2715 | dout); | |
2716 | input [64:0] din0; | |
2717 | input [64:0] din1; | |
2718 | output [64:0] dout; | |
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | ||
2724 | ||
2725 | or2 #(65) d0_0 ( | |
2726 | .in0(din0[64:0]), | |
2727 | .in1(din1[64:0]), | |
2728 | .out(dout[64:0]) | |
2729 | ); | |
2730 | ||
2731 | ||
2732 | ||
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | ||
2738 | ||
2739 | endmodule | |
2740 | ||
2741 | ||
2742 | ||
2743 | ||
2744 | ||
2745 | // | |
2746 | // 3:2 Carry Save Adder | |
2747 | // | |
2748 | // | |
2749 | ||
2750 | ||
2751 | ||
2752 | ||
2753 | // any PARAMS parms go into naming of macro | |
2754 | ||
2755 | ||
2756 | module fgu_fdd_dp_csa32_macro__stack_66c__width_65 ( | |
2757 | i0, | |
2758 | i1, | |
2759 | i2, | |
2760 | carry, | |
2761 | sum); | |
2762 | input [64:0] i0; | |
2763 | input [64:0] i1; | |
2764 | input [64:0] i2; | |
2765 | output [64:0] carry; | |
2766 | output [64:0] sum; | |
2767 | ||
2768 | ||
2769 | ||
2770 | ||
2771 | ||
2772 | ||
2773 | csa32 #(65) d0_0 ( | |
2774 | .in0(i0[64:0]), | |
2775 | .in1(i1[64:0]), | |
2776 | .in2(i2[64:0]), | |
2777 | .carry(carry[64:0]), | |
2778 | .sum(sum[64:0]) | |
2779 | ); | |
2780 | ||
2781 | ||
2782 | ||
2783 | ||
2784 | ||
2785 | ||
2786 | ||
2787 | ||
2788 | ||
2789 | endmodule | |
2790 | ||
2791 | ||
2792 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2793 | // also for pass-gate with decoder | |
2794 | ||
2795 | ||
2796 | ||
2797 | ||
2798 | ||
2799 | // any PARAMS parms go into naming of macro | |
2800 | ||
2801 | module fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_65 ( | |
2802 | din0, | |
2803 | sel0, | |
2804 | din1, | |
2805 | sel1, | |
2806 | din2, | |
2807 | sel2, | |
2808 | dout); | |
2809 | wire buffout0; | |
2810 | wire buffout1; | |
2811 | wire buffout2; | |
2812 | ||
2813 | input [64:0] din0; | |
2814 | input sel0; | |
2815 | input [64:0] din1; | |
2816 | input sel1; | |
2817 | input [64:0] din2; | |
2818 | input sel2; | |
2819 | output [64:0] dout; | |
2820 | ||
2821 | ||
2822 | ||
2823 | ||
2824 | ||
2825 | cl_dp1_muxbuff3_8x c0_0 ( | |
2826 | .in0(sel0), | |
2827 | .in1(sel1), | |
2828 | .in2(sel2), | |
2829 | .out0(buffout0), | |
2830 | .out1(buffout1), | |
2831 | .out2(buffout2) | |
2832 | ); | |
2833 | mux3s #(65) d0_0 ( | |
2834 | .sel0(buffout0), | |
2835 | .sel1(buffout1), | |
2836 | .sel2(buffout2), | |
2837 | .in0(din0[64:0]), | |
2838 | .in1(din1[64:0]), | |
2839 | .in2(din2[64:0]), | |
2840 | .dout(dout[64:0]) | |
2841 | ); | |
2842 | ||
2843 | ||
2844 | ||
2845 | ||
2846 | ||
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | ||
2853 | ||
2854 | ||
2855 | endmodule | |
2856 | ||
2857 | ||
2858 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2859 | // also for pass-gate with decoder | |
2860 | ||
2861 | ||
2862 | ||
2863 | ||
2864 | ||
2865 | // any PARAMS parms go into naming of macro | |
2866 | ||
2867 | module fgu_fdd_dp_mux_macro__dmux_6x__mux_aonpe__ports_3__stack_66c__width_64 ( | |
2868 | din0, | |
2869 | sel0, | |
2870 | din1, | |
2871 | sel1, | |
2872 | din2, | |
2873 | sel2, | |
2874 | dout); | |
2875 | wire buffout0; | |
2876 | wire buffout1; | |
2877 | wire buffout2; | |
2878 | ||
2879 | input [63:0] din0; | |
2880 | input sel0; | |
2881 | input [63:0] din1; | |
2882 | input sel1; | |
2883 | input [63:0] din2; | |
2884 | input sel2; | |
2885 | output [63:0] dout; | |
2886 | ||
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | cl_dp1_muxbuff3_8x c0_0 ( | |
2892 | .in0(sel0), | |
2893 | .in1(sel1), | |
2894 | .in2(sel2), | |
2895 | .out0(buffout0), | |
2896 | .out1(buffout1), | |
2897 | .out2(buffout2) | |
2898 | ); | |
2899 | mux3s #(64) d0_0 ( | |
2900 | .sel0(buffout0), | |
2901 | .sel1(buffout1), | |
2902 | .sel2(buffout2), | |
2903 | .in0(din0[63:0]), | |
2904 | .in1(din1[63:0]), | |
2905 | .in2(din2[63:0]), | |
2906 | .dout(dout[63:0]) | |
2907 | ); | |
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 | ||
2916 | ||
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | endmodule | |
2922 | ||
2923 | ||
2924 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2925 | // also for pass-gate with decoder | |
2926 | ||
2927 | ||
2928 | ||
2929 | ||
2930 | ||
2931 | // any PARAMS parms go into naming of macro | |
2932 | ||
2933 | module fgu_fdd_dp_mux_macro__mux_aonpe__ports_3__stack_66c__width_65 ( | |
2934 | din0, | |
2935 | sel0, | |
2936 | din1, | |
2937 | sel1, | |
2938 | din2, | |
2939 | sel2, | |
2940 | dout); | |
2941 | wire buffout0; | |
2942 | wire buffout1; | |
2943 | wire buffout2; | |
2944 | ||
2945 | input [64:0] din0; | |
2946 | input sel0; | |
2947 | input [64:0] din1; | |
2948 | input sel1; | |
2949 | input [64:0] din2; | |
2950 | input sel2; | |
2951 | output [64:0] dout; | |
2952 | ||
2953 | ||
2954 | ||
2955 | ||
2956 | ||
2957 | cl_dp1_muxbuff3_8x c0_0 ( | |
2958 | .in0(sel0), | |
2959 | .in1(sel1), | |
2960 | .in2(sel2), | |
2961 | .out0(buffout0), | |
2962 | .out1(buffout1), | |
2963 | .out2(buffout2) | |
2964 | ); | |
2965 | mux3s #(65) d0_0 ( | |
2966 | .sel0(buffout0), | |
2967 | .sel1(buffout1), | |
2968 | .sel2(buffout2), | |
2969 | .in0(din0[64:0]), | |
2970 | .in1(din1[64:0]), | |
2971 | .in2(din2[64:0]), | |
2972 | .dout(dout[64:0]) | |
2973 | ); | |
2974 | ||
2975 | ||
2976 | ||
2977 | ||
2978 | ||
2979 | ||
2980 | ||
2981 | ||
2982 | ||
2983 | ||
2984 | ||
2985 | ||
2986 | ||
2987 | endmodule | |
2988 | ||
2989 | ||
2990 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2991 | // also for pass-gate with decoder | |
2992 | ||
2993 | ||
2994 | ||
2995 | ||
2996 | ||
2997 | // any PARAMS parms go into naming of macro | |
2998 | ||
2999 | module fgu_fdd_dp_mux_macro__mux_aope__ports_2__stack_66c__width_64 ( | |
3000 | din0, | |
3001 | din1, | |
3002 | sel0, | |
3003 | dout); | |
3004 | wire psel0; | |
3005 | wire psel1; | |
3006 | ||
3007 | input [63:0] din0; | |
3008 | input [63:0] din1; | |
3009 | input sel0; | |
3010 | output [63:0] dout; | |
3011 | ||
3012 | ||
3013 | ||
3014 | ||
3015 | ||
3016 | cl_dp1_penc2_8x c0_0 ( | |
3017 | .sel0(sel0), | |
3018 | .psel0(psel0), | |
3019 | .psel1(psel1) | |
3020 | ); | |
3021 | ||
3022 | mux2s #(64) d0_0 ( | |
3023 | .sel0(psel0), | |
3024 | .sel1(psel1), | |
3025 | .in0(din0[63:0]), | |
3026 | .in1(din1[63:0]), | |
3027 | .dout(dout[63:0]) | |
3028 | ); | |
3029 | ||
3030 | ||
3031 | ||
3032 | ||
3033 | ||
3034 | ||
3035 | ||
3036 | ||
3037 | ||
3038 | ||
3039 | ||
3040 | ||
3041 | ||
3042 | endmodule | |
3043 | ||
3044 | ||
3045 | ||
3046 | ||
3047 | ||
3048 | ||
3049 | // any PARAMS parms go into naming of macro | |
3050 | ||
3051 | module fgu_fdd_dp_msff_macro__stack_66c__width_66 ( | |
3052 | din, | |
3053 | clk, | |
3054 | en, | |
3055 | se, | |
3056 | scan_in, | |
3057 | siclk, | |
3058 | soclk, | |
3059 | pce_ov, | |
3060 | stop, | |
3061 | dout, | |
3062 | scan_out); | |
3063 | wire l1clk; | |
3064 | wire siclk_out; | |
3065 | wire soclk_out; | |
3066 | wire [64:0] so; | |
3067 | ||
3068 | input [65:0] din; | |
3069 | ||
3070 | ||
3071 | input clk; | |
3072 | input en; | |
3073 | input se; | |
3074 | input scan_in; | |
3075 | input siclk; | |
3076 | input soclk; | |
3077 | input pce_ov; | |
3078 | input stop; | |
3079 | ||
3080 | ||
3081 | ||
3082 | output [65:0] dout; | |
3083 | ||
3084 | ||
3085 | output scan_out; | |
3086 | ||
3087 | ||
3088 | ||
3089 | ||
3090 | cl_dp1_l1hdr_8x c0_0 ( | |
3091 | .l2clk(clk), | |
3092 | .pce(en), | |
3093 | .aclk(siclk), | |
3094 | .bclk(soclk), | |
3095 | .l1clk(l1clk), | |
3096 | .se(se), | |
3097 | .pce_ov(pce_ov), | |
3098 | .stop(stop), | |
3099 | .siclk_out(siclk_out), | |
3100 | .soclk_out(soclk_out) | |
3101 | ); | |
3102 | dff #(66) d0_0 ( | |
3103 | .l1clk(l1clk), | |
3104 | .siclk(siclk_out), | |
3105 | .soclk(soclk_out), | |
3106 | .d(din[65:0]), | |
3107 | .si({scan_in,so[64:0]}), | |
3108 | .so({so[64:0],scan_out}), | |
3109 | .q(dout[65:0]) | |
3110 | ); | |
3111 | ||
3112 | ||
3113 | ||
3114 | ||
3115 | ||
3116 | ||
3117 | ||
3118 | ||
3119 | ||
3120 | ||
3121 | ||
3122 | ||
3123 | ||
3124 | ||
3125 | ||
3126 | ||
3127 | ||
3128 | ||
3129 | ||
3130 | ||
3131 | endmodule | |
3132 | ||
3133 | ||
3134 | ||
3135 | ||
3136 | ||
3137 | ||
3138 | ||
3139 | ||
3140 | ||
3141 | // | |
3142 | // invert macro | |
3143 | // | |
3144 | // | |
3145 | ||
3146 | ||
3147 | ||
3148 | ||
3149 | ||
3150 | module fgu_fdd_dp_inv_macro__stack_66c__width_65 ( | |
3151 | din, | |
3152 | dout); | |
3153 | input [64:0] din; | |
3154 | output [64:0] dout; | |
3155 | ||
3156 | ||
3157 | ||
3158 | ||
3159 | ||
3160 | ||
3161 | inv #(65) d0_0 ( | |
3162 | .in(din[64:0]), | |
3163 | .out(dout[64:0]) | |
3164 | ); | |
3165 | ||
3166 | ||
3167 | ||
3168 | ||
3169 | ||
3170 | ||
3171 | ||
3172 | ||
3173 | ||
3174 | endmodule | |
3175 | ||
3176 | ||
3177 | ||
3178 | ||
3179 | ||
3180 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3181 | // also for pass-gate with decoder | |
3182 | ||
3183 | ||
3184 | ||
3185 | ||
3186 | ||
3187 | // any PARAMS parms go into naming of macro | |
3188 | ||
3189 | module fgu_fdd_dp_mux_macro__mux_aope__ports_4__stack_66c__width_64 ( | |
3190 | din0, | |
3191 | din1, | |
3192 | din2, | |
3193 | din3, | |
3194 | sel0, | |
3195 | sel1, | |
3196 | sel2, | |
3197 | dout); | |
3198 | wire psel0; | |
3199 | wire psel1; | |
3200 | wire psel2; | |
3201 | wire psel3; | |
3202 | ||
3203 | input [63:0] din0; | |
3204 | input [63:0] din1; | |
3205 | input [63:0] din2; | |
3206 | input [63:0] din3; | |
3207 | input sel0; | |
3208 | input sel1; | |
3209 | input sel2; | |
3210 | output [63:0] dout; | |
3211 | ||
3212 | ||
3213 | ||
3214 | ||
3215 | ||
3216 | cl_dp1_penc4_8x c0_0 ( | |
3217 | .test(1'b1), | |
3218 | .sel0(sel0), | |
3219 | .sel1(sel1), | |
3220 | .sel2(sel2), | |
3221 | .psel0(psel0), | |
3222 | .psel1(psel1), | |
3223 | .psel2(psel2), | |
3224 | .psel3(psel3) | |
3225 | ); | |
3226 | ||
3227 | mux4s #(64) d0_0 ( | |
3228 | .sel0(psel0), | |
3229 | .sel1(psel1), | |
3230 | .sel2(psel2), | |
3231 | .sel3(psel3), | |
3232 | .in0(din0[63:0]), | |
3233 | .in1(din1[63:0]), | |
3234 | .in2(din2[63:0]), | |
3235 | .in3(din3[63:0]), | |
3236 | .dout(dout[63:0]) | |
3237 | ); | |
3238 | ||
3239 | ||
3240 | ||
3241 | ||
3242 | ||
3243 | ||
3244 | ||
3245 | ||
3246 | ||
3247 | ||
3248 | ||
3249 | ||
3250 | ||
3251 | endmodule | |
3252 | ||
3253 | ||
3254 | // | |
3255 | // 3:2 Carry Save Adder | |
3256 | // | |
3257 | // | |
3258 | ||
3259 | ||
3260 | ||
3261 | ||
3262 | // any PARAMS parms go into naming of macro | |
3263 | ||
3264 | ||
3265 | module fgu_fdd_dp_csa32_macro__stack_66c__width_64 ( | |
3266 | i0, | |
3267 | i1, | |
3268 | i2, | |
3269 | carry, | |
3270 | sum); | |
3271 | input [63:0] i0; | |
3272 | input [63:0] i1; | |
3273 | input [63:0] i2; | |
3274 | output [63:0] carry; | |
3275 | output [63:0] sum; | |
3276 | ||
3277 | ||
3278 | ||
3279 | ||
3280 | ||
3281 | ||
3282 | csa32 #(64) d0_0 ( | |
3283 | .in0(i0[63:0]), | |
3284 | .in1(i1[63:0]), | |
3285 | .in2(i2[63:0]), | |
3286 | .carry(carry[63:0]), | |
3287 | .sum(sum[63:0]) | |
3288 | ); | |
3289 | ||
3290 | ||
3291 | ||
3292 | ||
3293 | ||
3294 | ||
3295 | ||
3296 | ||
3297 | ||
3298 | endmodule | |
3299 | ||
3300 | ||
3301 | ||
3302 | ||
3303 | ||
3304 | ||
3305 | // any PARAMS parms go into naming of macro | |
3306 | ||
3307 | module fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_65 ( | |
3308 | din0, | |
3309 | din1, | |
3310 | din2, | |
3311 | din3, | |
3312 | din4, | |
3313 | din5, | |
3314 | sel0, | |
3315 | sel1, | |
3316 | sel2, | |
3317 | sel3, | |
3318 | sel4, | |
3319 | clk, | |
3320 | en, | |
3321 | se, | |
3322 | scan_in, | |
3323 | siclk, | |
3324 | soclk, | |
3325 | pce_ov, | |
3326 | stop, | |
3327 | dout, | |
3328 | scan_out); | |
3329 | wire psel0; | |
3330 | wire psel1; | |
3331 | wire psel2; | |
3332 | wire psel3; | |
3333 | wire psel4; | |
3334 | wire psel5; | |
3335 | wire [64:0] muxout; | |
3336 | wire l1clk; | |
3337 | wire siclk_out; | |
3338 | wire soclk_out; | |
3339 | wire [63:0] so; | |
3340 | ||
3341 | input [64:0] din0; | |
3342 | input [64:0] din1; | |
3343 | input [64:0] din2; | |
3344 | input [64:0] din3; | |
3345 | input [64:0] din4; | |
3346 | input [64:0] din5; | |
3347 | input sel0; | |
3348 | input sel1; | |
3349 | input sel2; | |
3350 | input sel3; | |
3351 | input sel4; | |
3352 | ||
3353 | ||
3354 | input clk; | |
3355 | input en; | |
3356 | input se; | |
3357 | input scan_in; | |
3358 | input siclk; | |
3359 | input soclk; | |
3360 | input pce_ov; | |
3361 | input stop; | |
3362 | ||
3363 | ||
3364 | ||
3365 | output [64:0] dout; | |
3366 | ||
3367 | ||
3368 | output scan_out; | |
3369 | ||
3370 | ||
3371 | ||
3372 | ||
3373 | cl_dp1_penc6_8x c1_0 ( | |
3374 | .test(1'b1), | |
3375 | .sel0(sel0), | |
3376 | .sel1(sel1), | |
3377 | .sel2(sel2), | |
3378 | .sel3(sel3), | |
3379 | .sel4(sel4), | |
3380 | .psel0(psel0), | |
3381 | .psel1(psel1), | |
3382 | .psel2(psel2), | |
3383 | .psel3(psel3), | |
3384 | .psel4(psel4), | |
3385 | .psel5(psel5) | |
3386 | ); | |
3387 | ||
3388 | mux6s #(65) d1_0 ( | |
3389 | .sel0(psel0), | |
3390 | .sel1(psel1), | |
3391 | .sel2(psel2), | |
3392 | .sel3(psel3), | |
3393 | .sel4(psel4), | |
3394 | .sel5(psel5), | |
3395 | .in0(din0[64:0]), | |
3396 | .in1(din1[64:0]), | |
3397 | .in2(din2[64:0]), | |
3398 | .in3(din3[64:0]), | |
3399 | .in4(din4[64:0]), | |
3400 | .in5(din5[64:0]), | |
3401 | .dout(muxout[64:0]) | |
3402 | ); | |
3403 | cl_dp1_l1hdr_8x c0_0 ( | |
3404 | .l2clk(clk), | |
3405 | .pce(en), | |
3406 | .aclk(siclk), | |
3407 | .bclk(soclk), | |
3408 | .l1clk(l1clk), | |
3409 | .se(se), | |
3410 | .pce_ov(pce_ov), | |
3411 | .stop(stop), | |
3412 | .siclk_out(siclk_out), | |
3413 | .soclk_out(soclk_out) | |
3414 | ); | |
3415 | dff #(65) d0_0 ( | |
3416 | .l1clk(l1clk), | |
3417 | .siclk(siclk_out), | |
3418 | .soclk(soclk_out), | |
3419 | .d(muxout[64:0]), | |
3420 | .si({scan_in,so[63:0]}), | |
3421 | .so({so[63:0],scan_out}), | |
3422 | .q(dout[64:0]) | |
3423 | ); | |
3424 | ||
3425 | ||
3426 | ||
3427 | ||
3428 | ||
3429 | ||
3430 | ||
3431 | ||
3432 | ||
3433 | ||
3434 | ||
3435 | ||
3436 | ||
3437 | ||
3438 | ||
3439 | ||
3440 | ||
3441 | ||
3442 | ||
3443 | ||
3444 | endmodule | |
3445 | ||
3446 | ||
3447 | ||
3448 | ||
3449 | ||
3450 | ||
3451 | ||
3452 | ||
3453 | ||
3454 | ||
3455 | ||
3456 | ||
3457 | ||
3458 | // any PARAMS parms go into naming of macro | |
3459 | ||
3460 | module fgu_fdd_dp_msff_macro__mux_aope__ports_4__stack_66c__width_65 ( | |
3461 | din0, | |
3462 | din1, | |
3463 | din2, | |
3464 | din3, | |
3465 | sel0, | |
3466 | sel1, | |
3467 | sel2, | |
3468 | clk, | |
3469 | en, | |
3470 | se, | |
3471 | scan_in, | |
3472 | siclk, | |
3473 | soclk, | |
3474 | pce_ov, | |
3475 | stop, | |
3476 | dout, | |
3477 | scan_out); | |
3478 | wire psel0; | |
3479 | wire psel1; | |
3480 | wire psel2; | |
3481 | wire psel3; | |
3482 | wire [64:0] muxout; | |
3483 | wire l1clk; | |
3484 | wire siclk_out; | |
3485 | wire soclk_out; | |
3486 | wire [63:0] so; | |
3487 | ||
3488 | input [64:0] din0; | |
3489 | input [64:0] din1; | |
3490 | input [64:0] din2; | |
3491 | input [64:0] din3; | |
3492 | input sel0; | |
3493 | input sel1; | |
3494 | input sel2; | |
3495 | ||
3496 | ||
3497 | input clk; | |
3498 | input en; | |
3499 | input se; | |
3500 | input scan_in; | |
3501 | input siclk; | |
3502 | input soclk; | |
3503 | input pce_ov; | |
3504 | input stop; | |
3505 | ||
3506 | ||
3507 | ||
3508 | output [64:0] dout; | |
3509 | ||
3510 | ||
3511 | output scan_out; | |
3512 | ||
3513 | ||
3514 | ||
3515 | ||
3516 | cl_dp1_penc4_8x c1_0 ( | |
3517 | .test(1'b1), | |
3518 | .sel0(sel0), | |
3519 | .sel1(sel1), | |
3520 | .sel2(sel2), | |
3521 | .psel0(psel0), | |
3522 | .psel1(psel1), | |
3523 | .psel2(psel2), | |
3524 | .psel3(psel3) | |
3525 | ); | |
3526 | ||
3527 | mux4s #(65) d1_0 ( | |
3528 | .sel0(psel0), | |
3529 | .sel1(psel1), | |
3530 | .sel2(psel2), | |
3531 | .sel3(psel3), | |
3532 | .in0(din0[64:0]), | |
3533 | .in1(din1[64:0]), | |
3534 | .in2(din2[64:0]), | |
3535 | .in3(din3[64:0]), | |
3536 | .dout(muxout[64:0]) | |
3537 | ); | |
3538 | cl_dp1_l1hdr_8x c0_0 ( | |
3539 | .l2clk(clk), | |
3540 | .pce(en), | |
3541 | .aclk(siclk), | |
3542 | .bclk(soclk), | |
3543 | .l1clk(l1clk), | |
3544 | .se(se), | |
3545 | .pce_ov(pce_ov), | |
3546 | .stop(stop), | |
3547 | .siclk_out(siclk_out), | |
3548 | .soclk_out(soclk_out) | |
3549 | ); | |
3550 | dff #(65) d0_0 ( | |
3551 | .l1clk(l1clk), | |
3552 | .siclk(siclk_out), | |
3553 | .soclk(soclk_out), | |
3554 | .d(muxout[64:0]), | |
3555 | .si({scan_in,so[63:0]}), | |
3556 | .so({so[63:0],scan_out}), | |
3557 | .q(dout[64:0]) | |
3558 | ); | |
3559 | ||
3560 | ||
3561 | ||
3562 | ||
3563 | ||
3564 | ||
3565 | ||
3566 | ||
3567 | ||
3568 | ||
3569 | ||
3570 | ||
3571 | ||
3572 | ||
3573 | ||
3574 | ||
3575 | ||
3576 | ||
3577 | ||
3578 | ||
3579 | endmodule | |
3580 | ||
3581 | ||
3582 | ||
3583 | ||
3584 | ||
3585 | ||
3586 | ||
3587 | ||
3588 | ||
3589 | // | |
3590 | // cla macro | |
3591 | // | |
3592 | // | |
3593 | ||
3594 | ||
3595 | ||
3596 | ||
3597 | ||
3598 | module fgu_fdd_dp_cla_macro__width_64 ( | |
3599 | cin, | |
3600 | din0, | |
3601 | din1, | |
3602 | dout, | |
3603 | cout); | |
3604 | input cin; | |
3605 | input [63:0] din0; | |
3606 | input [63:0] din1; | |
3607 | output [63:0] dout; | |
3608 | output cout; | |
3609 | ||
3610 | ||
3611 | ||
3612 | ||
3613 | ||
3614 | ||
3615 | ||
3616 | cla #(64) m0_0 ( | |
3617 | .cin(cin), | |
3618 | .in0(din0[63:0]), | |
3619 | .in1(din1[63:0]), | |
3620 | .out(dout[63:0]), | |
3621 | .cout(cout) | |
3622 | ); | |
3623 | ||
3624 | ||
3625 | ||
3626 | ||
3627 | ||
3628 | ||
3629 | ||
3630 | ||
3631 | ||
3632 | ||
3633 | ||
3634 | ||
3635 | endmodule | |
3636 | ||
3637 | ||
3638 | ||
3639 | ||
3640 | ||
3641 | // | |
3642 | // and macro for ports = 2,3,4 | |
3643 | // | |
3644 | // | |
3645 | ||
3646 | ||
3647 | ||
3648 | ||
3649 | ||
3650 | module fgu_fdd_dp_and_macro__ports_2__stack_66c__width_1 ( | |
3651 | din0, | |
3652 | din1, | |
3653 | dout); | |
3654 | input [0:0] din0; | |
3655 | input [0:0] din1; | |
3656 | output [0:0] dout; | |
3657 | ||
3658 | ||
3659 | ||
3660 | ||
3661 | ||
3662 | ||
3663 | and2 #(1) d0_0 ( | |
3664 | .in0(din0[0:0]), | |
3665 | .in1(din1[0:0]), | |
3666 | .out(dout[0:0]) | |
3667 | ); | |
3668 | ||
3669 | ||
3670 | ||
3671 | ||
3672 | ||
3673 | ||
3674 | ||
3675 | ||
3676 | ||
3677 | endmodule | |
3678 | ||
3679 | ||
3680 | ||
3681 | ||
3682 | ||
3683 | ||
3684 | ||
3685 | ||
3686 | ||
3687 | // any PARAMS parms go into naming of macro | |
3688 | ||
3689 | module fgu_fdd_dp_msff_macro__mux_aope__ports_6__stack_66c__width_64 ( | |
3690 | din0, | |
3691 | din1, | |
3692 | din2, | |
3693 | din3, | |
3694 | din4, | |
3695 | din5, | |
3696 | sel0, | |
3697 | sel1, | |
3698 | sel2, | |
3699 | sel3, | |
3700 | sel4, | |
3701 | clk, | |
3702 | en, | |
3703 | se, | |
3704 | scan_in, | |
3705 | siclk, | |
3706 | soclk, | |
3707 | pce_ov, | |
3708 | stop, | |
3709 | dout, | |
3710 | scan_out); | |
3711 | wire psel0; | |
3712 | wire psel1; | |
3713 | wire psel2; | |
3714 | wire psel3; | |
3715 | wire psel4; | |
3716 | wire psel5; | |
3717 | wire [63:0] muxout; | |
3718 | wire l1clk; | |
3719 | wire siclk_out; | |
3720 | wire soclk_out; | |
3721 | wire [62:0] so; | |
3722 | ||
3723 | input [63:0] din0; | |
3724 | input [63:0] din1; | |
3725 | input [63:0] din2; | |
3726 | input [63:0] din3; | |
3727 | input [63:0] din4; | |
3728 | input [63:0] din5; | |
3729 | input sel0; | |
3730 | input sel1; | |
3731 | input sel2; | |
3732 | input sel3; | |
3733 | input sel4; | |
3734 | ||
3735 | ||
3736 | input clk; | |
3737 | input en; | |
3738 | input se; | |
3739 | input scan_in; | |
3740 | input siclk; | |
3741 | input soclk; | |
3742 | input pce_ov; | |
3743 | input stop; | |
3744 | ||
3745 | ||
3746 | ||
3747 | output [63:0] dout; | |
3748 | ||
3749 | ||
3750 | output scan_out; | |
3751 | ||
3752 | ||
3753 | ||
3754 | ||
3755 | cl_dp1_penc6_8x c1_0 ( | |
3756 | .test(1'b1), | |
3757 | .sel0(sel0), | |
3758 | .sel1(sel1), | |
3759 | .sel2(sel2), | |
3760 | .sel3(sel3), | |
3761 | .sel4(sel4), | |
3762 | .psel0(psel0), | |
3763 | .psel1(psel1), | |
3764 | .psel2(psel2), | |
3765 | .psel3(psel3), | |
3766 | .psel4(psel4), | |
3767 | .psel5(psel5) | |
3768 | ); | |
3769 | ||
3770 | mux6s #(64) d1_0 ( | |
3771 | .sel0(psel0), | |
3772 | .sel1(psel1), | |
3773 | .sel2(psel2), | |
3774 | .sel3(psel3), | |
3775 | .sel4(psel4), | |
3776 | .sel5(psel5), | |
3777 | .in0(din0[63:0]), | |
3778 | .in1(din1[63:0]), | |
3779 | .in2(din2[63:0]), | |
3780 | .in3(din3[63:0]), | |
3781 | .in4(din4[63:0]), | |
3782 | .in5(din5[63:0]), | |
3783 | .dout(muxout[63:0]) | |
3784 | ); | |
3785 | cl_dp1_l1hdr_8x c0_0 ( | |
3786 | .l2clk(clk), | |
3787 | .pce(en), | |
3788 | .aclk(siclk), | |
3789 | .bclk(soclk), | |
3790 | .l1clk(l1clk), | |
3791 | .se(se), | |
3792 | .pce_ov(pce_ov), | |
3793 | .stop(stop), | |
3794 | .siclk_out(siclk_out), | |
3795 | .soclk_out(soclk_out) | |
3796 | ); | |
3797 | dff #(64) d0_0 ( | |
3798 | .l1clk(l1clk), | |
3799 | .siclk(siclk_out), | |
3800 | .soclk(soclk_out), | |
3801 | .d(muxout[63:0]), | |
3802 | .si({scan_in,so[62:0]}), | |
3803 | .so({so[62:0],scan_out}), | |
3804 | .q(dout[63:0]) | |
3805 | ); | |
3806 | ||
3807 | ||
3808 | ||
3809 | ||
3810 | ||
3811 | ||
3812 | ||
3813 | ||
3814 | ||
3815 | ||
3816 | ||
3817 | ||
3818 | ||
3819 | ||
3820 | ||
3821 | ||
3822 | ||
3823 | ||
3824 | ||
3825 | ||
3826 | endmodule | |
3827 | ||
3828 | ||
3829 | ||
3830 | ||
3831 | ||
3832 | ||
3833 | ||
3834 | ||
3835 | ||
3836 | ||
3837 | ||
3838 | ||
3839 | ||
3840 | // any PARAMS parms go into naming of macro | |
3841 | ||
3842 | module fgu_fdd_dp_msff_macro__mux_aope__ports_2__stack_66c__width_66 ( | |
3843 | din0, | |
3844 | din1, | |
3845 | sel0, | |
3846 | clk, | |
3847 | en, | |
3848 | se, | |
3849 | scan_in, | |
3850 | siclk, | |
3851 | soclk, | |
3852 | pce_ov, | |
3853 | stop, | |
3854 | dout, | |
3855 | scan_out); | |
3856 | wire psel0; | |
3857 | wire psel1; | |
3858 | wire [65:0] muxout; | |
3859 | wire l1clk; | |
3860 | wire siclk_out; | |
3861 | wire soclk_out; | |
3862 | wire [64:0] so; | |
3863 | ||
3864 | input [65:0] din0; | |
3865 | input [65:0] din1; | |
3866 | input sel0; | |
3867 | ||
3868 | ||
3869 | input clk; | |
3870 | input en; | |
3871 | input se; | |
3872 | input scan_in; | |
3873 | input siclk; | |
3874 | input soclk; | |
3875 | input pce_ov; | |
3876 | input stop; | |
3877 | ||
3878 | ||
3879 | ||
3880 | output [65:0] dout; | |
3881 | ||
3882 | ||
3883 | output scan_out; | |
3884 | ||
3885 | ||
3886 | ||
3887 | ||
3888 | cl_dp1_penc2_8x c1_0 ( | |
3889 | .sel0(sel0), | |
3890 | .psel0(psel0), | |
3891 | .psel1(psel1) | |
3892 | ); | |
3893 | ||
3894 | mux2s #(66) d1_0 ( | |
3895 | .sel0(psel0), | |
3896 | .sel1(psel1), | |
3897 | .in0(din0[65:0]), | |
3898 | .in1(din1[65:0]), | |
3899 | .dout(muxout[65:0]) | |
3900 | ); | |
3901 | cl_dp1_l1hdr_8x c0_0 ( | |
3902 | .l2clk(clk), | |
3903 | .pce(en), | |
3904 | .aclk(siclk), | |
3905 | .bclk(soclk), | |
3906 | .l1clk(l1clk), | |
3907 | .se(se), | |
3908 | .pce_ov(pce_ov), | |
3909 | .stop(stop), | |
3910 | .siclk_out(siclk_out), | |
3911 | .soclk_out(soclk_out) | |
3912 | ); | |
3913 | dff #(66) d0_0 ( | |
3914 | .l1clk(l1clk), | |
3915 | .siclk(siclk_out), | |
3916 | .soclk(soclk_out), | |
3917 | .d(muxout[65:0]), | |
3918 | .si({scan_in,so[64:0]}), | |
3919 | .so({so[64:0],scan_out}), | |
3920 | .q(dout[65:0]) | |
3921 | ); | |
3922 | ||
3923 | ||
3924 | ||
3925 | ||
3926 | ||
3927 | ||
3928 | ||
3929 | ||
3930 | ||
3931 | ||
3932 | ||
3933 | ||
3934 | ||
3935 | ||
3936 | ||
3937 | ||
3938 | ||
3939 | ||
3940 | ||
3941 | ||
3942 | endmodule | |
3943 | ||
3944 | ||
3945 | ||
3946 | ||
3947 | ||
3948 | ||
3949 | ||
3950 | ||
3951 | ||
3952 | // | |
3953 | // invert macro | |
3954 | // | |
3955 | // | |
3956 | ||
3957 | ||
3958 | ||
3959 | ||
3960 | ||
3961 | module fgu_fdd_dp_inv_macro__stack_66c__width_66 ( | |
3962 | din, | |
3963 | dout); | |
3964 | input [65:0] din; | |
3965 | output [65:0] dout; | |
3966 | ||
3967 | ||
3968 | ||
3969 | ||
3970 | ||
3971 | ||
3972 | inv #(66) d0_0 ( | |
3973 | .in(din[65:0]), | |
3974 | .out(dout[65:0]) | |
3975 | ); | |
3976 | ||
3977 | ||
3978 | ||
3979 | ||
3980 | ||
3981 | ||
3982 | ||
3983 | ||
3984 | ||
3985 | endmodule | |
3986 | ||
3987 | ||
3988 | ||
3989 | ||
3990 | ||
3991 | ||
3992 | ||
3993 | ||
3994 | ||
3995 | // any PARAMS parms go into naming of macro | |
3996 | ||
3997 | module fgu_fdd_dp_msff_macro__mux_aonpe__ports_2__stack_66c__width_66 ( | |
3998 | din0, | |
3999 | sel0, | |
4000 | din1, | |
4001 | sel1, | |
4002 | clk, | |
4003 | en, | |
4004 | se, | |
4005 | scan_in, | |
4006 | siclk, | |
4007 | soclk, | |
4008 | pce_ov, | |
4009 | stop, | |
4010 | dout, | |
4011 | scan_out); | |
4012 | wire buffout0; | |
4013 | wire buffout1; | |
4014 | wire [65:0] muxout; | |
4015 | wire l1clk; | |
4016 | wire siclk_out; | |
4017 | wire soclk_out; | |
4018 | wire [64:0] so; | |
4019 | ||
4020 | input [65:0] din0; | |
4021 | input sel0; | |
4022 | input [65:0] din1; | |
4023 | input sel1; | |
4024 | ||
4025 | ||
4026 | input clk; | |
4027 | input en; | |
4028 | input se; | |
4029 | input scan_in; | |
4030 | input siclk; | |
4031 | input soclk; | |
4032 | input pce_ov; | |
4033 | input stop; | |
4034 | ||
4035 | ||
4036 | ||
4037 | output [65:0] dout; | |
4038 | ||
4039 | ||
4040 | output scan_out; | |
4041 | ||
4042 | ||
4043 | ||
4044 | ||
4045 | cl_dp1_muxbuff2_8x c1_0 ( | |
4046 | .in0(sel0), | |
4047 | .in1(sel1), | |
4048 | .out0(buffout0), | |
4049 | .out1(buffout1) | |
4050 | ); | |
4051 | mux2s #(66) d1_0 ( | |
4052 | .sel0(buffout0), | |
4053 | .sel1(buffout1), | |
4054 | .in0(din0[65:0]), | |
4055 | .in1(din1[65:0]), | |
4056 | .dout(muxout[65:0]) | |
4057 | ); | |
4058 | cl_dp1_l1hdr_8x c0_0 ( | |
4059 | .l2clk(clk), | |
4060 | .pce(en), | |
4061 | .aclk(siclk), | |
4062 | .bclk(soclk), | |
4063 | .l1clk(l1clk), | |
4064 | .se(se), | |
4065 | .pce_ov(pce_ov), | |
4066 | .stop(stop), | |
4067 | .siclk_out(siclk_out), | |
4068 | .soclk_out(soclk_out) | |
4069 | ); | |
4070 | dff #(66) d0_0 ( | |
4071 | .l1clk(l1clk), | |
4072 | .siclk(siclk_out), | |
4073 | .soclk(soclk_out), | |
4074 | .d(muxout[65:0]), | |
4075 | .si({scan_in,so[64:0]}), | |
4076 | .so({so[64:0],scan_out}), | |
4077 | .q(dout[65:0]) | |
4078 | ); | |
4079 | ||
4080 | ||
4081 | ||
4082 | ||
4083 | ||
4084 | ||
4085 | ||
4086 | ||
4087 | ||
4088 | ||
4089 | ||
4090 | ||
4091 | ||
4092 | ||
4093 | ||
4094 | ||
4095 | ||
4096 | ||
4097 | ||
4098 | ||
4099 | endmodule | |
4100 | ||
4101 | ||
4102 | ||
4103 | ||
4104 | ||
4105 | ||
4106 | ||
4107 | ||
4108 | ||
4109 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4110 | // also for pass-gate with decoder | |
4111 | ||
4112 | ||
4113 | ||
4114 | ||
4115 | ||
4116 | // any PARAMS parms go into naming of macro | |
4117 | ||
4118 | module fgu_fdd_dp_mux_macro__mux_aonpe__ports_2__stack_66c__width_66 ( | |
4119 | din0, | |
4120 | sel0, | |
4121 | din1, | |
4122 | sel1, | |
4123 | dout); | |
4124 | wire buffout0; | |
4125 | wire buffout1; | |
4126 | ||
4127 | input [65:0] din0; | |
4128 | input sel0; | |
4129 | input [65:0] din1; | |
4130 | input sel1; | |
4131 | output [65:0] dout; | |
4132 | ||
4133 | ||
4134 | ||
4135 | ||
4136 | ||
4137 | cl_dp1_muxbuff2_8x c0_0 ( | |
4138 | .in0(sel0), | |
4139 | .in1(sel1), | |
4140 | .out0(buffout0), | |
4141 | .out1(buffout1) | |
4142 | ); | |
4143 | mux2s #(66) d0_0 ( | |
4144 | .sel0(buffout0), | |
4145 | .sel1(buffout1), | |
4146 | .in0(din0[65:0]), | |
4147 | .in1(din1[65:0]), | |
4148 | .dout(dout[65:0]) | |
4149 | ); | |
4150 | ||
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | ||
4157 | ||
4158 | ||
4159 | ||
4160 | ||
4161 | ||
4162 | ||
4163 | endmodule | |
4164 | ||
4165 | ||
4166 | // | |
4167 | // nand macro for ports = 2,3,4 | |
4168 | // | |
4169 | // | |
4170 | ||
4171 | ||
4172 | ||
4173 | ||
4174 | ||
4175 | module fgu_fdd_dp_nand_macro__ports_3__stack_66c__width_66 ( | |
4176 | din0, | |
4177 | din1, | |
4178 | din2, | |
4179 | dout); | |
4180 | input [65:0] din0; | |
4181 | input [65:0] din1; | |
4182 | input [65:0] din2; | |
4183 | output [65:0] dout; | |
4184 | ||
4185 | ||
4186 | ||
4187 | ||
4188 | ||
4189 | ||
4190 | nand3 #(66) d0_0 ( | |
4191 | .in0(din0[65:0]), | |
4192 | .in1(din1[65:0]), | |
4193 | .in2(din2[65:0]), | |
4194 | .out(dout[65:0]) | |
4195 | ); | |
4196 | ||
4197 | ||
4198 | ||
4199 | ||
4200 | ||
4201 | ||
4202 | ||
4203 | ||
4204 | ||
4205 | endmodule | |
4206 | ||
4207 | ||
4208 | ||
4209 | ||
4210 | ||
4211 | // | |
4212 | // nand macro for ports = 2,3,4 | |
4213 | // | |
4214 | // | |
4215 | ||
4216 | ||
4217 | ||
4218 | ||
4219 | ||
4220 | module fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_65 ( | |
4221 | din0, | |
4222 | din1, | |
4223 | dout); | |
4224 | input [64:0] din0; | |
4225 | input [64:0] din1; | |
4226 | output [64:0] dout; | |
4227 | ||
4228 | ||
4229 | ||
4230 | ||
4231 | ||
4232 | ||
4233 | nand2 #(65) d0_0 ( | |
4234 | .in0(din0[64:0]), | |
4235 | .in1(din1[64:0]), | |
4236 | .out(dout[64:0]) | |
4237 | ); | |
4238 | ||
4239 | ||
4240 | ||
4241 | ||
4242 | ||
4243 | ||
4244 | ||
4245 | ||
4246 | ||
4247 | endmodule | |
4248 | ||
4249 | ||
4250 | ||
4251 | ||
4252 | ||
4253 | // | |
4254 | // nand macro for ports = 2,3,4 | |
4255 | // | |
4256 | // | |
4257 | ||
4258 | ||
4259 | ||
4260 | ||
4261 | ||
4262 | module fgu_fdd_dp_nand_macro__ports_2__stack_66c__width_66 ( | |
4263 | din0, | |
4264 | din1, | |
4265 | dout); | |
4266 | input [65:0] din0; | |
4267 | input [65:0] din1; | |
4268 | output [65:0] dout; | |
4269 | ||
4270 | ||
4271 | ||
4272 | ||
4273 | ||
4274 | ||
4275 | nand2 #(66) d0_0 ( | |
4276 | .in0(din0[65:0]), | |
4277 | .in1(din1[65:0]), | |
4278 | .out(dout[65:0]) | |
4279 | ); | |
4280 | ||
4281 | ||
4282 | ||
4283 | ||
4284 | ||
4285 | ||
4286 | ||
4287 | ||
4288 | ||
4289 | endmodule | |
4290 | ||
4291 | ||
4292 | ||
4293 |