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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: fgu_fgd_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module fgu_fgd_dp ( | |
36 | fad_rs1_fmt_fx1, | |
37 | fad_rs2_fmt_fx1, | |
38 | fgd_rngl_cdbus_3f, | |
39 | fgd_result_fx5, | |
40 | vis_clken, | |
41 | coreon_clken, | |
42 | fac_fgx_abs_fx2, | |
43 | fac_fgx_neg_fx2, | |
44 | fac_fgx_logical_fx2, | |
45 | fac_fgx_expand_fx2, | |
46 | fac_fgx_merge_fx2, | |
47 | fac_fgx_align_fx2, | |
48 | fac_fgx_shuffle_fx2, | |
49 | fac_fgx_pack16_fx2, | |
50 | fac_fgx_pack32_fx2, | |
51 | fac_fgx_packfix_fx2, | |
52 | fac_fgx_pdist_fx1, | |
53 | fac_fgx_popc_fx2, | |
54 | fac_fgx_pack_sel_fx2, | |
55 | fac_opf_fx2, | |
56 | fac_gsr_asr_tid_fx2, | |
57 | fac_tid_fx2, | |
58 | fac_rng_fprs, | |
59 | fac_rng_rd_fprs_4f, | |
60 | fac_rng_rd_gsr_4f, | |
61 | fec_r1_ecc_fx1, | |
62 | fac_rng_rd_ecc_4f, | |
63 | fac_rng_rd_or_wr_3f, | |
64 | asi_clken, | |
65 | fgd_gsr_asr_mask_fx4_b31, | |
66 | fpc_gsr0_mask_sel_fx3, | |
67 | fpc_gsr1_mask_sel_fx3, | |
68 | fpc_gsr2_mask_sel_fx3, | |
69 | fpc_gsr3_mask_sel_fx3, | |
70 | fpc_gsr4_mask_sel_fx3, | |
71 | fpc_gsr5_mask_sel_fx3, | |
72 | fpc_gsr6_mask_sel_fx3, | |
73 | fpc_gsr7_mask_sel_fx3, | |
74 | fpc_gsr_scale_fx4, | |
75 | fpc_gsr_align_fx4, | |
76 | fpc_gsr_asr_11bits_fx4, | |
77 | exu_fgu_gsr_m, | |
78 | l2clk, | |
79 | scan_in, | |
80 | spc_aclk_wmr, | |
81 | wmr_scan_in, | |
82 | lb_scan_en_wmr, | |
83 | tcu_pce_ov, | |
84 | spc_aclk, | |
85 | spc_bclk, | |
86 | tcu_dectest, | |
87 | tcu_muxtest, | |
88 | tcu_scan_en, | |
89 | scan_out, | |
90 | wmr_scan_out, | |
91 | in_rngl_cdbus); | |
92 | wire stop; | |
93 | wire test; | |
94 | wire se; | |
95 | wire pce_ov; | |
96 | wire siclk; | |
97 | wire soclk; | |
98 | wire fx2_rs1_scanin; | |
99 | wire fx2_rs1_scanout; | |
100 | wire [63:0] rs1_fx2; | |
101 | wire fx2_rs2_scanin; | |
102 | wire fx2_rs2_scanout; | |
103 | wire [63:0] rs2_fx2; | |
104 | wire fx2_gsr_scanin; | |
105 | wire fx2_gsr_scanout; | |
106 | wire [31:0] gsr_fx2; | |
107 | wire fgx_pdist_fx3; | |
108 | wire fgx_popc_fx3; | |
109 | wire [11:0] pdist_rs3_fx2; | |
110 | wire popc_byte7a_cout_fx2; | |
111 | wire popc_byte7a_carry_fx2; | |
112 | wire popc_byte7a_sum_fx2; | |
113 | wire popc_byte7b_cout_fx2; | |
114 | wire popc_byte7b_carry_fx2; | |
115 | wire popc_byte7b_sum_fx2; | |
116 | wire popc_byte7c_cout_fx2; | |
117 | wire popc_byte7c_carry_fx2; | |
118 | wire popc_byte7c_sum_fx2; | |
119 | wire [3:0] popc_byte7_sum_fx2; | |
120 | wire popc_b7_unused; | |
121 | wire popc_byte6a_cout_fx2; | |
122 | wire popc_byte6a_carry_fx2; | |
123 | wire popc_byte6a_sum_fx2; | |
124 | wire popc_byte6b_cout_fx2; | |
125 | wire popc_byte6b_carry_fx2; | |
126 | wire popc_byte6b_sum_fx2; | |
127 | wire popc_byte6c_cout_fx2; | |
128 | wire popc_byte6c_carry_fx2; | |
129 | wire popc_byte6c_sum_fx2; | |
130 | wire [3:0] popc_byte6_sum_fx2; | |
131 | wire popc_b6_unused; | |
132 | wire popc_byte5a_cout_fx2; | |
133 | wire popc_byte5a_carry_fx2; | |
134 | wire popc_byte5a_sum_fx2; | |
135 | wire popc_byte5b_cout_fx2; | |
136 | wire popc_byte5b_carry_fx2; | |
137 | wire popc_byte5b_sum_fx2; | |
138 | wire popc_byte5c_cout_fx2; | |
139 | wire popc_byte5c_carry_fx2; | |
140 | wire popc_byte5c_sum_fx2; | |
141 | wire [3:0] popc_byte5_sum_fx2; | |
142 | wire popc_b5_unused; | |
143 | wire popc_byte4a_cout_fx2; | |
144 | wire popc_byte4a_carry_fx2; | |
145 | wire popc_byte4a_sum_fx2; | |
146 | wire popc_byte4b_cout_fx2; | |
147 | wire popc_byte4b_carry_fx2; | |
148 | wire popc_byte4b_sum_fx2; | |
149 | wire popc_byte4c_cout_fx2; | |
150 | wire popc_byte4c_carry_fx2; | |
151 | wire popc_byte4c_sum_fx2; | |
152 | wire [3:0] popc_byte4_sum_fx2; | |
153 | wire popc_b4_unused; | |
154 | wire popc_byte3a_cout_fx2; | |
155 | wire popc_byte3a_carry_fx2; | |
156 | wire popc_byte3a_sum_fx2; | |
157 | wire popc_byte3b_cout_fx2; | |
158 | wire popc_byte3b_carry_fx2; | |
159 | wire popc_byte3b_sum_fx2; | |
160 | wire popc_byte3c_cout_fx2; | |
161 | wire popc_byte3c_carry_fx2; | |
162 | wire popc_byte3c_sum_fx2; | |
163 | wire [3:0] popc_byte3_sum_fx2; | |
164 | wire popc_b3_unused; | |
165 | wire popc_byte2a_cout_fx2; | |
166 | wire popc_byte2a_carry_fx2; | |
167 | wire popc_byte2a_sum_fx2; | |
168 | wire popc_byte2b_cout_fx2; | |
169 | wire popc_byte2b_carry_fx2; | |
170 | wire popc_byte2b_sum_fx2; | |
171 | wire popc_byte2c_cout_fx2; | |
172 | wire popc_byte2c_carry_fx2; | |
173 | wire popc_byte2c_sum_fx2; | |
174 | wire [3:0] popc_byte2_sum_fx2; | |
175 | wire popc_b2_unused; | |
176 | wire popc_byte1a_cout_fx2; | |
177 | wire popc_byte1a_carry_fx2; | |
178 | wire popc_byte1a_sum_fx2; | |
179 | wire popc_byte1b_cout_fx2; | |
180 | wire popc_byte1b_carry_fx2; | |
181 | wire popc_byte1b_sum_fx2; | |
182 | wire popc_byte1c_cout_fx2; | |
183 | wire popc_byte1c_carry_fx2; | |
184 | wire popc_byte1c_sum_fx2; | |
185 | wire [3:0] popc_byte1_sum_fx2; | |
186 | wire popc_b1_unused; | |
187 | wire popc_byte0a_cout_fx2; | |
188 | wire popc_byte0a_carry_fx2; | |
189 | wire popc_byte0a_sum_fx2; | |
190 | wire popc_byte0b_cout_fx2; | |
191 | wire popc_byte0b_carry_fx2; | |
192 | wire popc_byte0b_sum_fx2; | |
193 | wire popc_byte0c_cout_fx2; | |
194 | wire popc_byte0c_carry_fx2; | |
195 | wire popc_byte0c_sum_fx2; | |
196 | wire [3:0] popc_byte0_sum_fx2; | |
197 | wire popc_b0_unused; | |
198 | wire fx3_rs1_scanin; | |
199 | wire fx3_rs1_scanout; | |
200 | wire [63:0] rs1_fx3; | |
201 | wire [63:0] rs10_fx3; | |
202 | wire fx3_rs2_scanin; | |
203 | wire fx3_rs2_scanout; | |
204 | wire [63:0] rs2_fx3; | |
205 | wire [63:0] rs20_fx3; | |
206 | wire fx3_gsr_mask_scanin; | |
207 | wire fx3_gsr_mask_scanout; | |
208 | wire [31:0] gsr_mask_fx3; | |
209 | wire fx3_popc_scanin; | |
210 | wire fx3_popc_scanout; | |
211 | wire [3:0] popc_byte0_sum_fx3; | |
212 | wire [3:0] popc_byte1_sum_fx3; | |
213 | wire [3:0] popc_byte2_sum_fx3; | |
214 | wire [3:0] popc_byte3_sum_fx3; | |
215 | wire [3:0] popc_byte4_sum_fx3; | |
216 | wire [3:0] popc_byte5_sum_fx3; | |
217 | wire [3:0] popc_byte6_sum_fx3; | |
218 | wire [3:0] popc_byte7_sum_fx3; | |
219 | wire fx3_ctl_scanin; | |
220 | wire fx3_ctl_scanout; | |
221 | wire fgx_pdist_fx2; | |
222 | wire fgx_pack_sel_fx3; | |
223 | wire fgx_abs_fx3; | |
224 | wire fgx_neg_fx3; | |
225 | wire fgx_logical_fx3; | |
226 | wire fgx_expand_fx3; | |
227 | wire fgx_merge_fx3; | |
228 | wire fgx_align_fx3; | |
229 | wire fgx_shuffle_fx3; | |
230 | wire fgx_pack16_fx3; | |
231 | wire fgx_pack32_fx3; | |
232 | wire fgx_packfix_fx3; | |
233 | wire [4:1] opf_fx3; | |
234 | wire fgx_pdist_fx4; | |
235 | wire fgx_popc_fx4; | |
236 | wire fgx_pack_sel_fx4; | |
237 | wire [11:0] pdist_rs3_fx3; | |
238 | wire [63:0] rs101_fx3; | |
239 | wire [63:0] rs201_fx3; | |
240 | wire [63:0] rs201_fx3_; | |
241 | wire [63:0] rs101_fx3_; | |
242 | wire [4:1] opf1_fx3; | |
243 | wire [4:1] opf0_fx3; | |
244 | wire [63:0] logical_int0_fx3; | |
245 | wire [63:0] logical_int1_fx3; | |
246 | wire [63:0] logical_int2_fx3; | |
247 | wire [63:0] logical_int3_fx3; | |
248 | wire [63:0] logical_result_fx3; | |
249 | wire [31:0] gsr_mask0_fx4; | |
250 | wire [63:0] rs1_shuf_fx3; | |
251 | wire [63:0] rs2_shuf_fx3; | |
252 | wire [63:0] shuf_result_fx3; | |
253 | wire [63:0] align_result_fx3; | |
254 | wire rs2_sign63_neg_fx3; | |
255 | wire rs2_sign63_res_fx3; | |
256 | wire fx4_simp_scanin; | |
257 | wire fx4_simp_scanout; | |
258 | wire [63:0] simp_result_fx4; | |
259 | wire fgx_pack16_fx3_; | |
260 | wire sh16_sel_fx3; | |
261 | wire [63:0] shift16_fx3; | |
262 | wire [23:0] gate16_fx3; | |
263 | wire [63:0] shift04_fx3; | |
264 | wire [5:0] gate04_fx3; | |
265 | wire [63:7] shift01_fx3; | |
266 | wire [6:0] pack_01_d2_unused; | |
267 | wire [6:0] pack_01_d0_unused; | |
268 | wire pack_sign63_fx3; | |
269 | wire [15:0] clip16_c3_fx3; | |
270 | wire [27:0] clip04_c3_fx3; | |
271 | wire [30:0] clip01_c3_fx3; | |
272 | wire [11:0] clip04_c2_fx3; | |
273 | wire [14:0] clip01_c2_fx3; | |
274 | wire pack_sign31_fx3; | |
275 | wire [15:0] clip16_c1_fx3; | |
276 | wire [27:0] clip04_c1_fx3; | |
277 | wire [30:0] clip01_c1_fx3; | |
278 | wire [11:0] clip04_c0_fx3; | |
279 | wire [14:0] clip01_c0_fx3; | |
280 | wire [63:0] pdist_amb_fx3; | |
281 | wire pdist_amb_cout0_fx3; | |
282 | wire pdist_amb_cout1_fx3; | |
283 | wire pdist_amb_cout2_fx3; | |
284 | wire pdist_amb_cout3_fx3; | |
285 | wire pdist_amb_cout4_fx3; | |
286 | wire pdist_amb_cout5_fx3; | |
287 | wire pdist_amb_cout6_fx3; | |
288 | wire pdist_amb_cout7_fx3; | |
289 | wire [63:0] pdist_bma_fx3; | |
290 | wire pdist_bma0_unused; | |
291 | wire pdist_bma1_unused; | |
292 | wire pdist_bma2_unused; | |
293 | wire pdist_bma3_unused; | |
294 | wire pdist_bma4_unused; | |
295 | wire pdist_bma5_unused; | |
296 | wire pdist_bma6_unused; | |
297 | wire pdist_bma7_unused; | |
298 | wire [63:0] pdist_mux_fx3; | |
299 | wire pdist_42csa_cout0_fx3; | |
300 | wire [8:1] pdist_42csa_carry0_fx3; | |
301 | wire [7:0] pdist_42csa_sum0_fx3; | |
302 | wire pdist_42csa_cout1_fx3; | |
303 | wire [8:1] pdist_42csa_carry1_fx3; | |
304 | wire [7:0] pdist_42csa_sum1_fx3; | |
305 | wire fx4_rs1_scanin; | |
306 | wire fx4_rs1_scanout; | |
307 | wire [55:0] rs1_fx4; | |
308 | wire fx4_shift_scanin; | |
309 | wire fx4_shift_scanout; | |
310 | wire [63:7] shift01_fx4; | |
311 | wire fx4_clipa_scanin; | |
312 | wire fx4_clipa_scanout; | |
313 | wire [30:0] clip01_c3_fx4; | |
314 | wire [30:0] clip01_c1_fx4; | |
315 | wire fx4_clipb_scanin; | |
316 | wire fx4_clipb_scanout; | |
317 | wire rs2_fx4_b63; | |
318 | wire rs2_fx4_b47; | |
319 | wire [14:0] clip01_c2_fx4; | |
320 | wire [14:0] clip01_c0_fx4; | |
321 | wire rs2_fx4_b31; | |
322 | wire rs2_fx4_b15; | |
323 | wire fgx_packfix_fx4; | |
324 | wire fgx_pack32_fx4; | |
325 | wire fgx_pack16_fx4; | |
326 | wire fx4_pdist_scanin; | |
327 | wire fx4_pdist_scanout; | |
328 | wire [33:0] pdist_42csa_data_fx4; | |
329 | wire fx4_gsrtid_scanin; | |
330 | wire fx4_gsrtid_scanout; | |
331 | wire [2:0] gsr_asr_tid_fx3; | |
332 | wire [2:0] tid_fx3; | |
333 | wire fx4_gsr0mask_wmr_scanin; | |
334 | wire fx4_gsr0mask_wmr_scanout; | |
335 | wire [63:0] in_rngl_cdbus_3f; | |
336 | wire [31:0] gsr0_mask_fx4; | |
337 | wire fx4_gsr1mask_wmr_scanin; | |
338 | wire fx4_gsr1mask_wmr_scanout; | |
339 | wire [31:0] gsr1_mask_fx4; | |
340 | wire fx4_gsr2mask_wmr_scanin; | |
341 | wire fx4_gsr2mask_wmr_scanout; | |
342 | wire [31:0] gsr2_mask_fx4; | |
343 | wire fx4_gsr3mask_wmr_scanin; | |
344 | wire fx4_gsr3mask_wmr_scanout; | |
345 | wire [31:0] gsr3_mask_fx4; | |
346 | wire fx4_gsr4mask_wmr_scanin; | |
347 | wire fx4_gsr4mask_wmr_scanout; | |
348 | wire [31:0] gsr4_mask_fx4; | |
349 | wire fx4_gsr5mask_wmr_scanin; | |
350 | wire fx4_gsr5mask_wmr_scanout; | |
351 | wire [31:0] gsr5_mask_fx4; | |
352 | wire fx4_gsr6mask_wmr_scanin; | |
353 | wire fx4_gsr6mask_wmr_scanout; | |
354 | wire [31:0] gsr6_mask_fx4; | |
355 | wire fx4_gsr7mask_wmr_scanin; | |
356 | wire fx4_gsr7mask_wmr_scanout; | |
357 | wire [31:0] gsr7_mask_fx4; | |
358 | wire [31:0] gsr_mask_fx4; | |
359 | wire tcu_muxtest_a_rep0; | |
360 | wire [30:0] gsr_asr_mask_fx4; | |
361 | wire pack_b01_gt255_fx4_; | |
362 | wire pack_b01_lt32768_fx4_; | |
363 | wire pack_b23_gt255_fx4_; | |
364 | wire pack_b45_gt255_fx4_; | |
365 | wire pack_b45_lt32768_fx4_; | |
366 | wire pack_b67_gt255_fx4_; | |
367 | wire pack_b01_gt255_fx4; | |
368 | wire pack_b01_lt32768_fx4; | |
369 | wire pack_b23_gt255_fx4; | |
370 | wire pack_b45_gt255_fx4; | |
371 | wire pack_b45_lt32768_fx4; | |
372 | wire pack_b67_gt255_fx4; | |
373 | wire rs2_fx4_b63_; | |
374 | wire rs2_fx4_b31_; | |
375 | wire packfix_hi_lt32768_fx4; | |
376 | wire packfix_lo_lt32768_fx4; | |
377 | wire packfix_hi_gt32767_fx4; | |
378 | wire packfix_lo_gt32767_fx4; | |
379 | wire pack_b3_sign_fx4; | |
380 | wire pack_b3_gt255_fx4; | |
381 | wire [63:32] pack_result_fx4; | |
382 | wire [7:0] pack_result_fx4_b7_0; | |
383 | wire pdist_42csa_cout2_fx4; | |
384 | wire [9:1] pdist_42csa_carry2_fx4; | |
385 | wire [8:0] pdist_42csa_sum2_fx4; | |
386 | wire [10:1] pdist_32csa_carry_fx4; | |
387 | wire [9:0] pdist_32csa_sum_fx4; | |
388 | wire q_pdist_rs3_fx3_b11; | |
389 | wire [63:0] pdist_sum_fx4; | |
390 | wire pdist_cout_fx4; | |
391 | wire [12:0] pdist_inc_unused; | |
392 | wire fx5_res_scanin; | |
393 | wire fx5_res_scanout; | |
394 | wire in_rng1_1f_scanin; | |
395 | wire in_rng1_1f_scanout; | |
396 | wire [63:0] in_rngl_cdbus_1f; | |
397 | wire in_rng0_1f_scanin; | |
398 | wire in_rng0_1f_scanout; | |
399 | wire in_rng1_2f_scanin; | |
400 | wire in_rng1_2f_scanout; | |
401 | wire [63:0] in_rngl_cdbus_2f; | |
402 | wire in_rng0_2f_scanin; | |
403 | wire in_rng0_2f_scanout; | |
404 | wire in_rng1_3f_scanin; | |
405 | wire in_rng1_3f_scanout; | |
406 | wire in_rng0_3f_scanin; | |
407 | wire in_rng0_3f_scanout; | |
408 | wire tcu_muxtest_b_rep0; | |
409 | wire tcu_muxtest_c_rep0; | |
410 | ||
411 | ||
412 | ||
413 | // ---------------------------------------------------------------------------- | |
414 | // Interface with FAD | |
415 | // ---------------------------------------------------------------------------- | |
416 | ||
417 | input [63:0] fad_rs1_fmt_fx1; // rs1 formatted | |
418 | input [63:0] fad_rs2_fmt_fx1; // rs2 formatted | |
419 | ||
420 | output [62:0] fgd_rngl_cdbus_3f; | |
421 | ||
422 | // ---------------------------------------------------------------------------- | |
423 | // Interface with FPF | |
424 | // ---------------------------------------------------------------------------- | |
425 | ||
426 | output [63:0] fgd_result_fx5; // FGX result | |
427 | ||
428 | // ---------------------------------------------------------------------------- | |
429 | // Interface with FAC | |
430 | // ---------------------------------------------------------------------------- | |
431 | ||
432 | input vis_clken; // vis clken | |
433 | input coreon_clken; // controls all "free running" flops | |
434 | ||
435 | input fac_fgx_abs_fx2; // FABS | |
436 | input fac_fgx_neg_fx2; // FNEG | |
437 | input fac_fgx_logical_fx2; // logical instructions | |
438 | input fac_fgx_expand_fx2; // FEXPAND | |
439 | input fac_fgx_merge_fx2; // FPMERGE | |
440 | input fac_fgx_align_fx2; // FALIGNDATA | |
441 | input fac_fgx_shuffle_fx2; // BSHUFFLE | |
442 | input fac_fgx_pack16_fx2; // FPACK16 | |
443 | input fac_fgx_pack32_fx2; // FPACK32 | |
444 | input fac_fgx_packfix_fx2; // FPACKFIX | |
445 | input fac_fgx_pdist_fx1; // PDIST | |
446 | input fac_fgx_popc_fx2; // POPC | |
447 | ||
448 | input fac_fgx_pack_sel_fx2; // FPACK16,FPACK32,FPACKFIX | |
449 | ||
450 | input [4:1] fac_opf_fx2; // instr opf field | |
451 | input [2:0] fac_gsr_asr_tid_fx2; | |
452 | input [2:0] fac_tid_fx2; | |
453 | ||
454 | input [2:0] fac_rng_fprs; // ASR FPRS read data | |
455 | input fac_rng_rd_fprs_4f; // ASR FPRS read | |
456 | input fac_rng_rd_gsr_4f; // ASR GSR read | |
457 | input [13:0] fec_r1_ecc_fx1; // ASI FRF ECC read data | |
458 | input fac_rng_rd_ecc_4f; // ASI FRF ECC read | |
459 | input fac_rng_rd_or_wr_3f; // ASR/ASI GSR/FPRS/FRF_ECC rd or wr decoded | |
460 | ||
461 | input asi_clken; // asi clken: controls ASI ring stage flops | |
462 | ||
463 | output fgd_gsr_asr_mask_fx4_b31; | |
464 | ||
465 | // ---------------------------------------------------------------------------- | |
466 | // Interface with FPC | |
467 | // ---------------------------------------------------------------------------- | |
468 | ||
469 | input [1:0] fpc_gsr0_mask_sel_fx3; | |
470 | input [1:0] fpc_gsr1_mask_sel_fx3; | |
471 | input [1:0] fpc_gsr2_mask_sel_fx3; | |
472 | input [1:0] fpc_gsr3_mask_sel_fx3; | |
473 | input [1:0] fpc_gsr4_mask_sel_fx3; | |
474 | input [1:0] fpc_gsr5_mask_sel_fx3; | |
475 | input [1:0] fpc_gsr6_mask_sel_fx3; | |
476 | input [1:0] fpc_gsr7_mask_sel_fx3; | |
477 | input [4:0] fpc_gsr_scale_fx4; | |
478 | input [2:0] fpc_gsr_align_fx4; | |
479 | input [10:0] fpc_gsr_asr_11bits_fx4; | |
480 | ||
481 | // ---------------------------------------------------------------------------- | |
482 | // Interface with EXU | |
483 | // ---------------------------------------------------------------------------- | |
484 | ||
485 | input [31:0] exu_fgu_gsr_m; // GSR.align data: | |
486 | // [31:3] = don't care | |
487 | // [2:0] = GSR.align | |
488 | // GSR.mask data: | |
489 | // [31:0] = GSR.mask | |
490 | ||
491 | // ---------------------------------------------------------------------------- | |
492 | // Global Signals | |
493 | // ---------------------------------------------------------------------------- | |
494 | ||
495 | input l2clk; // clock input | |
496 | input scan_in; | |
497 | input spc_aclk_wmr; | |
498 | input wmr_scan_in; | |
499 | input lb_scan_en_wmr; | |
500 | input tcu_pce_ov; // scan signals | |
501 | input spc_aclk; | |
502 | input spc_bclk; | |
503 | input tcu_dectest; | |
504 | input tcu_muxtest; | |
505 | input tcu_scan_en; | |
506 | output scan_out; | |
507 | output wmr_scan_out; | |
508 | input [63:0] in_rngl_cdbus; // ASI local ring | |
509 | ||
510 | ||
511 | // scan renames | |
512 | assign stop = 1'b0; | |
513 | assign test = tcu_dectest; | |
514 | // end scan | |
515 | ||
516 | fgu_fgd_dp_buff_macro__dbuff_32x__rep_1__width_4 test_rep0 ( | |
517 | .din ({tcu_scan_en, tcu_pce_ov, spc_aclk, spc_bclk}), | |
518 | .dout({se, pce_ov, siclk, soclk }) | |
519 | ); | |
520 | ||
521 | ||
522 | // ---------------------------------------------------------------------------- | |
523 | // FX2 stage | |
524 | // ---------------------------------------------------------------------------- | |
525 | ||
526 | fgu_fgd_dp_msff_macro__width_64 fx2_rs1 ( | |
527 | .scan_in(fx2_rs1_scanin), | |
528 | .scan_out(fx2_rs1_scanout), | |
529 | .clk (l2clk), | |
530 | .en (vis_clken), | |
531 | .din (fad_rs1_fmt_fx1[63:0]), | |
532 | .dout( rs1_fx2[63:0]), | |
533 | .se(se), | |
534 | .siclk(siclk), | |
535 | .soclk(soclk), | |
536 | .pce_ov(pce_ov), | |
537 | .stop(stop) | |
538 | ); | |
539 | ||
540 | fgu_fgd_dp_msff_macro__width_64 fx2_rs2 ( | |
541 | .scan_in(fx2_rs2_scanin), | |
542 | .scan_out(fx2_rs2_scanout), | |
543 | .clk (l2clk), | |
544 | .en (vis_clken), | |
545 | .din (fad_rs2_fmt_fx1[63:0]), | |
546 | .dout( rs2_fx2[63:0]), | |
547 | .se(se), | |
548 | .siclk(siclk), | |
549 | .soclk(soclk), | |
550 | .pce_ov(pce_ov), | |
551 | .stop(stop) | |
552 | ); | |
553 | ||
554 | fgu_fgd_dp_msff_macro__stack_32l__width_32 fx2_gsr ( | |
555 | .scan_in(fx2_gsr_scanin), | |
556 | .scan_out(fx2_gsr_scanout), | |
557 | .clk (l2clk), | |
558 | .en (vis_clken), | |
559 | .din (exu_fgu_gsr_m[31:0] ), | |
560 | .dout( gsr_fx2[31:0]), | |
561 | .se(se), | |
562 | .siclk(siclk), | |
563 | .soclk(soclk), | |
564 | .pce_ov(pce_ov), | |
565 | .stop(stop) | |
566 | ); | |
567 | ||
568 | fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 pdist_rs3 ( | |
569 | .din0(rs2_fx2[11:0]), | |
570 | .din1(12'b0), | |
571 | .sel0(fgx_pdist_fx3), // since rs3 data skips a stage, selects skip a stage | |
572 | .sel1(fgx_popc_fx3), | |
573 | .dout(pdist_rs3_fx2[11:0]) | |
574 | ); | |
575 | ||
576 | // ------------------------------------ | |
577 | // uniquie POPC frontend (fx2) | |
578 | // ------------------------------------ | |
579 | ||
580 | //------ | |
581 | // byte7 | |
582 | //------ | |
583 | ||
584 | fgu_fgd_dp_csa42_macro__width_1 popc_b7a ( | |
585 | .i0 (rs2_fx2[0]), | |
586 | .i1 (rs2_fx2[1]), | |
587 | .i2 (rs2_fx2[2]), | |
588 | .i3 (rs2_fx2[3]), | |
589 | .cin (1'b0 ), | |
590 | .cout (popc_byte7a_cout_fx2 ), | |
591 | .carry(popc_byte7a_carry_fx2), | |
592 | .sum (popc_byte7a_sum_fx2 ) | |
593 | ); | |
594 | ||
595 | fgu_fgd_dp_csa42_macro__width_1 popc_b7b ( | |
596 | .i0 (rs2_fx2[4]), | |
597 | .i1 (rs2_fx2[5]), | |
598 | .i2 (rs2_fx2[6]), | |
599 | .i3 (rs2_fx2[7]), | |
600 | .cin (1'b0 ), | |
601 | .cout (popc_byte7b_cout_fx2 ), | |
602 | .carry(popc_byte7b_carry_fx2), | |
603 | .sum (popc_byte7b_sum_fx2 ) | |
604 | ); | |
605 | ||
606 | fgu_fgd_dp_csa42_macro__width_1 popc_b7c ( | |
607 | .i0 (popc_byte7a_cout_fx2 ), | |
608 | .i1 (popc_byte7a_carry_fx2), | |
609 | .i2 (popc_byte7b_cout_fx2 ), | |
610 | .i3 (popc_byte7b_carry_fx2), | |
611 | .cin (1'b0 ), | |
612 | .cout (popc_byte7c_cout_fx2 ), | |
613 | .carry(popc_byte7c_carry_fx2), | |
614 | .sum (popc_byte7c_sum_fx2 ) | |
615 | ); | |
616 | ||
617 | fgu_fgd_dp_cla_macro__width_4 popc_b7 ( // 0in maximum -val 8 -var {popc_b7_unused, popc_byte7_sum_fx2[3:0]} | |
618 | .din0({1'b0, popc_byte7c_carry_fx2, popc_byte7c_sum_fx2, popc_byte7a_sum_fx2}), | |
619 | .din1({1'b0, popc_byte7c_cout_fx2 , 1'b0 , popc_byte7b_sum_fx2}), | |
620 | .cin (1'b0), | |
621 | .dout(popc_byte7_sum_fx2[3:0]), | |
622 | .cout(popc_b7_unused ) | |
623 | ); | |
624 | ||
625 | //------ | |
626 | // byte6 | |
627 | //------ | |
628 | ||
629 | fgu_fgd_dp_csa42_macro__width_1 popc_b6a ( | |
630 | .i0 (rs2_fx2[8]), | |
631 | .i1 (rs2_fx2[9]), | |
632 | .i2 (rs2_fx2[10]), | |
633 | .i3 (rs2_fx2[11]), | |
634 | .cin (1'b0 ), | |
635 | .cout (popc_byte6a_cout_fx2 ), | |
636 | .carry(popc_byte6a_carry_fx2), | |
637 | .sum (popc_byte6a_sum_fx2 ) | |
638 | ); | |
639 | ||
640 | fgu_fgd_dp_csa42_macro__width_1 popc_b6b ( | |
641 | .i0 (rs2_fx2[12]), | |
642 | .i1 (rs2_fx2[13]), | |
643 | .i2 (rs2_fx2[14]), | |
644 | .i3 (rs2_fx2[15]), | |
645 | .cin (1'b0 ), | |
646 | .cout (popc_byte6b_cout_fx2 ), | |
647 | .carry(popc_byte6b_carry_fx2), | |
648 | .sum (popc_byte6b_sum_fx2 ) | |
649 | ); | |
650 | ||
651 | fgu_fgd_dp_csa42_macro__width_1 popc_b6c ( | |
652 | .i0 (popc_byte6a_cout_fx2 ), | |
653 | .i1 (popc_byte6a_carry_fx2), | |
654 | .i2 (popc_byte6b_cout_fx2 ), | |
655 | .i3 (popc_byte6b_carry_fx2), | |
656 | .cin (1'b0 ), | |
657 | .cout (popc_byte6c_cout_fx2 ), | |
658 | .carry(popc_byte6c_carry_fx2), | |
659 | .sum (popc_byte6c_sum_fx2 ) | |
660 | ); | |
661 | ||
662 | fgu_fgd_dp_cla_macro__width_4 popc_b6 ( // 0in maximum -val 8 -var {popc_b6_unused, popc_byte6_sum_fx2[3:0]} | |
663 | .din0({1'b0, popc_byte6c_carry_fx2, popc_byte6c_sum_fx2, popc_byte6a_sum_fx2}), | |
664 | .din1({1'b0, popc_byte6c_cout_fx2 , 1'b0 , popc_byte6b_sum_fx2}), | |
665 | .cin (1'b0), | |
666 | .dout(popc_byte6_sum_fx2[3:0]), | |
667 | .cout(popc_b6_unused ) | |
668 | ); | |
669 | ||
670 | //------ | |
671 | // byte5 | |
672 | //------ | |
673 | ||
674 | fgu_fgd_dp_csa42_macro__width_1 popc_b5a ( | |
675 | .i0 (rs2_fx2[16]), | |
676 | .i1 (rs2_fx2[17]), | |
677 | .i2 (rs2_fx2[18]), | |
678 | .i3 (rs2_fx2[19]), | |
679 | .cin (1'b0 ), | |
680 | .cout (popc_byte5a_cout_fx2 ), | |
681 | .carry(popc_byte5a_carry_fx2), | |
682 | .sum (popc_byte5a_sum_fx2 ) | |
683 | ); | |
684 | ||
685 | fgu_fgd_dp_csa42_macro__width_1 popc_b5b ( | |
686 | .i0 (rs2_fx2[20]), | |
687 | .i1 (rs2_fx2[21]), | |
688 | .i2 (rs2_fx2[22]), | |
689 | .i3 (rs2_fx2[23]), | |
690 | .cin (1'b0 ), | |
691 | .cout (popc_byte5b_cout_fx2 ), | |
692 | .carry(popc_byte5b_carry_fx2), | |
693 | .sum (popc_byte5b_sum_fx2 ) | |
694 | ); | |
695 | ||
696 | fgu_fgd_dp_csa42_macro__width_1 popc_b5c ( | |
697 | .i0 (popc_byte5a_cout_fx2 ), | |
698 | .i1 (popc_byte5a_carry_fx2), | |
699 | .i2 (popc_byte5b_cout_fx2 ), | |
700 | .i3 (popc_byte5b_carry_fx2), | |
701 | .cin (1'b0 ), | |
702 | .cout (popc_byte5c_cout_fx2 ), | |
703 | .carry(popc_byte5c_carry_fx2), | |
704 | .sum (popc_byte5c_sum_fx2 ) | |
705 | ); | |
706 | ||
707 | fgu_fgd_dp_cla_macro__width_4 popc_b5 ( // 0in maximum -val 8 -var {popc_b5_unused, popc_byte5_sum_fx2[3:0]} | |
708 | .din0({1'b0, popc_byte5c_carry_fx2, popc_byte5c_sum_fx2, popc_byte5a_sum_fx2}), | |
709 | .din1({1'b0, popc_byte5c_cout_fx2 , 1'b0 , popc_byte5b_sum_fx2}), | |
710 | .cin (1'b0), | |
711 | .dout(popc_byte5_sum_fx2[3:0]), | |
712 | .cout(popc_b5_unused ) | |
713 | ); | |
714 | ||
715 | //------ | |
716 | // byte4 | |
717 | //------ | |
718 | ||
719 | fgu_fgd_dp_csa42_macro__width_1 popc_b4a ( | |
720 | .i0 (rs2_fx2[24]), | |
721 | .i1 (rs2_fx2[25]), | |
722 | .i2 (rs2_fx2[26]), | |
723 | .i3 (rs2_fx2[27]), | |
724 | .cin (1'b0 ), | |
725 | .cout (popc_byte4a_cout_fx2 ), | |
726 | .carry(popc_byte4a_carry_fx2), | |
727 | .sum (popc_byte4a_sum_fx2 ) | |
728 | ); | |
729 | ||
730 | fgu_fgd_dp_csa42_macro__width_1 popc_b4b ( | |
731 | .i0 (rs2_fx2[28]), | |
732 | .i1 (rs2_fx2[29]), | |
733 | .i2 (rs2_fx2[30]), | |
734 | .i3 (rs2_fx2[31]), | |
735 | .cin (1'b0 ), | |
736 | .cout (popc_byte4b_cout_fx2 ), | |
737 | .carry(popc_byte4b_carry_fx2), | |
738 | .sum (popc_byte4b_sum_fx2 ) | |
739 | ); | |
740 | ||
741 | fgu_fgd_dp_csa42_macro__width_1 popc_b4c ( | |
742 | .i0 (popc_byte4a_cout_fx2 ), | |
743 | .i1 (popc_byte4a_carry_fx2), | |
744 | .i2 (popc_byte4b_cout_fx2 ), | |
745 | .i3 (popc_byte4b_carry_fx2), | |
746 | .cin (1'b0 ), | |
747 | .cout (popc_byte4c_cout_fx2 ), | |
748 | .carry(popc_byte4c_carry_fx2), | |
749 | .sum (popc_byte4c_sum_fx2 ) | |
750 | ); | |
751 | ||
752 | fgu_fgd_dp_cla_macro__width_4 popc_b4 ( // 0in maximum -val 8 -var {popc_b4_unused, popc_byte4_sum_fx2[3:0]} | |
753 | .din0({1'b0, popc_byte4c_carry_fx2, popc_byte4c_sum_fx2, popc_byte4a_sum_fx2}), | |
754 | .din1({1'b0, popc_byte4c_cout_fx2 , 1'b0 , popc_byte4b_sum_fx2}), | |
755 | .cin (1'b0), | |
756 | .dout(popc_byte4_sum_fx2[3:0]), | |
757 | .cout(popc_b4_unused ) | |
758 | ); | |
759 | ||
760 | //------ | |
761 | // byte3 | |
762 | //------ | |
763 | ||
764 | fgu_fgd_dp_csa42_macro__width_1 popc_b3a ( | |
765 | .i0 (rs2_fx2[32]), | |
766 | .i1 (rs2_fx2[33]), | |
767 | .i2 (rs2_fx2[34]), | |
768 | .i3 (rs2_fx2[35]), | |
769 | .cin (1'b0 ), | |
770 | .cout (popc_byte3a_cout_fx2 ), | |
771 | .carry(popc_byte3a_carry_fx2), | |
772 | .sum (popc_byte3a_sum_fx2 ) | |
773 | ); | |
774 | ||
775 | fgu_fgd_dp_csa42_macro__width_1 popc_b3b ( | |
776 | .i0 (rs2_fx2[36]), | |
777 | .i1 (rs2_fx2[37]), | |
778 | .i2 (rs2_fx2[38]), | |
779 | .i3 (rs2_fx2[39]), | |
780 | .cin (1'b0 ), | |
781 | .cout (popc_byte3b_cout_fx2 ), | |
782 | .carry(popc_byte3b_carry_fx2), | |
783 | .sum (popc_byte3b_sum_fx2 ) | |
784 | ); | |
785 | ||
786 | fgu_fgd_dp_csa42_macro__width_1 popc_b3c ( | |
787 | .i0 (popc_byte3a_cout_fx2 ), | |
788 | .i1 (popc_byte3a_carry_fx2), | |
789 | .i2 (popc_byte3b_cout_fx2 ), | |
790 | .i3 (popc_byte3b_carry_fx2), | |
791 | .cin (1'b0 ), | |
792 | .cout (popc_byte3c_cout_fx2 ), | |
793 | .carry(popc_byte3c_carry_fx2), | |
794 | .sum (popc_byte3c_sum_fx2 ) | |
795 | ); | |
796 | ||
797 | fgu_fgd_dp_cla_macro__width_4 popc_b3 ( // 0in maximum -val 8 -var {popc_b3_unused, popc_byte3_sum_fx2[3:0]} | |
798 | .din0({1'b0, popc_byte3c_carry_fx2, popc_byte3c_sum_fx2, popc_byte3a_sum_fx2}), | |
799 | .din1({1'b0, popc_byte3c_cout_fx2 , 1'b0 , popc_byte3b_sum_fx2}), | |
800 | .cin (1'b0), | |
801 | .dout(popc_byte3_sum_fx2[3:0]), | |
802 | .cout(popc_b3_unused ) | |
803 | ); | |
804 | ||
805 | //------ | |
806 | // byte2 | |
807 | //------ | |
808 | ||
809 | fgu_fgd_dp_csa42_macro__width_1 popc_b2a ( | |
810 | .i0 (rs2_fx2[40]), | |
811 | .i1 (rs2_fx2[41]), | |
812 | .i2 (rs2_fx2[42]), | |
813 | .i3 (rs2_fx2[43]), | |
814 | .cin (1'b0 ), | |
815 | .cout (popc_byte2a_cout_fx2 ), | |
816 | .carry(popc_byte2a_carry_fx2), | |
817 | .sum (popc_byte2a_sum_fx2 ) | |
818 | ); | |
819 | ||
820 | fgu_fgd_dp_csa42_macro__width_1 popc_b2b ( | |
821 | .i0 (rs2_fx2[44]), | |
822 | .i1 (rs2_fx2[45]), | |
823 | .i2 (rs2_fx2[46]), | |
824 | .i3 (rs2_fx2[47]), | |
825 | .cin (1'b0 ), | |
826 | .cout (popc_byte2b_cout_fx2 ), | |
827 | .carry(popc_byte2b_carry_fx2), | |
828 | .sum (popc_byte2b_sum_fx2 ) | |
829 | ); | |
830 | ||
831 | fgu_fgd_dp_csa42_macro__width_1 popc_b2c ( | |
832 | .i0 (popc_byte2a_cout_fx2 ), | |
833 | .i1 (popc_byte2a_carry_fx2), | |
834 | .i2 (popc_byte2b_cout_fx2 ), | |
835 | .i3 (popc_byte2b_carry_fx2), | |
836 | .cin (1'b0 ), | |
837 | .cout (popc_byte2c_cout_fx2 ), | |
838 | .carry(popc_byte2c_carry_fx2), | |
839 | .sum (popc_byte2c_sum_fx2 ) | |
840 | ); | |
841 | ||
842 | fgu_fgd_dp_cla_macro__width_4 popc_b2 ( // 0in maximum -val 8 -var {popc_b2_unused, popc_byte2_sum_fx2[3:0]} | |
843 | .din0({1'b0, popc_byte2c_carry_fx2, popc_byte2c_sum_fx2, popc_byte2a_sum_fx2}), | |
844 | .din1({1'b0, popc_byte2c_cout_fx2 , 1'b0 , popc_byte2b_sum_fx2}), | |
845 | .cin (1'b0), | |
846 | .dout(popc_byte2_sum_fx2[3:0]), | |
847 | .cout(popc_b2_unused ) | |
848 | ); | |
849 | ||
850 | //------ | |
851 | // byte1 | |
852 | //------ | |
853 | ||
854 | fgu_fgd_dp_csa42_macro__width_1 popc_b1a ( | |
855 | .i0 (rs2_fx2[48]), | |
856 | .i1 (rs2_fx2[49]), | |
857 | .i2 (rs2_fx2[50]), | |
858 | .i3 (rs2_fx2[51]), | |
859 | .cin (1'b0 ), | |
860 | .cout (popc_byte1a_cout_fx2 ), | |
861 | .carry(popc_byte1a_carry_fx2), | |
862 | .sum (popc_byte1a_sum_fx2 ) | |
863 | ); | |
864 | ||
865 | fgu_fgd_dp_csa42_macro__width_1 popc_b1b ( | |
866 | .i0 (rs2_fx2[52]), | |
867 | .i1 (rs2_fx2[53]), | |
868 | .i2 (rs2_fx2[54]), | |
869 | .i3 (rs2_fx2[55]), | |
870 | .cin (1'b0 ), | |
871 | .cout (popc_byte1b_cout_fx2 ), | |
872 | .carry(popc_byte1b_carry_fx2), | |
873 | .sum (popc_byte1b_sum_fx2 ) | |
874 | ); | |
875 | ||
876 | fgu_fgd_dp_csa42_macro__width_1 popc_b1c ( | |
877 | .i0 (popc_byte1a_cout_fx2 ), | |
878 | .i1 (popc_byte1a_carry_fx2), | |
879 | .i2 (popc_byte1b_cout_fx2 ), | |
880 | .i3 (popc_byte1b_carry_fx2), | |
881 | .cin (1'b0 ), | |
882 | .cout (popc_byte1c_cout_fx2 ), | |
883 | .carry(popc_byte1c_carry_fx2), | |
884 | .sum (popc_byte1c_sum_fx2 ) | |
885 | ); | |
886 | ||
887 | fgu_fgd_dp_cla_macro__width_4 popc_b1 ( // 0in maximum -val 8 -var {popc_b1_unused, popc_byte1_sum_fx2[3:0]} | |
888 | .din0({1'b0, popc_byte1c_carry_fx2, popc_byte1c_sum_fx2, popc_byte1a_sum_fx2}), | |
889 | .din1({1'b0, popc_byte1c_cout_fx2 , 1'b0 , popc_byte1b_sum_fx2}), | |
890 | .cin (1'b0), | |
891 | .dout(popc_byte1_sum_fx2[3:0]), | |
892 | .cout(popc_b1_unused ) | |
893 | ); | |
894 | ||
895 | //------ | |
896 | // byte0 | |
897 | //------ | |
898 | ||
899 | fgu_fgd_dp_csa42_macro__width_1 popc_b0a ( | |
900 | .i0 (rs2_fx2[56]), | |
901 | .i1 (rs2_fx2[57]), | |
902 | .i2 (rs2_fx2[58]), | |
903 | .i3 (rs2_fx2[59]), | |
904 | .cin (1'b0 ), | |
905 | .cout (popc_byte0a_cout_fx2 ), | |
906 | .carry(popc_byte0a_carry_fx2), | |
907 | .sum (popc_byte0a_sum_fx2 ) | |
908 | ); | |
909 | ||
910 | fgu_fgd_dp_csa42_macro__width_1 popc_b0b ( | |
911 | .i0 (rs2_fx2[60]), | |
912 | .i1 (rs2_fx2[61]), | |
913 | .i2 (rs2_fx2[62]), | |
914 | .i3 (rs2_fx2[63]), | |
915 | .cin (1'b0 ), | |
916 | .cout (popc_byte0b_cout_fx2 ), | |
917 | .carry(popc_byte0b_carry_fx2), | |
918 | .sum (popc_byte0b_sum_fx2 ) | |
919 | ); | |
920 | ||
921 | fgu_fgd_dp_csa42_macro__width_1 popc_b0c ( | |
922 | .i0 (popc_byte0a_cout_fx2 ), | |
923 | .i1 (popc_byte0a_carry_fx2), | |
924 | .i2 (popc_byte0b_cout_fx2 ), | |
925 | .i3 (popc_byte0b_carry_fx2), | |
926 | .cin (1'b0 ), | |
927 | .cout (popc_byte0c_cout_fx2 ), | |
928 | .carry(popc_byte0c_carry_fx2), | |
929 | .sum (popc_byte0c_sum_fx2 ) | |
930 | ); | |
931 | ||
932 | fgu_fgd_dp_cla_macro__width_4 popc_b0 ( // 0in maximum -val 8 -var {popc_b0_unused, popc_byte0_sum_fx2[3:0]} | |
933 | .din0({1'b0, popc_byte0c_carry_fx2, popc_byte0c_sum_fx2, popc_byte0a_sum_fx2}), | |
934 | .din1({1'b0, popc_byte0c_cout_fx2 , 1'b0 , popc_byte0b_sum_fx2}), | |
935 | .cin (1'b0), | |
936 | .dout(popc_byte0_sum_fx2[3:0]), | |
937 | .cout(popc_b0_unused ) | |
938 | ); | |
939 | ||
940 | ||
941 | // ---------------------------------------------------------------------------- | |
942 | // FX3 stage | |
943 | // ---------------------------------------------------------------------------- | |
944 | ||
945 | fgu_fgd_dp_msff_macro__width_64 fx3_rs1 ( | |
946 | .scan_in(fx3_rs1_scanin), | |
947 | .scan_out(fx3_rs1_scanout), | |
948 | .clk (l2clk), | |
949 | .en (vis_clken), | |
950 | .din (rs1_fx2[63:0]), | |
951 | .dout(rs1_fx3[63:0]), | |
952 | .se(se), | |
953 | .siclk(siclk), | |
954 | .soclk(soclk), | |
955 | .pce_ov(pce_ov), | |
956 | .stop(stop) | |
957 | ); | |
958 | ||
959 | fgu_fgd_dp_buff_macro__width_64 buf_rs1 ( | |
960 | .din (rs1_fx3[63:0] ), | |
961 | .dout(rs10_fx3[63:0]) | |
962 | ); | |
963 | ||
964 | fgu_fgd_dp_msff_macro__minbuff_1__width_64 fx3_rs2 ( | |
965 | .scan_in(fx3_rs2_scanin), | |
966 | .scan_out(fx3_rs2_scanout), | |
967 | .clk (l2clk), | |
968 | .en (vis_clken), | |
969 | .din (rs2_fx2[63:0]), | |
970 | .dout(rs2_fx3[63:0]), | |
971 | .se(se), | |
972 | .siclk(siclk), | |
973 | .soclk(soclk), | |
974 | .pce_ov(pce_ov), | |
975 | .stop(stop) | |
976 | ); | |
977 | ||
978 | fgu_fgd_dp_buff_macro__width_64 buf_rs2 ( | |
979 | .din (rs2_fx3[63:0] ), | |
980 | .dout(rs20_fx3[63:0]) | |
981 | ); | |
982 | ||
983 | fgu_fgd_dp_msff_macro__stack_32l__width_32 fx3_gsr_mask ( | |
984 | .scan_in(fx3_gsr_mask_scanin), | |
985 | .scan_out(fx3_gsr_mask_scanout), | |
986 | .clk (l2clk), | |
987 | .en (vis_clken), | |
988 | .din (gsr_fx2[31:0]), | |
989 | .dout(gsr_mask_fx3[31:0]), | |
990 | .se(se), | |
991 | .siclk(siclk), | |
992 | .soclk(soclk), | |
993 | .pce_ov(pce_ov), | |
994 | .stop(stop) | |
995 | ); | |
996 | ||
997 | fgu_fgd_dp_msff_macro__width_32 fx3_popc ( | |
998 | .scan_in(fx3_popc_scanin), | |
999 | .scan_out(fx3_popc_scanout), | |
1000 | .clk (l2clk), | |
1001 | .en (vis_clken), | |
1002 | .din ({popc_byte0_sum_fx2[3:0], | |
1003 | popc_byte1_sum_fx2[3:0], | |
1004 | popc_byte2_sum_fx2[3:0], | |
1005 | popc_byte3_sum_fx2[3:0], | |
1006 | popc_byte4_sum_fx2[3:0], | |
1007 | popc_byte5_sum_fx2[3:0], | |
1008 | popc_byte6_sum_fx2[3:0], | |
1009 | popc_byte7_sum_fx2[3:0]}), | |
1010 | .dout({popc_byte0_sum_fx3[3:0], | |
1011 | popc_byte1_sum_fx3[3:0], | |
1012 | popc_byte2_sum_fx3[3:0], | |
1013 | popc_byte3_sum_fx3[3:0], | |
1014 | popc_byte4_sum_fx3[3:0], | |
1015 | popc_byte5_sum_fx3[3:0], | |
1016 | popc_byte6_sum_fx3[3:0], | |
1017 | popc_byte7_sum_fx3[3:0]}), | |
1018 | .se(se), | |
1019 | .siclk(siclk), | |
1020 | .soclk(soclk), | |
1021 | .pce_ov(pce_ov), | |
1022 | .stop(stop) | |
1023 | ); | |
1024 | ||
1025 | fgu_fgd_dp_msff_macro__width_33 fx3_ctl ( | |
1026 | .scan_in(fx3_ctl_scanin), | |
1027 | .scan_out(fx3_ctl_scanout), | |
1028 | .clk (l2clk), | |
1029 | .en (vis_clken), | |
1030 | .din ({fac_fgx_abs_fx2, | |
1031 | fac_fgx_neg_fx2, | |
1032 | fac_fgx_logical_fx2, | |
1033 | fac_fgx_expand_fx2, | |
1034 | fac_fgx_merge_fx2, | |
1035 | fac_fgx_align_fx2, | |
1036 | fac_fgx_shuffle_fx2, | |
1037 | fac_fgx_pack16_fx2, | |
1038 | fac_fgx_pack32_fx2, | |
1039 | fac_fgx_packfix_fx2, | |
1040 | fac_fgx_pdist_fx1, | |
1041 | fgx_pdist_fx2, | |
1042 | fac_fgx_popc_fx2, | |
1043 | fac_fgx_pack_sel_fx2, | |
1044 | fac_opf_fx2[4:1], | |
1045 | fgx_pdist_fx3, | |
1046 | fgx_popc_fx3, | |
1047 | fgx_pack_sel_fx3, | |
1048 | pdist_rs3_fx2[11:0]}), | |
1049 | .dout({ fgx_abs_fx3, | |
1050 | fgx_neg_fx3, | |
1051 | fgx_logical_fx3, | |
1052 | fgx_expand_fx3, | |
1053 | fgx_merge_fx3, | |
1054 | fgx_align_fx3, | |
1055 | fgx_shuffle_fx3, | |
1056 | fgx_pack16_fx3, | |
1057 | fgx_pack32_fx3, | |
1058 | fgx_packfix_fx3, | |
1059 | fgx_pdist_fx2, | |
1060 | fgx_pdist_fx3, | |
1061 | fgx_popc_fx3, | |
1062 | fgx_pack_sel_fx3, | |
1063 | opf_fx3[4:1], | |
1064 | fgx_pdist_fx4, | |
1065 | fgx_popc_fx4, | |
1066 | fgx_pack_sel_fx4, | |
1067 | pdist_rs3_fx3[11:0]}), | |
1068 | .se(se), | |
1069 | .siclk(siclk), | |
1070 | .soclk(soclk), | |
1071 | .pce_ov(pce_ov), | |
1072 | .stop(stop) | |
1073 | ); | |
1074 | ||
1075 | ||
1076 | // ---------------------------------------------------------------------------- | |
1077 | // Logical operations: | |
1078 | // | |
1079 | // Instr opf bit: 4321 rs1 rs2 | |
1080 | // -------------------------- sel1 sel0 out | |
1081 | // FZERO, FZEROS 0000 ------------------------- | |
1082 | // FNOR, FNORS 0001 0 0 in0: opf[1] | |
1083 | // FANDNOT2, FANDNOT2S 0010 0 1 in1: opf[3] | |
1084 | // FNOT2, FNOT2S 0011 1 0 in2: opf[2] | |
1085 | // FANDNOT1, FANDNOT1S 0100 1 1 in3: opf[4] | |
1086 | // FNOT1, FNOT1S 0101 | |
1087 | // FXOR, FXORS 0110 | |
1088 | // FNAND, FNANDS 0111 | |
1089 | // FAND, FANDS 1000 | |
1090 | // FXNOR, FXNORS 1001 | |
1091 | // FSRC1, FSRC1S 1010 | |
1092 | // FORNOT2, FORNOT2S 1011 | |
1093 | // FSRC2, FSRC2S 1100 | |
1094 | // FORNOT1, FORNOT1S 1101 | |
1095 | // FOR, FORS 1110 | |
1096 | // FONE, FONES 1111 | |
1097 | // | |
1098 | // Logical instr are implemented with a 4:1 mux structure built from a | |
1099 | // nand-nand (and-or) gate organization. | |
1100 | // | |
1101 | // ---------------------------------------------------------------------------- | |
1102 | ||
1103 | fgu_fgd_dp_buff_macro__width_64 buf_rs101 ( | |
1104 | .din (rs1_fx3[63:0] ), | |
1105 | .dout(rs101_fx3[63:0]) | |
1106 | ); | |
1107 | ||
1108 | fgu_fgd_dp_buff_macro__width_64 buf_rs201 ( | |
1109 | .din (rs2_fx3[63:0] ), | |
1110 | .dout(rs201_fx3[63:0]) | |
1111 | ); | |
1112 | ||
1113 | fgu_fgd_dp_inv_macro__width_64 inv_rs2 ( | |
1114 | .din (rs201_fx3[63:0] ), | |
1115 | .dout(rs201_fx3_[63:0]) | |
1116 | ); | |
1117 | ||
1118 | fgu_fgd_dp_inv_macro__width_64 inv_rs1 ( | |
1119 | .din (rs101_fx3[63:0] ), | |
1120 | .dout(rs101_fx3_[63:0]) | |
1121 | ); | |
1122 | ||
1123 | fgu_fgd_dp_buff_macro__width_8 buf_opf ( | |
1124 | .din ({opf_fx3[4:1], opf_fx3[4:1] }), | |
1125 | .dout({opf1_fx3[4:1],opf0_fx3[4:1]}) | |
1126 | ); | |
1127 | ||
1128 | fgu_fgd_dp_nand_macro__ports_3__width_64 log_00 ( | |
1129 | .din0(rs101_fx3_[63:0]), | |
1130 | .din1(rs201_fx3_[63:0]), | |
1131 | .din2({{32{opf1_fx3[1]}},{32{opf0_fx3[1]}}}), | |
1132 | .dout(logical_int0_fx3[63:0]) | |
1133 | ); | |
1134 | ||
1135 | fgu_fgd_dp_nand_macro__ports_3__width_64 log_01 ( | |
1136 | .din0(rs101_fx3_[63:0]), | |
1137 | .din1(rs201_fx3[63:0] ), | |
1138 | .din2({{32{opf1_fx3[3]}},{32{opf0_fx3[3]}}}), | |
1139 | .dout(logical_int1_fx3[63:0]) | |
1140 | ); | |
1141 | ||
1142 | fgu_fgd_dp_nand_macro__ports_3__width_64 log_02 ( | |
1143 | .din0(rs101_fx3[63:0] ), | |
1144 | .din1(rs201_fx3_[63:0]), | |
1145 | .din2({{32{opf1_fx3[2]}},{32{opf0_fx3[2]}}}), | |
1146 | .dout(logical_int2_fx3[63:0]) | |
1147 | ); | |
1148 | ||
1149 | fgu_fgd_dp_nand_macro__ports_3__width_64 log_03 ( | |
1150 | .din0(rs101_fx3[63:0]), | |
1151 | .din1(rs201_fx3[63:0]), | |
1152 | .din2({{32{opf1_fx3[4]}},{32{opf0_fx3[4]}}}), | |
1153 | .dout(logical_int3_fx3[63:0]) | |
1154 | ); | |
1155 | ||
1156 | fgu_fgd_dp_nand_macro__ports_4__width_64 log_04 ( | |
1157 | .din0(logical_int0_fx3[63:0]), | |
1158 | .din1(logical_int1_fx3[63:0]), | |
1159 | .din2(logical_int2_fx3[63:0]), | |
1160 | .din3(logical_int3_fx3[63:0]), | |
1161 | .dout(logical_result_fx3[63:0]) | |
1162 | ); | |
1163 | ||
1164 | // ------------------------------------ | |
1165 | // bshuffle rs1 and rs2 byte muxes | |
1166 | // ------------------------------------ | |
1167 | ||
1168 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b0 ( | |
1169 | .din0(rs10_fx3[63:56]), | |
1170 | .din1(rs10_fx3[55:48]), | |
1171 | .din2(rs10_fx3[47:40]), | |
1172 | .din3(rs10_fx3[39:32]), | |
1173 | .din4(rs10_fx3[31:24]), | |
1174 | .din5(rs10_fx3[23:16]), | |
1175 | .din6(rs10_fx3[15:8]), | |
1176 | .din7(rs10_fx3[7:0]), | |
1177 | .sel(gsr_mask0_fx4[30:28]), | |
1178 | .dout(rs1_shuf_fx3[63:56]) | |
1179 | ); | |
1180 | ||
1181 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b1 ( | |
1182 | .din0(rs10_fx3[63:56]), | |
1183 | .din1(rs10_fx3[55:48]), | |
1184 | .din2(rs10_fx3[47:40]), | |
1185 | .din3(rs10_fx3[39:32]), | |
1186 | .din4(rs10_fx3[31:24]), | |
1187 | .din5(rs10_fx3[23:16]), | |
1188 | .din6(rs10_fx3[15:8]), | |
1189 | .din7(rs10_fx3[7:0]), | |
1190 | .sel(gsr_mask0_fx4[26:24]), | |
1191 | .dout(rs1_shuf_fx3[55:48]) | |
1192 | ); | |
1193 | ||
1194 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b2 ( | |
1195 | .din0(rs10_fx3[63:56]), | |
1196 | .din1(rs10_fx3[55:48]), | |
1197 | .din2(rs10_fx3[47:40]), | |
1198 | .din3(rs10_fx3[39:32]), | |
1199 | .din4(rs10_fx3[31:24]), | |
1200 | .din5(rs10_fx3[23:16]), | |
1201 | .din6(rs10_fx3[15:8]), | |
1202 | .din7(rs10_fx3[7:0]), | |
1203 | .sel(gsr_mask0_fx4[22:20]), | |
1204 | .dout(rs1_shuf_fx3[47:40]) | |
1205 | ); | |
1206 | ||
1207 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b3 ( | |
1208 | .din0(rs10_fx3[63:56]), | |
1209 | .din1(rs10_fx3[55:48]), | |
1210 | .din2(rs10_fx3[47:40]), | |
1211 | .din3(rs10_fx3[39:32]), | |
1212 | .din4(rs10_fx3[31:24]), | |
1213 | .din5(rs10_fx3[23:16]), | |
1214 | .din6(rs10_fx3[15:8]), | |
1215 | .din7(rs10_fx3[7:0]), | |
1216 | .sel(gsr_mask0_fx4[18:16]), | |
1217 | .dout(rs1_shuf_fx3[39:32]) | |
1218 | ); | |
1219 | ||
1220 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b4 ( | |
1221 | .din0(rs10_fx3[63:56]), | |
1222 | .din1(rs10_fx3[55:48]), | |
1223 | .din2(rs10_fx3[47:40]), | |
1224 | .din3(rs10_fx3[39:32]), | |
1225 | .din4(rs10_fx3[31:24]), | |
1226 | .din5(rs10_fx3[23:16]), | |
1227 | .din6(rs10_fx3[15:8]), | |
1228 | .din7(rs10_fx3[7:0]), | |
1229 | .sel(gsr_mask0_fx4[14:12]), | |
1230 | .dout(rs1_shuf_fx3[31:24]) | |
1231 | ); | |
1232 | ||
1233 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b5 ( | |
1234 | .din0(rs10_fx3[63:56]), | |
1235 | .din1(rs10_fx3[55:48]), | |
1236 | .din2(rs10_fx3[47:40]), | |
1237 | .din3(rs10_fx3[39:32]), | |
1238 | .din4(rs10_fx3[31:24]), | |
1239 | .din5(rs10_fx3[23:16]), | |
1240 | .din6(rs10_fx3[15:8]), | |
1241 | .din7(rs10_fx3[7:0]), | |
1242 | .sel(gsr_mask0_fx4[10:8]), | |
1243 | .dout(rs1_shuf_fx3[23:16]) | |
1244 | ); | |
1245 | ||
1246 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b6 ( | |
1247 | .din0(rs10_fx3[63:56]), | |
1248 | .din1(rs10_fx3[55:48]), | |
1249 | .din2(rs10_fx3[47:40]), | |
1250 | .din3(rs10_fx3[39:32]), | |
1251 | .din4(rs10_fx3[31:24]), | |
1252 | .din5(rs10_fx3[23:16]), | |
1253 | .din6(rs10_fx3[15:8]), | |
1254 | .din7(rs10_fx3[7:0]), | |
1255 | .sel(gsr_mask0_fx4[6:4]), | |
1256 | .dout(rs1_shuf_fx3[15:8]) | |
1257 | ); | |
1258 | ||
1259 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf1_b7 ( | |
1260 | .din0(rs10_fx3[63:56]), | |
1261 | .din1(rs10_fx3[55:48]), | |
1262 | .din2(rs10_fx3[47:40]), | |
1263 | .din3(rs10_fx3[39:32]), | |
1264 | .din4(rs10_fx3[31:24]), | |
1265 | .din5(rs10_fx3[23:16]), | |
1266 | .din6(rs10_fx3[15:8]), | |
1267 | .din7(rs10_fx3[7:0]), | |
1268 | .sel(gsr_mask0_fx4[2:0]), | |
1269 | .dout(rs1_shuf_fx3[7:0]) | |
1270 | ); | |
1271 | ||
1272 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b0 ( | |
1273 | .din0(rs20_fx3[63:56]), | |
1274 | .din1(rs20_fx3[55:48]), | |
1275 | .din2(rs20_fx3[47:40]), | |
1276 | .din3(rs20_fx3[39:32]), | |
1277 | .din4(rs20_fx3[31:24]), | |
1278 | .din5(rs20_fx3[23:16]), | |
1279 | .din6(rs20_fx3[15:8]), | |
1280 | .din7(rs20_fx3[7:0]), | |
1281 | .sel(gsr_mask0_fx4[30:28]), | |
1282 | .dout(rs2_shuf_fx3[63:56]) | |
1283 | ); | |
1284 | ||
1285 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b1 ( | |
1286 | .din0(rs20_fx3[63:56]), | |
1287 | .din1(rs20_fx3[55:48]), | |
1288 | .din2(rs20_fx3[47:40]), | |
1289 | .din3(rs20_fx3[39:32]), | |
1290 | .din4(rs20_fx3[31:24]), | |
1291 | .din5(rs20_fx3[23:16]), | |
1292 | .din6(rs20_fx3[15:8]), | |
1293 | .din7(rs20_fx3[7:0]), | |
1294 | .sel(gsr_mask0_fx4[26:24]), | |
1295 | .dout(rs2_shuf_fx3[55:48]) | |
1296 | ); | |
1297 | ||
1298 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b2 ( | |
1299 | .din0(rs20_fx3[63:56]), | |
1300 | .din1(rs20_fx3[55:48]), | |
1301 | .din2(rs20_fx3[47:40]), | |
1302 | .din3(rs20_fx3[39:32]), | |
1303 | .din4(rs20_fx3[31:24]), | |
1304 | .din5(rs20_fx3[23:16]), | |
1305 | .din6(rs20_fx3[15:8]), | |
1306 | .din7(rs20_fx3[7:0]), | |
1307 | .sel(gsr_mask0_fx4[22:20]), | |
1308 | .dout(rs2_shuf_fx3[47:40]) | |
1309 | ); | |
1310 | ||
1311 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b3 ( | |
1312 | .din0(rs20_fx3[63:56]), | |
1313 | .din1(rs20_fx3[55:48]), | |
1314 | .din2(rs20_fx3[47:40]), | |
1315 | .din3(rs20_fx3[39:32]), | |
1316 | .din4(rs20_fx3[31:24]), | |
1317 | .din5(rs20_fx3[23:16]), | |
1318 | .din6(rs20_fx3[15:8]), | |
1319 | .din7(rs20_fx3[7:0]), | |
1320 | .sel(gsr_mask0_fx4[18:16]), | |
1321 | .dout(rs2_shuf_fx3[39:32]) | |
1322 | ); | |
1323 | ||
1324 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b4 ( | |
1325 | .din0(rs20_fx3[63:56]), | |
1326 | .din1(rs20_fx3[55:48]), | |
1327 | .din2(rs20_fx3[47:40]), | |
1328 | .din3(rs20_fx3[39:32]), | |
1329 | .din4(rs20_fx3[31:24]), | |
1330 | .din5(rs20_fx3[23:16]), | |
1331 | .din6(rs20_fx3[15:8]), | |
1332 | .din7(rs20_fx3[7:0]), | |
1333 | .sel(gsr_mask0_fx4[14:12]), | |
1334 | .dout(rs2_shuf_fx3[31:24]) | |
1335 | ); | |
1336 | ||
1337 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b5 ( | |
1338 | .din0(rs20_fx3[63:56]), | |
1339 | .din1(rs20_fx3[55:48]), | |
1340 | .din2(rs20_fx3[47:40]), | |
1341 | .din3(rs20_fx3[39:32]), | |
1342 | .din4(rs20_fx3[31:24]), | |
1343 | .din5(rs20_fx3[23:16]), | |
1344 | .din6(rs20_fx3[15:8]), | |
1345 | .din7(rs20_fx3[7:0]), | |
1346 | .sel(gsr_mask0_fx4[10:8]), | |
1347 | .dout(rs2_shuf_fx3[23:16]) | |
1348 | ); | |
1349 | ||
1350 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b6 ( | |
1351 | .din0(rs20_fx3[63:56]), | |
1352 | .din1(rs20_fx3[55:48]), | |
1353 | .din2(rs20_fx3[47:40]), | |
1354 | .din3(rs20_fx3[39:32]), | |
1355 | .din4(rs20_fx3[31:24]), | |
1356 | .din5(rs20_fx3[23:16]), | |
1357 | .din6(rs20_fx3[15:8]), | |
1358 | .din7(rs20_fx3[7:0]), | |
1359 | .sel(gsr_mask0_fx4[6:4]), | |
1360 | .dout(rs2_shuf_fx3[15:8]) | |
1361 | ); | |
1362 | ||
1363 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 shuf2_b7 ( | |
1364 | .din0(rs20_fx3[63:56]), | |
1365 | .din1(rs20_fx3[55:48]), | |
1366 | .din2(rs20_fx3[47:40]), | |
1367 | .din3(rs20_fx3[39:32]), | |
1368 | .din4(rs20_fx3[31:24]), | |
1369 | .din5(rs20_fx3[23:16]), | |
1370 | .din6(rs20_fx3[15:8]), | |
1371 | .din7(rs20_fx3[7:0]), | |
1372 | .sel(gsr_mask0_fx4[2:0]), | |
1373 | .dout(rs2_shuf_fx3[7:0]) | |
1374 | ); | |
1375 | ||
1376 | // ------------------------------------ | |
1377 | // bshuffle result muxes | |
1378 | // ------------------------------------ | |
1379 | ||
1380 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b0 ( | |
1381 | .din0(rs2_shuf_fx3[63:56]), | |
1382 | .din1(rs1_shuf_fx3[63:56]), | |
1383 | .sel0(gsr_mask0_fx4[31]), | |
1384 | .dout(shuf_result_fx3[63:56]) | |
1385 | ); | |
1386 | ||
1387 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b1 ( | |
1388 | .din0(rs2_shuf_fx3[55:48]), | |
1389 | .din1(rs1_shuf_fx3[55:48]), | |
1390 | .sel0(gsr_mask0_fx4[27]), | |
1391 | .dout(shuf_result_fx3[55:48]) | |
1392 | ); | |
1393 | ||
1394 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b2 ( | |
1395 | .din0(rs2_shuf_fx3[47:40]), | |
1396 | .din1(rs1_shuf_fx3[47:40]), | |
1397 | .sel0(gsr_mask0_fx4[23]), | |
1398 | .dout(shuf_result_fx3[47:40]) | |
1399 | ); | |
1400 | ||
1401 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b3 ( | |
1402 | .din0(rs2_shuf_fx3[39:32]), | |
1403 | .din1(rs1_shuf_fx3[39:32]), | |
1404 | .sel0(gsr_mask0_fx4[19]), | |
1405 | .dout(shuf_result_fx3[39:32]) | |
1406 | ); | |
1407 | ||
1408 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b4 ( | |
1409 | .din0(rs2_shuf_fx3[31:24]), | |
1410 | .din1(rs1_shuf_fx3[31:24]), | |
1411 | .sel0(gsr_mask0_fx4[15]), | |
1412 | .dout(shuf_result_fx3[31:24]) | |
1413 | ); | |
1414 | ||
1415 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b5 ( | |
1416 | .din0(rs2_shuf_fx3[23:16]), | |
1417 | .din1(rs1_shuf_fx3[23:16]), | |
1418 | .sel0(gsr_mask0_fx4[11]), | |
1419 | .dout(shuf_result_fx3[23:16]) | |
1420 | ); | |
1421 | ||
1422 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b6 ( | |
1423 | .din0(rs2_shuf_fx3[15:8]), | |
1424 | .din1(rs1_shuf_fx3[15:8]), | |
1425 | .sel0(gsr_mask0_fx4[7]), | |
1426 | .dout(shuf_result_fx3[15:8]) | |
1427 | ); | |
1428 | ||
1429 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 bres_b7 ( | |
1430 | .din0(rs2_shuf_fx3[7:0]), | |
1431 | .din1(rs1_shuf_fx3[7:0]), | |
1432 | .sel0(gsr_mask0_fx4[3]), | |
1433 | .dout(shuf_result_fx3[7:0]) | |
1434 | ); | |
1435 | ||
1436 | // ------------------------------------ | |
1437 | // faligndata mux | |
1438 | // ------------------------------------ | |
1439 | ||
1440 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_64 align ( | |
1441 | .din0(rs10_fx3[63:0]), | |
1442 | .din1({rs10_fx3[55:0],rs20_fx3[63:56]}), | |
1443 | .din2({rs10_fx3[47:0],rs20_fx3[63:48]}), | |
1444 | .din3({rs10_fx3[39:0],rs20_fx3[63:40]}), | |
1445 | .din4({rs10_fx3[31:0],rs20_fx3[63:32]}), | |
1446 | .din5({rs10_fx3[23:0],rs20_fx3[63:24]}), | |
1447 | .din6({rs10_fx3[15:0],rs20_fx3[63:16]}), | |
1448 | .din7({rs10_fx3[7:0], rs20_fx3[63:8] }), | |
1449 | .sel (fpc_gsr_align_fx4[2:0]), | |
1450 | .dout(align_result_fx3[63:0]) | |
1451 | ); | |
1452 | ||
1453 | // ------------------------------------ | |
1454 | // generate sign bit for FNEG, FABS | |
1455 | // ------------------------------------ | |
1456 | ||
1457 | fgu_fgd_dp_xnor_macro__ports_2__width_1 sign63a ( | |
1458 | .din0(fgx_neg_fx3), // negate sign bit | |
1459 | .din1(rs20_fx3[63]), | |
1460 | .dout(rs2_sign63_neg_fx3) | |
1461 | ); | |
1462 | ||
1463 | fgu_fgd_dp_nor_macro__ports_2__width_1 sign63b ( | |
1464 | .din0(fgx_abs_fx3), // clear sign bit | |
1465 | .din1(rs2_sign63_neg_fx3), | |
1466 | .dout(rs2_sign63_res_fx3) | |
1467 | ); | |
1468 | ||
1469 | // ------------------------------------ | |
1470 | // simple instruction intermediate result mux | |
1471 | // ------------------------------------ | |
1472 | ||
1473 | fgu_fgd_dp_msff_macro__mux_aope__ports_6__width_64 fx4_simp ( | |
1474 | .scan_in(fx4_simp_scanin), | |
1475 | .scan_out(fx4_simp_scanout), | |
1476 | .clk (l2clk), | |
1477 | .en (vis_clken), | |
1478 | .din0(logical_result_fx3[63:0]), | |
1479 | .din1({4'b0000,rs201_fx3[63:56],4'b0000, | |
1480 | 4'b0000,rs201_fx3[55:48],4'b0000, | |
1481 | 4'b0000,rs201_fx3[47:40],4'b0000, | |
1482 | 4'b0000,rs201_fx3[39:32],4'b0000 }), | |
1483 | .din2({rs101_fx3[63:56],rs201_fx3[63:56],rs101_fx3[55:48],rs201_fx3[55:48], | |
1484 | rs101_fx3[47:40],rs201_fx3[47:40],rs101_fx3[39:32],rs201_fx3[39:32] }), | |
1485 | .din3(align_result_fx3[63:0]), | |
1486 | .din4(shuf_result_fx3[63:0]), | |
1487 | .din5({rs2_sign63_res_fx3,rs201_fx3[62:0]}), | |
1488 | .sel0(fgx_logical_fx3), | |
1489 | .sel1(fgx_expand_fx3), | |
1490 | .sel2(fgx_merge_fx3), | |
1491 | .sel3(fgx_align_fx3), | |
1492 | .sel4(fgx_shuffle_fx3), | |
1493 | // else: FMOV(uncond/cond), FABS, FNEG | |
1494 | .dout(simp_result_fx4[63:0]), | |
1495 | .se(se), | |
1496 | .siclk(siclk), | |
1497 | .soclk(soclk), | |
1498 | .pce_ov(pce_ov), | |
1499 | .stop(stop) | |
1500 | ); | |
1501 | ||
1502 | // ------------------------------------ | |
1503 | // fpack left shifter (data result) | |
1504 | // partitioned into four 16b shifters: [63:48],[47:32],[31:16],[15:00] | |
1505 | // FPACK{16,32},FPACKFIX | |
1506 | // ------------------------------------ | |
1507 | ||
1508 | fgu_fgd_dp_inv_macro__width_1 ipack16 ( | |
1509 | .din (fgx_pack16_fx3 ), | |
1510 | .dout(fgx_pack16_fx3_) | |
1511 | ); | |
1512 | ||
1513 | fgu_fgd_dp_nand_macro__ports_2__width_1 gsr4 ( | |
1514 | .din0(fpc_gsr_scale_fx4[4]), | |
1515 | .din1(fgx_pack16_fx3_), // ignore gsr_scale_fx4[4] if FPACK16 | |
1516 | .dout(sh16_sel_fx3) | |
1517 | ); | |
1518 | ||
1519 | // ------------------------------------ | |
1520 | // fpack data result | |
1521 | // bits [63:32] | |
1522 | // ------------------------------------ | |
1523 | ||
1524 | fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 pack_16_d3d2 ( | |
1525 | .din0( rs201_fx3[63:32] ), | |
1526 | .din1({rs201_fx3[47:32], 16'b0}), | |
1527 | .sel0(sh16_sel_fx3), // shift 0,16 bits | |
1528 | .dout(shift16_fx3[63:32]) | |
1529 | ); | |
1530 | ||
1531 | fgu_fgd_dp_and_macro__ports_2__width_12 gate16d3 ( | |
1532 | .din0(shift16_fx3[47:36]), | |
1533 | .din1({12{fgx_pack16_fx3_}}), | |
1534 | .dout(gate16_fx3[23:12]) | |
1535 | ); | |
1536 | ||
1537 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d3 ( | |
1538 | .din0( shift16_fx3[63:48] ), | |
1539 | .din1({shift16_fx3[59:48], gate16_fx3[23:20]}), | |
1540 | .din2({shift16_fx3[55:48], gate16_fx3[23:16]}), | |
1541 | .din3({shift16_fx3[51:48], gate16_fx3[23:12]}), | |
1542 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1543 | .dout(shift04_fx3[63:48]) | |
1544 | ); | |
1545 | ||
1546 | fgu_fgd_dp_and_macro__ports_2__width_3 gate04d3 ( | |
1547 | .din0(shift04_fx3[47:45]), | |
1548 | .din1({3{fgx_pack16_fx3_}}), | |
1549 | .dout(gate04_fx3[5:3]) | |
1550 | ); | |
1551 | ||
1552 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d3 ( | |
1553 | .din0( shift04_fx3[63:48] ), | |
1554 | .din1({shift04_fx3[62:48], gate04_fx3[5:5]}), | |
1555 | .din2({shift04_fx3[61:48], gate04_fx3[5:4]}), | |
1556 | .din3({shift04_fx3[60:48], gate04_fx3[5:3]}), | |
1557 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1558 | .dout(shift01_fx3[63:48]) | |
1559 | ); | |
1560 | ||
1561 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d2 ( | |
1562 | .din0( shift16_fx3[47:32] ), | |
1563 | .din1({shift16_fx3[43:32], 4'b0}), | |
1564 | .din2({shift16_fx3[39:32], 8'b0}), | |
1565 | .din3({shift16_fx3[35:32], 12'b0}), | |
1566 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1567 | .dout(shift04_fx3[47:32]) | |
1568 | ); | |
1569 | ||
1570 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d2 ( | |
1571 | .din0( shift04_fx3[47:32] ), | |
1572 | .din1({shift04_fx3[46:32], 1'b0}), | |
1573 | .din2({shift04_fx3[45:32], 2'b0}), | |
1574 | .din3({shift04_fx3[44:32], 3'b0}), | |
1575 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1576 | .dout({shift01_fx3[47:39], pack_01_d2_unused[6:0]}) | |
1577 | ); | |
1578 | ||
1579 | // ------------------------------------ | |
1580 | // fpack data result | |
1581 | // bits [31:00] | |
1582 | // ------------------------------------ | |
1583 | ||
1584 | fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 pack_16_d1d0 ( | |
1585 | .din0( rs201_fx3[31:0] ), | |
1586 | .din1({rs201_fx3[15:0], 16'b0}), | |
1587 | .sel0(sh16_sel_fx3), // shift 0,16 bits | |
1588 | .dout(shift16_fx3[31:0]) | |
1589 | ); | |
1590 | ||
1591 | fgu_fgd_dp_and_macro__ports_2__width_12 gate16d1 ( | |
1592 | .din0(shift16_fx3[15:4]), | |
1593 | .din1({12{fgx_pack16_fx3_}}), | |
1594 | .dout(gate16_fx3[11:0]) | |
1595 | ); | |
1596 | ||
1597 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d1 ( | |
1598 | .din0( shift16_fx3[31:16] ), | |
1599 | .din1({shift16_fx3[27:16], gate16_fx3[11:8]}), | |
1600 | .din2({shift16_fx3[23:16], gate16_fx3[11:4]}), | |
1601 | .din3({shift16_fx3[19:16], gate16_fx3[11:0]}), | |
1602 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1603 | .dout(shift04_fx3[31:16]) | |
1604 | ); | |
1605 | ||
1606 | fgu_fgd_dp_and_macro__ports_2__width_3 gate04d1 ( | |
1607 | .din0(shift04_fx3[15:13]), | |
1608 | .din1({3{fgx_pack16_fx3_}}), | |
1609 | .dout(gate04_fx3[2:0]) | |
1610 | ); | |
1611 | ||
1612 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d1 ( | |
1613 | .din0( shift04_fx3[31:16] ), | |
1614 | .din1({shift04_fx3[30:16], gate04_fx3[2:2]}), | |
1615 | .din2({shift04_fx3[29:16], gate04_fx3[2:1]}), | |
1616 | .din3({shift04_fx3[28:16], gate04_fx3[2:0]}), | |
1617 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1618 | .dout(shift01_fx3[31:16]) | |
1619 | ); | |
1620 | ||
1621 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_04_d0 ( | |
1622 | .din0( shift16_fx3[15:0] ), | |
1623 | .din1({shift16_fx3[11:0], 4'b0}), | |
1624 | .din2({shift16_fx3[7:0], 8'b0}), | |
1625 | .din3({shift16_fx3[3:0], 12'b0}), | |
1626 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1627 | .dout(shift04_fx3[15:0]) | |
1628 | ); | |
1629 | ||
1630 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 pack_01_d0 ( | |
1631 | .din0( shift04_fx3[15:0] ), | |
1632 | .din1({shift04_fx3[14:0], 1'b0}), | |
1633 | .din2({shift04_fx3[13:0], 2'b0}), | |
1634 | .din3({shift04_fx3[12:0], 3'b0}), | |
1635 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1636 | .dout({shift01_fx3[15:7], pack_01_d0_unused[6:0]}) | |
1637 | ); | |
1638 | ||
1639 | // ------------------------------------ | |
1640 | // fpack collection of shifted off (clipping) data | |
1641 | // used to determine if const data output is required | |
1642 | // FPACK{16,32},FPACKFIX | |
1643 | // ------------------------------------ | |
1644 | ||
1645 | // ------------------------------------ | |
1646 | // fpack clipping result | |
1647 | // bits [63:32] | |
1648 | // ------------------------------------ | |
1649 | ||
1650 | fgu_fgd_dp_and_macro__ports_2__width_1 packsign63 ( | |
1651 | .din0(rs201_fx3[63]), | |
1652 | .din1(fgx_packfix_fx3), | |
1653 | .dout(pack_sign63_fx3) | |
1654 | ); | |
1655 | ||
1656 | fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 pack_16_c3c2 ( | |
1657 | .din0({16{pack_sign63_fx3}}), | |
1658 | .din1(rs201_fx3[63:48]), | |
1659 | .sel0(sh16_sel_fx3), // shift 0,16 bits | |
1660 | .dout(clip16_c3_fx3[15:0]) | |
1661 | ); | |
1662 | ||
1663 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 pack_04_c3 ( | |
1664 | .din0({{12{pack_sign63_fx3}}, clip16_c3_fx3[15:0] }), | |
1665 | .din1({{ 8{pack_sign63_fx3}}, clip16_c3_fx3[15:0], shift16_fx3[63:60]}), | |
1666 | .din2({{ 4{pack_sign63_fx3}}, clip16_c3_fx3[15:0], shift16_fx3[63:56]}), | |
1667 | .din3({ clip16_c3_fx3[15:0], shift16_fx3[63:52]}), | |
1668 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1669 | .dout(clip04_c3_fx3[27:0]) | |
1670 | ); | |
1671 | ||
1672 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 pack_01_c3 ( | |
1673 | .din0({{3{pack_sign63_fx3}}, clip04_c3_fx3[27:0] }), | |
1674 | .din1({{2{pack_sign63_fx3}}, clip04_c3_fx3[27:0], shift04_fx3[63:63]}), | |
1675 | .din2({{1{pack_sign63_fx3}}, clip04_c3_fx3[27:0], shift04_fx3[63:62]}), | |
1676 | .din3({ clip04_c3_fx3[27:0], shift04_fx3[63:61]}), | |
1677 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1678 | .dout(clip01_c3_fx3[30:0]) | |
1679 | ); | |
1680 | ||
1681 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 pack_04_c2 ( | |
1682 | .din0( 12'b0 ), | |
1683 | .din1({ 8'b0, shift16_fx3[47:44]}), | |
1684 | .din2({ 4'b0, shift16_fx3[47:40]}), | |
1685 | .din3( shift16_fx3[47:36] ), | |
1686 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1687 | .dout(clip04_c2_fx3[11:0]) | |
1688 | ); | |
1689 | ||
1690 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 pack_01_c2 ( | |
1691 | .din0({3'b0, clip04_c2_fx3[11:0] }), | |
1692 | .din1({2'b0, clip04_c2_fx3[11:0], shift04_fx3[47:47]}), | |
1693 | .din2({1'b0, clip04_c2_fx3[11:0], shift04_fx3[47:46]}), | |
1694 | .din3({ clip04_c2_fx3[11:0], shift04_fx3[47:45]}), | |
1695 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1696 | .dout(clip01_c2_fx3[14:0]) | |
1697 | ); | |
1698 | ||
1699 | // ------------------------------------ | |
1700 | // fpack clipping result | |
1701 | // bits [31:00] | |
1702 | // ------------------------------------ | |
1703 | ||
1704 | fgu_fgd_dp_and_macro__ports_2__width_1 packsign31 ( | |
1705 | .din0(rs201_fx3[31]), | |
1706 | .din1(fgx_packfix_fx3), | |
1707 | .dout(pack_sign31_fx3) | |
1708 | ); | |
1709 | ||
1710 | fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 pack_16_c1c0 ( | |
1711 | .din0({16{pack_sign31_fx3}}), | |
1712 | .din1(rs201_fx3[31:16]), | |
1713 | .sel0(sh16_sel_fx3), // shift 0,16 bits | |
1714 | .dout(clip16_c1_fx3[15:0]) | |
1715 | ); | |
1716 | ||
1717 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 pack_04_c1 ( | |
1718 | .din0({{12{pack_sign31_fx3}}, clip16_c1_fx3[15:0] }), | |
1719 | .din1({{ 8{pack_sign31_fx3}}, clip16_c1_fx3[15:0], shift16_fx3[31:28]}), | |
1720 | .din2({{ 4{pack_sign31_fx3}}, clip16_c1_fx3[15:0], shift16_fx3[31:24]}), | |
1721 | .din3({ clip16_c1_fx3[15:0], shift16_fx3[31:20]}), | |
1722 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1723 | .dout(clip04_c1_fx3[27:0]) | |
1724 | ); | |
1725 | ||
1726 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 pack_01_c1 ( | |
1727 | .din0({{3{pack_sign31_fx3}}, clip04_c1_fx3[27:0] }), | |
1728 | .din1({{2{pack_sign31_fx3}}, clip04_c1_fx3[27:0], shift04_fx3[31:31]}), | |
1729 | .din2({{1{pack_sign31_fx3}}, clip04_c1_fx3[27:0], shift04_fx3[31:30]}), | |
1730 | .din3({ clip04_c1_fx3[27:0], shift04_fx3[31:29]}), | |
1731 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1732 | .dout(clip01_c1_fx3[30:0]) | |
1733 | ); | |
1734 | ||
1735 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 pack_04_c0 ( | |
1736 | .din0( 12'b0 ), | |
1737 | .din1({ 8'b0, shift16_fx3[15:12]}), | |
1738 | .din2({ 4'b0, shift16_fx3[15:8]}), | |
1739 | .din3( shift16_fx3[15:4] ), | |
1740 | .sel (fpc_gsr_scale_fx4[3:2]), // shift 0,4,8,12 bits | |
1741 | .dout(clip04_c0_fx3[11:0]) | |
1742 | ); | |
1743 | ||
1744 | fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 pack_01_c0 ( | |
1745 | .din0({3'b0, clip04_c0_fx3[11:0] }), | |
1746 | .din1({2'b0, clip04_c0_fx3[11:0], shift04_fx3[15:15]}), | |
1747 | .din2({1'b0, clip04_c0_fx3[11:0], shift04_fx3[15:14]}), | |
1748 | .din3({ clip04_c0_fx3[11:0], shift04_fx3[15:13]}), | |
1749 | .sel (fpc_gsr_scale_fx4[1:0]), // shift 0,1,2,3 bits | |
1750 | .dout(clip01_c0_fx3[14:0]) | |
1751 | ); | |
1752 | ||
1753 | // ------------------------------------ | |
1754 | // PDIST,POPC | |
1755 | // ------------------------------------ | |
1756 | ||
1757 | // ------------------------------------ | |
1758 | // uniquie PDIST frontend (fx3) | |
1759 | // subtract (rs1 - rs2) | |
1760 | // ------------------------------------ | |
1761 | ||
1762 | fgu_fgd_dp_cla_macro__width_8 pdist_amb0 ( | |
1763 | .din0(rs101_fx3[63:56] ), | |
1764 | .din1(rs201_fx3_[63:56]), | |
1765 | .cin (1'b1), | |
1766 | .dout(pdist_amb_fx3[63:56]), | |
1767 | .cout(pdist_amb_cout0_fx3) | |
1768 | ); | |
1769 | ||
1770 | fgu_fgd_dp_cla_macro__width_8 pdist_amb1 ( | |
1771 | .din0(rs101_fx3[55:48] ), | |
1772 | .din1(rs201_fx3_[55:48]), | |
1773 | .cin (1'b1), | |
1774 | .dout(pdist_amb_fx3[55:48]), | |
1775 | .cout(pdist_amb_cout1_fx3) | |
1776 | ); | |
1777 | ||
1778 | fgu_fgd_dp_cla_macro__width_8 pdist_amb2 ( | |
1779 | .din0(rs101_fx3[47:40] ), | |
1780 | .din1(rs201_fx3_[47:40]), | |
1781 | .cin (1'b1), | |
1782 | .dout(pdist_amb_fx3[47:40]), | |
1783 | .cout(pdist_amb_cout2_fx3) | |
1784 | ); | |
1785 | ||
1786 | fgu_fgd_dp_cla_macro__width_8 pdist_amb3 ( | |
1787 | .din0(rs101_fx3[39:32] ), | |
1788 | .din1(rs201_fx3_[39:32]), | |
1789 | .cin (1'b1), | |
1790 | .dout(pdist_amb_fx3[39:32]), | |
1791 | .cout(pdist_amb_cout3_fx3) | |
1792 | ); | |
1793 | ||
1794 | fgu_fgd_dp_cla_macro__width_8 pdist_amb4 ( | |
1795 | .din0(rs101_fx3[31:24] ), | |
1796 | .din1(rs201_fx3_[31:24]), | |
1797 | .cin (1'b1), | |
1798 | .dout(pdist_amb_fx3[31:24]), | |
1799 | .cout(pdist_amb_cout4_fx3) | |
1800 | ); | |
1801 | ||
1802 | fgu_fgd_dp_cla_macro__width_8 pdist_amb5 ( | |
1803 | .din0(rs101_fx3[23:16] ), | |
1804 | .din1(rs201_fx3_[23:16]), | |
1805 | .cin (1'b1), | |
1806 | .dout(pdist_amb_fx3[23:16]), | |
1807 | .cout(pdist_amb_cout5_fx3) | |
1808 | ); | |
1809 | ||
1810 | fgu_fgd_dp_cla_macro__width_8 pdist_amb6 ( | |
1811 | .din0(rs101_fx3[15:8] ), | |
1812 | .din1(rs201_fx3_[15:8]), | |
1813 | .cin (1'b1), | |
1814 | .dout(pdist_amb_fx3[15:8]), | |
1815 | .cout(pdist_amb_cout6_fx3) | |
1816 | ); | |
1817 | ||
1818 | fgu_fgd_dp_cla_macro__width_8 pdist_amb7 ( | |
1819 | .din0(rs101_fx3[7:0] ), | |
1820 | .din1(rs201_fx3_[7:0]), | |
1821 | .cin (1'b1), | |
1822 | .dout(pdist_amb_fx3[7:0]), | |
1823 | .cout(pdist_amb_cout7_fx3) | |
1824 | ); | |
1825 | ||
1826 | // ------------------------------------ | |
1827 | // uniquie PDIST frontend (fx3) | |
1828 | // subtract (rs2 - rs1) | |
1829 | // ------------------------------------ | |
1830 | ||
1831 | fgu_fgd_dp_cla_macro__width_8 pdist_bma0 ( | |
1832 | .din0(rs201_fx3[63:56] ), | |
1833 | .din1(rs101_fx3_[63:56]), | |
1834 | .cin (1'b1), | |
1835 | .dout(pdist_bma_fx3[63:56]), | |
1836 | .cout(pdist_bma0_unused) | |
1837 | ); | |
1838 | ||
1839 | fgu_fgd_dp_cla_macro__width_8 pdist_bma1 ( | |
1840 | .din0(rs201_fx3[55:48] ), | |
1841 | .din1(rs101_fx3_[55:48]), | |
1842 | .cin (1'b1), | |
1843 | .dout(pdist_bma_fx3[55:48]), | |
1844 | .cout(pdist_bma1_unused) | |
1845 | ); | |
1846 | ||
1847 | fgu_fgd_dp_cla_macro__width_8 pdist_bma2 ( | |
1848 | .din0(rs201_fx3[47:40] ), | |
1849 | .din1(rs101_fx3_[47:40]), | |
1850 | .cin (1'b1), | |
1851 | .dout(pdist_bma_fx3[47:40]), | |
1852 | .cout(pdist_bma2_unused) | |
1853 | ); | |
1854 | ||
1855 | fgu_fgd_dp_cla_macro__width_8 pdist_bma3 ( | |
1856 | .din0(rs201_fx3[39:32] ), | |
1857 | .din1(rs101_fx3_[39:32]), | |
1858 | .cin (1'b1), | |
1859 | .dout(pdist_bma_fx3[39:32]), | |
1860 | .cout(pdist_bma3_unused) | |
1861 | ); | |
1862 | ||
1863 | fgu_fgd_dp_cla_macro__width_8 pdist_bma4 ( | |
1864 | .din0(rs201_fx3[31:24] ), | |
1865 | .din1(rs101_fx3_[31:24]), | |
1866 | .cin (1'b1), | |
1867 | .dout(pdist_bma_fx3[31:24]), | |
1868 | .cout(pdist_bma4_unused) | |
1869 | ); | |
1870 | ||
1871 | fgu_fgd_dp_cla_macro__width_8 pdist_bma5 ( | |
1872 | .din0(rs201_fx3[23:16] ), | |
1873 | .din1(rs101_fx3_[23:16]), | |
1874 | .cin (1'b1), | |
1875 | .dout(pdist_bma_fx3[23:16]), | |
1876 | .cout(pdist_bma5_unused) | |
1877 | ); | |
1878 | ||
1879 | fgu_fgd_dp_cla_macro__width_8 pdist_bma6 ( | |
1880 | .din0(rs201_fx3[15:8] ), | |
1881 | .din1(rs101_fx3_[15:8]), | |
1882 | .cin (1'b1), | |
1883 | .dout(pdist_bma_fx3[15:8]), | |
1884 | .cout(pdist_bma6_unused) | |
1885 | ); | |
1886 | ||
1887 | fgu_fgd_dp_cla_macro__width_8 pdist_bma7 ( | |
1888 | .din0(rs201_fx3[7:0] ), | |
1889 | .din1(rs101_fx3_[7:0]), | |
1890 | .cin (1'b1), | |
1891 | .dout(pdist_bma_fx3[7:0]), | |
1892 | .cout(pdist_bma7_unused) | |
1893 | ); | |
1894 | ||
1895 | // ------------------------------------ | |
1896 | // select PDIST or POPC | |
1897 | // to proceed to the common backend | |
1898 | // ------------------------------------ | |
1899 | ||
1900 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux0 ( | |
1901 | .din0({4'b0, popc_byte0_sum_fx3[3:0]}), | |
1902 | .din1(pdist_amb_fx3[63:56]), | |
1903 | .din2(pdist_bma_fx3[63:56]), | |
1904 | .sel0(fgx_popc_fx3), | |
1905 | .sel1(pdist_amb_cout0_fx3), | |
1906 | .dout(pdist_mux_fx3[63:56]) | |
1907 | ); | |
1908 | ||
1909 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux1 ( | |
1910 | .din0({4'b0, popc_byte1_sum_fx3[3:0]}), | |
1911 | .din1(pdist_amb_fx3[55:48]), | |
1912 | .din2(pdist_bma_fx3[55:48]), | |
1913 | .sel0(fgx_popc_fx3), | |
1914 | .sel1(pdist_amb_cout1_fx3), | |
1915 | .dout(pdist_mux_fx3[55:48]) | |
1916 | ); | |
1917 | ||
1918 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux2 ( | |
1919 | .din0({4'b0, popc_byte2_sum_fx3[3:0]}), | |
1920 | .din1(pdist_amb_fx3[47:40]), | |
1921 | .din2(pdist_bma_fx3[47:40]), | |
1922 | .sel0(fgx_popc_fx3), | |
1923 | .sel1(pdist_amb_cout2_fx3), | |
1924 | .dout(pdist_mux_fx3[47:40]) | |
1925 | ); | |
1926 | ||
1927 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux3 ( | |
1928 | .din0({4'b0, popc_byte3_sum_fx3[3:0]}), | |
1929 | .din1(pdist_amb_fx3[39:32]), | |
1930 | .din2(pdist_bma_fx3[39:32]), | |
1931 | .sel0(fgx_popc_fx3), | |
1932 | .sel1(pdist_amb_cout3_fx3), | |
1933 | .dout(pdist_mux_fx3[39:32]) | |
1934 | ); | |
1935 | ||
1936 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux4 ( | |
1937 | .din0({4'b0, popc_byte4_sum_fx3[3:0]}), | |
1938 | .din1(pdist_amb_fx3[31:24]), | |
1939 | .din2(pdist_bma_fx3[31:24]), | |
1940 | .sel0(fgx_popc_fx3), | |
1941 | .sel1(pdist_amb_cout4_fx3), | |
1942 | .dout(pdist_mux_fx3[31:24]) | |
1943 | ); | |
1944 | ||
1945 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux5 ( | |
1946 | .din0({4'b0, popc_byte5_sum_fx3[3:0]}), | |
1947 | .din1(pdist_amb_fx3[23:16]), | |
1948 | .din2(pdist_bma_fx3[23:16]), | |
1949 | .sel0(fgx_popc_fx3), | |
1950 | .sel1(pdist_amb_cout5_fx3), | |
1951 | .dout(pdist_mux_fx3[23:16]) | |
1952 | ); | |
1953 | ||
1954 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux6 ( | |
1955 | .din0({4'b0, popc_byte6_sum_fx3[3:0]}), | |
1956 | .din1(pdist_amb_fx3[15:8]), | |
1957 | .din2(pdist_bma_fx3[15:8]), | |
1958 | .sel0(fgx_popc_fx3), | |
1959 | .sel1(pdist_amb_cout6_fx3), | |
1960 | .dout(pdist_mux_fx3[15:8]) | |
1961 | ); | |
1962 | ||
1963 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pdist_mux7 ( | |
1964 | .din0({4'b0, popc_byte7_sum_fx3[3:0]}), | |
1965 | .din1(pdist_amb_fx3[7:0]), | |
1966 | .din2(pdist_bma_fx3[7:0]), | |
1967 | .sel0(fgx_popc_fx3), | |
1968 | .sel1(pdist_amb_cout7_fx3), | |
1969 | .dout(pdist_mux_fx3[7:0]) | |
1970 | ); | |
1971 | ||
1972 | // ------------------------------------ | |
1973 | // common PDIST,POPC backend (fx3) | |
1974 | // begin compression of 8 8-bit values | |
1975 | // ------------------------------------ | |
1976 | ||
1977 | fgu_fgd_dp_csa42_macro__width_8 pdist_42csa_0 ( | |
1978 | .i0 (pdist_mux_fx3[7:0]), | |
1979 | .i1 (pdist_mux_fx3[15:8]), | |
1980 | .i2 (pdist_mux_fx3[23:16]), | |
1981 | .i3 (pdist_mux_fx3[31:24]), | |
1982 | .cin (1'b0 ), | |
1983 | .cout (pdist_42csa_cout0_fx3 ), | |
1984 | .carry(pdist_42csa_carry0_fx3[8:1]), | |
1985 | .sum (pdist_42csa_sum0_fx3[7:0] ) | |
1986 | ); | |
1987 | ||
1988 | fgu_fgd_dp_csa42_macro__width_8 pdist_42csa_1 ( | |
1989 | .i0 (pdist_mux_fx3[39:32]), | |
1990 | .i1 (pdist_mux_fx3[47:40]), | |
1991 | .i2 (pdist_mux_fx3[55:48]), | |
1992 | .i3 (pdist_mux_fx3[63:56]), | |
1993 | .cin (1'b0 ), | |
1994 | .cout (pdist_42csa_cout1_fx3 ), | |
1995 | .carry(pdist_42csa_carry1_fx3[8:1]), | |
1996 | .sum (pdist_42csa_sum1_fx3[7:0] ) | |
1997 | ); | |
1998 | ||
1999 | // ---------------------------------------------------------------------------- | |
2000 | // FX4 stage | |
2001 | // ---------------------------------------------------------------------------- | |
2002 | ||
2003 | fgu_fgd_dp_msff_macro__width_48 fx4_rs1 ( | |
2004 | .scan_in(fx4_rs1_scanin), | |
2005 | .scan_out(fx4_rs1_scanout), | |
2006 | .clk (l2clk), | |
2007 | .en (vis_clken), | |
2008 | .din ({rs101_fx3[55:32], rs101_fx3[23:0]}), | |
2009 | .dout({rs1_fx4[55:32], rs1_fx4[23:0] }), | |
2010 | .se(se), | |
2011 | .siclk(siclk), | |
2012 | .soclk(soclk), | |
2013 | .pce_ov(pce_ov), | |
2014 | .stop(stop) | |
2015 | ); | |
2016 | ||
2017 | fgu_fgd_dp_msff_macro__width_50 fx4_shift ( | |
2018 | .scan_in(fx4_shift_scanin), | |
2019 | .scan_out(fx4_shift_scanout), | |
2020 | .clk (l2clk), | |
2021 | .en (vis_clken), | |
2022 | .din ({shift01_fx3[63:39], shift01_fx3[31:7]}), | |
2023 | .dout({shift01_fx4[63:39], shift01_fx4[31:7]}), | |
2024 | .se(se), | |
2025 | .siclk(siclk), | |
2026 | .soclk(soclk), | |
2027 | .pce_ov(pce_ov), | |
2028 | .stop(stop) | |
2029 | ); | |
2030 | ||
2031 | fgu_fgd_dp_msff_macro__width_62 fx4_clipa ( | |
2032 | .scan_in(fx4_clipa_scanin), | |
2033 | .scan_out(fx4_clipa_scanout), | |
2034 | .clk (l2clk), | |
2035 | .en (vis_clken), | |
2036 | .din ({clip01_c3_fx3[30:0],clip01_c1_fx3[30:0]}), | |
2037 | .dout({clip01_c3_fx4[30:0],clip01_c1_fx4[30:0]}), | |
2038 | .se(se), | |
2039 | .siclk(siclk), | |
2040 | .soclk(soclk), | |
2041 | .pce_ov(pce_ov), | |
2042 | .stop(stop) | |
2043 | ); | |
2044 | ||
2045 | fgu_fgd_dp_msff_macro__width_37 fx4_clipb ( | |
2046 | .scan_in(fx4_clipb_scanin), | |
2047 | .scan_out(fx4_clipb_scanout), | |
2048 | .clk (l2clk), | |
2049 | .en (vis_clken), | |
2050 | .din ({rs201_fx3[63], | |
2051 | rs201_fx3[47], | |
2052 | clip01_c2_fx3[14:0],clip01_c0_fx3[14:0], | |
2053 | rs201_fx3[31], | |
2054 | rs201_fx3[15], | |
2055 | fgx_packfix_fx3,fgx_pack32_fx3,fgx_pack16_fx3}), | |
2056 | .dout({rs2_fx4_b63, | |
2057 | rs2_fx4_b47, | |
2058 | clip01_c2_fx4[14:0],clip01_c0_fx4[14:0], | |
2059 | rs2_fx4_b31, | |
2060 | rs2_fx4_b15, | |
2061 | fgx_packfix_fx4,fgx_pack32_fx4,fgx_pack16_fx4}), | |
2062 | .se(se), | |
2063 | .siclk(siclk), | |
2064 | .soclk(soclk), | |
2065 | .pce_ov(pce_ov), | |
2066 | .stop(stop) | |
2067 | ); | |
2068 | ||
2069 | fgu_fgd_dp_msff_macro__width_34 fx4_pdist ( | |
2070 | .scan_in(fx4_pdist_scanin), | |
2071 | .scan_out(fx4_pdist_scanout), | |
2072 | .clk (l2clk), | |
2073 | .en (vis_clken), | |
2074 | .din ({pdist_42csa_cout0_fx3, | |
2075 | pdist_42csa_cout1_fx3, | |
2076 | pdist_42csa_carry0_fx3[8:1], | |
2077 | pdist_42csa_sum0_fx3[7:0], | |
2078 | pdist_42csa_carry1_fx3[8:1], | |
2079 | pdist_42csa_sum1_fx3[7:0] }), | |
2080 | .dout( pdist_42csa_data_fx4[33:0]), | |
2081 | .se(se), | |
2082 | .siclk(siclk), | |
2083 | .soclk(soclk), | |
2084 | .pce_ov(pce_ov), | |
2085 | .stop(stop) | |
2086 | ); | |
2087 | ||
2088 | // ------------------------------------ | |
2089 | // GSR.mask flops, threads 0-7 | |
2090 | // ------------------------------------ | |
2091 | ||
2092 | fgu_fgd_dp_msff_macro__stack_32l__width_6 fx4_gsrtid ( | |
2093 | .scan_in(fx4_gsrtid_scanin), | |
2094 | .scan_out(fx4_gsrtid_scanout), | |
2095 | .clk (l2clk), | |
2096 | .en (vis_clken), | |
2097 | .din ({fac_gsr_asr_tid_fx2[2:0], fac_tid_fx2[2:0]}), | |
2098 | .dout({ gsr_asr_tid_fx3[2:0], tid_fx3[2:0]}), | |
2099 | .se(se), | |
2100 | .siclk(siclk), | |
2101 | .soclk(soclk), | |
2102 | .pce_ov(pce_ov), | |
2103 | .stop(stop) | |
2104 | ); | |
2105 | ||
2106 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr0mask ( // FS:wmr_protect | |
2107 | .scan_in(fx4_gsr0mask_wmr_scanin), | |
2108 | .scan_out(fx4_gsr0mask_wmr_scanout), | |
2109 | .siclk(spc_aclk_wmr), | |
2110 | .se(lb_scan_en_wmr), | |
2111 | .clk (l2clk), | |
2112 | .en (fpc_gsr0_mask_sel_fx3[1]), | |
2113 | .din0(gsr_mask_fx3[31:0]), | |
2114 | .din1(in_rngl_cdbus_3f[63:32]), | |
2115 | .sel0(fpc_gsr0_mask_sel_fx3[0]), | |
2116 | .dout(gsr0_mask_fx4[31:0]), | |
2117 | .soclk(soclk), | |
2118 | .pce_ov(pce_ov), | |
2119 | .stop(stop) | |
2120 | ); | |
2121 | ||
2122 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr1mask ( // FS:wmr_protect | |
2123 | .scan_in(fx4_gsr1mask_wmr_scanin), | |
2124 | .scan_out(fx4_gsr1mask_wmr_scanout), | |
2125 | .siclk(spc_aclk_wmr), | |
2126 | .se(lb_scan_en_wmr), | |
2127 | .clk (l2clk), | |
2128 | .en (fpc_gsr1_mask_sel_fx3[1]), | |
2129 | .din0(gsr_mask_fx3[31:0]), | |
2130 | .din1(in_rngl_cdbus_3f[63:32]), | |
2131 | .sel0(fpc_gsr1_mask_sel_fx3[0]), | |
2132 | .dout(gsr1_mask_fx4[31:0]), | |
2133 | .soclk(soclk), | |
2134 | .pce_ov(pce_ov), | |
2135 | .stop(stop) | |
2136 | ); | |
2137 | ||
2138 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr2mask ( // FS:wmr_protect | |
2139 | .scan_in(fx4_gsr2mask_wmr_scanin), | |
2140 | .scan_out(fx4_gsr2mask_wmr_scanout), | |
2141 | .siclk(spc_aclk_wmr), | |
2142 | .se(lb_scan_en_wmr), | |
2143 | .clk (l2clk), | |
2144 | .en (fpc_gsr2_mask_sel_fx3[1]), | |
2145 | .din0(gsr_mask_fx3[31:0]), | |
2146 | .din1(in_rngl_cdbus_3f[63:32]), | |
2147 | .sel0(fpc_gsr2_mask_sel_fx3[0]), | |
2148 | .dout(gsr2_mask_fx4[31:0]), | |
2149 | .soclk(soclk), | |
2150 | .pce_ov(pce_ov), | |
2151 | .stop(stop) | |
2152 | ); | |
2153 | ||
2154 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr3mask ( // FS:wmr_protect | |
2155 | .scan_in(fx4_gsr3mask_wmr_scanin), | |
2156 | .scan_out(fx4_gsr3mask_wmr_scanout), | |
2157 | .siclk(spc_aclk_wmr), | |
2158 | .se(lb_scan_en_wmr), | |
2159 | .clk (l2clk), | |
2160 | .en (fpc_gsr3_mask_sel_fx3[1]), | |
2161 | .din0(gsr_mask_fx3[31:0]), | |
2162 | .din1(in_rngl_cdbus_3f[63:32]), | |
2163 | .sel0(fpc_gsr3_mask_sel_fx3[0]), | |
2164 | .dout(gsr3_mask_fx4[31:0]), | |
2165 | .soclk(soclk), | |
2166 | .pce_ov(pce_ov), | |
2167 | .stop(stop) | |
2168 | ); | |
2169 | ||
2170 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr4mask ( // FS:wmr_protect | |
2171 | .scan_in(fx4_gsr4mask_wmr_scanin), | |
2172 | .scan_out(fx4_gsr4mask_wmr_scanout), | |
2173 | .siclk(spc_aclk_wmr), | |
2174 | .se(lb_scan_en_wmr), | |
2175 | .clk (l2clk), | |
2176 | .en (fpc_gsr4_mask_sel_fx3[1]), | |
2177 | .din0(gsr_mask_fx3[31:0]), | |
2178 | .din1(in_rngl_cdbus_3f[63:32]), | |
2179 | .sel0(fpc_gsr4_mask_sel_fx3[0]), | |
2180 | .dout(gsr4_mask_fx4[31:0]), | |
2181 | .soclk(soclk), | |
2182 | .pce_ov(pce_ov), | |
2183 | .stop(stop) | |
2184 | ); | |
2185 | ||
2186 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr5mask ( // FS:wmr_protect | |
2187 | .scan_in(fx4_gsr5mask_wmr_scanin), | |
2188 | .scan_out(fx4_gsr5mask_wmr_scanout), | |
2189 | .siclk(spc_aclk_wmr), | |
2190 | .se(lb_scan_en_wmr), | |
2191 | .clk (l2clk), | |
2192 | .en (fpc_gsr5_mask_sel_fx3[1]), | |
2193 | .din0(gsr_mask_fx3[31:0]), | |
2194 | .din1(in_rngl_cdbus_3f[63:32]), | |
2195 | .sel0(fpc_gsr5_mask_sel_fx3[0]), | |
2196 | .dout(gsr5_mask_fx4[31:0]), | |
2197 | .soclk(soclk), | |
2198 | .pce_ov(pce_ov), | |
2199 | .stop(stop) | |
2200 | ); | |
2201 | ||
2202 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr6mask ( // FS:wmr_protect | |
2203 | .scan_in(fx4_gsr6mask_wmr_scanin), | |
2204 | .scan_out(fx4_gsr6mask_wmr_scanout), | |
2205 | .siclk(spc_aclk_wmr), | |
2206 | .se(lb_scan_en_wmr), | |
2207 | .clk (l2clk), | |
2208 | .en (fpc_gsr6_mask_sel_fx3[1]), | |
2209 | .din0(gsr_mask_fx3[31:0]), | |
2210 | .din1(in_rngl_cdbus_3f[63:32]), | |
2211 | .sel0(fpc_gsr6_mask_sel_fx3[0]), | |
2212 | .dout(gsr6_mask_fx4[31:0]), | |
2213 | .soclk(soclk), | |
2214 | .pce_ov(pce_ov), | |
2215 | .stop(stop) | |
2216 | ); | |
2217 | ||
2218 | fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 fx4_gsr7mask ( // FS:wmr_protect | |
2219 | .scan_in(fx4_gsr7mask_wmr_scanin), | |
2220 | .scan_out(fx4_gsr7mask_wmr_scanout), | |
2221 | .siclk(spc_aclk_wmr), | |
2222 | .se(lb_scan_en_wmr), | |
2223 | .clk (l2clk), | |
2224 | .en (fpc_gsr7_mask_sel_fx3[1]), | |
2225 | .din0(gsr_mask_fx3[31:0]), | |
2226 | .din1(in_rngl_cdbus_3f[63:32]), | |
2227 | .sel0(fpc_gsr7_mask_sel_fx3[0]), | |
2228 | .dout(gsr7_mask_fx4[31:0]), | |
2229 | .soclk(soclk), | |
2230 | .pce_ov(pce_ov), | |
2231 | .stop(stop) | |
2232 | ); | |
2233 | ||
2234 | // ------------------------------------ | |
2235 | // GSR.mask thread 0-7 mux | |
2236 | // ------------------------------------ | |
2237 | ||
2238 | fgu_fgd_dp_mux_macro__mux_aodec__ports_8__stack_32l__width_32 mux_gsr ( | |
2239 | .din0(gsr0_mask_fx4[31:0]), | |
2240 | .din1(gsr1_mask_fx4[31:0]), | |
2241 | .din2(gsr2_mask_fx4[31:0]), | |
2242 | .din3(gsr3_mask_fx4[31:0]), | |
2243 | .din4(gsr4_mask_fx4[31:0]), | |
2244 | .din5(gsr5_mask_fx4[31:0]), | |
2245 | .din6(gsr6_mask_fx4[31:0]), | |
2246 | .din7(gsr7_mask_fx4[31:0]), | |
2247 | .sel (tid_fx3[2:0]), | |
2248 | .dout(gsr_mask_fx4[31:0]) | |
2249 | ); | |
2250 | ||
2251 | fgu_fgd_dp_buff_macro__stack_32l__width_32 buf_gsr ( | |
2252 | .din (gsr_mask_fx4[31:0]), | |
2253 | .dout(gsr_mask0_fx4[31:0]) | |
2254 | ); | |
2255 | ||
2256 | fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_a_rep0 ( | |
2257 | .din (tcu_muxtest ), | |
2258 | .dout(tcu_muxtest_a_rep0) | |
2259 | ); | |
2260 | ||
2261 | fgu_fgd_dp_mux_macro__mux_pgdec__ports_8__stack_32l__width_32 mux_gsrasr ( | |
2262 | .muxtst(tcu_muxtest_a_rep0), | |
2263 | .din0(gsr0_mask_fx4[31:0]), | |
2264 | .din1(gsr1_mask_fx4[31:0]), | |
2265 | .din2(gsr2_mask_fx4[31:0]), | |
2266 | .din3(gsr3_mask_fx4[31:0]), | |
2267 | .din4(gsr4_mask_fx4[31:0]), | |
2268 | .din5(gsr5_mask_fx4[31:0]), | |
2269 | .din6(gsr6_mask_fx4[31:0]), | |
2270 | .din7(gsr7_mask_fx4[31:0]), | |
2271 | .sel (gsr_asr_tid_fx3[2:0]), | |
2272 | .dout({fgd_gsr_asr_mask_fx4_b31, gsr_asr_mask_fx4[30:0]}), | |
2273 | .test(test) | |
2274 | ); | |
2275 | ||
2276 | // ------------------------------------ | |
2277 | // fpack result const detection | |
2278 | // FPACK{16,32},FPACKFIX | |
2279 | // ------------------------------------ | |
2280 | ||
2281 | fgu_fgd_dp_zero_macro__width_32 pack_cmp3 ( | |
2282 | .din ({clip01_c3_fx4[30:0],shift01_fx4[63]}), | |
2283 | .dout(pack_b01_gt255_fx4_) // FPACK16: bits [30:15] == 0, not > 255 | |
2284 | ); // FPACK32: bits [62:31] == 0, not > 255 | |
2285 | // FPACKFIX: bits [62:31] == 0, not > 32767 | |
2286 | ||
2287 | fgu_fgd_dp_cmp_macro__width_32 packfix_cmp3 ( | |
2288 | .din0({clip01_c3_fx4[30:0],shift01_fx4[63]}), | |
2289 | .din1(32'hffffffff), | |
2290 | .dout(pack_b01_lt32768_fx4_) // FPACKFIX: bits [62:31] == 1, not < -32768 | |
2291 | ); | |
2292 | ||
2293 | fgu_fgd_dp_zero_macro__width_16 pack_cmp2 ( | |
2294 | .din ({clip01_c2_fx4[14:0],shift01_fx4[47]}), | |
2295 | .dout(pack_b23_gt255_fx4_) // FPACK16: bits [30:15] == 0, not > 255 | |
2296 | ); | |
2297 | ||
2298 | fgu_fgd_dp_zero_macro__width_32 pack_cmp1 ( | |
2299 | .din ({clip01_c1_fx4[30:0],shift01_fx4[31]}), | |
2300 | .dout(pack_b45_gt255_fx4_) // FPACK16: bits [30:15] == 0, not > 255 | |
2301 | ); // FPACK32: bits [62:31] == 0, not > 255 | |
2302 | // FPACKFIX: bits [62:31] == 0, not > 32767 | |
2303 | ||
2304 | fgu_fgd_dp_cmp_macro__width_32 packfix_cmp1 ( | |
2305 | .din0({clip01_c1_fx4[30:0],shift01_fx4[31]}), | |
2306 | .din1(32'hffffffff), | |
2307 | .dout(pack_b45_lt32768_fx4_) // FPACKFIX: bits [62:31] == 1, not < -32768 | |
2308 | ); | |
2309 | ||
2310 | fgu_fgd_dp_zero_macro__width_16 pack_cmp0 ( | |
2311 | .din ({clip01_c0_fx4[14:0],shift01_fx4[15]}), | |
2312 | .dout(pack_b67_gt255_fx4_) // FPACK16: bits [30:15] == 0, not > 255 | |
2313 | ); | |
2314 | ||
2315 | fgu_fgd_dp_inv_macro__width_8 ipackcmp ( // 0in bits_on -max 1 -var {packfix_hi_gt32767_fx4, packfix_hi_lt32768_fx4}; bits_on -max 1 -var {packfix_lo_gt32767_fx4, packfix_lo_lt32768_fx4} | |
2316 | .din ({pack_b01_gt255_fx4_, | |
2317 | pack_b01_lt32768_fx4_, | |
2318 | pack_b23_gt255_fx4_, | |
2319 | pack_b45_gt255_fx4_, | |
2320 | pack_b45_lt32768_fx4_, | |
2321 | pack_b67_gt255_fx4_, | |
2322 | rs2_fx4_b63, | |
2323 | rs2_fx4_b31}), | |
2324 | .dout({pack_b01_gt255_fx4, | |
2325 | pack_b01_lt32768_fx4, | |
2326 | pack_b23_gt255_fx4, | |
2327 | pack_b45_gt255_fx4, | |
2328 | pack_b45_lt32768_fx4, | |
2329 | pack_b67_gt255_fx4, | |
2330 | rs2_fx4_b63_, | |
2331 | rs2_fx4_b31_}) | |
2332 | ); | |
2333 | ||
2334 | fgu_fgd_dp_and_macro__ports_3__width_2 packsela ( | |
2335 | .din0({fgx_packfix_fx4, fgx_packfix_fx4 }), | |
2336 | .din1({rs2_fx4_b63, rs2_fx4_b31 }), // negative | |
2337 | .din2({pack_b01_lt32768_fx4, pack_b45_lt32768_fx4 }), | |
2338 | .dout({packfix_hi_lt32768_fx4, packfix_lo_lt32768_fx4}) | |
2339 | ); | |
2340 | ||
2341 | fgu_fgd_dp_and_macro__ports_3__width_2 packselb ( | |
2342 | .din0({fgx_packfix_fx4, fgx_packfix_fx4 }), | |
2343 | .din1({rs2_fx4_b63_, rs2_fx4_b31_ }), // positive | |
2344 | .din2({pack_b01_gt255_fx4, pack_b45_gt255_fx4 }), | |
2345 | .dout({packfix_hi_gt32767_fx4, packfix_lo_gt32767_fx4}) | |
2346 | ); | |
2347 | ||
2348 | fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 packselc ( | |
2349 | .din0({rs2_fx4_b15, pack_b67_gt255_fx4}), | |
2350 | .din1({rs2_fx4_b63, pack_b01_gt255_fx4}), | |
2351 | .sel0(fgx_pack16_fx4), | |
2352 | .sel1(fgx_pack32_fx4), | |
2353 | .dout({pack_b3_sign_fx4, pack_b3_gt255_fx4}) | |
2354 | ); | |
2355 | ||
2356 | // ------------------------------------ | |
2357 | // fpack result data/const selection | |
2358 | // FPACK{16,32},FPACKFIX | |
2359 | // | |
2360 | // only FPACK32 64b result updates 32 LSBs | |
2361 | // FPACK16/FPACKFIX 32b result updates 32 MSBs | |
2362 | // ------------------------------------ | |
2363 | ||
2364 | fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b0 ( | |
2365 | .din0(8'h80), // portion of 16'h8000 | |
2366 | .din1(8'h7f), // portion of 16'h7fff | |
2367 | .din2(shift01_fx4[63:56]), // portion of [63:48] | |
2368 | .din3(rs1_fx4[55:48]), | |
2369 | .din4(8'h00), | |
2370 | .din5(8'hff), | |
2371 | .din6(shift01_fx4[62:55]), | |
2372 | .sel0(packfix_hi_lt32768_fx4), | |
2373 | .sel1(packfix_hi_gt32767_fx4), | |
2374 | .sel2(fgx_packfix_fx4), | |
2375 | .sel3(fgx_pack32_fx4), | |
2376 | .sel4(rs2_fx4_b63), // negative | |
2377 | .sel5(pack_b01_gt255_fx4), | |
2378 | .dout(pack_result_fx4[63:56]) | |
2379 | ); | |
2380 | ||
2381 | fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b1 ( | |
2382 | .din0(8'h00), // portion of 16'h8000 | |
2383 | .din1(8'hff), // portion of 16'h7fff | |
2384 | .din2(shift01_fx4[55:48]), // portion of [63:48] | |
2385 | .din3(rs1_fx4[47:40]), | |
2386 | .din4(8'h00), | |
2387 | .din5(8'hff), | |
2388 | .din6(shift01_fx4[46:39]), | |
2389 | .sel0(packfix_hi_lt32768_fx4), | |
2390 | .sel1(packfix_hi_gt32767_fx4), | |
2391 | .sel2(fgx_packfix_fx4), | |
2392 | .sel3(fgx_pack32_fx4), | |
2393 | .sel4(rs2_fx4_b47), // negative | |
2394 | .sel5(pack_b23_gt255_fx4), | |
2395 | .dout(pack_result_fx4[55:48]) | |
2396 | ); | |
2397 | ||
2398 | fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b2 ( | |
2399 | .din0(8'h80), // portion of 16'h8000 | |
2400 | .din1(8'h7f), // portion of 16'h7fff | |
2401 | .din2(shift01_fx4[31:24]), // portion of [31:16] | |
2402 | .din3(rs1_fx4[39:32]), | |
2403 | .din4(8'h00), | |
2404 | .din5(8'hff), | |
2405 | .din6(shift01_fx4[30:23]), | |
2406 | .sel0(packfix_lo_lt32768_fx4), | |
2407 | .sel1(packfix_lo_gt32767_fx4), | |
2408 | .sel2(fgx_packfix_fx4), | |
2409 | .sel3(fgx_pack32_fx4), | |
2410 | .sel4(rs2_fx4_b31), // negative | |
2411 | .sel5(pack_b45_gt255_fx4), | |
2412 | .dout(pack_result_fx4[47:40]) | |
2413 | ); | |
2414 | ||
2415 | fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 pack_b3 ( | |
2416 | .din0(8'h00), // portion of 16'h8000 | |
2417 | .din1(8'hff), // portion of 16'h7fff | |
2418 | .din2(shift01_fx4[23:16]), // portion of [31:16] | |
2419 | .din3(8'h00), | |
2420 | .din4(8'hff), | |
2421 | .din5(shift01_fx4[62:55]), | |
2422 | .din6(shift01_fx4[14:7]), | |
2423 | .sel0(packfix_lo_lt32768_fx4), | |
2424 | .sel1(packfix_lo_gt32767_fx4), | |
2425 | .sel2(fgx_packfix_fx4), | |
2426 | .sel3(pack_b3_sign_fx4), // negative | |
2427 | .sel4(pack_b3_gt255_fx4), | |
2428 | .sel5(fgx_pack32_fx4), | |
2429 | .dout(pack_result_fx4[39:32]) | |
2430 | ); | |
2431 | ||
2432 | fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 pack_lo ( | |
2433 | .din0(8'h00), | |
2434 | .din1(8'hff), | |
2435 | .din2(shift01_fx4[30:23]), | |
2436 | .sel0(rs2_fx4_b31), // negative | |
2437 | .sel1(pack_b45_gt255_fx4), | |
2438 | .dout(pack_result_fx4_b7_0[7:0]) | |
2439 | ); | |
2440 | ||
2441 | // ------------------------------------ | |
2442 | // common PDIST,POPC backend (fx4) | |
2443 | // complete compression of 8 8-bit values (4 8-bit values remain), | |
2444 | // then add to rs3 if PDIST (rs3 arrives one cycle delayed on rs2) | |
2445 | // ------------------------------------ | |
2446 | ||
2447 | fgu_fgd_dp_csa42_macro__width_9 pdist_42csa_2 ( | |
2448 | .i0 ({ pdist_42csa_data_fx4[31:24], 1'b0 }), | |
2449 | .i1 ({pdist_42csa_data_fx4[33], pdist_42csa_data_fx4[23:16]}), | |
2450 | .i2 ({ pdist_42csa_data_fx4[15:8], 1'b0 }), | |
2451 | .i3 ({pdist_42csa_data_fx4[32], pdist_42csa_data_fx4[7:0]}), | |
2452 | .cin ( 1'b0 ), | |
2453 | .cout ( pdist_42csa_cout2_fx4 ), | |
2454 | .carry( pdist_42csa_carry2_fx4[9:1]), | |
2455 | .sum ( pdist_42csa_sum2_fx4[8:0] ) | |
2456 | ); | |
2457 | ||
2458 | fgu_fgd_dp_csa32_macro__width_10 pdist_32csa ( | |
2459 | .i0 ({ pdist_rs3_fx3[9:0]}), | |
2460 | .i1 ({ pdist_42csa_carry2_fx4[9:1], 1'b0}), | |
2461 | .i2 ({pdist_42csa_cout2_fx4, pdist_42csa_sum2_fx4[8:0]}), | |
2462 | .carry( pdist_32csa_carry_fx4[10:1]), | |
2463 | .sum ( pdist_32csa_sum_fx4[9:0] ) | |
2464 | ); | |
2465 | ||
2466 | fgu_fgd_dp_and_macro__ports_2__width_1 pdist_and ( | |
2467 | .din0(pdist_rs3_fx3[11]), | |
2468 | .din1(fgx_pdist_fx4), | |
2469 | .dout(q_pdist_rs3_fx3_b11) | |
2470 | ); | |
2471 | ||
2472 | fgu_fgd_dp_cla_macro__width_12 pdist_cla ( // 0in maximum -val 64 -var {pdist_cout_fx4, pdist_sum_fx4[11:00]} -active (fgx_popc_fx4 & ~fgx_pdist_fx4) | |
2473 | .din0({ 1'b0, pdist_32csa_carry_fx4[10:1], 1'b0}), | |
2474 | .din1({q_pdist_rs3_fx3_b11, pdist_rs3_fx3[10], pdist_32csa_sum_fx4[9:0]}), | |
2475 | .cin (1'b0), | |
2476 | .dout(pdist_sum_fx4[11:0]), | |
2477 | .cout(pdist_cout_fx4 ) // cout not possible if POPC (7-bit result max), | |
2478 | ); // cout not possible for any instr but pdist due to qual done on pdist_rs3_fx3[11] | |
2479 | ||
2480 | // 0in custom -fire (pdist_cout_fx4 & ~fgx_pdist_fx4) | |
2481 | ||
2482 | fgu_fgd_dp_increment_macro__width_64 pdist_inc ( | |
2483 | .din ({rs201_fx3[63:12], 12'hfff}), | |
2484 | .cin ( 1'b1 ), | |
2485 | .dout({pdist_sum_fx4[63:12], pdist_inc_unused[11:0]}), | |
2486 | .cout( pdist_inc_unused[12] ) | |
2487 | ); | |
2488 | ||
2489 | // ------------------------------------ | |
2490 | // FGD final result mux | |
2491 | // ------------------------------------ | |
2492 | ||
2493 | fgu_fgd_dp_msff_macro__mux_aope__ports_5__width_64 fx5_res ( | |
2494 | .scan_in(fx5_res_scanin), | |
2495 | .scan_out(fx5_res_scanout), | |
2496 | .clk (l2clk), | |
2497 | .en (vis_clken), | |
2498 | .din0({pack_result_fx4[63:32], rs1_fx4[23:0], pack_result_fx4_b7_0[7:0]}), | |
2499 | .din1(pdist_sum_fx4[63:0]), | |
2500 | .din2({rs201_fx3[63:12], pdist_sum_fx4[11:0]}), | |
2501 | .din3({57'b0, pdist_sum_fx4[6:0]}), | |
2502 | .din4(simp_result_fx4[63:0]), | |
2503 | .sel0(fgx_pack_sel_fx4), // FPACK16,FPACK32,FPACKFIX | |
2504 | .sel1(pdist_cout_fx4 ), // PDIST with cout from 12 LSBs | |
2505 | .sel2(fgx_pdist_fx4 ), // PDIST | |
2506 | .sel3(fgx_popc_fx4 ), // POPC | |
2507 | // else: other | |
2508 | .dout(fgd_result_fx5[63:0]), | |
2509 | .se(se), | |
2510 | .siclk(siclk), | |
2511 | .soclk(soclk), | |
2512 | .pce_ov(pce_ov), | |
2513 | .stop(stop) | |
2514 | ); | |
2515 | ||
2516 | // ---------------------------------------------------------------------------- | |
2517 | // FGU ASI local ring datapath | |
2518 | // - ASR GSR access | |
2519 | // - ASR FPRS access | |
2520 | // - ASI FRF ECC access (read only) | |
2521 | // ---------------------------------------------------------------------------- | |
2522 | ||
2523 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_1f ( | |
2524 | .scan_in(in_rng1_1f_scanin), | |
2525 | .scan_out(in_rng1_1f_scanout), | |
2526 | .clk (l2clk), | |
2527 | .en (coreon_clken), | |
2528 | .din (in_rngl_cdbus[63:32]), // requires free running clk or rng_data_1f[63] en | |
2529 | .dout(in_rngl_cdbus_1f[63:32]), | |
2530 | .se(se), | |
2531 | .siclk(siclk), | |
2532 | .soclk(soclk), | |
2533 | .pce_ov(pce_ov), | |
2534 | .stop(stop) | |
2535 | ); | |
2536 | ||
2537 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_1f ( | |
2538 | .scan_in(in_rng0_1f_scanin), | |
2539 | .scan_out(in_rng0_1f_scanout), | |
2540 | .clk (l2clk), | |
2541 | .en (coreon_clken), | |
2542 | .din (in_rngl_cdbus[31:0]), // requires free running clk or rng_data_1f[63] en | |
2543 | .dout(in_rngl_cdbus_1f[31:0]), | |
2544 | .se(se), | |
2545 | .siclk(siclk), | |
2546 | .soclk(soclk), | |
2547 | .pce_ov(pce_ov), | |
2548 | .stop(stop) | |
2549 | ); | |
2550 | ||
2551 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_2f ( | |
2552 | .scan_in(in_rng1_2f_scanin), | |
2553 | .scan_out(in_rng1_2f_scanout), | |
2554 | .clk (l2clk), | |
2555 | .en (asi_clken), | |
2556 | .din (in_rngl_cdbus_1f[63:32]), | |
2557 | .dout(in_rngl_cdbus_2f[63:32]), | |
2558 | .se(se), | |
2559 | .siclk(siclk), | |
2560 | .soclk(soclk), | |
2561 | .pce_ov(pce_ov), | |
2562 | .stop(stop) | |
2563 | ); | |
2564 | ||
2565 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_2f ( | |
2566 | .scan_in(in_rng0_2f_scanin), | |
2567 | .scan_out(in_rng0_2f_scanout), | |
2568 | .clk (l2clk), | |
2569 | .en (asi_clken), | |
2570 | .din (in_rngl_cdbus_1f[31:0]), | |
2571 | .dout(in_rngl_cdbus_2f[31:0]), | |
2572 | .se(se), | |
2573 | .siclk(siclk), | |
2574 | .soclk(soclk), | |
2575 | .pce_ov(pce_ov), | |
2576 | .stop(stop) | |
2577 | ); | |
2578 | ||
2579 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng1_3f ( | |
2580 | .scan_in(in_rng1_3f_scanin), | |
2581 | .scan_out(in_rng1_3f_scanout), | |
2582 | .clk (l2clk), | |
2583 | .en (asi_clken), | |
2584 | .din (in_rngl_cdbus_2f[63:32]), | |
2585 | .dout(in_rngl_cdbus_3f[63:32]), | |
2586 | .se(se), | |
2587 | .siclk(siclk), | |
2588 | .soclk(soclk), | |
2589 | .pce_ov(pce_ov), | |
2590 | .stop(stop) | |
2591 | ); | |
2592 | ||
2593 | fgu_fgd_dp_msff_macro__stack_32l__width_32 in_rng0_3f ( | |
2594 | .scan_in(in_rng0_3f_scanin), | |
2595 | .scan_out(in_rng0_3f_scanout), | |
2596 | .clk (l2clk), | |
2597 | .en (asi_clken), | |
2598 | .din (in_rngl_cdbus_2f[31:0]), | |
2599 | .dout(in_rngl_cdbus_3f[31:0]), | |
2600 | .se(se), | |
2601 | .siclk(siclk), | |
2602 | .soclk(soclk), | |
2603 | .pce_ov(pce_ov), | |
2604 | .stop(stop) | |
2605 | ); | |
2606 | ||
2607 | fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_b_rep0 ( | |
2608 | .din (tcu_muxtest ), | |
2609 | .dout(tcu_muxtest_b_rep0) | |
2610 | ); | |
2611 | ||
2612 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_5__stack_32l__width_31 mux_rng1_3f ( | |
2613 | .muxtst(tcu_muxtest_b_rep0), | |
2614 | .din0({ // ASR/ASI GSR/FPRS/FRF_ECC rd or wr (ctl ) | |
2615 | 1'b1, // set ack | |
2616 | in_rngl_cdbus_3f[61:56], // | |
2617 | 8'b0, // clear ASI field (report no exceptions) | |
2618 | in_rngl_cdbus_3f[47:32]}), // | |
2619 | .din1(gsr_asr_mask_fx4[30:0]), // ASR GSR read data ( data) | |
2620 | .din2(31'b0), // ASR FPRS read data ( data) | |
2621 | .din3(31'b0), // ASI FRF ECC read data ( data) | |
2622 | .din4(in_rngl_cdbus_3f[62:32]), // bypass incoming ASI data unmodified (ctl or data) | |
2623 | .sel0(fac_rng_rd_or_wr_3f), | |
2624 | .sel1(fac_rng_rd_gsr_4f), | |
2625 | .sel2(fac_rng_rd_fprs_4f), | |
2626 | .sel3(fac_rng_rd_ecc_4f), | |
2627 | .dout(fgd_rngl_cdbus_3f[62:32]), | |
2628 | .test(test) | |
2629 | ); | |
2630 | ||
2631 | fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 muxtest_c_rep0 ( | |
2632 | .din (tcu_muxtest ), | |
2633 | .dout(tcu_muxtest_c_rep0) | |
2634 | ); | |
2635 | ||
2636 | fgu_fgd_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_32 mux_rng0_3f ( | |
2637 | .muxtst(tcu_muxtest_c_rep0), | |
2638 | .din0({4'b0, // ASR GSR read data ( data) | |
2639 | fpc_gsr_asr_11bits_fx4[10], | |
2640 | fpc_gsr_asr_11bits_fx4[9:8], | |
2641 | 17'b0, | |
2642 | fpc_gsr_asr_11bits_fx4[7:3], | |
2643 | fpc_gsr_asr_11bits_fx4[2:0]}), | |
2644 | .din1({29'b0, fac_rng_fprs[2:0]}), // ASR FPRS read data ( data) | |
2645 | .din2({18'b0, fec_r1_ecc_fx1[13:0]}), // ASI FRF ECC read data ( data) | |
2646 | .din3(in_rngl_cdbus_3f[31:0]), // bypass incoming ASI data unmodified (ctl or data) | |
2647 | // OR | |
2648 | // ASR/ASI GSR/FPRS/FRF_ECC rd or wr (ctl ) | |
2649 | .sel0(fac_rng_rd_gsr_4f), | |
2650 | .sel1(fac_rng_rd_fprs_4f), | |
2651 | .sel2(fac_rng_rd_ecc_4f), | |
2652 | .dout(fgd_rngl_cdbus_3f[31:0]), | |
2653 | .test(test) | |
2654 | ); | |
2655 | ||
2656 | ||
2657 | // fixscan start: | |
2658 | assign fx2_rs1_scanin = scan_in ; | |
2659 | assign fx2_rs2_scanin = fx2_rs1_scanout ; | |
2660 | assign fx2_gsr_scanin = fx2_rs2_scanout ; | |
2661 | assign fx3_rs1_scanin = fx2_gsr_scanout ; | |
2662 | assign fx3_rs2_scanin = fx3_rs1_scanout ; | |
2663 | assign fx3_gsr_mask_scanin = fx3_rs2_scanout ; | |
2664 | assign fx3_popc_scanin = fx3_gsr_mask_scanout ; | |
2665 | assign fx3_ctl_scanin = fx3_popc_scanout ; | |
2666 | assign fx4_simp_scanin = fx3_ctl_scanout ; | |
2667 | assign fx4_rs1_scanin = fx4_simp_scanout ; | |
2668 | assign fx4_shift_scanin = fx4_rs1_scanout ; | |
2669 | assign fx4_clipa_scanin = fx4_shift_scanout ; | |
2670 | assign fx4_clipb_scanin = fx4_clipa_scanout ; | |
2671 | assign fx4_pdist_scanin = fx4_clipb_scanout ; | |
2672 | assign fx4_gsrtid_scanin = fx4_pdist_scanout ; | |
2673 | assign fx5_res_scanin = fx4_gsrtid_scanout ; | |
2674 | assign in_rng1_1f_scanin = fx5_res_scanout ; | |
2675 | assign in_rng0_1f_scanin = in_rng1_1f_scanout ; | |
2676 | assign in_rng1_2f_scanin = in_rng0_1f_scanout ; | |
2677 | assign in_rng0_2f_scanin = in_rng1_2f_scanout ; | |
2678 | assign in_rng1_3f_scanin = in_rng0_2f_scanout ; | |
2679 | assign in_rng0_3f_scanin = in_rng1_3f_scanout ; | |
2680 | assign scan_out = in_rng0_3f_scanout ; | |
2681 | ||
2682 | assign fx4_gsr0mask_wmr_scanin = wmr_scan_in ; | |
2683 | assign fx4_gsr1mask_wmr_scanin = fx4_gsr0mask_wmr_scanout ; | |
2684 | assign fx4_gsr2mask_wmr_scanin = fx4_gsr1mask_wmr_scanout ; | |
2685 | assign fx4_gsr3mask_wmr_scanin = fx4_gsr2mask_wmr_scanout ; | |
2686 | assign fx4_gsr4mask_wmr_scanin = fx4_gsr3mask_wmr_scanout ; | |
2687 | assign fx4_gsr5mask_wmr_scanin = fx4_gsr4mask_wmr_scanout ; | |
2688 | assign fx4_gsr6mask_wmr_scanin = fx4_gsr5mask_wmr_scanout ; | |
2689 | assign fx4_gsr7mask_wmr_scanin = fx4_gsr6mask_wmr_scanout ; | |
2690 | assign wmr_scan_out = fx4_gsr7mask_wmr_scanout ; | |
2691 | // fixscan end: | |
2692 | endmodule // fgu_fgd_dp | |
2693 | ||
2694 | ||
2695 | // | |
2696 | // buff macro | |
2697 | // | |
2698 | // | |
2699 | ||
2700 | ||
2701 | ||
2702 | ||
2703 | ||
2704 | module fgu_fgd_dp_buff_macro__dbuff_32x__rep_1__width_4 ( | |
2705 | din, | |
2706 | dout); | |
2707 | input [3:0] din; | |
2708 | output [3:0] dout; | |
2709 | ||
2710 | ||
2711 | ||
2712 | ||
2713 | ||
2714 | ||
2715 | buff #(4) d0_0 ( | |
2716 | .in(din[3:0]), | |
2717 | .out(dout[3:0]) | |
2718 | ); | |
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | ||
2724 | ||
2725 | ||
2726 | ||
2727 | endmodule | |
2728 | ||
2729 | ||
2730 | ||
2731 | ||
2732 | ||
2733 | ||
2734 | ||
2735 | ||
2736 | ||
2737 | // any PARAMS parms go into naming of macro | |
2738 | ||
2739 | module fgu_fgd_dp_msff_macro__width_64 ( | |
2740 | din, | |
2741 | clk, | |
2742 | en, | |
2743 | se, | |
2744 | scan_in, | |
2745 | siclk, | |
2746 | soclk, | |
2747 | pce_ov, | |
2748 | stop, | |
2749 | dout, | |
2750 | scan_out); | |
2751 | wire l1clk; | |
2752 | wire siclk_out; | |
2753 | wire soclk_out; | |
2754 | wire [62:0] so; | |
2755 | ||
2756 | input [63:0] din; | |
2757 | ||
2758 | ||
2759 | input clk; | |
2760 | input en; | |
2761 | input se; | |
2762 | input scan_in; | |
2763 | input siclk; | |
2764 | input soclk; | |
2765 | input pce_ov; | |
2766 | input stop; | |
2767 | ||
2768 | ||
2769 | ||
2770 | output [63:0] dout; | |
2771 | ||
2772 | ||
2773 | output scan_out; | |
2774 | ||
2775 | ||
2776 | ||
2777 | ||
2778 | cl_dp1_l1hdr_8x c0_0 ( | |
2779 | .l2clk(clk), | |
2780 | .pce(en), | |
2781 | .aclk(siclk), | |
2782 | .bclk(soclk), | |
2783 | .l1clk(l1clk), | |
2784 | .se(se), | |
2785 | .pce_ov(pce_ov), | |
2786 | .stop(stop), | |
2787 | .siclk_out(siclk_out), | |
2788 | .soclk_out(soclk_out) | |
2789 | ); | |
2790 | dff #(64) d0_0 ( | |
2791 | .l1clk(l1clk), | |
2792 | .siclk(siclk_out), | |
2793 | .soclk(soclk_out), | |
2794 | .d(din[63:0]), | |
2795 | .si({scan_in,so[62:0]}), | |
2796 | .so({so[62:0],scan_out}), | |
2797 | .q(dout[63:0]) | |
2798 | ); | |
2799 | ||
2800 | ||
2801 | ||
2802 | ||
2803 | ||
2804 | ||
2805 | ||
2806 | ||
2807 | ||
2808 | ||
2809 | ||
2810 | ||
2811 | ||
2812 | ||
2813 | ||
2814 | ||
2815 | ||
2816 | ||
2817 | ||
2818 | ||
2819 | endmodule | |
2820 | ||
2821 | ||
2822 | ||
2823 | ||
2824 | ||
2825 | ||
2826 | ||
2827 | ||
2828 | ||
2829 | ||
2830 | ||
2831 | ||
2832 | ||
2833 | // any PARAMS parms go into naming of macro | |
2834 | ||
2835 | module fgu_fgd_dp_msff_macro__stack_32l__width_32 ( | |
2836 | din, | |
2837 | clk, | |
2838 | en, | |
2839 | se, | |
2840 | scan_in, | |
2841 | siclk, | |
2842 | soclk, | |
2843 | pce_ov, | |
2844 | stop, | |
2845 | dout, | |
2846 | scan_out); | |
2847 | wire l1clk; | |
2848 | wire siclk_out; | |
2849 | wire soclk_out; | |
2850 | wire [30:0] so; | |
2851 | ||
2852 | input [31:0] din; | |
2853 | ||
2854 | ||
2855 | input clk; | |
2856 | input en; | |
2857 | input se; | |
2858 | input scan_in; | |
2859 | input siclk; | |
2860 | input soclk; | |
2861 | input pce_ov; | |
2862 | input stop; | |
2863 | ||
2864 | ||
2865 | ||
2866 | output [31:0] dout; | |
2867 | ||
2868 | ||
2869 | output scan_out; | |
2870 | ||
2871 | ||
2872 | ||
2873 | ||
2874 | cl_dp1_l1hdr_8x c0_0 ( | |
2875 | .l2clk(clk), | |
2876 | .pce(en), | |
2877 | .aclk(siclk), | |
2878 | .bclk(soclk), | |
2879 | .l1clk(l1clk), | |
2880 | .se(se), | |
2881 | .pce_ov(pce_ov), | |
2882 | .stop(stop), | |
2883 | .siclk_out(siclk_out), | |
2884 | .soclk_out(soclk_out) | |
2885 | ); | |
2886 | dff #(32) d0_0 ( | |
2887 | .l1clk(l1clk), | |
2888 | .siclk(siclk_out), | |
2889 | .soclk(soclk_out), | |
2890 | .d(din[31:0]), | |
2891 | .si({scan_in,so[30:0]}), | |
2892 | .so({so[30:0],scan_out}), | |
2893 | .q(dout[31:0]) | |
2894 | ); | |
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | ||
2902 | ||
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | ||
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 | endmodule | |
2916 | ||
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | ||
2922 | ||
2923 | ||
2924 | ||
2925 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2926 | // also for pass-gate with decoder | |
2927 | ||
2928 | ||
2929 | ||
2930 | ||
2931 | ||
2932 | // any PARAMS parms go into naming of macro | |
2933 | ||
2934 | module fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_12 ( | |
2935 | din0, | |
2936 | sel0, | |
2937 | din1, | |
2938 | sel1, | |
2939 | dout); | |
2940 | input [11:0] din0; | |
2941 | input sel0; | |
2942 | input [11:0] din1; | |
2943 | input sel1; | |
2944 | output [11:0] dout; | |
2945 | ||
2946 | ||
2947 | ||
2948 | ||
2949 | ||
2950 | mux2s #(12) d0_0 ( | |
2951 | .sel0(sel0), | |
2952 | .sel1(sel1), | |
2953 | .in0(din0[11:0]), | |
2954 | .in1(din1[11:0]), | |
2955 | .dout(dout[11:0]) | |
2956 | ); | |
2957 | ||
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | ||
2963 | ||
2964 | ||
2965 | ||
2966 | ||
2967 | ||
2968 | ||
2969 | ||
2970 | endmodule | |
2971 | ||
2972 | ||
2973 | // | |
2974 | // 4:2 Carry Save Adder | |
2975 | // | |
2976 | // | |
2977 | // i0 i1 i2 i3 | co | carry sum | |
2978 | // ------------|----|----------- | |
2979 | // 0 0 0 0 | 0 | 0 cin | |
2980 | // 0 0 0 1 | 0 | cin ~cin | |
2981 | // 0 0 1 0 | 0 | cin ~cin | |
2982 | // 0 0 1 1 | 0 | 1 cin | |
2983 | // | |
2984 | // 0 1 0 0 | 0 | cin ~cin | |
2985 | // 0 1 0 1 | 0 | 1 cin | |
2986 | // 0 1 1 0 | 1 | 0 cin | |
2987 | // 0 1 1 1 | 1 | cin ~cin | |
2988 | // | |
2989 | // 1 0 0 0 | 0 | cin ~cin | |
2990 | // 1 0 0 1 | 0 | 1 cin | |
2991 | // 1 0 1 0 | 1 | 0 cin | |
2992 | // 1 0 1 1 | 1 | cin ~cin | |
2993 | // | |
2994 | // 1 1 0 0 | 1 | 0 cin | |
2995 | // 1 1 0 1 | 1 | cin ~cin | |
2996 | // 1 1 1 0 | 1 | cin ~cin | |
2997 | // 1 1 1 1 | 1 | 1 cin | |
2998 | ||
2999 | ||
3000 | // This circuit looks like a compression of 5 terms down | |
3001 | // to 3 term on an individual bit basis. However, the fast | |
3002 | // output "co" from bit position "n" is actually the late input | |
3003 | // "cin" on bit position "n+1". Once a wrapper is written | |
3004 | // around multiple bits, this circuit will give the | |
3005 | // appearance of compressing 4 inputs down to 2 outputs. | |
3006 | ||
3007 | ||
3008 | ||
3009 | ||
3010 | ||
3011 | // any PARAMS parms go into naming of macro | |
3012 | ||
3013 | ||
3014 | module fgu_fgd_dp_csa42_macro__width_1 ( | |
3015 | i0, | |
3016 | i1, | |
3017 | i2, | |
3018 | i3, | |
3019 | cin, | |
3020 | cout, | |
3021 | carry, | |
3022 | sum); | |
3023 | input [0:0] i0; | |
3024 | input [0:0] i1; | |
3025 | input [0:0] i2; | |
3026 | input [0:0] i3; | |
3027 | input cin; | |
3028 | output cout; | |
3029 | output [0:0] carry; | |
3030 | output [0:0] sum; | |
3031 | ||
3032 | ||
3033 | ||
3034 | ||
3035 | ||
3036 | ||
3037 | csa42 #(1) d0_0 ( | |
3038 | .cin(cin), | |
3039 | .in0(i0[0:0]), | |
3040 | .in1(i1[0:0]), | |
3041 | .in2(i2[0:0]), | |
3042 | .in3(i3[0:0]), | |
3043 | .cout(cout), | |
3044 | .carry(carry[0:0]), | |
3045 | .sum(sum[0:0]) | |
3046 | ); | |
3047 | ||
3048 | ||
3049 | ||
3050 | ||
3051 | ||
3052 | ||
3053 | ||
3054 | ||
3055 | endmodule | |
3056 | ||
3057 | ||
3058 | ||
3059 | ||
3060 | // | |
3061 | // cla macro | |
3062 | // | |
3063 | // | |
3064 | ||
3065 | ||
3066 | ||
3067 | ||
3068 | ||
3069 | module fgu_fgd_dp_cla_macro__width_4 ( | |
3070 | cin, | |
3071 | din0, | |
3072 | din1, | |
3073 | dout, | |
3074 | cout); | |
3075 | input cin; | |
3076 | input [3:0] din0; | |
3077 | input [3:0] din1; | |
3078 | output [3:0] dout; | |
3079 | output cout; | |
3080 | ||
3081 | ||
3082 | ||
3083 | ||
3084 | ||
3085 | ||
3086 | ||
3087 | cla #(4) m0_0 ( | |
3088 | .cin(cin), | |
3089 | .in0(din0[3:0]), | |
3090 | .in1(din1[3:0]), | |
3091 | .out(dout[3:0]), | |
3092 | .cout(cout) | |
3093 | ); | |
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | ||
3100 | ||
3101 | ||
3102 | ||
3103 | ||
3104 | ||
3105 | ||
3106 | endmodule | |
3107 | ||
3108 | ||
3109 | ||
3110 | ||
3111 | ||
3112 | // | |
3113 | // buff macro | |
3114 | // | |
3115 | // | |
3116 | ||
3117 | ||
3118 | ||
3119 | ||
3120 | ||
3121 | module fgu_fgd_dp_buff_macro__width_64 ( | |
3122 | din, | |
3123 | dout); | |
3124 | input [63:0] din; | |
3125 | output [63:0] dout; | |
3126 | ||
3127 | ||
3128 | ||
3129 | ||
3130 | ||
3131 | ||
3132 | buff #(64) d0_0 ( | |
3133 | .in(din[63:0]), | |
3134 | .out(dout[63:0]) | |
3135 | ); | |
3136 | ||
3137 | ||
3138 | ||
3139 | ||
3140 | ||
3141 | ||
3142 | ||
3143 | ||
3144 | endmodule | |
3145 | ||
3146 | ||
3147 | ||
3148 | ||
3149 | ||
3150 | ||
3151 | ||
3152 | ||
3153 | ||
3154 | // any PARAMS parms go into naming of macro | |
3155 | ||
3156 | module fgu_fgd_dp_msff_macro__minbuff_1__width_64 ( | |
3157 | din, | |
3158 | clk, | |
3159 | en, | |
3160 | se, | |
3161 | scan_in, | |
3162 | siclk, | |
3163 | soclk, | |
3164 | pce_ov, | |
3165 | stop, | |
3166 | dout, | |
3167 | scan_out); | |
3168 | wire l1clk; | |
3169 | wire siclk_out; | |
3170 | wire soclk_out; | |
3171 | wire [62:0] so; | |
3172 | ||
3173 | input [63:0] din; | |
3174 | ||
3175 | ||
3176 | input clk; | |
3177 | input en; | |
3178 | input se; | |
3179 | input scan_in; | |
3180 | input siclk; | |
3181 | input soclk; | |
3182 | input pce_ov; | |
3183 | input stop; | |
3184 | ||
3185 | ||
3186 | ||
3187 | output [63:0] dout; | |
3188 | ||
3189 | ||
3190 | output scan_out; | |
3191 | ||
3192 | ||
3193 | ||
3194 | ||
3195 | cl_dp1_l1hdr_8x c0_0 ( | |
3196 | .l2clk(clk), | |
3197 | .pce(en), | |
3198 | .aclk(siclk), | |
3199 | .bclk(soclk), | |
3200 | .l1clk(l1clk), | |
3201 | .se(se), | |
3202 | .pce_ov(pce_ov), | |
3203 | .stop(stop), | |
3204 | .siclk_out(siclk_out), | |
3205 | .soclk_out(soclk_out) | |
3206 | ); | |
3207 | dff #(64) d0_0 ( | |
3208 | .l1clk(l1clk), | |
3209 | .siclk(siclk_out), | |
3210 | .soclk(soclk_out), | |
3211 | .d(din[63:0]), | |
3212 | .si({scan_in,so[62:0]}), | |
3213 | .so({so[62:0],scan_out}), | |
3214 | .q(dout[63:0]) | |
3215 | ); | |
3216 | ||
3217 | ||
3218 | ||
3219 | ||
3220 | ||
3221 | ||
3222 | ||
3223 | ||
3224 | ||
3225 | ||
3226 | ||
3227 | ||
3228 | ||
3229 | ||
3230 | ||
3231 | ||
3232 | ||
3233 | ||
3234 | ||
3235 | ||
3236 | endmodule | |
3237 | ||
3238 | ||
3239 | ||
3240 | ||
3241 | ||
3242 | ||
3243 | ||
3244 | ||
3245 | ||
3246 | ||
3247 | ||
3248 | ||
3249 | ||
3250 | // any PARAMS parms go into naming of macro | |
3251 | ||
3252 | module fgu_fgd_dp_msff_macro__width_32 ( | |
3253 | din, | |
3254 | clk, | |
3255 | en, | |
3256 | se, | |
3257 | scan_in, | |
3258 | siclk, | |
3259 | soclk, | |
3260 | pce_ov, | |
3261 | stop, | |
3262 | dout, | |
3263 | scan_out); | |
3264 | wire l1clk; | |
3265 | wire siclk_out; | |
3266 | wire soclk_out; | |
3267 | wire [30:0] so; | |
3268 | ||
3269 | input [31:0] din; | |
3270 | ||
3271 | ||
3272 | input clk; | |
3273 | input en; | |
3274 | input se; | |
3275 | input scan_in; | |
3276 | input siclk; | |
3277 | input soclk; | |
3278 | input pce_ov; | |
3279 | input stop; | |
3280 | ||
3281 | ||
3282 | ||
3283 | output [31:0] dout; | |
3284 | ||
3285 | ||
3286 | output scan_out; | |
3287 | ||
3288 | ||
3289 | ||
3290 | ||
3291 | cl_dp1_l1hdr_8x c0_0 ( | |
3292 | .l2clk(clk), | |
3293 | .pce(en), | |
3294 | .aclk(siclk), | |
3295 | .bclk(soclk), | |
3296 | .l1clk(l1clk), | |
3297 | .se(se), | |
3298 | .pce_ov(pce_ov), | |
3299 | .stop(stop), | |
3300 | .siclk_out(siclk_out), | |
3301 | .soclk_out(soclk_out) | |
3302 | ); | |
3303 | dff #(32) d0_0 ( | |
3304 | .l1clk(l1clk), | |
3305 | .siclk(siclk_out), | |
3306 | .soclk(soclk_out), | |
3307 | .d(din[31:0]), | |
3308 | .si({scan_in,so[30:0]}), | |
3309 | .so({so[30:0],scan_out}), | |
3310 | .q(dout[31:0]) | |
3311 | ); | |
3312 | ||
3313 | ||
3314 | ||
3315 | ||
3316 | ||
3317 | ||
3318 | ||
3319 | ||
3320 | ||
3321 | ||
3322 | ||
3323 | ||
3324 | ||
3325 | ||
3326 | ||
3327 | ||
3328 | ||
3329 | ||
3330 | ||
3331 | ||
3332 | endmodule | |
3333 | ||
3334 | ||
3335 | ||
3336 | ||
3337 | ||
3338 | ||
3339 | ||
3340 | ||
3341 | ||
3342 | ||
3343 | ||
3344 | ||
3345 | ||
3346 | // any PARAMS parms go into naming of macro | |
3347 | ||
3348 | module fgu_fgd_dp_msff_macro__width_33 ( | |
3349 | din, | |
3350 | clk, | |
3351 | en, | |
3352 | se, | |
3353 | scan_in, | |
3354 | siclk, | |
3355 | soclk, | |
3356 | pce_ov, | |
3357 | stop, | |
3358 | dout, | |
3359 | scan_out); | |
3360 | wire l1clk; | |
3361 | wire siclk_out; | |
3362 | wire soclk_out; | |
3363 | wire [31:0] so; | |
3364 | ||
3365 | input [32:0] din; | |
3366 | ||
3367 | ||
3368 | input clk; | |
3369 | input en; | |
3370 | input se; | |
3371 | input scan_in; | |
3372 | input siclk; | |
3373 | input soclk; | |
3374 | input pce_ov; | |
3375 | input stop; | |
3376 | ||
3377 | ||
3378 | ||
3379 | output [32:0] dout; | |
3380 | ||
3381 | ||
3382 | output scan_out; | |
3383 | ||
3384 | ||
3385 | ||
3386 | ||
3387 | cl_dp1_l1hdr_8x c0_0 ( | |
3388 | .l2clk(clk), | |
3389 | .pce(en), | |
3390 | .aclk(siclk), | |
3391 | .bclk(soclk), | |
3392 | .l1clk(l1clk), | |
3393 | .se(se), | |
3394 | .pce_ov(pce_ov), | |
3395 | .stop(stop), | |
3396 | .siclk_out(siclk_out), | |
3397 | .soclk_out(soclk_out) | |
3398 | ); | |
3399 | dff #(33) d0_0 ( | |
3400 | .l1clk(l1clk), | |
3401 | .siclk(siclk_out), | |
3402 | .soclk(soclk_out), | |
3403 | .d(din[32:0]), | |
3404 | .si({scan_in,so[31:0]}), | |
3405 | .so({so[31:0],scan_out}), | |
3406 | .q(dout[32:0]) | |
3407 | ); | |
3408 | ||
3409 | ||
3410 | ||
3411 | ||
3412 | ||
3413 | ||
3414 | ||
3415 | ||
3416 | ||
3417 | ||
3418 | ||
3419 | ||
3420 | ||
3421 | ||
3422 | ||
3423 | ||
3424 | ||
3425 | ||
3426 | ||
3427 | ||
3428 | endmodule | |
3429 | ||
3430 | ||
3431 | ||
3432 | ||
3433 | ||
3434 | ||
3435 | ||
3436 | ||
3437 | ||
3438 | // | |
3439 | // invert macro | |
3440 | // | |
3441 | // | |
3442 | ||
3443 | ||
3444 | ||
3445 | ||
3446 | ||
3447 | module fgu_fgd_dp_inv_macro__width_64 ( | |
3448 | din, | |
3449 | dout); | |
3450 | input [63:0] din; | |
3451 | output [63:0] dout; | |
3452 | ||
3453 | ||
3454 | ||
3455 | ||
3456 | ||
3457 | ||
3458 | inv #(64) d0_0 ( | |
3459 | .in(din[63:0]), | |
3460 | .out(dout[63:0]) | |
3461 | ); | |
3462 | ||
3463 | ||
3464 | ||
3465 | ||
3466 | ||
3467 | ||
3468 | ||
3469 | ||
3470 | ||
3471 | endmodule | |
3472 | ||
3473 | ||
3474 | ||
3475 | ||
3476 | ||
3477 | // | |
3478 | // buff macro | |
3479 | // | |
3480 | // | |
3481 | ||
3482 | ||
3483 | ||
3484 | ||
3485 | ||
3486 | module fgu_fgd_dp_buff_macro__width_8 ( | |
3487 | din, | |
3488 | dout); | |
3489 | input [7:0] din; | |
3490 | output [7:0] dout; | |
3491 | ||
3492 | ||
3493 | ||
3494 | ||
3495 | ||
3496 | ||
3497 | buff #(8) d0_0 ( | |
3498 | .in(din[7:0]), | |
3499 | .out(dout[7:0]) | |
3500 | ); | |
3501 | ||
3502 | ||
3503 | ||
3504 | ||
3505 | ||
3506 | ||
3507 | ||
3508 | ||
3509 | endmodule | |
3510 | ||
3511 | ||
3512 | ||
3513 | ||
3514 | ||
3515 | // | |
3516 | // nand macro for ports = 2,3,4 | |
3517 | // | |
3518 | // | |
3519 | ||
3520 | ||
3521 | ||
3522 | ||
3523 | ||
3524 | module fgu_fgd_dp_nand_macro__ports_3__width_64 ( | |
3525 | din0, | |
3526 | din1, | |
3527 | din2, | |
3528 | dout); | |
3529 | input [63:0] din0; | |
3530 | input [63:0] din1; | |
3531 | input [63:0] din2; | |
3532 | output [63:0] dout; | |
3533 | ||
3534 | ||
3535 | ||
3536 | ||
3537 | ||
3538 | ||
3539 | nand3 #(64) d0_0 ( | |
3540 | .in0(din0[63:0]), | |
3541 | .in1(din1[63:0]), | |
3542 | .in2(din2[63:0]), | |
3543 | .out(dout[63:0]) | |
3544 | ); | |
3545 | ||
3546 | ||
3547 | ||
3548 | ||
3549 | ||
3550 | ||
3551 | ||
3552 | ||
3553 | ||
3554 | endmodule | |
3555 | ||
3556 | ||
3557 | ||
3558 | ||
3559 | ||
3560 | // | |
3561 | // nand macro for ports = 2,3,4 | |
3562 | // | |
3563 | // | |
3564 | ||
3565 | ||
3566 | ||
3567 | ||
3568 | ||
3569 | module fgu_fgd_dp_nand_macro__ports_4__width_64 ( | |
3570 | din0, | |
3571 | din1, | |
3572 | din2, | |
3573 | din3, | |
3574 | dout); | |
3575 | input [63:0] din0; | |
3576 | input [63:0] din1; | |
3577 | input [63:0] din2; | |
3578 | input [63:0] din3; | |
3579 | output [63:0] dout; | |
3580 | ||
3581 | ||
3582 | ||
3583 | ||
3584 | ||
3585 | ||
3586 | nand4 #(64) d0_0 ( | |
3587 | .in0(din0[63:0]), | |
3588 | .in1(din1[63:0]), | |
3589 | .in2(din2[63:0]), | |
3590 | .in3(din3[63:0]), | |
3591 | .out(dout[63:0]) | |
3592 | ); | |
3593 | ||
3594 | ||
3595 | ||
3596 | ||
3597 | ||
3598 | ||
3599 | ||
3600 | ||
3601 | ||
3602 | endmodule | |
3603 | ||
3604 | ||
3605 | ||
3606 | ||
3607 | ||
3608 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3609 | // also for pass-gate with decoder | |
3610 | ||
3611 | ||
3612 | ||
3613 | ||
3614 | ||
3615 | // any PARAMS parms go into naming of macro | |
3616 | ||
3617 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_8 ( | |
3618 | din0, | |
3619 | din1, | |
3620 | din2, | |
3621 | din3, | |
3622 | din4, | |
3623 | din5, | |
3624 | din6, | |
3625 | din7, | |
3626 | sel, | |
3627 | dout); | |
3628 | wire psel0; | |
3629 | wire psel1; | |
3630 | wire psel2; | |
3631 | wire psel3; | |
3632 | wire psel4; | |
3633 | wire psel5; | |
3634 | wire psel6; | |
3635 | wire psel7; | |
3636 | ||
3637 | input [7:0] din0; | |
3638 | input [7:0] din1; | |
3639 | input [7:0] din2; | |
3640 | input [7:0] din3; | |
3641 | input [7:0] din4; | |
3642 | input [7:0] din5; | |
3643 | input [7:0] din6; | |
3644 | input [7:0] din7; | |
3645 | input [2:0] sel; | |
3646 | output [7:0] dout; | |
3647 | ||
3648 | ||
3649 | ||
3650 | ||
3651 | ||
3652 | cl_dp1_pdec8_8x c0_0 ( | |
3653 | .test(1'b1), | |
3654 | .sel0(sel[0]), | |
3655 | .sel1(sel[1]), | |
3656 | .sel2(sel[2]), | |
3657 | .psel0(psel0), | |
3658 | .psel1(psel1), | |
3659 | .psel2(psel2), | |
3660 | .psel3(psel3), | |
3661 | .psel4(psel4), | |
3662 | .psel5(psel5), | |
3663 | .psel6(psel6), | |
3664 | .psel7(psel7) | |
3665 | ); | |
3666 | ||
3667 | mux8s #(8) d0_0 ( | |
3668 | .sel0(psel0), | |
3669 | .sel1(psel1), | |
3670 | .sel2(psel2), | |
3671 | .sel3(psel3), | |
3672 | .sel4(psel4), | |
3673 | .sel5(psel5), | |
3674 | .sel6(psel6), | |
3675 | .sel7(psel7), | |
3676 | .in0(din0[7:0]), | |
3677 | .in1(din1[7:0]), | |
3678 | .in2(din2[7:0]), | |
3679 | .in3(din3[7:0]), | |
3680 | .in4(din4[7:0]), | |
3681 | .in5(din5[7:0]), | |
3682 | .in6(din6[7:0]), | |
3683 | .in7(din7[7:0]), | |
3684 | .dout(dout[7:0]) | |
3685 | ); | |
3686 | ||
3687 | ||
3688 | ||
3689 | ||
3690 | ||
3691 | ||
3692 | ||
3693 | ||
3694 | ||
3695 | ||
3696 | ||
3697 | ||
3698 | ||
3699 | endmodule | |
3700 | ||
3701 | ||
3702 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3703 | // also for pass-gate with decoder | |
3704 | ||
3705 | ||
3706 | ||
3707 | ||
3708 | ||
3709 | // any PARAMS parms go into naming of macro | |
3710 | ||
3711 | module fgu_fgd_dp_mux_macro__mux_pgpe__ports_2__width_8 ( | |
3712 | din0, | |
3713 | din1, | |
3714 | sel0, | |
3715 | dout); | |
3716 | wire psel0_unused; | |
3717 | wire psel1; | |
3718 | ||
3719 | input [7:0] din0; | |
3720 | input [7:0] din1; | |
3721 | input sel0; | |
3722 | output [7:0] dout; | |
3723 | ||
3724 | ||
3725 | ||
3726 | ||
3727 | ||
3728 | cl_dp1_penc2_8x c0_0 ( | |
3729 | .sel0(sel0), | |
3730 | .psel0(psel0_unused), | |
3731 | .psel1(psel1) | |
3732 | ); | |
3733 | ||
3734 | mux2e #(8) d0_0 ( | |
3735 | .sel(psel1), | |
3736 | .in0(din0[7:0]), | |
3737 | .in1(din1[7:0]), | |
3738 | .dout(dout[7:0]) | |
3739 | ); | |
3740 | ||
3741 | ||
3742 | ||
3743 | ||
3744 | ||
3745 | ||
3746 | ||
3747 | ||
3748 | ||
3749 | ||
3750 | ||
3751 | ||
3752 | ||
3753 | endmodule | |
3754 | ||
3755 | ||
3756 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3757 | // also for pass-gate with decoder | |
3758 | ||
3759 | ||
3760 | ||
3761 | ||
3762 | ||
3763 | // any PARAMS parms go into naming of macro | |
3764 | ||
3765 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__width_64 ( | |
3766 | din0, | |
3767 | din1, | |
3768 | din2, | |
3769 | din3, | |
3770 | din4, | |
3771 | din5, | |
3772 | din6, | |
3773 | din7, | |
3774 | sel, | |
3775 | dout); | |
3776 | wire psel0; | |
3777 | wire psel1; | |
3778 | wire psel2; | |
3779 | wire psel3; | |
3780 | wire psel4; | |
3781 | wire psel5; | |
3782 | wire psel6; | |
3783 | wire psel7; | |
3784 | ||
3785 | input [63:0] din0; | |
3786 | input [63:0] din1; | |
3787 | input [63:0] din2; | |
3788 | input [63:0] din3; | |
3789 | input [63:0] din4; | |
3790 | input [63:0] din5; | |
3791 | input [63:0] din6; | |
3792 | input [63:0] din7; | |
3793 | input [2:0] sel; | |
3794 | output [63:0] dout; | |
3795 | ||
3796 | ||
3797 | ||
3798 | ||
3799 | ||
3800 | cl_dp1_pdec8_8x c0_0 ( | |
3801 | .test(1'b1), | |
3802 | .sel0(sel[0]), | |
3803 | .sel1(sel[1]), | |
3804 | .sel2(sel[2]), | |
3805 | .psel0(psel0), | |
3806 | .psel1(psel1), | |
3807 | .psel2(psel2), | |
3808 | .psel3(psel3), | |
3809 | .psel4(psel4), | |
3810 | .psel5(psel5), | |
3811 | .psel6(psel6), | |
3812 | .psel7(psel7) | |
3813 | ); | |
3814 | ||
3815 | mux8s #(64) d0_0 ( | |
3816 | .sel0(psel0), | |
3817 | .sel1(psel1), | |
3818 | .sel2(psel2), | |
3819 | .sel3(psel3), | |
3820 | .sel4(psel4), | |
3821 | .sel5(psel5), | |
3822 | .sel6(psel6), | |
3823 | .sel7(psel7), | |
3824 | .in0(din0[63:0]), | |
3825 | .in1(din1[63:0]), | |
3826 | .in2(din2[63:0]), | |
3827 | .in3(din3[63:0]), | |
3828 | .in4(din4[63:0]), | |
3829 | .in5(din5[63:0]), | |
3830 | .in6(din6[63:0]), | |
3831 | .in7(din7[63:0]), | |
3832 | .dout(dout[63:0]) | |
3833 | ); | |
3834 | ||
3835 | ||
3836 | ||
3837 | ||
3838 | ||
3839 | ||
3840 | ||
3841 | ||
3842 | ||
3843 | ||
3844 | ||
3845 | ||
3846 | ||
3847 | endmodule | |
3848 | ||
3849 | ||
3850 | // | |
3851 | // xnor macro for ports = 2,3 | |
3852 | // | |
3853 | // | |
3854 | ||
3855 | ||
3856 | ||
3857 | ||
3858 | ||
3859 | module fgu_fgd_dp_xnor_macro__ports_2__width_1 ( | |
3860 | din0, | |
3861 | din1, | |
3862 | dout); | |
3863 | input [0:0] din0; | |
3864 | input [0:0] din1; | |
3865 | output [0:0] dout; | |
3866 | ||
3867 | ||
3868 | ||
3869 | ||
3870 | ||
3871 | ||
3872 | xnor2 #(1) d0_0 ( | |
3873 | .in0(din0[0:0]), | |
3874 | .in1(din1[0:0]), | |
3875 | .out(dout[0:0]) | |
3876 | ); | |
3877 | ||
3878 | ||
3879 | ||
3880 | ||
3881 | ||
3882 | ||
3883 | ||
3884 | endmodule | |
3885 | ||
3886 | ||
3887 | ||
3888 | ||
3889 | ||
3890 | // | |
3891 | // nor macro for ports = 2,3 | |
3892 | // | |
3893 | // | |
3894 | ||
3895 | ||
3896 | ||
3897 | ||
3898 | ||
3899 | module fgu_fgd_dp_nor_macro__ports_2__width_1 ( | |
3900 | din0, | |
3901 | din1, | |
3902 | dout); | |
3903 | input [0:0] din0; | |
3904 | input [0:0] din1; | |
3905 | output [0:0] dout; | |
3906 | ||
3907 | ||
3908 | ||
3909 | ||
3910 | ||
3911 | ||
3912 | nor2 #(1) d0_0 ( | |
3913 | .in0(din0[0:0]), | |
3914 | .in1(din1[0:0]), | |
3915 | .out(dout[0:0]) | |
3916 | ); | |
3917 | ||
3918 | ||
3919 | ||
3920 | ||
3921 | ||
3922 | ||
3923 | ||
3924 | endmodule | |
3925 | ||
3926 | ||
3927 | ||
3928 | ||
3929 | ||
3930 | ||
3931 | ||
3932 | ||
3933 | ||
3934 | // any PARAMS parms go into naming of macro | |
3935 | ||
3936 | module fgu_fgd_dp_msff_macro__mux_aope__ports_6__width_64 ( | |
3937 | din0, | |
3938 | din1, | |
3939 | din2, | |
3940 | din3, | |
3941 | din4, | |
3942 | din5, | |
3943 | sel0, | |
3944 | sel1, | |
3945 | sel2, | |
3946 | sel3, | |
3947 | sel4, | |
3948 | clk, | |
3949 | en, | |
3950 | se, | |
3951 | scan_in, | |
3952 | siclk, | |
3953 | soclk, | |
3954 | pce_ov, | |
3955 | stop, | |
3956 | dout, | |
3957 | scan_out); | |
3958 | wire psel0; | |
3959 | wire psel1; | |
3960 | wire psel2; | |
3961 | wire psel3; | |
3962 | wire psel4; | |
3963 | wire psel5; | |
3964 | wire [63:0] muxout; | |
3965 | wire l1clk; | |
3966 | wire siclk_out; | |
3967 | wire soclk_out; | |
3968 | wire [62:0] so; | |
3969 | ||
3970 | input [63:0] din0; | |
3971 | input [63:0] din1; | |
3972 | input [63:0] din2; | |
3973 | input [63:0] din3; | |
3974 | input [63:0] din4; | |
3975 | input [63:0] din5; | |
3976 | input sel0; | |
3977 | input sel1; | |
3978 | input sel2; | |
3979 | input sel3; | |
3980 | input sel4; | |
3981 | ||
3982 | ||
3983 | input clk; | |
3984 | input en; | |
3985 | input se; | |
3986 | input scan_in; | |
3987 | input siclk; | |
3988 | input soclk; | |
3989 | input pce_ov; | |
3990 | input stop; | |
3991 | ||
3992 | ||
3993 | ||
3994 | output [63:0] dout; | |
3995 | ||
3996 | ||
3997 | output scan_out; | |
3998 | ||
3999 | ||
4000 | ||
4001 | ||
4002 | cl_dp1_penc6_8x c1_0 ( | |
4003 | .test(1'b1), | |
4004 | .sel0(sel0), | |
4005 | .sel1(sel1), | |
4006 | .sel2(sel2), | |
4007 | .sel3(sel3), | |
4008 | .sel4(sel4), | |
4009 | .psel0(psel0), | |
4010 | .psel1(psel1), | |
4011 | .psel2(psel2), | |
4012 | .psel3(psel3), | |
4013 | .psel4(psel4), | |
4014 | .psel5(psel5) | |
4015 | ); | |
4016 | ||
4017 | mux6s #(64) d1_0 ( | |
4018 | .sel0(psel0), | |
4019 | .sel1(psel1), | |
4020 | .sel2(psel2), | |
4021 | .sel3(psel3), | |
4022 | .sel4(psel4), | |
4023 | .sel5(psel5), | |
4024 | .in0(din0[63:0]), | |
4025 | .in1(din1[63:0]), | |
4026 | .in2(din2[63:0]), | |
4027 | .in3(din3[63:0]), | |
4028 | .in4(din4[63:0]), | |
4029 | .in5(din5[63:0]), | |
4030 | .dout(muxout[63:0]) | |
4031 | ); | |
4032 | cl_dp1_l1hdr_8x c0_0 ( | |
4033 | .l2clk(clk), | |
4034 | .pce(en), | |
4035 | .aclk(siclk), | |
4036 | .bclk(soclk), | |
4037 | .l1clk(l1clk), | |
4038 | .se(se), | |
4039 | .pce_ov(pce_ov), | |
4040 | .stop(stop), | |
4041 | .siclk_out(siclk_out), | |
4042 | .soclk_out(soclk_out) | |
4043 | ); | |
4044 | dff #(64) d0_0 ( | |
4045 | .l1clk(l1clk), | |
4046 | .siclk(siclk_out), | |
4047 | .soclk(soclk_out), | |
4048 | .d(muxout[63:0]), | |
4049 | .si({scan_in,so[62:0]}), | |
4050 | .so({so[62:0],scan_out}), | |
4051 | .q(dout[63:0]) | |
4052 | ); | |
4053 | ||
4054 | ||
4055 | ||
4056 | ||
4057 | ||
4058 | ||
4059 | ||
4060 | ||
4061 | ||
4062 | ||
4063 | ||
4064 | ||
4065 | ||
4066 | ||
4067 | ||
4068 | ||
4069 | ||
4070 | ||
4071 | ||
4072 | ||
4073 | endmodule | |
4074 | ||
4075 | ||
4076 | ||
4077 | ||
4078 | ||
4079 | ||
4080 | ||
4081 | ||
4082 | ||
4083 | // | |
4084 | // invert macro | |
4085 | // | |
4086 | // | |
4087 | ||
4088 | ||
4089 | ||
4090 | ||
4091 | ||
4092 | module fgu_fgd_dp_inv_macro__width_1 ( | |
4093 | din, | |
4094 | dout); | |
4095 | input [0:0] din; | |
4096 | output [0:0] dout; | |
4097 | ||
4098 | ||
4099 | ||
4100 | ||
4101 | ||
4102 | ||
4103 | inv #(1) d0_0 ( | |
4104 | .in(din[0:0]), | |
4105 | .out(dout[0:0]) | |
4106 | ); | |
4107 | ||
4108 | ||
4109 | ||
4110 | ||
4111 | ||
4112 | ||
4113 | ||
4114 | ||
4115 | ||
4116 | endmodule | |
4117 | ||
4118 | ||
4119 | ||
4120 | ||
4121 | ||
4122 | // | |
4123 | // nand macro for ports = 2,3,4 | |
4124 | // | |
4125 | // | |
4126 | ||
4127 | ||
4128 | ||
4129 | ||
4130 | ||
4131 | module fgu_fgd_dp_nand_macro__ports_2__width_1 ( | |
4132 | din0, | |
4133 | din1, | |
4134 | dout); | |
4135 | input [0:0] din0; | |
4136 | input [0:0] din1; | |
4137 | output [0:0] dout; | |
4138 | ||
4139 | ||
4140 | ||
4141 | ||
4142 | ||
4143 | ||
4144 | nand2 #(1) d0_0 ( | |
4145 | .in0(din0[0:0]), | |
4146 | .in1(din1[0:0]), | |
4147 | .out(dout[0:0]) | |
4148 | ); | |
4149 | ||
4150 | ||
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | ||
4157 | ||
4158 | endmodule | |
4159 | ||
4160 | ||
4161 | ||
4162 | ||
4163 | ||
4164 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4165 | // also for pass-gate with decoder | |
4166 | ||
4167 | ||
4168 | ||
4169 | ||
4170 | ||
4171 | // any PARAMS parms go into naming of macro | |
4172 | ||
4173 | module fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_32 ( | |
4174 | din0, | |
4175 | din1, | |
4176 | sel0, | |
4177 | dout); | |
4178 | wire psel0; | |
4179 | wire psel1; | |
4180 | ||
4181 | input [31:0] din0; | |
4182 | input [31:0] din1; | |
4183 | input sel0; | |
4184 | output [31:0] dout; | |
4185 | ||
4186 | ||
4187 | ||
4188 | ||
4189 | ||
4190 | cl_dp1_penc2_8x c0_0 ( | |
4191 | .sel0(sel0), | |
4192 | .psel0(psel0), | |
4193 | .psel1(psel1) | |
4194 | ); | |
4195 | ||
4196 | mux2s #(32) d0_0 ( | |
4197 | .sel0(psel0), | |
4198 | .sel1(psel1), | |
4199 | .in0(din0[31:0]), | |
4200 | .in1(din1[31:0]), | |
4201 | .dout(dout[31:0]) | |
4202 | ); | |
4203 | ||
4204 | ||
4205 | ||
4206 | ||
4207 | ||
4208 | ||
4209 | ||
4210 | ||
4211 | ||
4212 | ||
4213 | ||
4214 | ||
4215 | ||
4216 | endmodule | |
4217 | ||
4218 | ||
4219 | // | |
4220 | // and macro for ports = 2,3,4 | |
4221 | // | |
4222 | // | |
4223 | ||
4224 | ||
4225 | ||
4226 | ||
4227 | ||
4228 | module fgu_fgd_dp_and_macro__ports_2__width_12 ( | |
4229 | din0, | |
4230 | din1, | |
4231 | dout); | |
4232 | input [11:0] din0; | |
4233 | input [11:0] din1; | |
4234 | output [11:0] dout; | |
4235 | ||
4236 | ||
4237 | ||
4238 | ||
4239 | ||
4240 | ||
4241 | and2 #(12) d0_0 ( | |
4242 | .in0(din0[11:0]), | |
4243 | .in1(din1[11:0]), | |
4244 | .out(dout[11:0]) | |
4245 | ); | |
4246 | ||
4247 | ||
4248 | ||
4249 | ||
4250 | ||
4251 | ||
4252 | ||
4253 | ||
4254 | ||
4255 | endmodule | |
4256 | ||
4257 | ||
4258 | ||
4259 | ||
4260 | ||
4261 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4262 | // also for pass-gate with decoder | |
4263 | ||
4264 | ||
4265 | ||
4266 | ||
4267 | ||
4268 | // any PARAMS parms go into naming of macro | |
4269 | ||
4270 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_16 ( | |
4271 | din0, | |
4272 | din1, | |
4273 | din2, | |
4274 | din3, | |
4275 | sel, | |
4276 | dout); | |
4277 | wire psel0; | |
4278 | wire psel1; | |
4279 | wire psel2; | |
4280 | wire psel3; | |
4281 | ||
4282 | input [15:0] din0; | |
4283 | input [15:0] din1; | |
4284 | input [15:0] din2; | |
4285 | input [15:0] din3; | |
4286 | input [1:0] sel; | |
4287 | output [15:0] dout; | |
4288 | ||
4289 | ||
4290 | ||
4291 | ||
4292 | ||
4293 | cl_dp1_pdec4_8x c0_0 ( | |
4294 | .test(1'b1), | |
4295 | .sel0(sel[0]), | |
4296 | .sel1(sel[1]), | |
4297 | .psel0(psel0), | |
4298 | .psel1(psel1), | |
4299 | .psel2(psel2), | |
4300 | .psel3(psel3) | |
4301 | ); | |
4302 | ||
4303 | mux4s #(16) d0_0 ( | |
4304 | .sel0(psel0), | |
4305 | .sel1(psel1), | |
4306 | .sel2(psel2), | |
4307 | .sel3(psel3), | |
4308 | .in0(din0[15:0]), | |
4309 | .in1(din1[15:0]), | |
4310 | .in2(din2[15:0]), | |
4311 | .in3(din3[15:0]), | |
4312 | .dout(dout[15:0]) | |
4313 | ); | |
4314 | ||
4315 | ||
4316 | ||
4317 | ||
4318 | ||
4319 | ||
4320 | ||
4321 | ||
4322 | ||
4323 | ||
4324 | ||
4325 | ||
4326 | ||
4327 | endmodule | |
4328 | ||
4329 | ||
4330 | // | |
4331 | // and macro for ports = 2,3,4 | |
4332 | // | |
4333 | // | |
4334 | ||
4335 | ||
4336 | ||
4337 | ||
4338 | ||
4339 | module fgu_fgd_dp_and_macro__ports_2__width_3 ( | |
4340 | din0, | |
4341 | din1, | |
4342 | dout); | |
4343 | input [2:0] din0; | |
4344 | input [2:0] din1; | |
4345 | output [2:0] dout; | |
4346 | ||
4347 | ||
4348 | ||
4349 | ||
4350 | ||
4351 | ||
4352 | and2 #(3) d0_0 ( | |
4353 | .in0(din0[2:0]), | |
4354 | .in1(din1[2:0]), | |
4355 | .out(dout[2:0]) | |
4356 | ); | |
4357 | ||
4358 | ||
4359 | ||
4360 | ||
4361 | ||
4362 | ||
4363 | ||
4364 | ||
4365 | ||
4366 | endmodule | |
4367 | ||
4368 | ||
4369 | ||
4370 | ||
4371 | ||
4372 | // | |
4373 | // and macro for ports = 2,3,4 | |
4374 | // | |
4375 | // | |
4376 | ||
4377 | ||
4378 | ||
4379 | ||
4380 | ||
4381 | module fgu_fgd_dp_and_macro__ports_2__width_1 ( | |
4382 | din0, | |
4383 | din1, | |
4384 | dout); | |
4385 | input [0:0] din0; | |
4386 | input [0:0] din1; | |
4387 | output [0:0] dout; | |
4388 | ||
4389 | ||
4390 | ||
4391 | ||
4392 | ||
4393 | ||
4394 | and2 #(1) d0_0 ( | |
4395 | .in0(din0[0:0]), | |
4396 | .in1(din1[0:0]), | |
4397 | .out(dout[0:0]) | |
4398 | ); | |
4399 | ||
4400 | ||
4401 | ||
4402 | ||
4403 | ||
4404 | ||
4405 | ||
4406 | ||
4407 | ||
4408 | endmodule | |
4409 | ||
4410 | ||
4411 | ||
4412 | ||
4413 | ||
4414 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4415 | // also for pass-gate with decoder | |
4416 | ||
4417 | ||
4418 | ||
4419 | ||
4420 | ||
4421 | // any PARAMS parms go into naming of macro | |
4422 | ||
4423 | module fgu_fgd_dp_mux_macro__mux_aope__ports_2__width_16 ( | |
4424 | din0, | |
4425 | din1, | |
4426 | sel0, | |
4427 | dout); | |
4428 | wire psel0; | |
4429 | wire psel1; | |
4430 | ||
4431 | input [15:0] din0; | |
4432 | input [15:0] din1; | |
4433 | input sel0; | |
4434 | output [15:0] dout; | |
4435 | ||
4436 | ||
4437 | ||
4438 | ||
4439 | ||
4440 | cl_dp1_penc2_8x c0_0 ( | |
4441 | .sel0(sel0), | |
4442 | .psel0(psel0), | |
4443 | .psel1(psel1) | |
4444 | ); | |
4445 | ||
4446 | mux2s #(16) d0_0 ( | |
4447 | .sel0(psel0), | |
4448 | .sel1(psel1), | |
4449 | .in0(din0[15:0]), | |
4450 | .in1(din1[15:0]), | |
4451 | .dout(dout[15:0]) | |
4452 | ); | |
4453 | ||
4454 | ||
4455 | ||
4456 | ||
4457 | ||
4458 | ||
4459 | ||
4460 | ||
4461 | ||
4462 | ||
4463 | ||
4464 | ||
4465 | ||
4466 | endmodule | |
4467 | ||
4468 | ||
4469 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4470 | // also for pass-gate with decoder | |
4471 | ||
4472 | ||
4473 | ||
4474 | ||
4475 | ||
4476 | // any PARAMS parms go into naming of macro | |
4477 | ||
4478 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_28 ( | |
4479 | din0, | |
4480 | din1, | |
4481 | din2, | |
4482 | din3, | |
4483 | sel, | |
4484 | dout); | |
4485 | wire psel0; | |
4486 | wire psel1; | |
4487 | wire psel2; | |
4488 | wire psel3; | |
4489 | ||
4490 | input [27:0] din0; | |
4491 | input [27:0] din1; | |
4492 | input [27:0] din2; | |
4493 | input [27:0] din3; | |
4494 | input [1:0] sel; | |
4495 | output [27:0] dout; | |
4496 | ||
4497 | ||
4498 | ||
4499 | ||
4500 | ||
4501 | cl_dp1_pdec4_8x c0_0 ( | |
4502 | .test(1'b1), | |
4503 | .sel0(sel[0]), | |
4504 | .sel1(sel[1]), | |
4505 | .psel0(psel0), | |
4506 | .psel1(psel1), | |
4507 | .psel2(psel2), | |
4508 | .psel3(psel3) | |
4509 | ); | |
4510 | ||
4511 | mux4s #(28) d0_0 ( | |
4512 | .sel0(psel0), | |
4513 | .sel1(psel1), | |
4514 | .sel2(psel2), | |
4515 | .sel3(psel3), | |
4516 | .in0(din0[27:0]), | |
4517 | .in1(din1[27:0]), | |
4518 | .in2(din2[27:0]), | |
4519 | .in3(din3[27:0]), | |
4520 | .dout(dout[27:0]) | |
4521 | ); | |
4522 | ||
4523 | ||
4524 | ||
4525 | ||
4526 | ||
4527 | ||
4528 | ||
4529 | ||
4530 | ||
4531 | ||
4532 | ||
4533 | ||
4534 | ||
4535 | endmodule | |
4536 | ||
4537 | ||
4538 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4539 | // also for pass-gate with decoder | |
4540 | ||
4541 | ||
4542 | ||
4543 | ||
4544 | ||
4545 | // any PARAMS parms go into naming of macro | |
4546 | ||
4547 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_31 ( | |
4548 | din0, | |
4549 | din1, | |
4550 | din2, | |
4551 | din3, | |
4552 | sel, | |
4553 | dout); | |
4554 | wire psel0; | |
4555 | wire psel1; | |
4556 | wire psel2; | |
4557 | wire psel3; | |
4558 | ||
4559 | input [30:0] din0; | |
4560 | input [30:0] din1; | |
4561 | input [30:0] din2; | |
4562 | input [30:0] din3; | |
4563 | input [1:0] sel; | |
4564 | output [30:0] dout; | |
4565 | ||
4566 | ||
4567 | ||
4568 | ||
4569 | ||
4570 | cl_dp1_pdec4_8x c0_0 ( | |
4571 | .test(1'b1), | |
4572 | .sel0(sel[0]), | |
4573 | .sel1(sel[1]), | |
4574 | .psel0(psel0), | |
4575 | .psel1(psel1), | |
4576 | .psel2(psel2), | |
4577 | .psel3(psel3) | |
4578 | ); | |
4579 | ||
4580 | mux4s #(31) d0_0 ( | |
4581 | .sel0(psel0), | |
4582 | .sel1(psel1), | |
4583 | .sel2(psel2), | |
4584 | .sel3(psel3), | |
4585 | .in0(din0[30:0]), | |
4586 | .in1(din1[30:0]), | |
4587 | .in2(din2[30:0]), | |
4588 | .in3(din3[30:0]), | |
4589 | .dout(dout[30:0]) | |
4590 | ); | |
4591 | ||
4592 | ||
4593 | ||
4594 | ||
4595 | ||
4596 | ||
4597 | ||
4598 | ||
4599 | ||
4600 | ||
4601 | ||
4602 | ||
4603 | ||
4604 | endmodule | |
4605 | ||
4606 | ||
4607 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4608 | // also for pass-gate with decoder | |
4609 | ||
4610 | ||
4611 | ||
4612 | ||
4613 | ||
4614 | // any PARAMS parms go into naming of macro | |
4615 | ||
4616 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_12 ( | |
4617 | din0, | |
4618 | din1, | |
4619 | din2, | |
4620 | din3, | |
4621 | sel, | |
4622 | dout); | |
4623 | wire psel0; | |
4624 | wire psel1; | |
4625 | wire psel2; | |
4626 | wire psel3; | |
4627 | ||
4628 | input [11:0] din0; | |
4629 | input [11:0] din1; | |
4630 | input [11:0] din2; | |
4631 | input [11:0] din3; | |
4632 | input [1:0] sel; | |
4633 | output [11:0] dout; | |
4634 | ||
4635 | ||
4636 | ||
4637 | ||
4638 | ||
4639 | cl_dp1_pdec4_8x c0_0 ( | |
4640 | .test(1'b1), | |
4641 | .sel0(sel[0]), | |
4642 | .sel1(sel[1]), | |
4643 | .psel0(psel0), | |
4644 | .psel1(psel1), | |
4645 | .psel2(psel2), | |
4646 | .psel3(psel3) | |
4647 | ); | |
4648 | ||
4649 | mux4s #(12) d0_0 ( | |
4650 | .sel0(psel0), | |
4651 | .sel1(psel1), | |
4652 | .sel2(psel2), | |
4653 | .sel3(psel3), | |
4654 | .in0(din0[11:0]), | |
4655 | .in1(din1[11:0]), | |
4656 | .in2(din2[11:0]), | |
4657 | .in3(din3[11:0]), | |
4658 | .dout(dout[11:0]) | |
4659 | ); | |
4660 | ||
4661 | ||
4662 | ||
4663 | ||
4664 | ||
4665 | ||
4666 | ||
4667 | ||
4668 | ||
4669 | ||
4670 | ||
4671 | ||
4672 | ||
4673 | endmodule | |
4674 | ||
4675 | ||
4676 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4677 | // also for pass-gate with decoder | |
4678 | ||
4679 | ||
4680 | ||
4681 | ||
4682 | ||
4683 | // any PARAMS parms go into naming of macro | |
4684 | ||
4685 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_4__width_15 ( | |
4686 | din0, | |
4687 | din1, | |
4688 | din2, | |
4689 | din3, | |
4690 | sel, | |
4691 | dout); | |
4692 | wire psel0; | |
4693 | wire psel1; | |
4694 | wire psel2; | |
4695 | wire psel3; | |
4696 | ||
4697 | input [14:0] din0; | |
4698 | input [14:0] din1; | |
4699 | input [14:0] din2; | |
4700 | input [14:0] din3; | |
4701 | input [1:0] sel; | |
4702 | output [14:0] dout; | |
4703 | ||
4704 | ||
4705 | ||
4706 | ||
4707 | ||
4708 | cl_dp1_pdec4_8x c0_0 ( | |
4709 | .test(1'b1), | |
4710 | .sel0(sel[0]), | |
4711 | .sel1(sel[1]), | |
4712 | .psel0(psel0), | |
4713 | .psel1(psel1), | |
4714 | .psel2(psel2), | |
4715 | .psel3(psel3) | |
4716 | ); | |
4717 | ||
4718 | mux4s #(15) d0_0 ( | |
4719 | .sel0(psel0), | |
4720 | .sel1(psel1), | |
4721 | .sel2(psel2), | |
4722 | .sel3(psel3), | |
4723 | .in0(din0[14:0]), | |
4724 | .in1(din1[14:0]), | |
4725 | .in2(din2[14:0]), | |
4726 | .in3(din3[14:0]), | |
4727 | .dout(dout[14:0]) | |
4728 | ); | |
4729 | ||
4730 | ||
4731 | ||
4732 | ||
4733 | ||
4734 | ||
4735 | ||
4736 | ||
4737 | ||
4738 | ||
4739 | ||
4740 | ||
4741 | ||
4742 | endmodule | |
4743 | ||
4744 | ||
4745 | // | |
4746 | // cla macro | |
4747 | // | |
4748 | // | |
4749 | ||
4750 | ||
4751 | ||
4752 | ||
4753 | ||
4754 | module fgu_fgd_dp_cla_macro__width_8 ( | |
4755 | cin, | |
4756 | din0, | |
4757 | din1, | |
4758 | dout, | |
4759 | cout); | |
4760 | input cin; | |
4761 | input [7:0] din0; | |
4762 | input [7:0] din1; | |
4763 | output [7:0] dout; | |
4764 | output cout; | |
4765 | ||
4766 | ||
4767 | ||
4768 | ||
4769 | ||
4770 | ||
4771 | ||
4772 | cla #(8) m0_0 ( | |
4773 | .cin(cin), | |
4774 | .in0(din0[7:0]), | |
4775 | .in1(din1[7:0]), | |
4776 | .out(dout[7:0]), | |
4777 | .cout(cout) | |
4778 | ); | |
4779 | ||
4780 | ||
4781 | ||
4782 | ||
4783 | ||
4784 | ||
4785 | ||
4786 | ||
4787 | ||
4788 | ||
4789 | ||
4790 | ||
4791 | endmodule | |
4792 | ||
4793 | ||
4794 | ||
4795 | ||
4796 | ||
4797 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
4798 | // also for pass-gate with decoder | |
4799 | ||
4800 | ||
4801 | ||
4802 | ||
4803 | ||
4804 | // any PARAMS parms go into naming of macro | |
4805 | ||
4806 | module fgu_fgd_dp_mux_macro__mux_aope__ports_3__width_8 ( | |
4807 | din0, | |
4808 | din1, | |
4809 | din2, | |
4810 | sel0, | |
4811 | sel1, | |
4812 | dout); | |
4813 | wire psel0; | |
4814 | wire psel1; | |
4815 | wire psel2; | |
4816 | ||
4817 | input [7:0] din0; | |
4818 | input [7:0] din1; | |
4819 | input [7:0] din2; | |
4820 | input sel0; | |
4821 | input sel1; | |
4822 | output [7:0] dout; | |
4823 | ||
4824 | ||
4825 | ||
4826 | ||
4827 | ||
4828 | cl_dp1_penc3_8x c0_0 ( | |
4829 | .test(1'b1), | |
4830 | .sel0(sel0), | |
4831 | .sel1(sel1), | |
4832 | .psel0(psel0), | |
4833 | .psel1(psel1), | |
4834 | .psel2(psel2) | |
4835 | ); | |
4836 | ||
4837 | mux3s #(8) d0_0 ( | |
4838 | .sel0(psel0), | |
4839 | .sel1(psel1), | |
4840 | .sel2(psel2), | |
4841 | .in0(din0[7:0]), | |
4842 | .in1(din1[7:0]), | |
4843 | .in2(din2[7:0]), | |
4844 | .dout(dout[7:0]) | |
4845 | ); | |
4846 | ||
4847 | ||
4848 | ||
4849 | ||
4850 | ||
4851 | ||
4852 | ||
4853 | ||
4854 | ||
4855 | ||
4856 | ||
4857 | ||
4858 | ||
4859 | endmodule | |
4860 | ||
4861 | ||
4862 | // | |
4863 | // 4:2 Carry Save Adder | |
4864 | // | |
4865 | // | |
4866 | // i0 i1 i2 i3 | co | carry sum | |
4867 | // ------------|----|----------- | |
4868 | // 0 0 0 0 | 0 | 0 cin | |
4869 | // 0 0 0 1 | 0 | cin ~cin | |
4870 | // 0 0 1 0 | 0 | cin ~cin | |
4871 | // 0 0 1 1 | 0 | 1 cin | |
4872 | // | |
4873 | // 0 1 0 0 | 0 | cin ~cin | |
4874 | // 0 1 0 1 | 0 | 1 cin | |
4875 | // 0 1 1 0 | 1 | 0 cin | |
4876 | // 0 1 1 1 | 1 | cin ~cin | |
4877 | // | |
4878 | // 1 0 0 0 | 0 | cin ~cin | |
4879 | // 1 0 0 1 | 0 | 1 cin | |
4880 | // 1 0 1 0 | 1 | 0 cin | |
4881 | // 1 0 1 1 | 1 | cin ~cin | |
4882 | // | |
4883 | // 1 1 0 0 | 1 | 0 cin | |
4884 | // 1 1 0 1 | 1 | cin ~cin | |
4885 | // 1 1 1 0 | 1 | cin ~cin | |
4886 | // 1 1 1 1 | 1 | 1 cin | |
4887 | ||
4888 | ||
4889 | // This circuit looks like a compression of 5 terms down | |
4890 | // to 3 term on an individual bit basis. However, the fast | |
4891 | // output "co" from bit position "n" is actually the late input | |
4892 | // "cin" on bit position "n+1". Once a wrapper is written | |
4893 | // around multiple bits, this circuit will give the | |
4894 | // appearance of compressing 4 inputs down to 2 outputs. | |
4895 | ||
4896 | ||
4897 | ||
4898 | ||
4899 | ||
4900 | // any PARAMS parms go into naming of macro | |
4901 | ||
4902 | ||
4903 | module fgu_fgd_dp_csa42_macro__width_8 ( | |
4904 | i0, | |
4905 | i1, | |
4906 | i2, | |
4907 | i3, | |
4908 | cin, | |
4909 | cout, | |
4910 | carry, | |
4911 | sum); | |
4912 | input [7:0] i0; | |
4913 | input [7:0] i1; | |
4914 | input [7:0] i2; | |
4915 | input [7:0] i3; | |
4916 | input cin; | |
4917 | output cout; | |
4918 | output [7:0] carry; | |
4919 | output [7:0] sum; | |
4920 | ||
4921 | ||
4922 | ||
4923 | ||
4924 | ||
4925 | ||
4926 | csa42 #(8) d0_0 ( | |
4927 | .cin(cin), | |
4928 | .in0(i0[7:0]), | |
4929 | .in1(i1[7:0]), | |
4930 | .in2(i2[7:0]), | |
4931 | .in3(i3[7:0]), | |
4932 | .cout(cout), | |
4933 | .carry(carry[7:0]), | |
4934 | .sum(sum[7:0]) | |
4935 | ); | |
4936 | ||
4937 | ||
4938 | ||
4939 | ||
4940 | ||
4941 | ||
4942 | ||
4943 | ||
4944 | endmodule | |
4945 | ||
4946 | ||
4947 | ||
4948 | ||
4949 | ||
4950 | ||
4951 | ||
4952 | ||
4953 | // any PARAMS parms go into naming of macro | |
4954 | ||
4955 | module fgu_fgd_dp_msff_macro__width_48 ( | |
4956 | din, | |
4957 | clk, | |
4958 | en, | |
4959 | se, | |
4960 | scan_in, | |
4961 | siclk, | |
4962 | soclk, | |
4963 | pce_ov, | |
4964 | stop, | |
4965 | dout, | |
4966 | scan_out); | |
4967 | wire l1clk; | |
4968 | wire siclk_out; | |
4969 | wire soclk_out; | |
4970 | wire [46:0] so; | |
4971 | ||
4972 | input [47:0] din; | |
4973 | ||
4974 | ||
4975 | input clk; | |
4976 | input en; | |
4977 | input se; | |
4978 | input scan_in; | |
4979 | input siclk; | |
4980 | input soclk; | |
4981 | input pce_ov; | |
4982 | input stop; | |
4983 | ||
4984 | ||
4985 | ||
4986 | output [47:0] dout; | |
4987 | ||
4988 | ||
4989 | output scan_out; | |
4990 | ||
4991 | ||
4992 | ||
4993 | ||
4994 | cl_dp1_l1hdr_8x c0_0 ( | |
4995 | .l2clk(clk), | |
4996 | .pce(en), | |
4997 | .aclk(siclk), | |
4998 | .bclk(soclk), | |
4999 | .l1clk(l1clk), | |
5000 | .se(se), | |
5001 | .pce_ov(pce_ov), | |
5002 | .stop(stop), | |
5003 | .siclk_out(siclk_out), | |
5004 | .soclk_out(soclk_out) | |
5005 | ); | |
5006 | dff #(48) d0_0 ( | |
5007 | .l1clk(l1clk), | |
5008 | .siclk(siclk_out), | |
5009 | .soclk(soclk_out), | |
5010 | .d(din[47:0]), | |
5011 | .si({scan_in,so[46:0]}), | |
5012 | .so({so[46:0],scan_out}), | |
5013 | .q(dout[47:0]) | |
5014 | ); | |
5015 | ||
5016 | ||
5017 | ||
5018 | ||
5019 | ||
5020 | ||
5021 | ||
5022 | ||
5023 | ||
5024 | ||
5025 | ||
5026 | ||
5027 | ||
5028 | ||
5029 | ||
5030 | ||
5031 | ||
5032 | ||
5033 | ||
5034 | ||
5035 | endmodule | |
5036 | ||
5037 | ||
5038 | ||
5039 | ||
5040 | ||
5041 | ||
5042 | ||
5043 | ||
5044 | ||
5045 | ||
5046 | ||
5047 | ||
5048 | ||
5049 | // any PARAMS parms go into naming of macro | |
5050 | ||
5051 | module fgu_fgd_dp_msff_macro__width_50 ( | |
5052 | din, | |
5053 | clk, | |
5054 | en, | |
5055 | se, | |
5056 | scan_in, | |
5057 | siclk, | |
5058 | soclk, | |
5059 | pce_ov, | |
5060 | stop, | |
5061 | dout, | |
5062 | scan_out); | |
5063 | wire l1clk; | |
5064 | wire siclk_out; | |
5065 | wire soclk_out; | |
5066 | wire [48:0] so; | |
5067 | ||
5068 | input [49:0] din; | |
5069 | ||
5070 | ||
5071 | input clk; | |
5072 | input en; | |
5073 | input se; | |
5074 | input scan_in; | |
5075 | input siclk; | |
5076 | input soclk; | |
5077 | input pce_ov; | |
5078 | input stop; | |
5079 | ||
5080 | ||
5081 | ||
5082 | output [49:0] dout; | |
5083 | ||
5084 | ||
5085 | output scan_out; | |
5086 | ||
5087 | ||
5088 | ||
5089 | ||
5090 | cl_dp1_l1hdr_8x c0_0 ( | |
5091 | .l2clk(clk), | |
5092 | .pce(en), | |
5093 | .aclk(siclk), | |
5094 | .bclk(soclk), | |
5095 | .l1clk(l1clk), | |
5096 | .se(se), | |
5097 | .pce_ov(pce_ov), | |
5098 | .stop(stop), | |
5099 | .siclk_out(siclk_out), | |
5100 | .soclk_out(soclk_out) | |
5101 | ); | |
5102 | dff #(50) d0_0 ( | |
5103 | .l1clk(l1clk), | |
5104 | .siclk(siclk_out), | |
5105 | .soclk(soclk_out), | |
5106 | .d(din[49:0]), | |
5107 | .si({scan_in,so[48:0]}), | |
5108 | .so({so[48:0],scan_out}), | |
5109 | .q(dout[49:0]) | |
5110 | ); | |
5111 | ||
5112 | ||
5113 | ||
5114 | ||
5115 | ||
5116 | ||
5117 | ||
5118 | ||
5119 | ||
5120 | ||
5121 | ||
5122 | ||
5123 | ||
5124 | ||
5125 | ||
5126 | ||
5127 | ||
5128 | ||
5129 | ||
5130 | ||
5131 | endmodule | |
5132 | ||
5133 | ||
5134 | ||
5135 | ||
5136 | ||
5137 | ||
5138 | ||
5139 | ||
5140 | ||
5141 | ||
5142 | ||
5143 | ||
5144 | ||
5145 | // any PARAMS parms go into naming of macro | |
5146 | ||
5147 | module fgu_fgd_dp_msff_macro__width_62 ( | |
5148 | din, | |
5149 | clk, | |
5150 | en, | |
5151 | se, | |
5152 | scan_in, | |
5153 | siclk, | |
5154 | soclk, | |
5155 | pce_ov, | |
5156 | stop, | |
5157 | dout, | |
5158 | scan_out); | |
5159 | wire l1clk; | |
5160 | wire siclk_out; | |
5161 | wire soclk_out; | |
5162 | wire [60:0] so; | |
5163 | ||
5164 | input [61:0] din; | |
5165 | ||
5166 | ||
5167 | input clk; | |
5168 | input en; | |
5169 | input se; | |
5170 | input scan_in; | |
5171 | input siclk; | |
5172 | input soclk; | |
5173 | input pce_ov; | |
5174 | input stop; | |
5175 | ||
5176 | ||
5177 | ||
5178 | output [61:0] dout; | |
5179 | ||
5180 | ||
5181 | output scan_out; | |
5182 | ||
5183 | ||
5184 | ||
5185 | ||
5186 | cl_dp1_l1hdr_8x c0_0 ( | |
5187 | .l2clk(clk), | |
5188 | .pce(en), | |
5189 | .aclk(siclk), | |
5190 | .bclk(soclk), | |
5191 | .l1clk(l1clk), | |
5192 | .se(se), | |
5193 | .pce_ov(pce_ov), | |
5194 | .stop(stop), | |
5195 | .siclk_out(siclk_out), | |
5196 | .soclk_out(soclk_out) | |
5197 | ); | |
5198 | dff #(62) d0_0 ( | |
5199 | .l1clk(l1clk), | |
5200 | .siclk(siclk_out), | |
5201 | .soclk(soclk_out), | |
5202 | .d(din[61:0]), | |
5203 | .si({scan_in,so[60:0]}), | |
5204 | .so({so[60:0],scan_out}), | |
5205 | .q(dout[61:0]) | |
5206 | ); | |
5207 | ||
5208 | ||
5209 | ||
5210 | ||
5211 | ||
5212 | ||
5213 | ||
5214 | ||
5215 | ||
5216 | ||
5217 | ||
5218 | ||
5219 | ||
5220 | ||
5221 | ||
5222 | ||
5223 | ||
5224 | ||
5225 | ||
5226 | ||
5227 | endmodule | |
5228 | ||
5229 | ||
5230 | ||
5231 | ||
5232 | ||
5233 | ||
5234 | ||
5235 | ||
5236 | ||
5237 | ||
5238 | ||
5239 | ||
5240 | ||
5241 | // any PARAMS parms go into naming of macro | |
5242 | ||
5243 | module fgu_fgd_dp_msff_macro__width_37 ( | |
5244 | din, | |
5245 | clk, | |
5246 | en, | |
5247 | se, | |
5248 | scan_in, | |
5249 | siclk, | |
5250 | soclk, | |
5251 | pce_ov, | |
5252 | stop, | |
5253 | dout, | |
5254 | scan_out); | |
5255 | wire l1clk; | |
5256 | wire siclk_out; | |
5257 | wire soclk_out; | |
5258 | wire [35:0] so; | |
5259 | ||
5260 | input [36:0] din; | |
5261 | ||
5262 | ||
5263 | input clk; | |
5264 | input en; | |
5265 | input se; | |
5266 | input scan_in; | |
5267 | input siclk; | |
5268 | input soclk; | |
5269 | input pce_ov; | |
5270 | input stop; | |
5271 | ||
5272 | ||
5273 | ||
5274 | output [36:0] dout; | |
5275 | ||
5276 | ||
5277 | output scan_out; | |
5278 | ||
5279 | ||
5280 | ||
5281 | ||
5282 | cl_dp1_l1hdr_8x c0_0 ( | |
5283 | .l2clk(clk), | |
5284 | .pce(en), | |
5285 | .aclk(siclk), | |
5286 | .bclk(soclk), | |
5287 | .l1clk(l1clk), | |
5288 | .se(se), | |
5289 | .pce_ov(pce_ov), | |
5290 | .stop(stop), | |
5291 | .siclk_out(siclk_out), | |
5292 | .soclk_out(soclk_out) | |
5293 | ); | |
5294 | dff #(37) d0_0 ( | |
5295 | .l1clk(l1clk), | |
5296 | .siclk(siclk_out), | |
5297 | .soclk(soclk_out), | |
5298 | .d(din[36:0]), | |
5299 | .si({scan_in,so[35:0]}), | |
5300 | .so({so[35:0],scan_out}), | |
5301 | .q(dout[36:0]) | |
5302 | ); | |
5303 | ||
5304 | ||
5305 | ||
5306 | ||
5307 | ||
5308 | ||
5309 | ||
5310 | ||
5311 | ||
5312 | ||
5313 | ||
5314 | ||
5315 | ||
5316 | ||
5317 | ||
5318 | ||
5319 | ||
5320 | ||
5321 | ||
5322 | ||
5323 | endmodule | |
5324 | ||
5325 | ||
5326 | ||
5327 | ||
5328 | ||
5329 | ||
5330 | ||
5331 | ||
5332 | ||
5333 | ||
5334 | ||
5335 | ||
5336 | ||
5337 | // any PARAMS parms go into naming of macro | |
5338 | ||
5339 | module fgu_fgd_dp_msff_macro__width_34 ( | |
5340 | din, | |
5341 | clk, | |
5342 | en, | |
5343 | se, | |
5344 | scan_in, | |
5345 | siclk, | |
5346 | soclk, | |
5347 | pce_ov, | |
5348 | stop, | |
5349 | dout, | |
5350 | scan_out); | |
5351 | wire l1clk; | |
5352 | wire siclk_out; | |
5353 | wire soclk_out; | |
5354 | wire [32:0] so; | |
5355 | ||
5356 | input [33:0] din; | |
5357 | ||
5358 | ||
5359 | input clk; | |
5360 | input en; | |
5361 | input se; | |
5362 | input scan_in; | |
5363 | input siclk; | |
5364 | input soclk; | |
5365 | input pce_ov; | |
5366 | input stop; | |
5367 | ||
5368 | ||
5369 | ||
5370 | output [33:0] dout; | |
5371 | ||
5372 | ||
5373 | output scan_out; | |
5374 | ||
5375 | ||
5376 | ||
5377 | ||
5378 | cl_dp1_l1hdr_8x c0_0 ( | |
5379 | .l2clk(clk), | |
5380 | .pce(en), | |
5381 | .aclk(siclk), | |
5382 | .bclk(soclk), | |
5383 | .l1clk(l1clk), | |
5384 | .se(se), | |
5385 | .pce_ov(pce_ov), | |
5386 | .stop(stop), | |
5387 | .siclk_out(siclk_out), | |
5388 | .soclk_out(soclk_out) | |
5389 | ); | |
5390 | dff #(34) d0_0 ( | |
5391 | .l1clk(l1clk), | |
5392 | .siclk(siclk_out), | |
5393 | .soclk(soclk_out), | |
5394 | .d(din[33:0]), | |
5395 | .si({scan_in,so[32:0]}), | |
5396 | .so({so[32:0],scan_out}), | |
5397 | .q(dout[33:0]) | |
5398 | ); | |
5399 | ||
5400 | ||
5401 | ||
5402 | ||
5403 | ||
5404 | ||
5405 | ||
5406 | ||
5407 | ||
5408 | ||
5409 | ||
5410 | ||
5411 | ||
5412 | ||
5413 | ||
5414 | ||
5415 | ||
5416 | ||
5417 | ||
5418 | ||
5419 | endmodule | |
5420 | ||
5421 | ||
5422 | ||
5423 | ||
5424 | ||
5425 | ||
5426 | ||
5427 | ||
5428 | ||
5429 | ||
5430 | ||
5431 | ||
5432 | ||
5433 | // any PARAMS parms go into naming of macro | |
5434 | ||
5435 | module fgu_fgd_dp_msff_macro__stack_32l__width_6 ( | |
5436 | din, | |
5437 | clk, | |
5438 | en, | |
5439 | se, | |
5440 | scan_in, | |
5441 | siclk, | |
5442 | soclk, | |
5443 | pce_ov, | |
5444 | stop, | |
5445 | dout, | |
5446 | scan_out); | |
5447 | wire l1clk; | |
5448 | wire siclk_out; | |
5449 | wire soclk_out; | |
5450 | wire [4:0] so; | |
5451 | ||
5452 | input [5:0] din; | |
5453 | ||
5454 | ||
5455 | input clk; | |
5456 | input en; | |
5457 | input se; | |
5458 | input scan_in; | |
5459 | input siclk; | |
5460 | input soclk; | |
5461 | input pce_ov; | |
5462 | input stop; | |
5463 | ||
5464 | ||
5465 | ||
5466 | output [5:0] dout; | |
5467 | ||
5468 | ||
5469 | output scan_out; | |
5470 | ||
5471 | ||
5472 | ||
5473 | ||
5474 | cl_dp1_l1hdr_8x c0_0 ( | |
5475 | .l2clk(clk), | |
5476 | .pce(en), | |
5477 | .aclk(siclk), | |
5478 | .bclk(soclk), | |
5479 | .l1clk(l1clk), | |
5480 | .se(se), | |
5481 | .pce_ov(pce_ov), | |
5482 | .stop(stop), | |
5483 | .siclk_out(siclk_out), | |
5484 | .soclk_out(soclk_out) | |
5485 | ); | |
5486 | dff #(6) d0_0 ( | |
5487 | .l1clk(l1clk), | |
5488 | .siclk(siclk_out), | |
5489 | .soclk(soclk_out), | |
5490 | .d(din[5:0]), | |
5491 | .si({scan_in,so[4:0]}), | |
5492 | .so({so[4:0],scan_out}), | |
5493 | .q(dout[5:0]) | |
5494 | ); | |
5495 | ||
5496 | ||
5497 | ||
5498 | ||
5499 | ||
5500 | ||
5501 | ||
5502 | ||
5503 | ||
5504 | ||
5505 | ||
5506 | ||
5507 | ||
5508 | ||
5509 | ||
5510 | ||
5511 | ||
5512 | ||
5513 | ||
5514 | ||
5515 | endmodule | |
5516 | ||
5517 | ||
5518 | ||
5519 | ||
5520 | ||
5521 | ||
5522 | ||
5523 | ||
5524 | ||
5525 | ||
5526 | ||
5527 | ||
5528 | ||
5529 | // any PARAMS parms go into naming of macro | |
5530 | ||
5531 | module fgu_fgd_dp_msff_macro__mux_aope__ports_2__stack_32l__width_32 ( | |
5532 | din0, | |
5533 | din1, | |
5534 | sel0, | |
5535 | clk, | |
5536 | en, | |
5537 | se, | |
5538 | scan_in, | |
5539 | siclk, | |
5540 | soclk, | |
5541 | pce_ov, | |
5542 | stop, | |
5543 | dout, | |
5544 | scan_out); | |
5545 | wire psel0; | |
5546 | wire psel1; | |
5547 | wire [31:0] muxout; | |
5548 | wire l1clk; | |
5549 | wire siclk_out; | |
5550 | wire soclk_out; | |
5551 | wire [30:0] so; | |
5552 | ||
5553 | input [31:0] din0; | |
5554 | input [31:0] din1; | |
5555 | input sel0; | |
5556 | ||
5557 | ||
5558 | input clk; | |
5559 | input en; | |
5560 | input se; | |
5561 | input scan_in; | |
5562 | input siclk; | |
5563 | input soclk; | |
5564 | input pce_ov; | |
5565 | input stop; | |
5566 | ||
5567 | ||
5568 | ||
5569 | output [31:0] dout; | |
5570 | ||
5571 | ||
5572 | output scan_out; | |
5573 | ||
5574 | ||
5575 | ||
5576 | ||
5577 | cl_dp1_penc2_8x c1_0 ( | |
5578 | .sel0(sel0), | |
5579 | .psel0(psel0), | |
5580 | .psel1(psel1) | |
5581 | ); | |
5582 | ||
5583 | mux2s #(32) d1_0 ( | |
5584 | .sel0(psel0), | |
5585 | .sel1(psel1), | |
5586 | .in0(din0[31:0]), | |
5587 | .in1(din1[31:0]), | |
5588 | .dout(muxout[31:0]) | |
5589 | ); | |
5590 | cl_dp1_l1hdr_8x c0_0 ( | |
5591 | .l2clk(clk), | |
5592 | .pce(en), | |
5593 | .aclk(siclk), | |
5594 | .bclk(soclk), | |
5595 | .l1clk(l1clk), | |
5596 | .se(se), | |
5597 | .pce_ov(pce_ov), | |
5598 | .stop(stop), | |
5599 | .siclk_out(siclk_out), | |
5600 | .soclk_out(soclk_out) | |
5601 | ); | |
5602 | dff #(32) d0_0 ( | |
5603 | .l1clk(l1clk), | |
5604 | .siclk(siclk_out), | |
5605 | .soclk(soclk_out), | |
5606 | .d(muxout[31:0]), | |
5607 | .si({scan_in,so[30:0]}), | |
5608 | .so({so[30:0],scan_out}), | |
5609 | .q(dout[31:0]) | |
5610 | ); | |
5611 | ||
5612 | ||
5613 | ||
5614 | ||
5615 | ||
5616 | ||
5617 | ||
5618 | ||
5619 | ||
5620 | ||
5621 | ||
5622 | ||
5623 | ||
5624 | ||
5625 | ||
5626 | ||
5627 | ||
5628 | ||
5629 | ||
5630 | ||
5631 | endmodule | |
5632 | ||
5633 | ||
5634 | ||
5635 | ||
5636 | ||
5637 | ||
5638 | ||
5639 | ||
5640 | ||
5641 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5642 | // also for pass-gate with decoder | |
5643 | ||
5644 | ||
5645 | ||
5646 | ||
5647 | ||
5648 | // any PARAMS parms go into naming of macro | |
5649 | ||
5650 | module fgu_fgd_dp_mux_macro__mux_aodec__ports_8__stack_32l__width_32 ( | |
5651 | din0, | |
5652 | din1, | |
5653 | din2, | |
5654 | din3, | |
5655 | din4, | |
5656 | din5, | |
5657 | din6, | |
5658 | din7, | |
5659 | sel, | |
5660 | dout); | |
5661 | wire psel0; | |
5662 | wire psel1; | |
5663 | wire psel2; | |
5664 | wire psel3; | |
5665 | wire psel4; | |
5666 | wire psel5; | |
5667 | wire psel6; | |
5668 | wire psel7; | |
5669 | ||
5670 | input [31:0] din0; | |
5671 | input [31:0] din1; | |
5672 | input [31:0] din2; | |
5673 | input [31:0] din3; | |
5674 | input [31:0] din4; | |
5675 | input [31:0] din5; | |
5676 | input [31:0] din6; | |
5677 | input [31:0] din7; | |
5678 | input [2:0] sel; | |
5679 | output [31:0] dout; | |
5680 | ||
5681 | ||
5682 | ||
5683 | ||
5684 | ||
5685 | cl_dp1_pdec8_8x c0_0 ( | |
5686 | .test(1'b1), | |
5687 | .sel0(sel[0]), | |
5688 | .sel1(sel[1]), | |
5689 | .sel2(sel[2]), | |
5690 | .psel0(psel0), | |
5691 | .psel1(psel1), | |
5692 | .psel2(psel2), | |
5693 | .psel3(psel3), | |
5694 | .psel4(psel4), | |
5695 | .psel5(psel5), | |
5696 | .psel6(psel6), | |
5697 | .psel7(psel7) | |
5698 | ); | |
5699 | ||
5700 | mux8s #(32) d0_0 ( | |
5701 | .sel0(psel0), | |
5702 | .sel1(psel1), | |
5703 | .sel2(psel2), | |
5704 | .sel3(psel3), | |
5705 | .sel4(psel4), | |
5706 | .sel5(psel5), | |
5707 | .sel6(psel6), | |
5708 | .sel7(psel7), | |
5709 | .in0(din0[31:0]), | |
5710 | .in1(din1[31:0]), | |
5711 | .in2(din2[31:0]), | |
5712 | .in3(din3[31:0]), | |
5713 | .in4(din4[31:0]), | |
5714 | .in5(din5[31:0]), | |
5715 | .in6(din6[31:0]), | |
5716 | .in7(din7[31:0]), | |
5717 | .dout(dout[31:0]) | |
5718 | ); | |
5719 | ||
5720 | ||
5721 | ||
5722 | ||
5723 | ||
5724 | ||
5725 | ||
5726 | ||
5727 | ||
5728 | ||
5729 | ||
5730 | ||
5731 | ||
5732 | endmodule | |
5733 | ||
5734 | ||
5735 | // | |
5736 | // buff macro | |
5737 | // | |
5738 | // | |
5739 | ||
5740 | ||
5741 | ||
5742 | ||
5743 | ||
5744 | module fgu_fgd_dp_buff_macro__stack_32l__width_32 ( | |
5745 | din, | |
5746 | dout); | |
5747 | input [31:0] din; | |
5748 | output [31:0] dout; | |
5749 | ||
5750 | ||
5751 | ||
5752 | ||
5753 | ||
5754 | ||
5755 | buff #(32) d0_0 ( | |
5756 | .in(din[31:0]), | |
5757 | .out(dout[31:0]) | |
5758 | ); | |
5759 | ||
5760 | ||
5761 | ||
5762 | ||
5763 | ||
5764 | ||
5765 | ||
5766 | ||
5767 | endmodule | |
5768 | ||
5769 | ||
5770 | ||
5771 | ||
5772 | ||
5773 | // | |
5774 | // buff macro | |
5775 | // | |
5776 | // | |
5777 | ||
5778 | ||
5779 | ||
5780 | ||
5781 | ||
5782 | module fgu_fgd_dp_buff_macro__dbuff_48x__stack_32l__width_1 ( | |
5783 | din, | |
5784 | dout); | |
5785 | input [0:0] din; | |
5786 | output [0:0] dout; | |
5787 | ||
5788 | ||
5789 | ||
5790 | ||
5791 | ||
5792 | ||
5793 | buff #(1) d0_0 ( | |
5794 | .in(din[0:0]), | |
5795 | .out(dout[0:0]) | |
5796 | ); | |
5797 | ||
5798 | ||
5799 | ||
5800 | ||
5801 | ||
5802 | ||
5803 | ||
5804 | ||
5805 | endmodule | |
5806 | ||
5807 | ||
5808 | ||
5809 | ||
5810 | ||
5811 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
5812 | // also for pass-gate with decoder | |
5813 | ||
5814 | ||
5815 | ||
5816 | ||
5817 | ||
5818 | // any PARAMS parms go into naming of macro | |
5819 | ||
5820 | module fgu_fgd_dp_mux_macro__mux_pgdec__ports_8__stack_32l__width_32 ( | |
5821 | din0, | |
5822 | din1, | |
5823 | din2, | |
5824 | din3, | |
5825 | din4, | |
5826 | din5, | |
5827 | din6, | |
5828 | din7, | |
5829 | sel, | |
5830 | muxtst, | |
5831 | test, | |
5832 | dout); | |
5833 | wire psel0; | |
5834 | wire psel1; | |
5835 | wire psel2; | |
5836 | wire psel3; | |
5837 | wire psel4; | |
5838 | wire psel5; | |
5839 | wire psel6; | |
5840 | wire psel7; | |
5841 | ||
5842 | input [31:0] din0; | |
5843 | input [31:0] din1; | |
5844 | input [31:0] din2; | |
5845 | input [31:0] din3; | |
5846 | input [31:0] din4; | |
5847 | input [31:0] din5; | |
5848 | input [31:0] din6; | |
5849 | input [31:0] din7; | |
5850 | input [2:0] sel; | |
5851 | input muxtst; | |
5852 | input test; | |
5853 | output [31:0] dout; | |
5854 | ||
5855 | ||
5856 | ||
5857 | ||
5858 | ||
5859 | cl_dp1_pdec8_8x c0_0 ( | |
5860 | .sel0(sel[0]), | |
5861 | .sel1(sel[1]), | |
5862 | .sel2(sel[2]), | |
5863 | .psel0(psel0), | |
5864 | .psel1(psel1), | |
5865 | .psel2(psel2), | |
5866 | .psel3(psel3), | |
5867 | .psel4(psel4), | |
5868 | .psel5(psel5), | |
5869 | .psel6(psel6), | |
5870 | .psel7(psel7), | |
5871 | .test(test) | |
5872 | ); | |
5873 | ||
5874 | mux8 #(32) d0_0 ( | |
5875 | .sel0(psel0), | |
5876 | .sel1(psel1), | |
5877 | .sel2(psel2), | |
5878 | .sel3(psel3), | |
5879 | .sel4(psel4), | |
5880 | .sel5(psel5), | |
5881 | .sel6(psel6), | |
5882 | .sel7(psel7), | |
5883 | .in0(din0[31:0]), | |
5884 | .in1(din1[31:0]), | |
5885 | .in2(din2[31:0]), | |
5886 | .in3(din3[31:0]), | |
5887 | .in4(din4[31:0]), | |
5888 | .in5(din5[31:0]), | |
5889 | .in6(din6[31:0]), | |
5890 | .in7(din7[31:0]), | |
5891 | .dout(dout[31:0]), | |
5892 | .muxtst(muxtst) | |
5893 | ); | |
5894 | ||
5895 | ||
5896 | ||
5897 | ||
5898 | ||
5899 | ||
5900 | ||
5901 | ||
5902 | ||
5903 | ||
5904 | ||
5905 | ||
5906 | ||
5907 | endmodule | |
5908 | ||
5909 | ||
5910 | // | |
5911 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
5912 | // | |
5913 | // | |
5914 | ||
5915 | ||
5916 | ||
5917 | ||
5918 | ||
5919 | module fgu_fgd_dp_zero_macro__width_32 ( | |
5920 | din, | |
5921 | dout); | |
5922 | input [31:0] din; | |
5923 | output dout; | |
5924 | ||
5925 | ||
5926 | ||
5927 | ||
5928 | ||
5929 | ||
5930 | zero #(32) m0_0 ( | |
5931 | .in(din[31:0]), | |
5932 | .out(dout) | |
5933 | ); | |
5934 | ||
5935 | ||
5936 | ||
5937 | ||
5938 | ||
5939 | ||
5940 | ||
5941 | ||
5942 | ||
5943 | ||
5944 | endmodule | |
5945 | ||
5946 | ||
5947 | ||
5948 | ||
5949 | ||
5950 | // | |
5951 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
5952 | // | |
5953 | // | |
5954 | ||
5955 | ||
5956 | ||
5957 | ||
5958 | ||
5959 | module fgu_fgd_dp_cmp_macro__width_32 ( | |
5960 | din0, | |
5961 | din1, | |
5962 | dout); | |
5963 | input [31:0] din0; | |
5964 | input [31:0] din1; | |
5965 | output dout; | |
5966 | ||
5967 | ||
5968 | ||
5969 | ||
5970 | ||
5971 | ||
5972 | cmp #(32) m0_0 ( | |
5973 | .in0(din0[31:0]), | |
5974 | .in1(din1[31:0]), | |
5975 | .out(dout) | |
5976 | ); | |
5977 | ||
5978 | ||
5979 | ||
5980 | ||
5981 | ||
5982 | ||
5983 | ||
5984 | ||
5985 | ||
5986 | ||
5987 | endmodule | |
5988 | ||
5989 | ||
5990 | ||
5991 | ||
5992 | ||
5993 | // | |
5994 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
5995 | // | |
5996 | // | |
5997 | ||
5998 | ||
5999 | ||
6000 | ||
6001 | ||
6002 | module fgu_fgd_dp_zero_macro__width_16 ( | |
6003 | din, | |
6004 | dout); | |
6005 | input [15:0] din; | |
6006 | output dout; | |
6007 | ||
6008 | ||
6009 | ||
6010 | ||
6011 | ||
6012 | ||
6013 | zero #(16) m0_0 ( | |
6014 | .in(din[15:0]), | |
6015 | .out(dout) | |
6016 | ); | |
6017 | ||
6018 | ||
6019 | ||
6020 | ||
6021 | ||
6022 | ||
6023 | ||
6024 | ||
6025 | ||
6026 | ||
6027 | endmodule | |
6028 | ||
6029 | ||
6030 | ||
6031 | ||
6032 | ||
6033 | // | |
6034 | // invert macro | |
6035 | // | |
6036 | // | |
6037 | ||
6038 | ||
6039 | ||
6040 | ||
6041 | ||
6042 | module fgu_fgd_dp_inv_macro__width_8 ( | |
6043 | din, | |
6044 | dout); | |
6045 | input [7:0] din; | |
6046 | output [7:0] dout; | |
6047 | ||
6048 | ||
6049 | ||
6050 | ||
6051 | ||
6052 | ||
6053 | inv #(8) d0_0 ( | |
6054 | .in(din[7:0]), | |
6055 | .out(dout[7:0]) | |
6056 | ); | |
6057 | ||
6058 | ||
6059 | ||
6060 | ||
6061 | ||
6062 | ||
6063 | ||
6064 | ||
6065 | ||
6066 | endmodule | |
6067 | ||
6068 | ||
6069 | ||
6070 | ||
6071 | ||
6072 | // | |
6073 | // and macro for ports = 2,3,4 | |
6074 | // | |
6075 | // | |
6076 | ||
6077 | ||
6078 | ||
6079 | ||
6080 | ||
6081 | module fgu_fgd_dp_and_macro__ports_3__width_2 ( | |
6082 | din0, | |
6083 | din1, | |
6084 | din2, | |
6085 | dout); | |
6086 | input [1:0] din0; | |
6087 | input [1:0] din1; | |
6088 | input [1:0] din2; | |
6089 | output [1:0] dout; | |
6090 | ||
6091 | ||
6092 | ||
6093 | ||
6094 | ||
6095 | ||
6096 | and3 #(2) d0_0 ( | |
6097 | .in0(din0[1:0]), | |
6098 | .in1(din1[1:0]), | |
6099 | .in2(din2[1:0]), | |
6100 | .out(dout[1:0]) | |
6101 | ); | |
6102 | ||
6103 | ||
6104 | ||
6105 | ||
6106 | ||
6107 | ||
6108 | ||
6109 | ||
6110 | ||
6111 | endmodule | |
6112 | ||
6113 | ||
6114 | ||
6115 | ||
6116 | ||
6117 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6118 | // also for pass-gate with decoder | |
6119 | ||
6120 | ||
6121 | ||
6122 | ||
6123 | ||
6124 | // any PARAMS parms go into naming of macro | |
6125 | ||
6126 | module fgu_fgd_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_2 ( | |
6127 | din0, | |
6128 | sel0, | |
6129 | din1, | |
6130 | sel1, | |
6131 | dout); | |
6132 | input [1:0] din0; | |
6133 | input sel0; | |
6134 | input [1:0] din1; | |
6135 | input sel1; | |
6136 | output [1:0] dout; | |
6137 | ||
6138 | ||
6139 | ||
6140 | ||
6141 | ||
6142 | mux2s #(2) d0_0 ( | |
6143 | .sel0(sel0), | |
6144 | .sel1(sel1), | |
6145 | .in0(din0[1:0]), | |
6146 | .in1(din1[1:0]), | |
6147 | .dout(dout[1:0]) | |
6148 | ); | |
6149 | ||
6150 | ||
6151 | ||
6152 | ||
6153 | ||
6154 | ||
6155 | ||
6156 | ||
6157 | ||
6158 | ||
6159 | ||
6160 | ||
6161 | ||
6162 | endmodule | |
6163 | ||
6164 | ||
6165 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6166 | // also for pass-gate with decoder | |
6167 | ||
6168 | ||
6169 | ||
6170 | ||
6171 | ||
6172 | // any PARAMS parms go into naming of macro | |
6173 | ||
6174 | module fgu_fgd_dp_mux_macro__mux_aope__ports_7__width_8 ( | |
6175 | din0, | |
6176 | din1, | |
6177 | din2, | |
6178 | din3, | |
6179 | din4, | |
6180 | din5, | |
6181 | din6, | |
6182 | sel0, | |
6183 | sel1, | |
6184 | sel2, | |
6185 | sel3, | |
6186 | sel4, | |
6187 | sel5, | |
6188 | dout); | |
6189 | wire psel0; | |
6190 | wire psel1; | |
6191 | wire psel2; | |
6192 | wire psel3; | |
6193 | wire psel4; | |
6194 | wire psel5; | |
6195 | wire psel6; | |
6196 | ||
6197 | input [7:0] din0; | |
6198 | input [7:0] din1; | |
6199 | input [7:0] din2; | |
6200 | input [7:0] din3; | |
6201 | input [7:0] din4; | |
6202 | input [7:0] din5; | |
6203 | input [7:0] din6; | |
6204 | input sel0; | |
6205 | input sel1; | |
6206 | input sel2; | |
6207 | input sel3; | |
6208 | input sel4; | |
6209 | input sel5; | |
6210 | output [7:0] dout; | |
6211 | ||
6212 | ||
6213 | ||
6214 | ||
6215 | ||
6216 | cl_dp1_penc7_8x c0_0 ( | |
6217 | .test(1'b1), | |
6218 | .sel0(sel0), | |
6219 | .sel1(sel1), | |
6220 | .sel2(sel2), | |
6221 | .sel3(sel3), | |
6222 | .sel4(sel4), | |
6223 | .sel5(sel5), | |
6224 | .psel0(psel0), | |
6225 | .psel1(psel1), | |
6226 | .psel2(psel2), | |
6227 | .psel3(psel3), | |
6228 | .psel4(psel4), | |
6229 | .psel5(psel5), | |
6230 | .psel6(psel6) | |
6231 | ); | |
6232 | ||
6233 | mux7s #(8) d0_0 ( | |
6234 | .sel0(psel0), | |
6235 | .sel1(psel1), | |
6236 | .sel2(psel2), | |
6237 | .sel3(psel3), | |
6238 | .sel4(psel4), | |
6239 | .sel5(psel5), | |
6240 | .sel6(psel6), | |
6241 | .in0(din0[7:0]), | |
6242 | .in1(din1[7:0]), | |
6243 | .in2(din2[7:0]), | |
6244 | .in3(din3[7:0]), | |
6245 | .in4(din4[7:0]), | |
6246 | .in5(din5[7:0]), | |
6247 | .in6(din6[7:0]), | |
6248 | .dout(dout[7:0]) | |
6249 | ); | |
6250 | ||
6251 | ||
6252 | ||
6253 | ||
6254 | ||
6255 | ||
6256 | ||
6257 | ||
6258 | ||
6259 | ||
6260 | ||
6261 | ||
6262 | ||
6263 | endmodule | |
6264 | ||
6265 | ||
6266 | // | |
6267 | // 4:2 Carry Save Adder | |
6268 | // | |
6269 | // | |
6270 | // i0 i1 i2 i3 | co | carry sum | |
6271 | // ------------|----|----------- | |
6272 | // 0 0 0 0 | 0 | 0 cin | |
6273 | // 0 0 0 1 | 0 | cin ~cin | |
6274 | // 0 0 1 0 | 0 | cin ~cin | |
6275 | // 0 0 1 1 | 0 | 1 cin | |
6276 | // | |
6277 | // 0 1 0 0 | 0 | cin ~cin | |
6278 | // 0 1 0 1 | 0 | 1 cin | |
6279 | // 0 1 1 0 | 1 | 0 cin | |
6280 | // 0 1 1 1 | 1 | cin ~cin | |
6281 | // | |
6282 | // 1 0 0 0 | 0 | cin ~cin | |
6283 | // 1 0 0 1 | 0 | 1 cin | |
6284 | // 1 0 1 0 | 1 | 0 cin | |
6285 | // 1 0 1 1 | 1 | cin ~cin | |
6286 | // | |
6287 | // 1 1 0 0 | 1 | 0 cin | |
6288 | // 1 1 0 1 | 1 | cin ~cin | |
6289 | // 1 1 1 0 | 1 | cin ~cin | |
6290 | // 1 1 1 1 | 1 | 1 cin | |
6291 | ||
6292 | ||
6293 | // This circuit looks like a compression of 5 terms down | |
6294 | // to 3 term on an individual bit basis. However, the fast | |
6295 | // output "co" from bit position "n" is actually the late input | |
6296 | // "cin" on bit position "n+1". Once a wrapper is written | |
6297 | // around multiple bits, this circuit will give the | |
6298 | // appearance of compressing 4 inputs down to 2 outputs. | |
6299 | ||
6300 | ||
6301 | ||
6302 | ||
6303 | ||
6304 | // any PARAMS parms go into naming of macro | |
6305 | ||
6306 | ||
6307 | module fgu_fgd_dp_csa42_macro__width_9 ( | |
6308 | i0, | |
6309 | i1, | |
6310 | i2, | |
6311 | i3, | |
6312 | cin, | |
6313 | cout, | |
6314 | carry, | |
6315 | sum); | |
6316 | input [8:0] i0; | |
6317 | input [8:0] i1; | |
6318 | input [8:0] i2; | |
6319 | input [8:0] i3; | |
6320 | input cin; | |
6321 | output cout; | |
6322 | output [8:0] carry; | |
6323 | output [8:0] sum; | |
6324 | ||
6325 | ||
6326 | ||
6327 | ||
6328 | ||
6329 | ||
6330 | csa42 #(9) d0_0 ( | |
6331 | .cin(cin), | |
6332 | .in0(i0[8:0]), | |
6333 | .in1(i1[8:0]), | |
6334 | .in2(i2[8:0]), | |
6335 | .in3(i3[8:0]), | |
6336 | .cout(cout), | |
6337 | .carry(carry[8:0]), | |
6338 | .sum(sum[8:0]) | |
6339 | ); | |
6340 | ||
6341 | ||
6342 | ||
6343 | ||
6344 | ||
6345 | ||
6346 | ||
6347 | ||
6348 | endmodule | |
6349 | ||
6350 | ||
6351 | ||
6352 | ||
6353 | // | |
6354 | // 3:2 Carry Save Adder | |
6355 | // | |
6356 | // | |
6357 | ||
6358 | ||
6359 | ||
6360 | ||
6361 | // any PARAMS parms go into naming of macro | |
6362 | ||
6363 | ||
6364 | module fgu_fgd_dp_csa32_macro__width_10 ( | |
6365 | i0, | |
6366 | i1, | |
6367 | i2, | |
6368 | carry, | |
6369 | sum); | |
6370 | input [9:0] i0; | |
6371 | input [9:0] i1; | |
6372 | input [9:0] i2; | |
6373 | output [9:0] carry; | |
6374 | output [9:0] sum; | |
6375 | ||
6376 | ||
6377 | ||
6378 | ||
6379 | ||
6380 | ||
6381 | csa32 #(10) d0_0 ( | |
6382 | .in0(i0[9:0]), | |
6383 | .in1(i1[9:0]), | |
6384 | .in2(i2[9:0]), | |
6385 | .carry(carry[9:0]), | |
6386 | .sum(sum[9:0]) | |
6387 | ); | |
6388 | ||
6389 | ||
6390 | ||
6391 | ||
6392 | ||
6393 | ||
6394 | ||
6395 | ||
6396 | ||
6397 | endmodule | |
6398 | ||
6399 | ||
6400 | // | |
6401 | // cla macro | |
6402 | // | |
6403 | // | |
6404 | ||
6405 | ||
6406 | ||
6407 | ||
6408 | ||
6409 | module fgu_fgd_dp_cla_macro__width_12 ( | |
6410 | cin, | |
6411 | din0, | |
6412 | din1, | |
6413 | dout, | |
6414 | cout); | |
6415 | input cin; | |
6416 | input [11:0] din0; | |
6417 | input [11:0] din1; | |
6418 | output [11:0] dout; | |
6419 | output cout; | |
6420 | ||
6421 | ||
6422 | ||
6423 | ||
6424 | ||
6425 | ||
6426 | ||
6427 | cla #(12) m0_0 ( | |
6428 | .cin(cin), | |
6429 | .in0(din0[11:0]), | |
6430 | .in1(din1[11:0]), | |
6431 | .out(dout[11:0]), | |
6432 | .cout(cout) | |
6433 | ); | |
6434 | ||
6435 | ||
6436 | ||
6437 | ||
6438 | ||
6439 | ||
6440 | ||
6441 | ||
6442 | ||
6443 | ||
6444 | ||
6445 | ||
6446 | endmodule | |
6447 | ||
6448 | ||
6449 | ||
6450 | ||
6451 | ||
6452 | // | |
6453 | // increment macro | |
6454 | // | |
6455 | // | |
6456 | ||
6457 | ||
6458 | ||
6459 | ||
6460 | ||
6461 | module fgu_fgd_dp_increment_macro__width_64 ( | |
6462 | din, | |
6463 | cin, | |
6464 | dout, | |
6465 | cout); | |
6466 | input [63:0] din; | |
6467 | input cin; | |
6468 | output [63:0] dout; | |
6469 | output cout; | |
6470 | ||
6471 | ||
6472 | ||
6473 | ||
6474 | ||
6475 | ||
6476 | incr #(64) m0_0 ( | |
6477 | .cin(cin), | |
6478 | .in(din[63:0]), | |
6479 | .out(dout[63:0]), | |
6480 | .cout(cout) | |
6481 | ); | |
6482 | ||
6483 | ||
6484 | ||
6485 | ||
6486 | ||
6487 | ||
6488 | ||
6489 | ||
6490 | ||
6491 | ||
6492 | ||
6493 | endmodule | |
6494 | ||
6495 | ||
6496 | ||
6497 | ||
6498 | ||
6499 | ||
6500 | ||
6501 | ||
6502 | ||
6503 | // any PARAMS parms go into naming of macro | |
6504 | ||
6505 | module fgu_fgd_dp_msff_macro__mux_aope__ports_5__width_64 ( | |
6506 | din0, | |
6507 | din1, | |
6508 | din2, | |
6509 | din3, | |
6510 | din4, | |
6511 | sel0, | |
6512 | sel1, | |
6513 | sel2, | |
6514 | sel3, | |
6515 | clk, | |
6516 | en, | |
6517 | se, | |
6518 | scan_in, | |
6519 | siclk, | |
6520 | soclk, | |
6521 | pce_ov, | |
6522 | stop, | |
6523 | dout, | |
6524 | scan_out); | |
6525 | wire psel0; | |
6526 | wire psel1; | |
6527 | wire psel2; | |
6528 | wire psel3; | |
6529 | wire psel4; | |
6530 | wire [63:0] muxout; | |
6531 | wire l1clk; | |
6532 | wire siclk_out; | |
6533 | wire soclk_out; | |
6534 | wire [62:0] so; | |
6535 | ||
6536 | input [63:0] din0; | |
6537 | input [63:0] din1; | |
6538 | input [63:0] din2; | |
6539 | input [63:0] din3; | |
6540 | input [63:0] din4; | |
6541 | input sel0; | |
6542 | input sel1; | |
6543 | input sel2; | |
6544 | input sel3; | |
6545 | ||
6546 | ||
6547 | input clk; | |
6548 | input en; | |
6549 | input se; | |
6550 | input scan_in; | |
6551 | input siclk; | |
6552 | input soclk; | |
6553 | input pce_ov; | |
6554 | input stop; | |
6555 | ||
6556 | ||
6557 | ||
6558 | output [63:0] dout; | |
6559 | ||
6560 | ||
6561 | output scan_out; | |
6562 | ||
6563 | ||
6564 | ||
6565 | ||
6566 | cl_dp1_penc5_8x c1_0 ( | |
6567 | .test(1'b1), | |
6568 | .sel0(sel0), | |
6569 | .sel1(sel1), | |
6570 | .sel2(sel2), | |
6571 | .sel3(sel3), | |
6572 | .psel0(psel0), | |
6573 | .psel1(psel1), | |
6574 | .psel2(psel2), | |
6575 | .psel3(psel3), | |
6576 | .psel4(psel4) | |
6577 | ); | |
6578 | ||
6579 | mux5s #(64) d1_0 ( | |
6580 | .sel0(psel0), | |
6581 | .sel1(psel1), | |
6582 | .sel2(psel2), | |
6583 | .sel3(psel3), | |
6584 | .sel4(psel4), | |
6585 | .in0(din0[63:0]), | |
6586 | .in1(din1[63:0]), | |
6587 | .in2(din2[63:0]), | |
6588 | .in3(din3[63:0]), | |
6589 | .in4(din4[63:0]), | |
6590 | .dout(muxout[63:0]) | |
6591 | ); | |
6592 | cl_dp1_l1hdr_8x c0_0 ( | |
6593 | .l2clk(clk), | |
6594 | .pce(en), | |
6595 | .aclk(siclk), | |
6596 | .bclk(soclk), | |
6597 | .l1clk(l1clk), | |
6598 | .se(se), | |
6599 | .pce_ov(pce_ov), | |
6600 | .stop(stop), | |
6601 | .siclk_out(siclk_out), | |
6602 | .soclk_out(soclk_out) | |
6603 | ); | |
6604 | dff #(64) d0_0 ( | |
6605 | .l1clk(l1clk), | |
6606 | .siclk(siclk_out), | |
6607 | .soclk(soclk_out), | |
6608 | .d(muxout[63:0]), | |
6609 | .si({scan_in,so[62:0]}), | |
6610 | .so({so[62:0],scan_out}), | |
6611 | .q(dout[63:0]) | |
6612 | ); | |
6613 | ||
6614 | ||
6615 | ||
6616 | ||
6617 | ||
6618 | ||
6619 | ||
6620 | ||
6621 | ||
6622 | ||
6623 | ||
6624 | ||
6625 | ||
6626 | ||
6627 | ||
6628 | ||
6629 | ||
6630 | ||
6631 | ||
6632 | ||
6633 | endmodule | |
6634 | ||
6635 | ||
6636 | ||
6637 | ||
6638 | ||
6639 | ||
6640 | ||
6641 | ||
6642 | ||
6643 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6644 | // also for pass-gate with decoder | |
6645 | ||
6646 | ||
6647 | ||
6648 | ||
6649 | ||
6650 | // any PARAMS parms go into naming of macro | |
6651 | ||
6652 | module fgu_fgd_dp_mux_macro__mux_pgpe__ports_5__stack_32l__width_31 ( | |
6653 | din0, | |
6654 | din1, | |
6655 | din2, | |
6656 | din3, | |
6657 | din4, | |
6658 | sel0, | |
6659 | sel1, | |
6660 | sel2, | |
6661 | sel3, | |
6662 | muxtst, | |
6663 | test, | |
6664 | dout); | |
6665 | wire psel0; | |
6666 | wire psel1; | |
6667 | wire psel2; | |
6668 | wire psel3; | |
6669 | wire psel4; | |
6670 | ||
6671 | input [30:0] din0; | |
6672 | input [30:0] din1; | |
6673 | input [30:0] din2; | |
6674 | input [30:0] din3; | |
6675 | input [30:0] din4; | |
6676 | input sel0; | |
6677 | input sel1; | |
6678 | input sel2; | |
6679 | input sel3; | |
6680 | input muxtst; | |
6681 | input test; | |
6682 | output [30:0] dout; | |
6683 | ||
6684 | ||
6685 | ||
6686 | ||
6687 | ||
6688 | cl_dp1_penc5_8x c0_0 ( | |
6689 | .sel0(sel0), | |
6690 | .sel1(sel1), | |
6691 | .sel2(sel2), | |
6692 | .sel3(sel3), | |
6693 | .psel0(psel0), | |
6694 | .psel1(psel1), | |
6695 | .psel2(psel2), | |
6696 | .psel3(psel3), | |
6697 | .psel4(psel4), | |
6698 | .test(test) | |
6699 | ); | |
6700 | ||
6701 | mux5 #(31) d0_0 ( | |
6702 | .sel0(psel0), | |
6703 | .sel1(psel1), | |
6704 | .sel2(psel2), | |
6705 | .sel3(psel3), | |
6706 | .sel4(psel4), | |
6707 | .in0(din0[30:0]), | |
6708 | .in1(din1[30:0]), | |
6709 | .in2(din2[30:0]), | |
6710 | .in3(din3[30:0]), | |
6711 | .in4(din4[30:0]), | |
6712 | .dout(dout[30:0]), | |
6713 | .muxtst(muxtst) | |
6714 | ); | |
6715 | ||
6716 | ||
6717 | ||
6718 | ||
6719 | ||
6720 | ||
6721 | ||
6722 | ||
6723 | ||
6724 | ||
6725 | ||
6726 | ||
6727 | ||
6728 | endmodule | |
6729 | ||
6730 | ||
6731 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
6732 | // also for pass-gate with decoder | |
6733 | ||
6734 | ||
6735 | ||
6736 | ||
6737 | ||
6738 | // any PARAMS parms go into naming of macro | |
6739 | ||
6740 | module fgu_fgd_dp_mux_macro__mux_pgpe__ports_4__stack_32l__width_32 ( | |
6741 | din0, | |
6742 | din1, | |
6743 | din2, | |
6744 | din3, | |
6745 | sel0, | |
6746 | sel1, | |
6747 | sel2, | |
6748 | muxtst, | |
6749 | test, | |
6750 | dout); | |
6751 | wire psel0; | |
6752 | wire psel1; | |
6753 | wire psel2; | |
6754 | wire psel3; | |
6755 | ||
6756 | input [31:0] din0; | |
6757 | input [31:0] din1; | |
6758 | input [31:0] din2; | |
6759 | input [31:0] din3; | |
6760 | input sel0; | |
6761 | input sel1; | |
6762 | input sel2; | |
6763 | input muxtst; | |
6764 | input test; | |
6765 | output [31:0] dout; | |
6766 | ||
6767 | ||
6768 | ||
6769 | ||
6770 | ||
6771 | cl_dp1_penc4_8x c0_0 ( | |
6772 | .sel0(sel0), | |
6773 | .sel1(sel1), | |
6774 | .sel2(sel2), | |
6775 | .psel0(psel0), | |
6776 | .psel1(psel1), | |
6777 | .psel2(psel2), | |
6778 | .psel3(psel3), | |
6779 | .test(test) | |
6780 | ); | |
6781 | ||
6782 | mux4 #(32) d0_0 ( | |
6783 | .sel0(psel0), | |
6784 | .sel1(psel1), | |
6785 | .sel2(psel2), | |
6786 | .sel3(psel3), | |
6787 | .in0(din0[31:0]), | |
6788 | .in1(din1[31:0]), | |
6789 | .in2(din2[31:0]), | |
6790 | .in3(din3[31:0]), | |
6791 | .dout(dout[31:0]), | |
6792 | .muxtst(muxtst) | |
6793 | ); | |
6794 | ||
6795 | ||
6796 | ||
6797 | ||
6798 | ||
6799 | ||
6800 | ||
6801 | ||
6802 | ||
6803 | ||
6804 | ||
6805 | ||
6806 | ||
6807 | endmodule | |
6808 |