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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / spc / ifu / rtl / ifu_cmu_lsi_dp.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: ifu_cmu_lsi_dp.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module ifu_cmu_lsi_dp (
36 tcu_scan_en,
37 l2clk,
38 spc_aclk,
39 spc_bclk,
40 tcu_pce_ov,
41 scan_in,
42 lsc_clken,
43 lsc_data_sel,
44 l15_spc_data1,
45 lsc_fill_rtn1,
46 lsc_fill_rtn2,
47 gkt_ifu_legal,
48 gkt_ifu_flip_parity,
49 cmu_ic_data,
50 cmu_fill_inst0,
51 cmu_fill_inst1,
52 cmu_fill_inst2,
53 cmu_fill_inst3,
54 scan_out) ;
55wire stop;
56wire se;
57wire pce_ov;
58wire siclk;
59wire soclk;
60wire l15_w0_parity_pre;
61wire l15_w0_parity;
62wire l15_w1_parity_pre;
63wire l15_w1_parity;
64wire l15_w2_parity_pre;
65wire l15_w2_parity;
66wire l15_w3_parity_pre;
67wire l15_w3_parity;
68wire [127:0] gkt_data;
69wire [32:0] w0_data_r1_buf;
70wire [32:0] w0_data_in;
71wire [32:0] w1_data_r1_buf;
72wire [32:0] w1_data_in;
73wire [32:0] w2_data_r1_buf;
74wire [32:0] w2_data_in;
75wire [32:0] w3_data_r1_buf;
76wire [32:0] w3_data_in;
77wire [32:0] w4_data_r1_buf;
78wire [32:0] w4_data_in;
79wire [32:0] w5_data_r1_buf;
80wire [32:0] w5_data_in;
81wire [32:0] w6_data_r1_buf;
82wire [32:0] w6_data_in;
83wire [32:0] w7_data_r1_buf;
84wire [32:0] w7_data_in;
85wire fill_data_w0_reg_scanin;
86wire fill_data_w0_reg_scanout;
87wire [32:0] w0_data_r1;
88wire fill_data_w1_reg_scanin;
89wire fill_data_w1_reg_scanout;
90wire [32:0] w1_data_r1;
91wire fill_data_w2_reg_scanin;
92wire fill_data_w2_reg_scanout;
93wire [32:0] w2_data_r1;
94wire fill_data_w3_reg_scanin;
95wire fill_data_w3_reg_scanout;
96wire [32:0] w3_data_r1;
97wire fill_data_w4_reg_scanin;
98wire fill_data_w4_reg_scanout;
99wire [32:0] w4_data_r1;
100wire fill_data_w5_reg_scanin;
101wire fill_data_w5_reg_scanout;
102wire [32:0] w5_data_r1;
103wire fill_data_w6_reg_scanin;
104wire fill_data_w6_reg_scanout;
105wire [32:0] w6_data_r1;
106wire fill_data_w7_reg_scanin;
107wire fill_data_w7_reg_scanout;
108wire [32:0] w7_data_r1;
109wire paddr_lat_scanin;
110wire paddr_lat_scanout;
111wire [7:0] lsc_data_sel_lat;
112wire [32:0] cmu_fill_inst0_prebuf;
113wire [32:0] cmu_fill_inst1_prebuf;
114wire [32:0] cmu_fill_inst2_prebuf;
115wire [32:0] cmu_fill_inst3_prebuf;
116
117
118input tcu_scan_en ;
119input l2clk;
120input spc_aclk;
121input spc_bclk;
122input tcu_pce_ov ;
123input scan_in;
124
125input lsc_clken;
126input [7:0] lsc_data_sel;
127
128
129input [127:0] l15_spc_data1;
130input lsc_fill_rtn1;
131input lsc_fill_rtn2;
132input [3:0] gkt_ifu_legal;
133input [3:0] gkt_ifu_flip_parity;
134
135
136
137output [263:0] cmu_ic_data;
138
139output [32:0] cmu_fill_inst0;
140output [32:0] cmu_fill_inst1;
141output [32:0] cmu_fill_inst2;
142output [32:0] cmu_fill_inst3;
143
144
145output scan_out;
146
147// scan renames
148assign stop = 1'b0;
149// end scan
150
151ifu_cmu_lsi_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 (
152 .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}),
153 .dout({se,pce_ov,siclk,soclk})
154);
155
156
157////////////////////////////////////////////////////////
158// Compute parity on input data from gkt
159// Data from gkt arrives at ~350ps, parity should be 250 ps.
160////////////////////////////////////////////////////////
161
162ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w0_parity (
163 .din(l15_spc_data1[127:96]),
164 .dout(l15_w0_parity_pre)
165);
166ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w0_parity_final (
167 .din0(l15_w0_parity_pre),
168 .din1(gkt_ifu_flip_parity[3]),
169 .dout(l15_w0_parity)
170);
171
172ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w1_parity (
173 .din(l15_spc_data1[95:64]),
174 .dout(l15_w1_parity_pre)
175);
176ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w1_parity_final (
177 .din0(l15_w1_parity_pre),
178 .din1(gkt_ifu_flip_parity[2]),
179 .dout(l15_w1_parity)
180);
181
182
183ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w2_parity (
184 .din(l15_spc_data1[63:32]),
185 .dout(l15_w2_parity_pre)
186);
187ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w2_parity_final (
188 .din0(l15_w2_parity_pre),
189 .din1(gkt_ifu_flip_parity[1]),
190 .dout(l15_w2_parity)
191);
192
193
194ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 w3_parity (
195 .din(l15_spc_data1[31:0]),
196 .dout(l15_w3_parity_pre)
197);
198ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 w3_parity_final (
199 .din0(l15_w3_parity_pre),
200 .din1(gkt_ifu_flip_parity[0]),
201 .dout(l15_w3_parity)
202);
203
204
205////////////////////////////////////////////////////////
206// For illegal instructions, 0 out bits 31,30,24,23,22 of instruction
207////////////////////////////////////////////////////////
208ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and0 (
209.din0 ({l15_spc_data1[31],l15_spc_data1[30],l15_spc_data1[24],l15_spc_data1[23],l15_spc_data1[22]}),
210.din1 ({5{gkt_ifu_legal[0]}}),
211.dout ({gkt_data[31],gkt_data[30],gkt_data[24],gkt_data[23],gkt_data[22]})
212);
213
214ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and1 (
215.din0 ({l15_spc_data1[63],l15_spc_data1[62],l15_spc_data1[56],l15_spc_data1[55],l15_spc_data1[54]}),
216.din1 ({5{gkt_ifu_legal[1]}}),
217.dout ({gkt_data[63],gkt_data[62],gkt_data[56],gkt_data[55],gkt_data[54]})
218);
219
220ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and2 (
221.din0 ({l15_spc_data1[95],l15_spc_data1[94],l15_spc_data1[88],l15_spc_data1[87],l15_spc_data1[86]}),
222.din1 ({5{gkt_ifu_legal[2]}}),
223.dout ({gkt_data[95],gkt_data[94],gkt_data[88],gkt_data[87],gkt_data[86]})
224);
225
226ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 zero_opc_and3 (
227.din0 ({l15_spc_data1[127],l15_spc_data1[126],l15_spc_data1[120],l15_spc_data1[119],l15_spc_data1[118]}),
228.din1 ({5{gkt_ifu_legal[3]}}),
229.dout ({gkt_data[127],gkt_data[126],gkt_data[120],gkt_data[119],gkt_data[118]})
230);
231
232assign gkt_data[29:25] = l15_spc_data1[29:25];
233assign gkt_data[21:0] = l15_spc_data1[21:0];
234
235assign gkt_data[61:57] = l15_spc_data1[61:57];
236assign gkt_data[53:32] = l15_spc_data1[53:32];
237
238assign gkt_data[93:89] = l15_spc_data1[93:89];
239assign gkt_data[85:64] = l15_spc_data1[85:64];
240
241assign gkt_data[125:121] = l15_spc_data1[125:121];
242assign gkt_data[117:96] = l15_spc_data1[117:96];
243
244
245////////////////////////////////////////////////////////
246// Flopping input data from gkt
247////////////////////////////////////////////////////////
248
249ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w0_data_mux (
250 .din1(w0_data_r1_buf[32:0]),
251 .din0({l15_w0_parity,gkt_data[127:96]}),
252 .sel0(lsc_fill_rtn1),
253 .dout(w0_data_in[32:0])
254);
255
256ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w1_data_mux (
257 .din1(w1_data_r1_buf[32:0]),
258 .din0({l15_w1_parity,gkt_data[95:64]}),
259 .sel0(lsc_fill_rtn1),
260 .dout(w1_data_in[32:0])
261);
262
263ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w2_data_mux (
264 .din1(w2_data_r1_buf[32:0]),
265 .din0({l15_w2_parity,gkt_data[63:32]}),
266 .sel0(lsc_fill_rtn1),
267 .dout(w2_data_in[32:0])
268);
269
270ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w3_data_mux (
271 .din1(w3_data_r1_buf[32:0]),
272 .din0({l15_w3_parity,gkt_data[31:0]}),
273 .sel0(lsc_fill_rtn1),
274 .dout(w3_data_in[32:0])
275);
276
277ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w4_data_mux (
278 .din1(w4_data_r1_buf[32:0]),
279 .din0({l15_w0_parity,gkt_data[127:96]}),
280 .sel0(lsc_fill_rtn2),
281 .dout(w4_data_in[32:0])
282);
283
284ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w5_data_mux (
285 .din1(w5_data_r1_buf[32:0]),
286 .din0({l15_w1_parity,gkt_data[95:64]}),
287 .sel0(lsc_fill_rtn2),
288 .dout(w5_data_in[32:0])
289);
290
291ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w6_data_mux (
292 .din1(w6_data_r1_buf[32:0]),
293 .din0({l15_w2_parity,gkt_data[63:32]}),
294 .sel0(lsc_fill_rtn2),
295 .dout(w6_data_in[32:0])
296);
297
298ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 w7_data_mux (
299 .din1(w7_data_r1_buf[32:0]),
300 .din0({l15_w3_parity,gkt_data[31:0]}),
301 .sel0(lsc_fill_rtn2),
302 .dout(w7_data_in[32:0])
303);
304
305ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w0_reg (
306 .scan_in(fill_data_w0_reg_scanin),
307 .scan_out(fill_data_w0_reg_scanout),
308 .clk (l2clk),
309 .en (lsc_clken),
310 .din (w0_data_in[32:0]),
311 .dout(w0_data_r1[32:0]),
312 .se(se),
313 .siclk(siclk),
314 .soclk(soclk),
315 .pce_ov(pce_ov),
316 .stop(stop)
317);
318
319ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w1_reg (
320 .scan_in(fill_data_w1_reg_scanin),
321 .scan_out(fill_data_w1_reg_scanout),
322 .clk (l2clk),
323 .en (lsc_clken),
324 .din (w1_data_in[32:0]),
325 .dout(w1_data_r1[32:0]),
326 .se(se),
327 .siclk(siclk),
328 .soclk(soclk),
329 .pce_ov(pce_ov),
330 .stop(stop)
331);
332
333ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w2_reg (
334 .scan_in(fill_data_w2_reg_scanin),
335 .scan_out(fill_data_w2_reg_scanout),
336 .clk (l2clk),
337 .en (lsc_clken),
338 .din (w2_data_in[32:0]),
339 .dout(w2_data_r1[32:0]),
340 .se(se),
341 .siclk(siclk),
342 .soclk(soclk),
343 .pce_ov(pce_ov),
344 .stop(stop)
345);
346
347ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w3_reg (
348 .scan_in(fill_data_w3_reg_scanin),
349 .scan_out(fill_data_w3_reg_scanout),
350 .clk (l2clk),
351 .en (lsc_clken),
352 .din (w3_data_in[32:0]),
353 .dout(w3_data_r1[32:0]),
354 .se(se),
355 .siclk(siclk),
356 .soclk(soclk),
357 .pce_ov(pce_ov),
358 .stop(stop)
359);
360
361ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w4_reg (
362 .scan_in(fill_data_w4_reg_scanin),
363 .scan_out(fill_data_w4_reg_scanout),
364 .clk (l2clk),
365 .en (lsc_clken),
366 .din (w4_data_in[32:0]),
367 .dout(w4_data_r1[32:0]),
368 .se(se),
369 .siclk(siclk),
370 .soclk(soclk),
371 .pce_ov(pce_ov),
372 .stop(stop)
373);
374
375ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w5_reg (
376 .scan_in(fill_data_w5_reg_scanin),
377 .scan_out(fill_data_w5_reg_scanout),
378 .clk (l2clk),
379 .en (lsc_clken),
380 .din (w5_data_in[32:0]),
381 .dout(w5_data_r1[32:0]),
382 .se(se),
383 .siclk(siclk),
384 .soclk(soclk),
385 .pce_ov(pce_ov),
386 .stop(stop)
387);
388
389ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w6_reg (
390 .scan_in(fill_data_w6_reg_scanin),
391 .scan_out(fill_data_w6_reg_scanout),
392 .clk (l2clk),
393 .en (lsc_clken),
394 .din (w6_data_in[32:0]),
395 .dout(w6_data_r1[32:0]),
396 .se(se),
397 .siclk(siclk),
398 .soclk(soclk),
399 .pce_ov(pce_ov),
400 .stop(stop)
401);
402
403ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 fill_data_w7_reg (
404 .scan_in(fill_data_w7_reg_scanin),
405 .scan_out(fill_data_w7_reg_scanout),
406 .clk (l2clk),
407 .en (lsc_clken),
408 .din (w7_data_in[32:0]),
409 .dout(w7_data_r1[32:0]),
410 .se(se),
411 .siclk(siclk),
412 .soclk(soclk),
413 .pce_ov(pce_ov),
414 .stop(stop)
415);
416
417////////////////////////////////////////////////////////
418// Instruction Mux
419////////////////////////////////////////////////////////
420ifu_cmu_lsi_dp_msff_macro__left_8__stack_16l__width_8 paddr_lat (
421 .scan_in(paddr_lat_scanin),
422 .scan_out(paddr_lat_scanout),
423 .clk (l2clk),
424 .en (lsc_clken),
425 .din (lsc_data_sel[7:0]),
426 .dout(lsc_data_sel_lat[7:0]),
427 .se(se),
428 .siclk(siclk),
429 .soclk(soclk),
430 .pce_ov(pce_ov),
431 .stop(stop)
432);
433
434ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst0_mux (
435 .din0(w0_data_r1_buf[32:0]),
436 .din1(w1_data_r1_buf[32:0]),
437 .din2(w2_data_r1_buf[32:0]),
438 .din3(w3_data_r1_buf[32:0]),
439 .din4(w4_data_r1_buf[32:0]),
440 .din5(w5_data_r1_buf[32:0]),
441 .din6(w6_data_r1_buf[32:0]),
442 .din7(w7_data_r1_buf[32:0]),
443 .sel0(lsc_data_sel_lat[0]),
444 .sel1(lsc_data_sel_lat[1]),
445 .sel2(lsc_data_sel_lat[2]),
446 .sel3(lsc_data_sel_lat[3]),
447 .sel4(lsc_data_sel_lat[4]),
448 .sel5(lsc_data_sel_lat[5]),
449 .sel6(lsc_data_sel_lat[6]),
450 .sel7(lsc_data_sel_lat[7]),
451 .dout(cmu_fill_inst0_prebuf[32:0])
452);
453
454ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst0_buf (
455 .din (cmu_fill_inst0_prebuf[32:0]),
456 .dout (cmu_fill_inst0[32:0])
457);
458
459ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst1_mux (
460 .din0(w1_data_r1_buf[32:0]),
461 .din1(w2_data_r1_buf[32:0]),
462 .din2(w3_data_r1_buf[32:0]),
463 .din3(w4_data_r1_buf[32:0]),
464 .din4(w5_data_r1_buf[32:0]),
465 .din5(w6_data_r1_buf[32:0]),
466 .din6(w7_data_r1_buf[32:0]),
467 .din7(w0_data_r1_buf[32:0]),
468 .sel0(lsc_data_sel_lat[0]),
469 .sel1(lsc_data_sel_lat[1]),
470 .sel2(lsc_data_sel_lat[2]),
471 .sel3(lsc_data_sel_lat[3]),
472 .sel4(lsc_data_sel_lat[4]),
473 .sel5(lsc_data_sel_lat[5]),
474 .sel6(lsc_data_sel_lat[6]),
475 .sel7(lsc_data_sel_lat[7]),
476 .dout(cmu_fill_inst1_prebuf[32:0])
477);
478
479ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst1_buf (
480 .din (cmu_fill_inst1_prebuf[32:0]),
481 .dout (cmu_fill_inst1[32:0])
482);
483
484ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst2_mux (
485 .din0(w2_data_r1_buf[32:0]),
486 .din1(w3_data_r1_buf[32:0]),
487 .din2(w4_data_r1_buf[32:0]),
488 .din3(w5_data_r1_buf[32:0]),
489 .din4(w6_data_r1_buf[32:0]),
490 .din5(w7_data_r1_buf[32:0]),
491 .din6(w0_data_r1_buf[32:0]),
492 .din7(w1_data_r1_buf[32:0]),
493 .sel0(lsc_data_sel_lat[0]),
494 .sel1(lsc_data_sel_lat[1]),
495 .sel2(lsc_data_sel_lat[2]),
496 .sel3(lsc_data_sel_lat[3]),
497 .sel4(lsc_data_sel_lat[4]),
498 .sel5(lsc_data_sel_lat[5]),
499 .sel6(lsc_data_sel_lat[6]),
500 .sel7(lsc_data_sel_lat[7]),
501 .dout(cmu_fill_inst2_prebuf[32:0])
502);
503
504ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst2_buf (
505 .din (cmu_fill_inst2_prebuf[32:0]),
506 .dout (cmu_fill_inst2[32:0])
507);
508
509ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 inst3_mux (
510 .din0(w3_data_r1_buf[32:0]),
511 .din1(w4_data_r1_buf[32:0]),
512 .din2(w5_data_r1_buf[32:0]),
513 .din3(w6_data_r1_buf[32:0]),
514 .din4(w7_data_r1_buf[32:0]),
515 .din5(w0_data_r1_buf[32:0]),
516 .din6(w1_data_r1_buf[32:0]),
517 .din7(w2_data_r1_buf[32:0]),
518 .sel0(lsc_data_sel_lat[0]),
519 .sel1(lsc_data_sel_lat[1]),
520 .sel2(lsc_data_sel_lat[2]),
521 .sel3(lsc_data_sel_lat[3]),
522 .sel4(lsc_data_sel_lat[4]),
523 .sel5(lsc_data_sel_lat[5]),
524 .sel6(lsc_data_sel_lat[6]),
525 .sel7(lsc_data_sel_lat[7]),
526 .dout(cmu_fill_inst3_prebuf[32:0])
527);
528
529ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 inst3_buf (
530 .din (cmu_fill_inst3_prebuf[32:0]),
531 .dout (cmu_fill_inst3[32:0])
532);
533
534
535////////////////////////////////////////////////////////
536// Buffer Cache data
537////////////////////////////////////////////////////////
538ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w0_data_buf (
539 .din (w0_data_r1[32:0]),
540 .dout (w0_data_r1_buf[32:0])
541);
542
543ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w1_data_buf (
544 .din (w1_data_r1[32:0]),
545 .dout (w1_data_r1_buf[32:0])
546);
547
548ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w2_data_buf (
549 .din (w2_data_r1[32:0]),
550 .dout (w2_data_r1_buf[32:0])
551);
552
553ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w3_data_buf (
554 .din (w3_data_r1[32:0]),
555 .dout (w3_data_r1_buf[32:0])
556);
557
558ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w4_data_buf (
559 .din (w4_data_r1[32:0]),
560 .dout (w4_data_r1_buf[32:0])
561);
562
563ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w5_data_buf (
564 .din (w5_data_r1[32:0]),
565 .dout (w5_data_r1_buf[32:0])
566);
567
568ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w6_data_buf (
569 .din (w6_data_r1[32:0]),
570 .dout (w6_data_r1_buf[32:0])
571);
572
573ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 w7_data_buf (
574 .din (w7_data_r1[32:0]),
575 .dout (w7_data_r1_buf[32:0])
576);
577
578////////////////////////////////////////////////////////
579// Cache Data Line
580////////////////////////////////////////////////////////
581assign cmu_ic_data[32:0] = w0_data_r1_buf[32:0];
582assign cmu_ic_data[65:33] = w1_data_r1_buf[32:0];
583assign cmu_ic_data[98:66] = w2_data_r1_buf[32:0];
584assign cmu_ic_data[131:99] = w3_data_r1_buf[32:0];
585assign cmu_ic_data[164:132] = w4_data_r1_buf[32:0];
586assign cmu_ic_data[197:165] = w5_data_r1_buf[32:0];
587assign cmu_ic_data[230:198] = w6_data_r1_buf[32:0];
588assign cmu_ic_data[263:231] = w7_data_r1_buf[32:0];
589
590
591
592
593// fixscan start:
594assign fill_data_w0_reg_scanin = scan_in ;
595assign fill_data_w1_reg_scanin = fill_data_w0_reg_scanout ;
596assign fill_data_w2_reg_scanin = fill_data_w1_reg_scanout ;
597assign fill_data_w3_reg_scanin = fill_data_w2_reg_scanout ;
598assign fill_data_w4_reg_scanin = fill_data_w3_reg_scanout ;
599assign fill_data_w5_reg_scanin = fill_data_w4_reg_scanout ;
600assign fill_data_w6_reg_scanin = fill_data_w5_reg_scanout ;
601assign fill_data_w7_reg_scanin = fill_data_w6_reg_scanout ;
602assign paddr_lat_scanin = fill_data_w7_reg_scanout ;
603assign scan_out = paddr_lat_scanout ;
604// fixscan end:
605endmodule
606
607
608//
609// buff macro
610//
611//
612
613
614
615
616
617module ifu_cmu_lsi_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 (
618 din,
619 dout);
620 input [3:0] din;
621 output [3:0] dout;
622
623
624
625
626
627
628buff #(4) d0_0 (
629.in(din[3:0]),
630.out(dout[3:0])
631);
632
633
634
635
636
637
638
639
640endmodule
641
642
643
644
645
646//
647// parity macro (even parity)
648//
649//
650
651
652
653
654
655module ifu_cmu_lsi_dp_prty_macro__dprty_8x__width_32 (
656 din,
657 dout);
658 input [31:0] din;
659 output dout;
660
661
662
663
664
665
666
667prty #(32) m0_0 (
668.in(din[31:0]),
669.out(dout)
670);
671
672
673
674
675
676
677
678
679
680
681endmodule
682
683
684
685
686
687//
688// xor macro for ports = 2,3
689//
690//
691
692
693
694
695
696module ifu_cmu_lsi_dp_xor_macro__ports_2__stack_34c__width_1 (
697 din0,
698 din1,
699 dout);
700 input [0:0] din0;
701 input [0:0] din1;
702 output [0:0] dout;
703
704
705
706
707
708xor2 #(1) d0_0 (
709.in0(din0[0:0]),
710.in1(din1[0:0]),
711.out(dout[0:0])
712);
713
714
715
716
717
718
719
720
721endmodule
722
723
724
725
726
727//
728// and macro for ports = 2,3,4
729//
730//
731
732
733
734
735
736module ifu_cmu_lsi_dp_and_macro__stack_34c__width_5 (
737 din0,
738 din1,
739 dout);
740 input [4:0] din0;
741 input [4:0] din1;
742 output [4:0] dout;
743
744
745
746
747
748
749and2 #(5) d0_0 (
750.in0(din0[4:0]),
751.in1(din1[4:0]),
752.out(dout[4:0])
753);
754
755
756
757
758
759
760
761
762
763endmodule
764
765
766
767
768
769// general mux macro for pass-gate and and-or muxes with/wout priority encoders
770// also for pass-gate with decoder
771
772
773
774
775
776// any PARAMS parms go into naming of macro
777
778module ifu_cmu_lsi_dp_mux_macro__mux_aope__ports_2__stack_34c__width_33 (
779 din0,
780 din1,
781 sel0,
782 dout);
783wire psel0;
784wire psel1;
785
786 input [32:0] din0;
787 input [32:0] din1;
788 input sel0;
789 output [32:0] dout;
790
791
792
793
794
795cl_dp1_penc2_8x c0_0 (
796 .sel0(sel0),
797 .psel0(psel0),
798 .psel1(psel1)
799);
800
801mux2s #(33) d0_0 (
802 .sel0(psel0),
803 .sel1(psel1),
804 .in0(din0[32:0]),
805 .in1(din1[32:0]),
806.dout(dout[32:0])
807);
808
809
810
811
812
813
814
815
816
817
818
819
820
821endmodule
822
823
824
825
826
827
828// any PARAMS parms go into naming of macro
829
830module ifu_cmu_lsi_dp_msff_macro__stack_34c__width_33 (
831 din,
832 clk,
833 en,
834 se,
835 scan_in,
836 siclk,
837 soclk,
838 pce_ov,
839 stop,
840 dout,
841 scan_out);
842wire l1clk;
843wire siclk_out;
844wire soclk_out;
845wire [31:0] so;
846
847 input [32:0] din;
848
849
850 input clk;
851 input en;
852 input se;
853 input scan_in;
854 input siclk;
855 input soclk;
856 input pce_ov;
857 input stop;
858
859
860
861 output [32:0] dout;
862
863
864 output scan_out;
865
866
867
868
869cl_dp1_l1hdr_8x c0_0 (
870.l2clk(clk),
871.pce(en),
872.aclk(siclk),
873.bclk(soclk),
874.l1clk(l1clk),
875 .se(se),
876 .pce_ov(pce_ov),
877 .stop(stop),
878 .siclk_out(siclk_out),
879 .soclk_out(soclk_out)
880);
881dff #(33) d0_0 (
882.l1clk(l1clk),
883.siclk(siclk_out),
884.soclk(soclk_out),
885.d(din[32:0]),
886.si({scan_in,so[31:0]}),
887.so({so[31:0],scan_out}),
888.q(dout[32:0])
889);
890
891
892
893
894
895
896
897
898
899
900
901
902
903
904
905
906
907
908
909
910endmodule
911
912
913
914
915
916
917
918
919
920
921
922
923
924// any PARAMS parms go into naming of macro
925
926module ifu_cmu_lsi_dp_msff_macro__left_8__stack_16l__width_8 (
927 din,
928 clk,
929 en,
930 se,
931 scan_in,
932 siclk,
933 soclk,
934 pce_ov,
935 stop,
936 dout,
937 scan_out);
938wire l1clk;
939wire siclk_out;
940wire soclk_out;
941wire [6:0] so;
942
943 input [7:0] din;
944
945
946 input clk;
947 input en;
948 input se;
949 input scan_in;
950 input siclk;
951 input soclk;
952 input pce_ov;
953 input stop;
954
955
956
957 output [7:0] dout;
958
959
960 output scan_out;
961
962
963
964
965cl_dp1_l1hdr_8x c0_0 (
966.l2clk(clk),
967.pce(en),
968.aclk(siclk),
969.bclk(soclk),
970.l1clk(l1clk),
971 .se(se),
972 .pce_ov(pce_ov),
973 .stop(stop),
974 .siclk_out(siclk_out),
975 .soclk_out(soclk_out)
976);
977dff #(8) d0_0 (
978.l1clk(l1clk),
979.siclk(siclk_out),
980.soclk(soclk_out),
981.d(din[7:0]),
982.si({scan_in,so[6:0]}),
983.so({so[6:0],scan_out}),
984.q(dout[7:0])
985);
986
987
988
989
990
991
992
993
994
995
996
997
998
999
1000
1001
1002
1003
1004
1005
1006endmodule
1007
1008
1009
1010
1011
1012
1013
1014
1015
1016// general mux macro for pass-gate and and-or muxes with/wout priority encoders
1017// also for pass-gate with decoder
1018
1019
1020
1021
1022
1023// any PARAMS parms go into naming of macro
1024
1025module ifu_cmu_lsi_dp_mux_macro__mux_aonpe__ports_8__stack_34c__width_33 (
1026 din0,
1027 sel0,
1028 din1,
1029 sel1,
1030 din2,
1031 sel2,
1032 din3,
1033 sel3,
1034 din4,
1035 sel4,
1036 din5,
1037 sel5,
1038 din6,
1039 sel6,
1040 din7,
1041 sel7,
1042 dout);
1043wire buffout0;
1044wire buffout1;
1045wire buffout2;
1046wire buffout3;
1047wire buffout4;
1048wire buffout5;
1049wire buffout6;
1050wire buffout7;
1051
1052 input [32:0] din0;
1053 input sel0;
1054 input [32:0] din1;
1055 input sel1;
1056 input [32:0] din2;
1057 input sel2;
1058 input [32:0] din3;
1059 input sel3;
1060 input [32:0] din4;
1061 input sel4;
1062 input [32:0] din5;
1063 input sel5;
1064 input [32:0] din6;
1065 input sel6;
1066 input [32:0] din7;
1067 input sel7;
1068 output [32:0] dout;
1069
1070
1071
1072
1073
1074cl_dp1_muxbuff8_8x c0_0 (
1075 .in0(sel0),
1076 .in1(sel1),
1077 .in2(sel2),
1078 .in3(sel3),
1079 .in4(sel4),
1080 .in5(sel5),
1081 .in6(sel6),
1082 .in7(sel7),
1083 .out0(buffout0),
1084 .out1(buffout1),
1085 .out2(buffout2),
1086 .out3(buffout3),
1087 .out4(buffout4),
1088 .out5(buffout5),
1089 .out6(buffout6),
1090 .out7(buffout7)
1091);
1092mux8s #(33) d0_0 (
1093 .sel0(buffout0),
1094 .sel1(buffout1),
1095 .sel2(buffout2),
1096 .sel3(buffout3),
1097 .sel4(buffout4),
1098 .sel5(buffout5),
1099 .sel6(buffout6),
1100 .sel7(buffout7),
1101 .in0(din0[32:0]),
1102 .in1(din1[32:0]),
1103 .in2(din2[32:0]),
1104 .in3(din3[32:0]),
1105 .in4(din4[32:0]),
1106 .in5(din5[32:0]),
1107 .in6(din6[32:0]),
1108 .in7(din7[32:0]),
1109.dout(dout[32:0])
1110);
1111
1112
1113
1114
1115
1116
1117
1118
1119
1120
1121
1122
1123
1124endmodule
1125
1126
1127//
1128// buff macro
1129//
1130//
1131
1132
1133
1134
1135
1136module ifu_cmu_lsi_dp_buff_macro__stack_34c__width_33 (
1137 din,
1138 dout);
1139 input [32:0] din;
1140 output [32:0] dout;
1141
1142
1143
1144
1145
1146
1147buff #(33) d0_0 (
1148.in(din[32:0]),
1149.out(dout[32:0])
1150);
1151
1152
1153
1154
1155
1156
1157
1158
1159endmodule
1160
1161
1162
1163
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