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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ifu_cmu_msb_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ifu_cmu_msb_ctl ( | |
36 | tcu_scan_en, | |
37 | l2clk, | |
38 | scan_in, | |
39 | tcu_pce_ov, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | lsu_ifu_cmu_pmen, | |
43 | l15_spc_cpkt, | |
44 | ftu_fetch_f, | |
45 | ftu_cmiss, | |
46 | ftu_inv_req, | |
47 | ftu_redirect, | |
48 | cmu_req_st, | |
49 | cmu_canleave_st, | |
50 | lsc_l15_valid, | |
51 | cmu_data_ready, | |
52 | lsc_fill_rtn2, | |
53 | mdp_mbhit_q, | |
54 | mct_early_req, | |
55 | mct_real_wom, | |
56 | mct_upd_addr, | |
57 | cmu_has_dup_miss, | |
58 | mct_rst_dupmiss, | |
59 | mct_fill_complete, | |
60 | mct_ignore_cmiss, | |
61 | mct_clken, | |
62 | scan_out) ; | |
63 | wire pce_ov; | |
64 | wire stop; | |
65 | wire siclk; | |
66 | wire soclk; | |
67 | wire se; | |
68 | wire l1clk; | |
69 | wire pmen_lat_scanin; | |
70 | wire pmen_lat_scanout; | |
71 | wire [7:0] ftu_fetch_c; | |
72 | wire ifu_pmen; | |
73 | wire [7:0] cmu_has_dup_miss_din; | |
74 | wire [7:0] mct_e0_wom; | |
75 | wire [7:0] mct_e1_wom; | |
76 | wire [7:0] mct_e2_wom; | |
77 | wire [7:0] mct_e3_wom; | |
78 | wire [7:0] mct_e4_wom; | |
79 | wire [7:0] mct_e5_wom; | |
80 | wire [7:0] mct_e6_wom; | |
81 | wire [7:0] mct_e7_wom; | |
82 | wire dup_miss_lat_scanin; | |
83 | wire dup_miss_lat_scanout; | |
84 | wire [7:0] mct_real_miss; | |
85 | wire cmu_mbhit_c; | |
86 | wire redirect_reg_scanin; | |
87 | wire redirect_reg_scanout; | |
88 | wire [7:0] ftu_redirect_lat; | |
89 | wire [7:0] csm_rmwbit_reset; | |
90 | wire set_e0wom_bit0; | |
91 | wire [7:0] mdp_e0_wom; | |
92 | wire reset_e0wom_bit0; | |
93 | wire next_e0wom_bit0; | |
94 | wire set_e1wom_bit0; | |
95 | wire [7:0] mdp_e1_wom; | |
96 | wire reset_e1wom_bit0; | |
97 | wire next_e1wom_bit0; | |
98 | wire set_e2wom_bit0; | |
99 | wire [7:0] mdp_e2_wom; | |
100 | wire reset_e2wom_bit0; | |
101 | wire next_e2wom_bit0; | |
102 | wire set_e3wom_bit0; | |
103 | wire [7:0] mdp_e3_wom; | |
104 | wire reset_e3wom_bit0; | |
105 | wire next_e3wom_bit0; | |
106 | wire set_e4wom_bit0; | |
107 | wire [7:0] mdp_e4_wom; | |
108 | wire reset_e4wom_bit0; | |
109 | wire next_e4wom_bit0; | |
110 | wire set_e5wom_bit0; | |
111 | wire [7:0] mdp_e5_wom; | |
112 | wire reset_e5wom_bit0; | |
113 | wire next_e5wom_bit0; | |
114 | wire set_e6wom_bit0; | |
115 | wire [7:0] mdp_e6_wom; | |
116 | wire reset_e6wom_bit0; | |
117 | wire next_e6wom_bit0; | |
118 | wire set_e7wom_bit0; | |
119 | wire [7:0] mdp_e7_wom; | |
120 | wire reset_e7wom_bit0; | |
121 | wire next_e7wom_bit0; | |
122 | wire set_e0wom_bit1; | |
123 | wire reset_e0wom_bit1; | |
124 | wire next_e0wom_bit1; | |
125 | wire set_e1wom_bit1; | |
126 | wire reset_e1wom_bit1; | |
127 | wire next_e1wom_bit1; | |
128 | wire set_e2wom_bit1; | |
129 | wire reset_e2wom_bit1; | |
130 | wire next_e2wom_bit1; | |
131 | wire set_e3wom_bit1; | |
132 | wire reset_e3wom_bit1; | |
133 | wire next_e3wom_bit1; | |
134 | wire set_e4wom_bit1; | |
135 | wire reset_e4wom_bit1; | |
136 | wire next_e4wom_bit1; | |
137 | wire set_e5wom_bit1; | |
138 | wire reset_e5wom_bit1; | |
139 | wire next_e5wom_bit1; | |
140 | wire set_e6wom_bit1; | |
141 | wire reset_e6wom_bit1; | |
142 | wire next_e6wom_bit1; | |
143 | wire set_e7wom_bit1; | |
144 | wire reset_e7wom_bit1; | |
145 | wire next_e7wom_bit1; | |
146 | wire set_e0wom_bit2; | |
147 | wire reset_e0wom_bit2; | |
148 | wire next_e0wom_bit2; | |
149 | wire set_e1wom_bit2; | |
150 | wire reset_e1wom_bit2; | |
151 | wire next_e1wom_bit2; | |
152 | wire set_e2wom_bit2; | |
153 | wire reset_e2wom_bit2; | |
154 | wire next_e2wom_bit2; | |
155 | wire set_e3wom_bit2; | |
156 | wire reset_e3wom_bit2; | |
157 | wire next_e3wom_bit2; | |
158 | wire set_e4wom_bit2; | |
159 | wire reset_e4wom_bit2; | |
160 | wire next_e4wom_bit2; | |
161 | wire set_e5wom_bit2; | |
162 | wire reset_e5wom_bit2; | |
163 | wire next_e5wom_bit2; | |
164 | wire set_e6wom_bit2; | |
165 | wire reset_e6wom_bit2; | |
166 | wire next_e6wom_bit2; | |
167 | wire set_e7wom_bit2; | |
168 | wire reset_e7wom_bit2; | |
169 | wire next_e7wom_bit2; | |
170 | wire set_e0wom_bit3; | |
171 | wire reset_e0wom_bit3; | |
172 | wire next_e0wom_bit3; | |
173 | wire set_e1wom_bit3; | |
174 | wire reset_e1wom_bit3; | |
175 | wire next_e1wom_bit3; | |
176 | wire set_e2wom_bit3; | |
177 | wire reset_e2wom_bit3; | |
178 | wire next_e2wom_bit3; | |
179 | wire set_e3wom_bit3; | |
180 | wire reset_e3wom_bit3; | |
181 | wire next_e3wom_bit3; | |
182 | wire set_e4wom_bit3; | |
183 | wire reset_e4wom_bit3; | |
184 | wire next_e4wom_bit3; | |
185 | wire set_e5wom_bit3; | |
186 | wire reset_e5wom_bit3; | |
187 | wire next_e5wom_bit3; | |
188 | wire set_e6wom_bit3; | |
189 | wire reset_e6wom_bit3; | |
190 | wire next_e6wom_bit3; | |
191 | wire set_e7wom_bit3; | |
192 | wire reset_e7wom_bit3; | |
193 | wire next_e7wom_bit3; | |
194 | wire set_e0wom_bit4; | |
195 | wire reset_e0wom_bit4; | |
196 | wire next_e0wom_bit4; | |
197 | wire set_e1wom_bit4; | |
198 | wire reset_e1wom_bit4; | |
199 | wire next_e1wom_bit4; | |
200 | wire set_e2wom_bit4; | |
201 | wire reset_e2wom_bit4; | |
202 | wire next_e2wom_bit4; | |
203 | wire set_e3wom_bit4; | |
204 | wire reset_e3wom_bit4; | |
205 | wire next_e3wom_bit4; | |
206 | wire set_e4wom_bit4; | |
207 | wire reset_e4wom_bit4; | |
208 | wire next_e4wom_bit4; | |
209 | wire set_e5wom_bit4; | |
210 | wire reset_e5wom_bit4; | |
211 | wire next_e5wom_bit4; | |
212 | wire set_e6wom_bit4; | |
213 | wire reset_e6wom_bit4; | |
214 | wire next_e6wom_bit4; | |
215 | wire set_e7wom_bit4; | |
216 | wire reset_e7wom_bit4; | |
217 | wire next_e7wom_bit4; | |
218 | wire set_e0wom_bit5; | |
219 | wire reset_e0wom_bit5; | |
220 | wire next_e0wom_bit5; | |
221 | wire set_e1wom_bit5; | |
222 | wire reset_e1wom_bit5; | |
223 | wire next_e1wom_bit5; | |
224 | wire set_e2wom_bit5; | |
225 | wire reset_e2wom_bit5; | |
226 | wire next_e2wom_bit5; | |
227 | wire set_e3wom_bit5; | |
228 | wire reset_e3wom_bit5; | |
229 | wire next_e3wom_bit5; | |
230 | wire set_e4wom_bit5; | |
231 | wire reset_e4wom_bit5; | |
232 | wire next_e4wom_bit5; | |
233 | wire set_e5wom_bit5; | |
234 | wire reset_e5wom_bit5; | |
235 | wire next_e5wom_bit5; | |
236 | wire set_e6wom_bit5; | |
237 | wire reset_e6wom_bit5; | |
238 | wire next_e6wom_bit5; | |
239 | wire set_e7wom_bit5; | |
240 | wire reset_e7wom_bit5; | |
241 | wire next_e7wom_bit5; | |
242 | wire set_e0wom_bit6; | |
243 | wire reset_e0wom_bit6; | |
244 | wire next_e0wom_bit6; | |
245 | wire set_e1wom_bit6; | |
246 | wire reset_e1wom_bit6; | |
247 | wire next_e1wom_bit6; | |
248 | wire set_e2wom_bit6; | |
249 | wire reset_e2wom_bit6; | |
250 | wire next_e2wom_bit6; | |
251 | wire set_e3wom_bit6; | |
252 | wire reset_e3wom_bit6; | |
253 | wire next_e3wom_bit6; | |
254 | wire set_e4wom_bit6; | |
255 | wire reset_e4wom_bit6; | |
256 | wire next_e4wom_bit6; | |
257 | wire set_e5wom_bit6; | |
258 | wire reset_e5wom_bit6; | |
259 | wire next_e5wom_bit6; | |
260 | wire set_e6wom_bit6; | |
261 | wire reset_e6wom_bit6; | |
262 | wire next_e6wom_bit6; | |
263 | wire set_e7wom_bit6; | |
264 | wire reset_e7wom_bit6; | |
265 | wire next_e7wom_bit6; | |
266 | wire set_e0wom_bit7; | |
267 | wire reset_e0wom_bit7; | |
268 | wire next_e0wom_bit7; | |
269 | wire set_e1wom_bit7; | |
270 | wire reset_e1wom_bit7; | |
271 | wire next_e1wom_bit7; | |
272 | wire set_e2wom_bit7; | |
273 | wire reset_e2wom_bit7; | |
274 | wire next_e2wom_bit7; | |
275 | wire set_e3wom_bit7; | |
276 | wire reset_e3wom_bit7; | |
277 | wire next_e3wom_bit7; | |
278 | wire set_e4wom_bit7; | |
279 | wire reset_e4wom_bit7; | |
280 | wire next_e4wom_bit7; | |
281 | wire set_e5wom_bit7; | |
282 | wire reset_e5wom_bit7; | |
283 | wire next_e5wom_bit7; | |
284 | wire set_e6wom_bit7; | |
285 | wire reset_e6wom_bit7; | |
286 | wire next_e6wom_bit7; | |
287 | wire set_e7wom_bit7; | |
288 | wire reset_e7wom_bit7; | |
289 | wire next_e7wom_bit7; | |
290 | wire e0_wom_reg_f_scanin; | |
291 | wire e0_wom_reg_f_scanout; | |
292 | wire e1_wom_reg_f_scanin; | |
293 | wire e1_wom_reg_f_scanout; | |
294 | wire e2_wom_reg_f_scanin; | |
295 | wire e2_wom_reg_f_scanout; | |
296 | wire e3_wom_reg_f_scanin; | |
297 | wire e3_wom_reg_f_scanout; | |
298 | wire e4_wom_reg_f_scanin; | |
299 | wire e4_wom_reg_f_scanout; | |
300 | wire e5_wom_reg_f_scanin; | |
301 | wire e5_wom_reg_f_scanout; | |
302 | wire e6_wom_reg_f_scanin; | |
303 | wire e6_wom_reg_f_scanout; | |
304 | wire e7_wom_reg_f_scanin; | |
305 | wire e7_wom_reg_f_scanout; | |
306 | wire [7:0] cmu_fill_wom; | |
307 | wire [7:0] data_ready_bf; | |
308 | wire data_ready_reg_f_scanin; | |
309 | wire data_ready_reg_f_scanout; | |
310 | wire [7:0] data_ready_f; | |
311 | wire data_ready_reg_c_scanin; | |
312 | wire data_ready_reg_c_scanout; | |
313 | wire [7:0] data_ready_c; | |
314 | wire spares_scanin; | |
315 | wire spares_scanout; | |
316 | ||
317 | ||
318 | input tcu_scan_en ; | |
319 | input l2clk; | |
320 | input scan_in; | |
321 | input tcu_pce_ov; // scan signals | |
322 | input spc_aclk; | |
323 | input spc_bclk; | |
324 | ||
325 | input lsu_ifu_cmu_pmen; | |
326 | ||
327 | input [8:6] l15_spc_cpkt; | |
328 | ||
329 | input [7:0] ftu_fetch_f; //from ftu tsm | |
330 | input [7:0] ftu_cmiss; //from ftu tsm | |
331 | input [7:0] ftu_inv_req; //from ftu tsm | |
332 | input [7:0] ftu_redirect; //from ftu tsm | |
333 | ||
334 | input [7:0] cmu_req_st; | |
335 | input [7:0] cmu_canleave_st; | |
336 | input [7:0] lsc_l15_valid; | |
337 | ||
338 | ||
339 | input [7:0] cmu_data_ready; // rtn pkt ready | |
340 | input lsc_fill_rtn2; // second pkt being returned, any data rdy | |
341 | ||
342 | input [7:0] mdp_mbhit_q; // Raw hit in miss buffer | |
343 | ||
344 | ||
345 | output mct_early_req; | |
346 | ||
347 | output [7:0] mct_real_wom; // real wom bits | |
348 | ||
349 | ||
350 | ||
351 | output [7:0] mct_upd_addr; //one-hot signal, selects one MB line to be updated | |
352 | ||
353 | ||
354 | ||
355 | output [7:0] cmu_has_dup_miss; //indicates thr0 dup miss exists, goes to CMSM0 | |
356 | output [7:0] mct_rst_dupmiss; // reset duplicate miss wait state | |
357 | output [7:0] mct_fill_complete; // signal fill complete 2 cycles after data ready | |
358 | output mct_ignore_cmiss; // ignore cmiss for 3 cycles when data is being returned | |
359 | ||
360 | ||
361 | output [7:0] mct_clken; | |
362 | ||
363 | output scan_out; | |
364 | ||
365 | // scan renames | |
366 | assign pce_ov = tcu_pce_ov; | |
367 | assign stop = 1'b0; | |
368 | assign siclk = spc_aclk; | |
369 | assign soclk = spc_bclk; | |
370 | assign se = tcu_scan_en ; | |
371 | // end scan | |
372 | ||
373 | //output mdp_cache_bit; //cacheable bit from MB to CMSB | |
374 | //output mdp_par_bit; //parity bit from MB to ?? | |
375 | //assign l2clk = clk; | |
376 | ||
377 | /////////////////////////////////////////////////// | |
378 | // clock header | |
379 | /////////////////////////////////////////////////// | |
380 | ifu_cmu_msb_ctl_l1clkhdr_ctl_macro clkgen ( | |
381 | .l2clk(l2clk), | |
382 | .l1en (1'b1 ), | |
383 | .l1clk(l1clk), | |
384 | .pce_ov(pce_ov), | |
385 | .stop(stop), | |
386 | .se(se) | |
387 | ); | |
388 | //////////////////////////////////////////////////////// | |
389 | // | |
390 | // Form clk enable for misbuffer | |
391 | ifu_cmu_msb_ctl_msff_ctl_macro__width_9 pmen_lat ( | |
392 | .scan_in(pmen_lat_scanin), | |
393 | .scan_out(pmen_lat_scanout), | |
394 | .l1clk ( l1clk ), | |
395 | .din ({ ftu_fetch_f[7:0],lsu_ifu_cmu_pmen}), | |
396 | .dout ({ ftu_fetch_c[7:0], ifu_pmen}), | |
397 | .siclk(siclk), | |
398 | .soclk(soclk) | |
399 | ); | |
400 | ||
401 | ||
402 | assign mct_clken[7:0] = ftu_fetch_c[7:0] | ~{8{ifu_pmen}}; | |
403 | ||
404 | ||
405 | //////////////////////////////////////////////////////// | |
406 | // Duplicate miss logic | |
407 | // Detect whether there exists a duplicate miss for | |
408 | // current thread (or PA). WOM bit entries are used | |
409 | // to detect this duplicate miss. Diagonal bits are ignored | |
410 | // because they indicate REAL MISS. | |
411 | // mct_e*_wom are next_wom bits | |
412 | // mdp_e*_wom are latched wom bits | |
413 | //////////////////////////////////////////////////////// | |
414 | assign cmu_has_dup_miss_din[0] = (mct_e0_wom[7] | mct_e0_wom[6] | mct_e0_wom[5] | mct_e0_wom[4] | | |
415 | mct_e0_wom[3] | mct_e0_wom[2] | mct_e0_wom[1]); | |
416 | assign cmu_has_dup_miss_din[1] = (mct_e1_wom[7] | mct_e1_wom[6] | mct_e1_wom[5] | mct_e1_wom[4] | | |
417 | mct_e1_wom[3] | mct_e1_wom[2] | mct_e1_wom[0]); | |
418 | assign cmu_has_dup_miss_din[2] = (mct_e2_wom[7] | mct_e2_wom[6] | mct_e2_wom[5] | mct_e2_wom[4] | | |
419 | mct_e2_wom[3] | mct_e2_wom[1] | mct_e2_wom[0]); | |
420 | assign cmu_has_dup_miss_din[3] = (mct_e3_wom[7] | mct_e3_wom[6] | mct_e3_wom[5] | mct_e3_wom[4] | | |
421 | mct_e3_wom[2] | mct_e3_wom[1] | mct_e3_wom[0]); | |
422 | assign cmu_has_dup_miss_din[4] = (mct_e4_wom[7] | mct_e4_wom[6] | mct_e4_wom[5] | mct_e4_wom[3] | | |
423 | mct_e4_wom[2] | mct_e4_wom[1] | mct_e4_wom[0]); | |
424 | assign cmu_has_dup_miss_din[5] = (mct_e5_wom[7] | mct_e5_wom[6] | mct_e5_wom[4] | mct_e5_wom[3] | | |
425 | mct_e5_wom[2] | mct_e5_wom[1] | mct_e5_wom[0]); | |
426 | assign cmu_has_dup_miss_din[6] = (mct_e6_wom[7] | mct_e6_wom[5] | mct_e6_wom[4] | mct_e6_wom[3] | | |
427 | mct_e6_wom[2] | mct_e6_wom[1] | mct_e6_wom[0]); | |
428 | assign cmu_has_dup_miss_din[7] = (mct_e7_wom[6] | mct_e7_wom[5] | mct_e7_wom[4] | mct_e7_wom[3] | | |
429 | mct_e7_wom[2] | mct_e7_wom[1] | mct_e7_wom[0]); | |
430 | ||
431 | ||
432 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 dup_miss_lat ( | |
433 | .scan_in(dup_miss_lat_scanin), | |
434 | .scan_out(dup_miss_lat_scanout), | |
435 | .l1clk ( l1clk ), | |
436 | .din ({ cmu_has_dup_miss_din[7:0]}), | |
437 | .dout ({ cmu_has_dup_miss[7:0]}), | |
438 | .siclk(siclk), | |
439 | .soclk(soclk) | |
440 | ); | |
441 | ||
442 | //////////////////////////////////////////////////////// | |
443 | // Generate update signal for address, cacheable bit, | |
444 | // parity and replace way bits. | |
445 | //////////////////////////////////////////////////////// | |
446 | // enables for miss buffer | |
447 | assign mct_upd_addr[7:0] = (ftu_cmiss[7:0] | ftu_inv_req[7:0]); | |
448 | ||
449 | assign mct_real_miss[7:0] = ftu_cmiss[7:0] & {8{~cmu_mbhit_c}}; | |
450 | //////////////////////////////////////////////////////// | |
451 | // WOM bits to be filled in the WOM field of MB | |
452 | // If there is a flush, set the whole column to '0'. | |
453 | // If there is a cmiss, then use mbhit signal to select | |
454 | // the bit to be set. | |
455 | //////////////////////////////////////////////////////// | |
456 | ||
457 | // raw mbhit is generated if incoming address bits 39:5 match the | |
458 | // missbuffer entry and | |
459 | // neither incoming nor the missbuffer entries are non-cacheable and | |
460 | // neither incoming nor the missbuffer entries are inval_req | |
461 | ||
462 | ||
463 | assign cmu_mbhit_c = mdp_mbhit_q[0] | mdp_mbhit_q[1] | mdp_mbhit_q[2] | mdp_mbhit_q[3] | |
464 | | mdp_mbhit_q[4] | mdp_mbhit_q[5] | mdp_mbhit_q[6] | mdp_mbhit_q[7]; | |
465 | ||
466 | ||
467 | assign mct_early_req = |(ftu_cmiss[7:0]) & ~cmu_mbhit_c; | |
468 | ||
469 | ||
470 | //////////////////////////////////////////////////////// | |
471 | //////////////////////////////////////////////////////// | |
472 | // SET the WOM bits | |
473 | // Each thread sets an entire column in WOM array | |
474 | //////////////////////////////////////////////////////// | |
475 | ||
476 | // Reset the diagonal WOM bits which are the real miss bits | |
477 | // 1.When a Real Miss is flushed and it has no dup misses and no mbhit_q, | |
478 | // 2.When in canleave state, and has no dup misses and no mbhit_q | |
479 | // 3.Fill complete | |
480 | ||
481 | // use delayed version of ftu_redirect for resetting real miss wom bit, but use raw | |
482 | // version to reset dup miss wom bit. | |
483 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 redirect_reg ( | |
484 | .scan_in(redirect_reg_scanin), | |
485 | .scan_out(redirect_reg_scanout), | |
486 | .l1clk(l1clk), | |
487 | .din (ftu_redirect[7:0]), | |
488 | .dout (ftu_redirect_lat[7:0]), | |
489 | .siclk(siclk), | |
490 | .soclk(soclk) | |
491 | ); | |
492 | ||
493 | assign csm_rmwbit_reset[7:0] = (cmu_req_st[7:0] & ftu_redirect_lat[7:0] & ~lsc_l15_valid[7:0] & ~cmu_has_dup_miss[7:0] & ~mdp_mbhit_q[7:0]) | | |
494 | (cmu_canleave_st[7:0] & ~lsc_l15_valid[7:0] & ~cmu_has_dup_miss[7:0] & ~mdp_mbhit_q[7:0]) | | |
495 | mct_fill_complete[7:0]; | |
496 | ||
497 | // Thread0 | |
498 | //////////////////////////////////////////////////////// | |
499 | assign set_e0wom_bit0 = mdp_e0_wom[0] | mct_real_miss[0]; | |
500 | assign reset_e0wom_bit0 = csm_rmwbit_reset[0]; | |
501 | assign next_e0wom_bit0 = set_e0wom_bit0 & ~reset_e0wom_bit0; | |
502 | ||
503 | assign set_e1wom_bit0 = mdp_e1_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[1]); | |
504 | assign reset_e1wom_bit0 = ftu_redirect[0] | mct_fill_complete[1]; | |
505 | assign next_e1wom_bit0 = set_e1wom_bit0 & ~reset_e1wom_bit0; | |
506 | ||
507 | assign set_e2wom_bit0 = mdp_e2_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[2]); | |
508 | assign reset_e2wom_bit0 = ftu_redirect[0] | mct_fill_complete[2]; | |
509 | assign next_e2wom_bit0 = set_e2wom_bit0 & ~reset_e2wom_bit0; | |
510 | ||
511 | assign set_e3wom_bit0 = mdp_e3_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[3]); | |
512 | assign reset_e3wom_bit0 = ftu_redirect[0] | mct_fill_complete[3]; | |
513 | assign next_e3wom_bit0 = set_e3wom_bit0 & ~reset_e3wom_bit0; | |
514 | ||
515 | assign set_e4wom_bit0 = mdp_e4_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[4]); | |
516 | assign reset_e4wom_bit0 = ftu_redirect[0] | mct_fill_complete[4]; | |
517 | assign next_e4wom_bit0 = set_e4wom_bit0 & ~reset_e4wom_bit0; | |
518 | ||
519 | assign set_e5wom_bit0 = mdp_e5_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[5]); | |
520 | assign reset_e5wom_bit0 = ftu_redirect[0] | mct_fill_complete[5]; | |
521 | assign next_e5wom_bit0 = set_e5wom_bit0 & ~reset_e5wom_bit0; | |
522 | ||
523 | assign set_e6wom_bit0 = mdp_e6_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[6]); | |
524 | assign reset_e6wom_bit0 = ftu_redirect[0] | mct_fill_complete[6]; | |
525 | assign next_e6wom_bit0 = set_e6wom_bit0 & ~reset_e6wom_bit0; | |
526 | ||
527 | assign set_e7wom_bit0 = mdp_e7_wom[0] | (ftu_cmiss[0] & mdp_mbhit_q[7]); | |
528 | assign reset_e7wom_bit0 = ftu_redirect[0] | mct_fill_complete[7]; | |
529 | assign next_e7wom_bit0 = set_e7wom_bit0 & ~reset_e7wom_bit0; | |
530 | ||
531 | //////////////////////////////////////////////////////// | |
532 | // Thread1 | |
533 | //////////////////////////////////////////////////////// | |
534 | assign set_e0wom_bit1 = mdp_e0_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[0]); | |
535 | assign reset_e0wom_bit1 = ftu_redirect[1] | mct_fill_complete[0]; | |
536 | assign next_e0wom_bit1 = set_e0wom_bit1 & ~reset_e0wom_bit1; | |
537 | ||
538 | assign set_e1wom_bit1 = mdp_e1_wom[1] | mct_real_miss[1]; | |
539 | assign reset_e1wom_bit1 = csm_rmwbit_reset[1]; | |
540 | assign next_e1wom_bit1 = set_e1wom_bit1 & ~reset_e1wom_bit1; | |
541 | ||
542 | assign set_e2wom_bit1 = mdp_e2_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[2]); | |
543 | assign reset_e2wom_bit1 = ftu_redirect[1] | mct_fill_complete[2]; | |
544 | assign next_e2wom_bit1 = set_e2wom_bit1 & ~reset_e2wom_bit1; | |
545 | ||
546 | assign set_e3wom_bit1 = mdp_e3_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[3]); | |
547 | assign reset_e3wom_bit1 = ftu_redirect[1] | mct_fill_complete[3]; | |
548 | assign next_e3wom_bit1 = set_e3wom_bit1 & ~reset_e3wom_bit1; | |
549 | ||
550 | assign set_e4wom_bit1 = mdp_e4_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[4]); | |
551 | assign reset_e4wom_bit1 = ftu_redirect[1] | mct_fill_complete[4]; | |
552 | assign next_e4wom_bit1 = set_e4wom_bit1 & ~reset_e4wom_bit1; | |
553 | ||
554 | assign set_e5wom_bit1 = mdp_e5_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[5]); | |
555 | assign reset_e5wom_bit1 = ftu_redirect[1] | mct_fill_complete[5]; | |
556 | assign next_e5wom_bit1 = set_e5wom_bit1 & ~reset_e5wom_bit1; | |
557 | ||
558 | assign set_e6wom_bit1 = mdp_e6_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[6]); | |
559 | assign reset_e6wom_bit1 = ftu_redirect[1] | mct_fill_complete[6]; | |
560 | assign next_e6wom_bit1 = set_e6wom_bit1 & ~reset_e6wom_bit1; | |
561 | ||
562 | assign set_e7wom_bit1 = mdp_e7_wom[1] | (ftu_cmiss[1] & mdp_mbhit_q[7]); | |
563 | assign reset_e7wom_bit1 = ftu_redirect[1] | mct_fill_complete[7]; | |
564 | assign next_e7wom_bit1 = set_e7wom_bit1 & ~reset_e7wom_bit1; | |
565 | ||
566 | //////////////////////////////////////////////////////// | |
567 | // Thread2 | |
568 | //////////////////////////////////////////////////////// | |
569 | assign set_e0wom_bit2 = mdp_e0_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[0]); | |
570 | assign reset_e0wom_bit2 = ftu_redirect[2] | mct_fill_complete[0]; | |
571 | assign next_e0wom_bit2 = set_e0wom_bit2 & ~reset_e0wom_bit2; | |
572 | ||
573 | assign set_e1wom_bit2 = mdp_e1_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[1]); | |
574 | assign reset_e1wom_bit2 = ftu_redirect[2] | mct_fill_complete[1]; | |
575 | assign next_e1wom_bit2 = set_e1wom_bit2 & ~reset_e1wom_bit2; | |
576 | ||
577 | assign set_e2wom_bit2 = mdp_e2_wom[2] | mct_real_miss[2]; | |
578 | assign reset_e2wom_bit2 = csm_rmwbit_reset[2]; | |
579 | assign next_e2wom_bit2 = set_e2wom_bit2 & ~reset_e2wom_bit2; | |
580 | ||
581 | assign set_e3wom_bit2 = mdp_e3_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[3]); | |
582 | assign reset_e3wom_bit2 = ftu_redirect[2] | mct_fill_complete[3]; | |
583 | assign next_e3wom_bit2 = set_e3wom_bit2 & ~reset_e3wom_bit2; | |
584 | ||
585 | assign set_e4wom_bit2 = mdp_e4_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[4]); | |
586 | assign reset_e4wom_bit2 = ftu_redirect[2] | mct_fill_complete[4]; | |
587 | assign next_e4wom_bit2 = set_e4wom_bit2 & ~reset_e4wom_bit2; | |
588 | ||
589 | assign set_e5wom_bit2 = mdp_e5_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[5]); | |
590 | assign reset_e5wom_bit2 = ftu_redirect[2] | mct_fill_complete[5]; | |
591 | assign next_e5wom_bit2 = set_e5wom_bit2 & ~reset_e5wom_bit2; | |
592 | ||
593 | assign set_e6wom_bit2 = mdp_e6_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[6]); | |
594 | assign reset_e6wom_bit2 = ftu_redirect[2] | mct_fill_complete[6]; | |
595 | assign next_e6wom_bit2 = set_e6wom_bit2 & ~reset_e6wom_bit2; | |
596 | ||
597 | assign set_e7wom_bit2 = mdp_e7_wom[2] | (ftu_cmiss[2] & mdp_mbhit_q[7]); | |
598 | assign reset_e7wom_bit2 = ftu_redirect[2] | mct_fill_complete[7]; | |
599 | assign next_e7wom_bit2 = set_e7wom_bit2 & ~reset_e7wom_bit2; | |
600 | ||
601 | //////////////////////////////////////////////////////// | |
602 | // Thread3 | |
603 | //////////////////////////////////////////////////////// | |
604 | assign set_e0wom_bit3 = mdp_e0_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[0]); | |
605 | assign reset_e0wom_bit3 = ftu_redirect[3] | mct_fill_complete[0]; | |
606 | assign next_e0wom_bit3 = set_e0wom_bit3 & ~reset_e0wom_bit3; | |
607 | ||
608 | assign set_e1wom_bit3 = mdp_e1_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[1]); | |
609 | assign reset_e1wom_bit3 = ftu_redirect[3] | mct_fill_complete[1]; | |
610 | assign next_e1wom_bit3 = set_e1wom_bit3 & ~reset_e1wom_bit3; | |
611 | ||
612 | assign set_e2wom_bit3 = mdp_e2_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[2]); | |
613 | assign reset_e2wom_bit3 = ftu_redirect[3] | mct_fill_complete[2]; | |
614 | assign next_e2wom_bit3 = set_e2wom_bit3 & ~reset_e2wom_bit3; | |
615 | ||
616 | assign set_e3wom_bit3 = mdp_e3_wom[3] | mct_real_miss[3]; | |
617 | assign reset_e3wom_bit3 = csm_rmwbit_reset[3]; | |
618 | assign next_e3wom_bit3 = set_e3wom_bit3 & ~reset_e3wom_bit3; | |
619 | ||
620 | assign set_e4wom_bit3 = mdp_e4_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[4]); | |
621 | assign reset_e4wom_bit3 = ftu_redirect[3] | mct_fill_complete[4]; | |
622 | assign next_e4wom_bit3 = set_e4wom_bit3 & ~reset_e4wom_bit3; | |
623 | ||
624 | assign set_e5wom_bit3 = mdp_e5_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[5]); | |
625 | assign reset_e5wom_bit3 = ftu_redirect[3] | mct_fill_complete[5]; | |
626 | assign next_e5wom_bit3 = set_e5wom_bit3 & ~reset_e5wom_bit3; | |
627 | ||
628 | assign set_e6wom_bit3 = mdp_e6_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[6]); | |
629 | assign reset_e6wom_bit3 = ftu_redirect[3] | mct_fill_complete[6]; | |
630 | assign next_e6wom_bit3 = set_e6wom_bit3 & ~reset_e6wom_bit3; | |
631 | ||
632 | assign set_e7wom_bit3 = mdp_e7_wom[3] | (ftu_cmiss[3] & mdp_mbhit_q[7]); | |
633 | assign reset_e7wom_bit3 = ftu_redirect[3] | mct_fill_complete[7]; | |
634 | assign next_e7wom_bit3 = set_e7wom_bit3 & ~reset_e7wom_bit3; | |
635 | ||
636 | //////////////////////////////////////////////////////// | |
637 | // Thread4 | |
638 | //////////////////////////////////////////////////////// | |
639 | assign set_e0wom_bit4 = mdp_e0_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[0]); | |
640 | assign reset_e0wom_bit4 = ftu_redirect[4] | mct_fill_complete[0]; | |
641 | assign next_e0wom_bit4 = set_e0wom_bit4 & ~reset_e0wom_bit4; | |
642 | ||
643 | assign set_e1wom_bit4 = mdp_e1_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[1]); | |
644 | assign reset_e1wom_bit4 = ftu_redirect[4] | mct_fill_complete[1]; | |
645 | assign next_e1wom_bit4 = set_e1wom_bit4 & ~reset_e1wom_bit4; | |
646 | ||
647 | assign set_e2wom_bit4 = mdp_e2_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[2]); | |
648 | assign reset_e2wom_bit4 = ftu_redirect[4] | mct_fill_complete[2]; | |
649 | assign next_e2wom_bit4 = set_e2wom_bit4 & ~reset_e2wom_bit4; | |
650 | ||
651 | assign set_e3wom_bit4 = mdp_e3_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[3]); | |
652 | assign reset_e3wom_bit4 = ftu_redirect[4] | mct_fill_complete[3]; | |
653 | assign next_e3wom_bit4 = set_e3wom_bit4 & ~reset_e3wom_bit4; | |
654 | ||
655 | assign set_e4wom_bit4 = mdp_e4_wom[4] | mct_real_miss[4]; | |
656 | assign reset_e4wom_bit4 = csm_rmwbit_reset[4]; | |
657 | assign next_e4wom_bit4 = set_e4wom_bit4 & ~reset_e4wom_bit4; | |
658 | ||
659 | assign set_e5wom_bit4 = mdp_e5_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[5]); | |
660 | assign reset_e5wom_bit4 = ftu_redirect[4] | mct_fill_complete[5]; | |
661 | assign next_e5wom_bit4 = set_e5wom_bit4 & ~reset_e5wom_bit4; | |
662 | ||
663 | assign set_e6wom_bit4 = mdp_e6_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[6]); | |
664 | assign reset_e6wom_bit4 = ftu_redirect[4] | mct_fill_complete[6]; | |
665 | assign next_e6wom_bit4 = set_e6wom_bit4 & ~reset_e6wom_bit4; | |
666 | ||
667 | assign set_e7wom_bit4 = mdp_e7_wom[4] | (ftu_cmiss[4] & mdp_mbhit_q[7]); | |
668 | assign reset_e7wom_bit4 = ftu_redirect[4] | mct_fill_complete[7]; | |
669 | assign next_e7wom_bit4 = set_e7wom_bit4 & ~reset_e7wom_bit4; | |
670 | ||
671 | //////////////////////////////////////////////////////// | |
672 | // Thread5 | |
673 | //////////////////////////////////////////////////////// | |
674 | assign set_e0wom_bit5 = mdp_e0_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[0]); | |
675 | assign reset_e0wom_bit5 = ftu_redirect[5] | mct_fill_complete[0]; | |
676 | assign next_e0wom_bit5 = set_e0wom_bit5 & ~reset_e0wom_bit5; | |
677 | ||
678 | assign set_e1wom_bit5 = mdp_e1_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[1]); | |
679 | assign reset_e1wom_bit5 = ftu_redirect[5] | mct_fill_complete[1]; | |
680 | assign next_e1wom_bit5 = set_e1wom_bit5 & ~reset_e1wom_bit5; | |
681 | ||
682 | assign set_e2wom_bit5 = mdp_e2_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[2]); | |
683 | assign reset_e2wom_bit5 = ftu_redirect[5] | mct_fill_complete[2]; | |
684 | assign next_e2wom_bit5 = set_e2wom_bit5 & ~reset_e2wom_bit5; | |
685 | ||
686 | assign set_e3wom_bit5 = mdp_e3_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[3]); | |
687 | assign reset_e3wom_bit5 = ftu_redirect[5] | mct_fill_complete[3]; | |
688 | assign next_e3wom_bit5 = set_e3wom_bit5 & ~reset_e3wom_bit5; | |
689 | ||
690 | assign set_e4wom_bit5 = mdp_e4_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[4]); | |
691 | assign reset_e4wom_bit5 = ftu_redirect[5] | mct_fill_complete[4]; | |
692 | assign next_e4wom_bit5 = set_e4wom_bit5 & ~reset_e4wom_bit5; | |
693 | ||
694 | assign set_e5wom_bit5 = mdp_e5_wom[5] | mct_real_miss[5]; | |
695 | assign reset_e5wom_bit5 = csm_rmwbit_reset[5]; | |
696 | assign next_e5wom_bit5 = set_e5wom_bit5 & ~reset_e5wom_bit5; | |
697 | ||
698 | assign set_e6wom_bit5 = mdp_e6_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[6]); | |
699 | assign reset_e6wom_bit5 = ftu_redirect[5] | mct_fill_complete[6]; | |
700 | assign next_e6wom_bit5 = set_e6wom_bit5 & ~reset_e6wom_bit5; | |
701 | ||
702 | assign set_e7wom_bit5 = mdp_e7_wom[5] | (ftu_cmiss[5] & mdp_mbhit_q[7]); | |
703 | assign reset_e7wom_bit5 = ftu_redirect[5] | mct_fill_complete[7]; | |
704 | assign next_e7wom_bit5 = set_e7wom_bit5 & ~reset_e7wom_bit5; | |
705 | ||
706 | //////////////////////////////////////////////////////// | |
707 | // Thread6 | |
708 | //////////////////////////////////////////////////////// | |
709 | assign set_e0wom_bit6 = mdp_e0_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[0]); | |
710 | assign reset_e0wom_bit6 = ftu_redirect[6] | mct_fill_complete[0]; | |
711 | assign next_e0wom_bit6 = set_e0wom_bit6 & ~reset_e0wom_bit6; | |
712 | ||
713 | assign set_e1wom_bit6 = mdp_e1_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[1]); | |
714 | assign reset_e1wom_bit6 = ftu_redirect[6] | mct_fill_complete[1]; | |
715 | assign next_e1wom_bit6 = set_e1wom_bit6 & ~reset_e1wom_bit6; | |
716 | ||
717 | assign set_e2wom_bit6 = mdp_e2_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[2]); | |
718 | assign reset_e2wom_bit6 = ftu_redirect[6] | mct_fill_complete[2]; | |
719 | assign next_e2wom_bit6 = set_e2wom_bit6 & ~reset_e2wom_bit6; | |
720 | ||
721 | assign set_e3wom_bit6 = mdp_e3_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[3]); | |
722 | assign reset_e3wom_bit6 = ftu_redirect[6] | mct_fill_complete[3]; | |
723 | assign next_e3wom_bit6 = set_e3wom_bit6 & ~reset_e3wom_bit6; | |
724 | ||
725 | assign set_e4wom_bit6 = mdp_e4_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[4]); | |
726 | assign reset_e4wom_bit6 = ftu_redirect[6] | mct_fill_complete[4]; | |
727 | assign next_e4wom_bit6 = set_e4wom_bit6 & ~reset_e4wom_bit6; | |
728 | ||
729 | assign set_e5wom_bit6 = mdp_e5_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[5]); | |
730 | assign reset_e5wom_bit6 = ftu_redirect[6] | mct_fill_complete[5]; | |
731 | assign next_e5wom_bit6 = set_e5wom_bit6 & ~reset_e5wom_bit6; | |
732 | ||
733 | assign set_e6wom_bit6 = mdp_e6_wom[6] | mct_real_miss[6]; | |
734 | assign reset_e6wom_bit6 = csm_rmwbit_reset[6]; | |
735 | assign next_e6wom_bit6 = set_e6wom_bit6 & ~reset_e6wom_bit6; | |
736 | ||
737 | assign set_e7wom_bit6 = mdp_e7_wom[6] | (ftu_cmiss[6] & mdp_mbhit_q[7]); | |
738 | assign reset_e7wom_bit6 = ftu_redirect[6] | mct_fill_complete[7]; | |
739 | assign next_e7wom_bit6 = set_e7wom_bit6 & ~reset_e7wom_bit6; | |
740 | ||
741 | //////////////////////////////////////////////////////// | |
742 | // Thread7 | |
743 | //////////////////////////////////////////////////////// | |
744 | assign set_e0wom_bit7 = mdp_e0_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[0]); | |
745 | assign reset_e0wom_bit7 = ftu_redirect[7] | mct_fill_complete[0]; | |
746 | assign next_e0wom_bit7 = set_e0wom_bit7 & ~reset_e0wom_bit7; | |
747 | ||
748 | assign set_e1wom_bit7 = mdp_e1_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[1]); | |
749 | assign reset_e1wom_bit7 = ftu_redirect[7] | mct_fill_complete[1]; | |
750 | assign next_e1wom_bit7 = set_e1wom_bit7 & ~reset_e1wom_bit7; | |
751 | ||
752 | assign set_e2wom_bit7 = mdp_e2_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[2]); | |
753 | assign reset_e2wom_bit7 = ftu_redirect[7] | mct_fill_complete[2]; | |
754 | assign next_e2wom_bit7 = set_e2wom_bit7 & ~reset_e2wom_bit7; | |
755 | ||
756 | assign set_e3wom_bit7 = mdp_e3_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[3]); | |
757 | assign reset_e3wom_bit7 = ftu_redirect[7] | mct_fill_complete[3]; | |
758 | assign next_e3wom_bit7 = set_e3wom_bit7 & ~reset_e3wom_bit7; | |
759 | ||
760 | assign set_e4wom_bit7 = mdp_e4_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[4]); | |
761 | assign reset_e4wom_bit7 = ftu_redirect[7] | mct_fill_complete[4]; | |
762 | assign next_e4wom_bit7 = set_e4wom_bit7 & ~reset_e4wom_bit7; | |
763 | ||
764 | assign set_e5wom_bit7 = mdp_e5_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[5]); | |
765 | assign reset_e5wom_bit7 = ftu_redirect[7] | mct_fill_complete[5]; | |
766 | assign next_e5wom_bit7 = set_e5wom_bit7 & ~reset_e5wom_bit7; | |
767 | ||
768 | assign set_e6wom_bit7 = mdp_e6_wom[7] | (ftu_cmiss[7] & mdp_mbhit_q[6]); | |
769 | assign reset_e6wom_bit7 = ftu_redirect[7] | mct_fill_complete[6]; | |
770 | assign next_e6wom_bit7 = set_e6wom_bit7 & ~reset_e6wom_bit7; | |
771 | ||
772 | assign set_e7wom_bit7 = mdp_e7_wom[7] | mct_real_miss[7]; | |
773 | assign reset_e7wom_bit7 = csm_rmwbit_reset[7]; | |
774 | assign next_e7wom_bit7 = set_e7wom_bit7 & ~reset_e7wom_bit7; | |
775 | ||
776 | assign mct_e0_wom[7:0] = ({next_e0wom_bit7, next_e0wom_bit6, next_e0wom_bit5, next_e0wom_bit4, | |
777 | next_e0wom_bit3, next_e0wom_bit2, next_e0wom_bit1, next_e0wom_bit0}); | |
778 | assign mct_e1_wom[7:0] = ({next_e1wom_bit7, next_e1wom_bit6, next_e1wom_bit5, next_e1wom_bit4, | |
779 | next_e1wom_bit3, next_e1wom_bit2, next_e1wom_bit1, next_e1wom_bit0}); | |
780 | assign mct_e2_wom[7:0] = ({next_e2wom_bit7, next_e2wom_bit6, next_e2wom_bit5, next_e2wom_bit4, | |
781 | next_e2wom_bit3, next_e2wom_bit2, next_e2wom_bit1, next_e2wom_bit0}); | |
782 | assign mct_e3_wom[7:0] = ({next_e3wom_bit7, next_e3wom_bit6, next_e3wom_bit5, next_e3wom_bit4, | |
783 | next_e3wom_bit3, next_e3wom_bit2, next_e3wom_bit1, next_e3wom_bit0}); | |
784 | assign mct_e4_wom[7:0] = ({next_e4wom_bit7, next_e4wom_bit6, next_e4wom_bit5, next_e4wom_bit4, | |
785 | next_e4wom_bit3, next_e4wom_bit2, next_e4wom_bit1, next_e4wom_bit0}); | |
786 | assign mct_e5_wom[7:0] = ({next_e5wom_bit7, next_e5wom_bit6, next_e5wom_bit5, next_e5wom_bit4, | |
787 | next_e5wom_bit3, next_e5wom_bit2, next_e5wom_bit1, next_e5wom_bit0}); | |
788 | assign mct_e6_wom[7:0] = ({next_e6wom_bit7, next_e6wom_bit6, next_e6wom_bit5, next_e6wom_bit4, | |
789 | next_e6wom_bit3, next_e6wom_bit2, next_e6wom_bit1, next_e6wom_bit0}); | |
790 | assign mct_e7_wom[7:0] = ({next_e7wom_bit7, next_e7wom_bit6, next_e7wom_bit5, next_e7wom_bit4, | |
791 | next_e7wom_bit3, next_e7wom_bit2, next_e7wom_bit1, next_e7wom_bit0}); | |
792 | ||
793 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e0_wom_reg_f ( | |
794 | .scan_in(e0_wom_reg_f_scanin), | |
795 | .scan_out(e0_wom_reg_f_scanout), | |
796 | .l1clk( l1clk ), | |
797 | .din ({mct_e0_wom[7:0]}), | |
798 | .dout ({mdp_e0_wom[7:0]}), | |
799 | .siclk(siclk), | |
800 | .soclk(soclk) | |
801 | ); | |
802 | ||
803 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e1_wom_reg_f ( | |
804 | .scan_in(e1_wom_reg_f_scanin), | |
805 | .scan_out(e1_wom_reg_f_scanout), | |
806 | .l1clk( l1clk ), | |
807 | .din ({mct_e1_wom[7:0]}), | |
808 | .dout ({mdp_e1_wom[7:0]}), | |
809 | .siclk(siclk), | |
810 | .soclk(soclk) | |
811 | ); | |
812 | ||
813 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e2_wom_reg_f ( | |
814 | .scan_in(e2_wom_reg_f_scanin), | |
815 | .scan_out(e2_wom_reg_f_scanout), | |
816 | .l1clk( l1clk ), | |
817 | .din ({mct_e2_wom[7:0]}), | |
818 | .dout ({mdp_e2_wom[7:0]}), | |
819 | .siclk(siclk), | |
820 | .soclk(soclk) | |
821 | ); | |
822 | ||
823 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e3_wom_reg_f ( | |
824 | .scan_in(e3_wom_reg_f_scanin), | |
825 | .scan_out(e3_wom_reg_f_scanout), | |
826 | .l1clk( l1clk ), | |
827 | .din ({mct_e3_wom[7:0]}), | |
828 | .dout ({mdp_e3_wom[7:0]}), | |
829 | .siclk(siclk), | |
830 | .soclk(soclk) | |
831 | ); | |
832 | ||
833 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e4_wom_reg_f ( | |
834 | .scan_in(e4_wom_reg_f_scanin), | |
835 | .scan_out(e4_wom_reg_f_scanout), | |
836 | .l1clk( l1clk ), | |
837 | .din ({mct_e4_wom[7:0]}), | |
838 | .dout ({mdp_e4_wom[7:0]}), | |
839 | .siclk(siclk), | |
840 | .soclk(soclk) | |
841 | ); | |
842 | ||
843 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e5_wom_reg_f ( | |
844 | .scan_in(e5_wom_reg_f_scanin), | |
845 | .scan_out(e5_wom_reg_f_scanout), | |
846 | .l1clk( l1clk ), | |
847 | .din ({mct_e5_wom[7:0]}), | |
848 | .dout ({mdp_e5_wom[7:0]}), | |
849 | .siclk(siclk), | |
850 | .soclk(soclk) | |
851 | ); | |
852 | ||
853 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e6_wom_reg_f ( | |
854 | .scan_in(e6_wom_reg_f_scanin), | |
855 | .scan_out(e6_wom_reg_f_scanout), | |
856 | .l1clk( l1clk ), | |
857 | .din ({mct_e6_wom[7:0]}), | |
858 | .dout ({mdp_e6_wom[7:0]}), | |
859 | .siclk(siclk), | |
860 | .soclk(soclk) | |
861 | ); | |
862 | ||
863 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 e7_wom_reg_f ( | |
864 | .scan_in(e7_wom_reg_f_scanin), | |
865 | .scan_out(e7_wom_reg_f_scanout), | |
866 | .l1clk( l1clk ), | |
867 | .din ({mct_e7_wom[7:0]}), | |
868 | .dout ({mdp_e7_wom[7:0]}), | |
869 | .siclk(siclk), | |
870 | .soclk(soclk) | |
871 | ); | |
872 | ||
873 | assign mct_real_wom[7:0] = {mdp_e7_wom[7],mdp_e6_wom[6],mdp_e5_wom[5],mdp_e4_wom[4], | |
874 | mdp_e3_wom[3],mdp_e2_wom[2],mdp_e1_wom[1],mdp_e0_wom[0]}; | |
875 | ||
876 | assign cmu_fill_wom[7:0] = ({8{~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e0_wom[7:0]) | | |
877 | ({8{~l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & l15_spc_cpkt[6]}} & mdp_e1_wom[7:0]) | | |
878 | ({8{~l15_spc_cpkt[8] & l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e2_wom[7:0]) | | |
879 | ({8{~l15_spc_cpkt[8] & l15_spc_cpkt[7] & l15_spc_cpkt[6]}} & mdp_e3_wom[7:0]) | | |
880 | ({8{ l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e4_wom[7:0]) | | |
881 | ({8{ l15_spc_cpkt[8] & ~l15_spc_cpkt[7] & l15_spc_cpkt[6]}} & mdp_e5_wom[7:0]) | | |
882 | ({8{ l15_spc_cpkt[8] & l15_spc_cpkt[7] & ~l15_spc_cpkt[6]}} & mdp_e6_wom[7:0]) | | |
883 | ({8{ l15_spc_cpkt[8] & l15_spc_cpkt[7] & l15_spc_cpkt[6]}} & mdp_e7_wom[7:0]); | |
884 | ||
885 | assign mct_rst_dupmiss[7:0] = cmu_fill_wom[7:0] & {8{lsc_fill_rtn2}}; | |
886 | ||
887 | //////////////////////////////////////////////////////////////// | |
888 | // Ignore CMISS | |
889 | //////////////////////////////////////////////////////////////// | |
890 | // Ignore cmiss, if cmiss occurs in either of following three cycles | |
891 | // | bf | f | C | | |
892 | // |--------------------------------------------------------- | |
893 | // | DATA_READY | CMISS | CMISS | | |
894 | // | CMISS | (same line) | (same line) | | |
895 | // | (cmiss on same line| | | | |
896 | // | as data_ready) | | | | |
897 | // | |
898 | ||
899 | assign data_ready_bf[7:0] = cmu_data_ready[7:0]; | |
900 | ||
901 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 data_ready_reg_f ( | |
902 | .scan_in(data_ready_reg_f_scanin), | |
903 | .scan_out(data_ready_reg_f_scanout), | |
904 | .l1clk( l1clk ), | |
905 | .din ({data_ready_bf[7:0]}), | |
906 | .dout ({data_ready_f[7:0]}), | |
907 | .siclk(siclk), | |
908 | .soclk(soclk) | |
909 | ); | |
910 | ||
911 | ifu_cmu_msb_ctl_msff_ctl_macro__width_8 data_ready_reg_c ( | |
912 | .scan_in(data_ready_reg_c_scanin), | |
913 | .scan_out(data_ready_reg_c_scanout), | |
914 | .l1clk( l1clk ), | |
915 | .din ({data_ready_f[7:0]}), | |
916 | .dout ({data_ready_c[7:0]}), | |
917 | .siclk(siclk), | |
918 | .soclk(soclk) | |
919 | ); | |
920 | ||
921 | ||
922 | ||
923 | // ignore cache miss if it is a dup miss and a data ready for the parent thread has been sent | |
924 | // on one of prev 3 cycles. | |
925 | assign mct_ignore_cmiss = (mdp_mbhit_q[0] & (data_ready_bf[0] | data_ready_f[0] | data_ready_c[0])) | | |
926 | (mdp_mbhit_q[1] & (data_ready_bf[1] | data_ready_f[1] | data_ready_c[1])) | | |
927 | (mdp_mbhit_q[2] & (data_ready_bf[2] | data_ready_f[2] | data_ready_c[2])) | | |
928 | (mdp_mbhit_q[3] & (data_ready_bf[3] | data_ready_f[3] | data_ready_c[3])) | | |
929 | (mdp_mbhit_q[4] & (data_ready_bf[4] | data_ready_f[4] | data_ready_c[4])) | | |
930 | (mdp_mbhit_q[5] & (data_ready_bf[5] | data_ready_f[5] | data_ready_c[5])) | | |
931 | (mdp_mbhit_q[6] & (data_ready_bf[6] | data_ready_f[6] | data_ready_c[6])) | | |
932 | (mdp_mbhit_q[7] & (data_ready_bf[7] | data_ready_f[7] | data_ready_c[7])) ; | |
933 | ||
934 | ||
935 | // signal fill complete 2 cycles after data ready | |
936 | assign mct_fill_complete[7:0] = data_ready_c[7:0]; | |
937 | ||
938 | //////////////////////////////////////////////////////// | |
939 | // SPARE CELLS | |
940 | //////////////////////////////////////////////////////// | |
941 | ifu_cmu_msb_ctl_spare_ctl_macro__num_2 spares ( | |
942 | .scan_in(spares_scanin), | |
943 | .scan_out(spares_scanout), | |
944 | .l1clk (l1clk), | |
945 | .siclk(siclk), | |
946 | .soclk(soclk) | |
947 | ); | |
948 | //////////////////////////////////////////////////////// | |
949 | ||
950 | supply0 vss; | |
951 | supply1 vdd; | |
952 | // fixscan start: | |
953 | assign pmen_lat_scanin = scan_in ; | |
954 | assign dup_miss_lat_scanin = pmen_lat_scanout ; | |
955 | assign redirect_reg_scanin = dup_miss_lat_scanout ; | |
956 | assign e0_wom_reg_f_scanin = redirect_reg_scanout ; | |
957 | assign e1_wom_reg_f_scanin = e0_wom_reg_f_scanout ; | |
958 | assign e2_wom_reg_f_scanin = e1_wom_reg_f_scanout ; | |
959 | assign e3_wom_reg_f_scanin = e2_wom_reg_f_scanout ; | |
960 | assign e4_wom_reg_f_scanin = e3_wom_reg_f_scanout ; | |
961 | assign e5_wom_reg_f_scanin = e4_wom_reg_f_scanout ; | |
962 | assign e6_wom_reg_f_scanin = e5_wom_reg_f_scanout ; | |
963 | assign e7_wom_reg_f_scanin = e6_wom_reg_f_scanout ; | |
964 | assign data_ready_reg_f_scanin = e7_wom_reg_f_scanout ; | |
965 | assign data_ready_reg_c_scanin = data_ready_reg_f_scanout ; | |
966 | assign spares_scanin = data_ready_reg_c_scanout ; | |
967 | assign scan_out = spares_scanout ; | |
968 | ||
969 | // fixscan end: | |
970 | endmodule | |
971 | ||
972 | ||
973 | ||
974 | ||
975 | ||
976 | ||
977 | // any PARAMS parms go into naming of macro | |
978 | ||
979 | module ifu_cmu_msb_ctl_l1clkhdr_ctl_macro ( | |
980 | l2clk, | |
981 | l1en, | |
982 | pce_ov, | |
983 | stop, | |
984 | se, | |
985 | l1clk); | |
986 | ||
987 | ||
988 | input l2clk; | |
989 | input l1en; | |
990 | input pce_ov; | |
991 | input stop; | |
992 | input se; | |
993 | output l1clk; | |
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | cl_sc1_l1hdr_8x c_0 ( | |
1000 | ||
1001 | ||
1002 | .l2clk(l2clk), | |
1003 | .pce(l1en), | |
1004 | .l1clk(l1clk), | |
1005 | .se(se), | |
1006 | .pce_ov(pce_ov), | |
1007 | .stop(stop) | |
1008 | ); | |
1009 | ||
1010 | ||
1011 | ||
1012 | endmodule | |
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | ||
1025 | ||
1026 | // any PARAMS parms go into naming of macro | |
1027 | ||
1028 | module ifu_cmu_msb_ctl_msff_ctl_macro__width_9 ( | |
1029 | din, | |
1030 | l1clk, | |
1031 | scan_in, | |
1032 | siclk, | |
1033 | soclk, | |
1034 | dout, | |
1035 | scan_out); | |
1036 | wire [8:0] fdin; | |
1037 | wire [7:0] so; | |
1038 | ||
1039 | input [8:0] din; | |
1040 | input l1clk; | |
1041 | input scan_in; | |
1042 | ||
1043 | ||
1044 | input siclk; | |
1045 | input soclk; | |
1046 | ||
1047 | output [8:0] dout; | |
1048 | output scan_out; | |
1049 | assign fdin[8:0] = din[8:0]; | |
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | dff #(9) d0_0 ( | |
1057 | .l1clk(l1clk), | |
1058 | .siclk(siclk), | |
1059 | .soclk(soclk), | |
1060 | .d(fdin[8:0]), | |
1061 | .si({scan_in,so[7:0]}), | |
1062 | .so({so[7:0],scan_out}), | |
1063 | .q(dout[8:0]) | |
1064 | ); | |
1065 | ||
1066 | ||
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | endmodule | |
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | // any PARAMS parms go into naming of macro | |
1092 | ||
1093 | module ifu_cmu_msb_ctl_msff_ctl_macro__width_8 ( | |
1094 | din, | |
1095 | l1clk, | |
1096 | scan_in, | |
1097 | siclk, | |
1098 | soclk, | |
1099 | dout, | |
1100 | scan_out); | |
1101 | wire [7:0] fdin; | |
1102 | wire [6:0] so; | |
1103 | ||
1104 | input [7:0] din; | |
1105 | input l1clk; | |
1106 | input scan_in; | |
1107 | ||
1108 | ||
1109 | input siclk; | |
1110 | input soclk; | |
1111 | ||
1112 | output [7:0] dout; | |
1113 | output scan_out; | |
1114 | assign fdin[7:0] = din[7:0]; | |
1115 | ||
1116 | ||
1117 | ||
1118 | ||
1119 | ||
1120 | ||
1121 | dff #(8) d0_0 ( | |
1122 | .l1clk(l1clk), | |
1123 | .siclk(siclk), | |
1124 | .soclk(soclk), | |
1125 | .d(fdin[7:0]), | |
1126 | .si({scan_in,so[6:0]}), | |
1127 | .so({so[6:0],scan_out}), | |
1128 | .q(dout[7:0]) | |
1129 | ); | |
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 | ||
1142 | endmodule | |
1143 | ||
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | // Description: Spare gate macro for control blocks | |
1153 | // | |
1154 | // Param num controls the number of times the macro is added | |
1155 | // flops=0 can be used to use only combination spare logic | |
1156 | ||
1157 | ||
1158 | module ifu_cmu_msb_ctl_spare_ctl_macro__num_2 ( | |
1159 | l1clk, | |
1160 | scan_in, | |
1161 | siclk, | |
1162 | soclk, | |
1163 | scan_out); | |
1164 | wire si_0; | |
1165 | wire so_0; | |
1166 | wire spare0_flop_unused; | |
1167 | wire spare0_buf_32x_unused; | |
1168 | wire spare0_nand3_8x_unused; | |
1169 | wire spare0_inv_8x_unused; | |
1170 | wire spare0_aoi22_4x_unused; | |
1171 | wire spare0_buf_8x_unused; | |
1172 | wire spare0_oai22_4x_unused; | |
1173 | wire spare0_inv_16x_unused; | |
1174 | wire spare0_nand2_16x_unused; | |
1175 | wire spare0_nor3_4x_unused; | |
1176 | wire spare0_nand2_8x_unused; | |
1177 | wire spare0_buf_16x_unused; | |
1178 | wire spare0_nor2_16x_unused; | |
1179 | wire spare0_inv_32x_unused; | |
1180 | wire si_1; | |
1181 | wire so_1; | |
1182 | wire spare1_flop_unused; | |
1183 | wire spare1_buf_32x_unused; | |
1184 | wire spare1_nand3_8x_unused; | |
1185 | wire spare1_inv_8x_unused; | |
1186 | wire spare1_aoi22_4x_unused; | |
1187 | wire spare1_buf_8x_unused; | |
1188 | wire spare1_oai22_4x_unused; | |
1189 | wire spare1_inv_16x_unused; | |
1190 | wire spare1_nand2_16x_unused; | |
1191 | wire spare1_nor3_4x_unused; | |
1192 | wire spare1_nand2_8x_unused; | |
1193 | wire spare1_buf_16x_unused; | |
1194 | wire spare1_nor2_16x_unused; | |
1195 | wire spare1_inv_32x_unused; | |
1196 | ||
1197 | ||
1198 | input l1clk; | |
1199 | input scan_in; | |
1200 | input siclk; | |
1201 | input soclk; | |
1202 | output scan_out; | |
1203 | ||
1204 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1205 | .siclk(siclk), | |
1206 | .soclk(soclk), | |
1207 | .si(si_0), | |
1208 | .so(so_0), | |
1209 | .d(1'b0), | |
1210 | .q(spare0_flop_unused)); | |
1211 | assign si_0 = scan_in; | |
1212 | ||
1213 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1214 | .out(spare0_buf_32x_unused)); | |
1215 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1216 | .in1(1'b1), | |
1217 | .in2(1'b1), | |
1218 | .out(spare0_nand3_8x_unused)); | |
1219 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1220 | .out(spare0_inv_8x_unused)); | |
1221 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1222 | .in01(1'b1), | |
1223 | .in10(1'b1), | |
1224 | .in11(1'b1), | |
1225 | .out(spare0_aoi22_4x_unused)); | |
1226 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1227 | .out(spare0_buf_8x_unused)); | |
1228 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1229 | .in01(1'b1), | |
1230 | .in10(1'b1), | |
1231 | .in11(1'b1), | |
1232 | .out(spare0_oai22_4x_unused)); | |
1233 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1234 | .out(spare0_inv_16x_unused)); | |
1235 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1236 | .in1(1'b1), | |
1237 | .out(spare0_nand2_16x_unused)); | |
1238 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1239 | .in1(1'b0), | |
1240 | .in2(1'b0), | |
1241 | .out(spare0_nor3_4x_unused)); | |
1242 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1243 | .in1(1'b1), | |
1244 | .out(spare0_nand2_8x_unused)); | |
1245 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1246 | .out(spare0_buf_16x_unused)); | |
1247 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1248 | .in1(1'b0), | |
1249 | .out(spare0_nor2_16x_unused)); | |
1250 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1251 | .out(spare0_inv_32x_unused)); | |
1252 | ||
1253 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1254 | .siclk(siclk), | |
1255 | .soclk(soclk), | |
1256 | .si(si_1), | |
1257 | .so(so_1), | |
1258 | .d(1'b0), | |
1259 | .q(spare1_flop_unused)); | |
1260 | assign si_1 = so_0; | |
1261 | ||
1262 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1263 | .out(spare1_buf_32x_unused)); | |
1264 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1265 | .in1(1'b1), | |
1266 | .in2(1'b1), | |
1267 | .out(spare1_nand3_8x_unused)); | |
1268 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1269 | .out(spare1_inv_8x_unused)); | |
1270 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1271 | .in01(1'b1), | |
1272 | .in10(1'b1), | |
1273 | .in11(1'b1), | |
1274 | .out(spare1_aoi22_4x_unused)); | |
1275 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1276 | .out(spare1_buf_8x_unused)); | |
1277 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1278 | .in01(1'b1), | |
1279 | .in10(1'b1), | |
1280 | .in11(1'b1), | |
1281 | .out(spare1_oai22_4x_unused)); | |
1282 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1283 | .out(spare1_inv_16x_unused)); | |
1284 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1285 | .in1(1'b1), | |
1286 | .out(spare1_nand2_16x_unused)); | |
1287 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1288 | .in1(1'b0), | |
1289 | .in2(1'b0), | |
1290 | .out(spare1_nor3_4x_unused)); | |
1291 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1292 | .in1(1'b1), | |
1293 | .out(spare1_nand2_8x_unused)); | |
1294 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1295 | .out(spare1_buf_16x_unused)); | |
1296 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1297 | .in1(1'b0), | |
1298 | .out(spare1_nor2_16x_unused)); | |
1299 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1300 | .out(spare1_inv_32x_unused)); | |
1301 | assign scan_out = so_1; | |
1302 | ||
1303 | ||
1304 | ||
1305 | endmodule | |
1306 |