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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ifu_cmu_msb_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ifu_cmu_msb_dp ( | |
36 | tcu_scan_en, | |
37 | l2clk, | |
38 | scan_in, | |
39 | tcu_pce_ov, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | mct_clken, | |
43 | l15_spc_cpkt, | |
44 | ftu_paddr, | |
45 | ftu_rep_way, | |
46 | ftu_inv_req, | |
47 | ftu_thrx_un_cacheable, | |
48 | lsc_pending_req, | |
49 | lsc_req_sel, | |
50 | mct_upd_addr, | |
51 | mct_real_wom, | |
52 | mdp_mbhit_q, | |
53 | mdp_lsi_rway, | |
54 | ifu_l15_addr, | |
55 | mdp_lsi_nc_bit, | |
56 | mdp_lsi_inv_bit, | |
57 | cmu_fill_wrway, | |
58 | cmu_fill_paddr, | |
59 | scan_out) ; | |
60 | wire stop; | |
61 | wire se; | |
62 | wire pce_ov; | |
63 | wire siclk; | |
64 | wire soclk; | |
65 | wire ftu_thrx_un_cacheable_buf; | |
66 | wire [2:0] ftu_rep_way_buf; | |
67 | wire [39:0] ftu_paddr_buf; | |
68 | wire [44:0] e0_misc_dout; | |
69 | wire [44:0] e0_misc_din; | |
70 | wire [44:0] e1_misc_dout; | |
71 | wire [44:0] e1_misc_din; | |
72 | wire [44:0] e2_misc_dout; | |
73 | wire [44:0] e2_misc_din; | |
74 | wire [44:0] e3_misc_dout; | |
75 | wire [44:0] e3_misc_din; | |
76 | wire [44:0] e4_misc_dout; | |
77 | wire [44:0] e4_misc_din; | |
78 | wire [44:0] e5_misc_dout; | |
79 | wire [44:0] e5_misc_din; | |
80 | wire [44:0] e6_misc_dout; | |
81 | wire [44:0] e6_misc_din; | |
82 | wire [44:0] e7_misc_dout; | |
83 | wire [44:0] e7_misc_din; | |
84 | wire e0_phyaddr_reg_scanin; | |
85 | wire e0_phyaddr_reg_scanout; | |
86 | wire e1_phyaddr_reg_scanin; | |
87 | wire e1_phyaddr_reg_scanout; | |
88 | wire e2_phyaddr_reg_scanin; | |
89 | wire e2_phyaddr_reg_scanout; | |
90 | wire e3_phyaddr_reg_scanin; | |
91 | wire e3_phyaddr_reg_scanout; | |
92 | wire e4_phyaddr_reg_scanin; | |
93 | wire e4_phyaddr_reg_scanout; | |
94 | wire e5_phyaddr_reg_scanin; | |
95 | wire e5_phyaddr_reg_scanout; | |
96 | wire e6_phyaddr_reg_scanin; | |
97 | wire e6_phyaddr_reg_scanout; | |
98 | wire e7_phyaddr_reg_scanin; | |
99 | wire e7_phyaddr_reg_scanout; | |
100 | wire [7:0] cmp1_hit; | |
101 | wire [7:0] cmp2_hit; | |
102 | wire [2:0] cmu_fill_wrway_prebuf; | |
103 | wire [39:0] cmu_fill_paddr_prebuf; | |
104 | wire mdp_lsi_nc_bit_prebuf; | |
105 | wire mdp_lsi_inv_bit_prebuf; | |
106 | wire [2:0] mdp_lsi_rway_prebuf; | |
107 | wire [39:0] ifu_l15_addr_din; | |
108 | wire [39:0] ifu_l15_addr_mux; | |
109 | wire [39:39] ifu_l15_addr_muxbuf; | |
110 | wire [4:0] ifu_l15_addr_mux_bit4_0; | |
111 | wire [38:5] ifu_l15_addr_mux_minbuf; | |
112 | wire ifu_l15_lat0_scanin; | |
113 | wire ifu_l15_lat0_scanout; | |
114 | wire [39:0] ifu_l15_addr_prebuf; | |
115 | ||
116 | ||
117 | input tcu_scan_en ; | |
118 | input l2clk; | |
119 | input scan_in; | |
120 | input tcu_pce_ov; // scan signals | |
121 | input spc_aclk; | |
122 | input spc_bclk; | |
123 | ||
124 | input [7:0] mct_clken; | |
125 | ||
126 | input [8:6] l15_spc_cpkt; | |
127 | ||
128 | input [39:0] ftu_paddr; | |
129 | input [2:0] ftu_rep_way; | |
130 | input [7:0] ftu_inv_req; //from ftu tsm | |
131 | input ftu_thrx_un_cacheable; | |
132 | ||
133 | input lsc_pending_req; | |
134 | input [7:0] lsc_req_sel; //selected pending requests | |
135 | ||
136 | input [7:0] mct_upd_addr; //one-hot signal, selects one MB line to be updated for phys addr | |
137 | input [7:0] mct_real_wom; // real wom bits | |
138 | ||
139 | ||
140 | output [7:0] mdp_mbhit_q; // misbuffer hit | |
141 | ||
142 | ||
143 | output [2:0] mdp_lsi_rway; //MB to LSU | |
144 | output [39:0] ifu_l15_addr; //MB to lsu | |
145 | output mdp_lsi_nc_bit; //cacheable bit from MB to CMSB | |
146 | output mdp_lsi_inv_bit; //cacheable bit from MB to CMSB | |
147 | //output mdp_lsu_par_bit; //parity bit from MB to ?? | |
148 | ||
149 | output [2:0] cmu_fill_wrway; //MB to ?? | |
150 | output [39:0] cmu_fill_paddr;//MB to lsu | |
151 | //output mdp_fill_par_bit; //parity bit from MB to ?? | |
152 | ||
153 | output scan_out; | |
154 | ||
155 | // scan renames | |
156 | assign stop = 1'b0 ; | |
157 | // end scan | |
158 | ||
159 | //assign l2clk = clk; | |
160 | ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 test_rep0 ( | |
161 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk}), | |
162 | .dout({se,pce_ov,siclk,soclk}) | |
163 | ); | |
164 | ||
165 | // buffer ftu data before using it | |
166 | ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 ftu_data ( | |
167 | .din ({ftu_thrx_un_cacheable, ftu_rep_way[2:0], ftu_paddr[39:0]}), | |
168 | .dout ({ftu_thrx_un_cacheable_buf, ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}) | |
169 | ); | |
170 | ||
171 | //////////////////////////////////////////////////////////////// | |
172 | // Miss buffers | |
173 | // physical adress, cacheable bit, parity bit and replace way | |
174 | // registers for all entries | |
175 | //////////////////////////////////////////////////////////////// | |
176 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux0 ( | |
177 | .din1({e0_misc_dout[44:0]}), | |
178 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[0], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
179 | .sel0(mct_upd_addr[0]), | |
180 | .dout({e0_misc_din[44:0]}) | |
181 | ); | |
182 | ||
183 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux1 ( | |
184 | .din1({e1_misc_dout[44:0]}), | |
185 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[1], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
186 | .sel0(mct_upd_addr[1]), | |
187 | .dout({e1_misc_din[44:0]}) | |
188 | ); | |
189 | ||
190 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux2 ( | |
191 | .din1({e2_misc_dout[44:0]}), | |
192 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[2], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
193 | .sel0(mct_upd_addr[2]), | |
194 | .dout({e2_misc_din[44:0]}) | |
195 | ); | |
196 | ||
197 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux3 ( | |
198 | .din1({e3_misc_dout[44:0]}), | |
199 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[3], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
200 | .sel0(mct_upd_addr[3]), | |
201 | .dout({e3_misc_din[44:0]}) | |
202 | ); | |
203 | ||
204 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux4 ( | |
205 | .din1({e4_misc_dout[44:0]}), | |
206 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[4], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
207 | .sel0(mct_upd_addr[4]), | |
208 | .dout({e4_misc_din[44:0]}) | |
209 | ); | |
210 | ||
211 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux5 ( | |
212 | .din1({e5_misc_dout[44:0]}), | |
213 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[5], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
214 | .sel0(mct_upd_addr[5]), | |
215 | .dout({e5_misc_din[44:0]}) | |
216 | ); | |
217 | ||
218 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux6 ( | |
219 | .din1({e6_misc_dout[44:0]}), | |
220 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[6], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
221 | .sel0(mct_upd_addr[6]), | |
222 | .dout({e6_misc_din[44:0]}) | |
223 | ); | |
224 | ||
225 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 addr_upd_mux7 ( | |
226 | .din1({e7_misc_dout[44:0]}), | |
227 | .din0({ftu_thrx_un_cacheable_buf, ftu_inv_req[7], ftu_rep_way_buf[2:0], ftu_paddr_buf[39:0]}), | |
228 | .sel0(mct_upd_addr[7]), | |
229 | .dout({e7_misc_din[44:0]}) | |
230 | ); | |
231 | ||
232 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e0_phyaddr_reg ( | |
233 | .scan_in(e0_phyaddr_reg_scanin), | |
234 | .scan_out(e0_phyaddr_reg_scanout), | |
235 | .clk (l2clk), | |
236 | .en (mct_clken[0]), | |
237 | .din ({e0_misc_din[44:0]}), | |
238 | .dout({e0_misc_dout[44:0]}), | |
239 | .se(se), | |
240 | .siclk(siclk), | |
241 | .soclk(soclk), | |
242 | .pce_ov(pce_ov), | |
243 | .stop(stop) | |
244 | ); | |
245 | ||
246 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e1_phyaddr_reg ( | |
247 | .scan_in(e1_phyaddr_reg_scanin), | |
248 | .scan_out(e1_phyaddr_reg_scanout), | |
249 | .clk (l2clk), | |
250 | .en (mct_clken[1]), | |
251 | .din ({e1_misc_din[44:0]}), | |
252 | .dout({e1_misc_dout[44:0]}), | |
253 | .se(se), | |
254 | .siclk(siclk), | |
255 | .soclk(soclk), | |
256 | .pce_ov(pce_ov), | |
257 | .stop(stop) | |
258 | ); | |
259 | ||
260 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e2_phyaddr_reg ( | |
261 | .scan_in(e2_phyaddr_reg_scanin), | |
262 | .scan_out(e2_phyaddr_reg_scanout), | |
263 | .clk (l2clk), | |
264 | .en (mct_clken[2]), | |
265 | .din ({e2_misc_din[44:0]}), | |
266 | .dout({e2_misc_dout[44:0]}), | |
267 | .se(se), | |
268 | .siclk(siclk), | |
269 | .soclk(soclk), | |
270 | .pce_ov(pce_ov), | |
271 | .stop(stop) | |
272 | ); | |
273 | ||
274 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e3_phyaddr_reg ( | |
275 | .scan_in(e3_phyaddr_reg_scanin), | |
276 | .scan_out(e3_phyaddr_reg_scanout), | |
277 | .clk (l2clk), | |
278 | .en (mct_clken[3]), | |
279 | .din ({e3_misc_din[44:0]}), | |
280 | .dout({e3_misc_dout[44:0]}), | |
281 | .se(se), | |
282 | .siclk(siclk), | |
283 | .soclk(soclk), | |
284 | .pce_ov(pce_ov), | |
285 | .stop(stop) | |
286 | ); | |
287 | ||
288 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e4_phyaddr_reg ( | |
289 | .scan_in(e4_phyaddr_reg_scanin), | |
290 | .scan_out(e4_phyaddr_reg_scanout), | |
291 | .clk (l2clk), | |
292 | .en (mct_clken[4]), | |
293 | .din ({e4_misc_din[44:0]}), | |
294 | .dout({e4_misc_dout[44:0]}), | |
295 | .se(se), | |
296 | .siclk(siclk), | |
297 | .soclk(soclk), | |
298 | .pce_ov(pce_ov), | |
299 | .stop(stop) | |
300 | ); | |
301 | ||
302 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e5_phyaddr_reg ( | |
303 | .scan_in(e5_phyaddr_reg_scanin), | |
304 | .scan_out(e5_phyaddr_reg_scanout), | |
305 | .clk (l2clk), | |
306 | .en (mct_clken[5]), | |
307 | .din ({e5_misc_din[44:0]}), | |
308 | .dout({e5_misc_dout[44:0]}), | |
309 | .se(se), | |
310 | .siclk(siclk), | |
311 | .soclk(soclk), | |
312 | .pce_ov(pce_ov), | |
313 | .stop(stop) | |
314 | ); | |
315 | ||
316 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e6_phyaddr_reg ( | |
317 | .scan_in(e6_phyaddr_reg_scanin), | |
318 | .scan_out(e6_phyaddr_reg_scanout), | |
319 | .en (mct_clken[6]), | |
320 | .clk (l2clk), | |
321 | .din ({e6_misc_din[44:0]}), | |
322 | .dout({e6_misc_dout[44:0]}), | |
323 | .se(se), | |
324 | .siclk(siclk), | |
325 | .soclk(soclk), | |
326 | .pce_ov(pce_ov), | |
327 | .stop(stop) | |
328 | ); | |
329 | ||
330 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 e7_phyaddr_reg ( | |
331 | .scan_in(e7_phyaddr_reg_scanin), | |
332 | .scan_out(e7_phyaddr_reg_scanout), | |
333 | .clk (l2clk), | |
334 | .en (mct_clken[7]), | |
335 | .din ({e7_misc_din[44:0]}), // ifu_lsu_nc_bit_mux, ifu_lsu_rway_mux[2:0]}), | |
336 | .dout({e7_misc_dout[44:0]}), | |
337 | .se(se), | |
338 | .siclk(siclk), | |
339 | .soclk(soclk), | |
340 | .pce_ov(pce_ov), | |
341 | .stop(stop) // ifu_lsu_nc_bit , ifu_lsu_rway[2:0]}) | |
342 | ); | |
343 | ||
344 | //////////////////////////////////////////////////////////////// | |
345 | // hit/miss logic | |
346 | // never generate a hit if the incoming request is non-cacheable. | |
347 | // This is taken care of in cmp1. | |
348 | // never generate a hit if stored entry is non-cacheable, or | |
349 | // it is a inv_req. This is taken care of in cmp2 | |
350 | //////////////////////////////////////////////////////////////// | |
351 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e0_addrhit_cmp1 ( | |
352 | .dout( cmp1_hit[0]), | |
353 | .din1( {1'b0, e0_misc_dout[35:5]}), | |
354 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
355 | ); | |
356 | ||
357 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e1_addrhit_cmp1 ( | |
358 | .dout( cmp1_hit[1]), | |
359 | .din1( {1'b0, e1_misc_dout[35:5]}), | |
360 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
361 | ); | |
362 | ||
363 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e2_addrhit_cmp1 ( | |
364 | .dout( cmp1_hit[2]), | |
365 | .din1( {1'b0, e2_misc_dout[35:5]}), | |
366 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
367 | ); | |
368 | ||
369 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e3_addrhit_cmp1 ( | |
370 | .dout( cmp1_hit[3]), | |
371 | .din1( {1'b0, e3_misc_dout[35:5]}), | |
372 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
373 | ); | |
374 | ||
375 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e4_addrhit_cmp1 ( | |
376 | .dout( cmp1_hit[4]), | |
377 | .din1( {1'b0, e4_misc_dout[35:5]}), | |
378 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
379 | ); | |
380 | ||
381 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e5_addrhit_cmp1 ( | |
382 | .dout( cmp1_hit[5]), | |
383 | .din1( {1'b0, e5_misc_dout[35:5]}), | |
384 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
385 | ); | |
386 | ||
387 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e6_addrhit_cmp1 ( | |
388 | .dout( cmp1_hit[6]), | |
389 | .din1( {1'b0, e6_misc_dout[35:5]}), | |
390 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
391 | ); | |
392 | ||
393 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 e7_addrhit_cmp1 ( | |
394 | .dout( cmp1_hit[7]), | |
395 | .din1( {1'b0, e7_misc_dout[35:5]}), | |
396 | .din0( {1'b0, ftu_paddr_buf[35:5]}) | |
397 | ); | |
398 | ||
399 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e0_addrhit_cmp2 ( | |
400 | .dout(cmp2_hit[0]), | |
401 | .din1({e0_misc_dout[44:43], 1'b0, 1'b0, e0_misc_dout[39:36]}), | |
402 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
403 | ); | |
404 | ||
405 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e1_addrhit_cmp2 ( | |
406 | .dout(cmp2_hit[1]), | |
407 | .din1({e1_misc_dout[44:43], 1'b0, 1'b0, e1_misc_dout[39:36]}), | |
408 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
409 | ); | |
410 | ||
411 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e2_addrhit_cmp2 ( | |
412 | .dout(cmp2_hit[2]), | |
413 | .din1({e2_misc_dout[44:43], 1'b0, 1'b0, e2_misc_dout[39:36]}), | |
414 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
415 | ); | |
416 | ||
417 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e3_addrhit_cmp2 ( | |
418 | .dout(cmp2_hit[3]), | |
419 | .din1({e3_misc_dout[44:43], 1'b0, 1'b0, e3_misc_dout[39:36]}), | |
420 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
421 | ); | |
422 | ||
423 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e4_addrhit_cmp2 ( | |
424 | .dout(cmp2_hit[4]), | |
425 | .din1({e4_misc_dout[44:43], 1'b0, 1'b0, e4_misc_dout[39:36]}), | |
426 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
427 | ); | |
428 | ||
429 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e5_addrhit_cmp2 ( | |
430 | .dout(cmp2_hit[5]), | |
431 | .din1({e5_misc_dout[44:43], 1'b0, 1'b0, e5_misc_dout[39:36]}), | |
432 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
433 | ); | |
434 | ||
435 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e6_addrhit_cmp2 ( | |
436 | .dout(cmp2_hit[6]), | |
437 | .din1({e6_misc_dout[44:43], 1'b0, 1'b0, e6_misc_dout[39:36]}), | |
438 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
439 | ); | |
440 | ||
441 | ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 e7_addrhit_cmp2 ( | |
442 | .dout(cmp2_hit[7]), | |
443 | .din1({e7_misc_dout[44:43], 1'b0, 1'b0, e7_misc_dout[39:36]}), | |
444 | .din0({2'b00, 1'b0, ftu_thrx_un_cacheable_buf, ftu_paddr_buf[39:36]}) | |
445 | ); | |
446 | ||
447 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and0 ( | |
448 | .din0(cmp1_hit[0]), | |
449 | .din1(cmp2_hit[0]), | |
450 | .din2(mct_real_wom[0]), | |
451 | .dout(mdp_mbhit_q[0]) | |
452 | ); | |
453 | ||
454 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and1 ( | |
455 | .din0(cmp1_hit[1]), | |
456 | .din1(cmp2_hit[1]), | |
457 | .din2(mct_real_wom[1]), | |
458 | .dout(mdp_mbhit_q[1]) | |
459 | ); | |
460 | ||
461 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and2 ( | |
462 | .din0(cmp1_hit[2]), | |
463 | .din1(cmp2_hit[2]), | |
464 | .din2(mct_real_wom[2]), | |
465 | .dout(mdp_mbhit_q[2]) | |
466 | ); | |
467 | ||
468 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and3 ( | |
469 | .din0(cmp1_hit[3]), | |
470 | .din1(cmp2_hit[3]), | |
471 | .din2(mct_real_wom[3]), | |
472 | .dout(mdp_mbhit_q[3]) | |
473 | ); | |
474 | ||
475 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and4 ( | |
476 | .din0(cmp1_hit[4]), | |
477 | .din1(cmp2_hit[4]), | |
478 | .din2(mct_real_wom[4]), | |
479 | .dout(mdp_mbhit_q[4]) | |
480 | ); | |
481 | ||
482 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and5 ( | |
483 | .din0(cmp1_hit[5]), | |
484 | .din1(cmp2_hit[5]), | |
485 | .din2(mct_real_wom[5]), | |
486 | .dout(mdp_mbhit_q[5]) | |
487 | ); | |
488 | ||
489 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and6 ( | |
490 | .din0(cmp1_hit[6]), | |
491 | .din1(cmp2_hit[6]), | |
492 | .din2(mct_real_wom[6]), | |
493 | .dout(mdp_mbhit_q[6]) | |
494 | ); | |
495 | ||
496 | ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 and7 ( | |
497 | .din0(cmp1_hit[7]), | |
498 | .din1(cmp2_hit[7]), | |
499 | .din2(mct_real_wom[7]), | |
500 | .dout(mdp_mbhit_q[7]) | |
501 | ); | |
502 | ||
503 | //////////////////////////////////////////////////////////////// | |
504 | //////////////////////////////////////////////////////////////// | |
505 | // MUX OUT MB data and send it to ftu | |
506 | //////////////////////////////////////////////////////////////// | |
507 | // Mux out remaing bits based on the return thread id | |
508 | // sent to ftu | |
509 | ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 fillwait_data_mux2 ( | |
510 | .din0({e0_misc_dout[42:0]}), | |
511 | .din1({e1_misc_dout[42:0]}), | |
512 | .din2({e2_misc_dout[42:0]}), | |
513 | .din3({e3_misc_dout[42:0]}), | |
514 | .din4({e4_misc_dout[42:0]}), | |
515 | .din5({e5_misc_dout[42:0]}), | |
516 | .din6({e6_misc_dout[42:0]}), | |
517 | .din7({e7_misc_dout[42:0]}), | |
518 | .sel(l15_spc_cpkt[8:6]), | |
519 | .dout({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]}) | |
520 | ); | |
521 | ||
522 | ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 fillwait_data_buf2 ( | |
523 | .din ({cmu_fill_wrway_prebuf[2:0], cmu_fill_paddr_prebuf[39:0]}), | |
524 | .dout ({cmu_fill_wrway[2:0], cmu_fill_paddr[39:0]}) | |
525 | ); | |
526 | ||
527 | // mux out MB data to send request out to gkt | |
528 | // select based on pending req selected | |
529 | ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 cmu_data_mux1 ( | |
530 | .din0(e0_misc_dout[44:0]), | |
531 | .din1(e1_misc_dout[44:0]), | |
532 | .din2(e2_misc_dout[44:0]), | |
533 | .din3(e3_misc_dout[44:0]), | |
534 | .din4(e4_misc_dout[44:0]), | |
535 | .din5(e5_misc_dout[44:0]), | |
536 | .din6(e6_misc_dout[44:0]), | |
537 | .din7(e7_misc_dout[44:0]), | |
538 | .sel0(lsc_req_sel[0]), | |
539 | .sel1(lsc_req_sel[1]), | |
540 | .sel2(lsc_req_sel[2]), | |
541 | .sel3(lsc_req_sel[3]), | |
542 | .sel4(lsc_req_sel[4]), | |
543 | .sel5(lsc_req_sel[5]), | |
544 | .sel6(lsc_req_sel[6]), | |
545 | .sel7(lsc_req_sel[7]), | |
546 | .dout({mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_din[39:0]}) | |
547 | ); | |
548 | ||
549 | // Mux out incoming request if no pending req | |
550 | ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 ifu_l15_mux0 ( | |
551 | .din1(ftu_paddr_buf[39:0]), | |
552 | .din0(ifu_l15_addr_din[39:0]), | |
553 | .sel0(lsc_pending_req), | |
554 | .dout(ifu_l15_addr_mux[39:0]) | |
555 | ); | |
556 | ||
557 | // if bit 39 = 1, it indicates a NCU or L2 CSR request. | |
558 | // if bit 39 = 0, it is a l2 request, and bits 4:0 need to be | |
559 | // cleared in this case. | |
560 | ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 ifu_l15_and_4_0 | |
561 | ( | |
562 | .din1({5{ifu_l15_addr_muxbuf[39]}}), | |
563 | .din0(ifu_l15_addr_mux[4:0]), | |
564 | .dout(ifu_l15_addr_mux_bit4_0[4:0]) | |
565 | ); | |
566 | ||
567 | ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 ifu_l15_minbuf ( | |
568 | .din ({ifu_l15_addr_mux[38:5]}), | |
569 | .dout ({ifu_l15_addr_mux_minbuf[38:5]}) | |
570 | ); | |
571 | ||
572 | ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 ifu_l15_lat0 ( | |
573 | .scan_in(ifu_l15_lat0_scanin), | |
574 | .scan_out(ifu_l15_lat0_scanout), | |
575 | .clk (l2clk), | |
576 | .en (1'b1), | |
577 | .din ({ifu_l15_addr_muxbuf[39],ifu_l15_addr_mux_minbuf[38:5], ifu_l15_addr_mux_bit4_0[4:0]}), | |
578 | .dout({ifu_l15_addr_prebuf[39:0]}), | |
579 | .se(se), | |
580 | .siclk(siclk), | |
581 | .soclk(soclk), | |
582 | .pce_ov(pce_ov), | |
583 | .stop(stop) | |
584 | ); | |
585 | ||
586 | ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 ifu_l15_buf0 ( | |
587 | .din ({ifu_l15_addr_mux[39], mdp_lsi_nc_bit_prebuf, mdp_lsi_inv_bit_prebuf, mdp_lsi_rway_prebuf[2:0], ifu_l15_addr_prebuf[39:0]}), | |
588 | .dout ({ifu_l15_addr_muxbuf[39], mdp_lsi_nc_bit, mdp_lsi_inv_bit, mdp_lsi_rway[2:0], ifu_l15_addr[39:0]}) | |
589 | ); | |
590 | ||
591 | ||
592 | // fixscan start: | |
593 | assign e0_phyaddr_reg_scanin = scan_in ; | |
594 | assign e1_phyaddr_reg_scanin = e0_phyaddr_reg_scanout ; | |
595 | assign e2_phyaddr_reg_scanin = e1_phyaddr_reg_scanout ; | |
596 | assign e3_phyaddr_reg_scanin = e2_phyaddr_reg_scanout ; | |
597 | assign e4_phyaddr_reg_scanin = e3_phyaddr_reg_scanout ; | |
598 | assign e5_phyaddr_reg_scanin = e4_phyaddr_reg_scanout ; | |
599 | assign e6_phyaddr_reg_scanin = e5_phyaddr_reg_scanout ; | |
600 | assign e7_phyaddr_reg_scanin = e6_phyaddr_reg_scanout ; | |
601 | assign ifu_l15_lat0_scanin = e7_phyaddr_reg_scanout ; | |
602 | assign scan_out = ifu_l15_lat0_scanout ; | |
603 | // fixscan end: | |
604 | endmodule | |
605 | ||
606 | ||
607 | // | |
608 | // buff macro | |
609 | // | |
610 | // | |
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | module ifu_cmu_msb_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_4 ( | |
617 | din, | |
618 | dout); | |
619 | input [3:0] din; | |
620 | output [3:0] dout; | |
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | buff #(4) d0_0 ( | |
628 | .in(din[3:0]), | |
629 | .out(dout[3:0]) | |
630 | ); | |
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | endmodule | |
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | // | |
646 | // buff macro | |
647 | // | |
648 | // | |
649 | ||
650 | ||
651 | ||
652 | ||
653 | ||
654 | module ifu_cmu_msb_dp_buff_macro__stack_60c__width_44 ( | |
655 | din, | |
656 | dout); | |
657 | input [43:0] din; | |
658 | output [43:0] dout; | |
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | buff #(44) d0_0 ( | |
666 | .in(din[43:0]), | |
667 | .out(dout[43:0]) | |
668 | ); | |
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | endmodule | |
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
684 | // also for pass-gate with decoder | |
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | // any PARAMS parms go into naming of macro | |
691 | ||
692 | module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_45 ( | |
693 | din0, | |
694 | din1, | |
695 | sel0, | |
696 | dout); | |
697 | wire psel0; | |
698 | wire psel1; | |
699 | ||
700 | input [44:0] din0; | |
701 | input [44:0] din1; | |
702 | input sel0; | |
703 | output [44:0] dout; | |
704 | ||
705 | ||
706 | ||
707 | ||
708 | ||
709 | cl_dp1_penc2_8x c0_0 ( | |
710 | .sel0(sel0), | |
711 | .psel0(psel0), | |
712 | .psel1(psel1) | |
713 | ); | |
714 | ||
715 | mux2s #(45) d0_0 ( | |
716 | .sel0(psel0), | |
717 | .sel1(psel1), | |
718 | .in0(din0[44:0]), | |
719 | .in1(din1[44:0]), | |
720 | .dout(dout[44:0]) | |
721 | ); | |
722 | ||
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | ||
734 | ||
735 | endmodule | |
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | // any PARAMS parms go into naming of macro | |
743 | ||
744 | module ifu_cmu_msb_dp_msff_macro__stack_60c__width_45 ( | |
745 | din, | |
746 | clk, | |
747 | en, | |
748 | se, | |
749 | scan_in, | |
750 | siclk, | |
751 | soclk, | |
752 | pce_ov, | |
753 | stop, | |
754 | dout, | |
755 | scan_out); | |
756 | wire l1clk; | |
757 | wire siclk_out; | |
758 | wire soclk_out; | |
759 | wire [43:0] so; | |
760 | ||
761 | input [44:0] din; | |
762 | ||
763 | ||
764 | input clk; | |
765 | input en; | |
766 | input se; | |
767 | input scan_in; | |
768 | input siclk; | |
769 | input soclk; | |
770 | input pce_ov; | |
771 | input stop; | |
772 | ||
773 | ||
774 | ||
775 | output [44:0] dout; | |
776 | ||
777 | ||
778 | output scan_out; | |
779 | ||
780 | ||
781 | ||
782 | ||
783 | cl_dp1_l1hdr_8x c0_0 ( | |
784 | .l2clk(clk), | |
785 | .pce(en), | |
786 | .aclk(siclk), | |
787 | .bclk(soclk), | |
788 | .l1clk(l1clk), | |
789 | .se(se), | |
790 | .pce_ov(pce_ov), | |
791 | .stop(stop), | |
792 | .siclk_out(siclk_out), | |
793 | .soclk_out(soclk_out) | |
794 | ); | |
795 | dff #(45) d0_0 ( | |
796 | .l1clk(l1clk), | |
797 | .siclk(siclk_out), | |
798 | .soclk(soclk_out), | |
799 | .d(din[44:0]), | |
800 | .si({scan_in,so[43:0]}), | |
801 | .so({so[43:0],scan_out}), | |
802 | .q(dout[44:0]) | |
803 | ); | |
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | ||
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | endmodule | |
825 | ||
826 | ||
827 | ||
828 | ||
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | // | |
835 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
836 | // | |
837 | // | |
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_32 ( | |
844 | din0, | |
845 | din1, | |
846 | dout); | |
847 | input [31:0] din0; | |
848 | input [31:0] din1; | |
849 | output dout; | |
850 | ||
851 | ||
852 | ||
853 | ||
854 | ||
855 | ||
856 | cmp #(32) m0_0 ( | |
857 | .in0(din0[31:0]), | |
858 | .in1(din1[31:0]), | |
859 | .out(dout) | |
860 | ); | |
861 | ||
862 | ||
863 | ||
864 | ||
865 | ||
866 | ||
867 | ||
868 | ||
869 | ||
870 | ||
871 | endmodule | |
872 | ||
873 | ||
874 | ||
875 | ||
876 | ||
877 | // | |
878 | // comparator macro (output is 1 if both inputs are equal; 0 otherwise) | |
879 | // | |
880 | // | |
881 | ||
882 | ||
883 | ||
884 | ||
885 | ||
886 | module ifu_cmu_msb_dp_cmp_macro__dcmp_8x__width_8 ( | |
887 | din0, | |
888 | din1, | |
889 | dout); | |
890 | input [7:0] din0; | |
891 | input [7:0] din1; | |
892 | output dout; | |
893 | ||
894 | ||
895 | ||
896 | ||
897 | ||
898 | ||
899 | cmp #(8) m0_0 ( | |
900 | .in0(din0[7:0]), | |
901 | .in1(din1[7:0]), | |
902 | .out(dout) | |
903 | ); | |
904 | ||
905 | ||
906 | ||
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | ||
914 | endmodule | |
915 | ||
916 | ||
917 | ||
918 | ||
919 | ||
920 | // | |
921 | // and macro for ports = 2,3,4 | |
922 | // | |
923 | // | |
924 | ||
925 | ||
926 | ||
927 | ||
928 | ||
929 | module ifu_cmu_msb_dp_and_macro__ports_3__stack_2l__width_1 ( | |
930 | din0, | |
931 | din1, | |
932 | din2, | |
933 | dout); | |
934 | input [0:0] din0; | |
935 | input [0:0] din1; | |
936 | input [0:0] din2; | |
937 | output [0:0] dout; | |
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | and3 #(1) d0_0 ( | |
945 | .in0(din0[0:0]), | |
946 | .in1(din1[0:0]), | |
947 | .in2(din2[0:0]), | |
948 | .out(dout[0:0]) | |
949 | ); | |
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | endmodule | |
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
966 | // also for pass-gate with decoder | |
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | // any PARAMS parms go into naming of macro | |
973 | ||
974 | module ifu_cmu_msb_dp_mux_macro__mux_aodec__ports_8__stack_60c__width_43 ( | |
975 | din0, | |
976 | din1, | |
977 | din2, | |
978 | din3, | |
979 | din4, | |
980 | din5, | |
981 | din6, | |
982 | din7, | |
983 | sel, | |
984 | dout); | |
985 | wire psel0; | |
986 | wire psel1; | |
987 | wire psel2; | |
988 | wire psel3; | |
989 | wire psel4; | |
990 | wire psel5; | |
991 | wire psel6; | |
992 | wire psel7; | |
993 | ||
994 | input [42:0] din0; | |
995 | input [42:0] din1; | |
996 | input [42:0] din2; | |
997 | input [42:0] din3; | |
998 | input [42:0] din4; | |
999 | input [42:0] din5; | |
1000 | input [42:0] din6; | |
1001 | input [42:0] din7; | |
1002 | input [2:0] sel; | |
1003 | output [42:0] dout; | |
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | cl_dp1_pdec8_8x c0_0 ( | |
1010 | .test(1'b1), | |
1011 | .sel0(sel[0]), | |
1012 | .sel1(sel[1]), | |
1013 | .sel2(sel[2]), | |
1014 | .psel0(psel0), | |
1015 | .psel1(psel1), | |
1016 | .psel2(psel2), | |
1017 | .psel3(psel3), | |
1018 | .psel4(psel4), | |
1019 | .psel5(psel5), | |
1020 | .psel6(psel6), | |
1021 | .psel7(psel7) | |
1022 | ); | |
1023 | ||
1024 | mux8s #(43) d0_0 ( | |
1025 | .sel0(psel0), | |
1026 | .sel1(psel1), | |
1027 | .sel2(psel2), | |
1028 | .sel3(psel3), | |
1029 | .sel4(psel4), | |
1030 | .sel5(psel5), | |
1031 | .sel6(psel6), | |
1032 | .sel7(psel7), | |
1033 | .in0(din0[42:0]), | |
1034 | .in1(din1[42:0]), | |
1035 | .in2(din2[42:0]), | |
1036 | .in3(din3[42:0]), | |
1037 | .in4(din4[42:0]), | |
1038 | .in5(din5[42:0]), | |
1039 | .in6(din6[42:0]), | |
1040 | .in7(din7[42:0]), | |
1041 | .dout(dout[42:0]) | |
1042 | ); | |
1043 | ||
1044 | ||
1045 | ||
1046 | ||
1047 | ||
1048 | ||
1049 | ||
1050 | ||
1051 | ||
1052 | ||
1053 | ||
1054 | ||
1055 | ||
1056 | endmodule | |
1057 | ||
1058 | ||
1059 | // | |
1060 | // buff macro | |
1061 | // | |
1062 | // | |
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | module ifu_cmu_msb_dp_buff_macro__stack_60c__width_43 ( | |
1069 | din, | |
1070 | dout); | |
1071 | input [42:0] din; | |
1072 | output [42:0] dout; | |
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | buff #(43) d0_0 ( | |
1080 | .in(din[42:0]), | |
1081 | .out(dout[42:0]) | |
1082 | ); | |
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | ||
1090 | ||
1091 | endmodule | |
1092 | ||
1093 | ||
1094 | ||
1095 | ||
1096 | ||
1097 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1098 | // also for pass-gate with decoder | |
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | ||
1104 | // any PARAMS parms go into naming of macro | |
1105 | ||
1106 | module ifu_cmu_msb_dp_mux_macro__mux_aonpe__ports_8__stack_60c__width_45 ( | |
1107 | din0, | |
1108 | sel0, | |
1109 | din1, | |
1110 | sel1, | |
1111 | din2, | |
1112 | sel2, | |
1113 | din3, | |
1114 | sel3, | |
1115 | din4, | |
1116 | sel4, | |
1117 | din5, | |
1118 | sel5, | |
1119 | din6, | |
1120 | sel6, | |
1121 | din7, | |
1122 | sel7, | |
1123 | dout); | |
1124 | wire buffout0; | |
1125 | wire buffout1; | |
1126 | wire buffout2; | |
1127 | wire buffout3; | |
1128 | wire buffout4; | |
1129 | wire buffout5; | |
1130 | wire buffout6; | |
1131 | wire buffout7; | |
1132 | ||
1133 | input [44:0] din0; | |
1134 | input sel0; | |
1135 | input [44:0] din1; | |
1136 | input sel1; | |
1137 | input [44:0] din2; | |
1138 | input sel2; | |
1139 | input [44:0] din3; | |
1140 | input sel3; | |
1141 | input [44:0] din4; | |
1142 | input sel4; | |
1143 | input [44:0] din5; | |
1144 | input sel5; | |
1145 | input [44:0] din6; | |
1146 | input sel6; | |
1147 | input [44:0] din7; | |
1148 | input sel7; | |
1149 | output [44:0] dout; | |
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | cl_dp1_muxbuff8_8x c0_0 ( | |
1156 | .in0(sel0), | |
1157 | .in1(sel1), | |
1158 | .in2(sel2), | |
1159 | .in3(sel3), | |
1160 | .in4(sel4), | |
1161 | .in5(sel5), | |
1162 | .in6(sel6), | |
1163 | .in7(sel7), | |
1164 | .out0(buffout0), | |
1165 | .out1(buffout1), | |
1166 | .out2(buffout2), | |
1167 | .out3(buffout3), | |
1168 | .out4(buffout4), | |
1169 | .out5(buffout5), | |
1170 | .out6(buffout6), | |
1171 | .out7(buffout7) | |
1172 | ); | |
1173 | mux8s #(45) d0_0 ( | |
1174 | .sel0(buffout0), | |
1175 | .sel1(buffout1), | |
1176 | .sel2(buffout2), | |
1177 | .sel3(buffout3), | |
1178 | .sel4(buffout4), | |
1179 | .sel5(buffout5), | |
1180 | .sel6(buffout6), | |
1181 | .sel7(buffout7), | |
1182 | .in0(din0[44:0]), | |
1183 | .in1(din1[44:0]), | |
1184 | .in2(din2[44:0]), | |
1185 | .in3(din3[44:0]), | |
1186 | .in4(din4[44:0]), | |
1187 | .in5(din5[44:0]), | |
1188 | .in6(din6[44:0]), | |
1189 | .in7(din7[44:0]), | |
1190 | .dout(dout[44:0]) | |
1191 | ); | |
1192 | ||
1193 | ||
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | ||
1201 | ||
1202 | ||
1203 | ||
1204 | ||
1205 | endmodule | |
1206 | ||
1207 | ||
1208 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1209 | // also for pass-gate with decoder | |
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | // any PARAMS parms go into naming of macro | |
1216 | ||
1217 | module ifu_cmu_msb_dp_mux_macro__mux_aope__ports_2__stack_60c__width_40 ( | |
1218 | din0, | |
1219 | din1, | |
1220 | sel0, | |
1221 | dout); | |
1222 | wire psel0; | |
1223 | wire psel1; | |
1224 | ||
1225 | input [39:0] din0; | |
1226 | input [39:0] din1; | |
1227 | input sel0; | |
1228 | output [39:0] dout; | |
1229 | ||
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | cl_dp1_penc2_8x c0_0 ( | |
1235 | .sel0(sel0), | |
1236 | .psel0(psel0), | |
1237 | .psel1(psel1) | |
1238 | ); | |
1239 | ||
1240 | mux2s #(40) d0_0 ( | |
1241 | .sel0(psel0), | |
1242 | .sel1(psel1), | |
1243 | .in0(din0[39:0]), | |
1244 | .in1(din1[39:0]), | |
1245 | .dout(dout[39:0]) | |
1246 | ); | |
1247 | ||
1248 | ||
1249 | ||
1250 | ||
1251 | ||
1252 | ||
1253 | ||
1254 | ||
1255 | ||
1256 | ||
1257 | ||
1258 | ||
1259 | ||
1260 | endmodule | |
1261 | ||
1262 | ||
1263 | // | |
1264 | // and macro for ports = 2,3,4 | |
1265 | // | |
1266 | // | |
1267 | ||
1268 | ||
1269 | ||
1270 | ||
1271 | ||
1272 | module ifu_cmu_msb_dp_and_macro__ports_2__stack_60c__width_5 ( | |
1273 | din0, | |
1274 | din1, | |
1275 | dout); | |
1276 | input [4:0] din0; | |
1277 | input [4:0] din1; | |
1278 | output [4:0] dout; | |
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | ||
1285 | and2 #(5) d0_0 ( | |
1286 | .in0(din0[4:0]), | |
1287 | .in1(din1[4:0]), | |
1288 | .out(dout[4:0]) | |
1289 | ); | |
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | ||
1299 | endmodule | |
1300 | ||
1301 | ||
1302 | ||
1303 | ||
1304 | ||
1305 | // | |
1306 | // buff macro | |
1307 | // | |
1308 | // | |
1309 | ||
1310 | ||
1311 | ||
1312 | ||
1313 | ||
1314 | module ifu_cmu_msb_dp_buff_macro__minbuff_1__stack_60c__width_34 ( | |
1315 | din, | |
1316 | dout); | |
1317 | input [33:0] din; | |
1318 | output [33:0] dout; | |
1319 | ||
1320 | ||
1321 | ||
1322 | ||
1323 | ||
1324 | ||
1325 | buff #(34) d0_0 ( | |
1326 | .in(din[33:0]), | |
1327 | .out(dout[33:0]) | |
1328 | ); | |
1329 | ||
1330 | ||
1331 | ||
1332 | ||
1333 | ||
1334 | ||
1335 | ||
1336 | ||
1337 | endmodule | |
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | // any PARAMS parms go into naming of macro | |
1348 | ||
1349 | module ifu_cmu_msb_dp_msff_macro__stack_60c__width_40 ( | |
1350 | din, | |
1351 | clk, | |
1352 | en, | |
1353 | se, | |
1354 | scan_in, | |
1355 | siclk, | |
1356 | soclk, | |
1357 | pce_ov, | |
1358 | stop, | |
1359 | dout, | |
1360 | scan_out); | |
1361 | wire l1clk; | |
1362 | wire siclk_out; | |
1363 | wire soclk_out; | |
1364 | wire [38:0] so; | |
1365 | ||
1366 | input [39:0] din; | |
1367 | ||
1368 | ||
1369 | input clk; | |
1370 | input en; | |
1371 | input se; | |
1372 | input scan_in; | |
1373 | input siclk; | |
1374 | input soclk; | |
1375 | input pce_ov; | |
1376 | input stop; | |
1377 | ||
1378 | ||
1379 | ||
1380 | output [39:0] dout; | |
1381 | ||
1382 | ||
1383 | output scan_out; | |
1384 | ||
1385 | ||
1386 | ||
1387 | ||
1388 | cl_dp1_l1hdr_8x c0_0 ( | |
1389 | .l2clk(clk), | |
1390 | .pce(en), | |
1391 | .aclk(siclk), | |
1392 | .bclk(soclk), | |
1393 | .l1clk(l1clk), | |
1394 | .se(se), | |
1395 | .pce_ov(pce_ov), | |
1396 | .stop(stop), | |
1397 | .siclk_out(siclk_out), | |
1398 | .soclk_out(soclk_out) | |
1399 | ); | |
1400 | dff #(40) d0_0 ( | |
1401 | .l1clk(l1clk), | |
1402 | .siclk(siclk_out), | |
1403 | .soclk(soclk_out), | |
1404 | .d(din[39:0]), | |
1405 | .si({scan_in,so[38:0]}), | |
1406 | .so({so[38:0],scan_out}), | |
1407 | .q(dout[39:0]) | |
1408 | ); | |
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | ||
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | ||
1429 | endmodule | |
1430 | ||
1431 | ||
1432 | ||
1433 | ||
1434 | ||
1435 | ||
1436 | ||
1437 | ||
1438 | ||
1439 | // | |
1440 | // buff macro | |
1441 | // | |
1442 | // | |
1443 | ||
1444 | ||
1445 | ||
1446 | ||
1447 | ||
1448 | module ifu_cmu_msb_dp_buff_macro__stack_60c__width_46 ( | |
1449 | din, | |
1450 | dout); | |
1451 | input [45:0] din; | |
1452 | output [45:0] dout; | |
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | ||
1459 | buff #(46) d0_0 ( | |
1460 | .in(din[45:0]), | |
1461 | .out(dout[45:0]) | |
1462 | ); | |
1463 | ||
1464 | ||
1465 | ||
1466 | ||
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | endmodule | |
1472 | ||
1473 | ||
1474 | ||
1475 |