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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ifu_ftu_asi_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define BUS_CTL 64 | |
36 | `define BUS_VLD 63 | |
37 | `define BUS_ACK 62 | |
38 | `define BUS_RD 59 | |
39 | `define BUS_TID_END 58 | |
40 | `define BUS_TID_ST 56 | |
41 | ||
42 | `define IC_ASI 8'h66 | |
43 | `define TG_ASI 8'h67 | |
44 | `define ITD_ASI 8'h55 | |
45 | `define ITT_ASI 8'h56 | |
46 | `define ITH_ASI 8'h53 | |
47 | `define ASI 2'b00 | |
48 | `define IT_VA 48'h000000000FF8 | |
49 | ||
50 | module ifu_ftu_asi_ctl ( | |
51 | tcu_scan_en, | |
52 | l2clk, | |
53 | tcu_pce_ov, | |
54 | spc_aclk, | |
55 | spc_bclk, | |
56 | scan_in, | |
57 | rng_in_cdbus, | |
58 | ic_rd_data, | |
59 | tg_rd_data, | |
60 | it_rd_data, | |
61 | agc_vl_data_c, | |
62 | ftp_asi_ic_rd_done, | |
63 | ftp_asi_ic_wr_done, | |
64 | ftp_asi_tg_rd_done, | |
65 | ftp_asi_tg_wr_done, | |
66 | ftp_asi_it_rd_done, | |
67 | asi_wr_data, | |
68 | asi_ic_rd_req, | |
69 | asi_ic_wr_req, | |
70 | asi_tg_rd_req, | |
71 | asi_tg_wr_req, | |
72 | asi_itd_rd_req, | |
73 | asi_itt_rd_req, | |
74 | asi_ith_det_req, | |
75 | asi_wr_request, | |
76 | asi_rd_request, | |
77 | scan_out, | |
78 | asi_addr_bf, | |
79 | asi_way_bf, | |
80 | asi_tid, | |
81 | ifu_rngl_cdbus); | |
82 | wire pce_ov; | |
83 | wire stop; | |
84 | wire siclk; | |
85 | wire soclk; | |
86 | wire asi_rd_data_rdy; | |
87 | wire asi_it_rd_done_p; | |
88 | wire [63:0] asi_data_out; | |
89 | wire asi_wr_done_in; | |
90 | wire l1clk; | |
91 | wire asi_it_rd_done_reg_scanin; | |
92 | wire asi_it_rd_done_reg_scanout; | |
93 | wire rng_stg1_data_scanin; | |
94 | wire rng_stg1_data_scanout; | |
95 | wire [63:0] data_1f; | |
96 | wire ic_data_parity; | |
97 | wire ic_par_err_inj; | |
98 | wire tg_data_parity; | |
99 | wire tg_par_err_inj; | |
100 | wire [63:0] data_2f; | |
101 | wire [1:0] vl_bits; | |
102 | wire [32:0] asi_wr_data_mux; | |
103 | wire asi_ic_wr_req_2f; | |
104 | wire [32:0] asi_wr_data_in; | |
105 | wire asi_wr_request_2f; | |
106 | wire [32:0] asi_wr_data_hold; | |
107 | wire wr_data_hold_scanin; | |
108 | wire wr_data_hold_scanout; | |
109 | wire rng_stg1_ctl_scanin; | |
110 | wire rng_stg1_ctl_scanout; | |
111 | wire ctl_1f; | |
112 | wire asi_ic_wr_req_in; | |
113 | wire asi_tg_wr_req_in; | |
114 | wire wr_req_ff_scanin; | |
115 | wire wr_req_ff_scanout; | |
116 | wire hole_det_1; | |
117 | wire indet_acc_1; | |
118 | wire rng_stg2_data_scanin; | |
119 | wire rng_stg2_data_scanout; | |
120 | wire rng_stg2_ctl_scanin; | |
121 | wire rng_stg2_ctl_scanout; | |
122 | wire ctl_2f; | |
123 | wire rng_stg2_decctl_scanin; | |
124 | wire rng_stg2_decctl_scanout; | |
125 | wire hole_det_2f; | |
126 | wire indet_acc_2f; | |
127 | wire next_indet_return_rd_first; | |
128 | wire indet_rd_rdy_f; | |
129 | wire indet_return_rd_first; | |
130 | wire indet_rd_done_2; | |
131 | wire indet_wr_rdy_f; | |
132 | wire indet_wr_done_2; | |
133 | wire rng_stg3_decctl_scanin; | |
134 | wire rng_stg3_decctl_scanout; | |
135 | wire indet_rd_done_3f; | |
136 | wire bypass_data_3; | |
137 | wire [63:0] data_2; | |
138 | wire [63:0] indet_data_f; | |
139 | wire valid_2; | |
140 | wire [2:0] tid_2; | |
141 | wire [2:0] indet_wr_tid_f; | |
142 | wire [2:0] indet_rd_tid_f; | |
143 | wire rdwr_2; | |
144 | wire ack_2; | |
145 | wire [7:0] asi_err_2; | |
146 | wire [63:0] ctl_2; | |
147 | wire [63:0] rng_data_out_mux; | |
148 | wire rng_stg3_scanin; | |
149 | wire rng_stg3_scanout; | |
150 | wire rng_stg3_ctl_scanin; | |
151 | wire rng_stg3_ctl_scanout; | |
152 | wire indet_rd_data_scanin; | |
153 | wire indet_rd_data_scanout; | |
154 | wire [2:0] next_indet_wr_tid; | |
155 | wire pr_tid_wr_ret_scanin; | |
156 | wire pr_tid_wr_ret_scanout; | |
157 | wire [2:0] next_indet_rd_tid; | |
158 | wire pr_tid_rd_ret_scanin; | |
159 | wire pr_tid_rd_ret_scanout; | |
160 | wire [39:3] next_rd_addr_bf; | |
161 | wire [39:3] asi_rd_addr_bf; | |
162 | wire address_rd_reg_scanin; | |
163 | wire address_rd_reg_scanout; | |
164 | wire [39:3] next_wr_addr_bf; | |
165 | wire [39:3] asi_wr_addr_bf; | |
166 | wire address_wr_reg_scanin; | |
167 | wire address_wr_reg_scanout; | |
168 | wire [2:0] next_rd_way_bf; | |
169 | wire [2:0] asi_rd_way_bf; | |
170 | wire rd_way_bf_reg_scanin; | |
171 | wire rd_way_bf_reg_scanout; | |
172 | wire [2:0] next_wr_way_bf; | |
173 | wire [2:0] asi_wr_way_bf; | |
174 | wire wr_way_bf_reg_scanin; | |
175 | wire wr_way_bf_reg_scanout; | |
176 | wire next_rd_is_first; | |
177 | wire true_old_wr_req_pending; | |
178 | wire rd_request_pending; | |
179 | wire asi_rd_is_first; | |
180 | wire rd_is_first_reg_scanin; | |
181 | wire rd_is_first_reg_scanout; | |
182 | wire wr_request_pending; | |
183 | wire next_wr_request_pending; | |
184 | wire next_rd_request_pending; | |
185 | wire wr_request_pending_reg_scanin; | |
186 | wire wr_request_pending_reg_scanout; | |
187 | wire [39:3] next_asi_addr_bf; | |
188 | wire address_reg_bf_scanin; | |
189 | wire address_reg_bf_scanout; | |
190 | wire [2:0] indet_tid_f; | |
191 | wire [2:0] indet_tid_unused; | |
192 | wire indet_rd_rdy_c; | |
193 | wire indet_wr_rdy_c; | |
194 | wire indet_comp_state_scanin; | |
195 | wire indet_comp_state_scanout; | |
196 | wire se; | |
197 | wire spares_scanin; | |
198 | wire spares_scanout; | |
199 | ||
200 | ||
201 | // globals | |
202 | input tcu_scan_en ; | |
203 | input l2clk ; | |
204 | input tcu_pce_ov; | |
205 | input spc_aclk; | |
206 | input spc_bclk; | |
207 | ||
208 | ||
209 | ||
210 | input scan_in; | |
211 | ||
212 | ||
213 | input [64:0] rng_in_cdbus; // 65 bit control/data bus to the ring from lsu | |
214 | input [32:0] ic_rd_data ; | |
215 | input [29:0] tg_rd_data ; | |
216 | input [63:0] it_rd_data ; | |
217 | input [1:0] agc_vl_data_c ; | |
218 | ||
219 | ||
220 | input ftp_asi_ic_rd_done; // indicates indeterminate ld data from ic is valid | |
221 | input ftp_asi_ic_wr_done; // indicates indeterminate store to IC is done. | |
222 | input ftp_asi_tg_rd_done; // indicates indeterminate ld data from tag is valid | |
223 | input ftp_asi_tg_wr_done; // indicates indeterminate store to tag is done. | |
224 | input ftp_asi_it_rd_done; // indicates indeterminate ld data from itlb is valid | |
225 | ||
226 | ||
227 | ||
228 | output [32:0] asi_wr_data; // Indeterminate store data to Cache or tag and Valid bits. | |
229 | output asi_ic_rd_req; // send indeterminate load request to Icache data, sent in stage 1 | |
230 | output asi_ic_wr_req; // send indeterminate store request to Icache data, sent in stage 1 | |
231 | output asi_tg_rd_req; // send indeterminate load request to Icache Tag, sent in stage 1 | |
232 | output asi_tg_wr_req; // send indeterminate store request to Icache Tag, sent in stage 1 | |
233 | output asi_itd_rd_req; // send indeterminate load request to ITLB data , sent in stage 1 | |
234 | output asi_itt_rd_req; // send indeterminate load request to ITLB tag , sent in stage 1 | |
235 | output asi_ith_det_req; // send indeterminate load request to ITLB to get translation , sent in stage 1 | |
236 | output asi_wr_request; // indeterminate sent in stage 1 | |
237 | output asi_rd_request; // indeterminate sent in stage 1 | |
238 | output scan_out ; | |
239 | output [39:3] asi_addr_bf ; // Read/write address | |
240 | output [2:0] asi_way_bf ; // Read/write way | |
241 | output [2:0] asi_tid ; // Thread id | |
242 | ||
243 | ||
244 | output [64:0] ifu_rngl_cdbus; // 65 bit control/data bus output from the ring | |
245 | // 64 - ctl/data | |
246 | // 63 - valid/hole | |
247 | // 62 - ack | |
248 | // 61:60 - 00-ASI, 01-ASR, 10-PR, 11-HPR | |
249 | // 59 - rd/wrx | |
250 | // 58:56 - Thread ID | |
251 | // 55:48 - ASI field | |
252 | // 47:0 - Virtual Address | |
253 | ||
254 | ||
255 | assign pce_ov = tcu_pce_ov; | |
256 | assign stop = 1'b0; | |
257 | assign siclk = spc_aclk; | |
258 | assign soclk = spc_bclk; | |
259 | ||
260 | ||
261 | ||
262 | assign asi_rd_data_rdy = ftp_asi_ic_rd_done | ftp_asi_tg_rd_done | asi_it_rd_done_p; | |
263 | assign asi_data_out[63:0] = ({64{ftp_asi_ic_rd_done}} & {31'b0, ic_rd_data[32:0]}) | | |
264 | ({64{ftp_asi_tg_rd_done}} & {32'b0, tg_rd_data[29:0],agc_vl_data_c[1:0]}) | | |
265 | ({64{asi_it_rd_done_p}} & it_rd_data[63:0]) ; | |
266 | ||
267 | assign asi_wr_done_in = ftp_asi_ic_wr_done | ftp_asi_tg_wr_done; | |
268 | ||
269 | ||
270 | ||
271 | ||
272 | //////////////////////////////////////////////////////// | |
273 | ifu_ftu_asi_ctl_l1clkhdr_ctl_macro clkgen | |
274 | ( | |
275 | .l2clk(l2clk), | |
276 | .l1en (1'b1 ), | |
277 | .l1clk(l1clk), | |
278 | .pce_ov(pce_ov), | |
279 | .stop(stop), | |
280 | .se(se)); | |
281 | //////////////////////////////////////////////////////// | |
282 | ||
283 | ifu_ftu_asi_ctl_msff_ctl_macro__width_1 asi_it_rd_done_reg ( | |
284 | .scan_in(asi_it_rd_done_reg_scanin), | |
285 | .scan_out(asi_it_rd_done_reg_scanout), | |
286 | .l1clk (l1clk), | |
287 | .din (ftp_asi_it_rd_done), | |
288 | .dout (asi_it_rd_done_p), | |
289 | .siclk(siclk), | |
290 | .soclk(soclk) | |
291 | ); | |
292 | ||
293 | ||
294 | ///////////////////////////////////////////////////////////////////// | |
295 | //STAGE 1 | |
296 | ///////////////////////////////////////////////////////////////////// | |
297 | // Stage the packet coming on the ring | |
298 | // First cycle of the packet holds control and address information | |
299 | // Second cycle holds the store/load data | |
300 | ||
301 | ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg1_data ( | |
302 | .scan_in(rng_stg1_data_scanin), | |
303 | .scan_out(rng_stg1_data_scanout), | |
304 | .l1clk (l1clk), | |
305 | .din( rng_in_cdbus[63:0]), | |
306 | .dout( data_1f[63:0]), | |
307 | .siclk(siclk), | |
308 | .soclk(soclk)); | |
309 | ||
310 | assign ic_data_parity = ^data_1f[31:0] ; | |
311 | assign ic_par_err_inj = ic_data_parity ^ data_1f[32] ; | |
312 | ||
313 | assign tg_data_parity = ^data_1f[30:2] ; | |
314 | assign tg_par_err_inj = tg_data_parity ^ data_2f[16] ; | |
315 | ||
316 | assign vl_bits[1] = data_1f[1] ; | |
317 | assign vl_bits[0] = data_1f[1] ^ data_2f[15] ; | |
318 | ||
319 | assign asi_wr_data_mux[32:0] = asi_ic_wr_req_2f ? {ic_par_err_inj,data_1f[31:0]} : {1'b0,vl_bits[1:0],tg_par_err_inj,data_1f[30:2]} ; | |
320 | assign asi_wr_data_in[32:0] = asi_wr_request_2f ? asi_wr_data_mux[32:0] : asi_wr_data_hold[32:0] ; | |
321 | ||
322 | ifu_ftu_asi_ctl_msff_ctl_macro__width_33 wr_data_hold ( | |
323 | .scan_in(wr_data_hold_scanin), | |
324 | .scan_out(wr_data_hold_scanout), | |
325 | .l1clk (l1clk), | |
326 | .din( asi_wr_data_in[32:0]), | |
327 | .dout( asi_wr_data_hold[32:0]), | |
328 | .siclk(siclk), | |
329 | .soclk(soclk)); | |
330 | ||
331 | assign asi_wr_data[32:0] = asi_wr_data_hold[32:0] ; | |
332 | ||
333 | // register control bit, bit 64 indicates whether ctl packet or data packet | |
334 | ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rng_stg1_ctl ( | |
335 | .scan_in(rng_stg1_ctl_scanin), | |
336 | .scan_out(rng_stg1_ctl_scanout), | |
337 | .l1clk (l1clk), | |
338 | .din (rng_in_cdbus[`BUS_CTL]), | |
339 | .dout (ctl_1f), | |
340 | .siclk(siclk), | |
341 | .soclk(soclk) | |
342 | ); | |
343 | ||
344 | // decode the packet, ack bit must not be set | |
345 | ||
346 | ||
347 | assign asi_ic_rd_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
348 | (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`IC_ASI) ; // & (data_1f[47:0] == `PR_VA); | |
349 | assign asi_ic_wr_req_in = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
350 | (data_1f[61:60] == `ASI) & ~data_1f[`BUS_RD] & (data_1f[55:48]==`IC_ASI);// & (data_1f[47:0] == `PR_VA); | |
351 | ||
352 | assign asi_tg_rd_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
353 | (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`TG_ASI) ; // & (data_1f[47:0] == `PR_VA); | |
354 | ||
355 | assign asi_tg_wr_req_in = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
356 | (data_1f[61:60] == `ASI) & ~data_1f[`BUS_RD] & (data_1f[55:48]==`TG_ASI);// & (data_1f[47:0] == `PR_VA); | |
357 | ||
358 | ifu_ftu_asi_ctl_msff_ctl_macro__width_2 wr_req_ff ( | |
359 | .scan_in(wr_req_ff_scanin), | |
360 | .scan_out(wr_req_ff_scanout), | |
361 | .l1clk (l1clk), | |
362 | .din ({asi_ic_wr_req_in, asi_tg_wr_req_in}), | |
363 | .dout ({asi_ic_wr_req, asi_tg_wr_req}), | |
364 | .siclk(siclk), | |
365 | .soclk(soclk) | |
366 | ); | |
367 | ||
368 | assign asi_itd_rd_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
369 | (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`ITD_ASI) ; // & (data_1f[47:0] == `IT_VA); | |
370 | ||
371 | assign asi_itt_rd_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
372 | (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`ITT_ASI) ; | |
373 | ||
374 | assign asi_ith_det_req = ctl_1f & ~data_1f[`BUS_ACK] & data_1f[`BUS_VLD] & | |
375 | (data_1f[61:60] == `ASI) & data_1f[`BUS_RD] & (data_1f[55:48]==`ITH_ASI);// & (data_1f[47:0] == `PR_VA); | |
376 | ||
377 | ||
378 | ||
379 | // assign pr_rd_1 = 1'b0 ; | |
380 | // assign pr_wr_1 = 1'b0 ; | |
381 | ||
382 | //detect a hole, this is used by indeterminate accesses. | |
383 | assign hole_det_1 = ctl_1f & ~data_1f[`BUS_VLD]; | |
384 | ||
385 | // indeterminate accesses will clear the valid bit on the packet | |
386 | // In this example stub, PR addresses are indeterminate. | |
387 | assign indet_acc_1 = asi_ic_rd_req | asi_ic_wr_req_in | asi_tg_rd_req | asi_tg_wr_req_in | asi_itd_rd_req | asi_itt_rd_req | asi_ith_det_req; | |
388 | ||
389 | // decode determinate accesses | |
390 | ||
391 | ||
392 | // Send load request and thread information from stage 1. | |
393 | // In this example stub, data will be returned 2 cycles later, | |
394 | // when ctl is in stage 3 and data is in stage 2. | |
395 | ||
396 | ///////////////////////////////////////////////////////////////////// | |
397 | //STAGE 2 | |
398 | ///////////////////////////////////////////////////////////////////// | |
399 | // pipe the packets and decoded control information | |
400 | ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg2_data ( | |
401 | .scan_in(rng_stg2_data_scanin), | |
402 | .scan_out(rng_stg2_data_scanout), | |
403 | .l1clk (l1clk), | |
404 | .din( data_1f[63:0]), | |
405 | .dout( data_2f[63:0]), | |
406 | .siclk(siclk), | |
407 | .soclk(soclk)); | |
408 | ||
409 | // register control bit | |
410 | ifu_ftu_asi_ctl_msff_ctl_macro__width_3 rng_stg2_ctl ( | |
411 | .scan_in(rng_stg2_ctl_scanin), | |
412 | .scan_out(rng_stg2_ctl_scanout), | |
413 | .l1clk (l1clk), | |
414 | .din ({ctl_1f,asi_ic_wr_req_in, asi_wr_request}), | |
415 | .dout ({ctl_2f,asi_ic_wr_req_2f, asi_wr_request_2f}), | |
416 | .siclk(siclk), | |
417 | .soclk(soclk)); | |
418 | ||
419 | ifu_ftu_asi_ctl_msff_ctl_macro__width_2 rng_stg2_decctl ( | |
420 | .scan_in(rng_stg2_decctl_scanin), | |
421 | .scan_out(rng_stg2_decctl_scanout), | |
422 | .l1clk (l1clk), | |
423 | .din ({hole_det_1, indet_acc_1}), | |
424 | .dout ({hole_det_2f, indet_acc_2f}), | |
425 | .siclk(siclk), | |
426 | .soclk(soclk) | |
427 | ); | |
428 | ||
429 | // send the store data out to the unit. Store data is in stage1 when control is in stage 2 | |
430 | // The data is accompanied by write control signal. | |
431 | ||
432 | ||
433 | // also send the Thread ID with store data. It is in stage 2 (control packet). | |
434 | // assign rng_wr_tid[2:0] = data_2f[`BUS_TID_END:`BUS_TID_ST]; | |
435 | ||
436 | assign next_indet_return_rd_first = (hole_det_2f & (indet_rd_rdy_f | indet_rd_rdy_f)) & ~indet_return_rd_first ; | |
437 | // If a hole is detected, and an indeterminate access is waiting to be sent, then insert it. | |
438 | assign indet_rd_done_2 = hole_det_2f & indet_rd_rdy_f & (~indet_wr_rdy_f | indet_return_rd_first) ; | |
439 | assign indet_wr_done_2 = hole_det_2f & indet_wr_rdy_f & (~indet_rd_rdy_f | ~indet_return_rd_first); | |
440 | ||
441 | // pipe the control bits 1 more cycle to line it up with data | |
442 | ifu_ftu_asi_ctl_msff_ctl_macro__width_2 rng_stg3_decctl ( | |
443 | .scan_in(rng_stg3_decctl_scanin), | |
444 | .scan_out(rng_stg3_decctl_scanout), | |
445 | .l1clk (l1clk), | |
446 | .din ({indet_rd_done_2,next_indet_return_rd_first}), | |
447 | .dout ({indet_rd_done_3f,indet_return_rd_first}), | |
448 | .siclk(siclk), | |
449 | .soclk(soclk) | |
450 | ); | |
451 | ||
452 | // bypass incoming data if the packet is not a read request to the unit. | |
453 | assign bypass_data_3 = ~indet_rd_done_3f; | |
454 | ||
455 | // Mux the output data | |
456 | // mux_macro mux_data_stg2 (width=64,ports=2,mux=aonpe) | |
457 | // ( | |
458 | // .din0(data_2f[63:0]), | |
459 | // .din1(indet_data_f[63:0]), | |
460 | // .sel0(bypass_data_3), | |
461 | // .sel1(indet_rd_done_3f), | |
462 | // .dout(data_2[63:0])); | |
463 | ||
464 | assign data_2[63:0] = bypass_data_3 ? data_2f[63:0] : indet_data_f[63:0] ; | |
465 | ||
466 | // valid bit is cleared if current packet is indeterminate rd/wr | |
467 | // valid bit is set if indeterminate data is being returned on current packet, indicated by indet_done | |
468 | // indet_done and indet_acc are mutually exclusive by design. | |
469 | assign valid_2 = (indet_wr_done_2 | indet_rd_done_2 | data_2f[`BUS_VLD]) & !indet_acc_2f; | |
470 | // assign tid_2[2:0] = (indet_wr_done_2 | indet_rd_done_2)? indet_tid_f[2:0]: data_2f[`BUS_TID_END:`BUS_TID_ST]; | |
471 | ||
472 | assign tid_2[2:0] = (({3{( indet_wr_done_2 & ~indet_rd_done_2)}}) & indet_wr_tid_f[2:0]) | | |
473 | (({3{(~indet_wr_done_2 & indet_rd_done_2)}}) & indet_rd_tid_f[2:0]) | | |
474 | (({3{(~indet_wr_done_2 & ~indet_rd_done_2)}}) & data_2f[`BUS_TID_END:`BUS_TID_ST]); | |
475 | ||
476 | assign rdwr_2 = (indet_rd_done_2 & !indet_wr_done_2) | (!indet_rd_done_2 & !indet_wr_done_2 & data_2f[`BUS_RD]); | |
477 | ||
478 | // ack bit is set if current packet was a determinate rd/wr destined for the unit. | |
479 | // ack bit is also set if indeterminate data is being returned on current packet. | |
480 | // ack bit is cleared if current packet is indeterminate rd/wr destined for the unit | |
481 | // Else, ack bit is passed unchanged | |
482 | ||
483 | assign ack_2 = (indet_wr_done_2 | indet_rd_done_2 | data_2f[`BUS_ACK]) & !indet_acc_2f; | |
484 | ||
485 | // report exceptions | |
486 | assign asi_err_2[7:0] = (ack_2 & ~data_2f[`BUS_ACK]) ? 8'b0 : data_2f[55:48]; | |
487 | ||
488 | assign ctl_2[63:0] = {valid_2, ack_2, data_2f[61:60], rdwr_2, tid_2[2:0], asi_err_2[7:0], data_2f[47:0]}; | |
489 | ||
490 | ///////////////////////////////////////////////////////////////////// | |
491 | //STAGE 3 | |
492 | ///////////////////////////////////////////////////////////////////// | |
493 | // This is the output register | |
494 | // Mux ctl and data | |
495 | // | |
496 | ||
497 | assign rng_data_out_mux[63:0] = ctl_2f ? ctl_2[63:0] : data_2[63:0] ; | |
498 | ||
499 | ifu_ftu_asi_ctl_msff_ctl_macro__width_64 rng_stg3 ( | |
500 | .scan_in(rng_stg3_scanin), | |
501 | .scan_out(rng_stg3_scanout), | |
502 | .l1clk (l1clk), | |
503 | .din (rng_data_out_mux[63:0]), | |
504 | .dout (ifu_rngl_cdbus[63:0]), | |
505 | .siclk(siclk), | |
506 | .soclk(soclk) | |
507 | ); | |
508 | ||
509 | ||
510 | ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rng_stg3_ctl ( | |
511 | .scan_in(rng_stg3_ctl_scanin), | |
512 | .scan_out(rng_stg3_ctl_scanout), | |
513 | .l1clk (l1clk), | |
514 | .din (ctl_2f), | |
515 | .dout (ifu_rngl_cdbus[`BUS_CTL]), | |
516 | .siclk(siclk), | |
517 | .soclk(soclk) | |
518 | ); | |
519 | ||
520 | ||
521 | ||
522 | // latch the indeterminate load data and set up state to hold it until | |
523 | // a hole is detected and data is returned. Same applies to indeterminate | |
524 | // store, except there is no data to return. Only a valid packet is returned | |
525 | // with the right tid and rd/wr bit. | |
526 | ||
527 | ||
528 | ifu_ftu_asi_ctl_msff_ctl_macro__en_1__width_64 indet_rd_data ( | |
529 | .scan_in(indet_rd_data_scanin), | |
530 | .scan_out(indet_rd_data_scanout), | |
531 | .l1clk (l1clk), | |
532 | .en ( asi_rd_data_rdy), | |
533 | .din( asi_data_out[63:0]), | |
534 | .dout( indet_data_f[63:0]), | |
535 | .siclk(siclk), | |
536 | .soclk(soclk)); | |
537 | ||
538 | assign next_indet_wr_tid[2:0] = asi_wr_request ? data_1f[`BUS_TID_END:`BUS_TID_ST] : indet_wr_tid_f; | |
539 | ||
540 | ifu_ftu_asi_ctl_msff_ctl_macro__width_3 pr_tid_wr_ret ( | |
541 | .scan_in(pr_tid_wr_ret_scanin), | |
542 | .scan_out(pr_tid_wr_ret_scanout), | |
543 | .l1clk (l1clk), | |
544 | .din (next_indet_wr_tid[2:0]), | |
545 | .dout (indet_wr_tid_f[2:0]), | |
546 | .siclk(siclk), | |
547 | .soclk(soclk) | |
548 | ); | |
549 | ||
550 | assign next_indet_rd_tid[2:0] = asi_rd_request ? data_1f[`BUS_TID_END:`BUS_TID_ST] : indet_rd_tid_f; | |
551 | ||
552 | ifu_ftu_asi_ctl_msff_ctl_macro__width_3 pr_tid_rd_ret ( | |
553 | .scan_in(pr_tid_rd_ret_scanin), | |
554 | .scan_out(pr_tid_rd_ret_scanout), | |
555 | .l1clk (l1clk), | |
556 | .din (next_indet_rd_tid[2:0]), | |
557 | .dout (indet_rd_tid_f[2:0]), | |
558 | .siclk(siclk), | |
559 | .soclk(soclk) | |
560 | ); | |
561 | ||
562 | assign next_rd_addr_bf[39:3] = asi_rd_request ? data_1f[39:3] : asi_rd_addr_bf[39:3]; | |
563 | ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_rd_reg ( | |
564 | .scan_in(address_rd_reg_scanin), | |
565 | .scan_out(address_rd_reg_scanout), | |
566 | .l1clk (l1clk), | |
567 | .din (next_rd_addr_bf[39:3]), | |
568 | .dout (asi_rd_addr_bf[39:3]), | |
569 | .siclk(siclk), | |
570 | .soclk(soclk) | |
571 | ); | |
572 | ||
573 | assign next_wr_addr_bf[39:3] = asi_wr_request ? data_1f[39:3] : asi_wr_addr_bf[39:3]; | |
574 | ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_wr_reg ( | |
575 | .scan_in(address_wr_reg_scanin), | |
576 | .scan_out(address_wr_reg_scanout), | |
577 | .l1clk (l1clk), | |
578 | .din (next_wr_addr_bf[39:3]), | |
579 | .dout (asi_wr_addr_bf[39:3]), | |
580 | .siclk(siclk), | |
581 | .soclk(soclk) | |
582 | ); | |
583 | ||
584 | ||
585 | assign next_rd_way_bf[2:0] = asi_rd_request ? data_1f[14:12] : asi_rd_way_bf[2:0]; | |
586 | ifu_ftu_asi_ctl_msff_ctl_macro__width_3 rd_way_bf_reg ( | |
587 | .scan_in(rd_way_bf_reg_scanin), | |
588 | .scan_out(rd_way_bf_reg_scanout), | |
589 | .l1clk (l1clk), | |
590 | .din (next_rd_way_bf[2:0]), | |
591 | .dout (asi_rd_way_bf[2:0]), | |
592 | .siclk(siclk), | |
593 | .soclk(soclk) | |
594 | ); | |
595 | ||
596 | assign next_wr_way_bf[2:0] = asi_wr_request ? data_1f[14:12] : asi_wr_way_bf[2:0]; | |
597 | ifu_ftu_asi_ctl_msff_ctl_macro__width_3 wr_way_bf_reg ( | |
598 | .scan_in(wr_way_bf_reg_scanin), | |
599 | .scan_out(wr_way_bf_reg_scanout), | |
600 | .l1clk (l1clk), | |
601 | .din (next_wr_way_bf[2:0]), | |
602 | .dout (asi_wr_way_bf[2:0]), | |
603 | .siclk(siclk), | |
604 | .soclk(soclk) | |
605 | ); | |
606 | ||
607 | assign next_rd_is_first = (asi_rd_request & ~true_old_wr_req_pending) | | |
608 | (rd_request_pending & ~true_old_wr_req_pending & ~asi_rd_data_rdy) | | |
609 | (asi_rd_is_first & ~asi_rd_data_rdy); | |
610 | ||
611 | ifu_ftu_asi_ctl_msff_ctl_macro__width_1 rd_is_first_reg ( | |
612 | .scan_in(rd_is_first_reg_scanin), | |
613 | .scan_out(rd_is_first_reg_scanout), | |
614 | .l1clk (l1clk), | |
615 | .din (next_rd_is_first), | |
616 | .dout (asi_rd_is_first), | |
617 | .siclk(siclk), | |
618 | .soclk(soclk) | |
619 | ); | |
620 | ||
621 | ||
622 | assign true_old_wr_req_pending = (wr_request_pending & ~asi_wr_done_in) ; | |
623 | assign next_wr_request_pending = asi_wr_request | (wr_request_pending & ~asi_wr_done_in); | |
624 | assign next_rd_request_pending = asi_rd_request | (rd_request_pending & ~asi_rd_data_rdy); | |
625 | ||
626 | ifu_ftu_asi_ctl_msff_ctl_macro__width_2 wr_request_pending_reg ( | |
627 | .scan_in(wr_request_pending_reg_scanin), | |
628 | .scan_out(wr_request_pending_reg_scanout), | |
629 | .l1clk (l1clk), | |
630 | .din ({next_wr_request_pending, next_rd_request_pending}), | |
631 | .dout ({wr_request_pending,rd_request_pending}), | |
632 | .siclk(siclk), | |
633 | .soclk(soclk) | |
634 | ); | |
635 | ||
636 | ||
637 | assign next_asi_addr_bf[39:3] = next_rd_is_first ? next_rd_addr_bf[39:3] : next_wr_addr_bf[39:3] ; | |
638 | ||
639 | ifu_ftu_asi_ctl_msff_ctl_macro__width_37 address_reg_bf ( | |
640 | .scan_in(address_reg_bf_scanin), | |
641 | .scan_out(address_reg_bf_scanout), | |
642 | .l1clk (l1clk), | |
643 | .din (next_asi_addr_bf[39:3]), | |
644 | .dout (asi_addr_bf[39:3]), | |
645 | .siclk(siclk), | |
646 | .soclk(soclk) | |
647 | ); | |
648 | ||
649 | ||
650 | assign asi_way_bf[2:0] = asi_rd_is_first ? asi_rd_way_bf[2:0] : asi_wr_way_bf[2:0] ; | |
651 | assign indet_tid_f[2:0] = asi_rd_is_first ? indet_rd_tid_f[2:0] : indet_wr_tid_f[2:0] ; | |
652 | assign indet_tid_unused[2:0] = indet_tid_f[2:0] ; | |
653 | ||
654 | // assign next_tid_bf[2:0] = asi_request ? data_1f[14:12] : asi_tid[2:0]; | |
655 | // msff_ctl_macro tid_bf_reg (width=3) ( | |
656 | // .scan_in(tid_bf_reg_scanin), | |
657 | // .scan_out(tid_bf_reg_scanout), | |
658 | // .l1clk (l1clk), | |
659 | // .din (next_tid_bf[2:0]), | |
660 | // .dout (asi_tid[2:0]) | |
661 | // ); | |
662 | ||
663 | assign asi_tid[2:0] = data_1f[58:56] ; | |
664 | ||
665 | // set up state to inidicate completed indeterminate operation | |
666 | assign indet_rd_rdy_c = (asi_rd_data_rdy | indet_rd_rdy_f) & !indet_rd_done_2; | |
667 | assign indet_wr_rdy_c = (asi_wr_done_in | indet_wr_rdy_f) & !indet_wr_done_2; | |
668 | ||
669 | ifu_ftu_asi_ctl_msff_ctl_macro__width_2 indet_comp_state ( | |
670 | .scan_in(indet_comp_state_scanin), | |
671 | .scan_out(indet_comp_state_scanout), | |
672 | .l1clk (l1clk), | |
673 | .din ({indet_rd_rdy_c, indet_wr_rdy_c}), | |
674 | .dout ({indet_rd_rdy_f, indet_wr_rdy_f}), | |
675 | .siclk(siclk), | |
676 | .soclk(soclk) | |
677 | ); | |
678 | ||
679 | assign asi_wr_request = asi_ic_wr_req_in | asi_tg_wr_req_in ; | |
680 | assign asi_rd_request = asi_ic_rd_req | asi_tg_rd_req | asi_itd_rd_req | asi_itt_rd_req | asi_ith_det_req; | |
681 | ||
682 | assign se = tcu_scan_en ; | |
683 | /////////////////////////////////////////////////////////////////////// | |
684 | // Spare circuits // | |
685 | /////////////////////////////////////////////////////////////////////// | |
686 | ifu_ftu_asi_ctl_spare_ctl_macro__num_4 spares ( | |
687 | .scan_in(spares_scanin), | |
688 | .scan_out(spares_scanout), | |
689 | .l1clk (l1clk), | |
690 | .siclk(siclk), | |
691 | .soclk(soclk) | |
692 | ); | |
693 | ||
694 | ||
695 | ||
696 | // fixscan start: | |
697 | assign asi_it_rd_done_reg_scanin = scan_in ; | |
698 | assign rng_stg1_data_scanin = asi_it_rd_done_reg_scanout; | |
699 | assign wr_data_hold_scanin = rng_stg1_data_scanout ; | |
700 | assign rng_stg1_ctl_scanin = wr_data_hold_scanout ; | |
701 | assign wr_req_ff_scanin = rng_stg1_ctl_scanout ; | |
702 | assign rng_stg2_data_scanin = wr_req_ff_scanout ; | |
703 | assign rng_stg2_ctl_scanin = rng_stg2_data_scanout ; | |
704 | assign rng_stg2_decctl_scanin = rng_stg2_ctl_scanout ; | |
705 | assign rng_stg3_decctl_scanin = rng_stg2_decctl_scanout ; | |
706 | assign rng_stg3_scanin = rng_stg3_decctl_scanout ; | |
707 | assign rng_stg3_ctl_scanin = rng_stg3_scanout ; | |
708 | assign indet_rd_data_scanin = rng_stg3_ctl_scanout ; | |
709 | assign pr_tid_wr_ret_scanin = indet_rd_data_scanout ; | |
710 | assign pr_tid_rd_ret_scanin = pr_tid_wr_ret_scanout ; | |
711 | assign address_rd_reg_scanin = pr_tid_rd_ret_scanout ; | |
712 | assign address_wr_reg_scanin = address_rd_reg_scanout ; | |
713 | assign rd_way_bf_reg_scanin = address_wr_reg_scanout ; | |
714 | assign wr_way_bf_reg_scanin = rd_way_bf_reg_scanout ; | |
715 | assign rd_is_first_reg_scanin = wr_way_bf_reg_scanout ; | |
716 | assign wr_request_pending_reg_scanin = rd_is_first_reg_scanout ; | |
717 | assign address_reg_bf_scanin = wr_request_pending_reg_scanout; | |
718 | assign indet_comp_state_scanin = address_reg_bf_scanout ; | |
719 | assign spares_scanin = indet_comp_state_scanout ; | |
720 | assign scan_out = spares_scanout ; | |
721 | // fixscan end: | |
722 | endmodule | |
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | // any PARAMS parms go into naming of macro | |
731 | ||
732 | module ifu_ftu_asi_ctl_l1clkhdr_ctl_macro ( | |
733 | l2clk, | |
734 | l1en, | |
735 | pce_ov, | |
736 | stop, | |
737 | se, | |
738 | l1clk); | |
739 | ||
740 | ||
741 | input l2clk; | |
742 | input l1en; | |
743 | input pce_ov; | |
744 | input stop; | |
745 | input se; | |
746 | output l1clk; | |
747 | ||
748 | ||
749 | ||
750 | ||
751 | ||
752 | cl_sc1_l1hdr_8x c_0 ( | |
753 | ||
754 | ||
755 | .l2clk(l2clk), | |
756 | .pce(l1en), | |
757 | .l1clk(l1clk), | |
758 | .se(se), | |
759 | .pce_ov(pce_ov), | |
760 | .stop(stop) | |
761 | ); | |
762 | ||
763 | ||
764 | ||
765 | endmodule | |
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | ||
775 | ||
776 | ||
777 | ||
778 | ||
779 | // any PARAMS parms go into naming of macro | |
780 | ||
781 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_1 ( | |
782 | din, | |
783 | l1clk, | |
784 | scan_in, | |
785 | siclk, | |
786 | soclk, | |
787 | dout, | |
788 | scan_out); | |
789 | wire [0:0] fdin; | |
790 | ||
791 | input [0:0] din; | |
792 | input l1clk; | |
793 | input scan_in; | |
794 | ||
795 | ||
796 | input siclk; | |
797 | input soclk; | |
798 | ||
799 | output [0:0] dout; | |
800 | output scan_out; | |
801 | assign fdin[0:0] = din[0:0]; | |
802 | ||
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | dff #(1) d0_0 ( | |
809 | .l1clk(l1clk), | |
810 | .siclk(siclk), | |
811 | .soclk(soclk), | |
812 | .d(fdin[0:0]), | |
813 | .si(scan_in), | |
814 | .so(scan_out), | |
815 | .q(dout[0:0]) | |
816 | ); | |
817 | ||
818 | ||
819 | ||
820 | ||
821 | ||
822 | ||
823 | ||
824 | ||
825 | ||
826 | ||
827 | ||
828 | ||
829 | endmodule | |
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | ||
837 | ||
838 | ||
839 | ||
840 | ||
841 | ||
842 | ||
843 | // any PARAMS parms go into naming of macro | |
844 | ||
845 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_64 ( | |
846 | din, | |
847 | l1clk, | |
848 | scan_in, | |
849 | siclk, | |
850 | soclk, | |
851 | dout, | |
852 | scan_out); | |
853 | wire [63:0] fdin; | |
854 | wire [62:0] so; | |
855 | ||
856 | input [63:0] din; | |
857 | input l1clk; | |
858 | input scan_in; | |
859 | ||
860 | ||
861 | input siclk; | |
862 | input soclk; | |
863 | ||
864 | output [63:0] dout; | |
865 | output scan_out; | |
866 | assign fdin[63:0] = din[63:0]; | |
867 | ||
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | dff #(64) d0_0 ( | |
874 | .l1clk(l1clk), | |
875 | .siclk(siclk), | |
876 | .soclk(soclk), | |
877 | .d(fdin[63:0]), | |
878 | .si({scan_in,so[62:0]}), | |
879 | .so({so[62:0],scan_out}), | |
880 | .q(dout[63:0]) | |
881 | ); | |
882 | ||
883 | ||
884 | ||
885 | ||
886 | ||
887 | ||
888 | ||
889 | ||
890 | ||
891 | ||
892 | ||
893 | ||
894 | endmodule | |
895 | ||
896 | ||
897 | ||
898 | ||
899 | ||
900 | ||
901 | ||
902 | ||
903 | ||
904 | ||
905 | ||
906 | ||
907 | ||
908 | // any PARAMS parms go into naming of macro | |
909 | ||
910 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_33 ( | |
911 | din, | |
912 | l1clk, | |
913 | scan_in, | |
914 | siclk, | |
915 | soclk, | |
916 | dout, | |
917 | scan_out); | |
918 | wire [32:0] fdin; | |
919 | wire [31:0] so; | |
920 | ||
921 | input [32:0] din; | |
922 | input l1clk; | |
923 | input scan_in; | |
924 | ||
925 | ||
926 | input siclk; | |
927 | input soclk; | |
928 | ||
929 | output [32:0] dout; | |
930 | output scan_out; | |
931 | assign fdin[32:0] = din[32:0]; | |
932 | ||
933 | ||
934 | ||
935 | ||
936 | ||
937 | ||
938 | dff #(33) d0_0 ( | |
939 | .l1clk(l1clk), | |
940 | .siclk(siclk), | |
941 | .soclk(soclk), | |
942 | .d(fdin[32:0]), | |
943 | .si({scan_in,so[31:0]}), | |
944 | .so({so[31:0],scan_out}), | |
945 | .q(dout[32:0]) | |
946 | ); | |
947 | ||
948 | ||
949 | ||
950 | ||
951 | ||
952 | ||
953 | ||
954 | ||
955 | ||
956 | ||
957 | ||
958 | ||
959 | endmodule | |
960 | ||
961 | ||
962 | ||
963 | ||
964 | ||
965 | ||
966 | ||
967 | ||
968 | ||
969 | ||
970 | ||
971 | ||
972 | ||
973 | // any PARAMS parms go into naming of macro | |
974 | ||
975 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_2 ( | |
976 | din, | |
977 | l1clk, | |
978 | scan_in, | |
979 | siclk, | |
980 | soclk, | |
981 | dout, | |
982 | scan_out); | |
983 | wire [1:0] fdin; | |
984 | wire [0:0] so; | |
985 | ||
986 | input [1:0] din; | |
987 | input l1clk; | |
988 | input scan_in; | |
989 | ||
990 | ||
991 | input siclk; | |
992 | input soclk; | |
993 | ||
994 | output [1:0] dout; | |
995 | output scan_out; | |
996 | assign fdin[1:0] = din[1:0]; | |
997 | ||
998 | ||
999 | ||
1000 | ||
1001 | ||
1002 | ||
1003 | dff #(2) d0_0 ( | |
1004 | .l1clk(l1clk), | |
1005 | .siclk(siclk), | |
1006 | .soclk(soclk), | |
1007 | .d(fdin[1:0]), | |
1008 | .si({scan_in,so[0:0]}), | |
1009 | .so({so[0:0],scan_out}), | |
1010 | .q(dout[1:0]) | |
1011 | ); | |
1012 | ||
1013 | ||
1014 | ||
1015 | ||
1016 | ||
1017 | ||
1018 | ||
1019 | ||
1020 | ||
1021 | ||
1022 | ||
1023 | ||
1024 | endmodule | |
1025 | ||
1026 | ||
1027 | ||
1028 | ||
1029 | ||
1030 | ||
1031 | ||
1032 | ||
1033 | ||
1034 | ||
1035 | ||
1036 | ||
1037 | ||
1038 | // any PARAMS parms go into naming of macro | |
1039 | ||
1040 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_3 ( | |
1041 | din, | |
1042 | l1clk, | |
1043 | scan_in, | |
1044 | siclk, | |
1045 | soclk, | |
1046 | dout, | |
1047 | scan_out); | |
1048 | wire [2:0] fdin; | |
1049 | wire [1:0] so; | |
1050 | ||
1051 | input [2:0] din; | |
1052 | input l1clk; | |
1053 | input scan_in; | |
1054 | ||
1055 | ||
1056 | input siclk; | |
1057 | input soclk; | |
1058 | ||
1059 | output [2:0] dout; | |
1060 | output scan_out; | |
1061 | assign fdin[2:0] = din[2:0]; | |
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | ||
1067 | ||
1068 | dff #(3) d0_0 ( | |
1069 | .l1clk(l1clk), | |
1070 | .siclk(siclk), | |
1071 | .soclk(soclk), | |
1072 | .d(fdin[2:0]), | |
1073 | .si({scan_in,so[1:0]}), | |
1074 | .so({so[1:0],scan_out}), | |
1075 | .q(dout[2:0]) | |
1076 | ); | |
1077 | ||
1078 | ||
1079 | ||
1080 | ||
1081 | ||
1082 | ||
1083 | ||
1084 | ||
1085 | ||
1086 | ||
1087 | ||
1088 | ||
1089 | endmodule | |
1090 | ||
1091 | ||
1092 | ||
1093 | ||
1094 | ||
1095 | ||
1096 | ||
1097 | ||
1098 | ||
1099 | ||
1100 | ||
1101 | ||
1102 | ||
1103 | // any PARAMS parms go into naming of macro | |
1104 | ||
1105 | module ifu_ftu_asi_ctl_msff_ctl_macro__en_1__width_64 ( | |
1106 | din, | |
1107 | en, | |
1108 | l1clk, | |
1109 | scan_in, | |
1110 | siclk, | |
1111 | soclk, | |
1112 | dout, | |
1113 | scan_out); | |
1114 | wire [63:0] fdin; | |
1115 | wire [62:0] so; | |
1116 | ||
1117 | input [63:0] din; | |
1118 | input en; | |
1119 | input l1clk; | |
1120 | input scan_in; | |
1121 | ||
1122 | ||
1123 | input siclk; | |
1124 | input soclk; | |
1125 | ||
1126 | output [63:0] dout; | |
1127 | output scan_out; | |
1128 | assign fdin[63:0] = (din[63:0] & {64{en}}) | (dout[63:0] & ~{64{en}}); | |
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | ||
1134 | ||
1135 | dff #(64) d0_0 ( | |
1136 | .l1clk(l1clk), | |
1137 | .siclk(siclk), | |
1138 | .soclk(soclk), | |
1139 | .d(fdin[63:0]), | |
1140 | .si({scan_in,so[62:0]}), | |
1141 | .so({so[62:0],scan_out}), | |
1142 | .q(dout[63:0]) | |
1143 | ); | |
1144 | ||
1145 | ||
1146 | ||
1147 | ||
1148 | ||
1149 | ||
1150 | ||
1151 | ||
1152 | ||
1153 | ||
1154 | ||
1155 | ||
1156 | endmodule | |
1157 | ||
1158 | ||
1159 | ||
1160 | ||
1161 | ||
1162 | ||
1163 | ||
1164 | ||
1165 | ||
1166 | ||
1167 | ||
1168 | ||
1169 | ||
1170 | // any PARAMS parms go into naming of macro | |
1171 | ||
1172 | module ifu_ftu_asi_ctl_msff_ctl_macro__width_37 ( | |
1173 | din, | |
1174 | l1clk, | |
1175 | scan_in, | |
1176 | siclk, | |
1177 | soclk, | |
1178 | dout, | |
1179 | scan_out); | |
1180 | wire [36:0] fdin; | |
1181 | wire [35:0] so; | |
1182 | ||
1183 | input [36:0] din; | |
1184 | input l1clk; | |
1185 | input scan_in; | |
1186 | ||
1187 | ||
1188 | input siclk; | |
1189 | input soclk; | |
1190 | ||
1191 | output [36:0] dout; | |
1192 | output scan_out; | |
1193 | assign fdin[36:0] = din[36:0]; | |
1194 | ||
1195 | ||
1196 | ||
1197 | ||
1198 | ||
1199 | ||
1200 | dff #(37) d0_0 ( | |
1201 | .l1clk(l1clk), | |
1202 | .siclk(siclk), | |
1203 | .soclk(soclk), | |
1204 | .d(fdin[36:0]), | |
1205 | .si({scan_in,so[35:0]}), | |
1206 | .so({so[35:0],scan_out}), | |
1207 | .q(dout[36:0]) | |
1208 | ); | |
1209 | ||
1210 | ||
1211 | ||
1212 | ||
1213 | ||
1214 | ||
1215 | ||
1216 | ||
1217 | ||
1218 | ||
1219 | ||
1220 | ||
1221 | endmodule | |
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | ||
1231 | // Description: Spare gate macro for control blocks | |
1232 | // | |
1233 | // Param num controls the number of times the macro is added | |
1234 | // flops=0 can be used to use only combination spare logic | |
1235 | ||
1236 | ||
1237 | module ifu_ftu_asi_ctl_spare_ctl_macro__num_4 ( | |
1238 | l1clk, | |
1239 | scan_in, | |
1240 | siclk, | |
1241 | soclk, | |
1242 | scan_out); | |
1243 | wire si_0; | |
1244 | wire so_0; | |
1245 | wire spare0_flop_unused; | |
1246 | wire spare0_buf_32x_unused; | |
1247 | wire spare0_nand3_8x_unused; | |
1248 | wire spare0_inv_8x_unused; | |
1249 | wire spare0_aoi22_4x_unused; | |
1250 | wire spare0_buf_8x_unused; | |
1251 | wire spare0_oai22_4x_unused; | |
1252 | wire spare0_inv_16x_unused; | |
1253 | wire spare0_nand2_16x_unused; | |
1254 | wire spare0_nor3_4x_unused; | |
1255 | wire spare0_nand2_8x_unused; | |
1256 | wire spare0_buf_16x_unused; | |
1257 | wire spare0_nor2_16x_unused; | |
1258 | wire spare0_inv_32x_unused; | |
1259 | wire si_1; | |
1260 | wire so_1; | |
1261 | wire spare1_flop_unused; | |
1262 | wire spare1_buf_32x_unused; | |
1263 | wire spare1_nand3_8x_unused; | |
1264 | wire spare1_inv_8x_unused; | |
1265 | wire spare1_aoi22_4x_unused; | |
1266 | wire spare1_buf_8x_unused; | |
1267 | wire spare1_oai22_4x_unused; | |
1268 | wire spare1_inv_16x_unused; | |
1269 | wire spare1_nand2_16x_unused; | |
1270 | wire spare1_nor3_4x_unused; | |
1271 | wire spare1_nand2_8x_unused; | |
1272 | wire spare1_buf_16x_unused; | |
1273 | wire spare1_nor2_16x_unused; | |
1274 | wire spare1_inv_32x_unused; | |
1275 | wire si_2; | |
1276 | wire so_2; | |
1277 | wire spare2_flop_unused; | |
1278 | wire spare2_buf_32x_unused; | |
1279 | wire spare2_nand3_8x_unused; | |
1280 | wire spare2_inv_8x_unused; | |
1281 | wire spare2_aoi22_4x_unused; | |
1282 | wire spare2_buf_8x_unused; | |
1283 | wire spare2_oai22_4x_unused; | |
1284 | wire spare2_inv_16x_unused; | |
1285 | wire spare2_nand2_16x_unused; | |
1286 | wire spare2_nor3_4x_unused; | |
1287 | wire spare2_nand2_8x_unused; | |
1288 | wire spare2_buf_16x_unused; | |
1289 | wire spare2_nor2_16x_unused; | |
1290 | wire spare2_inv_32x_unused; | |
1291 | wire si_3; | |
1292 | wire so_3; | |
1293 | wire spare3_flop_unused; | |
1294 | wire spare3_buf_32x_unused; | |
1295 | wire spare3_nand3_8x_unused; | |
1296 | wire spare3_inv_8x_unused; | |
1297 | wire spare3_aoi22_4x_unused; | |
1298 | wire spare3_buf_8x_unused; | |
1299 | wire spare3_oai22_4x_unused; | |
1300 | wire spare3_inv_16x_unused; | |
1301 | wire spare3_nand2_16x_unused; | |
1302 | wire spare3_nor3_4x_unused; | |
1303 | wire spare3_nand2_8x_unused; | |
1304 | wire spare3_buf_16x_unused; | |
1305 | wire spare3_nor2_16x_unused; | |
1306 | wire spare3_inv_32x_unused; | |
1307 | ||
1308 | ||
1309 | input l1clk; | |
1310 | input scan_in; | |
1311 | input siclk; | |
1312 | input soclk; | |
1313 | output scan_out; | |
1314 | ||
1315 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1316 | .siclk(siclk), | |
1317 | .soclk(soclk), | |
1318 | .si(si_0), | |
1319 | .so(so_0), | |
1320 | .d(1'b0), | |
1321 | .q(spare0_flop_unused)); | |
1322 | assign si_0 = scan_in; | |
1323 | ||
1324 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1325 | .out(spare0_buf_32x_unused)); | |
1326 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1327 | .in1(1'b1), | |
1328 | .in2(1'b1), | |
1329 | .out(spare0_nand3_8x_unused)); | |
1330 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1331 | .out(spare0_inv_8x_unused)); | |
1332 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1333 | .in01(1'b1), | |
1334 | .in10(1'b1), | |
1335 | .in11(1'b1), | |
1336 | .out(spare0_aoi22_4x_unused)); | |
1337 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1338 | .out(spare0_buf_8x_unused)); | |
1339 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1340 | .in01(1'b1), | |
1341 | .in10(1'b1), | |
1342 | .in11(1'b1), | |
1343 | .out(spare0_oai22_4x_unused)); | |
1344 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1345 | .out(spare0_inv_16x_unused)); | |
1346 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1347 | .in1(1'b1), | |
1348 | .out(spare0_nand2_16x_unused)); | |
1349 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1350 | .in1(1'b0), | |
1351 | .in2(1'b0), | |
1352 | .out(spare0_nor3_4x_unused)); | |
1353 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1354 | .in1(1'b1), | |
1355 | .out(spare0_nand2_8x_unused)); | |
1356 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1357 | .out(spare0_buf_16x_unused)); | |
1358 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1359 | .in1(1'b0), | |
1360 | .out(spare0_nor2_16x_unused)); | |
1361 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1362 | .out(spare0_inv_32x_unused)); | |
1363 | ||
1364 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1365 | .siclk(siclk), | |
1366 | .soclk(soclk), | |
1367 | .si(si_1), | |
1368 | .so(so_1), | |
1369 | .d(1'b0), | |
1370 | .q(spare1_flop_unused)); | |
1371 | assign si_1 = so_0; | |
1372 | ||
1373 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1374 | .out(spare1_buf_32x_unused)); | |
1375 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1376 | .in1(1'b1), | |
1377 | .in2(1'b1), | |
1378 | .out(spare1_nand3_8x_unused)); | |
1379 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1380 | .out(spare1_inv_8x_unused)); | |
1381 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1382 | .in01(1'b1), | |
1383 | .in10(1'b1), | |
1384 | .in11(1'b1), | |
1385 | .out(spare1_aoi22_4x_unused)); | |
1386 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1387 | .out(spare1_buf_8x_unused)); | |
1388 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1389 | .in01(1'b1), | |
1390 | .in10(1'b1), | |
1391 | .in11(1'b1), | |
1392 | .out(spare1_oai22_4x_unused)); | |
1393 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1394 | .out(spare1_inv_16x_unused)); | |
1395 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1396 | .in1(1'b1), | |
1397 | .out(spare1_nand2_16x_unused)); | |
1398 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1399 | .in1(1'b0), | |
1400 | .in2(1'b0), | |
1401 | .out(spare1_nor3_4x_unused)); | |
1402 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1403 | .in1(1'b1), | |
1404 | .out(spare1_nand2_8x_unused)); | |
1405 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1406 | .out(spare1_buf_16x_unused)); | |
1407 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1408 | .in1(1'b0), | |
1409 | .out(spare1_nor2_16x_unused)); | |
1410 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1411 | .out(spare1_inv_32x_unused)); | |
1412 | ||
1413 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
1414 | .siclk(siclk), | |
1415 | .soclk(soclk), | |
1416 | .si(si_2), | |
1417 | .so(so_2), | |
1418 | .d(1'b0), | |
1419 | .q(spare2_flop_unused)); | |
1420 | assign si_2 = so_1; | |
1421 | ||
1422 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
1423 | .out(spare2_buf_32x_unused)); | |
1424 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
1425 | .in1(1'b1), | |
1426 | .in2(1'b1), | |
1427 | .out(spare2_nand3_8x_unused)); | |
1428 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
1429 | .out(spare2_inv_8x_unused)); | |
1430 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
1431 | .in01(1'b1), | |
1432 | .in10(1'b1), | |
1433 | .in11(1'b1), | |
1434 | .out(spare2_aoi22_4x_unused)); | |
1435 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
1436 | .out(spare2_buf_8x_unused)); | |
1437 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
1438 | .in01(1'b1), | |
1439 | .in10(1'b1), | |
1440 | .in11(1'b1), | |
1441 | .out(spare2_oai22_4x_unused)); | |
1442 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
1443 | .out(spare2_inv_16x_unused)); | |
1444 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
1445 | .in1(1'b1), | |
1446 | .out(spare2_nand2_16x_unused)); | |
1447 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
1448 | .in1(1'b0), | |
1449 | .in2(1'b0), | |
1450 | .out(spare2_nor3_4x_unused)); | |
1451 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
1452 | .in1(1'b1), | |
1453 | .out(spare2_nand2_8x_unused)); | |
1454 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
1455 | .out(spare2_buf_16x_unused)); | |
1456 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
1457 | .in1(1'b0), | |
1458 | .out(spare2_nor2_16x_unused)); | |
1459 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
1460 | .out(spare2_inv_32x_unused)); | |
1461 | ||
1462 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
1463 | .siclk(siclk), | |
1464 | .soclk(soclk), | |
1465 | .si(si_3), | |
1466 | .so(so_3), | |
1467 | .d(1'b0), | |
1468 | .q(spare3_flop_unused)); | |
1469 | assign si_3 = so_2; | |
1470 | ||
1471 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
1472 | .out(spare3_buf_32x_unused)); | |
1473 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
1474 | .in1(1'b1), | |
1475 | .in2(1'b1), | |
1476 | .out(spare3_nand3_8x_unused)); | |
1477 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
1478 | .out(spare3_inv_8x_unused)); | |
1479 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
1480 | .in01(1'b1), | |
1481 | .in10(1'b1), | |
1482 | .in11(1'b1), | |
1483 | .out(spare3_aoi22_4x_unused)); | |
1484 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
1485 | .out(spare3_buf_8x_unused)); | |
1486 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
1487 | .in01(1'b1), | |
1488 | .in10(1'b1), | |
1489 | .in11(1'b1), | |
1490 | .out(spare3_oai22_4x_unused)); | |
1491 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
1492 | .out(spare3_inv_16x_unused)); | |
1493 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
1494 | .in1(1'b1), | |
1495 | .out(spare3_nand2_16x_unused)); | |
1496 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
1497 | .in1(1'b0), | |
1498 | .in2(1'b0), | |
1499 | .out(spare3_nor3_4x_unused)); | |
1500 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
1501 | .in1(1'b1), | |
1502 | .out(spare3_nand2_8x_unused)); | |
1503 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
1504 | .out(spare3_buf_16x_unused)); | |
1505 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
1506 | .in1(1'b0), | |
1507 | .out(spare3_nor2_16x_unused)); | |
1508 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
1509 | .out(spare3_inv_32x_unused)); | |
1510 | assign scan_out = so_3; | |
1511 | ||
1512 | ||
1513 | ||
1514 | endmodule | |
1515 |