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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: ifu_ftu_red_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module ifu_ftu_red_ctl ( | |
36 | efu_spc_fuse_data, | |
37 | efu_spc_fuse_ixfer_en, | |
38 | efu_spc_fuse_iclr, | |
39 | io_cmp_sync_en, | |
40 | cmp_io_sync_en, | |
41 | spc_efu_fuse_idata, | |
42 | spc_efu_fuse_ixfer_en, | |
43 | hdr_sram_rvalue, | |
44 | hdr_sram_rid, | |
45 | hdr_sram_wr_en, | |
46 | hdr_sram_red_clr, | |
47 | sram_hdr_read_data, | |
48 | l2clk, | |
49 | tcu_pce_ov, | |
50 | spc_aclk, | |
51 | spc_bclk, | |
52 | tcu_scan_en, | |
53 | scan_in, | |
54 | scan_out); | |
55 | wire [4:0] rval_unused; | |
56 | wire [6:0] rid_unused; | |
57 | ||
58 | ||
59 | // EFU to SRAM header | |
60 | input efu_spc_fuse_data; // Efuse to dest data info | |
61 | input efu_spc_fuse_ixfer_en;// Efuse to dest data valid | |
62 | input efu_spc_fuse_iclr; // EFuse to dest clear corresponding redudancy register | |
63 | input io_cmp_sync_en; | |
64 | input cmp_io_sync_en; | |
65 | ||
66 | // SRAM header to EFU | |
67 | output spc_efu_fuse_idata; // Dest to EFU read data return | |
68 | output spc_efu_fuse_ixfer_en; // Dest to EFU read data return valid | |
69 | ||
70 | // SRAM header to SRAM | |
71 | output [5:0] hdr_sram_rvalue; // Redudancy Value to be written | |
72 | // to SRAM red reg | |
73 | output [3:0] hdr_sram_rid; // Redudancy ID to address SRAM | |
74 | // red reg | |
75 | output hdr_sram_wr_en; // Redudancy register write | |
76 | // enable to write to red reg | |
77 | output hdr_sram_red_clr; // Redudancy register clear | |
78 | // | |
79 | ||
80 | // SRAM to SRAM header | |
81 | input [5:0] sram_hdr_read_data; // Redudancy Read data from SRAM | |
82 | ||
83 | ||
84 | // other common signals | |
85 | input l2clk; | |
86 | input tcu_pce_ov; | |
87 | input spc_aclk; | |
88 | input spc_bclk; | |
89 | input tcu_scan_en; | |
90 | input scan_in; | |
91 | output scan_out; | |
92 | ||
93 | n2_efuhdr1_ctl sram_header_instance | |
94 | ( | |
95 | // All the I/o ports to and from EFU <-> cluster | |
96 | .efu_hdr_write_data (efu_spc_fuse_data), | |
97 | .efu_hdr_xfer_en (efu_spc_fuse_ixfer_en), | |
98 | .efu_hdr_clr (efu_spc_fuse_iclr), | |
99 | .hdr_efu_read_data (spc_efu_fuse_idata), | |
100 | .io_cmp_sync_en (io_cmp_sync_en), | |
101 | .cmp_io_sync_en (cmp_io_sync_en), | |
102 | .hdr_efu_xfer_en (spc_efu_fuse_ixfer_en), | |
103 | // All other general signals for DFT and clocks | |
104 | .scan_in (scan_in), | |
105 | .scan_out (scan_out), | |
106 | .l2clk (l2clk), | |
107 | .tcu_pce_ov (tcu_pce_ov), | |
108 | .tcu_aclk (spc_aclk), | |
109 | .tcu_bclk (spc_bclk), | |
110 | .tcu_scan_en (tcu_scan_en), | |
111 | .tcu_clk_stop (1'b0), | |
112 | // All the I/o ports to and from SRAM | |
113 | .sram_hdr_read_data ({5'b0,sram_hdr_read_data[5:0]}), | |
114 | .hdr_sram_rvalue ({rval_unused[4:0],hdr_sram_rvalue[5:0]}), | |
115 | .hdr_sram_rid ({rid_unused[6:0],hdr_sram_rid[3:0]}), | |
116 | .hdr_sram_wr_en (hdr_sram_wr_en), | |
117 | .hdr_sram_red_clr (hdr_sram_red_clr) | |
118 | ); | |
119 | ||
120 | ||
121 | endmodule | |
122 | ||
123 | ||
124 | // any PARAMS parms go into naming of macro | |
125 | ||
126 | module ifu_ftu_red_ctl_l1clkhdr_ctl_macro ( | |
127 | l2clk, | |
128 | l1en, | |
129 | pce_ov, | |
130 | stop, | |
131 | se, | |
132 | l1clk); | |
133 | ||
134 | ||
135 | input l2clk; | |
136 | input l1en; | |
137 | input pce_ov; | |
138 | input stop; | |
139 | input se; | |
140 | output l1clk; | |
141 | ||
142 | ||
143 | ||
144 | ||
145 | ||
146 | cl_sc1_l1hdr_8x c_0 ( | |
147 | ||
148 | ||
149 | .l2clk(l2clk), | |
150 | .pce(l1en), | |
151 | .l1clk(l1clk), | |
152 | .se(se), | |
153 | .pce_ov(pce_ov), | |
154 | .stop(stop) | |
155 | ); | |
156 | ||
157 | ||
158 | ||
159 | endmodule | |
160 | ||
161 | ||
162 | ||
163 | ||
164 | ||
165 | ||
166 | ||
167 | ||
168 | ||
169 | ||
170 | ||
171 | ||
172 | ||
173 | // any PARAMS parms go into naming of macro | |
174 | ||
175 | module ifu_ftu_red_ctl_msff_ctl_macro__width_1 ( | |
176 | din, | |
177 | l1clk, | |
178 | scan_in, | |
179 | siclk, | |
180 | soclk, | |
181 | dout, | |
182 | scan_out); | |
183 | wire [0:0] fdin; | |
184 | ||
185 | input [0:0] din; | |
186 | input l1clk; | |
187 | input scan_in; | |
188 | ||
189 | ||
190 | input siclk; | |
191 | input soclk; | |
192 | ||
193 | output [0:0] dout; | |
194 | output scan_out; | |
195 | assign fdin[0:0] = din[0:0]; | |
196 | ||
197 | ||
198 | ||
199 | ||
200 | ||
201 | ||
202 | dff #(1) d0_0 ( | |
203 | .l1clk(l1clk), | |
204 | .siclk(siclk), | |
205 | .soclk(soclk), | |
206 | .d(fdin[0:0]), | |
207 | .si(scan_in), | |
208 | .so(scan_out), | |
209 | .q(dout[0:0]) | |
210 | ); | |
211 | ||
212 | ||
213 | ||
214 | ||
215 | ||
216 | ||
217 | ||
218 | ||
219 | ||
220 | ||
221 | ||
222 | ||
223 | endmodule | |
224 | ||
225 | ||
226 | ||
227 | ||
228 | ||
229 | ||
230 | ||
231 | ||
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | // any PARAMS parms go into naming of macro | |
238 | ||
239 | module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_4 ( | |
240 | din, | |
241 | en, | |
242 | l1clk, | |
243 | scan_in, | |
244 | siclk, | |
245 | soclk, | |
246 | dout, | |
247 | scan_out); | |
248 | wire [3:0] fdin; | |
249 | wire [2:0] so; | |
250 | ||
251 | input [3:0] din; | |
252 | input en; | |
253 | input l1clk; | |
254 | input scan_in; | |
255 | ||
256 | ||
257 | input siclk; | |
258 | input soclk; | |
259 | ||
260 | output [3:0] dout; | |
261 | output scan_out; | |
262 | assign fdin[3:0] = (din[3:0] & {4{en}}) | (dout[3:0] & ~{4{en}}); | |
263 | ||
264 | ||
265 | ||
266 | ||
267 | ||
268 | ||
269 | dff #(4) d0_0 ( | |
270 | .l1clk(l1clk), | |
271 | .siclk(siclk), | |
272 | .soclk(soclk), | |
273 | .d(fdin[3:0]), | |
274 | .si({scan_in,so[2:0]}), | |
275 | .so({so[2:0],scan_out}), | |
276 | .q(dout[3:0]) | |
277 | ); | |
278 | ||
279 | ||
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | endmodule | |
291 | ||
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | ||
302 | ||
303 | ||
304 | // any PARAMS parms go into naming of macro | |
305 | ||
306 | module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_22 ( | |
307 | din, | |
308 | en, | |
309 | l1clk, | |
310 | scan_in, | |
311 | siclk, | |
312 | soclk, | |
313 | dout, | |
314 | scan_out); | |
315 | wire [21:0] fdin; | |
316 | wire [20:0] so; | |
317 | ||
318 | input [21:0] din; | |
319 | input en; | |
320 | input l1clk; | |
321 | input scan_in; | |
322 | ||
323 | ||
324 | input siclk; | |
325 | input soclk; | |
326 | ||
327 | output [21:0] dout; | |
328 | output scan_out; | |
329 | assign fdin[21:0] = (din[21:0] & {22{en}}) | (dout[21:0] & ~{22{en}}); | |
330 | ||
331 | ||
332 | ||
333 | ||
334 | ||
335 | ||
336 | dff #(22) d0_0 ( | |
337 | .l1clk(l1clk), | |
338 | .siclk(siclk), | |
339 | .soclk(soclk), | |
340 | .d(fdin[21:0]), | |
341 | .si({scan_in,so[20:0]}), | |
342 | .so({so[20:0],scan_out}), | |
343 | .q(dout[21:0]) | |
344 | ); | |
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | endmodule | |
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | ||
368 | ||
369 | ||
370 | ||
371 | // any PARAMS parms go into naming of macro | |
372 | ||
373 | module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_1 ( | |
374 | din, | |
375 | en, | |
376 | l1clk, | |
377 | scan_in, | |
378 | siclk, | |
379 | soclk, | |
380 | dout, | |
381 | scan_out); | |
382 | wire [0:0] fdin; | |
383 | ||
384 | input [0:0] din; | |
385 | input en; | |
386 | input l1clk; | |
387 | input scan_in; | |
388 | ||
389 | ||
390 | input siclk; | |
391 | input soclk; | |
392 | ||
393 | output [0:0] dout; | |
394 | output scan_out; | |
395 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | dff #(1) d0_0 ( | |
403 | .l1clk(l1clk), | |
404 | .siclk(siclk), | |
405 | .soclk(soclk), | |
406 | .d(fdin[0:0]), | |
407 | .si(scan_in), | |
408 | .so(scan_out), | |
409 | .q(dout[0:0]) | |
410 | ); | |
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | ||
421 | ||
422 | ||
423 | endmodule | |
424 | ||
425 | ||
426 | ||
427 | ||
428 | ||
429 | ||
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | // any PARAMS parms go into naming of macro | |
438 | ||
439 | module ifu_ftu_red_ctl_msff_ctl_macro__en_1__width_5 ( | |
440 | din, | |
441 | en, | |
442 | l1clk, | |
443 | scan_in, | |
444 | siclk, | |
445 | soclk, | |
446 | dout, | |
447 | scan_out); | |
448 | wire [4:0] fdin; | |
449 | wire [3:0] so; | |
450 | ||
451 | input [4:0] din; | |
452 | input en; | |
453 | input l1clk; | |
454 | input scan_in; | |
455 | ||
456 | ||
457 | input siclk; | |
458 | input soclk; | |
459 | ||
460 | output [4:0] dout; | |
461 | output scan_out; | |
462 | assign fdin[4:0] = (din[4:0] & {5{en}}) | (dout[4:0] & ~{5{en}}); | |
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | dff #(5) d0_0 ( | |
470 | .l1clk(l1clk), | |
471 | .siclk(siclk), | |
472 | .soclk(soclk), | |
473 | .d(fdin[4:0]), | |
474 | .si({scan_in,so[3:0]}), | |
475 | .so({so[3:0],scan_out}), | |
476 | .q(dout[4:0]) | |
477 | ); | |
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | endmodule | |
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | // Description: Spare gate macro for control blocks | |
501 | // | |
502 | // Param num controls the number of times the macro is added | |
503 | // flops=0 can be used to use only combination spare logic | |
504 | ||
505 | ||
506 | module ifu_ftu_red_ctl_spare_ctl_macro__num_4 ( | |
507 | l1clk, | |
508 | scan_in, | |
509 | siclk, | |
510 | soclk, | |
511 | scan_out); | |
512 | wire si_0; | |
513 | wire so_0; | |
514 | wire spare0_flop_unused; | |
515 | wire spare0_buf_32x_unused; | |
516 | wire spare0_nand3_8x_unused; | |
517 | wire spare0_inv_8x_unused; | |
518 | wire spare0_aoi22_4x_unused; | |
519 | wire spare0_buf_8x_unused; | |
520 | wire spare0_oai22_4x_unused; | |
521 | wire spare0_inv_16x_unused; | |
522 | wire spare0_nand2_16x_unused; | |
523 | wire spare0_nor3_4x_unused; | |
524 | wire spare0_nand2_8x_unused; | |
525 | wire spare0_buf_16x_unused; | |
526 | wire spare0_nor2_16x_unused; | |
527 | wire spare0_inv_32x_unused; | |
528 | wire si_1; | |
529 | wire so_1; | |
530 | wire spare1_flop_unused; | |
531 | wire spare1_buf_32x_unused; | |
532 | wire spare1_nand3_8x_unused; | |
533 | wire spare1_inv_8x_unused; | |
534 | wire spare1_aoi22_4x_unused; | |
535 | wire spare1_buf_8x_unused; | |
536 | wire spare1_oai22_4x_unused; | |
537 | wire spare1_inv_16x_unused; | |
538 | wire spare1_nand2_16x_unused; | |
539 | wire spare1_nor3_4x_unused; | |
540 | wire spare1_nand2_8x_unused; | |
541 | wire spare1_buf_16x_unused; | |
542 | wire spare1_nor2_16x_unused; | |
543 | wire spare1_inv_32x_unused; | |
544 | wire si_2; | |
545 | wire so_2; | |
546 | wire spare2_flop_unused; | |
547 | wire spare2_buf_32x_unused; | |
548 | wire spare2_nand3_8x_unused; | |
549 | wire spare2_inv_8x_unused; | |
550 | wire spare2_aoi22_4x_unused; | |
551 | wire spare2_buf_8x_unused; | |
552 | wire spare2_oai22_4x_unused; | |
553 | wire spare2_inv_16x_unused; | |
554 | wire spare2_nand2_16x_unused; | |
555 | wire spare2_nor3_4x_unused; | |
556 | wire spare2_nand2_8x_unused; | |
557 | wire spare2_buf_16x_unused; | |
558 | wire spare2_nor2_16x_unused; | |
559 | wire spare2_inv_32x_unused; | |
560 | wire si_3; | |
561 | wire so_3; | |
562 | wire spare3_flop_unused; | |
563 | wire spare3_buf_32x_unused; | |
564 | wire spare3_nand3_8x_unused; | |
565 | wire spare3_inv_8x_unused; | |
566 | wire spare3_aoi22_4x_unused; | |
567 | wire spare3_buf_8x_unused; | |
568 | wire spare3_oai22_4x_unused; | |
569 | wire spare3_inv_16x_unused; | |
570 | wire spare3_nand2_16x_unused; | |
571 | wire spare3_nor3_4x_unused; | |
572 | wire spare3_nand2_8x_unused; | |
573 | wire spare3_buf_16x_unused; | |
574 | wire spare3_nor2_16x_unused; | |
575 | wire spare3_inv_32x_unused; | |
576 | ||
577 | ||
578 | input l1clk; | |
579 | input scan_in; | |
580 | input siclk; | |
581 | input soclk; | |
582 | output scan_out; | |
583 | ||
584 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
585 | .siclk(siclk), | |
586 | .soclk(soclk), | |
587 | .si(si_0), | |
588 | .so(so_0), | |
589 | .d(1'b0), | |
590 | .q(spare0_flop_unused)); | |
591 | assign si_0 = scan_in; | |
592 | ||
593 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
594 | .out(spare0_buf_32x_unused)); | |
595 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
596 | .in1(1'b1), | |
597 | .in2(1'b1), | |
598 | .out(spare0_nand3_8x_unused)); | |
599 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
600 | .out(spare0_inv_8x_unused)); | |
601 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
602 | .in01(1'b1), | |
603 | .in10(1'b1), | |
604 | .in11(1'b1), | |
605 | .out(spare0_aoi22_4x_unused)); | |
606 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
607 | .out(spare0_buf_8x_unused)); | |
608 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
609 | .in01(1'b1), | |
610 | .in10(1'b1), | |
611 | .in11(1'b1), | |
612 | .out(spare0_oai22_4x_unused)); | |
613 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
614 | .out(spare0_inv_16x_unused)); | |
615 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
616 | .in1(1'b1), | |
617 | .out(spare0_nand2_16x_unused)); | |
618 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
619 | .in1(1'b0), | |
620 | .in2(1'b0), | |
621 | .out(spare0_nor3_4x_unused)); | |
622 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
623 | .in1(1'b1), | |
624 | .out(spare0_nand2_8x_unused)); | |
625 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
626 | .out(spare0_buf_16x_unused)); | |
627 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
628 | .in1(1'b0), | |
629 | .out(spare0_nor2_16x_unused)); | |
630 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
631 | .out(spare0_inv_32x_unused)); | |
632 | ||
633 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
634 | .siclk(siclk), | |
635 | .soclk(soclk), | |
636 | .si(si_1), | |
637 | .so(so_1), | |
638 | .d(1'b0), | |
639 | .q(spare1_flop_unused)); | |
640 | assign si_1 = so_0; | |
641 | ||
642 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
643 | .out(spare1_buf_32x_unused)); | |
644 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
645 | .in1(1'b1), | |
646 | .in2(1'b1), | |
647 | .out(spare1_nand3_8x_unused)); | |
648 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
649 | .out(spare1_inv_8x_unused)); | |
650 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
651 | .in01(1'b1), | |
652 | .in10(1'b1), | |
653 | .in11(1'b1), | |
654 | .out(spare1_aoi22_4x_unused)); | |
655 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
656 | .out(spare1_buf_8x_unused)); | |
657 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
658 | .in01(1'b1), | |
659 | .in10(1'b1), | |
660 | .in11(1'b1), | |
661 | .out(spare1_oai22_4x_unused)); | |
662 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
663 | .out(spare1_inv_16x_unused)); | |
664 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
665 | .in1(1'b1), | |
666 | .out(spare1_nand2_16x_unused)); | |
667 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
668 | .in1(1'b0), | |
669 | .in2(1'b0), | |
670 | .out(spare1_nor3_4x_unused)); | |
671 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
672 | .in1(1'b1), | |
673 | .out(spare1_nand2_8x_unused)); | |
674 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
675 | .out(spare1_buf_16x_unused)); | |
676 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
677 | .in1(1'b0), | |
678 | .out(spare1_nor2_16x_unused)); | |
679 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
680 | .out(spare1_inv_32x_unused)); | |
681 | ||
682 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
683 | .siclk(siclk), | |
684 | .soclk(soclk), | |
685 | .si(si_2), | |
686 | .so(so_2), | |
687 | .d(1'b0), | |
688 | .q(spare2_flop_unused)); | |
689 | assign si_2 = so_1; | |
690 | ||
691 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
692 | .out(spare2_buf_32x_unused)); | |
693 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
694 | .in1(1'b1), | |
695 | .in2(1'b1), | |
696 | .out(spare2_nand3_8x_unused)); | |
697 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
698 | .out(spare2_inv_8x_unused)); | |
699 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
700 | .in01(1'b1), | |
701 | .in10(1'b1), | |
702 | .in11(1'b1), | |
703 | .out(spare2_aoi22_4x_unused)); | |
704 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
705 | .out(spare2_buf_8x_unused)); | |
706 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
707 | .in01(1'b1), | |
708 | .in10(1'b1), | |
709 | .in11(1'b1), | |
710 | .out(spare2_oai22_4x_unused)); | |
711 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
712 | .out(spare2_inv_16x_unused)); | |
713 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
714 | .in1(1'b1), | |
715 | .out(spare2_nand2_16x_unused)); | |
716 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
717 | .in1(1'b0), | |
718 | .in2(1'b0), | |
719 | .out(spare2_nor3_4x_unused)); | |
720 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
721 | .in1(1'b1), | |
722 | .out(spare2_nand2_8x_unused)); | |
723 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
724 | .out(spare2_buf_16x_unused)); | |
725 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
726 | .in1(1'b0), | |
727 | .out(spare2_nor2_16x_unused)); | |
728 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
729 | .out(spare2_inv_32x_unused)); | |
730 | ||
731 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
732 | .siclk(siclk), | |
733 | .soclk(soclk), | |
734 | .si(si_3), | |
735 | .so(so_3), | |
736 | .d(1'b0), | |
737 | .q(spare3_flop_unused)); | |
738 | assign si_3 = so_2; | |
739 | ||
740 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
741 | .out(spare3_buf_32x_unused)); | |
742 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
743 | .in1(1'b1), | |
744 | .in2(1'b1), | |
745 | .out(spare3_nand3_8x_unused)); | |
746 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
747 | .out(spare3_inv_8x_unused)); | |
748 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
749 | .in01(1'b1), | |
750 | .in10(1'b1), | |
751 | .in11(1'b1), | |
752 | .out(spare3_aoi22_4x_unused)); | |
753 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
754 | .out(spare3_buf_8x_unused)); | |
755 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
756 | .in01(1'b1), | |
757 | .in10(1'b1), | |
758 | .in11(1'b1), | |
759 | .out(spare3_oai22_4x_unused)); | |
760 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
761 | .out(spare3_inv_16x_unused)); | |
762 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
763 | .in1(1'b1), | |
764 | .out(spare3_nand2_16x_unused)); | |
765 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
766 | .in1(1'b0), | |
767 | .in2(1'b0), | |
768 | .out(spare3_nor3_4x_unused)); | |
769 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
770 | .in1(1'b1), | |
771 | .out(spare3_nand2_8x_unused)); | |
772 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
773 | .out(spare3_buf_16x_unused)); | |
774 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
775 | .in1(1'b0), | |
776 | .out(spare3_nor2_16x_unused)); | |
777 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
778 | .out(spare3_inv_32x_unused)); | |
779 | assign scan_out = so_3; | |
780 | ||
781 | ||
782 | ||
783 | endmodule | |
784 |