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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_adc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_adc_ctl ( | |
36 | asi_e, | |
37 | asi_m, | |
38 | lsu_va_m, | |
39 | sr_inst_e, | |
40 | pr_inst_e, | |
41 | hpr_inst_e, | |
42 | sr_inst_m, | |
43 | pr_inst_m, | |
44 | hpr_inst_m, | |
45 | altspace_ldst_e, | |
46 | altspace_ldst_m, | |
47 | ld_inst_vld_m, | |
48 | legal_asi_va_m, | |
49 | asi_legal_e, | |
50 | asr_legal_m, | |
51 | asi_sync_m, | |
52 | asi_internal_e, | |
53 | asi_rngf_m, | |
54 | asi_indet_m, | |
55 | lendian_asi_m, | |
56 | asi_sz_byte_m, | |
57 | asi_sz_hw_m, | |
58 | pst_asi_m, | |
59 | asi_pst8_m, | |
60 | asi_pst16_m, | |
61 | asi_pst32_m, | |
62 | asi_read_only_m, | |
63 | asi_write_only_m, | |
64 | quad_asi_m, | |
65 | binit_quad_asi_m, | |
66 | primary_asi_e, | |
67 | secondary_asi_e, | |
68 | real_asi_e, | |
69 | as_if_user_asi_e, | |
70 | as_if_priv_asi_e, | |
71 | atomic_asi_m, | |
72 | blk_asi_e, | |
73 | nofault_asi_m, | |
74 | asi_iomap_m, | |
75 | asi_no_va_check_m); | |
76 | wire indet_m; | |
77 | ||
78 | ||
79 | input [7:0] asi_e; | |
80 | input [7:0] asi_m; // This version has SR/PR/HPR muxed in | |
81 | input [11:3] lsu_va_m; | |
82 | input sr_inst_e; | |
83 | input pr_inst_e; | |
84 | input hpr_inst_e; | |
85 | input sr_inst_m; | |
86 | input pr_inst_m; | |
87 | input hpr_inst_m; | |
88 | input altspace_ldst_e; | |
89 | input altspace_ldst_m; | |
90 | input ld_inst_vld_m; | |
91 | ||
92 | output legal_asi_va_m; | |
93 | output asi_legal_e; | |
94 | output asr_legal_m; | |
95 | output asi_sync_m; | |
96 | output asi_internal_e ; | |
97 | output asi_rngf_m; | |
98 | output asi_indet_m; | |
99 | output lendian_asi_m; | |
100 | output asi_sz_byte_m; | |
101 | output asi_sz_hw_m; | |
102 | output pst_asi_m; | |
103 | output asi_pst8_m; | |
104 | output asi_pst16_m; | |
105 | output asi_pst32_m; | |
106 | output asi_read_only_m; | |
107 | output asi_write_only_m; | |
108 | output quad_asi_m ; | |
109 | output binit_quad_asi_m ; | |
110 | output primary_asi_e ; | |
111 | output secondary_asi_e ; | |
112 | output real_asi_e; | |
113 | output as_if_user_asi_e ; | |
114 | output as_if_priv_asi_e ; | |
115 | output atomic_asi_m ; | |
116 | output blk_asi_e ; | |
117 | output nofault_asi_m ; | |
118 | output asi_iomap_m ; | |
119 | output asi_no_va_check_m ; | |
120 | ||
121 | // CMP registers that reside off-chip and require IO mapping | |
122 | assign asi_iomap_m = altspace_ldst_m & ( | |
123 | (asi_m[7:0] == 8'h41) | // CMP registers | |
124 | (asi_m[7:0] == 8'h73) | // ASI_SWVR_UDB_INTR_W | |
125 | (asi_m[7:0] == 8'h45 & lsu_va_m[4]) // SOC debug registers | |
126 | ); | |
127 | ||
128 | // Quad (These are duplicated - they can be shared) | |
129 | assign binit_quad_asi_m = altspace_ldst_m & ( | |
130 | (asi_m[7:0] == 8'h27) | // asi_nucleus_blk_init_st_quad_ldd | |
131 | (asi_m[7:0] == 8'h2F) | // asi_nucleus_blk_init_st_quad_ldd_little | |
132 | (asi_m[7:0] == 8'h22) | // asi_as_if_user_primary_quad_ldd (blk-init) | |
133 | (asi_m[7:0] == 8'h2A) | // asi_as_if_user_primary_quad_ldd_little (blk-init) | |
134 | (asi_m[7:0] == 8'h23) | // asi_as_if_user_secondary_quad_ldd (blk-init) | |
135 | (asi_m[7:0] == 8'h2B) | // asi_as_if_user_secondary_quad_ldd_little (blk-init) | |
136 | (asi_m[7:0] == 8'hE2) | // asi_primary_quad_ldd (blk-init) | |
137 | (asi_m[7:0] == 8'hEA) | // asi_primary_quad_ldd_little (blk-init) | |
138 | (asi_m[7:0] == 8'hE3) | // asi_secondary_quad_ldd (blk-init) | |
139 | (asi_m[7:0] == 8'hEB) // asi_secondary_quad_ldd_little (blk-init) | |
140 | ); | |
141 | ||
142 | assign quad_asi_m = altspace_ldst_m & ( | |
143 | binit_quad_asi_m | // blk-init quad asi | |
144 | (asi_m[7:0] == 8'h26) | // asi_quad_ldd_real | |
145 | (asi_m[7:0] == 8'h2E) | // asi_quad_ldd_real_little | |
146 | (asi_m[7:0] == 8'h24) | // asi_nucleus_quad_ldd | |
147 | (asi_m[7:0] == 8'h2C) // asi_nucleus_quad_ldd_little | |
148 | ); | |
149 | ||
150 | // Legal ASI's | |
151 | assign asi_legal_e = (!asi_e[7]&!asi_e[6]&asi_e[4]&asi_e[2]&asi_e[1]&!asi_e[0]) | ( | |
152 | asi_e[7]&asi_e[6]&!asi_e[3]&!asi_e[2]&!asi_e[1]) | (!asi_e[7] | |
153 | &asi_e[6]&!asi_e[5]&!asi_e[3]&asi_e[0]) | (!asi_e[7]&asi_e[6] | |
154 | &!asi_e[5]&asi_e[3]&!asi_e[0]) | (!asi_e[7]&asi_e[5]&!asi_e[4] | |
155 | &!asi_e[3]&asi_e[2]&asi_e[1]) | (!asi_e[7]&asi_e[6]&!asi_e[3] | |
156 | &!asi_e[2]&asi_e[1]&asi_e[0]) | (!asi_e[7]&!asi_e[6]&!asi_e[4] | |
157 | &asi_e[2]&!asi_e[1]&!asi_e[0]) | (asi_e[6]&!asi_e[5]&!asi_e[2] | |
158 | &asi_e[1]&!asi_e[0]) | (asi_e[6]&!asi_e[5]&!asi_e[2]&!asi_e[1] | |
159 | &asi_e[0]) | (asi_e[6]&!asi_e[5]&asi_e[4]&!asi_e[2]) | (!asi_e[7] | |
160 | &!asi_e[6]&asi_e[5]&!asi_e[4]&asi_e[1]) | (!asi_e[7]&!asi_e[6] | |
161 | &asi_e[5]&!asi_e[4]&!asi_e[3]) | (asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[2] | |
162 | &!asi_e[1]) | (asi_e[7]&asi_e[6]&!asi_e[4]&!asi_e[2]&asi_e[1]) | ( | |
163 | !asi_e[7]&!asi_e[6]&asi_e[4]&!asi_e[2]&!asi_e[1]) | (!asi_e[7] | |
164 | &!asi_e[5]&asi_e[4]&asi_e[2]) | (asi_e[7]&!asi_e[5]&!asi_e[4] | |
165 | &!asi_e[2]) | (asi_e[7]&asi_e[6]&!asi_e[5]&!asi_e[4]&!asi_e[1]) | ( | |
166 | !asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[3]&asi_e[2]&!asi_e[1]&!asi_e[0]) | ( | |
167 | !asi_e[7]&asi_e[6]&asi_e[4]&!asi_e[3]&!asi_e[2]&asi_e[1]) | ( | |
168 | !asi_e[7]&asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]) | (!altspace_ldst_e); | |
169 | ||
170 | ||
171 | assign asr_legal_m = (hpr_inst_m&asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]) | ( | |
172 | !asi_m[4]&!asi_m[3]&!asi_m[2]&!asi_m[1]&!asi_m[0]) | (sr_inst_m | |
173 | &asi_m[4]&asi_m[3]&!asi_m[2]&!asi_m[0]) | (!sr_inst_m&!hpr_inst_m | |
174 | &!asi_m[4]&!asi_m[2]) | (!sr_inst_m&!hpr_inst_m&!asi_m[4]&!asi_m[3]) | ( | |
175 | sr_inst_m&!asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]&asi_m[0]) | ( | |
176 | !hpr_inst_m&!asi_m[4]&!asi_m[3]&!asi_m[2]&asi_m[1]) | (!sr_inst_m | |
177 | &!hpr_inst_m&!asi_m[4]&!asi_m[1]) | (sr_inst_m&!asi_m[3]&asi_m[2] | |
178 | &!asi_m[1]) | (!pr_inst_m&!hpr_inst_m&!asi_m[3]&!asi_m[2]&asi_m[1] | |
179 | &asi_m[0]) | (sr_inst_m&asi_m[4]&!asi_m[2]&!asi_m[1]) | (sr_inst_m | |
180 | &asi_m[4]&!asi_m[3]&asi_m[2]) | (!asi_m[4]&!asi_m[3]&!asi_m[2] | |
181 | &asi_m[1]&asi_m[0]) | (pr_inst_m&!asi_m[4]&!asi_m[0]) | (!hpr_inst_m | |
182 | &!asi_m[3]&!asi_m[2]&!asi_m[1]&!asi_m[0]) | (!sr_inst_m&!asi_m[4] | |
183 | &!asi_m[3]&!asi_m[1]&asi_m[0]) | (!asi_m[4]&!asi_m[3]&asi_m[2] | |
184 | &asi_m[1]&!asi_m[0]) | (!sr_inst_m&!pr_inst_m&!hpr_inst_m); | |
185 | ||
186 | // ASI Internal Registers | |
187 | assign asi_internal_e = (altspace_ldst_e&asi_e[5]&asi_e[4]&!asi_e[2]&asi_e[1]) | ( | |
188 | altspace_ldst_e&asi_e[6]&asi_e[5]&asi_e[2]) | (altspace_ldst_e | |
189 | &!asi_e[7]&!asi_e[4]&!asi_e[1]&asi_e[0]) | (altspace_ldst_e&asi_e[6] | |
190 | &asi_e[4]&asi_e[2]) | (altspace_ldst_e&asi_e[6]&asi_e[5]&!asi_e[4] | |
191 | &asi_e[3]&!asi_e[1]) | (altspace_ldst_e&!asi_e[6]&asi_e[4]&!asi_e[2] | |
192 | &asi_e[1]) | (altspace_ldst_e&!asi_e[7]&!asi_e[5]&!asi_e[4]&asi_e[1]) | ( | |
193 | altspace_ldst_e&!asi_e[7]&!asi_e[4]&!asi_e[2]&!asi_e[1]) | ( | |
194 | altspace_ldst_e&asi_e[5]&asi_e[4]&asi_e[1]&asi_e[0]) | ( | |
195 | altspace_ldst_e&asi_e[6]&asi_e[2]&asi_e[1]) | (hpr_inst_e) | ( | |
196 | sr_inst_e) | (pr_inst_e) | (altspace_ldst_e&asi_e[7]&!asi_e[6] | |
197 | &asi_e[5]) | (altspace_ldst_e&!asi_e[7]&asi_e[6]) | (altspace_ldst_e | |
198 | &asi_e[7]&!asi_e[6]&asi_e[4]) | (altspace_ldst_e&asi_e[7]&!asi_e[6] | |
199 | &asi_e[2]) | (altspace_ldst_e&asi_e[5]&asi_e[4]&asi_e[2]&!asi_e[1]); | |
200 | ||
201 | ||
202 | // Diferentiate between fast and slow ring. | |
203 | assign asi_rngf_m = (sr_inst_m&asi_m[4]&asi_m[2]) | (altspace_ldst_m&asi_m[3] | |
204 | &asi_m[1]&asi_m[0]) | (altspace_ldst_m&!asi_m[3]&!asi_m[2]&!asi_m[1] | |
205 | &asi_m[0]) | (altspace_ldst_m&asi_m[5]&!asi_m[1]) | (altspace_ldst_m | |
206 | &!asi_m[4]&!asi_m[2]&asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[2] | |
207 | &!asi_m[1]&!asi_m[0]) | (altspace_ldst_m&!asi_m[4]&asi_m[2]&!asi_m[1]) | ( | |
208 | hpr_inst_m) | (altspace_ldst_m&asi_m[4]&!asi_m[2]&!asi_m[0]) | ( | |
209 | sr_inst_m&asi_m[3]&!asi_m[1]) | (pr_inst_m&!asi_m[2]&!asi_m[1] | |
210 | &!asi_m[0]) | (altspace_ldst_m&asi_m[4]&asi_m[3]) | (pr_inst_m | |
211 | &!asi_m[3]) | (altspace_ldst_m&asi_m[3]&!asi_m[2]&asi_m[1]) | ( | |
212 | sr_inst_m&!asi_m[4]&asi_m[0]) | (sr_inst_m&asi_m[2]&!asi_m[1]) | ( | |
213 | altspace_ldst_m&asi_m[4]&asi_m[2]&asi_m[1]&asi_m[0]); | |
214 | ||
215 | ||
216 | assign indet_m = (altspace_ldst_m&!asi_m[7]&asi_m[4]&asi_m[3]&!asi_m[2] | |
217 | &asi_m[1]) | (altspace_ldst_m&asi_m[6]&asi_m[4]&!asi_m[3]&asi_m[2] | |
218 | &!asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[4]&!asi_m[3] | |
219 | &asi_m[2]&asi_m[1]) | (altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4] | |
220 | &asi_m[3]&!asi_m[2]) | (altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[5] | |
221 | &asi_m[4]&!asi_m[2]&asi_m[0]) | (pr_inst_m&~ld_inst_vld_m&asi_m[3]&!asi_m[2] | |
222 | &!asi_m[1]&asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[3]&asi_m[2] | |
223 | &asi_m[1]&!asi_m[0]); | |
224 | ||
225 | // ASI=0x40 / VA=0x30 and 0xA0 needs to be indeterminate as well | |
226 | assign asi_indet_m = indet_m | (altspace_ldst_m & (asi_m[7:0] == 8'h40) & | |
227 | ((lsu_va_m[7:5] == 3'b101) | (lsu_va_m[5:4] == 2'b11))); | |
228 | ||
229 | // ASIs which sync on writes | |
230 | assign asi_sync_m = (altspace_ldst_m&!asi_m[7]&asi_m[6]&asi_m[3]&!asi_m[0]) | ( | |
231 | altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[3]&asi_m[1]) | ( | |
232 | altspace_ldst_m&!asi_m[7]&!asi_m[4]&!asi_m[1]&asi_m[0]) | ( | |
233 | hpr_inst_m) | (sr_inst_m) | (pr_inst_m) | (altspace_ldst_m&!asi_m[7] | |
234 | &asi_m[6]&asi_m[4]); | |
235 | ||
236 | // Little Endian | |
237 | assign lendian_asi_m = (altspace_ldst_m&!asi_m[6]&asi_m[3]) | (altspace_ldst_m | |
238 | &asi_m[7]&asi_m[3]); | |
239 | ||
240 | // Size overrides for partial and short store ASIs | |
241 | assign asi_sz_byte_m = (altspace_ldst_m&asi_m[7]&!asi_m[5]&asi_m[4]&!asi_m[1]); | |
242 | ||
243 | assign asi_sz_hw_m = (altspace_ldst_m&asi_m[7]&asi_m[4]&asi_m[1]); | |
244 | ||
245 | // Partial Store ASIs | |
246 | assign pst_asi_m = altspace_ldst_m & (asi_m[7:4] == 4'hc); | |
247 | ||
248 | assign asi_pst8_m = (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4] | |
249 | &!asi_m[2]&!asi_m[1]); | |
250 | assign asi_pst16_m = (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4] | |
251 | &asi_m[1]); | |
252 | assign asi_pst32_m = (altspace_ldst_m&asi_m[7]&asi_m[2]); | |
253 | ||
254 | // Block ASI's | |
255 | assign blk_asi_e = (altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]) | ( | |
256 | altspace_ldst_e&asi_e[7]&asi_e[5]&!asi_e[1]); | |
257 | ||
258 | // Atomic asi | |
259 | assign atomic_asi_m = (!asi_m[6]&!asi_m[5]&!asi_m[2]&!asi_m[1]) | (!asi_m[6] | |
260 | &asi_m[5]&asi_m[4]) | (!asi_m[6]&!asi_m[5]&!asi_m[1]&!asi_m[0]) | ( | |
261 | !altspace_ldst_m); | |
262 | ||
263 | // Context selection | |
264 | assign primary_asi_e = (asi_e[6]&!asi_e[0]) | (!asi_e[5]&asi_e[1]&!asi_e[0]) | ( | |
265 | !asi_e[2]&!asi_e[0]) | (!altspace_ldst_e); | |
266 | ||
267 | assign secondary_asi_e = (altspace_ldst_e&!asi_e[5]&asi_e[0]) | ( | |
268 | altspace_ldst_e&!asi_e[2]&asi_e[0]); | |
269 | ||
270 | assign real_asi_e = (altspace_ldst_e&!asi_e[6]&!asi_e[4]&asi_e[2]&asi_e[1] | |
271 | &!asi_e[0]) | (altspace_ldst_e&!asi_e[6]&asi_e[4]&asi_e[2]&!asi_e[1]); | |
272 | ||
273 | assign as_if_user_asi_e = (altspace_ldst_e&!asi_e[6]&asi_e[5]&!asi_e[2]&asi_e[1]) | ( | |
274 | altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[4]&!asi_e[2]) | ( | |
275 | altspace_ldst_e&!asi_e[6]&!asi_e[5]&asi_e[2]&asi_e[1]); | |
276 | ||
277 | assign as_if_priv_asi_e = (altspace_ldst_e&!asi_e[6]&asi_e[5]&asi_e[4]); | |
278 | ||
279 | // No Fault | |
280 | assign nofault_asi_m = (altspace_ldst_m&asi_m[7]&!asi_m[6]&asi_m[1]); | |
281 | ||
282 | // Read and write only ASI's | |
283 | assign asi_read_only_m = (altspace_ldst_m&asi_m[5]&asi_m[4]&asi_m[2]&!asi_m[1]) | ( | |
284 | altspace_ldst_m&asi_m[7]&!asi_m[6]&asi_m[1]) | (altspace_ldst_m | |
285 | &!asi_m[7]&asi_m[4]&asi_m[3]&!asi_m[2]&asi_m[1]) | (altspace_ldst_m | |
286 | &!asi_m[7]&asi_m[6]&!asi_m[5]&asi_m[4]&!asi_m[2]&asi_m[0]) | ( | |
287 | altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4]&asi_m[3]&!asi_m[2]) | ( | |
288 | altspace_ldst_m&!asi_m[7]&asi_m[6]&asi_m[5]&!asi_m[4]&!asi_m[2]) | ( | |
289 | altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1]&!asi_m[0]); | |
290 | ||
291 | assign asi_write_only_m = (altspace_ldst_m&asi_m[5]&asi_m[4]&asi_m[1]&asi_m[0]) | ( | |
292 | altspace_ldst_m&asi_m[6]&asi_m[5]&!asi_m[4]&!asi_m[1]) | ( | |
293 | altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1]&asi_m[0]) | ( | |
294 | altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[3]&asi_m[2]&!asi_m[1] | |
295 | &!asi_m[0]) | (altspace_ldst_m&asi_m[7]&asi_m[6]&!asi_m[5]&!asi_m[4]); | |
296 | ||
297 | ||
298 | // ASI's which do not require VA checking | |
299 | assign asi_no_va_check_m = (altspace_ldst_m&asi_m[6]&asi_m[4]&asi_m[2]&asi_m[1] | |
300 | &asi_m[0]) | (altspace_ldst_m&asi_m[6]&!asi_m[4]&!asi_m[3]&asi_m[2] | |
301 | &asi_m[1]) | (altspace_ldst_m&!asi_m[7]&!asi_m[5]&!asi_m[4]&asi_m[3] | |
302 | &!asi_m[2]) | (altspace_ldst_m&!asi_m[7]&asi_m[6]&!asi_m[5]&asi_m[4] | |
303 | &!asi_m[2]&asi_m[0]); | |
304 | ||
305 | // Valid ASI/VA combinations | |
306 | assign legal_asi_va_m = (!asi_m[6]&asi_m[2]&!lsu_va_m[11]&!lsu_va_m[10] | |
307 | &lsu_va_m[9]&lsu_va_m[8]&lsu_va_m[7]&lsu_va_m[6]) | (!asi_m[6] | |
308 | &!asi_m[2]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
309 | &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&lsu_va_m[3]) | ( | |
310 | asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
311 | &!lsu_va_m[9]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4] | |
312 | &!lsu_va_m[3]) | (asi_m[5]&!asi_m[4]&asi_m[1]&!lsu_va_m[11] | |
313 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6] | |
314 | &!lsu_va_m[5]&!lsu_va_m[3]) | (asi_m[2]&!asi_m[0]&!lsu_va_m[11] | |
315 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6] | |
316 | &!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (asi_m[5]&!asi_m[4] | |
317 | &!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8] | |
318 | &!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[4]) | (asi_m[5]&!asi_m[0] | |
319 | &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7] | |
320 | &!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | (!asi_m[5] | |
321 | &!asi_m[4]&!asi_m[2]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
322 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[4]&!lsu_va_m[3]) | ( | |
323 | !asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
324 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5] | |
325 | &lsu_va_m[4]) | (!asi_m[5]&asi_m[4]&asi_m[2]&!lsu_va_m[11] | |
326 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5] | |
327 | &!lsu_va_m[4]&!lsu_va_m[3]) | (!asi_m[4]&!asi_m[2]&!asi_m[0] | |
328 | &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7] | |
329 | &!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&lsu_va_m[3]) | (asi_m[4] | |
330 | &asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
331 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]) | (!asi_m[4] | |
332 | &!asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
333 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4] | |
334 | &!lsu_va_m[3]) | (asi_m[4]&asi_m[3]&asi_m[1]&!lsu_va_m[11] | |
335 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6] | |
336 | &!lsu_va_m[3]) | (!asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0]&!lsu_va_m[11] | |
337 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[6] | |
338 | &lsu_va_m[5]&!lsu_va_m[4]) | (!asi_m[5]&!asi_m[2]&!asi_m[1]&asi_m[0] | |
339 | &!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7] | |
340 | &lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | (!asi_m[5]&!asi_m[3] | |
341 | &asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
342 | &!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[6]) | (!asi_m[5]&!asi_m[3] | |
343 | &asi_m[2]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
344 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[3]) | ( | |
345 | asi_m[4]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
346 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[4]&lsu_va_m[3]) | ( | |
347 | asi_m[3]&!asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
348 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]&!lsu_va_m[3]) | ( | |
349 | !asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
350 | &!lsu_va_m[9]&!lsu_va_m[8]&lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]) | ( | |
351 | !asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
352 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[5]) | (asi_m[4] | |
353 | &!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
354 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&lsu_va_m[4]) | ( | |
355 | !asi_m[5]&!asi_m[4]&!asi_m[2]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11] | |
356 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[5]) | ( | |
357 | !asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
358 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4] | |
359 | &!lsu_va_m[3]) | (!asi_m[5]&!asi_m[3]&asi_m[2]&!asi_m[0]&!lsu_va_m[11] | |
360 | &!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&lsu_va_m[4]) | ( | |
361 | !asi_m[5]&!asi_m[4]&!asi_m[1]&!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10] | |
362 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[4]) | ( | |
363 | !asi_m[5]&!asi_m[4]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10] | |
364 | &!lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[3]) | ( | |
365 | asi_m[6]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
366 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4] | |
367 | &!lsu_va_m[3]) | (!asi_m[3]&asi_m[2]&asi_m[1]&!lsu_va_m[11] | |
368 | &!lsu_va_m[9]) | (asi_m[4]&!asi_m[1]&asi_m[0]&!lsu_va_m[11] | |
369 | &!lsu_va_m[9]) | (asi_m[4]&!asi_m[2]&!asi_m[1]&asi_m[0]) | (asi_m[3] | |
370 | &!asi_m[2]&!asi_m[1]&asi_m[0]) | (!asi_m[4]&!asi_m[3]&asi_m[2] | |
371 | &asi_m[1]) | (!asi_m[5]&asi_m[4]&asi_m[1]&asi_m[0]) | (asi_m[2] | |
372 | &asi_m[1]&asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
373 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]) | (!asi_m[4]&!asi_m[1] | |
374 | &!asi_m[0]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9]&!lsu_va_m[8] | |
375 | &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]) | (!asi_m[5]&asi_m[4] | |
376 | &!asi_m[3]&!asi_m[2]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9] | |
377 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&!lsu_va_m[4] | |
378 | &!lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&!asi_m[2]&asi_m[1] | |
379 | &!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9]&!lsu_va_m[8]&!lsu_va_m[7] | |
380 | &!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[3]) | (!asi_m[5]&asi_m[4] | |
381 | &!asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
382 | &lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&lsu_va_m[5]&!lsu_va_m[4] | |
383 | &!lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&asi_m[1]&!lsu_va_m[11] | |
384 | &!lsu_va_m[10]&!lsu_va_m[9]&lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6] | |
385 | &!lsu_va_m[5]&lsu_va_m[3]) | (!asi_m[5]&asi_m[4]&!asi_m[3]&!asi_m[2] | |
386 | &asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&lsu_va_m[9]&!lsu_va_m[8] | |
387 | &!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | (!asi_m[5] | |
388 | &asi_m[4]&!asi_m[3]&asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
389 | &lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[6]&!lsu_va_m[5]&lsu_va_m[4]) | ( | |
390 | asi_m[3]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
391 | &!lsu_va_m[8]&!lsu_va_m[6]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | ( | |
392 | asi_m[3]&!asi_m[2]&!asi_m[1]&!lsu_va_m[11]&!lsu_va_m[10]&!lsu_va_m[9] | |
393 | &!lsu_va_m[8]&!lsu_va_m[7]&!lsu_va_m[5]&!lsu_va_m[4]&!lsu_va_m[3]) | ( | |
394 | asi_m[4]&asi_m[3]&asi_m[2]&asi_m[1]&!lsu_va_m[11]) | (asi_m[4] | |
395 | &asi_m[3]&asi_m[0]&!lsu_va_m[11]) | (!asi_m[4]&asi_m[3]&!asi_m[2] | |
396 | &!asi_m[0]); | |
397 | ||
398 | ||
399 | supply0 vss; | |
400 | supply1 vdd; | |
401 | endmodule | |
402 |