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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_dcs_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_dcs_dp ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | wmr_scan_in, | |
39 | tcu_pce_ov, | |
40 | tcu_scan_en, | |
41 | spc_aclk_wmr, | |
42 | spc_aclk, | |
43 | spc_bclk, | |
44 | lb_scan_en_wmr, | |
45 | scan_out, | |
46 | wmr_scan_out, | |
47 | const_cpuid, | |
48 | dec_lsu_tid0_d, | |
49 | dec_lsu_tid1_d, | |
50 | dec_lsu_tg_d, | |
51 | dcc_ld_inst_unqual_e, | |
52 | dcc_ctxt_tid0_d, | |
53 | dcc_ctxt_tid1_d, | |
54 | dcc_ctxt_tg_d, | |
55 | dcc_tid_m, | |
56 | dcc_tid_b, | |
57 | dcc_asi_reload_sel, | |
58 | dcc_wr_wtchpt, | |
59 | dcc_wr_lsu_ctl_reg, | |
60 | dcc_wr_pwr_mgmt, | |
61 | dcc_rd_lsu_ctl_reg_b, | |
62 | dcc_rd_diag_reg_b, | |
63 | dcc_rd_core_id_b, | |
64 | dcc_rd_intr_id_b, | |
65 | dcc_rd_rhs_asi_b, | |
66 | dcc_rd_diag_dca_b, | |
67 | dcc_rd_error_inj_b, | |
68 | dcc_rd_pwr_mgmt_b, | |
69 | dcc_wr_error_inj_w, | |
70 | dcc_p0ctxt_rd_m, | |
71 | dcc_p1ctxt_rd_m, | |
72 | dcc_s0ctxt_rd_m, | |
73 | dcc_s1ctxt_rd_m, | |
74 | dcc_pid_rd_m, | |
75 | dcc_wtchpt_sel_m, | |
76 | dcc_wtchpt_rd_b, | |
77 | dcc_pctxt_sel_e, | |
78 | dcc_sctxt_sel_e, | |
79 | dcc_dcs_memref_e, | |
80 | dcc_direct_map, | |
81 | dcc_asi_store_b, | |
82 | dcc_asi_load_m, | |
83 | dcc_asi_load_b, | |
84 | lsu_ifu_direct_map, | |
85 | asc_wr_p0ctxt, | |
86 | asc_wr_p1ctxt, | |
87 | asc_wr_s0ctxt, | |
88 | asc_wr_s1ctxt, | |
89 | asc_wr_pid, | |
90 | asc_wrasi, | |
91 | tlu_asi_0, | |
92 | tlu_asi_1, | |
93 | tlu_lsu_clear_ctl_reg_, | |
94 | dca_rparity_b, | |
95 | sbd_st_data_b, | |
96 | tgd_ldxa_asi_data_b, | |
97 | asd_asi_data, | |
98 | lsu_va_m, | |
99 | lsu_va_b, | |
100 | dcs_asi_d, | |
101 | dcs_context0_e, | |
102 | dcs_context1_e, | |
103 | dcs_pid_e, | |
104 | dcs_ldxa_asi_data_w, | |
105 | dcs_watchpoint_m, | |
106 | dcs_dc_enable, | |
107 | dcs_wpt_mask_m, | |
108 | dcs_wpt_enable_m, | |
109 | dcs_wpt_mode_m, | |
110 | dcs_dmmu_enable_d, | |
111 | lsu_immu_enable, | |
112 | lsu_ic_enable, | |
113 | lsu_context_b, | |
114 | lsu_asi_error_inject, | |
115 | lsu_asi_pwr_mgmt, | |
116 | dcs_memref_m); | |
117 | wire stop; | |
118 | wire se; | |
119 | wire pce_ov; | |
120 | wire siclk; | |
121 | wire soclk; | |
122 | wire siclk_wmr; | |
123 | wire scan_en_wmr; | |
124 | wire dff_in_data_scanin; | |
125 | wire dff_in_data_scanout; | |
126 | wire [47:0] wsr_data_w; | |
127 | wire [12:0] asi_data_in; | |
128 | wire [7:0] reload_asi_0; | |
129 | wire [7:0] asi_state0; | |
130 | wire [7:0] asi_state0_in; | |
131 | wire [7:0] asi_state1; | |
132 | wire [7:0] asi_state1_in; | |
133 | wire [7:0] asi_state2; | |
134 | wire [7:0] asi_state2_in; | |
135 | wire [7:0] asi_state3; | |
136 | wire [7:0] asi_state3_in; | |
137 | wire [7:0] reload_asi_1; | |
138 | wire [7:0] asi_state4; | |
139 | wire [7:0] asi_state4_in; | |
140 | wire [7:0] asi_state5; | |
141 | wire [7:0] asi_state5_in; | |
142 | wire [7:0] asi_state6; | |
143 | wire [7:0] asi_state6_in; | |
144 | wire [7:0] asi_state7; | |
145 | wire [7:0] asi_state7_in; | |
146 | wire [7:0] wr_p1ctxt_; | |
147 | wire [7:0] wr_s1ctxt_; | |
148 | wire [7:0] wr_p0ctxt_; | |
149 | wire [7:0] wr_s0ctxt_; | |
150 | wire [7:0] wr_pid_; | |
151 | wire [7:0] wr_p1ctxt; | |
152 | wire [7:0] wr_s1ctxt; | |
153 | wire [7:0] wr_p0ctxt; | |
154 | wire [7:0] wr_s0ctxt; | |
155 | wire [7:0] wr_pid; | |
156 | wire [12:0] p0ctxt_0; | |
157 | wire [12:0] p0ctxt_0_in; | |
158 | wire [12:0] p0ctxt_1; | |
159 | wire [12:0] p0ctxt_1_in; | |
160 | wire [12:0] p0ctxt_2; | |
161 | wire [12:0] p0ctxt_2_in; | |
162 | wire [12:0] p0ctxt_3; | |
163 | wire [12:0] p0ctxt_3_in; | |
164 | wire [12:0] p0ctxt_4; | |
165 | wire [12:0] p0ctxt_4_in; | |
166 | wire [12:0] p0ctxt_5; | |
167 | wire [12:0] p0ctxt_5_in; | |
168 | wire [12:0] p0ctxt_6; | |
169 | wire [12:0] p0ctxt_6_in; | |
170 | wire [12:0] p0ctxt_7; | |
171 | wire [12:0] p0ctxt_7_in; | |
172 | wire [12:0] p1ctxt_0; | |
173 | wire [12:0] p1ctxt_0_in; | |
174 | wire [12:0] p1ctxt_1; | |
175 | wire [12:0] p1ctxt_1_in; | |
176 | wire [12:0] p1ctxt_2; | |
177 | wire [12:0] p1ctxt_2_in; | |
178 | wire [12:0] p1ctxt_3; | |
179 | wire [12:0] p1ctxt_3_in; | |
180 | wire [12:0] p1ctxt_4; | |
181 | wire [12:0] p1ctxt_4_in; | |
182 | wire [12:0] p1ctxt_5; | |
183 | wire [12:0] p1ctxt_5_in; | |
184 | wire [12:0] p1ctxt_6; | |
185 | wire [12:0] p1ctxt_6_in; | |
186 | wire [12:0] p1ctxt_7; | |
187 | wire [12:0] p1ctxt_7_in; | |
188 | wire [12:0] s0ctxt_0; | |
189 | wire [12:0] s0ctxt_0_in; | |
190 | wire [12:0] s0ctxt_1; | |
191 | wire [12:0] s0ctxt_1_in; | |
192 | wire [12:0] s0ctxt_2; | |
193 | wire [12:0] s0ctxt_2_in; | |
194 | wire [12:0] s0ctxt_3; | |
195 | wire [12:0] s0ctxt_3_in; | |
196 | wire [12:0] s0ctxt_4; | |
197 | wire [12:0] s0ctxt_4_in; | |
198 | wire [12:0] s0ctxt_5; | |
199 | wire [12:0] s0ctxt_5_in; | |
200 | wire [12:0] s0ctxt_6; | |
201 | wire [12:0] s0ctxt_6_in; | |
202 | wire [12:0] s0ctxt_7; | |
203 | wire [12:0] s0ctxt_7_in; | |
204 | wire [12:0] s1ctxt_0; | |
205 | wire [12:0] s1ctxt_0_in; | |
206 | wire [12:0] s1ctxt_1; | |
207 | wire [12:0] s1ctxt_1_in; | |
208 | wire [12:0] s1ctxt_2; | |
209 | wire [12:0] s1ctxt_2_in; | |
210 | wire [12:0] s1ctxt_3; | |
211 | wire [12:0] s1ctxt_3_in; | |
212 | wire [12:0] s1ctxt_4; | |
213 | wire [12:0] s1ctxt_4_in; | |
214 | wire [12:0] s1ctxt_5; | |
215 | wire [12:0] s1ctxt_5_in; | |
216 | wire [12:0] s1ctxt_6; | |
217 | wire [12:0] s1ctxt_6_in; | |
218 | wire [12:0] s1ctxt_7; | |
219 | wire [12:0] s1ctxt_7_in; | |
220 | wire [2:0] pid0; | |
221 | wire [2:0] pid0_in; | |
222 | wire [2:0] pid1; | |
223 | wire [2:0] pid1_in; | |
224 | wire [2:0] pid2; | |
225 | wire [2:0] pid2_in; | |
226 | wire [2:0] pid3; | |
227 | wire [2:0] pid3_in; | |
228 | wire [2:0] pid4; | |
229 | wire [2:0] pid4_in; | |
230 | wire [2:0] pid5; | |
231 | wire [2:0] pid5_in; | |
232 | wire [2:0] pid6; | |
233 | wire [2:0] pid6_in; | |
234 | wire [2:0] pid7; | |
235 | wire [2:0] pid7_in; | |
236 | wire dff_state0_wmr_scanin; | |
237 | wire dff_state0_wmr_scanout; | |
238 | wire [62:0] state0; | |
239 | wire dff_state1_wmr_scanin; | |
240 | wire dff_state1_wmr_scanout; | |
241 | wire [62:0] state1; | |
242 | wire dff_state2_wmr_scanin; | |
243 | wire dff_state2_wmr_scanout; | |
244 | wire [62:0] state2; | |
245 | wire dff_state3_wmr_scanin; | |
246 | wire dff_state3_wmr_scanout; | |
247 | wire [62:0] state3; | |
248 | wire dff_state4_wmr_scanin; | |
249 | wire dff_state4_wmr_scanout; | |
250 | wire [62:0] state4; | |
251 | wire dff_state5_wmr_scanin; | |
252 | wire dff_state5_wmr_scanout; | |
253 | wire [62:0] state5; | |
254 | wire dff_state6_wmr_scanin; | |
255 | wire dff_state6_wmr_scanout; | |
256 | wire [62:0] state6; | |
257 | wire dff_state7_wmr_scanin; | |
258 | wire dff_state7_wmr_scanout; | |
259 | wire [62:0] state7; | |
260 | wire [62:0] state_tg0; | |
261 | wire [62:0] state_tg1; | |
262 | wire [7:0] dmmu_enable; | |
263 | wire dmmu_enable_tg0; | |
264 | wire dmmu_enable_tg1; | |
265 | wire dff_mx_ctxt_scanin; | |
266 | wire dff_mx_ctxt_scanout; | |
267 | wire [12:0] dcs_p1ctxt_e; | |
268 | wire [12:0] dcs_s1ctxt_e; | |
269 | wire [12:0] dcs_p0ctxt_e; | |
270 | wire [12:0] dcs_s0ctxt_e; | |
271 | wire [12:0] context0_e; | |
272 | wire [12:0] context1_e; | |
273 | wire dff_context_m_scanin; | |
274 | wire dff_context_m_scanout; | |
275 | wire memref_m; | |
276 | wire [12:0] dcs_context0_m; | |
277 | wire dff_context_b_scanin; | |
278 | wire dff_context_b_scanout; | |
279 | wire [4:0] lsu_ctl_reg_m; | |
280 | wire [12:0] dcs_context0_b; | |
281 | wire [1:0] dcs_wpt_mode_b; | |
282 | wire [7:0] dcs_wpt_mask_b; | |
283 | wire [1:0] dcs_wpt_enable_b; | |
284 | wire [4:0] lsu_ctl_reg_b; | |
285 | wire dff_state_m_scanin; | |
286 | wire dff_state_m_scanout; | |
287 | wire [2:0] dcs_pid_m; | |
288 | wire [12:0] dcs_p1ctxt_m; | |
289 | wire [12:0] dcs_s1ctxt_m; | |
290 | wire [12:0] dcs_p0ctxt_m; | |
291 | wire [12:0] dcs_s0ctxt_m; | |
292 | wire [12:0] ldxa_asi_data_m; | |
293 | wire dff_stg_b_scanin; | |
294 | wire dff_stg_b_scanout; | |
295 | wire [47:3] watchpoint_m; | |
296 | wire [46:0] stg_b; | |
297 | wire [12:0] ldxa_asi_data_b; | |
298 | wire [47:3] watchpoint_b; | |
299 | wire [5:0] core_id; | |
300 | wire [5:0] max_core_id; | |
301 | wire [5:0] max_strand_id; | |
302 | wire [63:0] ldxa_asi_data_b_2; | |
303 | wire dff_asi_w_scanin; | |
304 | wire dff_asi_w_scanout; | |
305 | wire dff_watchpoint_0_wmr_scanin; | |
306 | wire dff_watchpoint_0_wmr_scanout; | |
307 | wire [47:3] watchpoint0; | |
308 | wire dff_watchpoint_1_wmr_scanin; | |
309 | wire dff_watchpoint_1_wmr_scanout; | |
310 | wire [47:3] watchpoint1; | |
311 | wire dff_watchpoint_2_wmr_scanin; | |
312 | wire dff_watchpoint_2_wmr_scanout; | |
313 | wire [47:3] watchpoint2; | |
314 | wire dff_watchpoint_3_wmr_scanin; | |
315 | wire dff_watchpoint_3_wmr_scanout; | |
316 | wire [47:3] watchpoint3; | |
317 | wire dff_watchpoint_4_wmr_scanin; | |
318 | wire dff_watchpoint_4_wmr_scanout; | |
319 | wire [47:3] watchpoint4; | |
320 | wire dff_watchpoint_5_wmr_scanin; | |
321 | wire dff_watchpoint_5_wmr_scanout; | |
322 | wire [47:3] watchpoint5; | |
323 | wire dff_watchpoint_6_wmr_scanin; | |
324 | wire dff_watchpoint_6_wmr_scanout; | |
325 | wire [47:3] watchpoint6; | |
326 | wire dff_watchpoint_7_wmr_scanin; | |
327 | wire dff_watchpoint_7_wmr_scanout; | |
328 | wire [47:3] watchpoint7; | |
329 | wire [47:3] watchpoint_mx_m; | |
330 | wire [16:0] ctl_reg0_in; | |
331 | wire [16:0] ctl_reg1_in; | |
332 | wire [16:0] ctl_reg2_in; | |
333 | wire [16:0] ctl_reg3_in; | |
334 | wire [16:0] ctl_reg4_in; | |
335 | wire [16:0] ctl_reg5_in; | |
336 | wire [16:0] ctl_reg6_in; | |
337 | wire [16:0] ctl_reg7_in; | |
338 | wire dff_lsu_ctl_0_scanin; | |
339 | wire dff_lsu_ctl_0_scanout; | |
340 | wire [1:0] wpt_mode_0; | |
341 | wire [7:0] wpt_mask_0; | |
342 | wire [1:0] wpt_enable_0; | |
343 | wire [7:0] spec_enable; | |
344 | wire [7:0] immu_enable; | |
345 | wire [7:0] dc_enable; | |
346 | wire [7:0] ic_enable; | |
347 | wire dff_lsu_ctl_1_scanin; | |
348 | wire dff_lsu_ctl_1_scanout; | |
349 | wire [1:0] wpt_mode_1; | |
350 | wire [7:0] wpt_mask_1; | |
351 | wire [1:0] wpt_enable_1; | |
352 | wire dff_lsu_ctl_2_scanin; | |
353 | wire dff_lsu_ctl_2_scanout; | |
354 | wire [1:0] wpt_mode_2; | |
355 | wire [7:0] wpt_mask_2; | |
356 | wire [1:0] wpt_enable_2; | |
357 | wire dff_lsu_ctl_3_scanin; | |
358 | wire dff_lsu_ctl_3_scanout; | |
359 | wire [1:0] wpt_mode_3; | |
360 | wire [7:0] wpt_mask_3; | |
361 | wire [1:0] wpt_enable_3; | |
362 | wire dff_lsu_ctl_4_scanin; | |
363 | wire dff_lsu_ctl_4_scanout; | |
364 | wire [1:0] wpt_mode_4; | |
365 | wire [7:0] wpt_mask_4; | |
366 | wire [1:0] wpt_enable_4; | |
367 | wire dff_lsu_ctl_5_scanin; | |
368 | wire dff_lsu_ctl_5_scanout; | |
369 | wire [1:0] wpt_mode_5; | |
370 | wire [7:0] wpt_mask_5; | |
371 | wire [1:0] wpt_enable_5; | |
372 | wire dff_lsu_ctl_6_scanin; | |
373 | wire dff_lsu_ctl_6_scanout; | |
374 | wire [1:0] wpt_mode_6; | |
375 | wire [7:0] wpt_mask_6; | |
376 | wire [1:0] wpt_enable_6; | |
377 | wire dff_lsu_ctl_7_scanin; | |
378 | wire dff_lsu_ctl_7_scanout; | |
379 | wire [1:0] wpt_mode_7; | |
380 | wire [7:0] wpt_mask_7; | |
381 | wire [1:0] wpt_enable_7; | |
382 | wire [16:0] lsu_ctl_mx; | |
383 | wire dff_error_inject_scanin; | |
384 | wire dff_error_inject_scanout; | |
385 | wire [31:0] asi_error_inject; | |
386 | wire dff_pwr_mgmt_scanin; | |
387 | wire dff_pwr_mgmt_scanout; | |
388 | wire [15:0] asi_pwr_mgmt; | |
389 | wire dff_va_b_scanin; | |
390 | wire dff_va_b_scanout; | |
391 | wire [20:0] va_b; | |
392 | ||
393 | ||
394 | input l2clk; | |
395 | input scan_in; | |
396 | input wmr_scan_in; | |
397 | input tcu_pce_ov; // scan signals | |
398 | input tcu_scan_en; | |
399 | input spc_aclk_wmr; | |
400 | input spc_aclk; | |
401 | input spc_bclk; | |
402 | input lb_scan_en_wmr; | |
403 | output scan_out; | |
404 | output wmr_scan_out; | |
405 | ||
406 | input [2:0] const_cpuid; | |
407 | ||
408 | input [1:0] dec_lsu_tid0_d; | |
409 | input [1:0] dec_lsu_tid1_d; | |
410 | input dec_lsu_tg_d; | |
411 | ||
412 | input dcc_ld_inst_unqual_e; | |
413 | input [1:0] dcc_ctxt_tid0_d; | |
414 | input [1:0] dcc_ctxt_tid1_d; | |
415 | input dcc_ctxt_tg_d; | |
416 | input [2:0] dcc_tid_m; | |
417 | input [2:0] dcc_tid_b; | |
418 | input [7:0] dcc_asi_reload_sel; | |
419 | input [7:0] dcc_wr_wtchpt; | |
420 | input [7:0] dcc_wr_lsu_ctl_reg; | |
421 | input dcc_wr_pwr_mgmt; | |
422 | input dcc_rd_lsu_ctl_reg_b; | |
423 | input dcc_rd_diag_reg_b; | |
424 | input dcc_rd_core_id_b; | |
425 | input dcc_rd_intr_id_b; | |
426 | input dcc_rd_rhs_asi_b; | |
427 | input dcc_rd_diag_dca_b; | |
428 | input dcc_rd_error_inj_b; | |
429 | input dcc_rd_pwr_mgmt_b; | |
430 | input dcc_wr_error_inj_w; | |
431 | input dcc_p0ctxt_rd_m; | |
432 | input dcc_p1ctxt_rd_m; | |
433 | input dcc_s0ctxt_rd_m; | |
434 | input dcc_s1ctxt_rd_m; | |
435 | input dcc_pid_rd_m; | |
436 | input dcc_wtchpt_sel_m; | |
437 | input dcc_wtchpt_rd_b; | |
438 | input dcc_pctxt_sel_e; | |
439 | input dcc_sctxt_sel_e; | |
440 | input dcc_dcs_memref_e; | |
441 | input dcc_direct_map; // diag read only | |
442 | input dcc_asi_store_b; | |
443 | input dcc_asi_load_m; | |
444 | input dcc_asi_load_b; | |
445 | input lsu_ifu_direct_map; // diag read only | |
446 | ||
447 | input [7:0] asc_wr_p0ctxt; | |
448 | input [7:0] asc_wr_p1ctxt; | |
449 | input [7:0] asc_wr_s0ctxt; | |
450 | input [7:0] asc_wr_s1ctxt; | |
451 | input [7:0] asc_wr_pid; | |
452 | input [7:0] asc_wrasi; | |
453 | ||
454 | input [7:0] tlu_asi_0; // ASI reload data | |
455 | input [7:0] tlu_asi_1; | |
456 | input [7:0] tlu_lsu_clear_ctl_reg_; | |
457 | ||
458 | input [7:0] dca_rparity_b; | |
459 | ||
460 | input [47:0] sbd_st_data_b; | |
461 | ||
462 | input [63:0] tgd_ldxa_asi_data_b; | |
463 | ||
464 | input [12:0] asd_asi_data; | |
465 | ||
466 | input [20:0] lsu_va_m; | |
467 | output [20:0] lsu_va_b; | |
468 | ||
469 | output [7:0] dcs_asi_d; | |
470 | ||
471 | output [12:0] dcs_context0_e; | |
472 | output [12:0] dcs_context1_e; | |
473 | output [2:0] dcs_pid_e; | |
474 | output [63:0] dcs_ldxa_asi_data_w; | |
475 | output [47:3] dcs_watchpoint_m; | |
476 | output [7:0] dcs_dc_enable; | |
477 | output [7:0] dcs_wpt_mask_m; | |
478 | output [1:0] dcs_wpt_enable_m; | |
479 | output [1:0] dcs_wpt_mode_m; | |
480 | output dcs_dmmu_enable_d; | |
481 | ||
482 | output [7:0] lsu_immu_enable; | |
483 | output [7:0] lsu_ic_enable; | |
484 | output [12:0] lsu_context_b; | |
485 | output [31:0] lsu_asi_error_inject; | |
486 | output [15:0] lsu_asi_pwr_mgmt; | |
487 | output dcs_memref_m; | |
488 | ||
489 | // scan renames | |
490 | assign stop = 1'b0; | |
491 | // end scan | |
492 | ||
493 | lsu_dcs_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_6 test_rep0 ( | |
494 | .din ({tcu_scan_en,tcu_pce_ov,spc_aclk,spc_bclk,spc_aclk_wmr,lb_scan_en_wmr}), | |
495 | .dout({se,pce_ov,siclk,soclk,siclk_wmr,scan_en_wmr}) | |
496 | ); | |
497 | ||
498 | lsu_dcs_dp_msff_macro__left_16__stack_64c__width_48 dff_in_data ( | |
499 | .scan_in(dff_in_data_scanin), | |
500 | .scan_out(dff_in_data_scanout), | |
501 | .din (sbd_st_data_b[47:0]), | |
502 | .dout (wsr_data_w[47:0]), | |
503 | .clk (l2clk), | |
504 | .en (dcc_asi_store_b), | |
505 | .se(se), | |
506 | .siclk(siclk), | |
507 | .soclk(soclk), | |
508 | .pce_ov(pce_ov), | |
509 | .stop(stop) | |
510 | ); | |
511 | ||
512 | // These nets have a high internal load so buffer them off. | |
513 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 asi_data_buf ( | |
514 | .din (asd_asi_data[12:0]), | |
515 | .dout (asi_data_in[12:0]) | |
516 | ); | |
517 | ||
518 | //////////////////////////////////////////////////////////////////////////////// | |
519 | // ASI muxes | |
520 | ||
521 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state0 ( | |
522 | .din0 (reload_asi_0[7:0]), | |
523 | .din1 (asi_data_in[7:0]), | |
524 | .din2 (asi_state0[7:0]), | |
525 | .sel0 (dcc_asi_reload_sel[0]), | |
526 | .sel1 (asc_wrasi[0]), | |
527 | .dout (asi_state0_in[7:0]) | |
528 | ); | |
529 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state1 ( | |
530 | .din0 (reload_asi_0[7:0]), | |
531 | .din1 (asi_data_in[7:0]), | |
532 | .din2 (asi_state1[7:0]), | |
533 | .sel0 (dcc_asi_reload_sel[1]), | |
534 | .sel1 (asc_wrasi[1]), | |
535 | .dout (asi_state1_in[7:0]) | |
536 | ); | |
537 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state2 ( | |
538 | .din0 (reload_asi_0[7:0]), | |
539 | .din1 (asi_data_in[7:0]), | |
540 | .din2 (asi_state2[7:0]), | |
541 | .sel0 (dcc_asi_reload_sel[2]), | |
542 | .sel1 (asc_wrasi[2]), | |
543 | .dout (asi_state2_in[7:0]) | |
544 | ); | |
545 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state3 ( | |
546 | .din0 (reload_asi_0[7:0]), | |
547 | .din1 (asi_data_in[7:0]), | |
548 | .din2 (asi_state3[7:0]), | |
549 | .sel0 (dcc_asi_reload_sel[3]), | |
550 | .sel1 (asc_wrasi[3]), | |
551 | .dout (asi_state3_in[7:0]) | |
552 | ); | |
553 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state4 ( | |
554 | .din0 (reload_asi_1[7:0]), | |
555 | .din1 (asi_data_in[7:0]), | |
556 | .din2 (asi_state4[7:0]), | |
557 | .sel0 (dcc_asi_reload_sel[4]), | |
558 | .sel1 (asc_wrasi[4]), | |
559 | .dout (asi_state4_in[7:0]) | |
560 | ); | |
561 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state5 ( | |
562 | .din0 (reload_asi_1[7:0]), | |
563 | .din1 (asi_data_in[7:0]), | |
564 | .din2 (asi_state5[7:0]), | |
565 | .sel0 (dcc_asi_reload_sel[5]), | |
566 | .sel1 (asc_wrasi[5]), | |
567 | .dout (asi_state5_in[7:0]) | |
568 | ); | |
569 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state6 ( | |
570 | .din0 (reload_asi_1[7:0]), | |
571 | .din1 (asi_data_in[7:0]), | |
572 | .din2 (asi_state6[7:0]), | |
573 | .sel0 (dcc_asi_reload_sel[6]), | |
574 | .sel1 (asc_wrasi[6]), | |
575 | .dout (asi_state6_in[7:0]) | |
576 | ); | |
577 | lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 mx_asi_state7 ( | |
578 | .din0 (reload_asi_1[7:0]), | |
579 | .din1 (asi_data_in[7:0]), | |
580 | .din2 (asi_state7[7:0]), | |
581 | .sel0 (dcc_asi_reload_sel[7]), | |
582 | .sel1 (asc_wrasi[7]), | |
583 | .dout (asi_state7_in[7:0]) | |
584 | ); | |
585 | ||
586 | // Invert/buffer select lines for aomuxes | |
587 | lsu_dcs_dp_inv_macro__width_10 inv_sel0 ( | |
588 | .din ({asc_wr_p1ctxt [0],asc_wr_s1ctxt [0],asc_wr_p0ctxt [0],asc_wr_s0ctxt [0],asc_wr_pid [0], | |
589 | wr_p1ctxt_[0], wr_s1ctxt_[0], wr_p0ctxt_[0], wr_s0ctxt_[0], wr_pid_[0]}), | |
590 | .dout ({ wr_p1ctxt_[0], wr_s1ctxt_[0], wr_p0ctxt_[0], wr_s0ctxt_[0], wr_pid_[0], | |
591 | wr_p1ctxt [0], wr_s1ctxt [0], wr_p0ctxt [0], wr_s0ctxt [0], wr_pid[0]}) | |
592 | ); | |
593 | lsu_dcs_dp_inv_macro__width_10 inv_sel1 ( | |
594 | .din ({asc_wr_p1ctxt [1],asc_wr_s1ctxt [1],asc_wr_p0ctxt [1],asc_wr_s0ctxt [1],asc_wr_pid [1], | |
595 | wr_p1ctxt_[1], wr_s1ctxt_[1], wr_p0ctxt_[1], wr_s0ctxt_[1], wr_pid_[1]}), | |
596 | .dout ({ wr_p1ctxt_[1], wr_s1ctxt_[1], wr_p0ctxt_[1], wr_s0ctxt_[1], wr_pid_[1], | |
597 | wr_p1ctxt [1], wr_s1ctxt [1], wr_p0ctxt [1], wr_s0ctxt [1], wr_pid[1]}) | |
598 | ); | |
599 | lsu_dcs_dp_inv_macro__width_10 inv_sel2 ( | |
600 | .din ({asc_wr_p1ctxt [2],asc_wr_s1ctxt [2],asc_wr_p0ctxt [2],asc_wr_s0ctxt [2],asc_wr_pid [2], | |
601 | wr_p1ctxt_[2], wr_s1ctxt_[2], wr_p0ctxt_[2], wr_s0ctxt_[2], wr_pid_[2]}), | |
602 | .dout ({ wr_p1ctxt_[2], wr_s1ctxt_[2], wr_p0ctxt_[2], wr_s0ctxt_[2], wr_pid_[2], | |
603 | wr_p1ctxt [2], wr_s1ctxt [2], wr_p0ctxt [2], wr_s0ctxt [2], wr_pid[2]}) | |
604 | ); | |
605 | lsu_dcs_dp_inv_macro__width_10 inv_sel3 ( | |
606 | .din ({asc_wr_p1ctxt [3],asc_wr_s1ctxt [3],asc_wr_p0ctxt [3],asc_wr_s0ctxt [3],asc_wr_pid [3], | |
607 | wr_p1ctxt_[3], wr_s1ctxt_[3], wr_p0ctxt_[3], wr_s0ctxt_[3], wr_pid_[3]}), | |
608 | .dout ({ wr_p1ctxt_[3], wr_s1ctxt_[3], wr_p0ctxt_[3], wr_s0ctxt_[3], wr_pid_[3], | |
609 | wr_p1ctxt [3], wr_s1ctxt [3], wr_p0ctxt [3], wr_s0ctxt [3], wr_pid[3]}) | |
610 | ); | |
611 | lsu_dcs_dp_inv_macro__width_10 inv_sel4 ( | |
612 | .din ({asc_wr_p1ctxt [4],asc_wr_s1ctxt [4],asc_wr_p0ctxt [4],asc_wr_s0ctxt [4],asc_wr_pid [4], | |
613 | wr_p1ctxt_[4], wr_s1ctxt_[4], wr_p0ctxt_[4], wr_s0ctxt_[4], wr_pid_[4]}), | |
614 | .dout ({ wr_p1ctxt_[4], wr_s1ctxt_[4], wr_p0ctxt_[4], wr_s0ctxt_[4], wr_pid_[4], | |
615 | wr_p1ctxt [4], wr_s1ctxt [4], wr_p0ctxt [4], wr_s0ctxt [4], wr_pid[4]}) | |
616 | ); | |
617 | lsu_dcs_dp_inv_macro__width_10 inv_sel5 ( | |
618 | .din ({asc_wr_p1ctxt [5],asc_wr_s1ctxt [5],asc_wr_p0ctxt [5],asc_wr_s0ctxt [5],asc_wr_pid [5], | |
619 | wr_p1ctxt_[5], wr_s1ctxt_[5], wr_p0ctxt_[5], wr_s0ctxt_[5], wr_pid_[5]}), | |
620 | .dout ({ wr_p1ctxt_[5], wr_s1ctxt_[5], wr_p0ctxt_[5], wr_s0ctxt_[5], wr_pid_[5], | |
621 | wr_p1ctxt [5], wr_s1ctxt [5], wr_p0ctxt [5], wr_s0ctxt [5], wr_pid[5]}) | |
622 | ); | |
623 | lsu_dcs_dp_inv_macro__width_10 inv_sel6 ( | |
624 | .din ({asc_wr_p1ctxt [6],asc_wr_s1ctxt [6],asc_wr_p0ctxt [6],asc_wr_s0ctxt [6],asc_wr_pid [6], | |
625 | wr_p1ctxt_[6], wr_s1ctxt_[6], wr_p0ctxt_[6], wr_s0ctxt_[6], wr_pid_[6]}), | |
626 | .dout ({ wr_p1ctxt_[6], wr_s1ctxt_[6], wr_p0ctxt_[6], wr_s0ctxt_[6], wr_pid_[6], | |
627 | wr_p1ctxt [6], wr_s1ctxt [6], wr_p0ctxt [6], wr_s0ctxt [6], wr_pid[6]}) | |
628 | ); | |
629 | lsu_dcs_dp_inv_macro__width_10 inv_sel7 ( | |
630 | .din ({asc_wr_p1ctxt [7],asc_wr_s1ctxt [7],asc_wr_p0ctxt [7],asc_wr_s0ctxt [7],asc_wr_pid [7], | |
631 | wr_p1ctxt_[7], wr_s1ctxt_[7], wr_p0ctxt_[7], wr_s0ctxt_[7], wr_pid_[7]}), | |
632 | .dout ({ wr_p1ctxt_[7], wr_s1ctxt_[7], wr_p0ctxt_[7], wr_s0ctxt_[7], wr_pid_[7], | |
633 | wr_p1ctxt [7], wr_s1ctxt [7], wr_p0ctxt [7], wr_s0ctxt [7], wr_pid[7]}) | |
634 | ); | |
635 | ||
636 | // Primary context 0 muxes | |
637 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_0 ( | |
638 | .din0 (asi_data_in[12:0]), | |
639 | .din1 (p0ctxt_0[12:0]), | |
640 | .sel0 (wr_p0ctxt[0]), | |
641 | .sel1 (wr_p0ctxt_[0]), | |
642 | .dout (p0ctxt_0_in[12:0]) | |
643 | ); | |
644 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_1 ( | |
645 | .din0 (asi_data_in[12:0]), | |
646 | .din1 (p0ctxt_1[12:0]), | |
647 | .sel0 (wr_p0ctxt[1]), | |
648 | .sel1 (wr_p0ctxt_[1]), | |
649 | .dout (p0ctxt_1_in[12:0]) | |
650 | ); | |
651 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_2 ( | |
652 | .din0 (asi_data_in[12:0]), | |
653 | .din1 (p0ctxt_2[12:0]), | |
654 | .sel0 (wr_p0ctxt[2]), | |
655 | .sel1 (wr_p0ctxt_[2]), | |
656 | .dout (p0ctxt_2_in[12:0]) | |
657 | ); | |
658 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_3 ( | |
659 | .din0 (asi_data_in[12:0]), | |
660 | .din1 (p0ctxt_3[12:0]), | |
661 | .sel0 (wr_p0ctxt[3]), | |
662 | .sel1 (wr_p0ctxt_[3]), | |
663 | .dout (p0ctxt_3_in[12:0]) | |
664 | ); | |
665 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_4 ( | |
666 | .din0 (asi_data_in[12:0]), | |
667 | .din1 (p0ctxt_4[12:0]), | |
668 | .sel0 (wr_p0ctxt[4]), | |
669 | .sel1 (wr_p0ctxt_[4]), | |
670 | .dout (p0ctxt_4_in[12:0]) | |
671 | ); | |
672 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_5 ( | |
673 | .din0 (asi_data_in[12:0]), | |
674 | .din1 (p0ctxt_5[12:0]), | |
675 | .sel0 (wr_p0ctxt[5]), | |
676 | .sel1 (wr_p0ctxt_[5]), | |
677 | .dout (p0ctxt_5_in[12:0]) | |
678 | ); | |
679 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_6 ( | |
680 | .din0 (asi_data_in[12:0]), | |
681 | .din1 (p0ctxt_6[12:0]), | |
682 | .sel0 (wr_p0ctxt[6]), | |
683 | .sel1 (wr_p0ctxt_[6]), | |
684 | .dout (p0ctxt_6_in[12:0]) | |
685 | ); | |
686 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p0ctxt_7 ( | |
687 | .din0 (asi_data_in[12:0]), | |
688 | .din1 (p0ctxt_7[12:0]), | |
689 | .sel0 (wr_p0ctxt[7]), | |
690 | .sel1 (wr_p0ctxt_[7]), | |
691 | .dout (p0ctxt_7_in[12:0]) | |
692 | ); | |
693 | ||
694 | // Primary context 1 muxes | |
695 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_0 ( | |
696 | .din0 (asi_data_in[12:0]), | |
697 | .din1 (p1ctxt_0[12:0]), | |
698 | .sel0 (wr_p1ctxt[0]), | |
699 | .sel1 (wr_p1ctxt_[0]), | |
700 | .dout (p1ctxt_0_in[12:0]) | |
701 | ); | |
702 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_1 ( | |
703 | .din0 (asi_data_in[12:0]), | |
704 | .din1 (p1ctxt_1[12:0]), | |
705 | .sel0 (wr_p1ctxt[1]), | |
706 | .sel1 (wr_p1ctxt_[1]), | |
707 | .dout (p1ctxt_1_in[12:0]) | |
708 | ); | |
709 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_2 ( | |
710 | .din0 (asi_data_in[12:0]), | |
711 | .din1 (p1ctxt_2[12:0]), | |
712 | .sel0 (wr_p1ctxt[2]), | |
713 | .sel1 (wr_p1ctxt_[2]), | |
714 | .dout (p1ctxt_2_in[12:0]) | |
715 | ); | |
716 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_3 ( | |
717 | .din0 (asi_data_in[12:0]), | |
718 | .din1 (p1ctxt_3[12:0]), | |
719 | .sel0 (wr_p1ctxt[3]), | |
720 | .sel1 (wr_p1ctxt_[3]), | |
721 | .dout (p1ctxt_3_in[12:0]) | |
722 | ); | |
723 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_4 ( | |
724 | .din0 (asi_data_in[12:0]), | |
725 | .din1 (p1ctxt_4[12:0]), | |
726 | .sel0 (wr_p1ctxt[4]), | |
727 | .sel1 (wr_p1ctxt_[4]), | |
728 | .dout (p1ctxt_4_in[12:0]) | |
729 | ); | |
730 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_5 ( | |
731 | .din0 (asi_data_in[12:0]), | |
732 | .din1 (p1ctxt_5[12:0]), | |
733 | .sel0 (wr_p1ctxt[5]), | |
734 | .sel1 (wr_p1ctxt_[5]), | |
735 | .dout (p1ctxt_5_in[12:0]) | |
736 | ); | |
737 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_6 ( | |
738 | .din0 (asi_data_in[12:0]), | |
739 | .din1 (p1ctxt_6[12:0]), | |
740 | .sel0 (wr_p1ctxt[6]), | |
741 | .sel1 (wr_p1ctxt_[6]), | |
742 | .dout (p1ctxt_6_in[12:0]) | |
743 | ); | |
744 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_p1ctxt_7 ( | |
745 | .din0 (asi_data_in[12:0]), | |
746 | .din1 (p1ctxt_7[12:0]), | |
747 | .sel0 (wr_p1ctxt[7]), | |
748 | .sel1 (wr_p1ctxt_[7]), | |
749 | .dout (p1ctxt_7_in[12:0]) | |
750 | ); | |
751 | ||
752 | // Secondary context 0 muxes | |
753 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_0 ( | |
754 | .din0 (asi_data_in[12:0]), | |
755 | .din1 (s0ctxt_0[12:0]), | |
756 | .sel0 (wr_s0ctxt[0]), | |
757 | .sel1 (wr_s0ctxt_[0]), | |
758 | .dout (s0ctxt_0_in[12:0]) | |
759 | ); | |
760 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_1 ( | |
761 | .din0 (asi_data_in[12:0]), | |
762 | .din1 (s0ctxt_1[12:0]), | |
763 | .sel0 (wr_s0ctxt[1]), | |
764 | .sel1 (wr_s0ctxt_[1]), | |
765 | .dout (s0ctxt_1_in[12:0]) | |
766 | ); | |
767 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_2 ( | |
768 | .din0 (asi_data_in[12:0]), | |
769 | .din1 (s0ctxt_2[12:0]), | |
770 | .sel0 (wr_s0ctxt[2]), | |
771 | .sel1 (wr_s0ctxt_[2]), | |
772 | .dout (s0ctxt_2_in[12:0]) | |
773 | ); | |
774 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_3 ( | |
775 | .din0 (asi_data_in[12:0]), | |
776 | .din1 (s0ctxt_3[12:0]), | |
777 | .sel0 (wr_s0ctxt[3]), | |
778 | .sel1 (wr_s0ctxt_[3]), | |
779 | .dout (s0ctxt_3_in[12:0]) | |
780 | ); | |
781 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_4 ( | |
782 | .din0 (asi_data_in[12:0]), | |
783 | .din1 (s0ctxt_4[12:0]), | |
784 | .sel0 (wr_s0ctxt[4]), | |
785 | .sel1 (wr_s0ctxt_[4]), | |
786 | .dout (s0ctxt_4_in[12:0]) | |
787 | ); | |
788 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_5 ( | |
789 | .din0 (asi_data_in[12:0]), | |
790 | .din1 (s0ctxt_5[12:0]), | |
791 | .sel0 (wr_s0ctxt[5]), | |
792 | .sel1 (wr_s0ctxt_[5]), | |
793 | .dout (s0ctxt_5_in[12:0]) | |
794 | ); | |
795 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_6 ( | |
796 | .din0 (asi_data_in[12:0]), | |
797 | .din1 (s0ctxt_6[12:0]), | |
798 | .sel0 (wr_s0ctxt[6]), | |
799 | .sel1 (wr_s0ctxt_[6]), | |
800 | .dout (s0ctxt_6_in[12:0]) | |
801 | ); | |
802 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s0ctxt_7 ( | |
803 | .din0 (asi_data_in[12:0]), | |
804 | .din1 (s0ctxt_7[12:0]), | |
805 | .sel0 (wr_s0ctxt[7]), | |
806 | .sel1 (wr_s0ctxt_[7]), | |
807 | .dout (s0ctxt_7_in[12:0]) | |
808 | ); | |
809 | ||
810 | // Secondary context 1 muxes | |
811 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_0 ( | |
812 | .din0 (asi_data_in[12:0]), | |
813 | .din1 (s1ctxt_0[12:0]), | |
814 | .sel0 (wr_s1ctxt[0]), | |
815 | .sel1 (wr_s1ctxt_[0]), | |
816 | .dout (s1ctxt_0_in[12:0]) | |
817 | ); | |
818 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_1 ( | |
819 | .din0 (asi_data_in[12:0]), | |
820 | .din1 (s1ctxt_1[12:0]), | |
821 | .sel0 (wr_s1ctxt[1]), | |
822 | .sel1 (wr_s1ctxt_[1]), | |
823 | .dout (s1ctxt_1_in[12:0]) | |
824 | ); | |
825 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_2 ( | |
826 | .din0 (asi_data_in[12:0]), | |
827 | .din1 (s1ctxt_2[12:0]), | |
828 | .sel0 (wr_s1ctxt[2]), | |
829 | .sel1 (wr_s1ctxt_[2]), | |
830 | .dout (s1ctxt_2_in[12:0]) | |
831 | ); | |
832 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_3 ( | |
833 | .din0 (asi_data_in[12:0]), | |
834 | .din1 (s1ctxt_3[12:0]), | |
835 | .sel0 (wr_s1ctxt[3]), | |
836 | .sel1 (wr_s1ctxt_[3]), | |
837 | .dout (s1ctxt_3_in[12:0]) | |
838 | ); | |
839 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_4 ( | |
840 | .din0 (asi_data_in[12:0]), | |
841 | .din1 (s1ctxt_4[12:0]), | |
842 | .sel0 (wr_s1ctxt[4]), | |
843 | .sel1 (wr_s1ctxt_[4]), | |
844 | .dout (s1ctxt_4_in[12:0]) | |
845 | ); | |
846 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_5 ( | |
847 | .din0 (asi_data_in[12:0]), | |
848 | .din1 (s1ctxt_5[12:0]), | |
849 | .sel0 (wr_s1ctxt[5]), | |
850 | .sel1 (wr_s1ctxt_[5]), | |
851 | .dout (s1ctxt_5_in[12:0]) | |
852 | ); | |
853 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_6 ( | |
854 | .din0 (asi_data_in[12:0]), | |
855 | .din1 (s1ctxt_6[12:0]), | |
856 | .sel0 (wr_s1ctxt[6]), | |
857 | .sel1 (wr_s1ctxt_[6]), | |
858 | .dout (s1ctxt_6_in[12:0]) | |
859 | ); | |
860 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 mx_s1ctxt_7 ( | |
861 | .din0 (asi_data_in[12:0]), | |
862 | .din1 (s1ctxt_7[12:0]), | |
863 | .sel0 (wr_s1ctxt[7]), | |
864 | .sel1 (wr_s1ctxt_[7]), | |
865 | .dout (s1ctxt_7_in[12:0]) | |
866 | ); | |
867 | ||
868 | // Partition ID muxes | |
869 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid0 ( | |
870 | .din0 (asi_data_in[2:0]), | |
871 | .din1 (pid0[2:0]), | |
872 | .sel0 (wr_pid[0]), | |
873 | .sel1 (wr_pid_[0]), | |
874 | .dout (pid0_in[2:0]) | |
875 | ); | |
876 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid1 ( | |
877 | .din0 (asi_data_in[2:0]), | |
878 | .din1 (pid1[2:0]), | |
879 | .sel0 (wr_pid[1]), | |
880 | .sel1 (wr_pid_[1]), | |
881 | .dout (pid1_in[2:0]) | |
882 | ); | |
883 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid2 ( | |
884 | .din0 (asi_data_in[2:0]), | |
885 | .din1 (pid2[2:0]), | |
886 | .sel0 (wr_pid[2]), | |
887 | .sel1 (wr_pid_[2]), | |
888 | .dout (pid2_in[2:0]) | |
889 | ); | |
890 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid3 ( | |
891 | .din0 (asi_data_in[2:0]), | |
892 | .din1 (pid3[2:0]), | |
893 | .sel0 (wr_pid[3]), | |
894 | .sel1 (wr_pid_[3]), | |
895 | .dout (pid3_in[2:0]) | |
896 | ); | |
897 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid4 ( | |
898 | .din0 (asi_data_in[2:0]), | |
899 | .din1 (pid4[2:0]), | |
900 | .sel0 (wr_pid[4]), | |
901 | .sel1 (wr_pid_[4]), | |
902 | .dout (pid4_in[2:0]) | |
903 | ); | |
904 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid5 ( | |
905 | .din0 (asi_data_in[2:0]), | |
906 | .din1 (pid5[2:0]), | |
907 | .sel0 (wr_pid[5]), | |
908 | .sel1 (wr_pid_[5]), | |
909 | .dout (pid5_in[2:0]) | |
910 | ); | |
911 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid6 ( | |
912 | .din0 (asi_data_in[2:0]), | |
913 | .din1 (pid6[2:0]), | |
914 | .sel0 (wr_pid[6]), | |
915 | .sel1 (wr_pid_[6]), | |
916 | .dout (pid6_in[2:0]) | |
917 | ); | |
918 | lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 mx_pid7 ( | |
919 | .din0 (asi_data_in[2:0]), | |
920 | .din1 (pid7[2:0]), | |
921 | .sel0 (wr_pid[7]), | |
922 | .sel1 (wr_pid_[7]), | |
923 | .dout (pid7_in[2:0]) | |
924 | ); | |
925 | ||
926 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state0 ( // FS:wmr_protect | |
927 | .scan_in(dff_state0_wmr_scanin), | |
928 | .scan_out(dff_state0_wmr_scanout), | |
929 | .siclk(siclk_wmr), | |
930 | .din ({pid0_in[2:0],p1ctxt_0_in[12:0],s1ctxt_0_in[12:0],p0ctxt_0_in[12:0],s0ctxt_0_in[12:0],asi_state0_in[7:0]}), | |
931 | .dout (state0[62:0]), | |
932 | .clk (l2clk), | |
933 | .en (1'b1), | |
934 | .se(se), | |
935 | .soclk(soclk), | |
936 | .pce_ov(pce_ov), | |
937 | .stop(stop) | |
938 | ); | |
939 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state1 ( // FS:wmr_protect | |
940 | .scan_in(dff_state1_wmr_scanin), | |
941 | .scan_out(dff_state1_wmr_scanout), | |
942 | .siclk(siclk_wmr), | |
943 | .din ({pid1_in[2:0],p1ctxt_1_in[12:0],s1ctxt_1_in[12:0],p0ctxt_1_in[12:0],s0ctxt_1_in[12:0],asi_state1_in[7:0]}), | |
944 | .dout (state1[62:0]), | |
945 | .clk (l2clk), | |
946 | .en (1'b1), | |
947 | .se(se), | |
948 | .soclk(soclk), | |
949 | .pce_ov(pce_ov), | |
950 | .stop(stop) | |
951 | ); | |
952 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state2 ( // FS:wmr_protect | |
953 | .scan_in(dff_state2_wmr_scanin), | |
954 | .scan_out(dff_state2_wmr_scanout), | |
955 | .siclk(siclk_wmr), | |
956 | .din ({pid2_in[2:0],p1ctxt_2_in[12:0],s1ctxt_2_in[12:0],p0ctxt_2_in[12:0],s0ctxt_2_in[12:0],asi_state2_in[7:0]}), | |
957 | .dout (state2[62:0]), | |
958 | .clk (l2clk), | |
959 | .en (1'b1), | |
960 | .se(se), | |
961 | .soclk(soclk), | |
962 | .pce_ov(pce_ov), | |
963 | .stop(stop) | |
964 | ); | |
965 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state3 ( // FS:wmr_protect | |
966 | .scan_in(dff_state3_wmr_scanin), | |
967 | .scan_out(dff_state3_wmr_scanout), | |
968 | .siclk(siclk_wmr), | |
969 | .din ({pid3_in[2:0],p1ctxt_3_in[12:0],s1ctxt_3_in[12:0],p0ctxt_3_in[12:0],s0ctxt_3_in[12:0],asi_state3_in[7:0]}), | |
970 | .dout (state3[62:0]), | |
971 | .clk (l2clk), | |
972 | .en (1'b1), | |
973 | .se(se), | |
974 | .soclk(soclk), | |
975 | .pce_ov(pce_ov), | |
976 | .stop(stop) | |
977 | ); | |
978 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state4 ( // FS:wmr_protect | |
979 | .scan_in(dff_state4_wmr_scanin), | |
980 | .scan_out(dff_state4_wmr_scanout), | |
981 | .siclk(siclk_wmr), | |
982 | .din ({pid4_in[2:0],p1ctxt_4_in[12:0],s1ctxt_4_in[12:0],p0ctxt_4_in[12:0],s0ctxt_4_in[12:0],asi_state4_in[7:0]}), | |
983 | .dout (state4[62:0]), | |
984 | .clk (l2clk), | |
985 | .en (1'b1), | |
986 | .se(se), | |
987 | .soclk(soclk), | |
988 | .pce_ov(pce_ov), | |
989 | .stop(stop) | |
990 | ); | |
991 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state5 ( // FS:wmr_protect | |
992 | .scan_in(dff_state5_wmr_scanin), | |
993 | .scan_out(dff_state5_wmr_scanout), | |
994 | .siclk(siclk_wmr), | |
995 | .din ({pid5_in[2:0],p1ctxt_5_in[12:0],s1ctxt_5_in[12:0],p0ctxt_5_in[12:0],s0ctxt_5_in[12:0],asi_state5_in[7:0]}), | |
996 | .dout (state5[62:0]), | |
997 | .clk (l2clk), | |
998 | .en (1'b1), | |
999 | .se(se), | |
1000 | .soclk(soclk), | |
1001 | .pce_ov(pce_ov), | |
1002 | .stop(stop) | |
1003 | ); | |
1004 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state6 ( // FS:wmr_protect | |
1005 | .scan_in(dff_state6_wmr_scanin), | |
1006 | .scan_out(dff_state6_wmr_scanout), | |
1007 | .siclk(siclk_wmr), | |
1008 | .din ({pid6_in[2:0],p1ctxt_6_in[12:0],s1ctxt_6_in[12:0],p0ctxt_6_in[12:0],s0ctxt_6_in[12:0],asi_state6_in[7:0]}), | |
1009 | .dout (state6[62:0]), | |
1010 | .clk (l2clk), | |
1011 | .en (1'b1), | |
1012 | .se(se), | |
1013 | .soclk(soclk), | |
1014 | .pce_ov(pce_ov), | |
1015 | .stop(stop) | |
1016 | ); | |
1017 | lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 dff_state7 ( // FS:wmr_protect | |
1018 | .scan_in(dff_state7_wmr_scanin), | |
1019 | .scan_out(dff_state7_wmr_scanout), | |
1020 | .siclk(siclk_wmr), | |
1021 | .din ({pid7_in[2:0],p1ctxt_7_in[12:0],s1ctxt_7_in[12:0],p0ctxt_7_in[12:0],s0ctxt_7_in[12:0],asi_state7_in[7:0]}), | |
1022 | .dout (state7[62:0]), | |
1023 | .clk (l2clk), | |
1024 | .en (1'b1), | |
1025 | .se(se), | |
1026 | .soclk(soclk), | |
1027 | .pce_ov(pce_ov), | |
1028 | .stop(stop) | |
1029 | ); | |
1030 | ||
1031 | // DO NOT CHANGE THE NAMES OF THE asi_stateN SIGNALS. THE VERIFICATION BENCH EXPECTS THIS NAME. | |
1032 | assign {pid0[2:0],p1ctxt_0[12:0],s1ctxt_0[12:0],p0ctxt_0[12:0],s0ctxt_0[12:0],asi_state0[7:0]} = state0[62:0]; | |
1033 | assign {pid1[2:0],p1ctxt_1[12:0],s1ctxt_1[12:0],p0ctxt_1[12:0],s0ctxt_1[12:0],asi_state1[7:0]} = state1[62:0]; | |
1034 | assign {pid2[2:0],p1ctxt_2[12:0],s1ctxt_2[12:0],p0ctxt_2[12:0],s0ctxt_2[12:0],asi_state2[7:0]} = state2[62:0]; | |
1035 | assign {pid3[2:0],p1ctxt_3[12:0],s1ctxt_3[12:0],p0ctxt_3[12:0],s0ctxt_3[12:0],asi_state3[7:0]} = state3[62:0]; | |
1036 | assign {pid4[2:0],p1ctxt_4[12:0],s1ctxt_4[12:0],p0ctxt_4[12:0],s0ctxt_4[12:0],asi_state4[7:0]} = state4[62:0]; | |
1037 | assign {pid5[2:0],p1ctxt_5[12:0],s1ctxt_5[12:0],p0ctxt_5[12:0],s0ctxt_5[12:0],asi_state5[7:0]} = state5[62:0]; | |
1038 | assign {pid6[2:0],p1ctxt_6[12:0],s1ctxt_6[12:0],p0ctxt_6[12:0],s0ctxt_6[12:0],asi_state6[7:0]} = state6[62:0]; | |
1039 | assign {pid7[2:0],p1ctxt_7[12:0],s1ctxt_7[12:0],p0ctxt_7[12:0],s0ctxt_7[12:0],asi_state7[7:0]} = state7[62:0]; | |
1040 | ||
1041 | lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 mx_ctxt0 ( | |
1042 | .din0 (state0[62:8]), | |
1043 | .din1 (state1[62:8]), | |
1044 | .din2 (state2[62:8]), | |
1045 | .din3 (state3[62:8]), | |
1046 | .sel (dcc_ctxt_tid0_d[1:0]), | |
1047 | .dout (state_tg0[62:8]) | |
1048 | ); | |
1049 | ||
1050 | lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 mx_ctxt1 ( | |
1051 | .din0 (state4[62:8]), | |
1052 | .din1 (state5[62:8]), | |
1053 | .din2 (state6[62:8]), | |
1054 | .din3 (state7[62:8]), | |
1055 | .sel (dcc_ctxt_tid1_d[1:0]), | |
1056 | .dout (state_tg1[62:8]) | |
1057 | ); | |
1058 | lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 mx_asi0 ( | |
1059 | .din0 ({asi_state0[7:0],dmmu_enable[0]}), | |
1060 | .din1 ({asi_state1[7:0],dmmu_enable[1]}), | |
1061 | .din2 ({asi_state2[7:0],dmmu_enable[2]}), | |
1062 | .din3 ({asi_state3[7:0],dmmu_enable[3]}), | |
1063 | .sel (dec_lsu_tid0_d[1:0]), | |
1064 | .dout ({state_tg0[7:0],dmmu_enable_tg0}) | |
1065 | ); | |
1066 | ||
1067 | lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 mx_asi1 ( | |
1068 | .din0 ({asi_state4[7:0],dmmu_enable[4]}), | |
1069 | .din1 ({asi_state5[7:0],dmmu_enable[5]}), | |
1070 | .din2 ({asi_state6[7:0],dmmu_enable[6]}), | |
1071 | .din3 ({asi_state7[7:0],dmmu_enable[7]}), | |
1072 | .sel (dec_lsu_tid1_d[1:0]), | |
1073 | .dout ({state_tg1[7:0],dmmu_enable_tg1}) | |
1074 | ); | |
1075 | ||
1076 | lsu_dcs_dp_msff_macro__mux_aope__ports_2__stack_64c__width_55 dff_mx_ctxt ( | |
1077 | .scan_in(dff_mx_ctxt_scanin), | |
1078 | .scan_out(dff_mx_ctxt_scanout), | |
1079 | .din0 (state_tg1[62:8]), | |
1080 | .din1 (state_tg0[62:8]), | |
1081 | .sel0 (dcc_ctxt_tg_d), | |
1082 | .clk (l2clk), | |
1083 | .en (1'b1), | |
1084 | .dout ({dcs_pid_e[2:0],dcs_p1ctxt_e[12:0],dcs_s1ctxt_e[12:0],dcs_p0ctxt_e[12:0],dcs_s0ctxt_e[12:0]}), | |
1085 | .se(se), | |
1086 | .siclk(siclk), | |
1087 | .soclk(soclk), | |
1088 | .pce_ov(pce_ov), | |
1089 | .stop(stop) | |
1090 | ); | |
1091 | ||
1092 | lsu_dcs_dp_mux_macro__mux_pgpe__ports_2__stack_10r__width_9 mx_asi ( | |
1093 | .din0 ({state_tg1[7:0],dmmu_enable_tg1}), | |
1094 | .din1 ({state_tg0[7:0],dmmu_enable_tg0}), | |
1095 | .sel0 (dec_lsu_tg_d), | |
1096 | .dout ({dcs_asi_d[7:0],dcs_dmmu_enable_d}) | |
1097 | ); | |
1098 | ||
1099 | // Context selection | |
1100 | lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14l__width_13 mx_context0 ( | |
1101 | .din0 (dcs_p0ctxt_e[12:0]), | |
1102 | .din1 (dcs_s0ctxt_e[12:0]), | |
1103 | .sel0 (dcc_pctxt_sel_e), | |
1104 | .sel1 (dcc_sctxt_sel_e), | |
1105 | .dout (context0_e[12:0]) | |
1106 | ); | |
1107 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 buf_context0 ( | |
1108 | .din (context0_e[12:0]), | |
1109 | .dout (dcs_context0_e[12:0]) | |
1110 | ); | |
1111 | ||
1112 | // 0in bits_on -var {dcc_pctxt_sel_e,dcc_sctxt_sel_e} -max 1 -message "multiple context selects" | |
1113 | lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14r__width_13 mx_context1 ( | |
1114 | .din0 (dcs_p1ctxt_e[12:0]), | |
1115 | .din1 (dcs_s1ctxt_e[12:0]), | |
1116 | .sel0 (dcc_pctxt_sel_e), | |
1117 | .sel1 (dcc_sctxt_sel_e), | |
1118 | .dout (context1_e[12:0]) | |
1119 | ); | |
1120 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 buf_context1 ( | |
1121 | .din (context1_e[12:0]), | |
1122 | .dout (dcs_context1_e[12:0]) | |
1123 | ); | |
1124 | ||
1125 | // MMU needs the context in B for miss processing | |
1126 | lsu_dcs_dp_msff_macro__stack_14r__width_14 dff_context_m ( | |
1127 | .scan_in(dff_context_m_scanin), | |
1128 | .scan_out(dff_context_m_scanout), | |
1129 | .din ({dcc_dcs_memref_e,context0_e[12:0]}), | |
1130 | .dout ({memref_m ,dcs_context0_m[12:0]}), | |
1131 | .clk (l2clk), | |
1132 | .en (dcc_dcs_memref_e), | |
1133 | .se(se), | |
1134 | .siclk(siclk), | |
1135 | .soclk(soclk), | |
1136 | .pce_ov(pce_ov), | |
1137 | .stop(stop) // gated for power | |
1138 | ); | |
1139 | ||
1140 | // Used elsewhere for power management | |
1141 | assign dcs_memref_m = memref_m; | |
1142 | ||
1143 | lsu_dcs_dp_msff_macro__stack_30r__width_30 dff_context_b ( | |
1144 | .scan_in(dff_context_b_scanin), | |
1145 | .scan_out(dff_context_b_scanout), | |
1146 | .din ({dcs_context0_m[12:0], | |
1147 | dcs_wpt_mode_m[1:0],dcs_wpt_mask_m[7:0],dcs_wpt_enable_m[1:0],lsu_ctl_reg_m[4:0]}), | |
1148 | .dout ({dcs_context0_b[12:0], | |
1149 | dcs_wpt_mode_b[1:0],dcs_wpt_mask_b[7:0],dcs_wpt_enable_b[1:0],lsu_ctl_reg_b[4:0]}), | |
1150 | .clk (l2clk), | |
1151 | .en (memref_m), | |
1152 | .se(se), | |
1153 | .siclk(siclk), | |
1154 | .soclk(soclk), | |
1155 | .pce_ov(pce_ov), | |
1156 | .stop(stop) // gated for power | |
1157 | ); | |
1158 | ||
1159 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 context_buf ( | |
1160 | .din (dcs_context0_b[12:0]), | |
1161 | .dout (lsu_context_b[12:0]) | |
1162 | ); | |
1163 | ||
1164 | lsu_dcs_dp_msff_macro__stack_64c__width_55 dff_state_m ( | |
1165 | .scan_in(dff_state_m_scanin), | |
1166 | .scan_out(dff_state_m_scanout), | |
1167 | .din ({dcs_pid_e[2:0],dcs_p1ctxt_e[12:0],dcs_s1ctxt_e[12:0],dcs_p0ctxt_e[12:0],dcs_s0ctxt_e[12:0]}), | |
1168 | .dout ({dcs_pid_m[2:0],dcs_p1ctxt_m[12:0],dcs_s1ctxt_m[12:0],dcs_p0ctxt_m[12:0],dcs_s0ctxt_m[12:0]}), | |
1169 | .clk (l2clk), | |
1170 | .en (dcc_ld_inst_unqual_e), | |
1171 | .se(se), | |
1172 | .siclk(siclk), | |
1173 | .soclk(soclk), | |
1174 | .pce_ov(pce_ov), | |
1175 | .stop(stop) // gated for power | |
1176 | ); | |
1177 | ||
1178 | // Mux out values for asi read. (ASI register is read in TLU, so it's not used here) | |
1179 | lsu_dcs_dp_mux_macro__mux_aonpe__ports_5__stack_14l__width_13 mx_state_rd ( | |
1180 | .din0 (dcs_p0ctxt_m[12:0]), | |
1181 | .din1 (dcs_p1ctxt_m[12:0]), | |
1182 | .din2 (dcs_s0ctxt_m[12:0]), | |
1183 | .din3 (dcs_s1ctxt_m[12:0]), | |
1184 | .din4 ({10'd0,dcs_pid_m[2:0]}), | |
1185 | .sel0 (dcc_p0ctxt_rd_m), | |
1186 | .sel1 (dcc_p1ctxt_rd_m), | |
1187 | .sel2 (dcc_s0ctxt_rd_m), | |
1188 | .sel3 (dcc_s1ctxt_rd_m), | |
1189 | .sel4 (dcc_pid_rd_m), | |
1190 | .dout (ldxa_asi_data_m[12:0]) | |
1191 | ); | |
1192 | ||
1193 | lsu_dcs_dp_msff_macro__left_17__mux_aope__ports_2__stack_64c__width_47 dff_stg_b ( | |
1194 | .scan_in(dff_stg_b_scanin), | |
1195 | .scan_out(dff_stg_b_scanout), | |
1196 | .din0 ({watchpoint_m[47:3],2'b0}), | |
1197 | .din1 ({34'd0,ldxa_asi_data_m[12:0]}), | |
1198 | .sel0 (dcc_wtchpt_sel_m), | |
1199 | .dout (stg_b[46:0]), | |
1200 | .clk (l2clk), | |
1201 | .en (dcc_asi_load_m), | |
1202 | .se(se), | |
1203 | .siclk(siclk), | |
1204 | .soclk(soclk), | |
1205 | .pce_ov(pce_ov), | |
1206 | .stop(stop) | |
1207 | ); | |
1208 | ||
1209 | assign ldxa_asi_data_b[12:0] = stg_b[12:0]; | |
1210 | assign watchpoint_b[47:3] = {stg_b[46:2]}; | |
1211 | ||
1212 | assign core_id[5:0] = {const_cpuid[2:0],dcc_tid_b[2:0]}; | |
1213 | assign max_core_id[5:0] = 6'b111111; | |
1214 | assign max_strand_id[5:0] = 6'b000111; | |
1215 | ||
1216 | lsu_dcs_dp_mux_macro__mux_aope__ports_8__stack_64c__width_64 mx_asi_b ( | |
1217 | .din0 ({{16{watchpoint_b[47]}},watchpoint_b[47:3],3'b00}), | |
1218 | .din1 ({29'd0,dcs_wpt_mode_b[1:0],dcs_wpt_mask_b[7:0],dcs_wpt_enable_b[1:0],18'd0,lsu_ctl_reg_b[4:0]}), | |
1219 | .din2 ({56'd0,dca_rparity_b[7:0]}), | |
1220 | .din3 ({26'b0,max_strand_id[5:0],10'b0,max_core_id[5:0],10'b0,core_id[5:0]}), | |
1221 | .din4 ({58'b0,core_id[5:0]}), | |
1222 | .din5 ({32'b0,lsu_asi_error_inject[31:0]}), | |
1223 | .din6 ({48'b0,lsu_asi_pwr_mgmt[15:0]}), | |
1224 | .din7 ({51'd0,ldxa_asi_data_b[12:0]}), | |
1225 | .sel0 (dcc_wtchpt_rd_b), | |
1226 | .sel1 (dcc_rd_lsu_ctl_reg_b), | |
1227 | .sel2 (dcc_rd_diag_dca_b), | |
1228 | .sel3 (dcc_rd_core_id_b), | |
1229 | .sel4 (dcc_rd_intr_id_b), | |
1230 | .sel5 (dcc_rd_error_inj_b), | |
1231 | .sel6 (dcc_rd_pwr_mgmt_b), | |
1232 | .dout (ldxa_asi_data_b_2[63:0]) | |
1233 | ); | |
1234 | lsu_dcs_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 dff_asi_w ( | |
1235 | .scan_in(dff_asi_w_scanin), | |
1236 | .scan_out(dff_asi_w_scanout), | |
1237 | .din0 ({62'd0,dcc_direct_map,lsu_ifu_direct_map}), | |
1238 | .din1 (tgd_ldxa_asi_data_b[63:0]), | |
1239 | .din2 (ldxa_asi_data_b_2[63:0]), | |
1240 | .sel0 (dcc_rd_diag_reg_b), | |
1241 | .sel1 (dcc_rd_rhs_asi_b), | |
1242 | .dout (dcs_ldxa_asi_data_w[63:0]), | |
1243 | .clk (l2clk), | |
1244 | .en (dcc_asi_load_b), | |
1245 | .se(se), | |
1246 | .siclk(siclk), | |
1247 | .soclk(soclk), | |
1248 | .pce_ov(pce_ov), | |
1249 | .stop(stop) | |
1250 | ); | |
1251 | ||
1252 | //////////////////////////////////////////////////////////////////////////////// | |
1253 | // Watchpoint registers and comparator | |
1254 | ||
1255 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_0 ( // FS:wmr_protect | |
1256 | .scan_in(dff_watchpoint_0_wmr_scanin), | |
1257 | .scan_out(dff_watchpoint_0_wmr_scanout), | |
1258 | .siclk(siclk_wmr), | |
1259 | .se (scan_en_wmr), | |
1260 | .din (wsr_data_w[47:3]), | |
1261 | .dout (watchpoint0[47:3]), | |
1262 | .clk (l2clk), | |
1263 | .en (dcc_wr_wtchpt[0]), | |
1264 | .soclk(soclk), | |
1265 | .pce_ov(pce_ov), | |
1266 | .stop(stop) | |
1267 | ); | |
1268 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_1 ( // FS:wmr_protect | |
1269 | .scan_in(dff_watchpoint_1_wmr_scanin), | |
1270 | .scan_out(dff_watchpoint_1_wmr_scanout), | |
1271 | .siclk(siclk_wmr), | |
1272 | .se (scan_en_wmr), | |
1273 | .din (wsr_data_w[47:3]), | |
1274 | .dout (watchpoint1[47:3]), | |
1275 | .clk (l2clk), | |
1276 | .en (dcc_wr_wtchpt[1]), | |
1277 | .soclk(soclk), | |
1278 | .pce_ov(pce_ov), | |
1279 | .stop(stop) | |
1280 | ); | |
1281 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_2 ( // FS:wmr_protect | |
1282 | .scan_in(dff_watchpoint_2_wmr_scanin), | |
1283 | .scan_out(dff_watchpoint_2_wmr_scanout), | |
1284 | .siclk(siclk_wmr), | |
1285 | .se (scan_en_wmr), | |
1286 | .din (wsr_data_w[47:3]), | |
1287 | .dout (watchpoint2[47:3]), | |
1288 | .clk (l2clk), | |
1289 | .en (dcc_wr_wtchpt[2]), | |
1290 | .soclk(soclk), | |
1291 | .pce_ov(pce_ov), | |
1292 | .stop(stop) | |
1293 | ); | |
1294 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_3 ( // FS:wmr_protect | |
1295 | .scan_in(dff_watchpoint_3_wmr_scanin), | |
1296 | .scan_out(dff_watchpoint_3_wmr_scanout), | |
1297 | .siclk(siclk_wmr), | |
1298 | .se (scan_en_wmr), | |
1299 | .din (wsr_data_w[47:3]), | |
1300 | .dout (watchpoint3[47:3]), | |
1301 | .clk (l2clk), | |
1302 | .en (dcc_wr_wtchpt[3]), | |
1303 | .soclk(soclk), | |
1304 | .pce_ov(pce_ov), | |
1305 | .stop(stop) | |
1306 | ); | |
1307 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_4 ( // FS:wmr_protect | |
1308 | .scan_in(dff_watchpoint_4_wmr_scanin), | |
1309 | .scan_out(dff_watchpoint_4_wmr_scanout), | |
1310 | .siclk(siclk_wmr), | |
1311 | .se (scan_en_wmr), | |
1312 | .din (wsr_data_w[47:3]), | |
1313 | .dout (watchpoint4[47:3]), | |
1314 | .clk (l2clk), | |
1315 | .en (dcc_wr_wtchpt[4]), | |
1316 | .soclk(soclk), | |
1317 | .pce_ov(pce_ov), | |
1318 | .stop(stop) | |
1319 | ); | |
1320 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_5 ( // FS:wmr_protect | |
1321 | .scan_in(dff_watchpoint_5_wmr_scanin), | |
1322 | .scan_out(dff_watchpoint_5_wmr_scanout), | |
1323 | .siclk(siclk_wmr), | |
1324 | .se (scan_en_wmr), | |
1325 | .din (wsr_data_w[47:3]), | |
1326 | .dout (watchpoint5[47:3]), | |
1327 | .clk (l2clk), | |
1328 | .en (dcc_wr_wtchpt[5]), | |
1329 | .soclk(soclk), | |
1330 | .pce_ov(pce_ov), | |
1331 | .stop(stop) | |
1332 | ); | |
1333 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_6 ( // FS:wmr_protect | |
1334 | .scan_in(dff_watchpoint_6_wmr_scanin), | |
1335 | .scan_out(dff_watchpoint_6_wmr_scanout), | |
1336 | .siclk(siclk_wmr), | |
1337 | .se (scan_en_wmr), | |
1338 | .din (wsr_data_w[47:3]), | |
1339 | .dout (watchpoint6[47:3]), | |
1340 | .clk (l2clk), | |
1341 | .en (dcc_wr_wtchpt[6]), | |
1342 | .soclk(soclk), | |
1343 | .pce_ov(pce_ov), | |
1344 | .stop(stop) | |
1345 | ); | |
1346 | lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 dff_watchpoint_7 ( // FS:wmr_protect | |
1347 | .scan_in(dff_watchpoint_7_wmr_scanin), | |
1348 | .scan_out(dff_watchpoint_7_wmr_scanout), | |
1349 | .siclk(siclk_wmr), | |
1350 | .se (scan_en_wmr), | |
1351 | .din (wsr_data_w[47:3]), | |
1352 | .dout (watchpoint7[47:3]), | |
1353 | .clk (l2clk), | |
1354 | .en (dcc_wr_wtchpt[7]), | |
1355 | .soclk(soclk), | |
1356 | .pce_ov(pce_ov), | |
1357 | .stop(stop) | |
1358 | ); | |
1359 | ||
1360 | lsu_dcs_dp_mux_macro__left_18__mux_aodec__ports_8__stack_64c__width_45 mx_watchpoint ( | |
1361 | .din0 (watchpoint0[47:3]), | |
1362 | .din1 (watchpoint1[47:3]), | |
1363 | .din2 (watchpoint2[47:3]), | |
1364 | .din3 (watchpoint3[47:3]), | |
1365 | .din4 (watchpoint4[47:3]), | |
1366 | .din5 (watchpoint5[47:3]), | |
1367 | .din6 (watchpoint6[47:3]), | |
1368 | .din7 (watchpoint7[47:3]), | |
1369 | .sel (dcc_tid_m[2:0]), | |
1370 | .dout (watchpoint_mx_m[47:3]) | |
1371 | ); | |
1372 | ||
1373 | lsu_dcs_dp_buff_macro__left_18__stack_64c__width_45 buf_watchpoint ( | |
1374 | .din (watchpoint_mx_m[47:3]), | |
1375 | .dout (watchpoint_m[47:3]) | |
1376 | ); | |
1377 | assign dcs_watchpoint_m[47:3] = watchpoint_m[47:3]; | |
1378 | ||
1379 | //////////////////////////////////////////////////////////////////////////////// | |
1380 | // ASI_LSU_CTL_REG | |
1381 | ||
1382 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_0 ( | |
1383 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1384 | .din1 ({17{tlu_lsu_clear_ctl_reg_[0]}}), | |
1385 | .dout (ctl_reg0_in[16:0]) | |
1386 | ); | |
1387 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_1 ( | |
1388 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1389 | .din1 ({17{tlu_lsu_clear_ctl_reg_[1]}}), | |
1390 | .dout (ctl_reg1_in[16:0]) | |
1391 | ); | |
1392 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_2 ( | |
1393 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1394 | .din1 ({17{tlu_lsu_clear_ctl_reg_[2]}}), | |
1395 | .dout (ctl_reg2_in[16:0]) | |
1396 | ); | |
1397 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_3 ( | |
1398 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1399 | .din1 ({17{tlu_lsu_clear_ctl_reg_[3]}}), | |
1400 | .dout (ctl_reg3_in[16:0]) | |
1401 | ); | |
1402 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_4 ( | |
1403 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1404 | .din1 ({17{tlu_lsu_clear_ctl_reg_[4]}}), | |
1405 | .dout (ctl_reg4_in[16:0]) | |
1406 | ); | |
1407 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_5 ( | |
1408 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1409 | .din1 ({17{tlu_lsu_clear_ctl_reg_[5]}}), | |
1410 | .dout (ctl_reg5_in[16:0]) | |
1411 | ); | |
1412 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_6 ( | |
1413 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1414 | .din1 ({17{tlu_lsu_clear_ctl_reg_[6]}}), | |
1415 | .dout (ctl_reg6_in[16:0]) | |
1416 | ); | |
1417 | lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 clr_ctl_7 ( | |
1418 | .din0 ({wsr_data_w[34:23],wsr_data_w[4:0]}), | |
1419 | .din1 ({17{tlu_lsu_clear_ctl_reg_[7]}}), | |
1420 | .dout (ctl_reg7_in[16:0]) | |
1421 | ); | |
1422 | ||
1423 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_0 ( | |
1424 | .scan_in(dff_lsu_ctl_0_scanin), | |
1425 | .scan_out(dff_lsu_ctl_0_scanout), | |
1426 | .din (ctl_reg0_in[16:0]), | |
1427 | .dout ({wpt_mode_0[1:0],wpt_mask_0[7:0],wpt_enable_0[1:0],spec_enable[0], | |
1428 | dmmu_enable[0],immu_enable[0],dc_enable[0],ic_enable[0]}), | |
1429 | .clk (l2clk), | |
1430 | .en (dcc_wr_lsu_ctl_reg[0]), | |
1431 | .se(se), | |
1432 | .siclk(siclk), | |
1433 | .soclk(soclk), | |
1434 | .pce_ov(pce_ov), | |
1435 | .stop(stop) | |
1436 | ); | |
1437 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_1 ( | |
1438 | .scan_in(dff_lsu_ctl_1_scanin), | |
1439 | .scan_out(dff_lsu_ctl_1_scanout), | |
1440 | .din (ctl_reg1_in[16:0]), | |
1441 | .dout ({wpt_mode_1[1:0],wpt_mask_1[7:0],wpt_enable_1[1:0],spec_enable[1], | |
1442 | dmmu_enable[1],immu_enable[1],dc_enable[1],ic_enable[1]}), | |
1443 | .clk (l2clk), | |
1444 | .en (dcc_wr_lsu_ctl_reg[1]), | |
1445 | .se(se), | |
1446 | .siclk(siclk), | |
1447 | .soclk(soclk), | |
1448 | .pce_ov(pce_ov), | |
1449 | .stop(stop) | |
1450 | ); | |
1451 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_2 ( | |
1452 | .scan_in(dff_lsu_ctl_2_scanin), | |
1453 | .scan_out(dff_lsu_ctl_2_scanout), | |
1454 | .din (ctl_reg2_in[16:0]), | |
1455 | .dout ({wpt_mode_2[1:0],wpt_mask_2[7:0],wpt_enable_2[1:0],spec_enable[2], | |
1456 | dmmu_enable[2],immu_enable[2],dc_enable[2],ic_enable[2]}), | |
1457 | .clk (l2clk), | |
1458 | .en (dcc_wr_lsu_ctl_reg[2]), | |
1459 | .se(se), | |
1460 | .siclk(siclk), | |
1461 | .soclk(soclk), | |
1462 | .pce_ov(pce_ov), | |
1463 | .stop(stop) | |
1464 | ); | |
1465 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_3 ( | |
1466 | .scan_in(dff_lsu_ctl_3_scanin), | |
1467 | .scan_out(dff_lsu_ctl_3_scanout), | |
1468 | .din (ctl_reg3_in[16:0]), | |
1469 | .dout ({wpt_mode_3[1:0],wpt_mask_3[7:0],wpt_enable_3[1:0],spec_enable[3], | |
1470 | dmmu_enable[3],immu_enable[3],dc_enable[3],ic_enable[3]}), | |
1471 | .clk (l2clk), | |
1472 | .en (dcc_wr_lsu_ctl_reg[3]), | |
1473 | .se(se), | |
1474 | .siclk(siclk), | |
1475 | .soclk(soclk), | |
1476 | .pce_ov(pce_ov), | |
1477 | .stop(stop) | |
1478 | ); | |
1479 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_4 ( | |
1480 | .scan_in(dff_lsu_ctl_4_scanin), | |
1481 | .scan_out(dff_lsu_ctl_4_scanout), | |
1482 | .din (ctl_reg4_in[16:0]), | |
1483 | .dout ({wpt_mode_4[1:0],wpt_mask_4[7:0],wpt_enable_4[1:0],spec_enable[4], | |
1484 | dmmu_enable[4],immu_enable[4],dc_enable[4],ic_enable[4]}), | |
1485 | .clk (l2clk), | |
1486 | .en (dcc_wr_lsu_ctl_reg[4]), | |
1487 | .se(se), | |
1488 | .siclk(siclk), | |
1489 | .soclk(soclk), | |
1490 | .pce_ov(pce_ov), | |
1491 | .stop(stop) | |
1492 | ); | |
1493 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_5 ( | |
1494 | .scan_in(dff_lsu_ctl_5_scanin), | |
1495 | .scan_out(dff_lsu_ctl_5_scanout), | |
1496 | .din (ctl_reg5_in[16:0]), | |
1497 | .dout ({wpt_mode_5[1:0],wpt_mask_5[7:0],wpt_enable_5[1:0],spec_enable[5], | |
1498 | dmmu_enable[5],immu_enable[5],dc_enable[5],ic_enable[5]}), | |
1499 | .clk (l2clk), | |
1500 | .en (dcc_wr_lsu_ctl_reg[5]), | |
1501 | .se(se), | |
1502 | .siclk(siclk), | |
1503 | .soclk(soclk), | |
1504 | .pce_ov(pce_ov), | |
1505 | .stop(stop) | |
1506 | ); | |
1507 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_6 ( | |
1508 | .scan_in(dff_lsu_ctl_6_scanin), | |
1509 | .scan_out(dff_lsu_ctl_6_scanout), | |
1510 | .din (ctl_reg6_in[16:0]), | |
1511 | .dout ({wpt_mode_6[1:0],wpt_mask_6[7:0],wpt_enable_6[1:0],spec_enable[6], | |
1512 | dmmu_enable[6],immu_enable[6],dc_enable[6],ic_enable[6]}), | |
1513 | .clk (l2clk), | |
1514 | .en (dcc_wr_lsu_ctl_reg[6]), | |
1515 | .se(se), | |
1516 | .siclk(siclk), | |
1517 | .soclk(soclk), | |
1518 | .pce_ov(pce_ov), | |
1519 | .stop(stop) | |
1520 | ); | |
1521 | lsu_dcs_dp_msff_macro__stack_18r__width_17 dff_lsu_ctl_7 ( | |
1522 | .scan_in(dff_lsu_ctl_7_scanin), | |
1523 | .scan_out(dff_lsu_ctl_7_scanout), | |
1524 | .din (ctl_reg7_in[16:0]), | |
1525 | .dout ({wpt_mode_7[1:0],wpt_mask_7[7:0],wpt_enable_7[1:0],spec_enable[7], | |
1526 | dmmu_enable[7],immu_enable[7],dc_enable[7],ic_enable[7]}), | |
1527 | .clk (l2clk), | |
1528 | .en (dcc_wr_lsu_ctl_reg[7]), | |
1529 | .se(se), | |
1530 | .siclk(siclk), | |
1531 | .soclk(soclk), | |
1532 | .pce_ov(pce_ov), | |
1533 | .stop(stop) | |
1534 | ); | |
1535 | ||
1536 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_0 ( | |
1537 | .din ({immu_enable[0], dc_enable[0], ic_enable[0]}), | |
1538 | .dout ({lsu_immu_enable[0], dcs_dc_enable[0],lsu_ic_enable[0]}) | |
1539 | ); | |
1540 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_1 ( | |
1541 | .din ({immu_enable[1], dc_enable[1], ic_enable[1]}), | |
1542 | .dout ({lsu_immu_enable[1], dcs_dc_enable[1],lsu_ic_enable[1]}) | |
1543 | ); | |
1544 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_2 ( | |
1545 | .din ({immu_enable[2], dc_enable[2], ic_enable[2]}), | |
1546 | .dout ({lsu_immu_enable[2], dcs_dc_enable[2],lsu_ic_enable[2]}) | |
1547 | ); | |
1548 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_3 ( | |
1549 | .din ({immu_enable[3], dc_enable[3], ic_enable[3]}), | |
1550 | .dout ({lsu_immu_enable[3], dcs_dc_enable[3],lsu_ic_enable[3]}) | |
1551 | ); | |
1552 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_4 ( | |
1553 | .din ({immu_enable[4], dc_enable[4], ic_enable[4]}), | |
1554 | .dout ({lsu_immu_enable[4], dcs_dc_enable[4],lsu_ic_enable[4]}) | |
1555 | ); | |
1556 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_5 ( | |
1557 | .din ({immu_enable[5], dc_enable[5], ic_enable[5]}), | |
1558 | .dout ({lsu_immu_enable[5], dcs_dc_enable[5],lsu_ic_enable[5]}) | |
1559 | ); | |
1560 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_6 ( | |
1561 | .din ({immu_enable[6], dc_enable[6], ic_enable[6]}), | |
1562 | .dout ({lsu_immu_enable[6], dcs_dc_enable[6],lsu_ic_enable[6]}) | |
1563 | ); | |
1564 | lsu_dcs_dp_buff_macro__stack_4l__width_3 buf_lsu_ctl_7 ( | |
1565 | .din ({immu_enable[7], dc_enable[7], ic_enable[7]}), | |
1566 | .dout ({lsu_immu_enable[7], dcs_dc_enable[7],lsu_ic_enable[7]}) | |
1567 | ); | |
1568 | ||
1569 | lsu_dcs_dp_mux_macro__mux_aodec__ports_8__stack_18r__width_17 mx_lsu_ctl ( | |
1570 | .din0 ({wpt_mode_0[1:0],wpt_mask_0[7:0],wpt_enable_0[1:0],spec_enable[0], | |
1571 | dmmu_enable[0],immu_enable[0],dc_enable[0],ic_enable[0]}), | |
1572 | .din1 ({wpt_mode_1[1:0],wpt_mask_1[7:0],wpt_enable_1[1:0],spec_enable[1], | |
1573 | dmmu_enable[1],immu_enable[1],dc_enable[1],ic_enable[1]}), | |
1574 | .din2 ({wpt_mode_2[1:0],wpt_mask_2[7:0],wpt_enable_2[1:0],spec_enable[2], | |
1575 | dmmu_enable[2],immu_enable[2],dc_enable[2],ic_enable[2]}), | |
1576 | .din3 ({wpt_mode_3[1:0],wpt_mask_3[7:0],wpt_enable_3[1:0],spec_enable[3], | |
1577 | dmmu_enable[3],immu_enable[3],dc_enable[3],ic_enable[3]}), | |
1578 | .din4 ({wpt_mode_4[1:0],wpt_mask_4[7:0],wpt_enable_4[1:0],spec_enable[4], | |
1579 | dmmu_enable[4],immu_enable[4],dc_enable[4],ic_enable[4]}), | |
1580 | .din5 ({wpt_mode_5[1:0],wpt_mask_5[7:0],wpt_enable_5[1:0],spec_enable[5], | |
1581 | dmmu_enable[5],immu_enable[5],dc_enable[5],ic_enable[5]}), | |
1582 | .din6 ({wpt_mode_6[1:0],wpt_mask_6[7:0],wpt_enable_6[1:0],spec_enable[6], | |
1583 | dmmu_enable[6],immu_enable[6],dc_enable[6],ic_enable[6]}), | |
1584 | .din7 ({wpt_mode_7[1:0],wpt_mask_7[7:0],wpt_enable_7[1:0],spec_enable[7], | |
1585 | dmmu_enable[7],immu_enable[7],dc_enable[7],ic_enable[7]}), | |
1586 | .sel (dcc_tid_m[2:0]), | |
1587 | .dout (lsu_ctl_mx[16:0]) | |
1588 | ); | |
1589 | lsu_dcs_dp_buff_macro__stack_18r__width_17 buf_lsu_ctl ( | |
1590 | .din (lsu_ctl_mx[16:0]), | |
1591 | .dout ({dcs_wpt_mode_m[1:0],dcs_wpt_mask_m[7:0],dcs_wpt_enable_m[1:0],lsu_ctl_reg_m[4:0]}) | |
1592 | ); | |
1593 | ||
1594 | //////////////////////////////////////////////////////////////////////////////// | |
1595 | // ASI_ERROR_INJECT | |
1596 | ||
1597 | lsu_dcs_dp_msff_macro__stack_64c__width_32 dff_error_inject ( | |
1598 | .scan_in(dff_error_inject_scanin), | |
1599 | .scan_out(dff_error_inject_scanout), | |
1600 | .din ({wsr_data_w[31],1'b0,wsr_data_w[29:19],1'b0,wsr_data_w[17],9'b0,wsr_data_w[7:0]}), | |
1601 | .dout (asi_error_inject[31:0]), | |
1602 | .clk (l2clk), | |
1603 | .en (dcc_wr_error_inj_w), | |
1604 | .se(se), | |
1605 | .siclk(siclk), | |
1606 | .soclk(soclk), | |
1607 | .pce_ov(pce_ov), | |
1608 | .stop(stop) | |
1609 | ); | |
1610 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_32 buf_error_inject ( | |
1611 | .din (asi_error_inject[31:0]), | |
1612 | .dout (lsu_asi_error_inject[31:0]) | |
1613 | ); | |
1614 | ||
1615 | //////////////////////////////////////////////////////////////////////////////// | |
1616 | // ASI_SPARC_PWR_MGMT | |
1617 | ||
1618 | lsu_dcs_dp_msff_macro__stack_16r__width_16 dff_pwr_mgmt ( | |
1619 | .scan_in(dff_pwr_mgmt_scanin), | |
1620 | .scan_out(dff_pwr_mgmt_scanout), | |
1621 | .din (wsr_data_w[15:0]), | |
1622 | .dout (asi_pwr_mgmt[15:0]), | |
1623 | .clk (l2clk), | |
1624 | .en (dcc_wr_pwr_mgmt), | |
1625 | .se(se), | |
1626 | .siclk(siclk), | |
1627 | .soclk(soclk), | |
1628 | .pce_ov(pce_ov), | |
1629 | .stop(stop) | |
1630 | ); | |
1631 | lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_16r__width_16 buf_pwr_mgmt ( | |
1632 | .din (asi_pwr_mgmt[15:0]), | |
1633 | .dout (lsu_asi_pwr_mgmt[15:0]) | |
1634 | ); | |
1635 | ||
1636 | //////////////////////////////////////////////////////////////////////////////// | |
1637 | // Flop VA from M->B | |
1638 | lsu_dcs_dp_msff_macro__stack_48c__width_37 dff_va_b ( | |
1639 | .scan_in(dff_va_b_scanin), | |
1640 | .scan_out(dff_va_b_scanout), | |
1641 | .din ({tlu_asi_0[7:0],tlu_asi_1[7:0],lsu_va_m[20:0]}), | |
1642 | .dout ({reload_asi_0[7:0],reload_asi_1[7:0],va_b[20:0]}), | |
1643 | .clk (l2clk), | |
1644 | .en (1'b1), | |
1645 | .se(se), | |
1646 | .siclk(siclk), | |
1647 | .soclk(soclk), | |
1648 | .pce_ov(pce_ov), | |
1649 | .stop(stop) | |
1650 | ); | |
1651 | lsu_dcs_dp_buff_macro__stack_48c__width_21 buf_va_b ( | |
1652 | .din (va_b[20:0]), | |
1653 | .dout (lsu_va_b[20:0]) | |
1654 | ); | |
1655 | ||
1656 | // fixscan start: | |
1657 | assign dff_in_data_scanin = scan_in ; | |
1658 | assign dff_mx_ctxt_scanin = dff_in_data_scanout ; | |
1659 | assign dff_context_m_scanin = dff_mx_ctxt_scanout ; | |
1660 | assign dff_context_b_scanin = dff_context_m_scanout ; | |
1661 | assign dff_state_m_scanin = dff_context_b_scanout ; | |
1662 | assign dff_stg_b_scanin = dff_state_m_scanout ; | |
1663 | assign dff_asi_w_scanin = dff_stg_b_scanout ; | |
1664 | assign dff_lsu_ctl_0_scanin = dff_asi_w_scanout ; | |
1665 | assign dff_lsu_ctl_1_scanin = dff_lsu_ctl_0_scanout ; | |
1666 | assign dff_lsu_ctl_2_scanin = dff_lsu_ctl_1_scanout ; | |
1667 | assign dff_lsu_ctl_3_scanin = dff_lsu_ctl_2_scanout ; | |
1668 | assign dff_lsu_ctl_4_scanin = dff_lsu_ctl_3_scanout ; | |
1669 | assign dff_lsu_ctl_5_scanin = dff_lsu_ctl_4_scanout ; | |
1670 | assign dff_lsu_ctl_6_scanin = dff_lsu_ctl_5_scanout ; | |
1671 | assign dff_lsu_ctl_7_scanin = dff_lsu_ctl_6_scanout ; | |
1672 | assign dff_error_inject_scanin = dff_lsu_ctl_7_scanout ; | |
1673 | assign dff_pwr_mgmt_scanin = dff_error_inject_scanout ; | |
1674 | assign dff_va_b_scanin = dff_pwr_mgmt_scanout ; | |
1675 | assign scan_out = dff_va_b_scanout ; | |
1676 | ||
1677 | assign dff_state0_wmr_scanin = wmr_scan_in ; | |
1678 | assign dff_state1_wmr_scanin = dff_state0_wmr_scanout ; | |
1679 | assign dff_state2_wmr_scanin = dff_state1_wmr_scanout ; | |
1680 | assign dff_state3_wmr_scanin = dff_state2_wmr_scanout ; | |
1681 | assign dff_state4_wmr_scanin = dff_state3_wmr_scanout ; | |
1682 | assign dff_state5_wmr_scanin = dff_state4_wmr_scanout ; | |
1683 | assign dff_state6_wmr_scanin = dff_state5_wmr_scanout ; | |
1684 | assign dff_state7_wmr_scanin = dff_state6_wmr_scanout ; | |
1685 | assign dff_watchpoint_0_wmr_scanin = dff_state7_wmr_scanout ; | |
1686 | assign dff_watchpoint_1_wmr_scanin = dff_watchpoint_0_wmr_scanout; | |
1687 | assign dff_watchpoint_2_wmr_scanin = dff_watchpoint_1_wmr_scanout; | |
1688 | assign dff_watchpoint_3_wmr_scanin = dff_watchpoint_2_wmr_scanout; | |
1689 | assign dff_watchpoint_4_wmr_scanin = dff_watchpoint_3_wmr_scanout; | |
1690 | assign dff_watchpoint_5_wmr_scanin = dff_watchpoint_4_wmr_scanout; | |
1691 | assign dff_watchpoint_6_wmr_scanin = dff_watchpoint_5_wmr_scanout; | |
1692 | assign dff_watchpoint_7_wmr_scanin = dff_watchpoint_6_wmr_scanout; | |
1693 | assign wmr_scan_out = dff_watchpoint_7_wmr_scanout; | |
1694 | // fixscan end: | |
1695 | endmodule | |
1696 | ||
1697 | ||
1698 | ||
1699 | // | |
1700 | // buff macro | |
1701 | // | |
1702 | // | |
1703 | ||
1704 | ||
1705 | ||
1706 | ||
1707 | ||
1708 | module lsu_dcs_dp_buff_macro__dbuff_32x__rep_1__stack_none__width_6 ( | |
1709 | din, | |
1710 | dout); | |
1711 | input [5:0] din; | |
1712 | output [5:0] dout; | |
1713 | ||
1714 | ||
1715 | ||
1716 | ||
1717 | ||
1718 | ||
1719 | buff #(6) d0_0 ( | |
1720 | .in(din[5:0]), | |
1721 | .out(dout[5:0]) | |
1722 | ); | |
1723 | ||
1724 | ||
1725 | ||
1726 | ||
1727 | ||
1728 | ||
1729 | ||
1730 | ||
1731 | endmodule | |
1732 | ||
1733 | ||
1734 | ||
1735 | ||
1736 | ||
1737 | ||
1738 | ||
1739 | ||
1740 | ||
1741 | // any PARAMS parms go into naming of macro | |
1742 | ||
1743 | module lsu_dcs_dp_msff_macro__left_16__stack_64c__width_48 ( | |
1744 | din, | |
1745 | clk, | |
1746 | en, | |
1747 | se, | |
1748 | scan_in, | |
1749 | siclk, | |
1750 | soclk, | |
1751 | pce_ov, | |
1752 | stop, | |
1753 | dout, | |
1754 | scan_out); | |
1755 | wire l1clk; | |
1756 | wire siclk_out; | |
1757 | wire soclk_out; | |
1758 | wire [46:0] so; | |
1759 | ||
1760 | input [47:0] din; | |
1761 | ||
1762 | ||
1763 | input clk; | |
1764 | input en; | |
1765 | input se; | |
1766 | input scan_in; | |
1767 | input siclk; | |
1768 | input soclk; | |
1769 | input pce_ov; | |
1770 | input stop; | |
1771 | ||
1772 | ||
1773 | ||
1774 | output [47:0] dout; | |
1775 | ||
1776 | ||
1777 | output scan_out; | |
1778 | ||
1779 | ||
1780 | ||
1781 | ||
1782 | cl_dp1_l1hdr_8x c0_0 ( | |
1783 | .l2clk(clk), | |
1784 | .pce(en), | |
1785 | .aclk(siclk), | |
1786 | .bclk(soclk), | |
1787 | .l1clk(l1clk), | |
1788 | .se(se), | |
1789 | .pce_ov(pce_ov), | |
1790 | .stop(stop), | |
1791 | .siclk_out(siclk_out), | |
1792 | .soclk_out(soclk_out) | |
1793 | ); | |
1794 | dff #(48) d0_0 ( | |
1795 | .l1clk(l1clk), | |
1796 | .siclk(siclk_out), | |
1797 | .soclk(soclk_out), | |
1798 | .d(din[47:0]), | |
1799 | .si({scan_in,so[46:0]}), | |
1800 | .so({so[46:0],scan_out}), | |
1801 | .q(dout[47:0]) | |
1802 | ); | |
1803 | ||
1804 | ||
1805 | ||
1806 | ||
1807 | ||
1808 | ||
1809 | ||
1810 | ||
1811 | ||
1812 | ||
1813 | ||
1814 | ||
1815 | ||
1816 | ||
1817 | ||
1818 | ||
1819 | ||
1820 | ||
1821 | ||
1822 | ||
1823 | endmodule | |
1824 | ||
1825 | ||
1826 | ||
1827 | ||
1828 | ||
1829 | ||
1830 | ||
1831 | ||
1832 | ||
1833 | // | |
1834 | // buff macro | |
1835 | // | |
1836 | // | |
1837 | ||
1838 | ||
1839 | ||
1840 | ||
1841 | ||
1842 | module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__width_13 ( | |
1843 | din, | |
1844 | dout); | |
1845 | input [12:0] din; | |
1846 | output [12:0] dout; | |
1847 | ||
1848 | ||
1849 | ||
1850 | ||
1851 | ||
1852 | ||
1853 | buff #(13) d0_0 ( | |
1854 | .in(din[12:0]), | |
1855 | .out(dout[12:0]) | |
1856 | ); | |
1857 | ||
1858 | ||
1859 | ||
1860 | ||
1861 | ||
1862 | ||
1863 | ||
1864 | ||
1865 | endmodule | |
1866 | ||
1867 | ||
1868 | ||
1869 | ||
1870 | ||
1871 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1872 | // also for pass-gate with decoder | |
1873 | ||
1874 | ||
1875 | ||
1876 | ||
1877 | ||
1878 | // any PARAMS parms go into naming of macro | |
1879 | ||
1880 | module lsu_dcs_dp_mux_macro__mux_aope__ports_3__stack_8r__width_8 ( | |
1881 | din0, | |
1882 | din1, | |
1883 | din2, | |
1884 | sel0, | |
1885 | sel1, | |
1886 | dout); | |
1887 | wire psel0; | |
1888 | wire psel1; | |
1889 | wire psel2; | |
1890 | ||
1891 | input [7:0] din0; | |
1892 | input [7:0] din1; | |
1893 | input [7:0] din2; | |
1894 | input sel0; | |
1895 | input sel1; | |
1896 | output [7:0] dout; | |
1897 | ||
1898 | ||
1899 | ||
1900 | ||
1901 | ||
1902 | cl_dp1_penc3_8x c0_0 ( | |
1903 | .test(1'b1), | |
1904 | .sel0(sel0), | |
1905 | .sel1(sel1), | |
1906 | .psel0(psel0), | |
1907 | .psel1(psel1), | |
1908 | .psel2(psel2) | |
1909 | ); | |
1910 | ||
1911 | mux3s #(8) d0_0 ( | |
1912 | .sel0(psel0), | |
1913 | .sel1(psel1), | |
1914 | .sel2(psel2), | |
1915 | .in0(din0[7:0]), | |
1916 | .in1(din1[7:0]), | |
1917 | .in2(din2[7:0]), | |
1918 | .dout(dout[7:0]) | |
1919 | ); | |
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | ||
1925 | ||
1926 | ||
1927 | ||
1928 | ||
1929 | ||
1930 | ||
1931 | ||
1932 | ||
1933 | endmodule | |
1934 | ||
1935 | ||
1936 | // | |
1937 | // invert macro | |
1938 | // | |
1939 | // | |
1940 | ||
1941 | ||
1942 | ||
1943 | ||
1944 | ||
1945 | module lsu_dcs_dp_inv_macro__width_10 ( | |
1946 | din, | |
1947 | dout); | |
1948 | input [9:0] din; | |
1949 | output [9:0] dout; | |
1950 | ||
1951 | ||
1952 | ||
1953 | ||
1954 | ||
1955 | ||
1956 | inv #(10) d0_0 ( | |
1957 | .in(din[9:0]), | |
1958 | .out(dout[9:0]) | |
1959 | ); | |
1960 | ||
1961 | ||
1962 | ||
1963 | ||
1964 | ||
1965 | ||
1966 | ||
1967 | ||
1968 | ||
1969 | endmodule | |
1970 | ||
1971 | ||
1972 | ||
1973 | ||
1974 | ||
1975 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
1976 | // also for pass-gate with decoder | |
1977 | ||
1978 | ||
1979 | ||
1980 | ||
1981 | ||
1982 | // any PARAMS parms go into naming of macro | |
1983 | ||
1984 | module lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_13 ( | |
1985 | din0, | |
1986 | sel0, | |
1987 | din1, | |
1988 | sel1, | |
1989 | dout); | |
1990 | input [12:0] din0; | |
1991 | input sel0; | |
1992 | input [12:0] din1; | |
1993 | input sel1; | |
1994 | output [12:0] dout; | |
1995 | ||
1996 | ||
1997 | ||
1998 | ||
1999 | ||
2000 | mux2s #(13) d0_0 ( | |
2001 | .sel0(sel0), | |
2002 | .sel1(sel1), | |
2003 | .in0(din0[12:0]), | |
2004 | .in1(din1[12:0]), | |
2005 | .dout(dout[12:0]) | |
2006 | ); | |
2007 | ||
2008 | ||
2009 | ||
2010 | ||
2011 | ||
2012 | ||
2013 | ||
2014 | ||
2015 | ||
2016 | ||
2017 | ||
2018 | ||
2019 | ||
2020 | endmodule | |
2021 | ||
2022 | ||
2023 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2024 | // also for pass-gate with decoder | |
2025 | ||
2026 | ||
2027 | ||
2028 | ||
2029 | ||
2030 | // any PARAMS parms go into naming of macro | |
2031 | ||
2032 | module lsu_dcs_dp_mux_macro__buffsel_none__mux_aonpe__ports_2__width_3 ( | |
2033 | din0, | |
2034 | sel0, | |
2035 | din1, | |
2036 | sel1, | |
2037 | dout); | |
2038 | input [2:0] din0; | |
2039 | input sel0; | |
2040 | input [2:0] din1; | |
2041 | input sel1; | |
2042 | output [2:0] dout; | |
2043 | ||
2044 | ||
2045 | ||
2046 | ||
2047 | ||
2048 | mux2s #(3) d0_0 ( | |
2049 | .sel0(sel0), | |
2050 | .sel1(sel1), | |
2051 | .in0(din0[2:0]), | |
2052 | .in1(din1[2:0]), | |
2053 | .dout(dout[2:0]) | |
2054 | ); | |
2055 | ||
2056 | ||
2057 | ||
2058 | ||
2059 | ||
2060 | ||
2061 | ||
2062 | ||
2063 | ||
2064 | ||
2065 | ||
2066 | ||
2067 | ||
2068 | endmodule | |
2069 | ||
2070 | ||
2071 | ||
2072 | ||
2073 | ||
2074 | ||
2075 | // any PARAMS parms go into naming of macro | |
2076 | ||
2077 | module lsu_dcs_dp_msff_macro__left_1__stack_64c__width_63 ( | |
2078 | din, | |
2079 | clk, | |
2080 | en, | |
2081 | se, | |
2082 | scan_in, | |
2083 | siclk, | |
2084 | soclk, | |
2085 | pce_ov, | |
2086 | stop, | |
2087 | dout, | |
2088 | scan_out); | |
2089 | wire l1clk; | |
2090 | wire siclk_out; | |
2091 | wire soclk_out; | |
2092 | wire [61:0] so; | |
2093 | ||
2094 | input [62:0] din; | |
2095 | ||
2096 | ||
2097 | input clk; | |
2098 | input en; | |
2099 | input se; | |
2100 | input scan_in; | |
2101 | input siclk; | |
2102 | input soclk; | |
2103 | input pce_ov; | |
2104 | input stop; | |
2105 | ||
2106 | ||
2107 | ||
2108 | output [62:0] dout; | |
2109 | ||
2110 | ||
2111 | output scan_out; | |
2112 | ||
2113 | ||
2114 | ||
2115 | ||
2116 | cl_dp1_l1hdr_8x c0_0 ( | |
2117 | .l2clk(clk), | |
2118 | .pce(en), | |
2119 | .aclk(siclk), | |
2120 | .bclk(soclk), | |
2121 | .l1clk(l1clk), | |
2122 | .se(se), | |
2123 | .pce_ov(pce_ov), | |
2124 | .stop(stop), | |
2125 | .siclk_out(siclk_out), | |
2126 | .soclk_out(soclk_out) | |
2127 | ); | |
2128 | dff #(63) d0_0 ( | |
2129 | .l1clk(l1clk), | |
2130 | .siclk(siclk_out), | |
2131 | .soclk(soclk_out), | |
2132 | .d(din[62:0]), | |
2133 | .si({scan_in,so[61:0]}), | |
2134 | .so({so[61:0],scan_out}), | |
2135 | .q(dout[62:0]) | |
2136 | ); | |
2137 | ||
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | ||
2143 | ||
2144 | ||
2145 | ||
2146 | ||
2147 | ||
2148 | ||
2149 | ||
2150 | ||
2151 | ||
2152 | ||
2153 | ||
2154 | ||
2155 | ||
2156 | ||
2157 | endmodule | |
2158 | ||
2159 | ||
2160 | ||
2161 | ||
2162 | ||
2163 | ||
2164 | ||
2165 | ||
2166 | ||
2167 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2168 | // also for pass-gate with decoder | |
2169 | ||
2170 | ||
2171 | ||
2172 | ||
2173 | ||
2174 | // any PARAMS parms go into naming of macro | |
2175 | ||
2176 | module lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_64c__width_55 ( | |
2177 | din0, | |
2178 | din1, | |
2179 | din2, | |
2180 | din3, | |
2181 | sel, | |
2182 | dout); | |
2183 | wire psel0; | |
2184 | wire psel1; | |
2185 | wire psel2; | |
2186 | wire psel3; | |
2187 | ||
2188 | input [54:0] din0; | |
2189 | input [54:0] din1; | |
2190 | input [54:0] din2; | |
2191 | input [54:0] din3; | |
2192 | input [1:0] sel; | |
2193 | output [54:0] dout; | |
2194 | ||
2195 | ||
2196 | ||
2197 | ||
2198 | ||
2199 | cl_dp1_pdec4_8x c0_0 ( | |
2200 | .test(1'b1), | |
2201 | .sel0(sel[0]), | |
2202 | .sel1(sel[1]), | |
2203 | .psel0(psel0), | |
2204 | .psel1(psel1), | |
2205 | .psel2(psel2), | |
2206 | .psel3(psel3) | |
2207 | ); | |
2208 | ||
2209 | mux4s #(55) d0_0 ( | |
2210 | .sel0(psel0), | |
2211 | .sel1(psel1), | |
2212 | .sel2(psel2), | |
2213 | .sel3(psel3), | |
2214 | .in0(din0[54:0]), | |
2215 | .in1(din1[54:0]), | |
2216 | .in2(din2[54:0]), | |
2217 | .in3(din3[54:0]), | |
2218 | .dout(dout[54:0]) | |
2219 | ); | |
2220 | ||
2221 | ||
2222 | ||
2223 | ||
2224 | ||
2225 | ||
2226 | ||
2227 | ||
2228 | ||
2229 | ||
2230 | ||
2231 | ||
2232 | ||
2233 | endmodule | |
2234 | ||
2235 | ||
2236 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2237 | // also for pass-gate with decoder | |
2238 | ||
2239 | ||
2240 | ||
2241 | ||
2242 | ||
2243 | // any PARAMS parms go into naming of macro | |
2244 | ||
2245 | module lsu_dcs_dp_mux_macro__mux_aodec__ports_4__stack_10r__width_9 ( | |
2246 | din0, | |
2247 | din1, | |
2248 | din2, | |
2249 | din3, | |
2250 | sel, | |
2251 | dout); | |
2252 | wire psel0; | |
2253 | wire psel1; | |
2254 | wire psel2; | |
2255 | wire psel3; | |
2256 | ||
2257 | input [8:0] din0; | |
2258 | input [8:0] din1; | |
2259 | input [8:0] din2; | |
2260 | input [8:0] din3; | |
2261 | input [1:0] sel; | |
2262 | output [8:0] dout; | |
2263 | ||
2264 | ||
2265 | ||
2266 | ||
2267 | ||
2268 | cl_dp1_pdec4_8x c0_0 ( | |
2269 | .test(1'b1), | |
2270 | .sel0(sel[0]), | |
2271 | .sel1(sel[1]), | |
2272 | .psel0(psel0), | |
2273 | .psel1(psel1), | |
2274 | .psel2(psel2), | |
2275 | .psel3(psel3) | |
2276 | ); | |
2277 | ||
2278 | mux4s #(9) d0_0 ( | |
2279 | .sel0(psel0), | |
2280 | .sel1(psel1), | |
2281 | .sel2(psel2), | |
2282 | .sel3(psel3), | |
2283 | .in0(din0[8:0]), | |
2284 | .in1(din1[8:0]), | |
2285 | .in2(din2[8:0]), | |
2286 | .in3(din3[8:0]), | |
2287 | .dout(dout[8:0]) | |
2288 | ); | |
2289 | ||
2290 | ||
2291 | ||
2292 | ||
2293 | ||
2294 | ||
2295 | ||
2296 | ||
2297 | ||
2298 | ||
2299 | ||
2300 | ||
2301 | ||
2302 | endmodule | |
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | ||
2308 | ||
2309 | // any PARAMS parms go into naming of macro | |
2310 | ||
2311 | module lsu_dcs_dp_msff_macro__mux_aope__ports_2__stack_64c__width_55 ( | |
2312 | din0, | |
2313 | din1, | |
2314 | sel0, | |
2315 | clk, | |
2316 | en, | |
2317 | se, | |
2318 | scan_in, | |
2319 | siclk, | |
2320 | soclk, | |
2321 | pce_ov, | |
2322 | stop, | |
2323 | dout, | |
2324 | scan_out); | |
2325 | wire psel0; | |
2326 | wire psel1; | |
2327 | wire [54:0] muxout; | |
2328 | wire l1clk; | |
2329 | wire siclk_out; | |
2330 | wire soclk_out; | |
2331 | wire [53:0] so; | |
2332 | ||
2333 | input [54:0] din0; | |
2334 | input [54:0] din1; | |
2335 | input sel0; | |
2336 | ||
2337 | ||
2338 | input clk; | |
2339 | input en; | |
2340 | input se; | |
2341 | input scan_in; | |
2342 | input siclk; | |
2343 | input soclk; | |
2344 | input pce_ov; | |
2345 | input stop; | |
2346 | ||
2347 | ||
2348 | ||
2349 | output [54:0] dout; | |
2350 | ||
2351 | ||
2352 | output scan_out; | |
2353 | ||
2354 | ||
2355 | ||
2356 | ||
2357 | cl_dp1_penc2_8x c1_0 ( | |
2358 | .sel0(sel0), | |
2359 | .psel0(psel0), | |
2360 | .psel1(psel1) | |
2361 | ); | |
2362 | ||
2363 | mux2s #(55) d1_0 ( | |
2364 | .sel0(psel0), | |
2365 | .sel1(psel1), | |
2366 | .in0(din0[54:0]), | |
2367 | .in1(din1[54:0]), | |
2368 | .dout(muxout[54:0]) | |
2369 | ); | |
2370 | cl_dp1_l1hdr_8x c0_0 ( | |
2371 | .l2clk(clk), | |
2372 | .pce(en), | |
2373 | .aclk(siclk), | |
2374 | .bclk(soclk), | |
2375 | .l1clk(l1clk), | |
2376 | .se(se), | |
2377 | .pce_ov(pce_ov), | |
2378 | .stop(stop), | |
2379 | .siclk_out(siclk_out), | |
2380 | .soclk_out(soclk_out) | |
2381 | ); | |
2382 | dff #(55) d0_0 ( | |
2383 | .l1clk(l1clk), | |
2384 | .siclk(siclk_out), | |
2385 | .soclk(soclk_out), | |
2386 | .d(muxout[54:0]), | |
2387 | .si({scan_in,so[53:0]}), | |
2388 | .so({so[53:0],scan_out}), | |
2389 | .q(dout[54:0]) | |
2390 | ); | |
2391 | ||
2392 | ||
2393 | ||
2394 | ||
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | ||
2402 | ||
2403 | ||
2404 | ||
2405 | ||
2406 | ||
2407 | ||
2408 | ||
2409 | ||
2410 | ||
2411 | endmodule | |
2412 | ||
2413 | ||
2414 | ||
2415 | ||
2416 | ||
2417 | ||
2418 | ||
2419 | ||
2420 | ||
2421 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2422 | // also for pass-gate with decoder | |
2423 | ||
2424 | ||
2425 | ||
2426 | ||
2427 | ||
2428 | // any PARAMS parms go into naming of macro | |
2429 | ||
2430 | module lsu_dcs_dp_mux_macro__mux_pgpe__ports_2__stack_10r__width_9 ( | |
2431 | din0, | |
2432 | din1, | |
2433 | sel0, | |
2434 | dout); | |
2435 | wire psel0_unused; | |
2436 | wire psel1; | |
2437 | ||
2438 | input [8:0] din0; | |
2439 | input [8:0] din1; | |
2440 | input sel0; | |
2441 | output [8:0] dout; | |
2442 | ||
2443 | ||
2444 | ||
2445 | ||
2446 | ||
2447 | cl_dp1_penc2_8x c0_0 ( | |
2448 | .sel0(sel0), | |
2449 | .psel0(psel0_unused), | |
2450 | .psel1(psel1) | |
2451 | ); | |
2452 | ||
2453 | mux2e #(9) d0_0 ( | |
2454 | .sel(psel1), | |
2455 | .in0(din0[8:0]), | |
2456 | .in1(din1[8:0]), | |
2457 | .dout(dout[8:0]) | |
2458 | ); | |
2459 | ||
2460 | ||
2461 | ||
2462 | ||
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | ||
2468 | ||
2469 | ||
2470 | ||
2471 | ||
2472 | endmodule | |
2473 | ||
2474 | ||
2475 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2476 | // also for pass-gate with decoder | |
2477 | ||
2478 | ||
2479 | ||
2480 | ||
2481 | ||
2482 | // any PARAMS parms go into naming of macro | |
2483 | ||
2484 | module lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14l__width_13 ( | |
2485 | din0, | |
2486 | sel0, | |
2487 | din1, | |
2488 | sel1, | |
2489 | dout); | |
2490 | wire buffout0; | |
2491 | wire buffout1; | |
2492 | ||
2493 | input [12:0] din0; | |
2494 | input sel0; | |
2495 | input [12:0] din1; | |
2496 | input sel1; | |
2497 | output [12:0] dout; | |
2498 | ||
2499 | ||
2500 | ||
2501 | ||
2502 | ||
2503 | cl_dp1_muxbuff2_8x c0_0 ( | |
2504 | .in0(sel0), | |
2505 | .in1(sel1), | |
2506 | .out0(buffout0), | |
2507 | .out1(buffout1) | |
2508 | ); | |
2509 | mux2s #(13) d0_0 ( | |
2510 | .sel0(buffout0), | |
2511 | .sel1(buffout1), | |
2512 | .in0(din0[12:0]), | |
2513 | .in1(din1[12:0]), | |
2514 | .dout(dout[12:0]) | |
2515 | ); | |
2516 | ||
2517 | ||
2518 | ||
2519 | ||
2520 | ||
2521 | ||
2522 | ||
2523 | ||
2524 | ||
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | endmodule | |
2530 | ||
2531 | ||
2532 | // | |
2533 | // buff macro | |
2534 | // | |
2535 | // | |
2536 | ||
2537 | ||
2538 | ||
2539 | ||
2540 | ||
2541 | module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_14r__width_13 ( | |
2542 | din, | |
2543 | dout); | |
2544 | input [12:0] din; | |
2545 | output [12:0] dout; | |
2546 | ||
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | ||
2552 | buff #(13) d0_0 ( | |
2553 | .in(din[12:0]), | |
2554 | .out(dout[12:0]) | |
2555 | ); | |
2556 | ||
2557 | ||
2558 | ||
2559 | ||
2560 | ||
2561 | ||
2562 | ||
2563 | ||
2564 | endmodule | |
2565 | ||
2566 | ||
2567 | ||
2568 | ||
2569 | ||
2570 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2571 | // also for pass-gate with decoder | |
2572 | ||
2573 | ||
2574 | ||
2575 | ||
2576 | ||
2577 | // any PARAMS parms go into naming of macro | |
2578 | ||
2579 | module lsu_dcs_dp_mux_macro__mux_aonpe__ports_2__stack_14r__width_13 ( | |
2580 | din0, | |
2581 | sel0, | |
2582 | din1, | |
2583 | sel1, | |
2584 | dout); | |
2585 | wire buffout0; | |
2586 | wire buffout1; | |
2587 | ||
2588 | input [12:0] din0; | |
2589 | input sel0; | |
2590 | input [12:0] din1; | |
2591 | input sel1; | |
2592 | output [12:0] dout; | |
2593 | ||
2594 | ||
2595 | ||
2596 | ||
2597 | ||
2598 | cl_dp1_muxbuff2_8x c0_0 ( | |
2599 | .in0(sel0), | |
2600 | .in1(sel1), | |
2601 | .out0(buffout0), | |
2602 | .out1(buffout1) | |
2603 | ); | |
2604 | mux2s #(13) d0_0 ( | |
2605 | .sel0(buffout0), | |
2606 | .sel1(buffout1), | |
2607 | .in0(din0[12:0]), | |
2608 | .in1(din1[12:0]), | |
2609 | .dout(dout[12:0]) | |
2610 | ); | |
2611 | ||
2612 | ||
2613 | ||
2614 | ||
2615 | ||
2616 | ||
2617 | ||
2618 | ||
2619 | ||
2620 | ||
2621 | ||
2622 | ||
2623 | ||
2624 | endmodule | |
2625 | ||
2626 | ||
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | // any PARAMS parms go into naming of macro | |
2632 | ||
2633 | module lsu_dcs_dp_msff_macro__stack_14r__width_14 ( | |
2634 | din, | |
2635 | clk, | |
2636 | en, | |
2637 | se, | |
2638 | scan_in, | |
2639 | siclk, | |
2640 | soclk, | |
2641 | pce_ov, | |
2642 | stop, | |
2643 | dout, | |
2644 | scan_out); | |
2645 | wire l1clk; | |
2646 | wire siclk_out; | |
2647 | wire soclk_out; | |
2648 | wire [12:0] so; | |
2649 | ||
2650 | input [13:0] din; | |
2651 | ||
2652 | ||
2653 | input clk; | |
2654 | input en; | |
2655 | input se; | |
2656 | input scan_in; | |
2657 | input siclk; | |
2658 | input soclk; | |
2659 | input pce_ov; | |
2660 | input stop; | |
2661 | ||
2662 | ||
2663 | ||
2664 | output [13:0] dout; | |
2665 | ||
2666 | ||
2667 | output scan_out; | |
2668 | ||
2669 | ||
2670 | ||
2671 | ||
2672 | cl_dp1_l1hdr_8x c0_0 ( | |
2673 | .l2clk(clk), | |
2674 | .pce(en), | |
2675 | .aclk(siclk), | |
2676 | .bclk(soclk), | |
2677 | .l1clk(l1clk), | |
2678 | .se(se), | |
2679 | .pce_ov(pce_ov), | |
2680 | .stop(stop), | |
2681 | .siclk_out(siclk_out), | |
2682 | .soclk_out(soclk_out) | |
2683 | ); | |
2684 | dff #(14) d0_0 ( | |
2685 | .l1clk(l1clk), | |
2686 | .siclk(siclk_out), | |
2687 | .soclk(soclk_out), | |
2688 | .d(din[13:0]), | |
2689 | .si({scan_in,so[12:0]}), | |
2690 | .so({so[12:0],scan_out}), | |
2691 | .q(dout[13:0]) | |
2692 | ); | |
2693 | ||
2694 | ||
2695 | ||
2696 | ||
2697 | ||
2698 | ||
2699 | ||
2700 | ||
2701 | ||
2702 | ||
2703 | ||
2704 | ||
2705 | ||
2706 | ||
2707 | ||
2708 | ||
2709 | ||
2710 | ||
2711 | ||
2712 | ||
2713 | endmodule | |
2714 | ||
2715 | ||
2716 | ||
2717 | ||
2718 | ||
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | ||
2724 | ||
2725 | ||
2726 | ||
2727 | // any PARAMS parms go into naming of macro | |
2728 | ||
2729 | module lsu_dcs_dp_msff_macro__stack_30r__width_30 ( | |
2730 | din, | |
2731 | clk, | |
2732 | en, | |
2733 | se, | |
2734 | scan_in, | |
2735 | siclk, | |
2736 | soclk, | |
2737 | pce_ov, | |
2738 | stop, | |
2739 | dout, | |
2740 | scan_out); | |
2741 | wire l1clk; | |
2742 | wire siclk_out; | |
2743 | wire soclk_out; | |
2744 | wire [28:0] so; | |
2745 | ||
2746 | input [29:0] din; | |
2747 | ||
2748 | ||
2749 | input clk; | |
2750 | input en; | |
2751 | input se; | |
2752 | input scan_in; | |
2753 | input siclk; | |
2754 | input soclk; | |
2755 | input pce_ov; | |
2756 | input stop; | |
2757 | ||
2758 | ||
2759 | ||
2760 | output [29:0] dout; | |
2761 | ||
2762 | ||
2763 | output scan_out; | |
2764 | ||
2765 | ||
2766 | ||
2767 | ||
2768 | cl_dp1_l1hdr_8x c0_0 ( | |
2769 | .l2clk(clk), | |
2770 | .pce(en), | |
2771 | .aclk(siclk), | |
2772 | .bclk(soclk), | |
2773 | .l1clk(l1clk), | |
2774 | .se(se), | |
2775 | .pce_ov(pce_ov), | |
2776 | .stop(stop), | |
2777 | .siclk_out(siclk_out), | |
2778 | .soclk_out(soclk_out) | |
2779 | ); | |
2780 | dff #(30) d0_0 ( | |
2781 | .l1clk(l1clk), | |
2782 | .siclk(siclk_out), | |
2783 | .soclk(soclk_out), | |
2784 | .d(din[29:0]), | |
2785 | .si({scan_in,so[28:0]}), | |
2786 | .so({so[28:0],scan_out}), | |
2787 | .q(dout[29:0]) | |
2788 | ); | |
2789 | ||
2790 | ||
2791 | ||
2792 | ||
2793 | ||
2794 | ||
2795 | ||
2796 | ||
2797 | ||
2798 | ||
2799 | ||
2800 | ||
2801 | ||
2802 | ||
2803 | ||
2804 | ||
2805 | ||
2806 | ||
2807 | ||
2808 | ||
2809 | endmodule | |
2810 | ||
2811 | ||
2812 | ||
2813 | ||
2814 | ||
2815 | ||
2816 | ||
2817 | ||
2818 | ||
2819 | ||
2820 | ||
2821 | ||
2822 | ||
2823 | // any PARAMS parms go into naming of macro | |
2824 | ||
2825 | module lsu_dcs_dp_msff_macro__stack_64c__width_55 ( | |
2826 | din, | |
2827 | clk, | |
2828 | en, | |
2829 | se, | |
2830 | scan_in, | |
2831 | siclk, | |
2832 | soclk, | |
2833 | pce_ov, | |
2834 | stop, | |
2835 | dout, | |
2836 | scan_out); | |
2837 | wire l1clk; | |
2838 | wire siclk_out; | |
2839 | wire soclk_out; | |
2840 | wire [53:0] so; | |
2841 | ||
2842 | input [54:0] din; | |
2843 | ||
2844 | ||
2845 | input clk; | |
2846 | input en; | |
2847 | input se; | |
2848 | input scan_in; | |
2849 | input siclk; | |
2850 | input soclk; | |
2851 | input pce_ov; | |
2852 | input stop; | |
2853 | ||
2854 | ||
2855 | ||
2856 | output [54:0] dout; | |
2857 | ||
2858 | ||
2859 | output scan_out; | |
2860 | ||
2861 | ||
2862 | ||
2863 | ||
2864 | cl_dp1_l1hdr_8x c0_0 ( | |
2865 | .l2clk(clk), | |
2866 | .pce(en), | |
2867 | .aclk(siclk), | |
2868 | .bclk(soclk), | |
2869 | .l1clk(l1clk), | |
2870 | .se(se), | |
2871 | .pce_ov(pce_ov), | |
2872 | .stop(stop), | |
2873 | .siclk_out(siclk_out), | |
2874 | .soclk_out(soclk_out) | |
2875 | ); | |
2876 | dff #(55) d0_0 ( | |
2877 | .l1clk(l1clk), | |
2878 | .siclk(siclk_out), | |
2879 | .soclk(soclk_out), | |
2880 | .d(din[54:0]), | |
2881 | .si({scan_in,so[53:0]}), | |
2882 | .so({so[53:0],scan_out}), | |
2883 | .q(dout[54:0]) | |
2884 | ); | |
2885 | ||
2886 | ||
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | ||
2893 | ||
2894 | ||
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | ||
2902 | ||
2903 | ||
2904 | ||
2905 | endmodule | |
2906 | ||
2907 | ||
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
2916 | // also for pass-gate with decoder | |
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | ||
2922 | // any PARAMS parms go into naming of macro | |
2923 | ||
2924 | module lsu_dcs_dp_mux_macro__mux_aonpe__ports_5__stack_14l__width_13 ( | |
2925 | din0, | |
2926 | sel0, | |
2927 | din1, | |
2928 | sel1, | |
2929 | din2, | |
2930 | sel2, | |
2931 | din3, | |
2932 | sel3, | |
2933 | din4, | |
2934 | sel4, | |
2935 | dout); | |
2936 | wire buffout0; | |
2937 | wire buffout1; | |
2938 | wire buffout2; | |
2939 | wire buffout3; | |
2940 | wire buffout4; | |
2941 | ||
2942 | input [12:0] din0; | |
2943 | input sel0; | |
2944 | input [12:0] din1; | |
2945 | input sel1; | |
2946 | input [12:0] din2; | |
2947 | input sel2; | |
2948 | input [12:0] din3; | |
2949 | input sel3; | |
2950 | input [12:0] din4; | |
2951 | input sel4; | |
2952 | output [12:0] dout; | |
2953 | ||
2954 | ||
2955 | ||
2956 | ||
2957 | ||
2958 | cl_dp1_muxbuff5_8x c0_0 ( | |
2959 | .in0(sel0), | |
2960 | .in1(sel1), | |
2961 | .in2(sel2), | |
2962 | .in3(sel3), | |
2963 | .in4(sel4), | |
2964 | .out0(buffout0), | |
2965 | .out1(buffout1), | |
2966 | .out2(buffout2), | |
2967 | .out3(buffout3), | |
2968 | .out4(buffout4) | |
2969 | ); | |
2970 | mux5s #(13) d0_0 ( | |
2971 | .sel0(buffout0), | |
2972 | .sel1(buffout1), | |
2973 | .sel2(buffout2), | |
2974 | .sel3(buffout3), | |
2975 | .sel4(buffout4), | |
2976 | .in0(din0[12:0]), | |
2977 | .in1(din1[12:0]), | |
2978 | .in2(din2[12:0]), | |
2979 | .in3(din3[12:0]), | |
2980 | .in4(din4[12:0]), | |
2981 | .dout(dout[12:0]) | |
2982 | ); | |
2983 | ||
2984 | ||
2985 | ||
2986 | ||
2987 | ||
2988 | ||
2989 | ||
2990 | ||
2991 | ||
2992 | ||
2993 | ||
2994 | ||
2995 | ||
2996 | endmodule | |
2997 | ||
2998 | ||
2999 | ||
3000 | ||
3001 | ||
3002 | ||
3003 | // any PARAMS parms go into naming of macro | |
3004 | ||
3005 | module lsu_dcs_dp_msff_macro__left_17__mux_aope__ports_2__stack_64c__width_47 ( | |
3006 | din0, | |
3007 | din1, | |
3008 | sel0, | |
3009 | clk, | |
3010 | en, | |
3011 | se, | |
3012 | scan_in, | |
3013 | siclk, | |
3014 | soclk, | |
3015 | pce_ov, | |
3016 | stop, | |
3017 | dout, | |
3018 | scan_out); | |
3019 | wire psel0; | |
3020 | wire psel1; | |
3021 | wire [46:0] muxout; | |
3022 | wire l1clk; | |
3023 | wire siclk_out; | |
3024 | wire soclk_out; | |
3025 | wire [45:0] so; | |
3026 | ||
3027 | input [46:0] din0; | |
3028 | input [46:0] din1; | |
3029 | input sel0; | |
3030 | ||
3031 | ||
3032 | input clk; | |
3033 | input en; | |
3034 | input se; | |
3035 | input scan_in; | |
3036 | input siclk; | |
3037 | input soclk; | |
3038 | input pce_ov; | |
3039 | input stop; | |
3040 | ||
3041 | ||
3042 | ||
3043 | output [46:0] dout; | |
3044 | ||
3045 | ||
3046 | output scan_out; | |
3047 | ||
3048 | ||
3049 | ||
3050 | ||
3051 | cl_dp1_penc2_8x c1_0 ( | |
3052 | .sel0(sel0), | |
3053 | .psel0(psel0), | |
3054 | .psel1(psel1) | |
3055 | ); | |
3056 | ||
3057 | mux2s #(47) d1_0 ( | |
3058 | .sel0(psel0), | |
3059 | .sel1(psel1), | |
3060 | .in0(din0[46:0]), | |
3061 | .in1(din1[46:0]), | |
3062 | .dout(muxout[46:0]) | |
3063 | ); | |
3064 | cl_dp1_l1hdr_8x c0_0 ( | |
3065 | .l2clk(clk), | |
3066 | .pce(en), | |
3067 | .aclk(siclk), | |
3068 | .bclk(soclk), | |
3069 | .l1clk(l1clk), | |
3070 | .se(se), | |
3071 | .pce_ov(pce_ov), | |
3072 | .stop(stop), | |
3073 | .siclk_out(siclk_out), | |
3074 | .soclk_out(soclk_out) | |
3075 | ); | |
3076 | dff #(47) d0_0 ( | |
3077 | .l1clk(l1clk), | |
3078 | .siclk(siclk_out), | |
3079 | .soclk(soclk_out), | |
3080 | .d(muxout[46:0]), | |
3081 | .si({scan_in,so[45:0]}), | |
3082 | .so({so[45:0],scan_out}), | |
3083 | .q(dout[46:0]) | |
3084 | ); | |
3085 | ||
3086 | ||
3087 | ||
3088 | ||
3089 | ||
3090 | ||
3091 | ||
3092 | ||
3093 | ||
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | ||
3100 | ||
3101 | ||
3102 | ||
3103 | ||
3104 | ||
3105 | endmodule | |
3106 | ||
3107 | ||
3108 | ||
3109 | ||
3110 | ||
3111 | ||
3112 | ||
3113 | ||
3114 | ||
3115 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3116 | // also for pass-gate with decoder | |
3117 | ||
3118 | ||
3119 | ||
3120 | ||
3121 | ||
3122 | // any PARAMS parms go into naming of macro | |
3123 | ||
3124 | module lsu_dcs_dp_mux_macro__mux_aope__ports_8__stack_64c__width_64 ( | |
3125 | din0, | |
3126 | din1, | |
3127 | din2, | |
3128 | din3, | |
3129 | din4, | |
3130 | din5, | |
3131 | din6, | |
3132 | din7, | |
3133 | sel0, | |
3134 | sel1, | |
3135 | sel2, | |
3136 | sel3, | |
3137 | sel4, | |
3138 | sel5, | |
3139 | sel6, | |
3140 | dout); | |
3141 | wire psel0; | |
3142 | wire psel1; | |
3143 | wire psel2; | |
3144 | wire psel3; | |
3145 | wire psel4; | |
3146 | wire psel5; | |
3147 | wire psel6; | |
3148 | wire psel7; | |
3149 | ||
3150 | input [63:0] din0; | |
3151 | input [63:0] din1; | |
3152 | input [63:0] din2; | |
3153 | input [63:0] din3; | |
3154 | input [63:0] din4; | |
3155 | input [63:0] din5; | |
3156 | input [63:0] din6; | |
3157 | input [63:0] din7; | |
3158 | input sel0; | |
3159 | input sel1; | |
3160 | input sel2; | |
3161 | input sel3; | |
3162 | input sel4; | |
3163 | input sel5; | |
3164 | input sel6; | |
3165 | output [63:0] dout; | |
3166 | ||
3167 | ||
3168 | ||
3169 | ||
3170 | ||
3171 | cl_dp1_penc8_8x c0_0 ( | |
3172 | .test(1'b1), | |
3173 | .sel0(sel0), | |
3174 | .sel1(sel1), | |
3175 | .sel2(sel2), | |
3176 | .sel3(sel3), | |
3177 | .sel4(sel4), | |
3178 | .sel5(sel5), | |
3179 | .sel6(sel6), | |
3180 | .psel0(psel0), | |
3181 | .psel1(psel1), | |
3182 | .psel2(psel2), | |
3183 | .psel3(psel3), | |
3184 | .psel4(psel4), | |
3185 | .psel5(psel5), | |
3186 | .psel6(psel6), | |
3187 | .psel7(psel7) | |
3188 | ); | |
3189 | ||
3190 | mux8s #(64) d0_0 ( | |
3191 | .sel0(psel0), | |
3192 | .sel1(psel1), | |
3193 | .sel2(psel2), | |
3194 | .sel3(psel3), | |
3195 | .sel4(psel4), | |
3196 | .sel5(psel5), | |
3197 | .sel6(psel6), | |
3198 | .sel7(psel7), | |
3199 | .in0(din0[63:0]), | |
3200 | .in1(din1[63:0]), | |
3201 | .in2(din2[63:0]), | |
3202 | .in3(din3[63:0]), | |
3203 | .in4(din4[63:0]), | |
3204 | .in5(din5[63:0]), | |
3205 | .in6(din6[63:0]), | |
3206 | .in7(din7[63:0]), | |
3207 | .dout(dout[63:0]) | |
3208 | ); | |
3209 | ||
3210 | ||
3211 | ||
3212 | ||
3213 | ||
3214 | ||
3215 | ||
3216 | ||
3217 | ||
3218 | ||
3219 | ||
3220 | ||
3221 | ||
3222 | endmodule | |
3223 | ||
3224 | ||
3225 | ||
3226 | ||
3227 | ||
3228 | ||
3229 | // any PARAMS parms go into naming of macro | |
3230 | ||
3231 | module lsu_dcs_dp_msff_macro__mux_aope__ports_3__stack_64c__width_64 ( | |
3232 | din0, | |
3233 | din1, | |
3234 | din2, | |
3235 | sel0, | |
3236 | sel1, | |
3237 | clk, | |
3238 | en, | |
3239 | se, | |
3240 | scan_in, | |
3241 | siclk, | |
3242 | soclk, | |
3243 | pce_ov, | |
3244 | stop, | |
3245 | dout, | |
3246 | scan_out); | |
3247 | wire psel0; | |
3248 | wire psel1; | |
3249 | wire psel2; | |
3250 | wire [63:0] muxout; | |
3251 | wire l1clk; | |
3252 | wire siclk_out; | |
3253 | wire soclk_out; | |
3254 | wire [62:0] so; | |
3255 | ||
3256 | input [63:0] din0; | |
3257 | input [63:0] din1; | |
3258 | input [63:0] din2; | |
3259 | input sel0; | |
3260 | input sel1; | |
3261 | ||
3262 | ||
3263 | input clk; | |
3264 | input en; | |
3265 | input se; | |
3266 | input scan_in; | |
3267 | input siclk; | |
3268 | input soclk; | |
3269 | input pce_ov; | |
3270 | input stop; | |
3271 | ||
3272 | ||
3273 | ||
3274 | output [63:0] dout; | |
3275 | ||
3276 | ||
3277 | output scan_out; | |
3278 | ||
3279 | ||
3280 | ||
3281 | ||
3282 | cl_dp1_penc3_8x c1_0 ( | |
3283 | .test(1'b1), | |
3284 | .sel0(sel0), | |
3285 | .sel1(sel1), | |
3286 | .psel0(psel0), | |
3287 | .psel1(psel1), | |
3288 | .psel2(psel2) | |
3289 | ); | |
3290 | ||
3291 | mux3s #(64) d1_0 ( | |
3292 | .sel0(psel0), | |
3293 | .sel1(psel1), | |
3294 | .sel2(psel2), | |
3295 | .in0(din0[63:0]), | |
3296 | .in1(din1[63:0]), | |
3297 | .in2(din2[63:0]), | |
3298 | .dout(muxout[63:0]) | |
3299 | ); | |
3300 | cl_dp1_l1hdr_8x c0_0 ( | |
3301 | .l2clk(clk), | |
3302 | .pce(en), | |
3303 | .aclk(siclk), | |
3304 | .bclk(soclk), | |
3305 | .l1clk(l1clk), | |
3306 | .se(se), | |
3307 | .pce_ov(pce_ov), | |
3308 | .stop(stop), | |
3309 | .siclk_out(siclk_out), | |
3310 | .soclk_out(soclk_out) | |
3311 | ); | |
3312 | dff #(64) d0_0 ( | |
3313 | .l1clk(l1clk), | |
3314 | .siclk(siclk_out), | |
3315 | .soclk(soclk_out), | |
3316 | .d(muxout[63:0]), | |
3317 | .si({scan_in,so[62:0]}), | |
3318 | .so({so[62:0],scan_out}), | |
3319 | .q(dout[63:0]) | |
3320 | ); | |
3321 | ||
3322 | ||
3323 | ||
3324 | ||
3325 | ||
3326 | ||
3327 | ||
3328 | ||
3329 | ||
3330 | ||
3331 | ||
3332 | ||
3333 | ||
3334 | ||
3335 | ||
3336 | ||
3337 | ||
3338 | ||
3339 | ||
3340 | ||
3341 | endmodule | |
3342 | ||
3343 | ||
3344 | ||
3345 | ||
3346 | ||
3347 | ||
3348 | ||
3349 | ||
3350 | ||
3351 | ||
3352 | ||
3353 | ||
3354 | ||
3355 | // any PARAMS parms go into naming of macro | |
3356 | ||
3357 | module lsu_dcs_dp_msff_macro__left_18__stack_64c__width_45 ( | |
3358 | din, | |
3359 | clk, | |
3360 | en, | |
3361 | se, | |
3362 | scan_in, | |
3363 | siclk, | |
3364 | soclk, | |
3365 | pce_ov, | |
3366 | stop, | |
3367 | dout, | |
3368 | scan_out); | |
3369 | wire l1clk; | |
3370 | wire siclk_out; | |
3371 | wire soclk_out; | |
3372 | wire [43:0] so; | |
3373 | ||
3374 | input [44:0] din; | |
3375 | ||
3376 | ||
3377 | input clk; | |
3378 | input en; | |
3379 | input se; | |
3380 | input scan_in; | |
3381 | input siclk; | |
3382 | input soclk; | |
3383 | input pce_ov; | |
3384 | input stop; | |
3385 | ||
3386 | ||
3387 | ||
3388 | output [44:0] dout; | |
3389 | ||
3390 | ||
3391 | output scan_out; | |
3392 | ||
3393 | ||
3394 | ||
3395 | ||
3396 | cl_dp1_l1hdr_8x c0_0 ( | |
3397 | .l2clk(clk), | |
3398 | .pce(en), | |
3399 | .aclk(siclk), | |
3400 | .bclk(soclk), | |
3401 | .l1clk(l1clk), | |
3402 | .se(se), | |
3403 | .pce_ov(pce_ov), | |
3404 | .stop(stop), | |
3405 | .siclk_out(siclk_out), | |
3406 | .soclk_out(soclk_out) | |
3407 | ); | |
3408 | dff #(45) d0_0 ( | |
3409 | .l1clk(l1clk), | |
3410 | .siclk(siclk_out), | |
3411 | .soclk(soclk_out), | |
3412 | .d(din[44:0]), | |
3413 | .si({scan_in,so[43:0]}), | |
3414 | .so({so[43:0],scan_out}), | |
3415 | .q(dout[44:0]) | |
3416 | ); | |
3417 | ||
3418 | ||
3419 | ||
3420 | ||
3421 | ||
3422 | ||
3423 | ||
3424 | ||
3425 | ||
3426 | ||
3427 | ||
3428 | ||
3429 | ||
3430 | ||
3431 | ||
3432 | ||
3433 | ||
3434 | ||
3435 | ||
3436 | ||
3437 | endmodule | |
3438 | ||
3439 | ||
3440 | ||
3441 | ||
3442 | ||
3443 | ||
3444 | ||
3445 | ||
3446 | ||
3447 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3448 | // also for pass-gate with decoder | |
3449 | ||
3450 | ||
3451 | ||
3452 | ||
3453 | ||
3454 | // any PARAMS parms go into naming of macro | |
3455 | ||
3456 | module lsu_dcs_dp_mux_macro__left_18__mux_aodec__ports_8__stack_64c__width_45 ( | |
3457 | din0, | |
3458 | din1, | |
3459 | din2, | |
3460 | din3, | |
3461 | din4, | |
3462 | din5, | |
3463 | din6, | |
3464 | din7, | |
3465 | sel, | |
3466 | dout); | |
3467 | wire psel0; | |
3468 | wire psel1; | |
3469 | wire psel2; | |
3470 | wire psel3; | |
3471 | wire psel4; | |
3472 | wire psel5; | |
3473 | wire psel6; | |
3474 | wire psel7; | |
3475 | ||
3476 | input [44:0] din0; | |
3477 | input [44:0] din1; | |
3478 | input [44:0] din2; | |
3479 | input [44:0] din3; | |
3480 | input [44:0] din4; | |
3481 | input [44:0] din5; | |
3482 | input [44:0] din6; | |
3483 | input [44:0] din7; | |
3484 | input [2:0] sel; | |
3485 | output [44:0] dout; | |
3486 | ||
3487 | ||
3488 | ||
3489 | ||
3490 | ||
3491 | cl_dp1_pdec8_8x c0_0 ( | |
3492 | .test(1'b1), | |
3493 | .sel0(sel[0]), | |
3494 | .sel1(sel[1]), | |
3495 | .sel2(sel[2]), | |
3496 | .psel0(psel0), | |
3497 | .psel1(psel1), | |
3498 | .psel2(psel2), | |
3499 | .psel3(psel3), | |
3500 | .psel4(psel4), | |
3501 | .psel5(psel5), | |
3502 | .psel6(psel6), | |
3503 | .psel7(psel7) | |
3504 | ); | |
3505 | ||
3506 | mux8s #(45) d0_0 ( | |
3507 | .sel0(psel0), | |
3508 | .sel1(psel1), | |
3509 | .sel2(psel2), | |
3510 | .sel3(psel3), | |
3511 | .sel4(psel4), | |
3512 | .sel5(psel5), | |
3513 | .sel6(psel6), | |
3514 | .sel7(psel7), | |
3515 | .in0(din0[44:0]), | |
3516 | .in1(din1[44:0]), | |
3517 | .in2(din2[44:0]), | |
3518 | .in3(din3[44:0]), | |
3519 | .in4(din4[44:0]), | |
3520 | .in5(din5[44:0]), | |
3521 | .in6(din6[44:0]), | |
3522 | .in7(din7[44:0]), | |
3523 | .dout(dout[44:0]) | |
3524 | ); | |
3525 | ||
3526 | ||
3527 | ||
3528 | ||
3529 | ||
3530 | ||
3531 | ||
3532 | ||
3533 | ||
3534 | ||
3535 | ||
3536 | ||
3537 | ||
3538 | endmodule | |
3539 | ||
3540 | ||
3541 | // | |
3542 | // buff macro | |
3543 | // | |
3544 | // | |
3545 | ||
3546 | ||
3547 | ||
3548 | ||
3549 | ||
3550 | module lsu_dcs_dp_buff_macro__left_18__stack_64c__width_45 ( | |
3551 | din, | |
3552 | dout); | |
3553 | input [44:0] din; | |
3554 | output [44:0] dout; | |
3555 | ||
3556 | ||
3557 | ||
3558 | ||
3559 | ||
3560 | ||
3561 | buff #(45) d0_0 ( | |
3562 | .in(din[44:0]), | |
3563 | .out(dout[44:0]) | |
3564 | ); | |
3565 | ||
3566 | ||
3567 | ||
3568 | ||
3569 | ||
3570 | ||
3571 | ||
3572 | ||
3573 | endmodule | |
3574 | ||
3575 | ||
3576 | ||
3577 | ||
3578 | ||
3579 | // | |
3580 | // and macro for ports = 2,3,4 | |
3581 | // | |
3582 | // | |
3583 | ||
3584 | ||
3585 | ||
3586 | ||
3587 | ||
3588 | module lsu_dcs_dp_and_macro__ports_2__stack_18r__width_17 ( | |
3589 | din0, | |
3590 | din1, | |
3591 | dout); | |
3592 | input [16:0] din0; | |
3593 | input [16:0] din1; | |
3594 | output [16:0] dout; | |
3595 | ||
3596 | ||
3597 | ||
3598 | ||
3599 | ||
3600 | ||
3601 | and2 #(17) d0_0 ( | |
3602 | .in0(din0[16:0]), | |
3603 | .in1(din1[16:0]), | |
3604 | .out(dout[16:0]) | |
3605 | ); | |
3606 | ||
3607 | ||
3608 | ||
3609 | ||
3610 | ||
3611 | ||
3612 | ||
3613 | ||
3614 | ||
3615 | endmodule | |
3616 | ||
3617 | ||
3618 | ||
3619 | ||
3620 | ||
3621 | ||
3622 | ||
3623 | ||
3624 | ||
3625 | // any PARAMS parms go into naming of macro | |
3626 | ||
3627 | module lsu_dcs_dp_msff_macro__stack_18r__width_17 ( | |
3628 | din, | |
3629 | clk, | |
3630 | en, | |
3631 | se, | |
3632 | scan_in, | |
3633 | siclk, | |
3634 | soclk, | |
3635 | pce_ov, | |
3636 | stop, | |
3637 | dout, | |
3638 | scan_out); | |
3639 | wire l1clk; | |
3640 | wire siclk_out; | |
3641 | wire soclk_out; | |
3642 | wire [15:0] so; | |
3643 | ||
3644 | input [16:0] din; | |
3645 | ||
3646 | ||
3647 | input clk; | |
3648 | input en; | |
3649 | input se; | |
3650 | input scan_in; | |
3651 | input siclk; | |
3652 | input soclk; | |
3653 | input pce_ov; | |
3654 | input stop; | |
3655 | ||
3656 | ||
3657 | ||
3658 | output [16:0] dout; | |
3659 | ||
3660 | ||
3661 | output scan_out; | |
3662 | ||
3663 | ||
3664 | ||
3665 | ||
3666 | cl_dp1_l1hdr_8x c0_0 ( | |
3667 | .l2clk(clk), | |
3668 | .pce(en), | |
3669 | .aclk(siclk), | |
3670 | .bclk(soclk), | |
3671 | .l1clk(l1clk), | |
3672 | .se(se), | |
3673 | .pce_ov(pce_ov), | |
3674 | .stop(stop), | |
3675 | .siclk_out(siclk_out), | |
3676 | .soclk_out(soclk_out) | |
3677 | ); | |
3678 | dff #(17) d0_0 ( | |
3679 | .l1clk(l1clk), | |
3680 | .siclk(siclk_out), | |
3681 | .soclk(soclk_out), | |
3682 | .d(din[16:0]), | |
3683 | .si({scan_in,so[15:0]}), | |
3684 | .so({so[15:0],scan_out}), | |
3685 | .q(dout[16:0]) | |
3686 | ); | |
3687 | ||
3688 | ||
3689 | ||
3690 | ||
3691 | ||
3692 | ||
3693 | ||
3694 | ||
3695 | ||
3696 | ||
3697 | ||
3698 | ||
3699 | ||
3700 | ||
3701 | ||
3702 | ||
3703 | ||
3704 | ||
3705 | ||
3706 | ||
3707 | endmodule | |
3708 | ||
3709 | ||
3710 | ||
3711 | ||
3712 | ||
3713 | ||
3714 | ||
3715 | ||
3716 | ||
3717 | // | |
3718 | // buff macro | |
3719 | // | |
3720 | // | |
3721 | ||
3722 | ||
3723 | ||
3724 | ||
3725 | ||
3726 | module lsu_dcs_dp_buff_macro__stack_4l__width_3 ( | |
3727 | din, | |
3728 | dout); | |
3729 | input [2:0] din; | |
3730 | output [2:0] dout; | |
3731 | ||
3732 | ||
3733 | ||
3734 | ||
3735 | ||
3736 | ||
3737 | buff #(3) d0_0 ( | |
3738 | .in(din[2:0]), | |
3739 | .out(dout[2:0]) | |
3740 | ); | |
3741 | ||
3742 | ||
3743 | ||
3744 | ||
3745 | ||
3746 | ||
3747 | ||
3748 | ||
3749 | endmodule | |
3750 | ||
3751 | ||
3752 | ||
3753 | ||
3754 | ||
3755 | // general mux macro for pass-gate and and-or muxes with/wout priority encoders | |
3756 | // also for pass-gate with decoder | |
3757 | ||
3758 | ||
3759 | ||
3760 | ||
3761 | ||
3762 | // any PARAMS parms go into naming of macro | |
3763 | ||
3764 | module lsu_dcs_dp_mux_macro__mux_aodec__ports_8__stack_18r__width_17 ( | |
3765 | din0, | |
3766 | din1, | |
3767 | din2, | |
3768 | din3, | |
3769 | din4, | |
3770 | din5, | |
3771 | din6, | |
3772 | din7, | |
3773 | sel, | |
3774 | dout); | |
3775 | wire psel0; | |
3776 | wire psel1; | |
3777 | wire psel2; | |
3778 | wire psel3; | |
3779 | wire psel4; | |
3780 | wire psel5; | |
3781 | wire psel6; | |
3782 | wire psel7; | |
3783 | ||
3784 | input [16:0] din0; | |
3785 | input [16:0] din1; | |
3786 | input [16:0] din2; | |
3787 | input [16:0] din3; | |
3788 | input [16:0] din4; | |
3789 | input [16:0] din5; | |
3790 | input [16:0] din6; | |
3791 | input [16:0] din7; | |
3792 | input [2:0] sel; | |
3793 | output [16:0] dout; | |
3794 | ||
3795 | ||
3796 | ||
3797 | ||
3798 | ||
3799 | cl_dp1_pdec8_8x c0_0 ( | |
3800 | .test(1'b1), | |
3801 | .sel0(sel[0]), | |
3802 | .sel1(sel[1]), | |
3803 | .sel2(sel[2]), | |
3804 | .psel0(psel0), | |
3805 | .psel1(psel1), | |
3806 | .psel2(psel2), | |
3807 | .psel3(psel3), | |
3808 | .psel4(psel4), | |
3809 | .psel5(psel5), | |
3810 | .psel6(psel6), | |
3811 | .psel7(psel7) | |
3812 | ); | |
3813 | ||
3814 | mux8s #(17) d0_0 ( | |
3815 | .sel0(psel0), | |
3816 | .sel1(psel1), | |
3817 | .sel2(psel2), | |
3818 | .sel3(psel3), | |
3819 | .sel4(psel4), | |
3820 | .sel5(psel5), | |
3821 | .sel6(psel6), | |
3822 | .sel7(psel7), | |
3823 | .in0(din0[16:0]), | |
3824 | .in1(din1[16:0]), | |
3825 | .in2(din2[16:0]), | |
3826 | .in3(din3[16:0]), | |
3827 | .in4(din4[16:0]), | |
3828 | .in5(din5[16:0]), | |
3829 | .in6(din6[16:0]), | |
3830 | .in7(din7[16:0]), | |
3831 | .dout(dout[16:0]) | |
3832 | ); | |
3833 | ||
3834 | ||
3835 | ||
3836 | ||
3837 | ||
3838 | ||
3839 | ||
3840 | ||
3841 | ||
3842 | ||
3843 | ||
3844 | ||
3845 | ||
3846 | endmodule | |
3847 | ||
3848 | ||
3849 | // | |
3850 | // buff macro | |
3851 | // | |
3852 | // | |
3853 | ||
3854 | ||
3855 | ||
3856 | ||
3857 | ||
3858 | module lsu_dcs_dp_buff_macro__stack_18r__width_17 ( | |
3859 | din, | |
3860 | dout); | |
3861 | input [16:0] din; | |
3862 | output [16:0] dout; | |
3863 | ||
3864 | ||
3865 | ||
3866 | ||
3867 | ||
3868 | ||
3869 | buff #(17) d0_0 ( | |
3870 | .in(din[16:0]), | |
3871 | .out(dout[16:0]) | |
3872 | ); | |
3873 | ||
3874 | ||
3875 | ||
3876 | ||
3877 | ||
3878 | ||
3879 | ||
3880 | ||
3881 | endmodule | |
3882 | ||
3883 | ||
3884 | ||
3885 | ||
3886 | ||
3887 | ||
3888 | ||
3889 | ||
3890 | ||
3891 | // any PARAMS parms go into naming of macro | |
3892 | ||
3893 | module lsu_dcs_dp_msff_macro__stack_64c__width_32 ( | |
3894 | din, | |
3895 | clk, | |
3896 | en, | |
3897 | se, | |
3898 | scan_in, | |
3899 | siclk, | |
3900 | soclk, | |
3901 | pce_ov, | |
3902 | stop, | |
3903 | dout, | |
3904 | scan_out); | |
3905 | wire l1clk; | |
3906 | wire siclk_out; | |
3907 | wire soclk_out; | |
3908 | wire [30:0] so; | |
3909 | ||
3910 | input [31:0] din; | |
3911 | ||
3912 | ||
3913 | input clk; | |
3914 | input en; | |
3915 | input se; | |
3916 | input scan_in; | |
3917 | input siclk; | |
3918 | input soclk; | |
3919 | input pce_ov; | |
3920 | input stop; | |
3921 | ||
3922 | ||
3923 | ||
3924 | output [31:0] dout; | |
3925 | ||
3926 | ||
3927 | output scan_out; | |
3928 | ||
3929 | ||
3930 | ||
3931 | ||
3932 | cl_dp1_l1hdr_8x c0_0 ( | |
3933 | .l2clk(clk), | |
3934 | .pce(en), | |
3935 | .aclk(siclk), | |
3936 | .bclk(soclk), | |
3937 | .l1clk(l1clk), | |
3938 | .se(se), | |
3939 | .pce_ov(pce_ov), | |
3940 | .stop(stop), | |
3941 | .siclk_out(siclk_out), | |
3942 | .soclk_out(soclk_out) | |
3943 | ); | |
3944 | dff #(32) d0_0 ( | |
3945 | .l1clk(l1clk), | |
3946 | .siclk(siclk_out), | |
3947 | .soclk(soclk_out), | |
3948 | .d(din[31:0]), | |
3949 | .si({scan_in,so[30:0]}), | |
3950 | .so({so[30:0],scan_out}), | |
3951 | .q(dout[31:0]) | |
3952 | ); | |
3953 | ||
3954 | ||
3955 | ||
3956 | ||
3957 | ||
3958 | ||
3959 | ||
3960 | ||
3961 | ||
3962 | ||
3963 | ||
3964 | ||
3965 | ||
3966 | ||
3967 | ||
3968 | ||
3969 | ||
3970 | ||
3971 | ||
3972 | ||
3973 | endmodule | |
3974 | ||
3975 | ||
3976 | ||
3977 | ||
3978 | ||
3979 | ||
3980 | ||
3981 | ||
3982 | ||
3983 | // | |
3984 | // buff macro | |
3985 | // | |
3986 | // | |
3987 | ||
3988 | ||
3989 | ||
3990 | ||
3991 | ||
3992 | module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_64c__width_32 ( | |
3993 | din, | |
3994 | dout); | |
3995 | input [31:0] din; | |
3996 | output [31:0] dout; | |
3997 | ||
3998 | ||
3999 | ||
4000 | ||
4001 | ||
4002 | ||
4003 | buff #(32) d0_0 ( | |
4004 | .in(din[31:0]), | |
4005 | .out(dout[31:0]) | |
4006 | ); | |
4007 | ||
4008 | ||
4009 | ||
4010 | ||
4011 | ||
4012 | ||
4013 | ||
4014 | ||
4015 | endmodule | |
4016 | ||
4017 | ||
4018 | ||
4019 | ||
4020 | ||
4021 | ||
4022 | ||
4023 | ||
4024 | ||
4025 | // any PARAMS parms go into naming of macro | |
4026 | ||
4027 | module lsu_dcs_dp_msff_macro__stack_16r__width_16 ( | |
4028 | din, | |
4029 | clk, | |
4030 | en, | |
4031 | se, | |
4032 | scan_in, | |
4033 | siclk, | |
4034 | soclk, | |
4035 | pce_ov, | |
4036 | stop, | |
4037 | dout, | |
4038 | scan_out); | |
4039 | wire l1clk; | |
4040 | wire siclk_out; | |
4041 | wire soclk_out; | |
4042 | wire [14:0] so; | |
4043 | ||
4044 | input [15:0] din; | |
4045 | ||
4046 | ||
4047 | input clk; | |
4048 | input en; | |
4049 | input se; | |
4050 | input scan_in; | |
4051 | input siclk; | |
4052 | input soclk; | |
4053 | input pce_ov; | |
4054 | input stop; | |
4055 | ||
4056 | ||
4057 | ||
4058 | output [15:0] dout; | |
4059 | ||
4060 | ||
4061 | output scan_out; | |
4062 | ||
4063 | ||
4064 | ||
4065 | ||
4066 | cl_dp1_l1hdr_8x c0_0 ( | |
4067 | .l2clk(clk), | |
4068 | .pce(en), | |
4069 | .aclk(siclk), | |
4070 | .bclk(soclk), | |
4071 | .l1clk(l1clk), | |
4072 | .se(se), | |
4073 | .pce_ov(pce_ov), | |
4074 | .stop(stop), | |
4075 | .siclk_out(siclk_out), | |
4076 | .soclk_out(soclk_out) | |
4077 | ); | |
4078 | dff #(16) d0_0 ( | |
4079 | .l1clk(l1clk), | |
4080 | .siclk(siclk_out), | |
4081 | .soclk(soclk_out), | |
4082 | .d(din[15:0]), | |
4083 | .si({scan_in,so[14:0]}), | |
4084 | .so({so[14:0],scan_out}), | |
4085 | .q(dout[15:0]) | |
4086 | ); | |
4087 | ||
4088 | ||
4089 | ||
4090 | ||
4091 | ||
4092 | ||
4093 | ||
4094 | ||
4095 | ||
4096 | ||
4097 | ||
4098 | ||
4099 | ||
4100 | ||
4101 | ||
4102 | ||
4103 | ||
4104 | ||
4105 | ||
4106 | ||
4107 | endmodule | |
4108 | ||
4109 | ||
4110 | ||
4111 | ||
4112 | ||
4113 | ||
4114 | ||
4115 | ||
4116 | ||
4117 | // | |
4118 | // buff macro | |
4119 | // | |
4120 | // | |
4121 | ||
4122 | ||
4123 | ||
4124 | ||
4125 | ||
4126 | module lsu_dcs_dp_buff_macro__dbuff_16x__rep_1__stack_16r__width_16 ( | |
4127 | din, | |
4128 | dout); | |
4129 | input [15:0] din; | |
4130 | output [15:0] dout; | |
4131 | ||
4132 | ||
4133 | ||
4134 | ||
4135 | ||
4136 | ||
4137 | buff #(16) d0_0 ( | |
4138 | .in(din[15:0]), | |
4139 | .out(dout[15:0]) | |
4140 | ); | |
4141 | ||
4142 | ||
4143 | ||
4144 | ||
4145 | ||
4146 | ||
4147 | ||
4148 | ||
4149 | endmodule | |
4150 | ||
4151 | ||
4152 | ||
4153 | ||
4154 | ||
4155 | ||
4156 | ||
4157 | ||
4158 | ||
4159 | // any PARAMS parms go into naming of macro | |
4160 | ||
4161 | module lsu_dcs_dp_msff_macro__stack_48c__width_37 ( | |
4162 | din, | |
4163 | clk, | |
4164 | en, | |
4165 | se, | |
4166 | scan_in, | |
4167 | siclk, | |
4168 | soclk, | |
4169 | pce_ov, | |
4170 | stop, | |
4171 | dout, | |
4172 | scan_out); | |
4173 | wire l1clk; | |
4174 | wire siclk_out; | |
4175 | wire soclk_out; | |
4176 | wire [35:0] so; | |
4177 | ||
4178 | input [36:0] din; | |
4179 | ||
4180 | ||
4181 | input clk; | |
4182 | input en; | |
4183 | input se; | |
4184 | input scan_in; | |
4185 | input siclk; | |
4186 | input soclk; | |
4187 | input pce_ov; | |
4188 | input stop; | |
4189 | ||
4190 | ||
4191 | ||
4192 | output [36:0] dout; | |
4193 | ||
4194 | ||
4195 | output scan_out; | |
4196 | ||
4197 | ||
4198 | ||
4199 | ||
4200 | cl_dp1_l1hdr_8x c0_0 ( | |
4201 | .l2clk(clk), | |
4202 | .pce(en), | |
4203 | .aclk(siclk), | |
4204 | .bclk(soclk), | |
4205 | .l1clk(l1clk), | |
4206 | .se(se), | |
4207 | .pce_ov(pce_ov), | |
4208 | .stop(stop), | |
4209 | .siclk_out(siclk_out), | |
4210 | .soclk_out(soclk_out) | |
4211 | ); | |
4212 | dff #(37) d0_0 ( | |
4213 | .l1clk(l1clk), | |
4214 | .siclk(siclk_out), | |
4215 | .soclk(soclk_out), | |
4216 | .d(din[36:0]), | |
4217 | .si({scan_in,so[35:0]}), | |
4218 | .so({so[35:0],scan_out}), | |
4219 | .q(dout[36:0]) | |
4220 | ); | |
4221 | ||
4222 | ||
4223 | ||
4224 | ||
4225 | ||
4226 | ||
4227 | ||
4228 | ||
4229 | ||
4230 | ||
4231 | ||
4232 | ||
4233 | ||
4234 | ||
4235 | ||
4236 | ||
4237 | ||
4238 | ||
4239 | ||
4240 | ||
4241 | endmodule | |
4242 | ||
4243 | ||
4244 | ||
4245 | ||
4246 | ||
4247 | ||
4248 | ||
4249 | ||
4250 | ||
4251 | // | |
4252 | // buff macro | |
4253 | // | |
4254 | // | |
4255 | ||
4256 | ||
4257 | ||
4258 | ||
4259 | ||
4260 | module lsu_dcs_dp_buff_macro__stack_48c__width_21 ( | |
4261 | din, | |
4262 | dout); | |
4263 | input [20:0] din; | |
4264 | output [20:0] dout; | |
4265 | ||
4266 | ||
4267 | ||
4268 | ||
4269 | ||
4270 | ||
4271 | buff #(21) d0_0 ( | |
4272 | .in(din[20:0]), | |
4273 | .out(dout[20:0]) | |
4274 | ); | |
4275 | ||
4276 | ||
4277 | ||
4278 | ||
4279 | ||
4280 | ||
4281 | ||
4282 | ||
4283 | endmodule | |
4284 | ||
4285 | ||
4286 | ||
4287 |