Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_lmc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_lmc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | scan_out, | |
43 | dcc_tid_m, | |
44 | dcc_ld_inst_vld_m, | |
45 | dcc_pref_inst_m, | |
46 | dcc_ld_miss_b, | |
47 | dcc_ld_miss_ldd, | |
48 | dcc_asi_load_b, | |
49 | dcc_asi_iomap_b, | |
50 | dcc_blk_inst_b, | |
51 | dcc_ldbl_b, | |
52 | dcc_ncache_b, | |
53 | dcc_ld_miss_ctl_b43, | |
54 | dcc_atomic_b, | |
55 | dcc_casa_inst_b, | |
56 | dcc_lsu_asi_rd_b, | |
57 | dcc_lsu_asi_sel_w, | |
58 | dcc_ceter_wr_w, | |
59 | dcc_stb_diag_sel_w3, | |
60 | dcc_exception_flush_b, | |
61 | dcc_perror_b, | |
62 | dcc_sync_pipe_w, | |
63 | dcc_cache_diag_wr_b, | |
64 | dcc_asi_rtn_vld, | |
65 | dcc_asi_rtn_excp, | |
66 | dcc_asi_rtn_rd, | |
67 | pic_casa_squash_req, | |
68 | pic_early_ld_b_sel_p3, | |
69 | pic_no_load_p3, | |
70 | pic_asi_busy, | |
71 | lmd_pcx_pref, | |
72 | lmd_asi_ld, | |
73 | lmd_asi_indet, | |
74 | lmd_sec_cmp_b, | |
75 | lmd_addrb2, | |
76 | lmd_sz_b1, | |
77 | lmd_sz_b0, | |
78 | lmd_ldbl, | |
79 | lmd_rd_e, | |
80 | lmd_dc_err_e, | |
81 | lmd_fill_addr_b3_e, | |
82 | lmd_fill_sz_b0_e, | |
83 | tlb_pgnum_b39, | |
84 | tlb_cam_mhit, | |
85 | tlu_flush_lsu_b, | |
86 | tlu_cerer_sbdlc, | |
87 | tlu_cerer_sbdlu, | |
88 | tlu_cerer_dcl2c, | |
89 | tlu_cerer_dcl2u, | |
90 | tlu_cerer_dcl2nd, | |
91 | tlu_cerer_l2c_socc, | |
92 | tlu_cerer_l2u_socu, | |
93 | dec_flush_lm, | |
94 | dec_flush_lb, | |
95 | dec_ld_inst_d, | |
96 | cic_l2fill_vld_e, | |
97 | cic_cpq_ld_rdy, | |
98 | cic_cpq_ld_rdy_, | |
99 | cic_div_stall_d, | |
100 | cic_oddrd_e, | |
101 | cic_xinval_e, | |
102 | cic_xinval, | |
103 | cic_set_inval, | |
104 | cic_rtn_cmplt, | |
105 | cic_cpq_stall, | |
106 | cic_ext_interrupt, | |
107 | cid_tid, | |
108 | cid_err, | |
109 | cid_dcsoc_err_e, | |
110 | cid_l2miss, | |
111 | stb_cam_hit, | |
112 | stb_cam_mhit, | |
113 | stb_ld_part_raw, | |
114 | stb_cecc_err, | |
115 | stb_uecc_err, | |
116 | sbd_st_data_b_62, | |
117 | sbs_all_commited, | |
118 | sbc_st_atom_p3, | |
119 | sbc_rawp_rst, | |
120 | sbc_st_sel_tid_p4, | |
121 | sbc_force_inv, | |
122 | sbc_kill_store_p4_, | |
123 | lsu_lsu_pmen, | |
124 | lmc_lmq_enable_b, | |
125 | lmc_pcx_sel_p4, | |
126 | lmc_pcx_rq_vld, | |
127 | lmc_asi_rq_vld, | |
128 | lmc_ld_rq_p3, | |
129 | lmc_ld_vld_p4, | |
130 | lmc_ld_no_req_p4, | |
131 | lmc_ld_inv_p4, | |
132 | lmc_ld_tid, | |
133 | lmc_byp_sel_e, | |
134 | lmc_cpq_tid_m, | |
135 | lmc_lmq_bypass_en, | |
136 | lmc_asi_bypass_m, | |
137 | lmc_bld_addr54, | |
138 | lmc_bld_req, | |
139 | lmc_bld_req_, | |
140 | lmc_bld_annul, | |
141 | lmc_bld_miss_e, | |
142 | lmc_bld_last_e, | |
143 | lmc_rd_update, | |
144 | lmc_pref_issued, | |
145 | lmc_ldd_vld, | |
146 | lmc_ld_unfilled, | |
147 | lmc_lmd_ncache_b, | |
148 | lmc_ld_sz, | |
149 | lmc_ld_inst_w, | |
150 | lmc_full_raw_w, | |
151 | lmc_ld_stall, | |
152 | lmc_l2_err_noup, | |
153 | lmc_l2_uerr, | |
154 | lmc_byp_data_hi, | |
155 | lmc_byp_data_enable, | |
156 | lmc_thrd_byp_sel_e, | |
157 | lmc_thrd_byp_sel_m, | |
158 | lmc_byp_tid_m, | |
159 | lmc_byp_vld_m, | |
160 | lmc_lmq0_byp_sel, | |
161 | lmc_lmq1_byp_sel, | |
162 | lmc_lmq2_byp_sel, | |
163 | lmc_lmq3_byp_sel, | |
164 | lmc_lmq4_byp_sel, | |
165 | lmc_lmq5_byp_sel, | |
166 | lmc_lmq6_byp_sel, | |
167 | lmc_lmq7_byp_sel, | |
168 | lmc_asi_indet_retire, | |
169 | lsu_ifu_no_miss, | |
170 | lsu_dcmh_err_g, | |
171 | lsu_dcvp_err_g, | |
172 | lsu_dctp_err_g, | |
173 | lsu_dcdp_err_g, | |
174 | lsu_dcerr_tid_g, | |
175 | lsu_dcl2c_err_g, | |
176 | lsu_dcl2u_err_g, | |
177 | lsu_dcl2nd_err_g, | |
178 | lsu_sbdlc_err_g, | |
179 | lsu_sbdlu_err_g, | |
180 | lsu_stberr_tid_g, | |
181 | lbist_run, | |
182 | mbi_run, | |
183 | lmc_mbi_run, | |
184 | lmc_bist_or_diag_e); | |
185 | wire se; | |
186 | wire pce_ov; | |
187 | wire stop; | |
188 | wire siclk; | |
189 | wire soclk; | |
190 | wire l1clk; | |
191 | wire rqpend_clken; | |
192 | wire l1clk_pm1; | |
193 | wire [7:0] cpq_mx_thread; | |
194 | wire [7:0] ceter_pscce_in; | |
195 | wire [7:0] thread_w; | |
196 | wire st_data_w_62; | |
197 | wire [7:0] ceter_pscce_reg; | |
198 | wire dff_ceter_scanin; | |
199 | wire dff_ceter_scanout; | |
200 | wire ceter_pscce_cpq; | |
201 | wire ceter_pscce_w3; | |
202 | wire [7:0] thread_w3; | |
203 | wire dff_cerer_scanin; | |
204 | wire dff_cerer_scanout; | |
205 | wire cerer_sbdlc; | |
206 | wire cerer_sbdlu; | |
207 | wire cerer_dcl2c; | |
208 | wire cerer_dcl2u; | |
209 | wire cerer_dcl2nd; | |
210 | wire cerer_socc; | |
211 | wire cerer_socu; | |
212 | wire [7:0] thread_b; | |
213 | wire [2:0] tid_b; | |
214 | wire dff_thread_w_scanin; | |
215 | wire dff_thread_w_scanout; | |
216 | wire dff_flush_b_scanin; | |
217 | wire dff_flush_b_scanout; | |
218 | wire local_flush_b; | |
219 | wire flush_b; | |
220 | wire excep_only_flush_b; | |
221 | wire dff_flush_w_scanin; | |
222 | wire dff_flush_w_scanout; | |
223 | wire flush_w; | |
224 | wire perror_w; | |
225 | wire dff_inst_b_scanin; | |
226 | wire dff_inst_b_scanout; | |
227 | wire ld_inst_vld_b; | |
228 | wire pref_inst_b; | |
229 | wire blk_inst_w; | |
230 | wire dff_inst_w_scanin; | |
231 | wire dff_inst_w_scanout; | |
232 | wire pref_inst_w; | |
233 | wire excep_only_flush_w; | |
234 | wire [7:0] load_lmq_entry; | |
235 | wire dff_l2fill_scanin; | |
236 | wire dff_l2fill_scanout; | |
237 | wire l2fill_vld_m; | |
238 | wire [7:0] ld_fill; | |
239 | wire [7:0] ld_unfilled_in; | |
240 | wire [7:0] ld_unfilled; | |
241 | wire dff_unfilled_scanin; | |
242 | wire dff_unfilled_scanout; | |
243 | wire [7:0] ld_unfilled_out; | |
244 | wire [7:0] ld_pcx_vld_set; | |
245 | wire ncache_w; | |
246 | wire ld_sec_hit_b; | |
247 | wire tlb_pgnum_b39_b; | |
248 | wire stb_cam_hit_b; | |
249 | wire stb_cam_mhit_b; | |
250 | wire stb_ld_part_raw_b; | |
251 | wire dff_stb_raw_scanin; | |
252 | wire dff_stb_raw_scanout; | |
253 | wire stb_cam_hit_w; | |
254 | wire stb_cam_mhit_w; | |
255 | wire stb_ld_part_raw_w; | |
256 | wire tlb_pgnum_b39_w; | |
257 | wire ldbl_w; | |
258 | wire ld_full_raw_w; | |
259 | wire ld_part_raw_w; | |
260 | wire ld_rawp_disabled_asi_b; | |
261 | wire [7:0] ld_rawp_disabled_in; | |
262 | wire [7:0] ld_rawp_disabled; | |
263 | wire dff_rawp_disable_scanin; | |
264 | wire dff_rawp_disable_scanout; | |
265 | wire ld_rawp_disabled_asi_w; | |
266 | wire [7:0] ld_rawp_disabled_out; | |
267 | wire [7:0] ld_rawp_disabled_set; | |
268 | wire [7:0] ldd_vld_in; | |
269 | wire dff_ldd_vld_scanin; | |
270 | wire dff_ldd_vld_scanout; | |
271 | wire lmq_vld_enable_b; | |
272 | wire lmq_vld_cancel_b; | |
273 | wire dff_ld_lmq_en_b_scanin; | |
274 | wire dff_ld_lmq_en_b_scanout; | |
275 | wire lmq_vld_enable_w_pre; | |
276 | wire lmq_vld_cancel_w_pre; | |
277 | wire lmq_vld_cancel_w; | |
278 | wire lmq_vld_enable_w; | |
279 | wire [7:0] ld_pcx_vld_rst; | |
280 | wire [7:0] ld_pcx_commit; | |
281 | wire [7:0] kill_pcx_ld_req; | |
282 | wire [7:0] bld_hold; | |
283 | wire [7:0] perr_inv; | |
284 | wire [7:0] ld_pcx_vld_in; | |
285 | wire [7:0] ld_pcx_vld; | |
286 | wire dff_ld_pcx_vld_scanin; | |
287 | wire dff_ld_pcx_vld_scanout; | |
288 | wire [7:0] ld_pcx_vld_out; | |
289 | wire ld_asi_vld_set_b; | |
290 | wire [7:0] ld_asi_vld_set; | |
291 | wire ld_asi_vld_set_w; | |
292 | wire [7:0] ld_asi_vld_in; | |
293 | wire [7:0] ld_asi_vld_rst; | |
294 | wire [7:0] ld_asi_vld; | |
295 | wire dff_ld_asi_vld_scanin; | |
296 | wire dff_ld_asi_vld_scanout; | |
297 | wire [7:0] ld_asi_vld_out; | |
298 | wire early_ld_cancel_w; | |
299 | wire [7:0] ld_pcx_rq_vld; | |
300 | wire early_ld_b_sel_p4; | |
301 | wire block_ldd_req; | |
302 | wire [7:0] ld_asi_rq_vld; | |
303 | wire asi_indet_block; | |
304 | wire [7:0] ld_rq_vld; | |
305 | wire [7:0] load_miss_w; | |
306 | wire ld_inst_unflushed_w; | |
307 | wire ld_inst_vld_w; | |
308 | wire lru8_scanin; | |
309 | wire lru8_scanout; | |
310 | wire [7:0] ld_rq_sel; | |
311 | wire [7:0] ld_pcx_rq_sel; | |
312 | wire [7:0] ld_asi_rq_sel; | |
313 | wire ld_pcx_sel_p3; | |
314 | wire ld_asi_sel_p3; | |
315 | wire [7:0] ld_early_rq_sel; | |
316 | wire [7:0] ld_all_rq_sel; | |
317 | wire [7:0] st_atom_p4_dec; | |
318 | wire dff_ld_sel_scanin; | |
319 | wire dff_ld_sel_scanout; | |
320 | wire [7:0] ld_all_sel_p4; | |
321 | wire ld_pcx_sel_p4; | |
322 | wire [3:0] ldd_count_p1; | |
323 | wire [3:0] ldd_count; | |
324 | wire [3:0] ldd_count_m1; | |
325 | wire inc_ldd_count_pre; | |
326 | wire dec_ldd_count; | |
327 | wire [3:0] ldd_count_in; | |
328 | wire inc_ldd_count; | |
329 | wire dff_ldd_out_scanin; | |
330 | wire dff_ldd_out_scanout; | |
331 | wire cpq_stall; | |
332 | wire casa_ld_to_pcx; | |
333 | wire [3:0] st_atom_p3; | |
334 | wire casa_bypass_d; | |
335 | wire dff_st_atom_p4_scanin; | |
336 | wire dff_st_atom_p4_scanout; | |
337 | wire [3:0] st_atom_p4; | |
338 | wire casa_bypass_e; | |
339 | wire [3:0] st_atom_p4_in; | |
340 | wire dff_st_atom_p5_scanin; | |
341 | wire dff_st_atom_p5_scanout; | |
342 | wire asi_indet_sel; | |
343 | wire asi_indet_retire; | |
344 | wire asi_indet_in; | |
345 | wire dff_asi_indet_scanin; | |
346 | wire dff_asi_indet_scanout; | |
347 | wire dff_cpq_tid_scanin; | |
348 | wire dff_cpq_tid_scanout; | |
349 | wire ld_inst_nopref_b; | |
350 | wire dff_ld_raw_w_scanin; | |
351 | wire dff_ld_raw_w_scanout; | |
352 | wire ld_inst_nopref_w; | |
353 | wire [2:0] tid_w; | |
354 | wire ld_raw_bypass_w; | |
355 | wire dff_ld_raw_w2_scanin; | |
356 | wire dff_ld_raw_w2_scanout; | |
357 | wire ld_raw_bypass_w2; | |
358 | wire [2:0] tid_w2; | |
359 | wire dff_ld_raw_w3_scanin; | |
360 | wire dff_ld_raw_w3_scanout; | |
361 | wire ld_raw_bypass_w3; | |
362 | wire [2:0] tid_w3; | |
363 | wire sbdlc_err; | |
364 | wire sbdlu_err; | |
365 | wire [7:0] lmq_bypass_vld; | |
366 | wire [7:0] ldbyp_vld_en; | |
367 | wire [7:0] ldbyp_rst; | |
368 | wire [7:0] ldbyp_vld; | |
369 | wire dff_ldbyp_vld_scanin; | |
370 | wire dff_ldbyp_vld_scanout; | |
371 | wire ld_bypass_ok_d; | |
372 | wire dff_ld_inst_e_scanin; | |
373 | wire dff_ld_inst_e_scanout; | |
374 | wire ld_bypass_ok_e; | |
375 | wire byp_cnt_rst; | |
376 | wire [2:0] byp_cnt_in; | |
377 | wire [2:0] byp_cnt; | |
378 | wire dff_byp_cnt_scanin; | |
379 | wire dff_byp_cnt_scanout; | |
380 | wire ld_bypass_e; | |
381 | wire byp_vld_e; | |
382 | wire [7:0] thrd_byp_sel_e; | |
383 | wire dff_thrd_byp_sel_m_scanin; | |
384 | wire dff_thrd_byp_sel_m_scanout; | |
385 | wire [7:0] thrd_byp_sel_m; | |
386 | wire [7:0] bld_inst_w; | |
387 | wire [7:0] bld_pending; | |
388 | wire [7:0] bld_pend_hold; | |
389 | wire [7:0] bld_pending_in; | |
390 | wire [7:0] bld_reset; | |
391 | wire dff_bld_pending_scanin; | |
392 | wire dff_bld_pending_scanout; | |
393 | wire [1:0] bld_addr54_p3; | |
394 | wire [1:0] bld_cnt0; | |
395 | wire [1:0] bld_cnt1; | |
396 | wire [1:0] bld_cnt2; | |
397 | wire [1:0] bld_cnt3; | |
398 | wire [1:0] bld_cnt4; | |
399 | wire [1:0] bld_cnt5; | |
400 | wire [1:0] bld_cnt6; | |
401 | wire [1:0] bld_cnt7; | |
402 | wire bld_req_p3; | |
403 | wire dff_bld_addr_scanin; | |
404 | wire dff_bld_addr_scanout; | |
405 | wire [1:0] bld_cnt0_in; | |
406 | wire inc_bld0_cnt; | |
407 | wire dff_bld_cnt0_scanin; | |
408 | wire dff_bld_cnt0_scanout; | |
409 | wire [1:0] bld_cnt1_in; | |
410 | wire inc_bld1_cnt; | |
411 | wire dff_bld_cnt1_scanin; | |
412 | wire dff_bld_cnt1_scanout; | |
413 | wire [1:0] bld_cnt2_in; | |
414 | wire inc_bld2_cnt; | |
415 | wire dff_bld_cnt2_scanin; | |
416 | wire dff_bld_cnt2_scanout; | |
417 | wire [1:0] bld_cnt3_in; | |
418 | wire inc_bld3_cnt; | |
419 | wire dff_bld_cnt3_scanin; | |
420 | wire dff_bld_cnt3_scanout; | |
421 | wire [1:0] bld_cnt4_in; | |
422 | wire inc_bld4_cnt; | |
423 | wire dff_bld_cnt4_scanin; | |
424 | wire dff_bld_cnt4_scanout; | |
425 | wire [1:0] bld_cnt5_in; | |
426 | wire inc_bld5_cnt; | |
427 | wire dff_bld_cnt5_scanin; | |
428 | wire dff_bld_cnt5_scanout; | |
429 | wire [1:0] bld_cnt6_in; | |
430 | wire inc_bld6_cnt; | |
431 | wire dff_bld_cnt6_scanin; | |
432 | wire dff_bld_cnt6_scanout; | |
433 | wire [1:0] bld_cnt7_in; | |
434 | wire inc_bld7_cnt; | |
435 | wire dff_bld_cnt7_scanin; | |
436 | wire dff_bld_cnt7_scanout; | |
437 | wire [7:0] bld_annul_rst; | |
438 | wire [7:0] bld_annul_in; | |
439 | wire [7:0] bld_annul; | |
440 | wire dff_bld_bypass_scanin; | |
441 | wire dff_bld_bypass_scanout; | |
442 | wire block_load_annul; | |
443 | wire [7:0] bld_miss_set; | |
444 | wire [7:0] bld_miss_in; | |
445 | wire [7:0] bld_miss; | |
446 | wire report_and_clear_error; | |
447 | wire [7:0] bld_miss_out; | |
448 | wire bld_pass7; | |
449 | wire dff_bld_miss_scanin; | |
450 | wire dff_bld_miss_scanout; | |
451 | wire bld_pass7_done; | |
452 | wire [7:0] pref_issued; | |
453 | wire dff_pref_issued_scanin; | |
454 | wire dff_pref_issued_scanout; | |
455 | wire [7:0] perr_set; | |
456 | wire [7:0] perr_inv_in; | |
457 | wire dff_perr_scanin; | |
458 | wire dff_perr_scanout; | |
459 | wire ld_inv_p3; | |
460 | wire [7:0] perr_inv_out; | |
461 | wire ld_inv_p4; | |
462 | wire lsu_dcvp_err_e2; | |
463 | wire lsu_dctp_err_e2; | |
464 | wire lsu_dcmh_err_e2; | |
465 | wire lsu_dcdp_err_e2; | |
466 | wire dff_dcerr_scanin; | |
467 | wire dff_dcerr_scanout; | |
468 | wire [1:0] l2_err; | |
469 | wire [1:0] l2_err0; | |
470 | wire [1:0] l2_err1; | |
471 | wire [1:0] l2_err2; | |
472 | wire [1:0] l2_err3; | |
473 | wire [1:0] l2_err4; | |
474 | wire [1:0] l2_err5; | |
475 | wire [1:0] l2_err6; | |
476 | wire [1:0] l2_err7; | |
477 | wire [1:0] l2_err_qual; | |
478 | wire [1:0] l2_err_new; | |
479 | wire [1:0] l2_err0_in; | |
480 | wire [1:0] l2_err1_in; | |
481 | wire [1:0] l2_err2_in; | |
482 | wire [1:0] l2_err3_in; | |
483 | wire [1:0] l2_err4_in; | |
484 | wire [1:0] l2_err5_in; | |
485 | wire [1:0] l2_err6_in; | |
486 | wire [1:0] l2_err7_in; | |
487 | wire dff_l2errcode_scanin; | |
488 | wire dff_l2errcode_scanout; | |
489 | wire dcl2c_err; | |
490 | wire dcl2u_err; | |
491 | wire dcl2nd_err; | |
492 | wire dff_l2err_scanin; | |
493 | wire dff_l2err_scanout; | |
494 | wire [2:0] stberr_tid; | |
495 | wire dff_stberr_scanin; | |
496 | wire dff_stberr_scanout; | |
497 | wire [7:0] xinval_pend_in; | |
498 | wire [7:0] xinval_pend; | |
499 | wire cpq_xinval_m; | |
500 | wire dff_xinval_pend_scanin; | |
501 | wire dff_xinval_pend_scanout; | |
502 | wire dff_bist_diag_scanin; | |
503 | wire dff_bist_diag_scanout; | |
504 | wire bist_or_diag_d; | |
505 | wire spares_scanin; | |
506 | wire spares_scanout; | |
507 | wire [4:0] unused; | |
508 | ||
509 | ||
510 | // Globals | |
511 | input l2clk; | |
512 | input scan_in; | |
513 | input tcu_pce_ov; // scan signals | |
514 | input tcu_scan_en; | |
515 | input spc_aclk; | |
516 | input spc_bclk; | |
517 | output scan_out; | |
518 | ||
519 | input [2:0] dcc_tid_m; | |
520 | input dcc_ld_inst_vld_m; | |
521 | input dcc_pref_inst_m; | |
522 | input dcc_ld_miss_b; // A load that needs to go to L2 | |
523 | input dcc_ld_miss_ldd; | |
524 | input dcc_asi_load_b; | |
525 | input dcc_asi_iomap_b; | |
526 | input dcc_blk_inst_b; // Block load instruction in B | |
527 | input dcc_ldbl_b; | |
528 | input dcc_ncache_b; // Non-cacheable ldst in B | |
529 | input dcc_ld_miss_ctl_b43; // Non-cacheable request to pcx | |
530 | input dcc_atomic_b; | |
531 | input dcc_casa_inst_b; | |
532 | input dcc_lsu_asi_rd_b; | |
533 | input dcc_lsu_asi_sel_w; | |
534 | input dcc_ceter_wr_w; | |
535 | input dcc_stb_diag_sel_w3; | |
536 | input dcc_exception_flush_b; | |
537 | input dcc_perror_b; | |
538 | input dcc_sync_pipe_w; | |
539 | input dcc_cache_diag_wr_b; | |
540 | ||
541 | input [7:0] dcc_asi_rtn_vld; | |
542 | input dcc_asi_rtn_excp; | |
543 | input dcc_asi_rtn_rd; | |
544 | ||
545 | input pic_casa_squash_req; // No loads can request this cycle | |
546 | input pic_early_ld_b_sel_p3; // The load in B is going to the pcx | |
547 | input pic_no_load_p3; // Load cannot issue in P3 | |
548 | input pic_asi_busy; // ASI ring cannot accept a request | |
549 | ||
550 | input lmd_pcx_pref; | |
551 | input [7:0] lmd_asi_ld; | |
552 | input [7:0] lmd_asi_indet; | |
553 | input [7:0] lmd_sec_cmp_b; // secondary hit compare results | |
554 | input lmd_addrb2; | |
555 | input lmd_sz_b1; | |
556 | input lmd_sz_b0; | |
557 | input lmd_ldbl; | |
558 | input [2:1] lmd_rd_e; | |
559 | input [1:0] lmd_dc_err_e; | |
560 | input lmd_fill_addr_b3_e; | |
561 | input lmd_fill_sz_b0_e; | |
562 | ||
563 | input tlb_pgnum_b39; | |
564 | input tlb_cam_mhit; | |
565 | ||
566 | input tlu_flush_lsu_b; // Flush the instruction in B | |
567 | input tlu_cerer_sbdlc; | |
568 | input tlu_cerer_sbdlu; | |
569 | input tlu_cerer_dcl2c; | |
570 | input tlu_cerer_dcl2u; | |
571 | input tlu_cerer_dcl2nd; | |
572 | input tlu_cerer_l2c_socc; | |
573 | input tlu_cerer_l2u_socu; | |
574 | ||
575 | input dec_flush_lm; // Flush the instruction in M | |
576 | input dec_flush_lb; // Flush the instruction in B | |
577 | input dec_ld_inst_d; | |
578 | ||
579 | input cic_l2fill_vld_e; | |
580 | input cic_cpq_ld_rdy; | |
581 | input cic_cpq_ld_rdy_; | |
582 | input cic_div_stall_d; | |
583 | input cic_oddrd_e; | |
584 | input cic_xinval_e; // xinval is being processed | |
585 | input [7:0] cic_xinval; // xinval arrived for a thread | |
586 | input cic_set_inval; | |
587 | input cic_rtn_cmplt; | |
588 | input cic_cpq_stall; | |
589 | input cic_ext_interrupt; | |
590 | ||
591 | input [2:0] cid_tid; | |
592 | input [1:0] cid_err; | |
593 | input cid_dcsoc_err_e; | |
594 | input cid_l2miss; | |
595 | ||
596 | input stb_cam_hit; | |
597 | input stb_cam_mhit; | |
598 | input stb_ld_part_raw; | |
599 | input stb_cecc_err; | |
600 | input stb_uecc_err; | |
601 | ||
602 | input sbd_st_data_b_62; | |
603 | ||
604 | input [7:0] sbs_all_commited; | |
605 | ||
606 | input [7:0] sbc_st_atom_p3; | |
607 | input [7:0] sbc_rawp_rst; | |
608 | input [2:0] sbc_st_sel_tid_p4; | |
609 | input sbc_force_inv; | |
610 | input sbc_kill_store_p4_; | |
611 | ||
612 | input lsu_lsu_pmen; | |
613 | ||
614 | output [7:0] lmc_lmq_enable_b; // Load enables for LMQ flops (threaded) | |
615 | output [7:0] lmc_pcx_sel_p4; // Which thread to send to pcx/asi | |
616 | output lmc_pcx_rq_vld; // At least one thread is ready to issue | |
617 | output lmc_asi_rq_vld; // At least one thread is ready to issue | |
618 | output lmc_ld_rq_p3; | |
619 | output lmc_ld_vld_p4; | |
620 | output lmc_ld_no_req_p4; // Cancel the pcx request of the load | |
621 | output lmc_ld_inv_p4; | |
622 | output [2:0] lmc_ld_tid; // Thread ID of load selected for issue | |
623 | output [7:0] lmc_byp_sel_e; // Thread select for fill/bypass data | |
624 | output [2:0] lmc_cpq_tid_m; // Thread ID of current cpq packet | |
625 | output [7:0] lmc_lmq_bypass_en; // Load enable for the LMQ bypass registers | |
626 | output lmc_asi_bypass_m; // ASI data is bypassing now | |
627 | output [1:0] lmc_bld_addr54; // Block load address modifier | |
628 | output lmc_bld_req; // Current pcx req is for block load | |
629 | output lmc_bld_req_; | |
630 | output lmc_bld_annul; | |
631 | output lmc_bld_miss_e; | |
632 | output lmc_bld_last_e; | |
633 | output [7:0] lmc_rd_update; | |
634 | output [7:0] lmc_pref_issued; // Prefetch issued to pcx | |
635 | output [7:0] lmc_ldd_vld; | |
636 | output [7:0] lmc_ld_unfilled; | |
637 | output lmc_lmd_ncache_b; | |
638 | output [4:0] lmc_ld_sz; | |
639 | output lmc_ld_inst_w; | |
640 | output lmc_full_raw_w; | |
641 | output lmc_ld_stall; // stall pipe so bypass can complete | |
642 | output lmc_l2_err_noup; | |
643 | output lmc_l2_uerr; | |
644 | output lmc_byp_data_hi; | |
645 | output lmc_byp_data_enable; | |
646 | ||
647 | output [7:0] lmc_thrd_byp_sel_e; // Thread is bypassing (or filling) | |
648 | output [7:0] lmc_thrd_byp_sel_m; // Which thread's bypass register is bypassing | |
649 | output [2:0] lmc_byp_tid_m; // Which thread's bypass register is bypassing | |
650 | output lmc_byp_vld_m; // A bypass is occuring | |
651 | output [4:0] lmc_lmq0_byp_sel; // source selects for load bypass registers | |
652 | output [4:0] lmc_lmq1_byp_sel; // source selects for load bypass registers | |
653 | output [4:0] lmc_lmq2_byp_sel; // source selects for load bypass registers | |
654 | output [4:0] lmc_lmq3_byp_sel; // source selects for load bypass registers | |
655 | output [4:0] lmc_lmq4_byp_sel; // source selects for load bypass registers | |
656 | output [4:0] lmc_lmq5_byp_sel; // source selects for load bypass registers | |
657 | output [4:0] lmc_lmq6_byp_sel; // source selects for load bypass registers | |
658 | output [4:0] lmc_lmq7_byp_sel; // source selects for load bypass registers | |
659 | output lmc_asi_indet_retire; // indeterminate ASI load back from ring | |
660 | ||
661 | output [7:0] lsu_ifu_no_miss; // xinval pending so do not allow I$ miss | |
662 | ||
663 | output lsu_dcmh_err_g; | |
664 | output lsu_dcvp_err_g; | |
665 | output lsu_dctp_err_g; | |
666 | output lsu_dcdp_err_g; | |
667 | output [2:0] lsu_dcerr_tid_g; | |
668 | ||
669 | output lsu_dcl2c_err_g; | |
670 | output lsu_dcl2u_err_g; | |
671 | output lsu_dcl2nd_err_g; | |
672 | ||
673 | output lsu_sbdlc_err_g; | |
674 | output lsu_sbdlu_err_g; | |
675 | output [2:0] lsu_stberr_tid_g; | |
676 | ||
677 | input lbist_run; | |
678 | input mbi_run; | |
679 | output lmc_mbi_run; | |
680 | output lmc_bist_or_diag_e; | |
681 | ||
682 | // scan renames | |
683 | assign se = tcu_scan_en; | |
684 | assign pce_ov = tcu_pce_ov; | |
685 | assign stop = 1'b0; | |
686 | assign siclk = spc_aclk; | |
687 | assign soclk = spc_bclk; | |
688 | // end scan | |
689 | ||
690 | ////////////////////////////// | |
691 | // Clock header | |
692 | ////////////////////////////// | |
693 | lsu_lmc_ctll1clkhdr_ctl_macro clkgen ( | |
694 | .l2clk (l2clk ), | |
695 | .l1en (1'b1 ), | |
696 | .l1clk (l1clk ), | |
697 | .pce_ov(pce_ov), | |
698 | .stop(stop), | |
699 | .se(se) | |
700 | ); | |
701 | ||
702 | lsu_lmc_ctll1clkhdr_ctl_macro rqpend_clkgen ( | |
703 | .l2clk (l2clk ), | |
704 | .l1en (rqpend_clken ), | |
705 | .l1clk (l1clk_pm1 ), | |
706 | .pce_ov(pce_ov), | |
707 | .stop(stop), | |
708 | .se(se) | |
709 | ); | |
710 | ||
711 | assign cpq_mx_thread[0] = (cid_tid[2:0] == 3'd0); | |
712 | assign cpq_mx_thread[1] = (cid_tid[2:0] == 3'd1); | |
713 | assign cpq_mx_thread[2] = (cid_tid[2:0] == 3'd2); | |
714 | assign cpq_mx_thread[3] = (cid_tid[2:0] == 3'd3); | |
715 | assign cpq_mx_thread[4] = (cid_tid[2:0] == 3'd4); | |
716 | assign cpq_mx_thread[5] = (cid_tid[2:0] == 3'd5); | |
717 | assign cpq_mx_thread[6] = (cid_tid[2:0] == 3'd6); | |
718 | assign cpq_mx_thread[7] = (cid_tid[2:0] == 3'd7); | |
719 | ||
720 | assign ceter_pscce_in[0] = (dcc_ceter_wr_w & thread_w[0]) ? st_data_w_62 : ceter_pscce_reg[0]; | |
721 | assign ceter_pscce_in[1] = (dcc_ceter_wr_w & thread_w[1]) ? st_data_w_62 : ceter_pscce_reg[1]; | |
722 | assign ceter_pscce_in[2] = (dcc_ceter_wr_w & thread_w[2]) ? st_data_w_62 : ceter_pscce_reg[2]; | |
723 | assign ceter_pscce_in[3] = (dcc_ceter_wr_w & thread_w[3]) ? st_data_w_62 : ceter_pscce_reg[3]; | |
724 | assign ceter_pscce_in[4] = (dcc_ceter_wr_w & thread_w[4]) ? st_data_w_62 : ceter_pscce_reg[4]; | |
725 | assign ceter_pscce_in[5] = (dcc_ceter_wr_w & thread_w[5]) ? st_data_w_62 : ceter_pscce_reg[5]; | |
726 | assign ceter_pscce_in[6] = (dcc_ceter_wr_w & thread_w[6]) ? st_data_w_62 : ceter_pscce_reg[6]; | |
727 | assign ceter_pscce_in[7] = (dcc_ceter_wr_w & thread_w[7]) ? st_data_w_62 : ceter_pscce_reg[7]; | |
728 | ||
729 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_ceter ( | |
730 | .scan_in(dff_ceter_scanin), | |
731 | .scan_out(dff_ceter_scanout), | |
732 | .din ({sbd_st_data_b_62,ceter_pscce_in[7:0]}), | |
733 | .dout ({st_data_w_62, ceter_pscce_reg[7:0]}), | |
734 | .l1clk(l1clk), | |
735 | .siclk(siclk), | |
736 | .soclk(soclk) | |
737 | ); | |
738 | ||
739 | assign ceter_pscce_cpq = (cpq_mx_thread[0] & ceter_pscce_reg[0]) | | |
740 | (cpq_mx_thread[1] & ceter_pscce_reg[1]) | | |
741 | (cpq_mx_thread[2] & ceter_pscce_reg[2]) | | |
742 | (cpq_mx_thread[3] & ceter_pscce_reg[3]) | | |
743 | (cpq_mx_thread[4] & ceter_pscce_reg[4]) | | |
744 | (cpq_mx_thread[5] & ceter_pscce_reg[5]) | | |
745 | (cpq_mx_thread[6] & ceter_pscce_reg[6]) | | |
746 | (cpq_mx_thread[7] & ceter_pscce_reg[7]) ; | |
747 | ||
748 | assign ceter_pscce_w3 = (thread_w3[0] & ceter_pscce_reg[0]) | | |
749 | (thread_w3[1] & ceter_pscce_reg[1]) | | |
750 | (thread_w3[2] & ceter_pscce_reg[2]) | | |
751 | (thread_w3[3] & ceter_pscce_reg[3]) | | |
752 | (thread_w3[4] & ceter_pscce_reg[4]) | | |
753 | (thread_w3[5] & ceter_pscce_reg[5]) | | |
754 | (thread_w3[6] & ceter_pscce_reg[6]) | | |
755 | (thread_w3[7] & ceter_pscce_reg[7]) ; | |
756 | ||
757 | lsu_lmc_ctlmsff_ctl_macro__width_7 dff_cerer ( | |
758 | .scan_in(dff_cerer_scanin), | |
759 | .scan_out(dff_cerer_scanout), | |
760 | .din ({tlu_cerer_sbdlc,tlu_cerer_sbdlu,tlu_cerer_dcl2c,tlu_cerer_dcl2u,tlu_cerer_dcl2nd, | |
761 | tlu_cerer_l2c_socc, tlu_cerer_l2u_socu}), | |
762 | .dout ({ cerer_sbdlc, cerer_sbdlu, cerer_dcl2c, cerer_dcl2u, cerer_dcl2nd, | |
763 | cerer_socc, cerer_socu}), | |
764 | .l1clk(l1clk), | |
765 | .siclk(siclk), | |
766 | .soclk(soclk) | |
767 | ); | |
768 | ||
769 | ////////////////////////////// | |
770 | // Thread decoding | |
771 | ////////////////////////////// | |
772 | ||
773 | assign thread_b[0] = ~tid_b[2] & ~tid_b[1] & ~tid_b[0]; | |
774 | assign thread_b[1] = ~tid_b[2] & ~tid_b[1] & tid_b[0]; | |
775 | assign thread_b[2] = ~tid_b[2] & tid_b[1] & ~tid_b[0]; | |
776 | assign thread_b[3] = ~tid_b[2] & tid_b[1] & tid_b[0]; | |
777 | assign thread_b[4] = tid_b[2] & ~tid_b[1] & ~tid_b[0]; | |
778 | assign thread_b[5] = tid_b[2] & ~tid_b[1] & tid_b[0]; | |
779 | assign thread_b[6] = tid_b[2] & tid_b[1] & ~tid_b[0]; | |
780 | assign thread_b[7] = tid_b[2] & tid_b[1] & tid_b[0]; | |
781 | ||
782 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_thread_w ( | |
783 | .scan_in(dff_thread_w_scanin), | |
784 | .scan_out(dff_thread_w_scanout), | |
785 | .l1clk (l1clk_pm1), | |
786 | .din (thread_b[7:0]), | |
787 | .dout (thread_w[7:0]), | |
788 | .siclk(siclk), | |
789 | .soclk(soclk) | |
790 | ); | |
791 | ||
792 | ////////////////////////////// | |
793 | // Instruction flushing | |
794 | ////////////////////////////// | |
795 | ||
796 | lsu_lmc_ctlmsff_ctl_macro__width_1 dff_flush_b ( | |
797 | .scan_in(dff_flush_b_scanin), | |
798 | .scan_out(dff_flush_b_scanout), | |
799 | .din (dec_flush_lm), | |
800 | .dout (local_flush_b), | |
801 | .l1clk(l1clk), | |
802 | .siclk(siclk), | |
803 | .soclk(soclk) | |
804 | ); | |
805 | ||
806 | assign flush_b = tlu_flush_lsu_b | dec_flush_lb | local_flush_b | dcc_exception_flush_b; | |
807 | assign excep_only_flush_b = dcc_exception_flush_b & ~(tlu_flush_lsu_b | dec_flush_lb | local_flush_b); | |
808 | ||
809 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_flush_w ( | |
810 | .scan_in(dff_flush_w_scanin), | |
811 | .scan_out(dff_flush_w_scanout), | |
812 | .din ({flush_b,dcc_perror_b}), | |
813 | .dout ({flush_w,perror_w}), | |
814 | .l1clk(l1clk), | |
815 | .siclk(siclk), | |
816 | .soclk(soclk) | |
817 | ); | |
818 | ||
819 | //////////////////////////////////////////////////////////////////////////////// | |
820 | // Enables to load miss information into the LMQ buffers | |
821 | // LMQ buffers are written in the W stage, so the enable must be valid in B. | |
822 | // ld_miss_b will be the critical signal. If it's too late, the LMQ can be loaded | |
823 | // on every miss and a separate signal used to track whether the load needs to go | |
824 | // to L2, but this will mess up the LRU mechanism below, so I'd like to avoid it | |
825 | // if possible. | |
826 | //////////////////////////////////////////////////////////////////////////////// | |
827 | ||
828 | lsu_lmc_ctlmsff_ctl_macro__width_6 dff_inst_b ( | |
829 | .scan_in(dff_inst_b_scanin), | |
830 | .scan_out(dff_inst_b_scanout), | |
831 | .din ({dcc_ld_inst_vld_m, dcc_pref_inst_m, dcc_blk_inst_b,dcc_tid_m[2:0]}), | |
832 | .dout ({ ld_inst_vld_b, pref_inst_b, blk_inst_w, tid_b[2:0]}), | |
833 | .l1clk(l1clk), | |
834 | .siclk(siclk), | |
835 | .soclk(soclk) | |
836 | ); | |
837 | ||
838 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_inst_w ( | |
839 | .scan_in(dff_inst_w_scanin), | |
840 | .scan_out(dff_inst_w_scanout), | |
841 | .l1clk (l1clk_pm1), | |
842 | .din ({pref_inst_b, excep_only_flush_b}), | |
843 | .dout ({pref_inst_w, excep_only_flush_w}), | |
844 | .siclk(siclk), | |
845 | .soclk(soclk) | |
846 | ); | |
847 | ||
848 | assign load_lmq_entry[7:0] = (({8{ld_inst_vld_b}} & thread_b[7:0]) & | |
849 | ~(({8{dcc_sync_pipe_w}} & thread_w[7:0]) | {8{local_flush_b}})); | |
850 | assign lmc_lmq_enable_b[7:0] = load_lmq_entry[7:0] | lmc_rd_update[7:0]; | |
851 | ||
852 | //////////////////////////////////////////////////////////////////////////////// | |
853 | // Fill state of each entry. An unfilled flag is set when the miss occurs | |
854 | // and cleared when the cache is filled (or when the data is bypassed in the | |
855 | // case of non-cacheable loads). | |
856 | //////////////////////////////////////////////////////////////////////////////// | |
857 | ||
858 | lsu_lmc_ctlmsff_ctl_macro__width_1 dff_l2fill ( | |
859 | .scan_in(dff_l2fill_scanin), | |
860 | .scan_out(dff_l2fill_scanout), | |
861 | .din (cic_l2fill_vld_e), | |
862 | .dout (l2fill_vld_m), | |
863 | .l1clk(l1clk), | |
864 | .siclk(siclk), | |
865 | .soclk(soclk) | |
866 | ); | |
867 | ||
868 | assign ld_fill[0] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b000); | |
869 | assign ld_fill[1] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b001); | |
870 | assign ld_fill[2] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b010); | |
871 | assign ld_fill[3] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b011); | |
872 | assign ld_fill[4] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b100); | |
873 | assign ld_fill[5] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b101); | |
874 | assign ld_fill[6] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b110); | |
875 | assign ld_fill[7] = l2fill_vld_m & (lmc_cpq_tid_m[2:0] == 3'b111); | |
876 | ||
877 | assign ld_unfilled_in[7:0] = ld_unfilled[7:0] & ~ld_fill[7:0]; | |
878 | ||
879 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_unfilled ( | |
880 | .scan_in(dff_unfilled_scanin), | |
881 | .scan_out(dff_unfilled_scanout), | |
882 | .din (ld_unfilled_in[7:0]), | |
883 | .dout (ld_unfilled_out[7:0]), | |
884 | .l1clk(l1clk), | |
885 | .siclk(siclk), | |
886 | .soclk(soclk) | |
887 | ); | |
888 | assign ld_unfilled[7:0] = (ld_pcx_vld_set[7:0] & {8{~ncache_w}}) | ld_unfilled_out[7:0]; | |
889 | ||
890 | //////////////////////////////////////////////////////////////////////////////// | |
891 | // Secondary miss processing | |
892 | // A load miss is considered secondary if it matches a load from another thread | |
893 | // that has a miss pending. In this case, the secondary load will be marked | |
894 | // as non-cacheable to avoid cache pollution. | |
895 | //////////////////////////////////////////////////////////////////////////////// | |
896 | ||
897 | assign lmc_ld_unfilled[7:0] = ld_unfilled[7:0]; | |
898 | ||
899 | assign ld_sec_hit_b = (|(lmd_sec_cmp_b[7:0]) & ~dcc_asi_load_b); | |
900 | ||
901 | assign lmc_lmd_ncache_b = dcc_ld_miss_ctl_b43 | ld_sec_hit_b; | |
902 | ||
903 | //////////////////////////////////////////////////////////////////////////////// | |
904 | // Partial RAW handling | |
905 | // Partial RAWs and loads treated like partial raws (full raw to multiple stb | |
906 | // entries) cannot issue to the pcx until dependent stores have been committed | |
907 | // to the pcx. The depedency tracking is done in lsu_sbc_ctl. | |
908 | //////////////////////////////////////////////////////////////////////////////// | |
909 | ||
910 | assign tlb_pgnum_b39_b = ld_inst_vld_b & tlb_pgnum_b39 & ~tlb_cam_mhit; | |
911 | ||
912 | assign stb_cam_hit_b = stb_cam_hit & ~(lbist_run | lmc_mbi_run); | |
913 | assign stb_cam_mhit_b = stb_cam_mhit & ~(lbist_run | lmc_mbi_run); | |
914 | assign stb_ld_part_raw_b = stb_ld_part_raw & ~(lbist_run | lmc_mbi_run); | |
915 | ||
916 | lsu_lmc_ctlmsff_ctl_macro__width_5 dff_stb_raw ( | |
917 | .scan_in(dff_stb_raw_scanin), | |
918 | .scan_out(dff_stb_raw_scanout), | |
919 | .l1clk (l1clk_pm1), | |
920 | .din ({stb_cam_hit_b,stb_cam_mhit_b,stb_ld_part_raw_b,tlb_pgnum_b39_b,dcc_ldbl_b}), | |
921 | .dout ({stb_cam_hit_w,stb_cam_mhit_w,stb_ld_part_raw_w,tlb_pgnum_b39_w,ldbl_w}), | |
922 | .siclk(siclk), | |
923 | .soclk(soclk) | |
924 | ); | |
925 | ||
926 | assign ld_full_raw_w = stb_cam_hit_w & ~ld_part_raw_w; | |
927 | assign ld_part_raw_w = stb_ld_part_raw_w | // a partial hit | |
928 | stb_cam_mhit_w | // multiple hits | |
929 | tlb_pgnum_b39_w | // IO load | |
930 | (ldbl_w & stb_cam_hit_w) ; // BLD/QUAD/LDD | |
931 | ||
932 | assign ld_rawp_disabled_asi_b = (dcc_asi_load_b & ~dcc_lsu_asi_rd_b) & ld_inst_vld_b; | |
933 | ||
934 | assign ld_rawp_disabled_in[7:0] = (ld_rawp_disabled[7:0] & ~sbc_rawp_rst[7:0]) & ~sbs_all_commited[7:0]; | |
935 | ||
936 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_rawp_disable ( | |
937 | .scan_in(dff_rawp_disable_scanin), | |
938 | .scan_out(dff_rawp_disable_scanout), | |
939 | .l1clk (l1clk_pm1), | |
940 | .din ({ld_rawp_disabled_asi_b,ld_rawp_disabled_in[7:0]}), | |
941 | .dout ({ld_rawp_disabled_asi_w,ld_rawp_disabled_out[7:0]}), | |
942 | .siclk(siclk), | |
943 | .soclk(soclk) | |
944 | ); | |
945 | ||
946 | // Don't change or remove this signal name. It's used by the bench. | |
947 | assign ld_rawp_disabled_set[7:0] = {8{ (ld_rawp_disabled_asi_w | ld_part_raw_w) & ~flush_w }} & thread_w[7:0]; | |
948 | ||
949 | assign ld_rawp_disabled[7:0] = ld_rawp_disabled_set[7:0] | ld_rawp_disabled_out[7:0]; | |
950 | ||
951 | //////////////////////////////////////////////////////////////////////////////// | |
952 | // Track ldd flags here. They used to be part of lmq entry in lsu_lmd_dp, but | |
953 | // they need to be here for timing. | |
954 | //////////////////////////////////////////////////////////////////////////////// | |
955 | ||
956 | assign ldd_vld_in[7:0] = ( load_lmq_entry[7:0] & {8{dcc_ld_miss_ldd}}) | | |
957 | (~load_lmq_entry[7:0] & lmc_ldd_vld[7:0]); | |
958 | ||
959 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ldd_vld ( | |
960 | .scan_in(dff_ldd_vld_scanin), | |
961 | .scan_out(dff_ldd_vld_scanout), | |
962 | .l1clk (l1clk_pm1), | |
963 | .din (ldd_vld_in[7:0]), | |
964 | .dout (lmc_ldd_vld[7:0]), | |
965 | .siclk(siclk), | |
966 | .soclk(soclk) | |
967 | ); | |
968 | ||
969 | //////////////////////////////////////////////////////////////////////////////// | |
970 | // PCX and ASI Load Control | |
971 | // An LMQ entry is ready to issue to the pcx when it is loaded. | |
972 | // The request is cleared once the entry successfully issues to the pcx. | |
973 | // | |
974 | // B | W/P3 | P4 | |
975 | // | | | |
976 | // miss detected| LMQ loaded | packet to gasket | |
977 | // | request set | | |
978 | // | arb for pcx | | |
979 | // | |
980 | // Arbitration among threads with pending load requests happens here. Arbitration | |
981 | // between the pcx sources (loads and stores) happens in the pic control block. | |
982 | //////////////////////////////////////////////////////////////////////////////// | |
983 | ||
984 | // Load misses issue to the pcx with the following exceptions | |
985 | // - internal ASI's which aren't IO mapped (they go to the ASI ring instead) | |
986 | // - atomics (the STB arbitrates for these) | |
987 | // - prefetches always issue, regardless | |
988 | // - full raw | |
989 | ||
990 | assign lmq_vld_enable_b = dcc_ld_miss_b & ld_inst_vld_b; | |
991 | assign lmq_vld_cancel_b = (dcc_asi_load_b & ~dcc_asi_iomap_b) | dcc_atomic_b; | |
992 | ||
993 | lsu_lmc_ctlmsff_ctl_macro__width_3 dff_ld_lmq_en_b ( | |
994 | .scan_in(dff_ld_lmq_en_b_scanin), | |
995 | .scan_out(dff_ld_lmq_en_b_scanout), | |
996 | .l1clk (l1clk_pm1), | |
997 | .din ({lmq_vld_enable_b, lmq_vld_cancel_b, lmc_lmd_ncache_b}), | |
998 | .dout ({lmq_vld_enable_w_pre,lmq_vld_cancel_w_pre,ncache_w}), | |
999 | .siclk(siclk), | |
1000 | .soclk(soclk) | |
1001 | ); | |
1002 | assign lmq_vld_cancel_w = lmq_vld_cancel_w_pre | ld_full_raw_w; | |
1003 | assign lmq_vld_enable_w = (lmq_vld_enable_w_pre | ld_part_raw_w) & ~lmq_vld_cancel_w; | |
1004 | ||
1005 | // PCX requests pending | |
1006 | assign ld_pcx_vld_set[0] = lmq_vld_enable_w & ~flush_w & thread_w[0]; | |
1007 | assign ld_pcx_vld_set[1] = lmq_vld_enable_w & ~flush_w & thread_w[1]; | |
1008 | assign ld_pcx_vld_set[2] = lmq_vld_enable_w & ~flush_w & thread_w[2]; | |
1009 | assign ld_pcx_vld_set[3] = lmq_vld_enable_w & ~flush_w & thread_w[3]; | |
1010 | assign ld_pcx_vld_set[4] = lmq_vld_enable_w & ~flush_w & thread_w[4]; | |
1011 | assign ld_pcx_vld_set[5] = lmq_vld_enable_w & ~flush_w & thread_w[5]; | |
1012 | assign ld_pcx_vld_set[6] = lmq_vld_enable_w & ~flush_w & thread_w[6]; | |
1013 | assign ld_pcx_vld_set[7] = lmq_vld_enable_w & ~flush_w & thread_w[7]; | |
1014 | ||
1015 | assign ld_pcx_vld_rst[7:0] = (ld_pcx_commit[7:0] | kill_pcx_ld_req[7:0]) & ~(bld_hold[7:0] | perr_inv[7:0]); | |
1016 | ||
1017 | assign ld_pcx_vld_in[7:0] = ~ld_pcx_vld_rst[7:0] & ld_pcx_vld[7:0]; | |
1018 | ||
1019 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ld_pcx_vld ( | |
1020 | .scan_in(dff_ld_pcx_vld_scanin), | |
1021 | .scan_out(dff_ld_pcx_vld_scanout), | |
1022 | .l1clk (l1clk_pm1), | |
1023 | .din (ld_pcx_vld_in[7:0]), | |
1024 | .dout (ld_pcx_vld_out[7:0]), | |
1025 | .siclk(siclk), | |
1026 | .soclk(soclk) | |
1027 | ); | |
1028 | assign ld_pcx_vld[7:0] = ld_pcx_vld_set[7:0] | ld_pcx_vld_out[7:0]; | |
1029 | ||
1030 | // ASI requests pending | |
1031 | assign ld_asi_vld_set_b = dcc_asi_load_b & ~dcc_asi_iomap_b & ~dcc_lsu_asi_rd_b; | |
1032 | ||
1033 | assign ld_asi_vld_set[0] = ld_asi_vld_set_w & ~flush_w & thread_w[0]; | |
1034 | assign ld_asi_vld_set[1] = ld_asi_vld_set_w & ~flush_w & thread_w[1]; | |
1035 | assign ld_asi_vld_set[2] = ld_asi_vld_set_w & ~flush_w & thread_w[2]; | |
1036 | assign ld_asi_vld_set[3] = ld_asi_vld_set_w & ~flush_w & thread_w[3]; | |
1037 | assign ld_asi_vld_set[4] = ld_asi_vld_set_w & ~flush_w & thread_w[4]; | |
1038 | assign ld_asi_vld_set[5] = ld_asi_vld_set_w & ~flush_w & thread_w[5]; | |
1039 | assign ld_asi_vld_set[6] = ld_asi_vld_set_w & ~flush_w & thread_w[6]; | |
1040 | assign ld_asi_vld_set[7] = ld_asi_vld_set_w & ~flush_w & thread_w[7]; | |
1041 | ||
1042 | assign ld_asi_vld_in[7:0] = ~ld_asi_vld_rst[7:0] & ld_asi_vld[7:0]; | |
1043 | ||
1044 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_ld_asi_vld ( | |
1045 | .scan_in(dff_ld_asi_vld_scanin), | |
1046 | .scan_out(dff_ld_asi_vld_scanout), | |
1047 | .l1clk (l1clk_pm1), | |
1048 | .din ({ld_asi_vld_set_b,ld_asi_vld_in[7:0]}), | |
1049 | .dout ({ld_asi_vld_set_w,ld_asi_vld_out[7:0]}), | |
1050 | .siclk(siclk), | |
1051 | .soclk(soclk) | |
1052 | ); | |
1053 | ||
1054 | assign ld_asi_vld[7:0] = ld_asi_vld_set[7:0] | ld_asi_vld_out[7:0]; | |
1055 | ||
1056 | // Is the load which made an early request still valid? | |
1057 | assign early_ld_cancel_w = ld_full_raw_w | ld_part_raw_w | flush_w | perror_w; | |
1058 | ||
1059 | // A thread should never have pcx and asi requests valid simultaneously | |
1060 | // 0in bits_on -var {ld_pcx_vld[0],ld_asi_vld[0]} -max 1 -message "PCX and ASI load requests for thread 0" | |
1061 | // 0in bits_on -var {ld_pcx_vld[1],ld_asi_vld[1]} -max 1 -message "PCX and ASI load requests for thread 1" | |
1062 | // 0in bits_on -var {ld_pcx_vld[2],ld_asi_vld[2]} -max 1 -message "PCX and ASI load requests for thread 2" | |
1063 | // 0in bits_on -var {ld_pcx_vld[3],ld_asi_vld[3]} -max 1 -message "PCX and ASI load requests for thread 3" | |
1064 | // 0in bits_on -var {ld_pcx_vld[4],ld_asi_vld[4]} -max 1 -message "PCX and ASI load requests for thread 4" | |
1065 | // 0in bits_on -var {ld_pcx_vld[5],ld_asi_vld[5]} -max 1 -message "PCX and ASI load requests for thread 5" | |
1066 | // 0in bits_on -var {ld_pcx_vld[6],ld_asi_vld[6]} -max 1 -message "PCX and ASI load requests for thread 6" | |
1067 | // 0in bits_on -var {ld_pcx_vld[7],ld_asi_vld[7]} -max 1 -message "PCX and ASI load requests for thread 7" | |
1068 | ||
1069 | ////////////////////// | |
1070 | // P3 stage | |
1071 | ////////////////////// | |
1072 | ||
1073 | // Generate valid pcx and asi requests. | |
1074 | // PCX requests can be cancelled by rawp conditions | |
1075 | // ASI requests can be cancelled by rawp conditions and by another outstanding indeterminate. | |
1076 | ||
1077 | assign ld_pcx_rq_vld[7:0] = ld_pcx_vld[7:0] & ~ld_rawp_disabled[7:0] & ~({8{early_ld_b_sel_p4}} & thread_w[7:0]) & ~({8{block_ldd_req}} & lmc_ldd_vld[7:0]); | |
1078 | assign ld_asi_rq_vld[7:0] = ld_asi_vld[7:0] & ~ld_rawp_disabled[7:0] & ~(lmd_asi_ld[7:0] & lmd_asi_indet[7:0] & {8{asi_indet_block}}); | |
1079 | ||
1080 | assign ld_rq_vld[7:0] = ld_pcx_rq_vld[7:0] | ld_asi_rq_vld[7:0]; | |
1081 | assign lmc_ld_rq_p3 = |(ld_rq_vld[7:0]); | |
1082 | ||
1083 | // Pseudo-LRU picker to choose the oldest thread for issuing to pcx. | |
1084 | // LRU state is updated after a load is put into the miss queue | |
1085 | assign load_miss_w[7:0] = {8{(ld_inst_unflushed_w | (ld_inst_vld_w & ~flush_w))}} & thread_w[7:0] & (ld_pcx_vld[7:0] | ld_asi_vld[7:0]); | |
1086 | ||
1087 | lsu_lru8_ctl lru8 ( | |
1088 | .scan_in(lru8_scanin), | |
1089 | .scan_out(lru8_scanout), | |
1090 | .request (ld_rq_vld[7:0]), | |
1091 | .enable (load_miss_w[7:0]), | |
1092 | .select (ld_rq_sel[7:0]), | |
1093 | .l1clk(l1clk), | |
1094 | .spc_aclk(spc_aclk), | |
1095 | .spc_bclk(spc_bclk) | |
1096 | ); | |
1097 | ||
1098 | // Tell pic if request was pcx or asi | |
1099 | assign lmc_pcx_rq_vld = |(ld_rq_sel[7:0] & ld_pcx_rq_vld[7:0]); | |
1100 | assign lmc_asi_rq_vld = |(ld_rq_sel[7:0] & ld_asi_rq_vld[7:0]); | |
1101 | ||
1102 | // A request wins arbitration to the pcx if it's thread is selected AND | |
1103 | // the load port wins source arbitration. | |
1104 | // Loads will win over stores unless blocked by pic_no_load_p3 | |
1105 | assign ld_pcx_rq_sel[7:0] = ld_rq_sel[7:0] & ld_pcx_rq_vld[7:0] & {8{~pic_no_load_p3}}; | |
1106 | assign ld_asi_rq_sel[7:0] = ld_rq_sel[7:0] & ld_asi_rq_vld[7:0] & {8{~(pic_no_load_p3 | pic_asi_busy)}}; | |
1107 | assign ld_pcx_sel_p3 = |(ld_pcx_rq_sel[7:0]); | |
1108 | assign ld_asi_sel_p3 = |(ld_asi_rq_sel[7:0]); | |
1109 | ||
1110 | assign ld_early_rq_sel[7:0] = {8{~(ld_pcx_sel_p3 | ld_asi_sel_p3 | pic_casa_squash_req)}} & thread_b[7:0]; | |
1111 | assign ld_all_rq_sel[7:0] = ld_pcx_rq_sel[7:0] | ld_asi_rq_sel[7:0] | ld_early_rq_sel[7:0] | st_atom_p4_dec[7:0]; | |
1112 | ||
1113 | assign ld_pcx_commit[7:0] = ld_pcx_rq_sel[7:0]; | |
1114 | assign ld_asi_vld_rst[7:0] = ld_asi_rq_sel[7:0]; | |
1115 | ||
1116 | lsu_lmc_ctlmsff_ctl_macro__width_10 dff_ld_sel ( | |
1117 | .scan_in(dff_ld_sel_scanin), | |
1118 | .scan_out(dff_ld_sel_scanout), | |
1119 | .l1clk (l1clk_pm1), | |
1120 | .din ({ld_all_rq_sel[7:0],ld_pcx_sel_p3,pic_early_ld_b_sel_p3}), | |
1121 | .dout ({ld_all_sel_p4[7:0],ld_pcx_sel_p4, early_ld_b_sel_p4}), | |
1122 | .siclk(siclk), | |
1123 | .soclk(soclk) | |
1124 | ); | |
1125 | ||
1126 | // Need to throttle the number of outstanding LDD requests to avoid CPQ overflow. | |
1127 | // No more LDD requests can be sent if | |
1128 | // (i) Number of outstanding requests is 14 OR | |
1129 | // (ii)cic is issuing a stall due to CPQ above high water mark | |
1130 | // Counter is incremented one cycle late to ease timing. | |
1131 | ||
1132 | assign ldd_count_p1[3:0] = ldd_count[3:0] + 4'b0001; | |
1133 | assign ldd_count_m1[3:0] = ldd_count[3:0] - 4'b0001; | |
1134 | ||
1135 | assign inc_ldd_count_pre = |(ld_pcx_rq_sel[7:0] & lmc_ldd_vld[7:0] & ~perr_inv[7:0]); | |
1136 | assign dec_ldd_count = cic_oddrd_e; | |
1137 | assign ldd_count_in[3:0] = ({4{inc_ldd_count & ~dec_ldd_count}} & ldd_count_p1[3:0]) | | |
1138 | ({4{dec_ldd_count & ~inc_ldd_count}} & ldd_count_m1[3:0]) | | |
1139 | ({4{inc_ldd_count ~^ dec_ldd_count}} & ldd_count[3:0]) ; | |
1140 | ||
1141 | lsu_lmc_ctlmsff_ctl_macro__width_6 dff_ldd_out ( | |
1142 | .scan_in(dff_ldd_out_scanin), | |
1143 | .scan_out(dff_ldd_out_scanout), | |
1144 | .din ({cic_cpq_stall,inc_ldd_count_pre,ldd_count_in[3:0]}), | |
1145 | .dout ({cpq_stall, inc_ldd_count ,ldd_count[3:0]}), | |
1146 | .l1clk(l1clk), | |
1147 | .siclk(siclk), | |
1148 | .soclk(soclk) | |
1149 | ); | |
1150 | ||
1151 | assign block_ldd_req = (ldd_count[3:2]==2'b11 & (ldd_count[1] | ldd_count[0] & inc_ldd_count)) | cpq_stall; | |
1152 | ||
1153 | ////////////////////// | |
1154 | // P4 stage | |
1155 | ////////////////////// | |
1156 | ||
1157 | assign lmc_ld_no_req_p4 = early_ld_b_sel_p4 & early_ld_cancel_w; | |
1158 | ||
1159 | assign kill_pcx_ld_req[7:0] = {8{(early_ld_b_sel_p4 & ~early_ld_cancel_w)}} & thread_w[7:0]; | |
1160 | ||
1161 | assign lmc_ld_vld_p4 = (casa_ld_to_pcx) | // CAS packet 2 | |
1162 | (ld_pcx_sel_p4) | // queued miss request | |
1163 | (early_ld_b_sel_p4 & ~early_ld_cancel_w);// early B/W request | |
1164 | ||
1165 | assign lmc_pcx_sel_p4[7:0] = ld_all_sel_p4[7:0]; | |
1166 | ||
1167 | assign lmc_ld_tid[2] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[6] | lmc_pcx_sel_p4[5] | lmc_pcx_sel_p4[4]; | |
1168 | assign lmc_ld_tid[1] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[6] | lmc_pcx_sel_p4[3] | lmc_pcx_sel_p4[2]; | |
1169 | assign lmc_ld_tid[0] = lmc_pcx_sel_p4[7] | lmc_pcx_sel_p4[5] | lmc_pcx_sel_p4[3] | lmc_pcx_sel_p4[1]; | |
1170 | ||
1171 | // Encode this info to save some flops. [3]=valid,[2:0]=tid | |
1172 | assign st_atom_p3[3] = |(sbc_st_atom_p3[7:0]); | |
1173 | assign st_atom_p3[2] = sbc_st_atom_p3[7] | sbc_st_atom_p3[6] | sbc_st_atom_p3[5] | sbc_st_atom_p3[4]; | |
1174 | assign st_atom_p3[1] = sbc_st_atom_p3[7] | sbc_st_atom_p3[6] | sbc_st_atom_p3[3] | sbc_st_atom_p3[2]; | |
1175 | assign st_atom_p3[0] = sbc_st_atom_p3[7] | sbc_st_atom_p3[5] | sbc_st_atom_p3[3] | sbc_st_atom_p3[1]; | |
1176 | ||
1177 | assign casa_bypass_d = st_atom_p3[3]; | |
1178 | ||
1179 | lsu_lmc_ctlmsff_ctl_macro__width_4 dff_st_atom_p4 ( | |
1180 | .scan_in(dff_st_atom_p4_scanin), | |
1181 | .scan_out(dff_st_atom_p4_scanout), | |
1182 | .din (st_atom_p3[3:0]), | |
1183 | .dout (st_atom_p4[3:0]), | |
1184 | .l1clk(l1clk), | |
1185 | .siclk(siclk), | |
1186 | .soclk(soclk) | |
1187 | ); | |
1188 | ||
1189 | // If casa is using the bypass register, other bypasses must be blocked. | |
1190 | assign casa_bypass_e = st_atom_p4[3]; | |
1191 | ||
1192 | // If STB read of CAS1 had an error, kill the CAS2 and restart the thread | |
1193 | assign st_atom_p4_in[3] = st_atom_p4[3] & sbc_kill_store_p4_; | |
1194 | assign st_atom_p4_in[2:0] = st_atom_p4[2:0]; | |
1195 | ||
1196 | assign st_atom_p4_dec[0] = st_atom_p4[3] & ~st_atom_p4[2] & ~st_atom_p4[1] & ~st_atom_p4[0]; | |
1197 | assign st_atom_p4_dec[1] = st_atom_p4[3] & ~st_atom_p4[2] & ~st_atom_p4[1] & st_atom_p4[0]; | |
1198 | assign st_atom_p4_dec[2] = st_atom_p4[3] & ~st_atom_p4[2] & st_atom_p4[1] & ~st_atom_p4[0]; | |
1199 | assign st_atom_p4_dec[3] = st_atom_p4[3] & ~st_atom_p4[2] & st_atom_p4[1] & st_atom_p4[0]; | |
1200 | assign st_atom_p4_dec[4] = st_atom_p4[3] & st_atom_p4[2] & ~st_atom_p4[1] & ~st_atom_p4[0]; | |
1201 | assign st_atom_p4_dec[5] = st_atom_p4[3] & st_atom_p4[2] & ~st_atom_p4[1] & st_atom_p4[0]; | |
1202 | assign st_atom_p4_dec[6] = st_atom_p4[3] & st_atom_p4[2] & st_atom_p4[1] & ~st_atom_p4[0]; | |
1203 | assign st_atom_p4_dec[7] = st_atom_p4[3] & st_atom_p4[2] & st_atom_p4[1] & st_atom_p4[0]; | |
1204 | ||
1205 | lsu_lmc_ctlmsff_ctl_macro__width_1 dff_st_atom_p5 ( | |
1206 | .scan_in(dff_st_atom_p5_scanin), | |
1207 | .scan_out(dff_st_atom_p5_scanout), | |
1208 | .din (st_atom_p4_in[3]), | |
1209 | .dout (casa_ld_to_pcx), | |
1210 | .l1clk(l1clk), | |
1211 | .siclk(siclk), | |
1212 | .soclk(soclk) | |
1213 | ); | |
1214 | ||
1215 | // Indeterminate ASI blocks | |
1216 | ||
1217 | assign asi_indet_sel = |(ld_asi_vld_rst[7:0] & lmd_asi_indet[7:0]); | |
1218 | assign asi_indet_retire = (lmc_lmq0_byp_sel[1] & lmd_asi_indet[0]) | | |
1219 | (lmc_lmq1_byp_sel[1] & lmd_asi_indet[1]) | | |
1220 | (lmc_lmq2_byp_sel[1] & lmd_asi_indet[2]) | | |
1221 | (lmc_lmq3_byp_sel[1] & lmd_asi_indet[3]) | | |
1222 | (lmc_lmq4_byp_sel[1] & lmd_asi_indet[4]) | | |
1223 | (lmc_lmq5_byp_sel[1] & lmd_asi_indet[5]) | | |
1224 | (lmc_lmq6_byp_sel[1] & lmd_asi_indet[6]) | | |
1225 | (lmc_lmq7_byp_sel[1] & lmd_asi_indet[7]) ; | |
1226 | ||
1227 | assign lmc_asi_indet_retire = asi_indet_retire; | |
1228 | ||
1229 | assign asi_indet_in = asi_indet_sel | (asi_indet_block & ~asi_indet_retire); | |
1230 | ||
1231 | lsu_lmc_ctlmsff_ctl_macro__width_1 dff_asi_indet ( | |
1232 | .scan_in(dff_asi_indet_scanin), | |
1233 | .scan_out(dff_asi_indet_scanout), | |
1234 | .din (asi_indet_in), | |
1235 | .dout (asi_indet_block), | |
1236 | .l1clk(l1clk), | |
1237 | .siclk(siclk), | |
1238 | .soclk(soclk) | |
1239 | ); | |
1240 | ||
1241 | //////////////////////////////////////////////////////////////////////////////// | |
1242 | // Data return | |
1243 | //////////////////////////////////////////////////////////////////////////////// | |
1244 | ||
1245 | // Select the correct thread's LMQ | |
1246 | assign lmc_byp_sel_e[0] = cpq_mx_thread[0] & cic_cpq_ld_rdy | | |
1247 | lmc_thrd_byp_sel_e[0]; | |
1248 | assign lmc_byp_sel_e[1] = cpq_mx_thread[1] & cic_cpq_ld_rdy | | |
1249 | lmc_thrd_byp_sel_e[1]; | |
1250 | assign lmc_byp_sel_e[2] = cpq_mx_thread[2] & cic_cpq_ld_rdy | | |
1251 | lmc_thrd_byp_sel_e[2]; | |
1252 | assign lmc_byp_sel_e[3] = cpq_mx_thread[3] & cic_cpq_ld_rdy | | |
1253 | lmc_thrd_byp_sel_e[3]; | |
1254 | assign lmc_byp_sel_e[4] = cpq_mx_thread[4] & cic_cpq_ld_rdy | | |
1255 | lmc_thrd_byp_sel_e[4]; | |
1256 | assign lmc_byp_sel_e[5] = cpq_mx_thread[5] & cic_cpq_ld_rdy | | |
1257 | lmc_thrd_byp_sel_e[5]; | |
1258 | assign lmc_byp_sel_e[6] = cpq_mx_thread[6] & cic_cpq_ld_rdy | | |
1259 | lmc_thrd_byp_sel_e[6]; | |
1260 | assign lmc_byp_sel_e[7] = cpq_mx_thread[7] & cic_cpq_ld_rdy | | |
1261 | lmc_thrd_byp_sel_e[7]; | |
1262 | ||
1263 | lsu_lmc_ctlmsff_ctl_macro__width_3 dff_cpq_tid ( | |
1264 | .scan_in(dff_cpq_tid_scanin), | |
1265 | .scan_out(dff_cpq_tid_scanout), | |
1266 | .din (cid_tid[2:0]), | |
1267 | .dout (lmc_cpq_tid_m[2:0]), | |
1268 | .l1clk(l1clk), | |
1269 | .siclk(siclk), | |
1270 | .soclk(soclk) | |
1271 | ); | |
1272 | ||
1273 | //////////////////////////////////////////////////////////////////////////////// | |
1274 | // LMQ bypassing | |
1275 | //////////////////////////////////////////////////////////////////////////////// | |
1276 | ||
1277 | assign ld_inst_nopref_b = ld_inst_vld_b & ~pref_inst_b; | |
1278 | ||
1279 | lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w ( | |
1280 | .scan_in(dff_ld_raw_w_scanin), | |
1281 | .scan_out(dff_ld_raw_w_scanout), | |
1282 | .l1clk (l1clk_pm1), | |
1283 | .din ({ld_inst_nopref_b,tid_b[2:0]}), | |
1284 | .dout ({ld_inst_nopref_w,tid_w[2:0]}), | |
1285 | .siclk(siclk), | |
1286 | .soclk(soclk) | |
1287 | ); | |
1288 | ||
1289 | assign ld_inst_unflushed_w = ld_inst_nopref_w & ~flush_w; | |
1290 | assign lmc_ld_inst_w = ld_inst_unflushed_w; | |
1291 | ||
1292 | assign ld_raw_bypass_w = ld_inst_unflushed_w & ld_full_raw_w & ~stb_cam_mhit_w & ~ldbl_w; | |
1293 | ||
1294 | assign lmc_full_raw_w = ld_raw_bypass_w; | |
1295 | ||
1296 | lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w2 ( | |
1297 | .scan_in(dff_ld_raw_w2_scanin), | |
1298 | .scan_out(dff_ld_raw_w2_scanout), | |
1299 | .din ({ld_raw_bypass_w, tid_w[2:0]}), | |
1300 | .dout ({ld_raw_bypass_w2,tid_w2[2:0]}), | |
1301 | .l1clk(l1clk), | |
1302 | .siclk(siclk), | |
1303 | .soclk(soclk) | |
1304 | ); | |
1305 | ||
1306 | lsu_lmc_ctlmsff_ctl_macro__width_4 dff_ld_raw_w3 ( | |
1307 | .scan_in(dff_ld_raw_w3_scanin), | |
1308 | .scan_out(dff_ld_raw_w3_scanout), | |
1309 | .din ({ld_raw_bypass_w2,tid_w2[2:0]}), | |
1310 | .dout ({ld_raw_bypass_w3,tid_w3[2:0]}), | |
1311 | .l1clk(l1clk), | |
1312 | .siclk(siclk), | |
1313 | .soclk(soclk) | |
1314 | ); | |
1315 | ||
1316 | assign thread_w3[0] = ~tid_w3[2] & ~tid_w3[1] & ~tid_w3[0]; | |
1317 | assign thread_w3[1] = ~tid_w3[2] & ~tid_w3[1] & tid_w3[0]; | |
1318 | assign thread_w3[2] = ~tid_w3[2] & tid_w3[1] & ~tid_w3[0]; | |
1319 | assign thread_w3[3] = ~tid_w3[2] & tid_w3[1] & tid_w3[0]; | |
1320 | assign thread_w3[4] = tid_w3[2] & ~tid_w3[1] & ~tid_w3[0]; | |
1321 | assign thread_w3[5] = tid_w3[2] & ~tid_w3[1] & tid_w3[0]; | |
1322 | assign thread_w3[6] = tid_w3[2] & tid_w3[1] & ~tid_w3[0]; | |
1323 | assign thread_w3[7] = tid_w3[2] & tid_w3[1] & tid_w3[0]; | |
1324 | ||
1325 | // Select the source to load into the bypass register | |
1326 | // [0] - swap data for CAS operation | |
1327 | // [1] - load return data from the ASI interface | |
1328 | // [2] - raw bypass from stb | |
1329 | // [3] - ldxa asi read data from registers internal to LSU (left side) | |
1330 | // [4] - ldxa asi read data from registers internal to LSU (right side) | |
1331 | // [5] - error code from L2 | |
1332 | assign lmc_lmq0_byp_sel[0] = dcc_casa_inst_b & thread_b[0] & ~(dcc_sync_pipe_w & thread_w[0]) & ~local_flush_b; | |
1333 | assign lmc_lmq1_byp_sel[0] = dcc_casa_inst_b & thread_b[1] & ~(dcc_sync_pipe_w & thread_w[1]) & ~local_flush_b; | |
1334 | assign lmc_lmq2_byp_sel[0] = dcc_casa_inst_b & thread_b[2] & ~(dcc_sync_pipe_w & thread_w[2]) & ~local_flush_b; | |
1335 | assign lmc_lmq3_byp_sel[0] = dcc_casa_inst_b & thread_b[3] & ~(dcc_sync_pipe_w & thread_w[3]) & ~local_flush_b; | |
1336 | assign lmc_lmq4_byp_sel[0] = dcc_casa_inst_b & thread_b[4] & ~(dcc_sync_pipe_w & thread_w[4]) & ~local_flush_b; | |
1337 | assign lmc_lmq5_byp_sel[0] = dcc_casa_inst_b & thread_b[5] & ~(dcc_sync_pipe_w & thread_w[5]) & ~local_flush_b; | |
1338 | assign lmc_lmq6_byp_sel[0] = dcc_casa_inst_b & thread_b[6] & ~(dcc_sync_pipe_w & thread_w[6]) & ~local_flush_b; | |
1339 | assign lmc_lmq7_byp_sel[0] = dcc_casa_inst_b & thread_b[7] & ~(dcc_sync_pipe_w & thread_w[7]) & ~local_flush_b; | |
1340 | ||
1341 | assign lmc_lmq0_byp_sel[1] = dcc_asi_rtn_vld[0] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1342 | assign lmc_lmq1_byp_sel[1] = dcc_asi_rtn_vld[1] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1343 | assign lmc_lmq2_byp_sel[1] = dcc_asi_rtn_vld[2] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1344 | assign lmc_lmq3_byp_sel[1] = dcc_asi_rtn_vld[3] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1345 | assign lmc_lmq4_byp_sel[1] = dcc_asi_rtn_vld[4] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1346 | assign lmc_lmq5_byp_sel[1] = dcc_asi_rtn_vld[5] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1347 | assign lmc_lmq6_byp_sel[1] = dcc_asi_rtn_vld[6] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1348 | assign lmc_lmq7_byp_sel[1] = dcc_asi_rtn_vld[7] & dcc_asi_rtn_rd & ~dcc_asi_rtn_excp; | |
1349 | ||
1350 | assign lmc_lmq0_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[0]; | |
1351 | assign lmc_lmq1_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[1]; | |
1352 | assign lmc_lmq2_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[2]; | |
1353 | assign lmc_lmq3_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[3]; | |
1354 | assign lmc_lmq4_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[4]; | |
1355 | assign lmc_lmq5_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[5]; | |
1356 | assign lmc_lmq6_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[6]; | |
1357 | assign lmc_lmq7_byp_sel[2] = ld_raw_bypass_w3 & ~(sbdlc_err | sbdlu_err) & thread_w3[7]; | |
1358 | ||
1359 | assign lmc_lmq0_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[0] & ~flush_w; | |
1360 | assign lmc_lmq1_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[1] & ~flush_w; | |
1361 | assign lmc_lmq2_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[2] & ~flush_w; | |
1362 | assign lmc_lmq3_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[3] & ~flush_w; | |
1363 | assign lmc_lmq4_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[4] & ~flush_w; | |
1364 | assign lmc_lmq5_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[5] & ~flush_w; | |
1365 | assign lmc_lmq6_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[6] & ~flush_w; | |
1366 | assign lmc_lmq7_byp_sel[3] = dcc_lsu_asi_sel_w & thread_w[7] & ~flush_w; | |
1367 | ||
1368 | assign lmc_lmq0_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[0]; | |
1369 | assign lmc_lmq1_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[1]; | |
1370 | assign lmc_lmq2_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[2]; | |
1371 | assign lmc_lmq3_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[3]; | |
1372 | assign lmc_lmq4_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[4]; | |
1373 | assign lmc_lmq5_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[5]; | |
1374 | assign lmc_lmq6_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[6]; | |
1375 | assign lmc_lmq7_byp_sel[4] = dcc_stb_diag_sel_w3 & thread_w3[7]; | |
1376 | ||
1377 | assign lmc_lmq_bypass_en[0] = |(lmc_lmq0_byp_sel[4:0]); | |
1378 | assign lmc_lmq_bypass_en[1] = |(lmc_lmq1_byp_sel[4:0]); | |
1379 | assign lmc_lmq_bypass_en[2] = |(lmc_lmq2_byp_sel[4:0]); | |
1380 | assign lmc_lmq_bypass_en[3] = |(lmc_lmq3_byp_sel[4:0]); | |
1381 | assign lmc_lmq_bypass_en[4] = |(lmc_lmq4_byp_sel[4:0]); | |
1382 | assign lmc_lmq_bypass_en[5] = |(lmc_lmq5_byp_sel[4:0]); | |
1383 | assign lmc_lmq_bypass_en[6] = |(lmc_lmq6_byp_sel[4:0]); | |
1384 | assign lmc_lmq_bypass_en[7] = |(lmc_lmq7_byp_sel[4:0]); | |
1385 | ||
1386 | // This indicates bypass data ready to bypass back to the registers. | |
1387 | // It should not be valid for CAS/DIAG storage | |
1388 | assign lmq_bypass_vld[0] = |(lmc_lmq0_byp_sel[4:1]); | |
1389 | assign lmq_bypass_vld[1] = |(lmc_lmq1_byp_sel[4:1]); | |
1390 | assign lmq_bypass_vld[2] = |(lmc_lmq2_byp_sel[4:1]); | |
1391 | assign lmq_bypass_vld[3] = |(lmc_lmq3_byp_sel[4:1]); | |
1392 | assign lmq_bypass_vld[4] = |(lmc_lmq4_byp_sel[4:1]); | |
1393 | assign lmq_bypass_vld[5] = |(lmc_lmq5_byp_sel[4:1]); | |
1394 | assign lmq_bypass_vld[6] = |(lmc_lmq6_byp_sel[4:1]); | |
1395 | assign lmq_bypass_vld[7] = |(lmc_lmq7_byp_sel[4:1]); | |
1396 | ||
1397 | // Valid tracking | |
1398 | assign ldbyp_vld_en[7:0] = ~ldbyp_rst[7:0] & // Reset | |
1399 | (lmq_bypass_vld[7:0] | ldbyp_vld[7:0]); // Set/hold | |
1400 | ||
1401 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_ldbyp_vld ( | |
1402 | .scan_in(dff_ldbyp_vld_scanin), | |
1403 | .scan_out(dff_ldbyp_vld_scanout), | |
1404 | .din (ldbyp_vld_en[7:0]), | |
1405 | .dout (ldbyp_vld[7:0]), | |
1406 | .l1clk(l1clk), | |
1407 | .siclk(siclk), | |
1408 | .soclk(soclk) | |
1409 | ); | |
1410 | ||
1411 | // A valid entry ready for bypass can only go when there are no loads | |
1412 | // in the pipe and no data coming from the CPQ. | |
1413 | ||
1414 | assign ld_bypass_ok_d = ~dec_ld_inst_d & ~cic_div_stall_d & ~casa_bypass_d; | |
1415 | ||
1416 | lsu_lmc_ctlmsff_ctl_macro__width_1 dff_ld_inst_e ( | |
1417 | .scan_in(dff_ld_inst_e_scanin), | |
1418 | .scan_out(dff_ld_inst_e_scanout), | |
1419 | .din (ld_bypass_ok_d), | |
1420 | .dout (ld_bypass_ok_e), | |
1421 | .l1clk(l1clk), | |
1422 | .siclk(siclk), | |
1423 | .soclk(soclk) | |
1424 | ); | |
1425 | ||
1426 | // Because of the low priority of bypass, and because of the fixed thread priority, | |
1427 | // there is a livelock concern. If a bypass has been ready for eight cycles without | |
1428 | // proceeding, a decode block will be issued to free up the pipe. The block will | |
1429 | // be removed once the bypass queue clears. | |
1430 | ||
1431 | assign byp_cnt_rst = &(~ldbyp_vld[7:0] | lmc_thrd_byp_sel_e[7:0]); | |
1432 | assign byp_cnt_in[2:0] = {3{~byp_cnt_rst}} & (lmc_ld_stall ? byp_cnt[2:0] : (byp_cnt[2:0] + 3'b001)); | |
1433 | ||
1434 | lsu_lmc_ctlmsff_ctl_macro__width_3 dff_byp_cnt ( | |
1435 | .scan_in(dff_byp_cnt_scanin), | |
1436 | .scan_out(dff_byp_cnt_scanout), | |
1437 | .din (byp_cnt_in[2:0]), | |
1438 | .dout (byp_cnt[2:0]), | |
1439 | .l1clk(l1clk), | |
1440 | .siclk(siclk), | |
1441 | .soclk(soclk) | |
1442 | ); | |
1443 | assign lmc_ld_stall = &(byp_cnt[2:0]); | |
1444 | ||
1445 | assign ld_bypass_e = ld_bypass_ok_e & cic_cpq_ld_rdy_; | |
1446 | ||
1447 | assign lmc_thrd_byp_sel_e[0] = ldbyp_vld[0] & ld_bypass_e; | |
1448 | assign lmc_thrd_byp_sel_e[1] = ldbyp_vld[1] & ~ldbyp_vld[0] & ld_bypass_e; | |
1449 | assign lmc_thrd_byp_sel_e[2] = ldbyp_vld[2] & ~(|ldbyp_vld[1:0]) & ld_bypass_e; | |
1450 | assign lmc_thrd_byp_sel_e[3] = ldbyp_vld[3] & ~(|ldbyp_vld[2:0]) & ld_bypass_e; | |
1451 | assign lmc_thrd_byp_sel_e[4] = ldbyp_vld[4] & ~(|ldbyp_vld[3:0]) & ld_bypass_e; | |
1452 | assign lmc_thrd_byp_sel_e[5] = ldbyp_vld[5] & ~(|ldbyp_vld[4:0]) & ld_bypass_e; | |
1453 | assign lmc_thrd_byp_sel_e[6] = ldbyp_vld[6] & ~(|ldbyp_vld[5:0]) & ld_bypass_e; | |
1454 | assign lmc_thrd_byp_sel_e[7] = ldbyp_vld[7] & ~(|ldbyp_vld[6:0]) & ld_bypass_e; | |
1455 | ||
1456 | assign byp_vld_e = |(lmc_thrd_byp_sel_e[7:0]); | |
1457 | ||
1458 | assign ldbyp_rst[7:0] = lmc_thrd_byp_sel_e[7:0]; | |
1459 | ||
1460 | // Combine true bypass and a casa issue | |
1461 | assign thrd_byp_sel_e[7:0] = lmc_thrd_byp_sel_e[7:0] | st_atom_p4_dec[7:0]; | |
1462 | ||
1463 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_thrd_byp_sel_m ( | |
1464 | .scan_in(dff_thrd_byp_sel_m_scanin), | |
1465 | .scan_out(dff_thrd_byp_sel_m_scanout), | |
1466 | .din ({ byp_vld_e,thrd_byp_sel_e[7:0]}), | |
1467 | .dout ({lmc_byp_vld_m,thrd_byp_sel_m[7:0]}), | |
1468 | .l1clk(l1clk), | |
1469 | .siclk(siclk), | |
1470 | .soclk(soclk) | |
1471 | ); | |
1472 | ||
1473 | assign lmc_thrd_byp_sel_m[7:0] = thrd_byp_sel_m[7:0]; | |
1474 | ||
1475 | assign lmc_asi_bypass_m = |(thrd_byp_sel_m[7:0] & lmd_asi_ld[7:0]); | |
1476 | ||
1477 | assign lmc_byp_tid_m[2] = thrd_byp_sel_m[7] | thrd_byp_sel_m[6] | thrd_byp_sel_m[5] | thrd_byp_sel_m[4]; | |
1478 | assign lmc_byp_tid_m[1] = thrd_byp_sel_m[7] | thrd_byp_sel_m[6] | thrd_byp_sel_m[3] | thrd_byp_sel_m[2]; | |
1479 | assign lmc_byp_tid_m[0] = thrd_byp_sel_m[7] | thrd_byp_sel_m[5] | thrd_byp_sel_m[3] | thrd_byp_sel_m[1]; | |
1480 | ||
1481 | ||
1482 | //////////////////////////////////////////////////////////////////////////////// | |
1483 | // Block load control | |
1484 | // Each incoming block (64B) load instruction must cause four requests to the | |
1485 | // L2 which return 16B each. | |
1486 | //////////////////////////////////////////////////////////////////////////////// | |
1487 | ||
1488 | assign bld_inst_w[7:0] = {8{blk_inst_w & ld_inst_unflushed_w}} & thread_w[7:0]; | |
1489 | ||
1490 | assign bld_pending[7:0] = bld_inst_w[7:0] | bld_pend_hold[7:0]; | |
1491 | ||
1492 | assign bld_pending_in[7:0] = bld_pending[7:0] & ~bld_reset[7:0]; | |
1493 | ||
1494 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_bld_pending ( | |
1495 | .scan_in(dff_bld_pending_scanin), | |
1496 | .scan_out(dff_bld_pending_scanout), | |
1497 | .l1clk (l1clk_pm1), | |
1498 | .din (bld_pending_in[7:0]), | |
1499 | .dout (bld_pend_hold[7:0]), | |
1500 | .siclk(siclk), | |
1501 | .soclk(soclk) | |
1502 | ); | |
1503 | ||
1504 | assign bld_addr54_p3[1:0] = {2{ld_pcx_rq_sel[0]}} & bld_cnt0[1:0] | | |
1505 | {2{ld_pcx_rq_sel[1]}} & bld_cnt1[1:0] | | |
1506 | {2{ld_pcx_rq_sel[2]}} & bld_cnt2[1:0] | | |
1507 | {2{ld_pcx_rq_sel[3]}} & bld_cnt3[1:0] | | |
1508 | {2{ld_pcx_rq_sel[4]}} & bld_cnt4[1:0] | | |
1509 | {2{ld_pcx_rq_sel[5]}} & bld_cnt5[1:0] | | |
1510 | {2{ld_pcx_rq_sel[6]}} & bld_cnt6[1:0] | | |
1511 | {2{ld_pcx_rq_sel[7]}} & bld_cnt7[1:0] ; | |
1512 | ||
1513 | assign bld_req_p3 = |(ld_pcx_rq_sel[7:0] & bld_pending[7:0]); | |
1514 | ||
1515 | lsu_lmc_ctlmsff_ctl_macro__width_3 dff_bld_addr ( | |
1516 | .scan_in(dff_bld_addr_scanin), | |
1517 | .scan_out(dff_bld_addr_scanout), | |
1518 | .l1clk (l1clk_pm1), | |
1519 | .din ({bld_addr54_p3[1:0], bld_req_p3}), | |
1520 | .dout ({lmc_bld_addr54[1:0],lmc_bld_req}), | |
1521 | .siclk(siclk), | |
1522 | .soclk(soclk) | |
1523 | ); | |
1524 | assign lmc_bld_req_ = ~lmc_bld_req; | |
1525 | ||
1526 | // Thread 0 | |
1527 | ||
1528 | // Counter is incremented when the preceeding request was accepted. | |
1529 | assign bld_cnt0_in[1:0] = bld_cnt0[1:0] + {1'b0,inc_bld0_cnt}; | |
1530 | assign inc_bld0_cnt = ld_pcx_rq_sel[0] & ~perr_inv[0] & bld_pending[0]; | |
1531 | ||
1532 | // Reset the bld pending state when the final request is accepted. | |
1533 | assign bld_reset[0] = ld_pcx_rq_sel[0] & (&(bld_cnt0[1:0])); | |
1534 | ||
1535 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1536 | // following requests still go to the pcx. | |
1537 | assign bld_hold[0] = ~(&(bld_cnt0[1:0])) & bld_pending[0]; | |
1538 | ||
1539 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt0 ( | |
1540 | .scan_in(dff_bld_cnt0_scanin), | |
1541 | .scan_out(dff_bld_cnt0_scanout), | |
1542 | .l1clk (l1clk_pm1), | |
1543 | .din (bld_cnt0_in[1:0]), | |
1544 | .dout (bld_cnt0[1:0]), | |
1545 | .siclk(siclk), | |
1546 | .soclk(soclk) | |
1547 | ); | |
1548 | ||
1549 | // Thread 1 | |
1550 | ||
1551 | // Counter is incremented when the preceeding request was accepted. | |
1552 | assign bld_cnt1_in[1:0] = bld_cnt1[1:0] + {1'b0,inc_bld1_cnt}; | |
1553 | assign inc_bld1_cnt = ld_pcx_rq_sel[1] & ~perr_inv[1] & bld_pending[1]; | |
1554 | ||
1555 | // Reset the bld pending state when the final request is accepted. | |
1556 | assign bld_reset[1] = ld_pcx_rq_sel[1] & (&(bld_cnt1[1:0])); | |
1557 | ||
1558 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1559 | // following requests still go to the pcx. | |
1560 | assign bld_hold[1] = ~(&(bld_cnt1[1:0])) & bld_pending[1]; | |
1561 | ||
1562 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt1 ( | |
1563 | .scan_in(dff_bld_cnt1_scanin), | |
1564 | .scan_out(dff_bld_cnt1_scanout), | |
1565 | .l1clk (l1clk_pm1), | |
1566 | .din (bld_cnt1_in[1:0]), | |
1567 | .dout (bld_cnt1[1:0]), | |
1568 | .siclk(siclk), | |
1569 | .soclk(soclk) | |
1570 | ); | |
1571 | ||
1572 | // Thread 2 | |
1573 | ||
1574 | // Counter is incremented when the preceeding request was accepted. | |
1575 | assign bld_cnt2_in[1:0] = bld_cnt2[1:0] + {1'b0,inc_bld2_cnt}; | |
1576 | assign inc_bld2_cnt = ld_pcx_rq_sel[2] & ~perr_inv[2] & bld_pending[2]; | |
1577 | ||
1578 | // Reset the bld pending state when the final request is accepted. | |
1579 | assign bld_reset[2] = ld_pcx_rq_sel[2] & (&(bld_cnt2[1:0])); | |
1580 | ||
1581 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1582 | // following requests still go to the pcx. | |
1583 | assign bld_hold[2] = ~(&(bld_cnt2[1:0])) & bld_pending[2]; | |
1584 | ||
1585 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt2 ( | |
1586 | .scan_in(dff_bld_cnt2_scanin), | |
1587 | .scan_out(dff_bld_cnt2_scanout), | |
1588 | .l1clk (l1clk_pm1), | |
1589 | .din (bld_cnt2_in[1:0]), | |
1590 | .dout (bld_cnt2[1:0]), | |
1591 | .siclk(siclk), | |
1592 | .soclk(soclk) | |
1593 | ); | |
1594 | ||
1595 | // Thread 3 | |
1596 | ||
1597 | // Counter is incremented when the preceeding request was accepted. | |
1598 | assign bld_cnt3_in[1:0] = bld_cnt3[1:0] + {1'b0,inc_bld3_cnt}; | |
1599 | assign inc_bld3_cnt = ld_pcx_rq_sel[3] & ~perr_inv[3] & bld_pending[3]; | |
1600 | ||
1601 | // Reset the bld pending state when the final request is accepted. | |
1602 | assign bld_reset[3] = ld_pcx_rq_sel[3] & (&(bld_cnt3[1:0])); | |
1603 | ||
1604 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1605 | // following requests still go to the pcx. | |
1606 | assign bld_hold[3] = ~(&(bld_cnt3[1:0])) & bld_pending[3]; | |
1607 | ||
1608 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt3 ( | |
1609 | .scan_in(dff_bld_cnt3_scanin), | |
1610 | .scan_out(dff_bld_cnt3_scanout), | |
1611 | .l1clk (l1clk_pm1), | |
1612 | .din (bld_cnt3_in[1:0]), | |
1613 | .dout (bld_cnt3[1:0]), | |
1614 | .siclk(siclk), | |
1615 | .soclk(soclk) | |
1616 | ); | |
1617 | ||
1618 | // Thread 4 | |
1619 | ||
1620 | // Counter is incremented when the preceeding request was accepted. | |
1621 | assign bld_cnt4_in[1:0] = bld_cnt4[1:0] + {1'b0,inc_bld4_cnt}; | |
1622 | assign inc_bld4_cnt = ld_pcx_rq_sel[4] & ~perr_inv[4] & bld_pending[4]; | |
1623 | ||
1624 | // Reset the bld pending state when the final request is accepted. | |
1625 | assign bld_reset[4] = ld_pcx_rq_sel[4] & (&(bld_cnt4[1:0])); | |
1626 | ||
1627 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1628 | // following requests still go to the pcx. | |
1629 | assign bld_hold[4] = ~(&(bld_cnt4[1:0])) & bld_pending[4]; | |
1630 | ||
1631 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt4 ( | |
1632 | .scan_in(dff_bld_cnt4_scanin), | |
1633 | .scan_out(dff_bld_cnt4_scanout), | |
1634 | .l1clk (l1clk_pm1), | |
1635 | .din (bld_cnt4_in[1:0]), | |
1636 | .dout (bld_cnt4[1:0]), | |
1637 | .siclk(siclk), | |
1638 | .soclk(soclk) | |
1639 | ); | |
1640 | ||
1641 | // Thread 5 | |
1642 | ||
1643 | // Counter is incremented when the preceeding request was accepted. | |
1644 | assign bld_cnt5_in[1:0] = bld_cnt5[1:0] + {1'b0,inc_bld5_cnt}; | |
1645 | assign inc_bld5_cnt = ld_pcx_rq_sel[5] & ~perr_inv[5] & bld_pending[5]; | |
1646 | ||
1647 | // Reset the bld pending state when the final request is accepted. | |
1648 | assign bld_reset[5] = ld_pcx_rq_sel[5] & (&(bld_cnt5[1:0])); | |
1649 | ||
1650 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1651 | // following requests still go to the pcx. | |
1652 | assign bld_hold[5] = ~(&(bld_cnt5[1:0])) & bld_pending[5]; | |
1653 | ||
1654 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt5 ( | |
1655 | .scan_in(dff_bld_cnt5_scanin), | |
1656 | .scan_out(dff_bld_cnt5_scanout), | |
1657 | .l1clk (l1clk_pm1), | |
1658 | .din (bld_cnt5_in[1:0]), | |
1659 | .dout (bld_cnt5[1:0]), | |
1660 | .siclk(siclk), | |
1661 | .soclk(soclk) | |
1662 | ); | |
1663 | ||
1664 | // Thread 6 | |
1665 | ||
1666 | // Counter is incremented when the preceeding request was accepted. | |
1667 | assign bld_cnt6_in[1:0] = bld_cnt6[1:0] + {1'b0,inc_bld6_cnt}; | |
1668 | assign inc_bld6_cnt = ld_pcx_rq_sel[6] & ~perr_inv[6] & bld_pending[6]; | |
1669 | ||
1670 | // Reset the bld pending state when the final request is accepted. | |
1671 | assign bld_reset[6] = ld_pcx_rq_sel[6] & (&(bld_cnt6[1:0])); | |
1672 | ||
1673 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1674 | // following requests still go to the pcx. | |
1675 | assign bld_hold[6] = ~(&(bld_cnt6[1:0])) & bld_pending[6]; | |
1676 | ||
1677 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt6 ( | |
1678 | .scan_in(dff_bld_cnt6_scanin), | |
1679 | .scan_out(dff_bld_cnt6_scanout), | |
1680 | .l1clk (l1clk_pm1), | |
1681 | .din (bld_cnt6_in[1:0]), | |
1682 | .dout (bld_cnt6[1:0]), | |
1683 | .siclk(siclk), | |
1684 | .soclk(soclk) | |
1685 | ); | |
1686 | ||
1687 | // Thread 7 | |
1688 | ||
1689 | // Counter is incremented when the preceeding request was accepted. | |
1690 | assign bld_cnt7_in[1:0] = bld_cnt7[1:0] + {1'b0,inc_bld7_cnt}; | |
1691 | assign inc_bld7_cnt = ld_pcx_rq_sel[7] & ~perr_inv[7] & bld_pending[7]; | |
1692 | ||
1693 | // Reset the bld pending state when the final request is accepted. | |
1694 | assign bld_reset[7] = ld_pcx_rq_sel[7] & (&(bld_cnt7[1:0])); | |
1695 | ||
1696 | // Requests 1-3 must prevent the ld_pcx_vld state from being reset so that | |
1697 | // following requests still go to the pcx. | |
1698 | assign bld_hold[7] = ~(&(bld_cnt7[1:0])) & bld_pending[7]; | |
1699 | ||
1700 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bld_cnt7 ( | |
1701 | .scan_in(dff_bld_cnt7_scanin), | |
1702 | .scan_out(dff_bld_cnt7_scanout), | |
1703 | .l1clk (l1clk_pm1), | |
1704 | .din (bld_cnt7_in[1:0]), | |
1705 | .dout (bld_cnt7[1:0]), | |
1706 | .siclk(siclk), | |
1707 | .soclk(soclk) | |
1708 | ); | |
1709 | ||
1710 | // Increment Rd after a load returns (used for QUAD/LDD/BLD) | |
1711 | // This path is also used to update the entry during a set invalidate to | |
1712 | // clear the error code. | |
1713 | ||
1714 | assign lmc_rd_update[7:0] = {8{cic_l2fill_vld_e}} & lmc_byp_sel_e[7:0]; | |
1715 | ||
1716 | assign bld_annul_rst[7:0] = {8{(&lmd_rd_e[2:1] & cic_l2fill_vld_e)}} & lmc_byp_sel_e[7:0]; | |
1717 | ||
1718 | assign bld_annul_in[7:0] = ~bld_annul_rst[7:0] & (bld_annul[7:0] | bld_inst_w[7:0]); | |
1719 | ||
1720 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_bld_bypass ( | |
1721 | .scan_in(dff_bld_bypass_scanin), | |
1722 | .scan_out(dff_bld_bypass_scanout), | |
1723 | .din (bld_annul_in[7:0]), | |
1724 | .dout (bld_annul[7:0]), | |
1725 | .l1clk(l1clk), | |
1726 | .siclk(siclk), | |
1727 | .soclk(soclk) | |
1728 | ); | |
1729 | ||
1730 | assign block_load_annul = (cpq_mx_thread[0] & bld_annul[0]) | | |
1731 | (cpq_mx_thread[1] & bld_annul[1]) | | |
1732 | (cpq_mx_thread[2] & bld_annul[2]) | | |
1733 | (cpq_mx_thread[3] & bld_annul[3]) | | |
1734 | (cpq_mx_thread[4] & bld_annul[4]) | | |
1735 | (cpq_mx_thread[5] & bld_annul[5]) | | |
1736 | (cpq_mx_thread[6] & bld_annul[6]) | | |
1737 | (cpq_mx_thread[7] & bld_annul[7]) ; | |
1738 | ||
1739 | assign lmc_bld_annul = block_load_annul; | |
1740 | ||
1741 | // Must track the l2miss behavior for block loads to properly trap & | |
1742 | // write frf on perfmon events. Block loads will act based on the first | |
1743 | // helper. If it misses, the entire instruction is considered a miss. | |
1744 | ||
1745 | assign bld_miss_set[7:0] = bld_annul[7:0] & cpq_mx_thread[7:0] & {8{lmd_rd_e[2:1] == 2'b00}} & {8{cid_l2miss}}; | |
1746 | ||
1747 | assign bld_miss_in[7:0] = (bld_miss_set[7:0] | bld_miss[7:0]) & | |
1748 | ~({8{report_and_clear_error}} & cpq_mx_thread[7:0]); | |
1749 | ||
1750 | assign bld_miss[7:0] = bld_miss_set[7:0] | bld_miss_out[7:0]; | |
1751 | ||
1752 | assign bld_pass7 = |(bld_annul_rst[7:0]) & ~report_and_clear_error; | |
1753 | ||
1754 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_bld_miss ( | |
1755 | .scan_in(dff_bld_miss_scanin), | |
1756 | .scan_out(dff_bld_miss_scanout), | |
1757 | .din ({bld_miss_in[7:0], bld_pass7}), | |
1758 | .dout ({bld_miss_out[7:0],bld_pass7_done}), | |
1759 | .l1clk(l1clk), | |
1760 | .siclk(siclk), | |
1761 | .soclk(soclk) | |
1762 | ); | |
1763 | ||
1764 | assign lmc_bld_last_e = bld_pass7_done & report_and_clear_error; | |
1765 | ||
1766 | assign lmc_bld_miss_e = (cpq_mx_thread[0] & bld_miss[0]) | | |
1767 | (cpq_mx_thread[1] & bld_miss[1]) | | |
1768 | (cpq_mx_thread[2] & bld_miss[2]) | | |
1769 | (cpq_mx_thread[3] & bld_miss[3]) | | |
1770 | (cpq_mx_thread[4] & bld_miss[4]) | | |
1771 | (cpq_mx_thread[5] & bld_miss[5]) | | |
1772 | (cpq_mx_thread[6] & bld_miss[6]) | | |
1773 | (cpq_mx_thread[7] & bld_miss[7]) ; | |
1774 | ||
1775 | //////////////////////////////////////////////////////////////////////////////// | |
1776 | // Tracking issued prefetches | |
1777 | //////////////////////////////////////////////////////////////////////////////// | |
1778 | ||
1779 | assign pref_issued[7:0] = (ld_all_sel_p4[7:0] & {8{ld_pcx_sel_p4 & lmd_pcx_pref & ~(early_ld_b_sel_p4 & flush_w)}}) | | |
1780 | (thread_w[7:0] & {8{pref_inst_w & excep_only_flush_w}}) ; | |
1781 | ||
1782 | lsu_lmc_ctlmsff_ctl_macro__width_8 dff_pref_issued ( | |
1783 | .scan_in(dff_pref_issued_scanin), | |
1784 | .scan_out(dff_pref_issued_scanout), | |
1785 | .din (pref_issued[7:0]), | |
1786 | .dout (lmc_pref_issued[7:0]), | |
1787 | .l1clk(l1clk), | |
1788 | .siclk(siclk), | |
1789 | .soclk(soclk) | |
1790 | ); | |
1791 | ||
1792 | //////////////////////////////////////////////////////////////////////////////// | |
1793 | // Figure size mask for loads | |
1794 | // CAS(X)A uses the store format (00001111, 11110000, or 11111111) | |
1795 | // Loads use 00=byte, 01=hw, 10=wd, 11=dw, 100=quad; 5 MSB's are zero | |
1796 | //////////////////////////////////////////////////////////////////////////////// | |
1797 | ||
1798 | assign lmc_ld_sz[4] = casa_ld_to_pcx & (~lmd_addrb2 | lmd_sz_b0); | |
1799 | assign lmc_ld_sz[3] = casa_ld_to_pcx & (lmd_addrb2 | lmd_sz_b0); | |
1800 | assign lmc_ld_sz[2] = lmc_ld_sz[3] | (lmd_ldbl & lmd_sz_b0); | |
1801 | assign lmc_ld_sz[1] = lmc_ld_sz[3] | (~casa_ld_to_pcx & lmd_sz_b1 & ~lmd_sz_b0) | (~lmd_ldbl & lmd_sz_b1 & lmd_sz_b0); | |
1802 | assign lmc_ld_sz[0] = (casa_ld_to_pcx & lmd_addrb2) | (lmd_ldbl ^ lmd_sz_b0); | |
1803 | ||
1804 | //////////////////////////////////////////////////////////////////////////////// | |
1805 | // Select hi or low 64b for load return | |
1806 | // For LDD (sz=10), addr[3] determines | |
1807 | // For QUAD (sz=11), first pass is hi, second is low | |
1808 | //////////////////////////////////////////////////////////////////////////////// | |
1809 | ||
1810 | assign lmc_byp_data_hi = cic_cpq_ld_rdy & ~lmd_fill_addr_b3_e & ~(cic_oddrd_e & lmd_fill_sz_b0_e); | |
1811 | ||
1812 | //////////////////////////////////////////////////////////////////////////////// | |
1813 | // Clock enable for the bypass/fill data register | |
1814 | ||
1815 | assign lmc_byp_data_enable = cic_l2fill_vld_e | byp_vld_e | cic_ext_interrupt; | |
1816 | ||
1817 | //////////////////////////////////////////////////////////////////////////////// | |
1818 | // Parity errors require an inval request to be sent to L2. | |
1819 | //////////////////////////////////////////////////////////////////////////////// | |
1820 | ||
1821 | assign perr_set[7:0] = {8{perror_w & ~(ld_raw_bypass_w | flush_w)}} & thread_w[7:0]; | |
1822 | ||
1823 | assign perr_inv_in[7:0] = perr_inv[7:0] & ~ld_pcx_rq_sel[7:0]; | |
1824 | ||
1825 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_perr ( | |
1826 | .scan_in(dff_perr_scanin), | |
1827 | .scan_out(dff_perr_scanout), | |
1828 | .l1clk (l1clk_pm1), | |
1829 | .din ({perr_inv_in[7:0], ld_inv_p3}), | |
1830 | .dout ({perr_inv_out[7:0],ld_inv_p4}), | |
1831 | .siclk(siclk), | |
1832 | .soclk(soclk) | |
1833 | ); | |
1834 | ||
1835 | assign perr_inv[7:0] = perr_inv_out[7:0] | perr_set[7:0]; | |
1836 | ||
1837 | // INV bit in pcx is asserted for line invalidation requests and for CAS2 packets | |
1838 | // if the store buffer had a UE | |
1839 | assign ld_inv_p3 = |(ld_pcx_rq_sel[7:0] & perr_inv[7:0]) | (sbc_force_inv & casa_bypass_e); | |
1840 | ||
1841 | // INV bit is also asserted for prefetch ICE | |
1842 | assign lmc_ld_inv_p4 = ld_inv_p4 | (lmd_pcx_pref & lmd_ldbl); | |
1843 | ||
1844 | // Error is reported when the inval_all packet comes back | |
1845 | // encoded error type: 00=valid, 01=tag, 10=mhit, 11=data | |
1846 | ||
1847 | assign lsu_dcvp_err_e2 = cic_set_inval & (~lmd_dc_err_e[1] & ~lmd_dc_err_e[0]); | |
1848 | assign lsu_dctp_err_e2 = cic_set_inval & (~lmd_dc_err_e[1] & lmd_dc_err_e[0]); | |
1849 | assign lsu_dcmh_err_e2 = cic_set_inval & ( lmd_dc_err_e[1] & ~lmd_dc_err_e[0]); | |
1850 | assign lsu_dcdp_err_e2 = cic_set_inval & ( lmd_dc_err_e[1] & lmd_dc_err_e[0]); | |
1851 | ||
1852 | lsu_lmc_ctlmsff_ctl_macro__width_4 dff_dcerr ( | |
1853 | .scan_in(dff_dcerr_scanin), | |
1854 | .scan_out(dff_dcerr_scanout), | |
1855 | .din ({lsu_dcvp_err_e2,lsu_dctp_err_e2,lsu_dcmh_err_e2,lsu_dcdp_err_e2}), | |
1856 | .dout ({lsu_dcvp_err_g ,lsu_dctp_err_g ,lsu_dcmh_err_g ,lsu_dcdp_err_g }), | |
1857 | .l1clk(l1clk), | |
1858 | .siclk(siclk), | |
1859 | .soclk(soclk) | |
1860 | ); | |
1861 | ||
1862 | assign lsu_dcerr_tid_g[2:0] = lmc_cpq_tid_m[2:0]; | |
1863 | ||
1864 | // Check that errors are never signaled during normal testing | |
1865 | ||
1866 | ||
1867 | ||
1868 | //////////////////////////////////////////////////////////////////////////////// | |
1869 | // L2 errors | |
1870 | // Multi-cycle loads (LDD,BLD) must wait until the final update to report the | |
1871 | // error. Block loads will stop updating registers once an unc. error is detected. | |
1872 | // If multiple errors of different types are detected on the block load helpers, | |
1873 | // the highest priority error will be reported. (UE > ND > CE) | |
1874 | //////////////////////////////////////////////////////////////////////////////// | |
1875 | ||
1876 | assign l2_err[1:0] = ({2{cpq_mx_thread[0]}} & l2_err0[1:0]) | | |
1877 | ({2{cpq_mx_thread[1]}} & l2_err1[1:0]) | | |
1878 | ({2{cpq_mx_thread[2]}} & l2_err2[1:0]) | | |
1879 | ({2{cpq_mx_thread[3]}} & l2_err3[1:0]) | | |
1880 | ({2{cpq_mx_thread[4]}} & l2_err4[1:0]) | | |
1881 | ({2{cpq_mx_thread[5]}} & l2_err5[1:0]) | | |
1882 | ({2{cpq_mx_thread[6]}} & l2_err6[1:0]) | | |
1883 | ({2{cpq_mx_thread[7]}} & l2_err7[1:0]) ; | |
1884 | ||
1885 | assign l2_err_qual[1] = cic_cpq_ld_rdy & ceter_pscce_cpq & | |
1886 | ((cid_err[1] & ~cid_err[0] & cid_dcsoc_err_e & cerer_socu) | | |
1887 | (cid_err[1] & ~cid_err[0] & ~cid_dcsoc_err_e & cerer_dcl2u) | | |
1888 | (cid_err[1] & cid_err[0] & cerer_dcl2nd)); | |
1889 | ||
1890 | assign l2_err_qual[0] = cic_cpq_ld_rdy & | |
1891 | ((~cid_err[1] & cid_err[0] & cid_dcsoc_err_e & cerer_socc) | | |
1892 | (~cid_err[1] & cid_err[0] & ~cid_dcsoc_err_e & cerer_dcl2c) | | |
1893 | ( cid_err[1] & cid_err[0] & ceter_pscce_cpq & cerer_dcl2nd)); | |
1894 | ||
1895 | assign l2_err_new[1] = l2_err[1] | l2_err_qual[1]; | |
1896 | assign l2_err_new[0] = (l2_err[0] & ~l2_err_qual[1]) | | |
1897 | (l2_err_qual[1] & l2_err_qual[0]) | | |
1898 | (~l2_err[1] & l2_err_qual[0]) | | |
1899 | (l2_err[1] & l2_err[0]); | |
1900 | ||
1901 | // Suppress register update on any uncorrectable error, including accumulated errors. | |
1902 | assign lmc_l2_err_noup = l2_err_new[1]; | |
1903 | ||
1904 | // For uncorrectable errors on fill data, inject a parity error into the D$ | |
1905 | // Don't need to worry about the accumulated error since LDD & BLD don't fill | |
1906 | // Inject errors even if ceter.pscce is off (for timing reasons). | |
1907 | assign lmc_l2_uerr = (cerer_dcl2u & cid_err[1] & ~cid_err[0]) | (cerer_dcl2nd & cid_err[1] & cid_err[0]); | |
1908 | ||
1909 | assign l2_err0_in[1:0] = cpq_mx_thread[0] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err0[1:0]; | |
1910 | assign l2_err1_in[1:0] = cpq_mx_thread[1] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err1[1:0]; | |
1911 | assign l2_err2_in[1:0] = cpq_mx_thread[2] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err2[1:0]; | |
1912 | assign l2_err3_in[1:0] = cpq_mx_thread[3] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err3[1:0]; | |
1913 | assign l2_err4_in[1:0] = cpq_mx_thread[4] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err4[1:0]; | |
1914 | assign l2_err5_in[1:0] = cpq_mx_thread[5] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err5[1:0]; | |
1915 | assign l2_err6_in[1:0] = cpq_mx_thread[6] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err6[1:0]; | |
1916 | assign l2_err7_in[1:0] = cpq_mx_thread[7] ? (l2_err_new[1:0] & {2{~report_and_clear_error}}) : l2_err7[1:0]; | |
1917 | ||
1918 | lsu_lmc_ctlmsff_ctl_macro__width_16 dff_l2errcode ( | |
1919 | .scan_in(dff_l2errcode_scanin), | |
1920 | .scan_out(dff_l2errcode_scanout), | |
1921 | .din ({l2_err0_in[1:0],l2_err1_in[1:0],l2_err2_in[1:0],l2_err3_in[1:0], | |
1922 | l2_err4_in[1:0],l2_err5_in[1:0],l2_err6_in[1:0],l2_err7_in[1:0]}), | |
1923 | .dout ({l2_err0[1:0], l2_err1[1:0], l2_err2[1:0], l2_err3[1:0], | |
1924 | l2_err4[1:0], l2_err5[1:0], l2_err6[1:0], l2_err7[1:0]}), | |
1925 | .l1clk(l1clk), | |
1926 | .siclk(siclk), | |
1927 | .soclk(soclk) | |
1928 | ); | |
1929 | ||
1930 | assign report_and_clear_error = cic_rtn_cmplt & ~block_load_annul; | |
1931 | ||
1932 | assign dcl2c_err = report_and_clear_error & (~l2_err_new[1] & l2_err_new[0]); | |
1933 | assign dcl2u_err = report_and_clear_error & ( l2_err_new[1] & ~l2_err_new[0]); | |
1934 | assign dcl2nd_err = report_and_clear_error & ( l2_err_new[1] & l2_err_new[0]); | |
1935 | ||
1936 | lsu_lmc_ctlmsff_ctl_macro__width_3 dff_l2err ( | |
1937 | .scan_in(dff_l2err_scanin), | |
1938 | .scan_out(dff_l2err_scanout), | |
1939 | .din ({dcl2c_err, dcl2u_err, dcl2nd_err}), | |
1940 | .dout ({lsu_dcl2c_err_g,lsu_dcl2u_err_g,lsu_dcl2nd_err_g}), | |
1941 | .l1clk(l1clk), | |
1942 | .siclk(siclk), | |
1943 | .soclk(soclk) | |
1944 | ); | |
1945 | ||
1946 | //////////////////////////////////////////////////////////////////////////////// | |
1947 | // STB RAW errors | |
1948 | //////////////////////////////////////////////////////////////////////////////// | |
1949 | assign sbdlc_err = ld_raw_bypass_w3 & stb_cecc_err & ~stb_uecc_err & ceter_pscce_w3 & cerer_sbdlc; | |
1950 | assign sbdlu_err = ld_raw_bypass_w3 & stb_uecc_err & ceter_pscce_w3 & cerer_sbdlu; | |
1951 | assign stberr_tid[2:0] = ld_raw_bypass_w3 ? tid_w3[2:0] : sbc_st_sel_tid_p4[2:0]; | |
1952 | ||
1953 | lsu_lmc_ctlmsff_ctl_macro__width_5 dff_stberr ( | |
1954 | .scan_in(dff_stberr_scanin), | |
1955 | .scan_out(dff_stberr_scanout), | |
1956 | .din ({sbdlc_err, sbdlu_err, stberr_tid[2:0]}), | |
1957 | .dout ({lsu_sbdlc_err_g,lsu_sbdlu_err_g,lsu_stberr_tid_g[2:0]}), | |
1958 | .l1clk(l1clk), | |
1959 | .siclk(siclk), | |
1960 | .soclk(soclk) | |
1961 | ); | |
1962 | ||
1963 | //////////////////////////////////////////////////////////////////////////////// | |
1964 | // xinval control | |
1965 | // Because the IFU does not queue incoming packets, there is the possibility | |
1966 | // that they process an ifill which requires D$ invalidation much earlier than | |
1967 | // the LSU. This causes a problem because the fill will occur and the thread | |
1968 | // could miss again before the D$ inval occurs. I will signal when an inval | |
1969 | // is pending. During this time, the I$ will not service a miss from that thread. | |
1970 | //////////////////////////////////////////////////////////////////////////////// | |
1971 | ||
1972 | assign xinval_pend_in[0] = cic_xinval[0] | (xinval_pend[0] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b000)); | |
1973 | assign xinval_pend_in[1] = cic_xinval[1] | (xinval_pend[1] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b001)); | |
1974 | assign xinval_pend_in[2] = cic_xinval[2] | (xinval_pend[2] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b010)); | |
1975 | assign xinval_pend_in[3] = cic_xinval[3] | (xinval_pend[3] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b011)); | |
1976 | assign xinval_pend_in[4] = cic_xinval[4] | (xinval_pend[4] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b100)); | |
1977 | assign xinval_pend_in[5] = cic_xinval[5] | (xinval_pend[5] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b101)); | |
1978 | assign xinval_pend_in[6] = cic_xinval[6] | (xinval_pend[6] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b110)); | |
1979 | assign xinval_pend_in[7] = cic_xinval[7] | (xinval_pend[7] & ~(cpq_xinval_m & lmc_cpq_tid_m[2:0] == 3'b111)); | |
1980 | ||
1981 | lsu_lmc_ctlmsff_ctl_macro__width_9 dff_xinval_pend ( | |
1982 | .scan_in(dff_xinval_pend_scanin), | |
1983 | .scan_out(dff_xinval_pend_scanout), | |
1984 | .din ({xinval_pend_in[7:0],cic_xinval_e}), | |
1985 | .dout ({xinval_pend[7:0], cpq_xinval_m}), | |
1986 | .l1clk(l1clk), | |
1987 | .siclk(siclk), | |
1988 | .soclk(soclk) | |
1989 | ); | |
1990 | ||
1991 | assign lsu_ifu_no_miss[7:0] = xinval_pend[7:0]; | |
1992 | ||
1993 | //////////////////////////////////////////////////////////////////////////////// | |
1994 | // Power management. | |
1995 | // lmc has 2 clock domains. | |
1996 | // 1. Free running (l1clk) | |
1997 | // 2. Any load request pending (l1clk_pm1) | |
1998 | // A third possible domain which represends any load miss outstanding could | |
1999 | // gate ~50 flops but would require adding 8 flops and logic. Not worth it. | |
2000 | //////////////////////////////////////////////////////////////////////////////// | |
2001 | ||
2002 | assign rqpend_clken = ~lsu_lsu_pmen | ld_inst_vld_b | ld_inst_nopref_w | pref_inst_w | | |
2003 | (|(ld_pcx_vld[7:0])) | (|(ld_asi_vld[7:0])) | (|(ld_all_sel_p4[7:0])); | |
2004 | ||
2005 | ||
2006 | //////////////////////////////////////////////////////////////////////////////// | |
2007 | // BIST/DIAG | |
2008 | //////////////////////////////////////////////////////////////////////////////// | |
2009 | ||
2010 | lsu_lmc_ctlmsff_ctl_macro__width_2 dff_bist_diag ( | |
2011 | .scan_in(dff_bist_diag_scanin), | |
2012 | .scan_out(dff_bist_diag_scanout), | |
2013 | .din ({mbi_run, bist_or_diag_d}), | |
2014 | .dout ({lmc_mbi_run,lmc_bist_or_diag_e}), | |
2015 | .l1clk(l1clk), | |
2016 | .siclk(siclk), | |
2017 | .soclk(soclk) | |
2018 | ); | |
2019 | ||
2020 | assign bist_or_diag_d = lmc_mbi_run | dcc_cache_diag_wr_b; | |
2021 | ||
2022 | lsu_lmc_ctlmsff_ctl_macro__scanreverse_1__width_6 dff_spares ( | |
2023 | .scan_in(spares_scanin), | |
2024 | .scan_out(spares_scanout), | |
2025 | .din ({ld_inst_vld_b,5'b0 }), | |
2026 | .dout ({ld_inst_vld_w,unused[4:0]}), | |
2027 | .l1clk(l1clk), | |
2028 | .siclk(siclk), | |
2029 | .soclk(soclk) | |
2030 | ); | |
2031 | ||
2032 | //spare_ctl_macro spares (num=6) ( | |
2033 | // .scan_in(spares_scanin), | |
2034 | // .scan_out(spares_scanout), | |
2035 | // .l1clk (l1clk) | |
2036 | //); | |
2037 | ||
2038 | supply0 vss; | |
2039 | supply1 vdd; | |
2040 | // fixscan start: | |
2041 | assign dff_ceter_scanin = scan_in ; | |
2042 | assign dff_cerer_scanin = dff_ceter_scanout ; | |
2043 | assign dff_thread_w_scanin = dff_cerer_scanout ; | |
2044 | assign dff_flush_b_scanin = dff_thread_w_scanout ; | |
2045 | assign dff_flush_w_scanin = dff_flush_b_scanout ; | |
2046 | assign dff_inst_b_scanin = dff_flush_w_scanout ; | |
2047 | assign dff_inst_w_scanin = dff_inst_b_scanout ; | |
2048 | assign dff_l2fill_scanin = dff_inst_w_scanout ; | |
2049 | assign dff_unfilled_scanin = dff_l2fill_scanout ; | |
2050 | assign dff_stb_raw_scanin = dff_unfilled_scanout ; | |
2051 | assign dff_rawp_disable_scanin = dff_stb_raw_scanout ; | |
2052 | assign dff_ldd_vld_scanin = dff_rawp_disable_scanout ; | |
2053 | assign dff_ld_lmq_en_b_scanin = dff_ldd_vld_scanout ; | |
2054 | assign dff_ld_pcx_vld_scanin = dff_ld_lmq_en_b_scanout ; | |
2055 | assign dff_ld_asi_vld_scanin = dff_ld_pcx_vld_scanout ; | |
2056 | assign lru8_scanin = dff_ld_asi_vld_scanout ; | |
2057 | assign dff_ld_sel_scanin = lru8_scanout ; | |
2058 | assign dff_ldd_out_scanin = dff_ld_sel_scanout ; | |
2059 | assign dff_st_atom_p4_scanin = dff_ldd_out_scanout ; | |
2060 | assign dff_st_atom_p5_scanin = dff_st_atom_p4_scanout ; | |
2061 | assign dff_asi_indet_scanin = dff_st_atom_p5_scanout ; | |
2062 | assign dff_cpq_tid_scanin = dff_asi_indet_scanout ; | |
2063 | assign dff_ld_raw_w_scanin = dff_cpq_tid_scanout ; | |
2064 | assign dff_ld_raw_w2_scanin = dff_ld_raw_w_scanout ; | |
2065 | assign dff_ld_raw_w3_scanin = dff_ld_raw_w2_scanout ; | |
2066 | assign dff_ldbyp_vld_scanin = dff_ld_raw_w3_scanout ; | |
2067 | assign dff_ld_inst_e_scanin = dff_ldbyp_vld_scanout ; | |
2068 | assign dff_byp_cnt_scanin = dff_ld_inst_e_scanout ; | |
2069 | assign dff_thrd_byp_sel_m_scanin = dff_byp_cnt_scanout ; | |
2070 | assign dff_bld_pending_scanin = dff_thrd_byp_sel_m_scanout; | |
2071 | assign dff_bld_addr_scanin = dff_bld_pending_scanout ; | |
2072 | assign dff_bld_cnt0_scanin = dff_bld_addr_scanout ; | |
2073 | assign dff_bld_cnt1_scanin = dff_bld_cnt0_scanout ; | |
2074 | assign dff_bld_cnt2_scanin = dff_bld_cnt1_scanout ; | |
2075 | assign dff_bld_cnt3_scanin = dff_bld_cnt2_scanout ; | |
2076 | assign dff_bld_cnt4_scanin = dff_bld_cnt3_scanout ; | |
2077 | assign dff_bld_cnt5_scanin = dff_bld_cnt4_scanout ; | |
2078 | assign dff_bld_cnt6_scanin = dff_bld_cnt5_scanout ; | |
2079 | assign dff_bld_cnt7_scanin = dff_bld_cnt6_scanout ; | |
2080 | assign dff_bld_bypass_scanin = dff_bld_cnt7_scanout ; | |
2081 | assign dff_bld_miss_scanin = dff_bld_bypass_scanout ; | |
2082 | assign dff_pref_issued_scanin = dff_bld_miss_scanout ; | |
2083 | assign dff_perr_scanin = dff_pref_issued_scanout ; | |
2084 | assign dff_dcerr_scanin = dff_perr_scanout ; | |
2085 | assign dff_l2errcode_scanin = dff_dcerr_scanout ; | |
2086 | assign dff_l2err_scanin = dff_l2errcode_scanout ; | |
2087 | assign dff_stberr_scanin = dff_l2err_scanout ; | |
2088 | assign dff_xinval_pend_scanin = dff_stberr_scanout ; | |
2089 | assign dff_bist_diag_scanin = dff_xinval_pend_scanout ; | |
2090 | assign spares_scanin = dff_bist_diag_scanout ; | |
2091 | assign scan_out = spares_scanout ; | |
2092 | // fixscan end: | |
2093 | endmodule | |
2094 | ||
2095 | ||
2096 | ||
2097 | ||
2098 | ||
2099 | ||
2100 | // any PARAMS parms go into naming of macro | |
2101 | ||
2102 | module lsu_lmc_ctll1clkhdr_ctl_macro ( | |
2103 | l2clk, | |
2104 | l1en, | |
2105 | pce_ov, | |
2106 | stop, | |
2107 | se, | |
2108 | l1clk); | |
2109 | ||
2110 | ||
2111 | input l2clk; | |
2112 | input l1en; | |
2113 | input pce_ov; | |
2114 | input stop; | |
2115 | input se; | |
2116 | output l1clk; | |
2117 | ||
2118 | ||
2119 | ||
2120 | ||
2121 | ||
2122 | cl_sc1_l1hdr_8x c_0 ( | |
2123 | ||
2124 | ||
2125 | .l2clk(l2clk), | |
2126 | .pce(l1en), | |
2127 | .l1clk(l1clk), | |
2128 | .se(se), | |
2129 | .pce_ov(pce_ov), | |
2130 | .stop(stop) | |
2131 | ); | |
2132 | ||
2133 | ||
2134 | ||
2135 | endmodule | |
2136 | ||
2137 | ||
2138 | ||
2139 | ||
2140 | ||
2141 | ||
2142 | ||
2143 | ||
2144 | ||
2145 | ||
2146 | ||
2147 | ||
2148 | ||
2149 | // any PARAMS parms go into naming of macro | |
2150 | ||
2151 | module lsu_lmc_ctlmsff_ctl_macro__width_9 ( | |
2152 | din, | |
2153 | l1clk, | |
2154 | scan_in, | |
2155 | siclk, | |
2156 | soclk, | |
2157 | dout, | |
2158 | scan_out); | |
2159 | wire [8:0] fdin; | |
2160 | wire [7:0] so; | |
2161 | ||
2162 | input [8:0] din; | |
2163 | input l1clk; | |
2164 | input scan_in; | |
2165 | ||
2166 | ||
2167 | input siclk; | |
2168 | input soclk; | |
2169 | ||
2170 | output [8:0] dout; | |
2171 | output scan_out; | |
2172 | assign fdin[8:0] = din[8:0]; | |
2173 | ||
2174 | ||
2175 | ||
2176 | ||
2177 | ||
2178 | ||
2179 | dff #(9) d0_0 ( | |
2180 | .l1clk(l1clk), | |
2181 | .siclk(siclk), | |
2182 | .soclk(soclk), | |
2183 | .d(fdin[8:0]), | |
2184 | .si({scan_in,so[7:0]}), | |
2185 | .so({so[7:0],scan_out}), | |
2186 | .q(dout[8:0]) | |
2187 | ); | |
2188 | ||
2189 | ||
2190 | ||
2191 | ||
2192 | ||
2193 | ||
2194 | ||
2195 | ||
2196 | ||
2197 | ||
2198 | ||
2199 | ||
2200 | endmodule | |
2201 | ||
2202 | ||
2203 | ||
2204 | ||
2205 | ||
2206 | ||
2207 | ||
2208 | ||
2209 | ||
2210 | ||
2211 | ||
2212 | ||
2213 | ||
2214 | // any PARAMS parms go into naming of macro | |
2215 | ||
2216 | module lsu_lmc_ctlmsff_ctl_macro__width_7 ( | |
2217 | din, | |
2218 | l1clk, | |
2219 | scan_in, | |
2220 | siclk, | |
2221 | soclk, | |
2222 | dout, | |
2223 | scan_out); | |
2224 | wire [6:0] fdin; | |
2225 | wire [5:0] so; | |
2226 | ||
2227 | input [6:0] din; | |
2228 | input l1clk; | |
2229 | input scan_in; | |
2230 | ||
2231 | ||
2232 | input siclk; | |
2233 | input soclk; | |
2234 | ||
2235 | output [6:0] dout; | |
2236 | output scan_out; | |
2237 | assign fdin[6:0] = din[6:0]; | |
2238 | ||
2239 | ||
2240 | ||
2241 | ||
2242 | ||
2243 | ||
2244 | dff #(7) d0_0 ( | |
2245 | .l1clk(l1clk), | |
2246 | .siclk(siclk), | |
2247 | .soclk(soclk), | |
2248 | .d(fdin[6:0]), | |
2249 | .si({scan_in,so[5:0]}), | |
2250 | .so({so[5:0],scan_out}), | |
2251 | .q(dout[6:0]) | |
2252 | ); | |
2253 | ||
2254 | ||
2255 | ||
2256 | ||
2257 | ||
2258 | ||
2259 | ||
2260 | ||
2261 | ||
2262 | ||
2263 | ||
2264 | ||
2265 | endmodule | |
2266 | ||
2267 | ||
2268 | ||
2269 | ||
2270 | ||
2271 | ||
2272 | ||
2273 | ||
2274 | ||
2275 | ||
2276 | ||
2277 | ||
2278 | ||
2279 | // any PARAMS parms go into naming of macro | |
2280 | ||
2281 | module lsu_lmc_ctlmsff_ctl_macro__width_8 ( | |
2282 | din, | |
2283 | l1clk, | |
2284 | scan_in, | |
2285 | siclk, | |
2286 | soclk, | |
2287 | dout, | |
2288 | scan_out); | |
2289 | wire [7:0] fdin; | |
2290 | wire [6:0] so; | |
2291 | ||
2292 | input [7:0] din; | |
2293 | input l1clk; | |
2294 | input scan_in; | |
2295 | ||
2296 | ||
2297 | input siclk; | |
2298 | input soclk; | |
2299 | ||
2300 | output [7:0] dout; | |
2301 | output scan_out; | |
2302 | assign fdin[7:0] = din[7:0]; | |
2303 | ||
2304 | ||
2305 | ||
2306 | ||
2307 | ||
2308 | ||
2309 | dff #(8) d0_0 ( | |
2310 | .l1clk(l1clk), | |
2311 | .siclk(siclk), | |
2312 | .soclk(soclk), | |
2313 | .d(fdin[7:0]), | |
2314 | .si({scan_in,so[6:0]}), | |
2315 | .so({so[6:0],scan_out}), | |
2316 | .q(dout[7:0]) | |
2317 | ); | |
2318 | ||
2319 | ||
2320 | ||
2321 | ||
2322 | ||
2323 | ||
2324 | ||
2325 | ||
2326 | ||
2327 | ||
2328 | ||
2329 | ||
2330 | endmodule | |
2331 | ||
2332 | ||
2333 | ||
2334 | ||
2335 | ||
2336 | ||
2337 | ||
2338 | ||
2339 | ||
2340 | ||
2341 | ||
2342 | ||
2343 | ||
2344 | // any PARAMS parms go into naming of macro | |
2345 | ||
2346 | module lsu_lmc_ctlmsff_ctl_macro__width_1 ( | |
2347 | din, | |
2348 | l1clk, | |
2349 | scan_in, | |
2350 | siclk, | |
2351 | soclk, | |
2352 | dout, | |
2353 | scan_out); | |
2354 | wire [0:0] fdin; | |
2355 | ||
2356 | input [0:0] din; | |
2357 | input l1clk; | |
2358 | input scan_in; | |
2359 | ||
2360 | ||
2361 | input siclk; | |
2362 | input soclk; | |
2363 | ||
2364 | output [0:0] dout; | |
2365 | output scan_out; | |
2366 | assign fdin[0:0] = din[0:0]; | |
2367 | ||
2368 | ||
2369 | ||
2370 | ||
2371 | ||
2372 | ||
2373 | dff #(1) d0_0 ( | |
2374 | .l1clk(l1clk), | |
2375 | .siclk(siclk), | |
2376 | .soclk(soclk), | |
2377 | .d(fdin[0:0]), | |
2378 | .si(scan_in), | |
2379 | .so(scan_out), | |
2380 | .q(dout[0:0]) | |
2381 | ); | |
2382 | ||
2383 | ||
2384 | ||
2385 | ||
2386 | ||
2387 | ||
2388 | ||
2389 | ||
2390 | ||
2391 | ||
2392 | ||
2393 | ||
2394 | endmodule | |
2395 | ||
2396 | ||
2397 | ||
2398 | ||
2399 | ||
2400 | ||
2401 | ||
2402 | ||
2403 | ||
2404 | ||
2405 | ||
2406 | ||
2407 | ||
2408 | // any PARAMS parms go into naming of macro | |
2409 | ||
2410 | module lsu_lmc_ctlmsff_ctl_macro__width_2 ( | |
2411 | din, | |
2412 | l1clk, | |
2413 | scan_in, | |
2414 | siclk, | |
2415 | soclk, | |
2416 | dout, | |
2417 | scan_out); | |
2418 | wire [1:0] fdin; | |
2419 | wire [0:0] so; | |
2420 | ||
2421 | input [1:0] din; | |
2422 | input l1clk; | |
2423 | input scan_in; | |
2424 | ||
2425 | ||
2426 | input siclk; | |
2427 | input soclk; | |
2428 | ||
2429 | output [1:0] dout; | |
2430 | output scan_out; | |
2431 | assign fdin[1:0] = din[1:0]; | |
2432 | ||
2433 | ||
2434 | ||
2435 | ||
2436 | ||
2437 | ||
2438 | dff #(2) d0_0 ( | |
2439 | .l1clk(l1clk), | |
2440 | .siclk(siclk), | |
2441 | .soclk(soclk), | |
2442 | .d(fdin[1:0]), | |
2443 | .si({scan_in,so[0:0]}), | |
2444 | .so({so[0:0],scan_out}), | |
2445 | .q(dout[1:0]) | |
2446 | ); | |
2447 | ||
2448 | ||
2449 | ||
2450 | ||
2451 | ||
2452 | ||
2453 | ||
2454 | ||
2455 | ||
2456 | ||
2457 | ||
2458 | ||
2459 | endmodule | |
2460 | ||
2461 | ||
2462 | ||
2463 | ||
2464 | ||
2465 | ||
2466 | ||
2467 | ||
2468 | ||
2469 | ||
2470 | ||
2471 | ||
2472 | ||
2473 | // any PARAMS parms go into naming of macro | |
2474 | ||
2475 | module lsu_lmc_ctlmsff_ctl_macro__width_6 ( | |
2476 | din, | |
2477 | l1clk, | |
2478 | scan_in, | |
2479 | siclk, | |
2480 | soclk, | |
2481 | dout, | |
2482 | scan_out); | |
2483 | wire [5:0] fdin; | |
2484 | wire [4:0] so; | |
2485 | ||
2486 | input [5:0] din; | |
2487 | input l1clk; | |
2488 | input scan_in; | |
2489 | ||
2490 | ||
2491 | input siclk; | |
2492 | input soclk; | |
2493 | ||
2494 | output [5:0] dout; | |
2495 | output scan_out; | |
2496 | assign fdin[5:0] = din[5:0]; | |
2497 | ||
2498 | ||
2499 | ||
2500 | ||
2501 | ||
2502 | ||
2503 | dff #(6) d0_0 ( | |
2504 | .l1clk(l1clk), | |
2505 | .siclk(siclk), | |
2506 | .soclk(soclk), | |
2507 | .d(fdin[5:0]), | |
2508 | .si({scan_in,so[4:0]}), | |
2509 | .so({so[4:0],scan_out}), | |
2510 | .q(dout[5:0]) | |
2511 | ); | |
2512 | ||
2513 | ||
2514 | ||
2515 | ||
2516 | ||
2517 | ||
2518 | ||
2519 | ||
2520 | ||
2521 | ||
2522 | ||
2523 | ||
2524 | endmodule | |
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | ||
2530 | ||
2531 | ||
2532 | ||
2533 | ||
2534 | ||
2535 | ||
2536 | ||
2537 | ||
2538 | // any PARAMS parms go into naming of macro | |
2539 | ||
2540 | module lsu_lmc_ctlmsff_ctl_macro__width_5 ( | |
2541 | din, | |
2542 | l1clk, | |
2543 | scan_in, | |
2544 | siclk, | |
2545 | soclk, | |
2546 | dout, | |
2547 | scan_out); | |
2548 | wire [4:0] fdin; | |
2549 | wire [3:0] so; | |
2550 | ||
2551 | input [4:0] din; | |
2552 | input l1clk; | |
2553 | input scan_in; | |
2554 | ||
2555 | ||
2556 | input siclk; | |
2557 | input soclk; | |
2558 | ||
2559 | output [4:0] dout; | |
2560 | output scan_out; | |
2561 | assign fdin[4:0] = din[4:0]; | |
2562 | ||
2563 | ||
2564 | ||
2565 | ||
2566 | ||
2567 | ||
2568 | dff #(5) d0_0 ( | |
2569 | .l1clk(l1clk), | |
2570 | .siclk(siclk), | |
2571 | .soclk(soclk), | |
2572 | .d(fdin[4:0]), | |
2573 | .si({scan_in,so[3:0]}), | |
2574 | .so({so[3:0],scan_out}), | |
2575 | .q(dout[4:0]) | |
2576 | ); | |
2577 | ||
2578 | ||
2579 | ||
2580 | ||
2581 | ||
2582 | ||
2583 | ||
2584 | ||
2585 | ||
2586 | ||
2587 | ||
2588 | ||
2589 | endmodule | |
2590 | ||
2591 | ||
2592 | ||
2593 | ||
2594 | ||
2595 | ||
2596 | ||
2597 | ||
2598 | ||
2599 | ||
2600 | ||
2601 | ||
2602 | ||
2603 | // any PARAMS parms go into naming of macro | |
2604 | ||
2605 | module lsu_lmc_ctlmsff_ctl_macro__width_3 ( | |
2606 | din, | |
2607 | l1clk, | |
2608 | scan_in, | |
2609 | siclk, | |
2610 | soclk, | |
2611 | dout, | |
2612 | scan_out); | |
2613 | wire [2:0] fdin; | |
2614 | wire [1:0] so; | |
2615 | ||
2616 | input [2:0] din; | |
2617 | input l1clk; | |
2618 | input scan_in; | |
2619 | ||
2620 | ||
2621 | input siclk; | |
2622 | input soclk; | |
2623 | ||
2624 | output [2:0] dout; | |
2625 | output scan_out; | |
2626 | assign fdin[2:0] = din[2:0]; | |
2627 | ||
2628 | ||
2629 | ||
2630 | ||
2631 | ||
2632 | ||
2633 | dff #(3) d0_0 ( | |
2634 | .l1clk(l1clk), | |
2635 | .siclk(siclk), | |
2636 | .soclk(soclk), | |
2637 | .d(fdin[2:0]), | |
2638 | .si({scan_in,so[1:0]}), | |
2639 | .so({so[1:0],scan_out}), | |
2640 | .q(dout[2:0]) | |
2641 | ); | |
2642 | ||
2643 | ||
2644 | ||
2645 | ||
2646 | ||
2647 | ||
2648 | ||
2649 | ||
2650 | ||
2651 | ||
2652 | ||
2653 | ||
2654 | endmodule | |
2655 | ||
2656 | ||
2657 | ||
2658 | ||
2659 | ||
2660 | ||
2661 | // any PARAMS parms go into naming of macro | |
2662 | ||
2663 | module lsu_lmc_ctlmsff_ctl_macro__width_10 ( | |
2664 | din, | |
2665 | l1clk, | |
2666 | scan_in, | |
2667 | siclk, | |
2668 | soclk, | |
2669 | dout, | |
2670 | scan_out); | |
2671 | wire [9:0] fdin; | |
2672 | wire [8:0] so; | |
2673 | ||
2674 | input [9:0] din; | |
2675 | input l1clk; | |
2676 | input scan_in; | |
2677 | ||
2678 | ||
2679 | input siclk; | |
2680 | input soclk; | |
2681 | ||
2682 | output [9:0] dout; | |
2683 | output scan_out; | |
2684 | assign fdin[9:0] = din[9:0]; | |
2685 | ||
2686 | ||
2687 | ||
2688 | ||
2689 | ||
2690 | ||
2691 | dff #(10) d0_0 ( | |
2692 | .l1clk(l1clk), | |
2693 | .siclk(siclk), | |
2694 | .soclk(soclk), | |
2695 | .d(fdin[9:0]), | |
2696 | .si({scan_in,so[8:0]}), | |
2697 | .so({so[8:0],scan_out}), | |
2698 | .q(dout[9:0]) | |
2699 | ); | |
2700 | ||
2701 | ||
2702 | ||
2703 | ||
2704 | ||
2705 | ||
2706 | ||
2707 | ||
2708 | ||
2709 | ||
2710 | ||
2711 | ||
2712 | endmodule | |
2713 | ||
2714 | ||
2715 | ||
2716 | ||
2717 | ||
2718 | ||
2719 | ||
2720 | ||
2721 | ||
2722 | ||
2723 | ||
2724 | ||
2725 | ||
2726 | // any PARAMS parms go into naming of macro | |
2727 | ||
2728 | module lsu_lmc_ctlmsff_ctl_macro__width_4 ( | |
2729 | din, | |
2730 | l1clk, | |
2731 | scan_in, | |
2732 | siclk, | |
2733 | soclk, | |
2734 | dout, | |
2735 | scan_out); | |
2736 | wire [3:0] fdin; | |
2737 | wire [2:0] so; | |
2738 | ||
2739 | input [3:0] din; | |
2740 | input l1clk; | |
2741 | input scan_in; | |
2742 | ||
2743 | ||
2744 | input siclk; | |
2745 | input soclk; | |
2746 | ||
2747 | output [3:0] dout; | |
2748 | output scan_out; | |
2749 | assign fdin[3:0] = din[3:0]; | |
2750 | ||
2751 | ||
2752 | ||
2753 | ||
2754 | ||
2755 | ||
2756 | dff #(4) d0_0 ( | |
2757 | .l1clk(l1clk), | |
2758 | .siclk(siclk), | |
2759 | .soclk(soclk), | |
2760 | .d(fdin[3:0]), | |
2761 | .si({scan_in,so[2:0]}), | |
2762 | .so({so[2:0],scan_out}), | |
2763 | .q(dout[3:0]) | |
2764 | ); | |
2765 | ||
2766 | ||
2767 | ||
2768 | ||
2769 | ||
2770 | ||
2771 | ||
2772 | ||
2773 | ||
2774 | ||
2775 | ||
2776 | ||
2777 | endmodule | |
2778 | ||
2779 | ||
2780 | ||
2781 | ||
2782 | ||
2783 | ||
2784 | ||
2785 | ||
2786 | ||
2787 | ||
2788 | ||
2789 | ||
2790 | ||
2791 | // any PARAMS parms go into naming of macro | |
2792 | ||
2793 | module lsu_lmc_ctlmsff_ctl_macro__width_16 ( | |
2794 | din, | |
2795 | l1clk, | |
2796 | scan_in, | |
2797 | siclk, | |
2798 | soclk, | |
2799 | dout, | |
2800 | scan_out); | |
2801 | wire [15:0] fdin; | |
2802 | wire [14:0] so; | |
2803 | ||
2804 | input [15:0] din; | |
2805 | input l1clk; | |
2806 | input scan_in; | |
2807 | ||
2808 | ||
2809 | input siclk; | |
2810 | input soclk; | |
2811 | ||
2812 | output [15:0] dout; | |
2813 | output scan_out; | |
2814 | assign fdin[15:0] = din[15:0]; | |
2815 | ||
2816 | ||
2817 | ||
2818 | ||
2819 | ||
2820 | ||
2821 | dff #(16) d0_0 ( | |
2822 | .l1clk(l1clk), | |
2823 | .siclk(siclk), | |
2824 | .soclk(soclk), | |
2825 | .d(fdin[15:0]), | |
2826 | .si({scan_in,so[14:0]}), | |
2827 | .so({so[14:0],scan_out}), | |
2828 | .q(dout[15:0]) | |
2829 | ); | |
2830 | ||
2831 | ||
2832 | ||
2833 | ||
2834 | ||
2835 | ||
2836 | ||
2837 | ||
2838 | ||
2839 | ||
2840 | ||
2841 | ||
2842 | endmodule | |
2843 | ||
2844 | ||
2845 | ||
2846 | ||
2847 | ||
2848 | ||
2849 | ||
2850 | ||
2851 | ||
2852 | ||
2853 | ||
2854 | ||
2855 | ||
2856 | // any PARAMS parms go into naming of macro | |
2857 | ||
2858 | module lsu_lmc_ctlmsff_ctl_macro__scanreverse_1__width_6 ( | |
2859 | din, | |
2860 | l1clk, | |
2861 | scan_in, | |
2862 | siclk, | |
2863 | soclk, | |
2864 | dout, | |
2865 | scan_out); | |
2866 | wire [5:0] fdin; | |
2867 | wire [0:4] so; | |
2868 | ||
2869 | input [5:0] din; | |
2870 | input l1clk; | |
2871 | input scan_in; | |
2872 | ||
2873 | ||
2874 | input siclk; | |
2875 | input soclk; | |
2876 | ||
2877 | output [5:0] dout; | |
2878 | output scan_out; | |
2879 | assign fdin[5:0] = din[5:0]; | |
2880 | ||
2881 | ||
2882 | ||
2883 | ||
2884 | ||
2885 | ||
2886 | dff #(6) d0_0 ( | |
2887 | .l1clk(l1clk), | |
2888 | .siclk(siclk), | |
2889 | .soclk(soclk), | |
2890 | .d(fdin[5:0]), | |
2891 | .si({so[0:4],scan_in}), | |
2892 | .so({scan_out,so[0:4]}), | |
2893 | .q(dout[5:0]) | |
2894 | ); | |
2895 | ||
2896 | ||
2897 | ||
2898 | ||
2899 | ||
2900 | ||
2901 | ||
2902 | ||
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | endmodule | |
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 |