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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_sbs_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_sbs_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | scan_out, | |
43 | sbc_cam_wvld_m, | |
44 | sbc_st_sel_p3, | |
45 | sbc_bst_sel, | |
46 | sbc_rmo_st_b, | |
47 | sbc_st_addr_new, | |
48 | sbc_bst_b, | |
49 | sbc_bst_in_prog_b, | |
50 | sbc_fgu_ecc_b, | |
51 | sbc_bst_rd_err, | |
52 | sbc_sbs_kill_store_p4_, | |
53 | sbc_tte_vld_b, | |
54 | sbc_blk_inst_b, | |
55 | dec_flush_lm, | |
56 | dec_flush_lb, | |
57 | tlu_flush_lsu_b, | |
58 | spd_st_line_match, | |
59 | dcc_asi_store_b, | |
60 | dcc_asi_iomap_b, | |
61 | dcc_asi_rngf_b, | |
62 | dcc_asi_indet_b, | |
63 | dcc_sync_inst_w, | |
64 | dcc_casa_inst_b, | |
65 | dcc_pst_asi_b, | |
66 | dcc_st_rq_type_w, | |
67 | dcc_exception_flush_b, | |
68 | tlb_tte_ie_b, | |
69 | cic_st_ack, | |
70 | cic_st_dequeue, | |
71 | cic_rmo_dequeue, | |
72 | pic_st_sel_p3, | |
73 | dcc_asi_rtn_vld, | |
74 | dcc_asi_rtn_excp, | |
75 | dcc_asi_rtn_rd, | |
76 | lsu_lsu_pmen_, | |
77 | sbs_stb_wptr_m, | |
78 | sbs_stb_rptr, | |
79 | sbs_pcx_rq_vld, | |
80 | sbs_atm_rq_vld, | |
81 | sbs_asi_rq_vld, | |
82 | sbs_state_vld, | |
83 | sbs_state_ced, | |
84 | sbs_state_asi_rngf, | |
85 | sbs_pcx_pst_ie_p4, | |
86 | sbs_all_commited, | |
87 | sbs_stb_empty, | |
88 | sbs_stb_full, | |
89 | sbs_bst_req, | |
90 | sbs_sync, | |
91 | sbs_asi_indet_req, | |
92 | sbs_asi_indet_retire, | |
93 | sbs_rmo_st_p4, | |
94 | sbs_blk_st_p4, | |
95 | sbs_st_type, | |
96 | lsu_stb_alloc, | |
97 | lsu_stb_dealloc, | |
98 | lsu_block_store_kill, | |
99 | lsu_stb_empty); | |
100 | wire se; | |
101 | wire pce_ov; | |
102 | wire stop; | |
103 | wire siclk; | |
104 | wire soclk; | |
105 | wire sbs_clken; | |
106 | wire stb_cam_wvld_b; | |
107 | wire stb_alloc_w; | |
108 | wire bst_pend; | |
109 | wire l1clk; | |
110 | wire l1clk_pm1; | |
111 | wire dff_flush_b_scanin; | |
112 | wire dff_flush_b_scanout; | |
113 | wire pipe_flush_b; | |
114 | wire flush_b; | |
115 | wire dff_flush_w_scanin; | |
116 | wire dff_flush_w_scanout; | |
117 | wire flush_w; | |
118 | wire dff_cam_wvld_b_scanin; | |
119 | wire dff_cam_wvld_b_scanout; | |
120 | wire kill_store_p4; | |
121 | wire st_commit_p4; | |
122 | wire dff_st_dq_scanin; | |
123 | wire dff_st_dq_scanout; | |
124 | wire block_store_kill; | |
125 | wire st_dequeue_d1; | |
126 | wire kill_store_p5; | |
127 | wire [7:0] dec_rptr_pcx; | |
128 | wire [7:0] dec_stb_rptr; | |
129 | wire [7:0] stb_state_vld; | |
130 | wire [7:0] stb_state_ced; | |
131 | wire [7:0] stb_state_ack; | |
132 | wire [7:0] stb_state_mem; | |
133 | wire [7:0] stb_state_rmo; | |
134 | wire [7:0] stb_state_asi; | |
135 | wire [7:0] dec_dqptr; | |
136 | wire [4:0] rmo_count; | |
137 | wire sbs_rmo_st; | |
138 | wire bst_err; | |
139 | wire [7:0] stb_state_cas; | |
140 | wire [3:0] stb_rptr_inc; | |
141 | wire [3:0] stb_rptr; | |
142 | wire [3:0] stb_rptr_in; | |
143 | wire stb_commit_entry; | |
144 | wire flush_bst_inst; | |
145 | wire bst_kill; | |
146 | wire dff_rptr_scanin; | |
147 | wire dff_rptr_scanout; | |
148 | wire [3:0] stb_wptr_incr; | |
149 | wire [3:0] stb_wptr; | |
150 | wire flush_st_w; | |
151 | wire [3:0] stb_wptr_decr; | |
152 | wire [3:0] stb_wptr_in; | |
153 | wire dff_wptr_scanin; | |
154 | wire dff_wptr_scanout; | |
155 | wire dff_wptr_b_scanin; | |
156 | wire dff_wptr_b_scanout; | |
157 | wire [2:0] stb_wptr_b; | |
158 | wire [7:0] dec_wptr_b; | |
159 | wire dff_wptr_w_scanin; | |
160 | wire dff_wptr_w_scanout; | |
161 | wire [2:0] stb_wptr_w; | |
162 | wire [7:0] dec_wptr_w; | |
163 | wire stb_empty; | |
164 | wire rmo_st_commit_p4; | |
165 | wire sbs_last_entry; | |
166 | wire stb_flush_state; | |
167 | wire [2:0] dqptr_in; | |
168 | wire stb_flush_done; | |
169 | wire [2:0] dqptr; | |
170 | wire dff_dqptr_scanin; | |
171 | wire dff_dqptr_scanout; | |
172 | wire [7:0] stb_state_rst; | |
173 | wire rmo_st_commit_p3; | |
174 | wire set_valid_b; | |
175 | wire [7:0] stb_state_vld_set; | |
176 | wire [7:0] stb_state_vld_din; | |
177 | wire dff_stb_vld_scanin; | |
178 | wire dff_stb_vld_scanout; | |
179 | wire [7:0] stb_state_vld_out; | |
180 | wire set_valid_w; | |
181 | wire [7:0] misc_state_wr; | |
182 | wire stb_alloc_b; | |
183 | wire dff_stb_alloc_w_scanin; | |
184 | wire dff_stb_alloc_w_scanout; | |
185 | wire st_commit_p3; | |
186 | wire dff_st_commit_p4_scanin; | |
187 | wire dff_st_commit_p4_scanout; | |
188 | wire [7:0] stb_state_ced_set; | |
189 | wire [7:0] stb_state_ced_din; | |
190 | wire dff_stb_ced_scanin; | |
191 | wire dff_stb_ced_scanout; | |
192 | wire [2:0] ackptr_in; | |
193 | wire [2:0] ackptr; | |
194 | wire dff_ackptr_scanin; | |
195 | wire dff_ackptr_scanout; | |
196 | wire [7:0] dec_ackptr; | |
197 | wire [7:0] stb_state_ack_set; | |
198 | wire pipe_store_w; | |
199 | wire [7:0] stb_state_ack_rst; | |
200 | wire [7:0] stb_state_ack_din; | |
201 | wire dff_stb_ack_scanin; | |
202 | wire dff_stb_ack_scanout; | |
203 | wire dff_asi_w_scanin; | |
204 | wire dff_asi_w_scanout; | |
205 | wire asi_store_w; | |
206 | wire asi_rngf_w; | |
207 | wire rmo_st_w; | |
208 | wire last_st_asi; | |
209 | wire last_st_asi_d1; | |
210 | wire last_asi_ring; | |
211 | wire last_asi_ring_d1; | |
212 | wire last_st_rmo; | |
213 | wire last_st_rmo_d1; | |
214 | wire dff_asi_pipe_scanin; | |
215 | wire dff_asi_pipe_scanout; | |
216 | wire pipe_store_b; | |
217 | wire [2:0] sbs_state_in; | |
218 | wire [2:0] stb_state_0_din; | |
219 | wire [2:0] sbs_state_0; | |
220 | wire [2:0] stb_state_1_din; | |
221 | wire [2:0] sbs_state_1; | |
222 | wire [2:0] stb_state_2_din; | |
223 | wire [2:0] sbs_state_2; | |
224 | wire [2:0] stb_state_3_din; | |
225 | wire [2:0] sbs_state_3; | |
226 | wire [2:0] stb_state_4_din; | |
227 | wire [2:0] sbs_state_4; | |
228 | wire [2:0] stb_state_5_din; | |
229 | wire [2:0] sbs_state_5; | |
230 | wire [2:0] stb_state_6_din; | |
231 | wire [2:0] sbs_state_6; | |
232 | wire [2:0] stb_state_7_din; | |
233 | wire [2:0] sbs_state_7; | |
234 | wire dff_state_0_scanin; | |
235 | wire dff_state_0_scanout; | |
236 | wire dff_state_1_scanin; | |
237 | wire dff_state_1_scanout; | |
238 | wire dff_state_2_scanin; | |
239 | wire dff_state_2_scanout; | |
240 | wire dff_state_3_scanin; | |
241 | wire dff_state_3_scanout; | |
242 | wire dff_state_4_scanin; | |
243 | wire dff_state_4_scanout; | |
244 | wire dff_state_5_scanin; | |
245 | wire dff_state_5_scanout; | |
246 | wire dff_state_6_scanin; | |
247 | wire dff_state_6_scanout; | |
248 | wire dff_state_7_scanin; | |
249 | wire dff_state_7_scanout; | |
250 | wire sbs_blk_st; | |
251 | wire [7:0] stb_state_indet; | |
252 | wire asi_error; | |
253 | wire sync_state; | |
254 | wire sync_state_out; | |
255 | wire sync_state_rst; | |
256 | wire sync_state_in; | |
257 | wire dff_sync_state_scanin; | |
258 | wire dff_sync_state_scanout; | |
259 | wire trap_sync; | |
260 | wire dff_sbs_sync_scanin; | |
261 | wire dff_sbs_sync_scanout; | |
262 | wire bst_pend_in; | |
263 | wire bst_w; | |
264 | wire dff_bst_pend_scanin; | |
265 | wire dff_bst_pend_scanout; | |
266 | wire bst_pend_out; | |
267 | wire blk_inst_w; | |
268 | wire dff_bst_err_scanin; | |
269 | wire dff_bst_err_scanout; | |
270 | wire bst_err_next; | |
271 | wire [4:0] rmo_count_dec; | |
272 | wire [4:0] rmo_count_in; | |
273 | wire blk_st_commit_p3; | |
274 | wire dff_rmo_count_scanin; | |
275 | wire dff_rmo_count_scanout; | |
276 | wire [4:0] rmo_count_out; | |
277 | wire blk_st_commit_p4; | |
278 | wire dff_rmo_commit_scanin; | |
279 | wire dff_rmo_commit_scanout; | |
280 | wire rmo_st_commit_p5; | |
281 | wire rmo_commit_p5; | |
282 | wire pst_ie_b; | |
283 | wire dff_pst_ie_scanin; | |
284 | wire dff_pst_ie_scanout; | |
285 | wire pst_ie_in; | |
286 | wire pst_ie_w; | |
287 | wire pst_ie; | |
288 | wire [1:0] st_type_in; | |
289 | wire [1:0] st_type; | |
290 | wire dff_st_type_scanin; | |
291 | wire dff_st_type_scanout; | |
292 | wire stb_flush_set; | |
293 | wire stb_flush_clr; | |
294 | wire stb_flush_in; | |
295 | wire dff_stb_flush_scanin; | |
296 | wire dff_stb_flush_scanout; | |
297 | wire spares_scanin; | |
298 | wire spares_scanout; | |
299 | ||
300 | ||
301 | input l2clk; | |
302 | input scan_in; | |
303 | input tcu_pce_ov; // scan signals | |
304 | input tcu_scan_en; | |
305 | input spc_aclk; | |
306 | input spc_bclk; | |
307 | output scan_out; | |
308 | ||
309 | input sbc_cam_wvld_m; // CAM is writing for this thread | |
310 | input sbc_st_sel_p3; // This thread was selected (not ld/st P3 qualified) | |
311 | input sbc_bst_sel; | |
312 | input sbc_rmo_st_b; | |
313 | input sbc_st_addr_new; | |
314 | input sbc_bst_b; // signals block store for this thread | |
315 | input sbc_bst_in_prog_b; // signals block store for any thread | |
316 | input sbc_fgu_ecc_b; // FRF ECC error in B (only used for block store) | |
317 | input sbc_bst_rd_err; // FRF ECC error in B (only used for block store) | |
318 | input sbc_sbs_kill_store_p4_; | |
319 | input sbc_tte_vld_b; // tlb_miss not accounted for | |
320 | input sbc_blk_inst_b; | |
321 | ||
322 | input dec_flush_lm; | |
323 | input dec_flush_lb; | |
324 | input tlu_flush_lsu_b; | |
325 | ||
326 | input spd_st_line_match; // Store in B is to same line as previous | |
327 | ||
328 | input dcc_asi_store_b; | |
329 | input dcc_asi_iomap_b; | |
330 | input dcc_asi_rngf_b; | |
331 | input dcc_asi_indet_b; | |
332 | input dcc_sync_inst_w; | |
333 | input dcc_casa_inst_b; | |
334 | input dcc_pst_asi_b; | |
335 | input [1:0] dcc_st_rq_type_w; | |
336 | input dcc_exception_flush_b; | |
337 | ||
338 | input tlb_tte_ie_b; | |
339 | ||
340 | input cic_st_ack; // Store from this thread is acked | |
341 | input cic_st_dequeue; // Dequeue the store from this thread. | |
342 | input cic_rmo_dequeue; // RMO ack received | |
343 | ||
344 | input pic_st_sel_p3; // Store wins ld/st arbitration in P3 | |
345 | ||
346 | input dcc_asi_rtn_vld; | |
347 | input dcc_asi_rtn_excp; | |
348 | input dcc_asi_rtn_rd; | |
349 | ||
350 | input lsu_lsu_pmen_; | |
351 | ||
352 | output [2:0] sbs_stb_wptr_m; | |
353 | output [2:0] sbs_stb_rptr; | |
354 | output sbs_pcx_rq_vld; | |
355 | output sbs_atm_rq_vld; | |
356 | output sbs_asi_rq_vld; | |
357 | output [7:0] sbs_state_vld; | |
358 | output [7:0] sbs_state_ced; | |
359 | output sbs_state_asi_rngf; | |
360 | output sbs_pcx_pst_ie_p4; | |
361 | output sbs_all_commited; | |
362 | output sbs_stb_empty; | |
363 | output sbs_stb_full; | |
364 | output sbs_bst_req; | |
365 | output sbs_sync; | |
366 | output sbs_asi_indet_req; // Indeterminate ASI store selected for issue | |
367 | output sbs_asi_indet_retire; // Indeterminate ASI store retired | |
368 | output sbs_rmo_st_p4; | |
369 | output sbs_blk_st_p4; | |
370 | output [1:0] sbs_st_type; | |
371 | ||
372 | output lsu_stb_alloc; | |
373 | output lsu_stb_dealloc; | |
374 | output lsu_block_store_kill; | |
375 | output lsu_stb_empty; | |
376 | ||
377 | // scan renames | |
378 | assign se = tcu_scan_en; | |
379 | assign pce_ov = tcu_pce_ov; | |
380 | assign stop = 1'b0; | |
381 | assign siclk = spc_aclk; | |
382 | assign soclk = spc_bclk; | |
383 | // end scan | |
384 | ||
385 | ////////////////////////////////////////// | |
386 | // Clock header and power mangagement | |
387 | ////////////////////////////////////////// | |
388 | ||
389 | // Clocks run when a store is in M/B/W of the pipe and anytime the store buffer is not empty | |
390 | assign sbs_clken = sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w | bst_pend | ~sbs_stb_empty | lsu_lsu_pmen_; | |
391 | ||
392 | lsu_sbs_ctl_l1clkhdr_ctl_macro clkgen ( | |
393 | .l2clk (l2clk), | |
394 | .l1en (1'b1 ), | |
395 | .l1clk (l1clk), | |
396 | .pce_ov(pce_ov), | |
397 | .stop(stop), | |
398 | .se(se) | |
399 | ); | |
400 | ||
401 | lsu_sbs_ctl_l1clkhdr_ctl_macro clkgenpm ( | |
402 | .l2clk (l2clk ), | |
403 | .l1en (sbs_clken), | |
404 | .l1clk (l1clk_pm1 ), | |
405 | .pce_ov(pce_ov), | |
406 | .stop(stop), | |
407 | .se(se) | |
408 | ); | |
409 | ||
410 | ////////////////////////////// | |
411 | // Flush logic | |
412 | ////////////////////////////// | |
413 | ||
414 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_flush_b ( | |
415 | .scan_in(dff_flush_b_scanin), | |
416 | .scan_out(dff_flush_b_scanout), | |
417 | .din (dec_flush_lm), | |
418 | .dout (pipe_flush_b), | |
419 | .l1clk(l1clk), | |
420 | .siclk(siclk), | |
421 | .soclk(soclk) | |
422 | ); | |
423 | ||
424 | assign flush_b = tlu_flush_lsu_b | dec_flush_lb | pipe_flush_b | dcc_exception_flush_b; | |
425 | ||
426 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_flush_w ( | |
427 | .scan_in(dff_flush_w_scanin), | |
428 | .scan_out(dff_flush_w_scanout), | |
429 | .din (flush_b), | |
430 | .dout (flush_w), | |
431 | .l1clk(l1clk), | |
432 | .siclk(siclk), | |
433 | .soclk(soclk) | |
434 | ); | |
435 | ||
436 | /////////////////////////////////////////////////// | |
437 | ||
438 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_cam_wvld_b ( | |
439 | .scan_in(dff_cam_wvld_b_scanin), | |
440 | .scan_out(dff_cam_wvld_b_scanout), | |
441 | .l1clk (l1clk_pm1), | |
442 | .din (sbc_cam_wvld_m), | |
443 | .dout (stb_cam_wvld_b), | |
444 | .siclk(siclk), | |
445 | .soclk(soclk) | |
446 | ); | |
447 | ||
448 | assign kill_store_p4 = st_commit_p4 & ~sbc_sbs_kill_store_p4_; | |
449 | ||
450 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_st_dq ( | |
451 | .scan_in(dff_st_dq_scanin), | |
452 | .scan_out(dff_st_dq_scanout), | |
453 | .din ({(cic_st_dequeue | dcc_asi_rtn_vld & ~dcc_asi_rtn_rd),kill_store_p4,block_store_kill}), | |
454 | .dout ({st_dequeue_d1, kill_store_p5,lsu_block_store_kill}), | |
455 | .l1clk(l1clk), | |
456 | .siclk(siclk), | |
457 | .soclk(soclk) | |
458 | ); | |
459 | ||
460 | // Assertion to check for STB overflow | |
461 | // 0in multi_enq_deq_fifo -enq stb_cam_wvld_b -deq flush_st_w lsu_stb_dealloc bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill bst_kill (kill_store_p4 & ~(rmo_st_commit_p4 & ~stb_flush_state) & ~sbc_bst_sel) flush_bst_inst -depth 8 | |
462 | ||
463 | //////////////////////////////////////////////////////////////////////////////// | |
464 | // STB Read Pointer | |
465 | //////////////////////////////////////////////////////////////////////////////// | |
466 | // A store can be sent to the pcx if the previous entry has been acked, or if | |
467 | // the it is addressed to the same L2 cache line (addr[39:6]) as the previous | |
468 | // store. Stores to IO cannot be pipelined. Conditions for release are | |
469 | // (1) Entry is valid and not already sent to pcx. AND | |
470 | // (2) Previous entry is invalid or | |
471 | // (3) Previous entry is valid and | |
472 | // (a) mem store - prev. entry is acked OR (non-rmo only) | |
473 | // (b) asi store - prev. entry is asi and acked | |
474 | // If a store can be pipelined, the ack for the previous store will be set. | |
475 | // The dec_dqptr term at the end is to prevent a deadlock condition where | |
476 | // all entries are valid but none have been committed. | |
477 | ||
478 | // Timing : this is very critical. Some improvement could be made by | |
479 | // decoding dec_stb_rptr and/or dec_dqptr in the previous cycle. | |
480 | assign dec_rptr_pcx[7:0] = | |
481 | dec_stb_rptr[7:0] & stb_state_vld[7:0] & ~stb_state_ced[7:0] & // --> (1) | |
482 | (~{stb_state_vld[6:0],stb_state_vld[7]} | // --> (2) | |
483 | ({stb_state_vld[6:0],stb_state_vld[7]} & // --> (3) | |
484 | {stb_state_ack[6:0],stb_state_ack[7]} & | |
485 | (stb_state_mem[7:0] & ~stb_state_rmo[7:0]) | // --> (3a) | |
486 | (stb_state_asi[7:0] & {stb_state_asi[6:0],stb_state_asi[7]}) // --> (3b) | |
487 | ) | | |
488 | dec_dqptr[7:0]); | |
489 | ||
490 | // Max number of RMO stores outstanding is 8. When 8 are out, rmo stores are blocked. | |
491 | assign sbs_pcx_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_mem[7:0]) & ~(rmo_count[4] & sbs_rmo_st) & ~bst_err; | |
492 | assign sbs_atm_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_cas[7:0]); | |
493 | assign sbs_asi_rq_vld = |(dec_rptr_pcx[7:0] & stb_state_asi[7:0]); | |
494 | ||
495 | assign stb_rptr_inc[3:0] = stb_rptr[3:0] + 4'b0001; | |
496 | ||
497 | // Bit 3 must "wrap" when the buffer is flushed on a bst_kill error | |
498 | assign stb_rptr_in[3] = ((stb_commit_entry | flush_bst_inst) ? stb_rptr_inc[3] : stb_rptr[3]) ^ bst_kill; | |
499 | assign stb_rptr_in[2:0] = (stb_commit_entry | flush_bst_inst) ? stb_rptr_inc[2:0] : stb_rptr[2:0]; | |
500 | ||
501 | lsu_sbs_ctl_msff_ctl_macro__width_4 dff_rptr ( | |
502 | .scan_in(dff_rptr_scanin), | |
503 | .scan_out(dff_rptr_scanout), | |
504 | .l1clk (l1clk_pm1), | |
505 | .din (stb_rptr_in[3:0]), | |
506 | .dout (stb_rptr[3:0]), | |
507 | .siclk(siclk), | |
508 | .soclk(soclk) | |
509 | ); | |
510 | ||
511 | assign sbs_stb_rptr[2:0] = stb_rptr[2:0]; | |
512 | ||
513 | assign dec_stb_rptr[0] = ~stb_rptr[2] & ~stb_rptr[1] & ~stb_rptr[0]; | |
514 | assign dec_stb_rptr[1] = ~stb_rptr[2] & ~stb_rptr[1] & stb_rptr[0]; | |
515 | assign dec_stb_rptr[2] = ~stb_rptr[2] & stb_rptr[1] & ~stb_rptr[0]; | |
516 | assign dec_stb_rptr[3] = ~stb_rptr[2] & stb_rptr[1] & stb_rptr[0]; | |
517 | assign dec_stb_rptr[4] = stb_rptr[2] & ~stb_rptr[1] & ~stb_rptr[0]; | |
518 | assign dec_stb_rptr[5] = stb_rptr[2] & ~stb_rptr[1] & stb_rptr[0]; | |
519 | assign dec_stb_rptr[6] = stb_rptr[2] & stb_rptr[1] & ~stb_rptr[0]; | |
520 | assign dec_stb_rptr[7] = stb_rptr[2] & stb_rptr[1] & stb_rptr[0]; | |
521 | ||
522 | //////////////////////////////////////////////////////////////////////////////// | |
523 | // STB Write Pointer | |
524 | //////////////////////////////////////////////////////////////////////////////// | |
525 | ||
526 | // A valid entry causes the pointer to increment. | |
527 | // A flushed store instruction decrements the pointer. | |
528 | ||
529 | assign stb_wptr_incr[3:0] = stb_wptr[3:0] + {3'b000,~flush_st_w}; | |
530 | assign stb_wptr_decr[3:0] = stb_wptr[3:0] - {3'b000,flush_st_w}; | |
531 | ||
532 | assign stb_wptr_in[3:0] = sbc_cam_wvld_m ? stb_wptr_incr[3:0] : stb_wptr_decr[3:0]; | |
533 | ||
534 | lsu_sbs_ctl_msff_ctl_macro__width_4 dff_wptr ( | |
535 | .scan_in(dff_wptr_scanin), | |
536 | .scan_out(dff_wptr_scanout), | |
537 | .l1clk (l1clk_pm1), | |
538 | .din (stb_wptr_in[3:0]), | |
539 | .dout (stb_wptr[3:0]), | |
540 | .siclk(siclk), | |
541 | .soclk(soclk) | |
542 | ); | |
543 | ||
544 | assign sbs_stb_wptr_m[2:0] = stb_wptr[2:0]; | |
545 | ||
546 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_wptr_b ( | |
547 | .scan_in(dff_wptr_b_scanin), | |
548 | .scan_out(dff_wptr_b_scanout), | |
549 | .l1clk (l1clk_pm1), | |
550 | .din (stb_wptr[2:0]), | |
551 | .dout (stb_wptr_b[2:0]), | |
552 | .siclk(siclk), | |
553 | .soclk(soclk) | |
554 | ); | |
555 | ||
556 | assign dec_wptr_b[0] = ~stb_wptr_b[2] & ~stb_wptr_b[1] & ~stb_wptr_b[0]; | |
557 | assign dec_wptr_b[1] = ~stb_wptr_b[2] & ~stb_wptr_b[1] & stb_wptr_b[0]; | |
558 | assign dec_wptr_b[2] = ~stb_wptr_b[2] & stb_wptr_b[1] & ~stb_wptr_b[0]; | |
559 | assign dec_wptr_b[3] = ~stb_wptr_b[2] & stb_wptr_b[1] & stb_wptr_b[0]; | |
560 | assign dec_wptr_b[4] = stb_wptr_b[2] & ~stb_wptr_b[1] & ~stb_wptr_b[0]; | |
561 | assign dec_wptr_b[5] = stb_wptr_b[2] & ~stb_wptr_b[1] & stb_wptr_b[0]; | |
562 | assign dec_wptr_b[6] = stb_wptr_b[2] & stb_wptr_b[1] & ~stb_wptr_b[0]; | |
563 | assign dec_wptr_b[7] = stb_wptr_b[2] & stb_wptr_b[1] & stb_wptr_b[0]; | |
564 | ||
565 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_wptr_w ( | |
566 | .scan_in(dff_wptr_w_scanin), | |
567 | .scan_out(dff_wptr_w_scanout), | |
568 | .l1clk (l1clk_pm1), | |
569 | .din (stb_wptr_b[2:0]), | |
570 | .dout (stb_wptr_w[2:0]), | |
571 | .siclk(siclk), | |
572 | .soclk(soclk) | |
573 | ); | |
574 | ||
575 | assign dec_wptr_w[0] = ~stb_wptr_w[2] & ~stb_wptr_w[1] & ~stb_wptr_w[0]; | |
576 | assign dec_wptr_w[1] = ~stb_wptr_w[2] & ~stb_wptr_w[1] & stb_wptr_w[0]; | |
577 | assign dec_wptr_w[2] = ~stb_wptr_w[2] & stb_wptr_w[1] & ~stb_wptr_w[0]; | |
578 | assign dec_wptr_w[3] = ~stb_wptr_w[2] & stb_wptr_w[1] & stb_wptr_w[0]; | |
579 | assign dec_wptr_w[4] = stb_wptr_w[2] & ~stb_wptr_w[1] & ~stb_wptr_w[0]; | |
580 | assign dec_wptr_w[5] = stb_wptr_w[2] & ~stb_wptr_w[1] & stb_wptr_w[0]; | |
581 | assign dec_wptr_w[6] = stb_wptr_w[2] & stb_wptr_w[1] & ~stb_wptr_w[0]; | |
582 | assign dec_wptr_w[7] = stb_wptr_w[2] & stb_wptr_w[1] & stb_wptr_w[0]; | |
583 | ||
584 | assign stb_empty = ~|(stb_state_vld[7:0]) & (rmo_count[4:0] == 5'd0) & ~rmo_st_commit_p4; | |
585 | assign sbs_stb_empty = stb_empty & ~bst_pend & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w); | |
586 | assign lsu_stb_empty = stb_empty & ~bst_pend; | |
587 | ||
588 | // Might be able to speed this up by comparing stb_wptr_decr == stb_rptr_inc | |
589 | // in previous cycle and flopping down. I'd still have to deal with the | |
590 | // stb_flush_done part though. | |
591 | assign sbs_last_entry = (stb_wptr[3:0] == stb_rptr[3:0]); | |
592 | ||
593 | assign sbs_stb_full = &(stb_state_vld[7:0]); | |
594 | ||
595 | //////////////////////////////////////////////////////////////////////////////// | |
596 | // Control state | |
597 | //////////////////////////////////////////////////////////////////////////////// | |
598 | ||
599 | // State is reset when an entry is dequeued and when a store gets flushed. | |
600 | // 0in bits_on -var {st_dequeue_d1,(rmo_st_commit_p4 & ~stb_flush_state)} -max 1 -message "multiple stores retiring simultaneously" | |
601 | assign lsu_stb_dealloc = st_dequeue_d1 | (rmo_st_commit_p4 & ~stb_flush_state); | |
602 | ||
603 | assign dqptr_in[2:0] = stb_flush_done ? stb_wptr[2:0] : (dqptr[2:0] + {2'b00, lsu_stb_dealloc}); | |
604 | ||
605 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_dqptr ( | |
606 | .scan_in(dff_dqptr_scanin), | |
607 | .scan_out(dff_dqptr_scanout), | |
608 | .din (dqptr_in[2:0]), | |
609 | .dout (dqptr[2:0]), | |
610 | .l1clk(l1clk), | |
611 | .siclk(siclk), | |
612 | .soclk(soclk) | |
613 | ); | |
614 | assign dec_dqptr[0] = ~dqptr[2] & ~dqptr[1] & ~dqptr[0]; | |
615 | assign dec_dqptr[1] = ~dqptr[2] & ~dqptr[1] & dqptr[0]; | |
616 | assign dec_dqptr[2] = ~dqptr[2] & dqptr[1] & ~dqptr[0]; | |
617 | assign dec_dqptr[3] = ~dqptr[2] & dqptr[1] & dqptr[0]; | |
618 | assign dec_dqptr[4] = dqptr[2] & ~dqptr[1] & ~dqptr[0]; | |
619 | assign dec_dqptr[5] = dqptr[2] & ~dqptr[1] & dqptr[0]; | |
620 | assign dec_dqptr[6] = dqptr[2] & dqptr[1] & ~dqptr[0]; | |
621 | assign dec_dqptr[7] = dqptr[2] & dqptr[1] & dqptr[0]; | |
622 | ||
623 | assign stb_state_rst[7:0] = ({8{st_dequeue_d1}} & dec_dqptr[7:0]) | | |
624 | ({8{rmo_st_commit_p3}} & dec_stb_rptr[7:0]) | | |
625 | ({dec_stb_rptr[0],dec_stb_rptr[7:1]} & {8{kill_store_p5}}) | | |
626 | (dec_wptr_w[7:0] & {8{flush_st_w}}) | | |
627 | {8{bst_kill}}; | |
628 | ||
629 | // Valid state. Set when a store is written to the STB. Cleared when the store | |
630 | // updates the cache. The valid state is set in W. If the store | |
631 | // in W must be flushed, disqualify the valid bit and reset the state. | |
632 | ||
633 | assign set_valid_b = stb_cam_wvld_b & ~sbc_blk_inst_b; | |
634 | ||
635 | assign stb_state_vld_set[7:0] = dec_wptr_b[7:0] & {8{set_valid_b}}; | |
636 | ||
637 | assign stb_state_vld_din[7:0] = stb_state_vld_set[7:0] | | |
638 | (~stb_state_rst[7:0] & stb_state_vld[7:0]); | |
639 | ||
640 | lsu_sbs_ctl_msff_ctl_macro__width_9 dff_stb_vld ( | |
641 | .scan_in(dff_stb_vld_scanin), | |
642 | .scan_out(dff_stb_vld_scanout), | |
643 | .l1clk (l1clk_pm1), | |
644 | .din ({stb_state_vld_din[7:0],set_valid_b}), | |
645 | .dout ({stb_state_vld_out[7:0], set_valid_w}), | |
646 | .siclk(siclk), | |
647 | .soclk(soclk) | |
648 | ); | |
649 | assign stb_state_vld[7:0] = stb_state_vld_out[7:0] & ~({8{flush_st_w}} & dec_wptr_w[7:0]); | |
650 | ||
651 | // Used for enabling CAM lookup on the next cycle | |
652 | assign sbs_state_vld[7:0] = stb_state_mem[7:0] | (misc_state_wr[7:0] & {8{~dcc_asi_store_b}}); | |
653 | ||
654 | assign stb_alloc_b = stb_cam_wvld_b; | |
655 | ||
656 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_stb_alloc_w ( | |
657 | .scan_in(dff_stb_alloc_w_scanin), | |
658 | .scan_out(dff_stb_alloc_w_scanout), | |
659 | .l1clk (l1clk_pm1), | |
660 | .din (stb_alloc_b), | |
661 | .dout (stb_alloc_w), | |
662 | .siclk(siclk), | |
663 | .soclk(soclk) | |
664 | ); | |
665 | assign lsu_stb_alloc = stb_alloc_w & ~flush_w; | |
666 | assign flush_st_w = stb_alloc_w & flush_w; | |
667 | ||
668 | ||
669 | // Commited State. Set when a store is issued to the pcx. | |
670 | ||
671 | // 0in bits_on -var {(sbc_st_sel_p3 & pic_st_sel_p3),sbc_bst_sel,flush_bst_inst} -max 1 -message "multiple stores commiting" | |
672 | ||
673 | assign flush_bst_inst = bst_pend & stb_flush_state & stb_empty & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w); | |
674 | ||
675 | assign stb_commit_entry = (sbc_st_sel_p3 & pic_st_sel_p3) | sbc_bst_sel; | |
676 | ||
677 | assign st_commit_p3 = sbc_st_sel_p3 & pic_st_sel_p3; | |
678 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_st_commit_p4 ( | |
679 | .scan_in(dff_st_commit_p4_scanin), | |
680 | .scan_out(dff_st_commit_p4_scanout), | |
681 | .l1clk (l1clk_pm1), | |
682 | .din (st_commit_p3), | |
683 | .dout (st_commit_p4), | |
684 | .siclk(siclk), | |
685 | .soclk(soclk) | |
686 | ); | |
687 | ||
688 | ||
689 | assign stb_state_ced_set[7:0] = dec_stb_rptr[7:0] & {8{stb_commit_entry}}; | |
690 | ||
691 | assign stb_state_ced_din[7:0] = ~stb_state_rst[7:0] & | |
692 | (stb_state_ced_set[7:0] | stb_state_ced[7:0]); | |
693 | ||
694 | lsu_sbs_ctl_msff_ctl_macro__width_8 dff_stb_ced ( | |
695 | .scan_in(dff_stb_ced_scanin), | |
696 | .scan_out(dff_stb_ced_scanout), | |
697 | .l1clk (l1clk_pm1), | |
698 | .din (stb_state_ced_din[7:0]), | |
699 | .dout (stb_state_ced[7:0]), | |
700 | .siclk(siclk), | |
701 | .soclk(soclk) | |
702 | ); | |
703 | ||
704 | assign sbs_state_ced[7:0] = stb_state_ced[7:0]; | |
705 | assign sbs_all_commited = &(~stb_state_vld[7:0] | stb_state_ced[7:0]); | |
706 | ||
707 | // Acked State. Set when a store ack is received from the CPX. We do not have | |
708 | // to wait for the ack to reach the head of the CPQ since the | |
709 | // arrival on the CPX means the L2 has the store and will enforce | |
710 | // ordering requirements. | |
711 | // Ack state is automatically set when the "next" store can | |
712 | // be pipelined. Ack state is cleared when a store is first | |
713 | // written to prevent stray acks. | |
714 | ||
715 | // 0in bits_on -var {cic_st_ack,sbc_bst_sel,(rmo_st_commit_p4 & ~stb_flush_state),(dcc_asi_rtn_vld & ~dcc_asi_rtn_rd)} -max 1 -message "multiple acks received" | |
716 | assign ackptr_in[2:0] = stb_flush_done ? stb_wptr[2:0] : | |
717 | (ackptr[2:0] + {2'b00, (cic_st_ack | (dcc_asi_rtn_vld & ~dcc_asi_rtn_rd) | sbc_bst_sel | rmo_st_commit_p4)}); | |
718 | ||
719 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_ackptr ( | |
720 | .scan_in(dff_ackptr_scanin), | |
721 | .scan_out(dff_ackptr_scanout), | |
722 | .din (ackptr_in[2:0]), | |
723 | .dout (ackptr[2:0]), | |
724 | .l1clk(l1clk), | |
725 | .siclk(siclk), | |
726 | .soclk(soclk) | |
727 | ); | |
728 | ||
729 | assign dec_ackptr[0] = ~ackptr[2] & ~ackptr[1] & ~ackptr[0]; | |
730 | assign dec_ackptr[1] = ~ackptr[2] & ~ackptr[1] & ackptr[0]; | |
731 | assign dec_ackptr[2] = ~ackptr[2] & ackptr[1] & ~ackptr[0]; | |
732 | assign dec_ackptr[3] = ~ackptr[2] & ackptr[1] & ackptr[0]; | |
733 | assign dec_ackptr[4] = ackptr[2] & ~ackptr[1] & ~ackptr[0]; | |
734 | assign dec_ackptr[5] = ackptr[2] & ~ackptr[1] & ackptr[0]; | |
735 | assign dec_ackptr[6] = ackptr[2] & ackptr[1] & ~ackptr[0]; | |
736 | assign dec_ackptr[7] = ackptr[2] & ackptr[1] & ackptr[0]; | |
737 | ||
738 | assign stb_state_ack_set[7:0] = (dec_ackptr[7:0] & {8{cic_st_ack | (dcc_asi_rtn_vld & ~dcc_asi_rtn_rd)}}) | | |
739 | ({dec_wptr_w[0],dec_wptr_w[7:1]} & {8{pipe_store_w & set_valid_w & ~flush_w}}); | |
740 | ||
741 | assign stb_state_ack_rst[7:0] = stb_state_rst[7:0] | (dec_wptr_b[7:0] & {8{stb_cam_wvld_b}}); | |
742 | ||
743 | assign stb_state_ack_din[7:0] = ~stb_state_ack_rst[7:0] & (stb_state_ack_set[7:0] | stb_state_ack[7:0]); | |
744 | ||
745 | lsu_sbs_ctl_msff_ctl_macro__width_8 dff_stb_ack ( | |
746 | .scan_in(dff_stb_ack_scanin), | |
747 | .scan_out(dff_stb_ack_scanout), | |
748 | .l1clk (l1clk_pm1), | |
749 | .din (stb_state_ack_din[7:0]), | |
750 | .dout (stb_state_ack[7:0]), | |
751 | .siclk(siclk), | |
752 | .soclk(soclk) | |
753 | ); | |
754 | ||
755 | // Stores are pipelinable if they are to the same L2 cache line, | |
756 | // to the same ring for ASI stores, and they are not IO stores. | |
757 | ||
758 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_asi_w ( | |
759 | .scan_in(dff_asi_w_scanin), | |
760 | .scan_out(dff_asi_w_scanout), | |
761 | .l1clk (l1clk_pm1), | |
762 | .din ({dcc_asi_store_b,dcc_asi_rngf_b,sbc_rmo_st_b}), | |
763 | .dout ({asi_store_w, asi_rngf_w, rmo_st_w}), | |
764 | .siclk(siclk), | |
765 | .soclk(soclk) | |
766 | ); | |
767 | ||
768 | assign last_st_asi = sbc_st_addr_new ? asi_store_w : last_st_asi_d1 ; | |
769 | assign last_asi_ring = sbc_st_addr_new ? asi_rngf_w : last_asi_ring_d1; | |
770 | assign last_st_rmo = sbc_st_addr_new ? rmo_st_w : last_st_rmo_d1 ; | |
771 | ||
772 | lsu_sbs_ctl_msff_ctl_macro__width_4 dff_asi_pipe ( | |
773 | .scan_in(dff_asi_pipe_scanin), | |
774 | .scan_out(dff_asi_pipe_scanout), | |
775 | .l1clk (l1clk_pm1), | |
776 | .din ({last_st_asi,last_asi_ring, last_st_rmo, pipe_store_b}), | |
777 | .dout ({last_st_asi_d1,last_asi_ring_d1,last_st_rmo_d1,pipe_store_w}), | |
778 | .siclk(siclk), | |
779 | .soclk(soclk) | |
780 | ); | |
781 | ||
782 | assign pipe_store_b = (dcc_asi_store_b ~^ last_st_asi) & // asi/non-asi must match | |
783 | (sbc_rmo_st_b ~^ last_st_rmo) & // rmo must match | |
784 | ~dcc_asi_indet_b & // indeterminate ASI's never pipeline | |
785 | ~dcc_asi_iomap_b & // iomapped ASI's never pipeline | |
786 | ((~dcc_asi_store_b & spd_st_line_match) | // non-asi must be same L2 line | |
787 | (dcc_asi_store_b & (last_asi_ring ~^ dcc_asi_rngf_b))); // asi must be same ring | |
788 | ||
789 | //////////////////////////////////////////////////////////////////////////////// | |
790 | // Misc information. The information differs between asi and non-asi stores | |
791 | // 2 1 0 | |
792 | // ASI | 1'b0 | ind | fast | | |
793 | // | |
794 | // 2 1 0 | |
795 | // non-ASI | 1'b1 | CAS | rmo | | |
796 | // | |
797 | // Use [2:0] = 111 to signal a block store type | |
798 | //////////////////////////////////////////////////////////////////////////////// | |
799 | ||
800 | assign misc_state_wr[7:0] = dec_wptr_b[7:0] & {8{stb_cam_wvld_b & ~sbc_blk_inst_b}}; | |
801 | ||
802 | assign sbs_state_in[2:0] = (dcc_asi_store_b & ~dcc_asi_iomap_b) ? | |
803 | {1'b0,dcc_asi_indet_b,dcc_asi_rngf_b} : | |
804 | {1'b1,(dcc_casa_inst_b | sbc_bst_b),sbc_rmo_st_b}; | |
805 | ||
806 | assign stb_state_0_din[2:0] = {3{~stb_state_rst[0]}} & (misc_state_wr[0] ? sbs_state_in[2:0] : sbs_state_0[2:0]); | |
807 | assign stb_state_1_din[2:0] = {3{~stb_state_rst[1]}} & (misc_state_wr[1] ? sbs_state_in[2:0] : sbs_state_1[2:0]); | |
808 | assign stb_state_2_din[2:0] = {3{~stb_state_rst[2]}} & (misc_state_wr[2] ? sbs_state_in[2:0] : sbs_state_2[2:0]); | |
809 | assign stb_state_3_din[2:0] = {3{~stb_state_rst[3]}} & (misc_state_wr[3] ? sbs_state_in[2:0] : sbs_state_3[2:0]); | |
810 | assign stb_state_4_din[2:0] = {3{~stb_state_rst[4]}} & (misc_state_wr[4] ? sbs_state_in[2:0] : sbs_state_4[2:0]); | |
811 | assign stb_state_5_din[2:0] = {3{~stb_state_rst[5]}} & (misc_state_wr[5] ? sbs_state_in[2:0] : sbs_state_5[2:0]); | |
812 | assign stb_state_6_din[2:0] = {3{~stb_state_rst[6]}} & (misc_state_wr[6] ? sbs_state_in[2:0] : sbs_state_6[2:0]); | |
813 | assign stb_state_7_din[2:0] = {3{~stb_state_rst[7]}} & (misc_state_wr[7] ? sbs_state_in[2:0] : sbs_state_7[2:0]); | |
814 | ||
815 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_0 ( | |
816 | .scan_in(dff_state_0_scanin), | |
817 | .scan_out(dff_state_0_scanout), | |
818 | .l1clk (l1clk_pm1), | |
819 | .din (stb_state_0_din[2:0]), | |
820 | .dout (sbs_state_0[2:0]), | |
821 | .siclk(siclk), | |
822 | .soclk(soclk) | |
823 | ); | |
824 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_1 ( | |
825 | .scan_in(dff_state_1_scanin), | |
826 | .scan_out(dff_state_1_scanout), | |
827 | .l1clk (l1clk_pm1), | |
828 | .din (stb_state_1_din[2:0]), | |
829 | .dout (sbs_state_1[2:0]), | |
830 | .siclk(siclk), | |
831 | .soclk(soclk) | |
832 | ); | |
833 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_2 ( | |
834 | .scan_in(dff_state_2_scanin), | |
835 | .scan_out(dff_state_2_scanout), | |
836 | .l1clk (l1clk_pm1), | |
837 | .din (stb_state_2_din[2:0]), | |
838 | .dout (sbs_state_2[2:0]), | |
839 | .siclk(siclk), | |
840 | .soclk(soclk) | |
841 | ); | |
842 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_3 ( | |
843 | .scan_in(dff_state_3_scanin), | |
844 | .scan_out(dff_state_3_scanout), | |
845 | .l1clk (l1clk_pm1), | |
846 | .din (stb_state_3_din[2:0]), | |
847 | .dout (sbs_state_3[2:0]), | |
848 | .siclk(siclk), | |
849 | .soclk(soclk) | |
850 | ); | |
851 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_4 ( | |
852 | .scan_in(dff_state_4_scanin), | |
853 | .scan_out(dff_state_4_scanout), | |
854 | .l1clk (l1clk_pm1), | |
855 | .din (stb_state_4_din[2:0]), | |
856 | .dout (sbs_state_4[2:0]), | |
857 | .siclk(siclk), | |
858 | .soclk(soclk) | |
859 | ); | |
860 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_5 ( | |
861 | .scan_in(dff_state_5_scanin), | |
862 | .scan_out(dff_state_5_scanout), | |
863 | .l1clk (l1clk_pm1), | |
864 | .din (stb_state_5_din[2:0]), | |
865 | .dout (sbs_state_5[2:0]), | |
866 | .siclk(siclk), | |
867 | .soclk(soclk) | |
868 | ); | |
869 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_6 ( | |
870 | .scan_in(dff_state_6_scanin), | |
871 | .scan_out(dff_state_6_scanout), | |
872 | .l1clk (l1clk_pm1), | |
873 | .din (stb_state_6_din[2:0]), | |
874 | .dout (sbs_state_6[2:0]), | |
875 | .siclk(siclk), | |
876 | .soclk(soclk) | |
877 | ); | |
878 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_state_7 ( | |
879 | .scan_in(dff_state_7_scanin), | |
880 | .scan_out(dff_state_7_scanout), | |
881 | .l1clk (l1clk_pm1), | |
882 | .din (stb_state_7_din[2:0]), | |
883 | .dout (sbs_state_7[2:0]), | |
884 | .siclk(siclk), | |
885 | .soclk(soclk) | |
886 | ); | |
887 | ||
888 | assign stb_state_mem[7:0] = {sbs_state_7[2],sbs_state_6[2],sbs_state_5[2],sbs_state_4[2], | |
889 | sbs_state_3[2],sbs_state_2[2],sbs_state_1[2],sbs_state_0[2]}; | |
890 | assign stb_state_asi[7:0] = ~stb_state_mem[7:0]; | |
891 | ||
892 | assign sbs_state_asi_rngf = (dec_stb_rptr[0] & sbs_state_0[0]) | | |
893 | (dec_stb_rptr[1] & sbs_state_1[0]) | | |
894 | (dec_stb_rptr[2] & sbs_state_2[0]) | | |
895 | (dec_stb_rptr[3] & sbs_state_3[0]) | | |
896 | (dec_stb_rptr[4] & sbs_state_4[0]) | | |
897 | (dec_stb_rptr[5] & sbs_state_5[0]) | | |
898 | (dec_stb_rptr[6] & sbs_state_6[0]) | | |
899 | (dec_stb_rptr[7] & sbs_state_7[0]); | |
900 | ||
901 | assign sbs_rmo_st = (dec_stb_rptr[0] & stb_state_mem[0] & sbs_state_0[0]) | | |
902 | (dec_stb_rptr[1] & stb_state_mem[1] & sbs_state_1[0]) | | |
903 | (dec_stb_rptr[2] & stb_state_mem[2] & sbs_state_2[0]) | | |
904 | (dec_stb_rptr[3] & stb_state_mem[3] & sbs_state_3[0]) | | |
905 | (dec_stb_rptr[4] & stb_state_mem[4] & sbs_state_4[0]) | | |
906 | (dec_stb_rptr[5] & stb_state_mem[5] & sbs_state_5[0]) | | |
907 | (dec_stb_rptr[6] & stb_state_mem[6] & sbs_state_6[0]) | | |
908 | (dec_stb_rptr[7] & stb_state_mem[7] & sbs_state_7[0]) ; | |
909 | ||
910 | assign stb_state_rmo[7:0] = {sbs_state_7[0],sbs_state_6[0],sbs_state_5[0],sbs_state_4[0], | |
911 | sbs_state_3[0],sbs_state_2[0],sbs_state_1[0],sbs_state_0[0]}; | |
912 | ||
913 | assign sbs_blk_st = (dec_stb_rptr[0] & stb_state_mem[0] & sbs_state_0[1] & sbs_state_0[0]) | | |
914 | (dec_stb_rptr[1] & stb_state_mem[1] & sbs_state_1[1] & sbs_state_1[0]) | | |
915 | (dec_stb_rptr[2] & stb_state_mem[2] & sbs_state_2[1] & sbs_state_2[0]) | | |
916 | (dec_stb_rptr[3] & stb_state_mem[3] & sbs_state_3[1] & sbs_state_3[0]) | | |
917 | (dec_stb_rptr[4] & stb_state_mem[4] & sbs_state_4[1] & sbs_state_4[0]) | | |
918 | (dec_stb_rptr[5] & stb_state_mem[5] & sbs_state_5[1] & sbs_state_5[0]) | | |
919 | (dec_stb_rptr[6] & stb_state_mem[6] & sbs_state_6[1] & sbs_state_6[0]) | | |
920 | (dec_stb_rptr[7] & stb_state_mem[7] & sbs_state_7[1] & sbs_state_7[0]) ; | |
921 | ||
922 | assign stb_state_indet[7:0] = {sbs_state_7[1] & stb_state_asi[7], | |
923 | sbs_state_6[1] & stb_state_asi[6], | |
924 | sbs_state_5[1] & stb_state_asi[5], | |
925 | sbs_state_4[1] & stb_state_asi[4], | |
926 | sbs_state_3[1] & stb_state_asi[3], | |
927 | sbs_state_2[1] & stb_state_asi[2], | |
928 | sbs_state_1[1] & stb_state_asi[1], | |
929 | sbs_state_0[1] & stb_state_asi[0] | |
930 | }; | |
931 | ||
932 | assign sbs_asi_indet_req = |(stb_state_indet[7:0] & dec_stb_rptr[7:0]); | |
933 | assign sbs_asi_indet_retire = |(stb_state_indet[7:0] & dec_dqptr[7:0]) & st_dequeue_d1; | |
934 | ||
935 | assign stb_state_cas[7:0] = {sbs_state_7[1] & ~sbs_state_7[0], | |
936 | sbs_state_6[1] & ~sbs_state_6[0], | |
937 | sbs_state_5[1] & ~sbs_state_5[0], | |
938 | sbs_state_4[1] & ~sbs_state_4[0], | |
939 | sbs_state_3[1] & ~sbs_state_3[0], | |
940 | sbs_state_2[1] & ~sbs_state_2[0], | |
941 | sbs_state_1[1] & ~sbs_state_1[0], | |
942 | sbs_state_0[1] & ~sbs_state_0[0]}; | |
943 | ||
944 | //////////////////////////////////////////////////////////////////////////////// | |
945 | // Synchronizing instruction (flush/membar/stbar) tracking | |
946 | // The thread will postsync on one of these instructions. Once the store | |
947 | // buffer is empty, a trap flush will restart the thread. | |
948 | //////////////////////////////////////////////////////////////////////////////// | |
949 | ||
950 | assign asi_error = dcc_asi_rtn_vld & dcc_asi_rtn_excp; | |
951 | ||
952 | assign sync_state = dcc_sync_inst_w | sync_state_out; | |
953 | ||
954 | assign sync_state_rst = (sync_state & sbs_stb_empty) | asi_error; | |
955 | ||
956 | assign sync_state_in = (dcc_sync_inst_w | sync_state_out) & ~sync_state_rst; | |
957 | ||
958 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_sync_state ( | |
959 | .scan_in(dff_sync_state_scanin), | |
960 | .scan_out(dff_sync_state_scanout), | |
961 | .din (sync_state_in), | |
962 | .dout (sync_state_out), | |
963 | .l1clk(l1clk), | |
964 | .siclk(siclk), | |
965 | .soclk(soclk) | |
966 | ); | |
967 | ||
968 | assign trap_sync = sync_state_rst & ~asi_error; | |
969 | ||
970 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_sbs_sync ( | |
971 | .scan_in(dff_sbs_sync_scanin), | |
972 | .scan_out(dff_sbs_sync_scanout), | |
973 | .din (trap_sync), | |
974 | .dout (sbs_sync), | |
975 | .l1clk(l1clk), | |
976 | .siclk(siclk), | |
977 | .soclk(soclk) | |
978 | ); | |
979 | ||
980 | //////////////////////////////////////////////////////////////////////////////// | |
981 | // Block stores | |
982 | //////////////////////////////////////////////////////////////////////////////// | |
983 | ||
984 | // Simultaneous set and reset could be a problem so check for it. | |
985 | // 0in bits_on -var {(stb_alloc_w & blk_inst_w & ~flush_w),(bst_w & ~sbc_bst_b)} -max 1 | |
986 | assign bst_pend_in = (bst_pend & ~(bst_w & ~sbc_bst_b)) & ~flush_bst_inst; | |
987 | ||
988 | lsu_sbs_ctl_msff_ctl_macro__width_3 dff_bst_pend ( | |
989 | .scan_in(dff_bst_pend_scanin), | |
990 | .scan_out(dff_bst_pend_scanout), | |
991 | .l1clk (l1clk_pm1), | |
992 | .din ({bst_pend_in, sbc_bst_b,sbc_blk_inst_b}), | |
993 | .dout ({bst_pend_out,bst_w, blk_inst_w}), | |
994 | .siclk(siclk), | |
995 | .soclk(soclk) | |
996 | ); | |
997 | ||
998 | assign bst_pend = (stb_alloc_w & blk_inst_w & ~flush_w) | bst_pend_out; | |
999 | ||
1000 | assign sbs_bst_req = bst_pend & ~bst_w & ~|(stb_state_vld[7:0]); | |
1001 | //assign sbs_bst_req = |(dec_stb_rptr[7:0] & ~stb_state_vld[7:0] & ~{stb_state_vld[6:0],stb_state_vld[7]} & stb_state_mem[7:0] & stb_state_cas[7:0]); | |
1002 | ||
1003 | // If an error occurs on any one of the 8 FRF reads, kill the entire bst | |
1004 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_bst_err ( | |
1005 | .scan_in(dff_bst_err_scanin), | |
1006 | .scan_out(dff_bst_err_scanout), | |
1007 | .l1clk (l1clk_pm1), | |
1008 | .din (bst_err_next), | |
1009 | .dout (bst_err), | |
1010 | .siclk(siclk), | |
1011 | .soclk(soclk) | |
1012 | ); | |
1013 | ||
1014 | assign bst_err_next = sbc_bst_b & (bst_err | sbc_fgu_ecc_b | sbc_bst_rd_err); | |
1015 | assign bst_kill = bst_w & ~sbc_bst_in_prog_b & bst_err; | |
1016 | ||
1017 | //////////////////////////////////////////////////////////////////////////////// | |
1018 | // RMO store counting | |
1019 | // Count the number of RMO stores outstanding to the L2. The store buffer is | |
1020 | // not considered empty until all entries are dequeued AND there are no outstanding | |
1021 | // RMO stores. | |
1022 | // The counter is incremented in P5 when an RMO store is selected for issue | |
1023 | // The counter is decremented when the ack comes back from L2 | |
1024 | //////////////////////////////////////////////////////////////////////////////// | |
1025 | ||
1026 | assign rmo_count_dec[4:0] = rmo_count[4:0] - 5'b00001; | |
1027 | ||
1028 | assign rmo_st_commit_p3 = sbs_rmo_st & (sbc_st_sel_p3 & pic_st_sel_p3); | |
1029 | ||
1030 | assign rmo_count_in[4:0] = cic_rmo_dequeue ? rmo_count_dec[4:0] : rmo_count[4:0]; | |
1031 | ||
1032 | assign blk_st_commit_p3 = sbs_blk_st & (sbc_st_sel_p3 & pic_st_sel_p3); | |
1033 | ||
1034 | lsu_sbs_ctl_msff_ctl_macro__width_7 dff_rmo_count ( | |
1035 | .scan_in(dff_rmo_count_scanin), | |
1036 | .scan_out(dff_rmo_count_scanout), | |
1037 | .l1clk (l1clk_pm1), | |
1038 | .din ({rmo_count_in[4:0], rmo_st_commit_p3,blk_st_commit_p3}), | |
1039 | .dout ({rmo_count_out[4:0],rmo_st_commit_p4,blk_st_commit_p4}), | |
1040 | .siclk(siclk), | |
1041 | .soclk(soclk) | |
1042 | ); | |
1043 | ||
1044 | lsu_sbs_ctl_msff_ctl_macro__width_1 dff_rmo_commit ( | |
1045 | .scan_in(dff_rmo_commit_scanin), | |
1046 | .scan_out(dff_rmo_commit_scanout), | |
1047 | .din (rmo_st_commit_p4), | |
1048 | .dout (rmo_st_commit_p5), | |
1049 | .l1clk(l1clk), | |
1050 | .siclk(siclk), | |
1051 | .soclk(soclk) | |
1052 | ); | |
1053 | ||
1054 | assign rmo_commit_p5 = rmo_st_commit_p5 & ~kill_store_p5; | |
1055 | assign rmo_count[4:0] = rmo_count_out[4:0] + {4'b0000,rmo_commit_p5}; | |
1056 | ||
1057 | // 0in overflow -var rmo_count[4:0] -message "rmo counter overflow" | |
1058 | // 0in underflow -var rmo_count[4:0] -message "rmo counter underflow" | |
1059 | ||
1060 | assign sbs_rmo_st_p4 = rmo_st_commit_p4; | |
1061 | assign sbs_blk_st_p4 = blk_st_commit_p4; | |
1062 | ||
1063 | //////////////////////////////////////////////////////////////////////////////// | |
1064 | // Tracking of partial stores with TTE.IE=1 | |
1065 | // Because the byte mask is written to the CAM in B, but the TTE is not read until | |
1066 | // B, a partial store instruction with TTE.IE=1 will have it's stored byte mask | |
1067 | // with the wrong endianess. We need to indicate when this store is issuing so | |
1068 | // that the mask can be reversed. | |
1069 | //////////////////////////////////////////////////////////////////////////////// | |
1070 | ||
1071 | assign pst_ie_b = dcc_pst_asi_b & stb_cam_wvld_b & tlb_tte_ie_b & sbc_tte_vld_b; | |
1072 | ||
1073 | lsu_sbs_ctl_msff_ctl_macro__width_2 dff_pst_ie ( | |
1074 | .scan_in(dff_pst_ie_scanin), | |
1075 | .scan_out(dff_pst_ie_scanout), | |
1076 | .l1clk (l1clk_pm1), | |
1077 | .din ({pst_ie_b,pst_ie_in}), | |
1078 | .dout ({pst_ie_w,pst_ie}), | |
1079 | .siclk(siclk), | |
1080 | .soclk(soclk) | |
1081 | ); | |
1082 | ||
1083 | assign pst_ie_in = (pst_ie_w & ~flush_w) | (pst_ie & ~sbs_pcx_pst_ie_p4); | |
1084 | ||
1085 | assign sbs_pcx_pst_ie_p4 = pst_ie & sbs_last_entry & st_commit_p4; | |
1086 | ||
1087 | //////////////////////////////////////////////////////////////////////////////// | |
1088 | // Instruction type storage | |
1089 | // The type of store is held here. All "non-standard" stores are synchronizing, | |
1090 | // so this value is only valid when reading the last entry in the stb | |
1091 | // ASI - 00=ASI, 01=SR, 10=PR, 11=HPR | |
1092 | // mem - 00=store, 01=CAS, 10=unused, 11=SWAP | |
1093 | ||
1094 | assign st_type_in[1:0] = lsu_stb_alloc ? dcc_st_rq_type_w[1:0] : st_type[1:0]; | |
1095 | ||
1096 | lsu_sbs_ctl_msff_ctl_macro__width_2 dff_st_type ( | |
1097 | .scan_in(dff_st_type_scanin), | |
1098 | .scan_out(dff_st_type_scanout), | |
1099 | .l1clk (l1clk_pm1), | |
1100 | .din (st_type_in[1:0]), | |
1101 | .dout (st_type[1:0]), | |
1102 | .siclk(siclk), | |
1103 | .soclk(soclk) | |
1104 | ); | |
1105 | ||
1106 | assign sbs_st_type[1:0] = st_type[1:0] & {2{sbs_last_entry}}; | |
1107 | ||
1108 | //////////////////////////////////////////////////////////////////////////////// | |
1109 | // Cleanup for store buffer flush | |
1110 | // Once all stores have been killed due to a fatal error, the pick counters | |
1111 | // must be cleared and the dqptr reset. | |
1112 | ||
1113 | assign stb_flush_set = kill_store_p5; | |
1114 | assign stb_flush_clr = stb_empty & ~bst_pend & ~(sbc_cam_wvld_m | stb_cam_wvld_b | stb_alloc_w); | |
1115 | assign stb_flush_in = (stb_flush_set | stb_flush_state) & ~stb_flush_clr; | |
1116 | ||
1117 | lsu_sbs_ctl_msff_ctl_macro__width_2 dff_stb_flush ( | |
1118 | .scan_in(dff_stb_flush_scanin), | |
1119 | .scan_out(dff_stb_flush_scanout), | |
1120 | .din ({stb_flush_in ,((stb_flush_state | stb_flush_set) & stb_flush_clr)}), | |
1121 | .dout ({stb_flush_state,stb_flush_done}), | |
1122 | .l1clk(l1clk), | |
1123 | .siclk(siclk), | |
1124 | .soclk(soclk) | |
1125 | ); | |
1126 | ||
1127 | assign block_store_kill = bst_kill | stb_flush_done; | |
1128 | ||
1129 | ||
1130 | lsu_sbs_ctl_spare_ctl_macro__num_3 spares ( | |
1131 | .scan_in(spares_scanin), | |
1132 | .scan_out(spares_scanout), | |
1133 | .l1clk (l1clk), | |
1134 | .siclk(siclk), | |
1135 | .soclk(soclk) | |
1136 | ); | |
1137 | ||
1138 | supply0 vss; | |
1139 | supply1 vdd; | |
1140 | // fixscan start: | |
1141 | assign dff_flush_b_scanin = scan_in ; | |
1142 | assign dff_flush_w_scanin = dff_flush_b_scanout ; | |
1143 | assign dff_cam_wvld_b_scanin = dff_flush_w_scanout ; | |
1144 | assign dff_st_dq_scanin = dff_cam_wvld_b_scanout ; | |
1145 | assign dff_rptr_scanin = dff_st_dq_scanout ; | |
1146 | assign dff_wptr_scanin = dff_rptr_scanout ; | |
1147 | assign dff_wptr_b_scanin = dff_wptr_scanout ; | |
1148 | assign dff_wptr_w_scanin = dff_wptr_b_scanout ; | |
1149 | assign dff_dqptr_scanin = dff_wptr_w_scanout ; | |
1150 | assign dff_stb_vld_scanin = dff_dqptr_scanout ; | |
1151 | assign dff_stb_alloc_w_scanin = dff_stb_vld_scanout ; | |
1152 | assign dff_st_commit_p4_scanin = dff_stb_alloc_w_scanout ; | |
1153 | assign dff_stb_ced_scanin = dff_st_commit_p4_scanout ; | |
1154 | assign dff_ackptr_scanin = dff_stb_ced_scanout ; | |
1155 | assign dff_stb_ack_scanin = dff_ackptr_scanout ; | |
1156 | assign dff_asi_w_scanin = dff_stb_ack_scanout ; | |
1157 | assign dff_asi_pipe_scanin = dff_asi_w_scanout ; | |
1158 | assign dff_state_0_scanin = dff_asi_pipe_scanout ; | |
1159 | assign dff_state_1_scanin = dff_state_0_scanout ; | |
1160 | assign dff_state_2_scanin = dff_state_1_scanout ; | |
1161 | assign dff_state_3_scanin = dff_state_2_scanout ; | |
1162 | assign dff_state_4_scanin = dff_state_3_scanout ; | |
1163 | assign dff_state_5_scanin = dff_state_4_scanout ; | |
1164 | assign dff_state_6_scanin = dff_state_5_scanout ; | |
1165 | assign dff_state_7_scanin = dff_state_6_scanout ; | |
1166 | assign dff_sync_state_scanin = dff_state_7_scanout ; | |
1167 | assign dff_sbs_sync_scanin = dff_sync_state_scanout ; | |
1168 | assign dff_bst_pend_scanin = dff_sbs_sync_scanout ; | |
1169 | assign dff_bst_err_scanin = dff_bst_pend_scanout ; | |
1170 | assign dff_rmo_count_scanin = dff_bst_err_scanout ; | |
1171 | assign dff_rmo_commit_scanin = dff_rmo_count_scanout ; | |
1172 | assign dff_pst_ie_scanin = dff_rmo_commit_scanout ; | |
1173 | assign dff_st_type_scanin = dff_pst_ie_scanout ; | |
1174 | assign dff_stb_flush_scanin = dff_st_type_scanout ; | |
1175 | assign spares_scanin = dff_stb_flush_scanout ; | |
1176 | assign scan_out = spares_scanout ; | |
1177 | // fixscan end: | |
1178 | endmodule | |
1179 | ||
1180 | ||
1181 | ||
1182 | ||
1183 | ||
1184 | ||
1185 | // any PARAMS parms go into naming of macro | |
1186 | ||
1187 | module lsu_sbs_ctl_l1clkhdr_ctl_macro ( | |
1188 | l2clk, | |
1189 | l1en, | |
1190 | pce_ov, | |
1191 | stop, | |
1192 | se, | |
1193 | l1clk); | |
1194 | ||
1195 | ||
1196 | input l2clk; | |
1197 | input l1en; | |
1198 | input pce_ov; | |
1199 | input stop; | |
1200 | input se; | |
1201 | output l1clk; | |
1202 | ||
1203 | ||
1204 | ||
1205 | ||
1206 | ||
1207 | cl_sc1_l1hdr_8x c_0 ( | |
1208 | ||
1209 | ||
1210 | .l2clk(l2clk), | |
1211 | .pce(l1en), | |
1212 | .l1clk(l1clk), | |
1213 | .se(se), | |
1214 | .pce_ov(pce_ov), | |
1215 | .stop(stop) | |
1216 | ); | |
1217 | ||
1218 | ||
1219 | ||
1220 | endmodule | |
1221 | ||
1222 | ||
1223 | ||
1224 | ||
1225 | ||
1226 | ||
1227 | ||
1228 | ||
1229 | ||
1230 | ||
1231 | ||
1232 | ||
1233 | ||
1234 | // any PARAMS parms go into naming of macro | |
1235 | ||
1236 | module lsu_sbs_ctl_msff_ctl_macro__width_1 ( | |
1237 | din, | |
1238 | l1clk, | |
1239 | scan_in, | |
1240 | siclk, | |
1241 | soclk, | |
1242 | dout, | |
1243 | scan_out); | |
1244 | wire [0:0] fdin; | |
1245 | ||
1246 | input [0:0] din; | |
1247 | input l1clk; | |
1248 | input scan_in; | |
1249 | ||
1250 | ||
1251 | input siclk; | |
1252 | input soclk; | |
1253 | ||
1254 | output [0:0] dout; | |
1255 | output scan_out; | |
1256 | assign fdin[0:0] = din[0:0]; | |
1257 | ||
1258 | ||
1259 | ||
1260 | ||
1261 | ||
1262 | ||
1263 | dff #(1) d0_0 ( | |
1264 | .l1clk(l1clk), | |
1265 | .siclk(siclk), | |
1266 | .soclk(soclk), | |
1267 | .d(fdin[0:0]), | |
1268 | .si(scan_in), | |
1269 | .so(scan_out), | |
1270 | .q(dout[0:0]) | |
1271 | ); | |
1272 | ||
1273 | ||
1274 | ||
1275 | ||
1276 | ||
1277 | ||
1278 | ||
1279 | ||
1280 | ||
1281 | ||
1282 | ||
1283 | ||
1284 | endmodule | |
1285 | ||
1286 | ||
1287 | ||
1288 | ||
1289 | ||
1290 | ||
1291 | ||
1292 | ||
1293 | ||
1294 | ||
1295 | ||
1296 | ||
1297 | ||
1298 | // any PARAMS parms go into naming of macro | |
1299 | ||
1300 | module lsu_sbs_ctl_msff_ctl_macro__width_3 ( | |
1301 | din, | |
1302 | l1clk, | |
1303 | scan_in, | |
1304 | siclk, | |
1305 | soclk, | |
1306 | dout, | |
1307 | scan_out); | |
1308 | wire [2:0] fdin; | |
1309 | wire [1:0] so; | |
1310 | ||
1311 | input [2:0] din; | |
1312 | input l1clk; | |
1313 | input scan_in; | |
1314 | ||
1315 | ||
1316 | input siclk; | |
1317 | input soclk; | |
1318 | ||
1319 | output [2:0] dout; | |
1320 | output scan_out; | |
1321 | assign fdin[2:0] = din[2:0]; | |
1322 | ||
1323 | ||
1324 | ||
1325 | ||
1326 | ||
1327 | ||
1328 | dff #(3) d0_0 ( | |
1329 | .l1clk(l1clk), | |
1330 | .siclk(siclk), | |
1331 | .soclk(soclk), | |
1332 | .d(fdin[2:0]), | |
1333 | .si({scan_in,so[1:0]}), | |
1334 | .so({so[1:0],scan_out}), | |
1335 | .q(dout[2:0]) | |
1336 | ); | |
1337 | ||
1338 | ||
1339 | ||
1340 | ||
1341 | ||
1342 | ||
1343 | ||
1344 | ||
1345 | ||
1346 | ||
1347 | ||
1348 | ||
1349 | endmodule | |
1350 | ||
1351 | ||
1352 | ||
1353 | ||
1354 | ||
1355 | ||
1356 | ||
1357 | ||
1358 | ||
1359 | ||
1360 | ||
1361 | ||
1362 | ||
1363 | // any PARAMS parms go into naming of macro | |
1364 | ||
1365 | module lsu_sbs_ctl_msff_ctl_macro__width_4 ( | |
1366 | din, | |
1367 | l1clk, | |
1368 | scan_in, | |
1369 | siclk, | |
1370 | soclk, | |
1371 | dout, | |
1372 | scan_out); | |
1373 | wire [3:0] fdin; | |
1374 | wire [2:0] so; | |
1375 | ||
1376 | input [3:0] din; | |
1377 | input l1clk; | |
1378 | input scan_in; | |
1379 | ||
1380 | ||
1381 | input siclk; | |
1382 | input soclk; | |
1383 | ||
1384 | output [3:0] dout; | |
1385 | output scan_out; | |
1386 | assign fdin[3:0] = din[3:0]; | |
1387 | ||
1388 | ||
1389 | ||
1390 | ||
1391 | ||
1392 | ||
1393 | dff #(4) d0_0 ( | |
1394 | .l1clk(l1clk), | |
1395 | .siclk(siclk), | |
1396 | .soclk(soclk), | |
1397 | .d(fdin[3:0]), | |
1398 | .si({scan_in,so[2:0]}), | |
1399 | .so({so[2:0],scan_out}), | |
1400 | .q(dout[3:0]) | |
1401 | ); | |
1402 | ||
1403 | ||
1404 | ||
1405 | ||
1406 | ||
1407 | ||
1408 | ||
1409 | ||
1410 | ||
1411 | ||
1412 | ||
1413 | ||
1414 | endmodule | |
1415 | ||
1416 | ||
1417 | ||
1418 | ||
1419 | ||
1420 | ||
1421 | ||
1422 | ||
1423 | ||
1424 | ||
1425 | ||
1426 | ||
1427 | ||
1428 | // any PARAMS parms go into naming of macro | |
1429 | ||
1430 | module lsu_sbs_ctl_msff_ctl_macro__width_9 ( | |
1431 | din, | |
1432 | l1clk, | |
1433 | scan_in, | |
1434 | siclk, | |
1435 | soclk, | |
1436 | dout, | |
1437 | scan_out); | |
1438 | wire [8:0] fdin; | |
1439 | wire [7:0] so; | |
1440 | ||
1441 | input [8:0] din; | |
1442 | input l1clk; | |
1443 | input scan_in; | |
1444 | ||
1445 | ||
1446 | input siclk; | |
1447 | input soclk; | |
1448 | ||
1449 | output [8:0] dout; | |
1450 | output scan_out; | |
1451 | assign fdin[8:0] = din[8:0]; | |
1452 | ||
1453 | ||
1454 | ||
1455 | ||
1456 | ||
1457 | ||
1458 | dff #(9) d0_0 ( | |
1459 | .l1clk(l1clk), | |
1460 | .siclk(siclk), | |
1461 | .soclk(soclk), | |
1462 | .d(fdin[8:0]), | |
1463 | .si({scan_in,so[7:0]}), | |
1464 | .so({so[7:0],scan_out}), | |
1465 | .q(dout[8:0]) | |
1466 | ); | |
1467 | ||
1468 | ||
1469 | ||
1470 | ||
1471 | ||
1472 | ||
1473 | ||
1474 | ||
1475 | ||
1476 | ||
1477 | ||
1478 | ||
1479 | endmodule | |
1480 | ||
1481 | ||
1482 | ||
1483 | ||
1484 | ||
1485 | ||
1486 | ||
1487 | ||
1488 | ||
1489 | ||
1490 | ||
1491 | ||
1492 | ||
1493 | // any PARAMS parms go into naming of macro | |
1494 | ||
1495 | module lsu_sbs_ctl_msff_ctl_macro__width_8 ( | |
1496 | din, | |
1497 | l1clk, | |
1498 | scan_in, | |
1499 | siclk, | |
1500 | soclk, | |
1501 | dout, | |
1502 | scan_out); | |
1503 | wire [7:0] fdin; | |
1504 | wire [6:0] so; | |
1505 | ||
1506 | input [7:0] din; | |
1507 | input l1clk; | |
1508 | input scan_in; | |
1509 | ||
1510 | ||
1511 | input siclk; | |
1512 | input soclk; | |
1513 | ||
1514 | output [7:0] dout; | |
1515 | output scan_out; | |
1516 | assign fdin[7:0] = din[7:0]; | |
1517 | ||
1518 | ||
1519 | ||
1520 | ||
1521 | ||
1522 | ||
1523 | dff #(8) d0_0 ( | |
1524 | .l1clk(l1clk), | |
1525 | .siclk(siclk), | |
1526 | .soclk(soclk), | |
1527 | .d(fdin[7:0]), | |
1528 | .si({scan_in,so[6:0]}), | |
1529 | .so({so[6:0],scan_out}), | |
1530 | .q(dout[7:0]) | |
1531 | ); | |
1532 | ||
1533 | ||
1534 | ||
1535 | ||
1536 | ||
1537 | ||
1538 | ||
1539 | ||
1540 | ||
1541 | ||
1542 | ||
1543 | ||
1544 | endmodule | |
1545 | ||
1546 | ||
1547 | ||
1548 | ||
1549 | ||
1550 | ||
1551 | ||
1552 | ||
1553 | ||
1554 | ||
1555 | ||
1556 | ||
1557 | ||
1558 | // any PARAMS parms go into naming of macro | |
1559 | ||
1560 | module lsu_sbs_ctl_msff_ctl_macro__width_7 ( | |
1561 | din, | |
1562 | l1clk, | |
1563 | scan_in, | |
1564 | siclk, | |
1565 | soclk, | |
1566 | dout, | |
1567 | scan_out); | |
1568 | wire [6:0] fdin; | |
1569 | wire [5:0] so; | |
1570 | ||
1571 | input [6:0] din; | |
1572 | input l1clk; | |
1573 | input scan_in; | |
1574 | ||
1575 | ||
1576 | input siclk; | |
1577 | input soclk; | |
1578 | ||
1579 | output [6:0] dout; | |
1580 | output scan_out; | |
1581 | assign fdin[6:0] = din[6:0]; | |
1582 | ||
1583 | ||
1584 | ||
1585 | ||
1586 | ||
1587 | ||
1588 | dff #(7) d0_0 ( | |
1589 | .l1clk(l1clk), | |
1590 | .siclk(siclk), | |
1591 | .soclk(soclk), | |
1592 | .d(fdin[6:0]), | |
1593 | .si({scan_in,so[5:0]}), | |
1594 | .so({so[5:0],scan_out}), | |
1595 | .q(dout[6:0]) | |
1596 | ); | |
1597 | ||
1598 | ||
1599 | ||
1600 | ||
1601 | ||
1602 | ||
1603 | ||
1604 | ||
1605 | ||
1606 | ||
1607 | ||
1608 | ||
1609 | endmodule | |
1610 | ||
1611 | ||
1612 | ||
1613 | ||
1614 | ||
1615 | ||
1616 | ||
1617 | ||
1618 | ||
1619 | ||
1620 | ||
1621 | ||
1622 | ||
1623 | // any PARAMS parms go into naming of macro | |
1624 | ||
1625 | module lsu_sbs_ctl_msff_ctl_macro__width_2 ( | |
1626 | din, | |
1627 | l1clk, | |
1628 | scan_in, | |
1629 | siclk, | |
1630 | soclk, | |
1631 | dout, | |
1632 | scan_out); | |
1633 | wire [1:0] fdin; | |
1634 | wire [0:0] so; | |
1635 | ||
1636 | input [1:0] din; | |
1637 | input l1clk; | |
1638 | input scan_in; | |
1639 | ||
1640 | ||
1641 | input siclk; | |
1642 | input soclk; | |
1643 | ||
1644 | output [1:0] dout; | |
1645 | output scan_out; | |
1646 | assign fdin[1:0] = din[1:0]; | |
1647 | ||
1648 | ||
1649 | ||
1650 | ||
1651 | ||
1652 | ||
1653 | dff #(2) d0_0 ( | |
1654 | .l1clk(l1clk), | |
1655 | .siclk(siclk), | |
1656 | .soclk(soclk), | |
1657 | .d(fdin[1:0]), | |
1658 | .si({scan_in,so[0:0]}), | |
1659 | .so({so[0:0],scan_out}), | |
1660 | .q(dout[1:0]) | |
1661 | ); | |
1662 | ||
1663 | ||
1664 | ||
1665 | ||
1666 | ||
1667 | ||
1668 | ||
1669 | ||
1670 | ||
1671 | ||
1672 | ||
1673 | ||
1674 | endmodule | |
1675 | ||
1676 | ||
1677 | ||
1678 | ||
1679 | ||
1680 | ||
1681 | ||
1682 | ||
1683 | ||
1684 | // Description: Spare gate macro for control blocks | |
1685 | // | |
1686 | // Param num controls the number of times the macro is added | |
1687 | // flops=0 can be used to use only combination spare logic | |
1688 | ||
1689 | ||
1690 | module lsu_sbs_ctl_spare_ctl_macro__num_3 ( | |
1691 | l1clk, | |
1692 | scan_in, | |
1693 | siclk, | |
1694 | soclk, | |
1695 | scan_out); | |
1696 | wire si_0; | |
1697 | wire so_0; | |
1698 | wire spare0_flop_unused; | |
1699 | wire spare0_buf_32x_unused; | |
1700 | wire spare0_nand3_8x_unused; | |
1701 | wire spare0_inv_8x_unused; | |
1702 | wire spare0_aoi22_4x_unused; | |
1703 | wire spare0_buf_8x_unused; | |
1704 | wire spare0_oai22_4x_unused; | |
1705 | wire spare0_inv_16x_unused; | |
1706 | wire spare0_nand2_16x_unused; | |
1707 | wire spare0_nor3_4x_unused; | |
1708 | wire spare0_nand2_8x_unused; | |
1709 | wire spare0_buf_16x_unused; | |
1710 | wire spare0_nor2_16x_unused; | |
1711 | wire spare0_inv_32x_unused; | |
1712 | wire si_1; | |
1713 | wire so_1; | |
1714 | wire spare1_flop_unused; | |
1715 | wire spare1_buf_32x_unused; | |
1716 | wire spare1_nand3_8x_unused; | |
1717 | wire spare1_inv_8x_unused; | |
1718 | wire spare1_aoi22_4x_unused; | |
1719 | wire spare1_buf_8x_unused; | |
1720 | wire spare1_oai22_4x_unused; | |
1721 | wire spare1_inv_16x_unused; | |
1722 | wire spare1_nand2_16x_unused; | |
1723 | wire spare1_nor3_4x_unused; | |
1724 | wire spare1_nand2_8x_unused; | |
1725 | wire spare1_buf_16x_unused; | |
1726 | wire spare1_nor2_16x_unused; | |
1727 | wire spare1_inv_32x_unused; | |
1728 | wire si_2; | |
1729 | wire so_2; | |
1730 | wire spare2_flop_unused; | |
1731 | wire spare2_buf_32x_unused; | |
1732 | wire spare2_nand3_8x_unused; | |
1733 | wire spare2_inv_8x_unused; | |
1734 | wire spare2_aoi22_4x_unused; | |
1735 | wire spare2_buf_8x_unused; | |
1736 | wire spare2_oai22_4x_unused; | |
1737 | wire spare2_inv_16x_unused; | |
1738 | wire spare2_nand2_16x_unused; | |
1739 | wire spare2_nor3_4x_unused; | |
1740 | wire spare2_nand2_8x_unused; | |
1741 | wire spare2_buf_16x_unused; | |
1742 | wire spare2_nor2_16x_unused; | |
1743 | wire spare2_inv_32x_unused; | |
1744 | ||
1745 | ||
1746 | input l1clk; | |
1747 | input scan_in; | |
1748 | input siclk; | |
1749 | input soclk; | |
1750 | output scan_out; | |
1751 | ||
1752 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
1753 | .siclk(siclk), | |
1754 | .soclk(soclk), | |
1755 | .si(si_0), | |
1756 | .so(so_0), | |
1757 | .d(1'b0), | |
1758 | .q(spare0_flop_unused)); | |
1759 | assign si_0 = scan_in; | |
1760 | ||
1761 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
1762 | .out(spare0_buf_32x_unused)); | |
1763 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
1764 | .in1(1'b1), | |
1765 | .in2(1'b1), | |
1766 | .out(spare0_nand3_8x_unused)); | |
1767 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
1768 | .out(spare0_inv_8x_unused)); | |
1769 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
1770 | .in01(1'b1), | |
1771 | .in10(1'b1), | |
1772 | .in11(1'b1), | |
1773 | .out(spare0_aoi22_4x_unused)); | |
1774 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
1775 | .out(spare0_buf_8x_unused)); | |
1776 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
1777 | .in01(1'b1), | |
1778 | .in10(1'b1), | |
1779 | .in11(1'b1), | |
1780 | .out(spare0_oai22_4x_unused)); | |
1781 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
1782 | .out(spare0_inv_16x_unused)); | |
1783 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
1784 | .in1(1'b1), | |
1785 | .out(spare0_nand2_16x_unused)); | |
1786 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
1787 | .in1(1'b0), | |
1788 | .in2(1'b0), | |
1789 | .out(spare0_nor3_4x_unused)); | |
1790 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
1791 | .in1(1'b1), | |
1792 | .out(spare0_nand2_8x_unused)); | |
1793 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
1794 | .out(spare0_buf_16x_unused)); | |
1795 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
1796 | .in1(1'b0), | |
1797 | .out(spare0_nor2_16x_unused)); | |
1798 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
1799 | .out(spare0_inv_32x_unused)); | |
1800 | ||
1801 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
1802 | .siclk(siclk), | |
1803 | .soclk(soclk), | |
1804 | .si(si_1), | |
1805 | .so(so_1), | |
1806 | .d(1'b0), | |
1807 | .q(spare1_flop_unused)); | |
1808 | assign si_1 = so_0; | |
1809 | ||
1810 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
1811 | .out(spare1_buf_32x_unused)); | |
1812 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
1813 | .in1(1'b1), | |
1814 | .in2(1'b1), | |
1815 | .out(spare1_nand3_8x_unused)); | |
1816 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
1817 | .out(spare1_inv_8x_unused)); | |
1818 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
1819 | .in01(1'b1), | |
1820 | .in10(1'b1), | |
1821 | .in11(1'b1), | |
1822 | .out(spare1_aoi22_4x_unused)); | |
1823 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
1824 | .out(spare1_buf_8x_unused)); | |
1825 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
1826 | .in01(1'b1), | |
1827 | .in10(1'b1), | |
1828 | .in11(1'b1), | |
1829 | .out(spare1_oai22_4x_unused)); | |
1830 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
1831 | .out(spare1_inv_16x_unused)); | |
1832 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
1833 | .in1(1'b1), | |
1834 | .out(spare1_nand2_16x_unused)); | |
1835 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
1836 | .in1(1'b0), | |
1837 | .in2(1'b0), | |
1838 | .out(spare1_nor3_4x_unused)); | |
1839 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
1840 | .in1(1'b1), | |
1841 | .out(spare1_nand2_8x_unused)); | |
1842 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
1843 | .out(spare1_buf_16x_unused)); | |
1844 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
1845 | .in1(1'b0), | |
1846 | .out(spare1_nor2_16x_unused)); | |
1847 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
1848 | .out(spare1_inv_32x_unused)); | |
1849 | ||
1850 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
1851 | .siclk(siclk), | |
1852 | .soclk(soclk), | |
1853 | .si(si_2), | |
1854 | .so(so_2), | |
1855 | .d(1'b0), | |
1856 | .q(spare2_flop_unused)); | |
1857 | assign si_2 = so_1; | |
1858 | ||
1859 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
1860 | .out(spare2_buf_32x_unused)); | |
1861 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
1862 | .in1(1'b1), | |
1863 | .in2(1'b1), | |
1864 | .out(spare2_nand3_8x_unused)); | |
1865 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
1866 | .out(spare2_inv_8x_unused)); | |
1867 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
1868 | .in01(1'b1), | |
1869 | .in10(1'b1), | |
1870 | .in11(1'b1), | |
1871 | .out(spare2_aoi22_4x_unused)); | |
1872 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
1873 | .out(spare2_buf_8x_unused)); | |
1874 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
1875 | .in01(1'b1), | |
1876 | .in10(1'b1), | |
1877 | .in11(1'b1), | |
1878 | .out(spare2_oai22_4x_unused)); | |
1879 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
1880 | .out(spare2_inv_16x_unused)); | |
1881 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
1882 | .in1(1'b1), | |
1883 | .out(spare2_nand2_16x_unused)); | |
1884 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
1885 | .in1(1'b0), | |
1886 | .in2(1'b0), | |
1887 | .out(spare2_nor3_4x_unused)); | |
1888 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
1889 | .in1(1'b1), | |
1890 | .out(spare2_nand2_8x_unused)); | |
1891 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
1892 | .out(spare2_buf_16x_unused)); | |
1893 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
1894 | .in1(1'b0), | |
1895 | .out(spare2_nor2_16x_unused)); | |
1896 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
1897 | .out(spare2_inv_32x_unused)); | |
1898 | assign scan_out = so_2; | |
1899 | ||
1900 | ||
1901 | ||
1902 | endmodule | |
1903 |