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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_tgc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_tgc_ctl ( | |
36 | dva_valid_m, | |
37 | dva_valid2_m, | |
38 | lsu_va_m, | |
39 | lsu_va_b12to11_m, | |
40 | exu_lsu_address_e, | |
41 | dcc_ld_inst_vld_m, | |
42 | dcc_dva_din_e, | |
43 | dcc_dva_din2_e, | |
44 | tgd_bist_compare, | |
45 | tgc_cache_way_vld_m, | |
46 | tgc_cache_way_vld2_m, | |
47 | tgc_verr_b, | |
48 | tgc_way_sel_m, | |
49 | tgc_dva_rd_addr_e, | |
50 | tgc_dva_din, | |
51 | lsu_mbi_dva_fail, | |
52 | lsu_mbi_dta_fail, | |
53 | lsu_mbi_dtb_fail, | |
54 | mbi_run, | |
55 | mbi_cambist_run, | |
56 | mbi_wdata, | |
57 | mbi_cmpsel, | |
58 | mbi_addr, | |
59 | mbi_dta_read_en, | |
60 | mbi_dva_read_en, | |
61 | mbi_dtb_read_en, | |
62 | bist_wdata_1, | |
63 | bist_cmp_data, | |
64 | bist_cmpsel_1, | |
65 | bist_cmpsel_2, | |
66 | bist_addr_1, | |
67 | bist_dta_cmp_en, | |
68 | l2clk, | |
69 | scan_in, | |
70 | tcu_pce_ov, | |
71 | tcu_scan_en, | |
72 | spc_aclk, | |
73 | spc_bclk, | |
74 | scan_out, | |
75 | lsu_lsu_pmen); | |
76 | wire se; | |
77 | wire pce_ov; | |
78 | wire stop; | |
79 | wire siclk; | |
80 | wire soclk; | |
81 | wire ld_vld_m_clken; | |
82 | wire tgc_mbi_run; | |
83 | wire l1clk_pm1; | |
84 | wire [3:0] verr_m; | |
85 | wire dff_way_vld_scanin; | |
86 | wire dff_way_vld_scanout; | |
87 | wire [8:5] local_bist_addr_1; | |
88 | wire dva_fail; | |
89 | wire bist_dva_cmp_en; | |
90 | wire dta_fail; | |
91 | wire dtb_fail; | |
92 | wire bist_dtb_cmp_en; | |
93 | wire dff_bist_fail_scanin; | |
94 | wire dff_bist_fail_scanout; | |
95 | wire [7:0] wdata_or_addr; | |
96 | wire dff_bist_scanin; | |
97 | wire dff_bist_scanout; | |
98 | wire bist_dta_rd_1; | |
99 | wire dtb_read_en; | |
100 | wire bist_dtb_rd_1; | |
101 | wire [7:0] cmp_data_in; | |
102 | wire bist_dta_rd_2; | |
103 | wire bist_dtb_rd_2; | |
104 | wire [7:0] bist_wdata_2; | |
105 | wire spares_scanin; | |
106 | wire spares_scanout; | |
107 | ||
108 | ||
109 | input [15:0] dva_valid_m; | |
110 | input [15:0] dva_valid2_m; // redundant copies | |
111 | ||
112 | input [5:4] lsu_va_m; | |
113 | input [12:11] lsu_va_b12to11_m; | |
114 | ||
115 | input [10:6] exu_lsu_address_e; | |
116 | ||
117 | input dcc_ld_inst_vld_m; | |
118 | input dcc_dva_din_e; | |
119 | input dcc_dva_din2_e; | |
120 | ||
121 | input tgd_bist_compare; | |
122 | ||
123 | output [3:0] tgc_cache_way_vld_m; | |
124 | output [3:0] tgc_cache_way_vld2_m; | |
125 | output [3:0] tgc_verr_b; | |
126 | output [1:0] tgc_way_sel_m; | |
127 | output [10:6] tgc_dva_rd_addr_e; | |
128 | output [31:0] tgc_dva_din; | |
129 | ||
130 | output lsu_mbi_dva_fail; | |
131 | output lsu_mbi_dta_fail; | |
132 | output lsu_mbi_dtb_fail; | |
133 | ||
134 | // BIST | |
135 | input mbi_run; | |
136 | input mbi_cambist_run; | |
137 | input [7:0] mbi_wdata; | |
138 | input [1:0] mbi_cmpsel; // encoded | |
139 | input [8:0] mbi_addr; | |
140 | input mbi_dta_read_en; | |
141 | input mbi_dva_read_en; | |
142 | input mbi_dtb_read_en; | |
143 | output [7:0] bist_wdata_1; | |
144 | output [7:0] bist_cmp_data; | |
145 | output [1:0] bist_cmpsel_1; | |
146 | output bist_cmpsel_2; | |
147 | output [8:5] bist_addr_1; | |
148 | output bist_dta_cmp_en; | |
149 | ||
150 | ||
151 | input l2clk; | |
152 | input scan_in; | |
153 | input tcu_pce_ov; // scan signals | |
154 | input tcu_scan_en; | |
155 | input spc_aclk; | |
156 | input spc_bclk; | |
157 | output scan_out; | |
158 | ||
159 | input lsu_lsu_pmen; | |
160 | ||
161 | // scan renames | |
162 | assign se = tcu_scan_en; | |
163 | assign pce_ov = tcu_pce_ov; | |
164 | assign stop = 1'b0; | |
165 | assign siclk = spc_aclk; | |
166 | assign soclk = spc_bclk; | |
167 | // end scan | |
168 | ||
169 | ////////////////////////////// | |
170 | // Clock headers | |
171 | ////////////////////////////// | |
172 | ||
173 | // Enable flops only when load is in M or during bist | |
174 | assign ld_vld_m_clken = dcc_ld_inst_vld_m | mbi_run | tgc_mbi_run | ~lsu_lsu_pmen; | |
175 | ||
176 | lsu_tgc_ctl_l1clkhdr_ctl_macro clkgen0 ( | |
177 | .l2clk (l2clk ), | |
178 | .l1en (ld_vld_m_clken ), | |
179 | .l1clk (l1clk_pm1 ), | |
180 | .pce_ov(pce_ov), | |
181 | .stop(stop), | |
182 | .se(se) | |
183 | ); | |
184 | ||
185 | ////////////////////////////// | |
186 | ||
187 | // Valid bit muxing | |
188 | ||
189 | assign tgc_cache_way_vld_m[3:0] = ({4{(lsu_va_m[5:4] == 2'b00)}} & dva_valid_m[3:0]) | | |
190 | ({4{(lsu_va_m[5:4] == 2'b01)}} & dva_valid_m[7:4]) | | |
191 | ({4{(lsu_va_m[5:4] == 2'b10)}} & dva_valid_m[11:8]) | | |
192 | ({4{(lsu_va_m[5:4] == 2'b11)}} & dva_valid_m[15:12]); | |
193 | ||
194 | assign tgc_cache_way_vld2_m[3:0] = ({4{(lsu_va_m[5:4] == 2'b00)}} & dva_valid2_m[3:0]) | | |
195 | ({4{(lsu_va_m[5:4] == 2'b01)}} & dva_valid2_m[7:4]) | | |
196 | ({4{(lsu_va_m[5:4] == 2'b10)}} & dva_valid2_m[11:8]) | | |
197 | ({4{(lsu_va_m[5:4] == 2'b11)}} & dva_valid2_m[15:12]); | |
198 | ||
199 | // Valid bit error detection | |
200 | ||
201 | assign verr_m[0] = tgc_cache_way_vld_m[0] ^ tgc_cache_way_vld2_m[0]; | |
202 | assign verr_m[1] = tgc_cache_way_vld_m[1] ^ tgc_cache_way_vld2_m[1]; | |
203 | assign verr_m[2] = tgc_cache_way_vld_m[2] ^ tgc_cache_way_vld2_m[2]; | |
204 | assign verr_m[3] = tgc_cache_way_vld_m[3] ^ tgc_cache_way_vld2_m[3]; | |
205 | ||
206 | lsu_tgc_ctl_msff_ctl_macro__width_4 dff_way_vld ( | |
207 | .scan_in(dff_way_vld_scanin), | |
208 | .scan_out(dff_way_vld_scanout), | |
209 | .din (verr_m[3:0]), | |
210 | .dout (tgc_verr_b[3:0]), | |
211 | .l1clk (l1clk_pm1), | |
212 | .siclk(siclk), | |
213 | .soclk(soclk) | |
214 | ); | |
215 | ||
216 | // Valid array data in | |
217 | ||
218 | assign tgc_dva_din[31:0] = tgc_mbi_run ? {4{mbi_wdata[7:0]}} : {{16{dcc_dva_din2_e}},{16{dcc_dva_din_e}}}; | |
219 | ||
220 | // This is the tag way select used for diagnostic and bist reads | |
221 | assign tgc_way_sel_m[1:0] = tgc_mbi_run ? local_bist_addr_1[8:7] : lsu_va_b12to11_m[12:11]; | |
222 | ||
223 | // BIST compare results | |
224 | assign dva_fail = bist_dva_cmp_en & ({dva_valid_m[15:0],dva_valid2_m[15:0]} != {4{bist_wdata_1[7:0]}}); | |
225 | assign dta_fail = bist_dta_cmp_en & ~tgd_bist_compare; | |
226 | assign dtb_fail = bist_dtb_cmp_en & ~tgd_bist_compare & ~mbi_cambist_run; | |
227 | ||
228 | lsu_tgc_ctl_msff_ctl_macro__width_3 dff_bist_fail ( | |
229 | .scan_in(dff_bist_fail_scanin), | |
230 | .scan_out(dff_bist_fail_scanout), | |
231 | .l1clk (l1clk_pm1), | |
232 | .din ({dta_fail, dtb_fail, dva_fail}), | |
233 | .dout ({lsu_mbi_dta_fail,lsu_mbi_dtb_fail,lsu_mbi_dva_fail}), | |
234 | .siclk(siclk), | |
235 | .soclk(soclk) | |
236 | ); | |
237 | ||
238 | // | |
239 | // Address muxing for DVA array | |
240 | // | |
241 | assign tgc_dva_rd_addr_e[10:6] = tgc_mbi_run ? mbi_addr[4:0] : exu_lsu_address_e[10:6]; | |
242 | ||
243 | //////////////////////////////////////////////////////////////////////////////// | |
244 | // Flops for bist signals | |
245 | ||
246 | assign wdata_or_addr[7:0] = mbi_cambist_run ? mbi_addr[7:0] : mbi_wdata[7:0]; | |
247 | ||
248 | lsu_tgc_ctl_msff_ctl_macro__width_38 dff_bist ( | |
249 | .scan_in(dff_bist_scanin), | |
250 | .scan_out(dff_bist_scanout), | |
251 | .l1clk (l1clk_pm1), | |
252 | .din ({mbi_run, | |
253 | mbi_dta_read_en, bist_dta_rd_1, | |
254 | mbi_dtb_read_en, dtb_read_en, | |
255 | bist_dtb_rd_1, mbi_dva_read_en, | |
256 | wdata_or_addr[7:0], bist_wdata_1[7:0], | |
257 | mbi_cmpsel[1:0], bist_cmpsel_1[0], | |
258 | mbi_addr[8:5], cmp_data_in[7:0] | |
259 | }), | |
260 | .dout ({tgc_mbi_run, | |
261 | bist_dta_rd_1, bist_dta_rd_2, | |
262 | dtb_read_en, bist_dtb_rd_1, | |
263 | bist_dtb_rd_2, bist_dva_cmp_en, | |
264 | bist_wdata_1[7:0], bist_wdata_2[7:0], | |
265 | bist_cmpsel_1[1:0], bist_cmpsel_2, | |
266 | local_bist_addr_1[8:5],bist_cmp_data[7:0] | |
267 | }), | |
268 | .siclk(siclk), | |
269 | .soclk(soclk) | |
270 | ); | |
271 | ||
272 | assign cmp_data_in[7:0] = bist_dtb_rd_1 ? bist_wdata_2[7:0] : bist_wdata_1[7:0]; | |
273 | ||
274 | assign bist_addr_1[8:5] = local_bist_addr_1[8:5]; | |
275 | assign bist_dta_cmp_en = bist_dta_rd_2; | |
276 | assign bist_dtb_cmp_en = bist_dtb_rd_2; | |
277 | ||
278 | ||
279 | lsu_tgc_ctl_spare_ctl_macro__num_1 spares ( | |
280 | .scan_in(spares_scanin), | |
281 | .scan_out(spares_scanout), | |
282 | .l1clk (l1clk_pm1), | |
283 | .siclk(siclk), | |
284 | .soclk(soclk) | |
285 | ); | |
286 | ||
287 | // fixscan start: | |
288 | assign dff_way_vld_scanin = scan_in ; | |
289 | assign dff_bist_fail_scanin = dff_way_vld_scanout ; | |
290 | assign dff_bist_scanin = dff_bist_fail_scanout ; | |
291 | assign spares_scanin = dff_bist_scanout ; | |
292 | assign scan_out = spares_scanout ; | |
293 | // fixscan end: | |
294 | endmodule | |
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | // any PARAMS parms go into naming of macro | |
302 | ||
303 | module lsu_tgc_ctl_l1clkhdr_ctl_macro ( | |
304 | l2clk, | |
305 | l1en, | |
306 | pce_ov, | |
307 | stop, | |
308 | se, | |
309 | l1clk); | |
310 | ||
311 | ||
312 | input l2clk; | |
313 | input l1en; | |
314 | input pce_ov; | |
315 | input stop; | |
316 | input se; | |
317 | output l1clk; | |
318 | ||
319 | ||
320 | ||
321 | ||
322 | ||
323 | cl_sc1_l1hdr_8x c_0 ( | |
324 | ||
325 | ||
326 | .l2clk(l2clk), | |
327 | .pce(l1en), | |
328 | .l1clk(l1clk), | |
329 | .se(se), | |
330 | .pce_ov(pce_ov), | |
331 | .stop(stop) | |
332 | ); | |
333 | ||
334 | ||
335 | ||
336 | endmodule | |
337 | ||
338 | ||
339 | ||
340 | ||
341 | ||
342 | ||
343 | ||
344 | ||
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | // any PARAMS parms go into naming of macro | |
351 | ||
352 | module lsu_tgc_ctl_msff_ctl_macro__width_4 ( | |
353 | din, | |
354 | l1clk, | |
355 | scan_in, | |
356 | siclk, | |
357 | soclk, | |
358 | dout, | |
359 | scan_out); | |
360 | wire [3:0] fdin; | |
361 | wire [2:0] so; | |
362 | ||
363 | input [3:0] din; | |
364 | input l1clk; | |
365 | input scan_in; | |
366 | ||
367 | ||
368 | input siclk; | |
369 | input soclk; | |
370 | ||
371 | output [3:0] dout; | |
372 | output scan_out; | |
373 | assign fdin[3:0] = din[3:0]; | |
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | dff #(4) d0_0 ( | |
381 | .l1clk(l1clk), | |
382 | .siclk(siclk), | |
383 | .soclk(soclk), | |
384 | .d(fdin[3:0]), | |
385 | .si({scan_in,so[2:0]}), | |
386 | .so({so[2:0],scan_out}), | |
387 | .q(dout[3:0]) | |
388 | ); | |
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | endmodule | |
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | // any PARAMS parms go into naming of macro | |
416 | ||
417 | module lsu_tgc_ctl_msff_ctl_macro__width_3 ( | |
418 | din, | |
419 | l1clk, | |
420 | scan_in, | |
421 | siclk, | |
422 | soclk, | |
423 | dout, | |
424 | scan_out); | |
425 | wire [2:0] fdin; | |
426 | wire [1:0] so; | |
427 | ||
428 | input [2:0] din; | |
429 | input l1clk; | |
430 | input scan_in; | |
431 | ||
432 | ||
433 | input siclk; | |
434 | input soclk; | |
435 | ||
436 | output [2:0] dout; | |
437 | output scan_out; | |
438 | assign fdin[2:0] = din[2:0]; | |
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | dff #(3) d0_0 ( | |
446 | .l1clk(l1clk), | |
447 | .siclk(siclk), | |
448 | .soclk(soclk), | |
449 | .d(fdin[2:0]), | |
450 | .si({scan_in,so[1:0]}), | |
451 | .so({so[1:0],scan_out}), | |
452 | .q(dout[2:0]) | |
453 | ); | |
454 | ||
455 | ||
456 | ||
457 | ||
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | endmodule | |
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | // any PARAMS parms go into naming of macro | |
481 | ||
482 | module lsu_tgc_ctl_msff_ctl_macro__width_38 ( | |
483 | din, | |
484 | l1clk, | |
485 | scan_in, | |
486 | siclk, | |
487 | soclk, | |
488 | dout, | |
489 | scan_out); | |
490 | wire [37:0] fdin; | |
491 | wire [36:0] so; | |
492 | ||
493 | input [37:0] din; | |
494 | input l1clk; | |
495 | input scan_in; | |
496 | ||
497 | ||
498 | input siclk; | |
499 | input soclk; | |
500 | ||
501 | output [37:0] dout; | |
502 | output scan_out; | |
503 | assign fdin[37:0] = din[37:0]; | |
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | dff #(38) d0_0 ( | |
511 | .l1clk(l1clk), | |
512 | .siclk(siclk), | |
513 | .soclk(soclk), | |
514 | .d(fdin[37:0]), | |
515 | .si({scan_in,so[36:0]}), | |
516 | .so({so[36:0],scan_out}), | |
517 | .q(dout[37:0]) | |
518 | ); | |
519 | ||
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | endmodule | |
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | // Description: Spare gate macro for control blocks | |
542 | // | |
543 | // Param num controls the number of times the macro is added | |
544 | // flops=0 can be used to use only combination spare logic | |
545 | ||
546 | ||
547 | module lsu_tgc_ctl_spare_ctl_macro__num_1 ( | |
548 | l1clk, | |
549 | scan_in, | |
550 | siclk, | |
551 | soclk, | |
552 | scan_out); | |
553 | wire si_0; | |
554 | wire so_0; | |
555 | wire spare0_flop_unused; | |
556 | wire spare0_buf_32x_unused; | |
557 | wire spare0_nand3_8x_unused; | |
558 | wire spare0_inv_8x_unused; | |
559 | wire spare0_aoi22_4x_unused; | |
560 | wire spare0_buf_8x_unused; | |
561 | wire spare0_oai22_4x_unused; | |
562 | wire spare0_inv_16x_unused; | |
563 | wire spare0_nand2_16x_unused; | |
564 | wire spare0_nor3_4x_unused; | |
565 | wire spare0_nand2_8x_unused; | |
566 | wire spare0_buf_16x_unused; | |
567 | wire spare0_nor2_16x_unused; | |
568 | wire spare0_inv_32x_unused; | |
569 | ||
570 | ||
571 | input l1clk; | |
572 | input scan_in; | |
573 | input siclk; | |
574 | input soclk; | |
575 | output scan_out; | |
576 | ||
577 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
578 | .siclk(siclk), | |
579 | .soclk(soclk), | |
580 | .si(si_0), | |
581 | .so(so_0), | |
582 | .d(1'b0), | |
583 | .q(spare0_flop_unused)); | |
584 | assign si_0 = scan_in; | |
585 | ||
586 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
587 | .out(spare0_buf_32x_unused)); | |
588 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
589 | .in1(1'b1), | |
590 | .in2(1'b1), | |
591 | .out(spare0_nand3_8x_unused)); | |
592 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
593 | .out(spare0_inv_8x_unused)); | |
594 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
595 | .in01(1'b1), | |
596 | .in10(1'b1), | |
597 | .in11(1'b1), | |
598 | .out(spare0_aoi22_4x_unused)); | |
599 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
600 | .out(spare0_buf_8x_unused)); | |
601 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
602 | .in01(1'b1), | |
603 | .in10(1'b1), | |
604 | .in11(1'b1), | |
605 | .out(spare0_oai22_4x_unused)); | |
606 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
607 | .out(spare0_inv_16x_unused)); | |
608 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
609 | .in1(1'b1), | |
610 | .out(spare0_nand2_16x_unused)); | |
611 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
612 | .in1(1'b0), | |
613 | .in2(1'b0), | |
614 | .out(spare0_nor3_4x_unused)); | |
615 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
616 | .in1(1'b1), | |
617 | .out(spare0_nand2_8x_unused)); | |
618 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
619 | .out(spare0_buf_16x_unused)); | |
620 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
621 | .in1(1'b0), | |
622 | .out(spare0_nor2_16x_unused)); | |
623 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
624 | .out(spare0_inv_32x_unused)); | |
625 | assign scan_out = so_0; | |
626 | ||
627 | ||
628 | ||
629 | endmodule | |
630 |