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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: lsu_tlc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module lsu_tlc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | tcu_scan_en, | |
40 | spc_aclk, | |
41 | spc_bclk, | |
42 | mmu_dtlb_reload, | |
43 | tld_demap_control0, | |
44 | tld_demap_control1, | |
45 | tld_use_secondary_context0, | |
46 | tld_index_valid, | |
47 | lsu_lsu_pmen_, | |
48 | lsu_asi_error_inject_b31, | |
49 | lsu_asi_error_inject_b27, | |
50 | lsu_asi_error_inject_b26, | |
51 | dcc_tlb_rw_index_e, | |
52 | lbist_run, | |
53 | mbi_run, | |
54 | mbi_dtb_write_en, | |
55 | mbi_repl_write, | |
56 | mbi_dis_clr_ubit, | |
57 | mbi_cambist_run, | |
58 | mbi_dtb_demap_en, | |
59 | mbi_demap_type, | |
60 | scan_out, | |
61 | tlc_wr_u_en, | |
62 | tlc_rw_index_vld, | |
63 | tlc_demap, | |
64 | tlc_demap_context, | |
65 | tlc_demap_all, | |
66 | tlc_demap_real, | |
67 | tlc_sel_demap_tag_c0, | |
68 | tlc_sel_demap_tag_c1, | |
69 | tlc_sel_write_tag, | |
70 | tlc_sel_dm_tag, | |
71 | tlc_sel_wr_dm_bist, | |
72 | tlc_sel_tte_tag, | |
73 | tlc_use_primary_context_c0, | |
74 | tlc_use_secondary_context_c0, | |
75 | tlc_wr_or_demap, | |
76 | tlc_write_next, | |
77 | tlc_tte0_clken, | |
78 | tlc_tte1_clken, | |
79 | tlc_tag_error_inj, | |
80 | tlc_data_error_inj, | |
81 | tlc_mbi_run, | |
82 | tlc_dis_clr_ubit, | |
83 | lsu_sel_lsu_addr_e); | |
84 | wire se; | |
85 | wire pce_ov; | |
86 | wire stop; | |
87 | wire siclk; | |
88 | wire soclk; | |
89 | wire l1clk; | |
90 | wire reload0_latch_scanin; | |
91 | wire reload0_latch_scanout; | |
92 | wire reload0; | |
93 | wire reload1_latch_scanin; | |
94 | wire reload1_latch_scanout; | |
95 | wire reload1; | |
96 | wire [2:0] demap_c0; | |
97 | wire [3:0] demap_c1; | |
98 | wire wr_vld_in; | |
99 | wire sel_wr_dm_bist_next; | |
100 | wire dm_tag_in; | |
101 | wire wr_vld_latch_scanin; | |
102 | wire wr_vld_latch_scanout; | |
103 | wire wr_vld; | |
104 | wire demap_context; | |
105 | wire demap_all; | |
106 | wire demap_real; | |
107 | wire sel_demap_tag_d; | |
108 | wire override_context0; | |
109 | wire tag_error_inj; | |
110 | wire data_error_inj; | |
111 | wire error_inj_latch_scanin; | |
112 | wire error_inj_latch_scanout; | |
113 | wire bist_latch_scanin; | |
114 | wire bist_latch_scanout; | |
115 | wire spares_scanin; | |
116 | wire spares_scanout; | |
117 | ||
118 | ||
119 | ||
120 | ||
121 | input l2clk; | |
122 | input scan_in; | |
123 | input tcu_pce_ov; | |
124 | input tcu_scan_en; | |
125 | input spc_aclk; | |
126 | input spc_bclk; | |
127 | // The following signals indicate the | |
128 | // first cycle of TTE transfer as well | |
129 | // as the operation (write or demap) | |
130 | input mmu_dtlb_reload; | |
131 | ||
132 | input [2:0] tld_demap_control0; // Demap and context controls | |
133 | input [3:0] tld_demap_control1; // Demap and context controls | |
134 | input tld_use_secondary_context0; | |
135 | input tld_index_valid; // Write with index | |
136 | ||
137 | input lsu_lsu_pmen_; // Power management enable | |
138 | input lsu_asi_error_inject_b31; | |
139 | input lsu_asi_error_inject_b27; | |
140 | input lsu_asi_error_inject_b26; | |
141 | ||
142 | input dcc_tlb_rw_index_e; | |
143 | ||
144 | input lbist_run; | |
145 | input mbi_run; | |
146 | input mbi_dtb_write_en; | |
147 | input mbi_repl_write; | |
148 | input mbi_dis_clr_ubit; | |
149 | input mbi_cambist_run; | |
150 | input mbi_dtb_demap_en; | |
151 | input [1:0] mbi_demap_type; | |
152 | ||
153 | output scan_out; | |
154 | output tlc_wr_u_en; // Write enable for tlb | |
155 | output tlc_rw_index_vld; // Use index for read or write | |
156 | output tlc_demap; // Any demap | |
157 | output tlc_demap_context; // Demap context | |
158 | output tlc_demap_all; // Demap all | |
159 | output tlc_demap_real; // Demap real | |
160 | ||
161 | output tlc_sel_demap_tag_c0; | |
162 | output tlc_sel_demap_tag_c1; | |
163 | output tlc_sel_write_tag; | |
164 | output tlc_sel_dm_tag; | |
165 | output tlc_sel_wr_dm_bist; | |
166 | output tlc_sel_tte_tag; | |
167 | ||
168 | output tlc_use_primary_context_c0;// Control context muxes | |
169 | output tlc_use_secondary_context_c0; | |
170 | ||
171 | output tlc_wr_or_demap; // Tells LSU to use the demap/write tid for context selection | |
172 | output tlc_write_next; | |
173 | ||
174 | output tlc_tte0_clken; | |
175 | output tlc_tte1_clken; | |
176 | ||
177 | output tlc_tag_error_inj; | |
178 | output tlc_data_error_inj; | |
179 | output tlc_mbi_run; | |
180 | output tlc_dis_clr_ubit; | |
181 | ||
182 | output lsu_sel_lsu_addr_e; | |
183 | ||
184 | ////////////////////////////////////////////////////////////////////////////// | |
185 | ||
186 | assign se = tcu_scan_en; | |
187 | assign pce_ov = tcu_pce_ov; | |
188 | assign stop = 1'b0; | |
189 | assign siclk = spc_aclk; | |
190 | assign soclk = spc_bclk; | |
191 | ||
192 | // Clock header | |
193 | lsu_tlc_ctl_l1clkhdr_ctl_macro clkgen ( | |
194 | .l2clk (l2clk ), | |
195 | .l1en (1'b1 ), | |
196 | .l1clk (l1clk ), | |
197 | .pce_ov(pce_ov), | |
198 | .stop(stop), | |
199 | .se(se) | |
200 | ); | |
201 | ||
202 | ||
203 | ||
204 | ||
205 | ||
206 | //////////////////////////////////////////////////////////////////////////////// | |
207 | // | |
208 | // | |
209 | // | |
210 | ||
211 | ||
212 | ||
213 | //flop mmu_dtlb_reload | |
214 | ||
215 | lsu_tlc_ctl_msff_ctl_macro__width_1 reload0_latch ( | |
216 | .scan_in(reload0_latch_scanin), | |
217 | .scan_out(reload0_latch_scanout), | |
218 | .din (mmu_dtlb_reload ), | |
219 | .dout (reload0 ), | |
220 | .l1clk(l1clk), | |
221 | .siclk(siclk), | |
222 | .soclk(soclk) | |
223 | ); | |
224 | ||
225 | lsu_tlc_ctl_msff_ctl_macro__width_1 reload1_latch ( | |
226 | .scan_in(reload1_latch_scanin), | |
227 | .scan_out(reload1_latch_scanout), | |
228 | .din (reload0 ), | |
229 | .dout (reload1 ), | |
230 | .l1clk(l1clk), | |
231 | .siclk(siclk), | |
232 | .soclk(soclk) | |
233 | ); | |
234 | ||
235 | // demap_control[3]: use secondary context for demap/write | |
236 | // demap_control[2]: 1 means demap, 0 means write | |
237 | // demap_control[1:0] (if demap_control[2] is 1) | |
238 | // 00 Demap page | |
239 | // 01 Demap context | |
240 | // 10 Demap all (to be consistent with Niagara 1) | |
241 | // 11 Demap real | |
242 | // demap_control[1:0] (if demap_control[2] is 0) | |
243 | // 00 Demap and write with supplied context | |
244 | // 01 Demap and write with context_0 | |
245 | // 10 Demap and write with context_1 | |
246 | // 11 Illegal (but demap and write with context_0) | |
247 | ||
248 | assign demap_c0[2:0] = | |
249 | tld_demap_control0[2:0]; | |
250 | assign demap_c1[3:0] = | |
251 | tld_demap_control1[3:0]; | |
252 | ||
253 | assign wr_vld_in = | |
254 | reload1 & ~demap_c1[2] & ~tlc_mbi_run; | |
255 | ||
256 | assign tlc_write_next = wr_vld_in; | |
257 | ||
258 | assign sel_wr_dm_bist_next = wr_vld_in | reload0 | tlc_mbi_run; | |
259 | ||
260 | assign dm_tag_in = ~(wr_vld_in | tlc_mbi_run); | |
261 | ||
262 | lsu_tlc_ctl_msff_ctl_macro__width_3 wr_vld_latch ( | |
263 | .scan_in(wr_vld_latch_scanin), | |
264 | .scan_out(wr_vld_latch_scanout), | |
265 | .din ({wr_vld_in, dm_tag_in, sel_wr_dm_bist_next}), | |
266 | .dout ({wr_vld, tlc_sel_dm_tag,tlc_sel_wr_dm_bist}), | |
267 | .l1clk(l1clk), | |
268 | .siclk(siclk), | |
269 | .soclk(soclk) | |
270 | ); | |
271 | ||
272 | assign lsu_sel_lsu_addr_e = tlc_sel_wr_dm_bist; | |
273 | ||
274 | assign demap_context = | |
275 | reload1 & demap_c1[2] & ~demap_c1[1] & demap_c1[0]; | |
276 | ||
277 | assign demap_all = | |
278 | reload1 & demap_c1[2] & demap_c1[1] & ~demap_c1[0]; | |
279 | ||
280 | assign demap_real = | |
281 | reload1 & demap_c1[2] & demap_c1[1] & demap_c1[0]; | |
282 | ||
283 | // demap default context if: | |
284 | // a write with the use_context_[0,1] bits off OR | |
285 | // a demap with use_seconday off | |
286 | assign sel_demap_tag_d = | |
287 | (reload1 & demap_c1[2] & ~demap_c1[3]) | | |
288 | (reload1 & ~demap_c1[2] & ~demap_c1[1] & ~demap_c1[0]) ; | |
289 | ||
290 | // demap context 0 if: | |
291 | // a demap with use_secondary OR | |
292 | // a write with use_context_0 on | |
293 | assign tlc_sel_demap_tag_c0 = | |
294 | (reload1 & demap_c1[2] & demap_c1[3]) | | |
295 | (reload1 & ~demap_c1[2] & demap_c1[0]) ; | |
296 | ||
297 | // demap context 1 if a write with use_context_1 on | |
298 | assign tlc_sel_demap_tag_c1 = | |
299 | (reload1 & ~demap_c1[2] & demap_c1[1] & ~demap_c1[0]) ; | |
300 | ||
301 | ||
302 | assign tlc_sel_write_tag = wr_vld; | |
303 | assign tlc_sel_tte_tag = wr_vld | sel_demap_tag_d | tlc_mbi_run; | |
304 | ||
305 | ||
306 | // Context mux controls | |
307 | assign override_context0 = | |
308 | reload0 & ~demap_c0[2] & (demap_c0[1] | demap_c0[0]); | |
309 | ||
310 | assign tlc_use_primary_context_c0 = | |
311 | (override_context0 & ~tld_use_secondary_context0) | | |
312 | (reload0 & demap_c0[2] & ~tld_use_secondary_context0) ; | |
313 | ||
314 | assign tlc_use_secondary_context_c0 = | |
315 | (override_context0 & tld_use_secondary_context0) | | |
316 | (reload0 & demap_c0[2] & tld_use_secondary_context0) ; | |
317 | ||
318 | ///outputs | |
319 | ||
320 | assign tlc_demap = tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en) : reload1; | |
321 | assign tlc_demap_context = tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b10)) : demap_context; | |
322 | assign tlc_demap_all = tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b11)) : demap_all; | |
323 | assign tlc_demap_real = tlc_mbi_run ? (mbi_cambist_run & mbi_dtb_demap_en & (mbi_demap_type[1:0] == 2'b01)) : demap_real; | |
324 | ||
325 | assign tlc_wr_u_en = tlc_mbi_run ? mbi_dtb_write_en : wr_vld; | |
326 | ||
327 | assign tlc_rw_index_vld = (tlc_mbi_run ? ~mbi_repl_write : (dcc_tlb_rw_index_e | (wr_vld & tld_index_valid))) | lbist_run; | |
328 | ||
329 | // This needs to be a cycle earlier than the tlb controls for timing | |
330 | assign tlc_wr_or_demap = reload0 | wr_vld_in; | |
331 | ||
332 | ////////////////////////////////// | |
333 | // Power mgmt for the datapath | |
334 | assign tlc_tte0_clken = mmu_dtlb_reload | reload0 | lsu_lsu_pmen_; | |
335 | assign tlc_tte1_clken = reload0 | reload1 | lsu_lsu_pmen_; | |
336 | ||
337 | /////////////////////////////////// | |
338 | // Error injection | |
339 | assign tag_error_inj = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b26 & wr_vld_in; | |
340 | assign data_error_inj = lsu_asi_error_inject_b31 & lsu_asi_error_inject_b27 & wr_vld_in; | |
341 | ||
342 | lsu_tlc_ctl_msff_ctl_macro__width_2 error_inj_latch ( | |
343 | .scan_in(error_inj_latch_scanin), | |
344 | .scan_out(error_inj_latch_scanout), | |
345 | .din ({ tag_error_inj, data_error_inj }), | |
346 | .dout ({tlc_tag_error_inj,tlc_data_error_inj }), | |
347 | .l1clk(l1clk), | |
348 | .siclk(siclk), | |
349 | .soclk(soclk) | |
350 | ); | |
351 | ||
352 | /////////////////////////////////// | |
353 | // BIST | |
354 | ||
355 | lsu_tlc_ctl_msff_ctl_macro__width_1 bist_latch ( | |
356 | .scan_in(bist_latch_scanin), | |
357 | .scan_out(bist_latch_scanout), | |
358 | .din (mbi_run), | |
359 | .dout (tlc_mbi_run), | |
360 | .l1clk(l1clk), | |
361 | .siclk(siclk), | |
362 | .soclk(soclk) | |
363 | ); | |
364 | ||
365 | assign tlc_dis_clr_ubit = tlc_mbi_run & mbi_dis_clr_ubit; | |
366 | ||
367 | lsu_tlc_ctl_spare_ctl_macro__num_1 spares ( | |
368 | .scan_in(spares_scanin), | |
369 | .scan_out(spares_scanout), | |
370 | .l1clk (l1clk), | |
371 | .siclk(siclk), | |
372 | .soclk(soclk) | |
373 | ); | |
374 | ||
375 | // fixscan start: | |
376 | assign reload0_latch_scanin = scan_in ; | |
377 | assign reload1_latch_scanin = reload0_latch_scanout ; | |
378 | assign wr_vld_latch_scanin = reload1_latch_scanout ; | |
379 | assign error_inj_latch_scanin = wr_vld_latch_scanout ; | |
380 | assign bist_latch_scanin = error_inj_latch_scanout ; | |
381 | assign spares_scanin = bist_latch_scanout ; | |
382 | assign scan_out = spares_scanout ; | |
383 | // fixscan end: | |
384 | endmodule | |
385 | ||
386 | ||
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | // any PARAMS parms go into naming of macro | |
394 | ||
395 | module lsu_tlc_ctl_l1clkhdr_ctl_macro ( | |
396 | l2clk, | |
397 | l1en, | |
398 | pce_ov, | |
399 | stop, | |
400 | se, | |
401 | l1clk); | |
402 | ||
403 | ||
404 | input l2clk; | |
405 | input l1en; | |
406 | input pce_ov; | |
407 | input stop; | |
408 | input se; | |
409 | output l1clk; | |
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | cl_sc1_l1hdr_8x c_0 ( | |
416 | ||
417 | ||
418 | .l2clk(l2clk), | |
419 | .pce(l1en), | |
420 | .l1clk(l1clk), | |
421 | .se(se), | |
422 | .pce_ov(pce_ov), | |
423 | .stop(stop) | |
424 | ); | |
425 | ||
426 | ||
427 | ||
428 | endmodule | |
429 | ||
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 | ||
441 | ||
442 | // any PARAMS parms go into naming of macro | |
443 | ||
444 | module lsu_tlc_ctl_msff_ctl_macro__width_1 ( | |
445 | din, | |
446 | l1clk, | |
447 | scan_in, | |
448 | siclk, | |
449 | soclk, | |
450 | dout, | |
451 | scan_out); | |
452 | wire [0:0] fdin; | |
453 | ||
454 | input [0:0] din; | |
455 | input l1clk; | |
456 | input scan_in; | |
457 | ||
458 | ||
459 | input siclk; | |
460 | input soclk; | |
461 | ||
462 | output [0:0] dout; | |
463 | output scan_out; | |
464 | assign fdin[0:0] = din[0:0]; | |
465 | ||
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | dff #(1) d0_0 ( | |
472 | .l1clk(l1clk), | |
473 | .siclk(siclk), | |
474 | .soclk(soclk), | |
475 | .d(fdin[0:0]), | |
476 | .si(scan_in), | |
477 | .so(scan_out), | |
478 | .q(dout[0:0]) | |
479 | ); | |
480 | ||
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | endmodule | |
493 | ||
494 | ||
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | ||
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | // any PARAMS parms go into naming of macro | |
507 | ||
508 | module lsu_tlc_ctl_msff_ctl_macro__width_3 ( | |
509 | din, | |
510 | l1clk, | |
511 | scan_in, | |
512 | siclk, | |
513 | soclk, | |
514 | dout, | |
515 | scan_out); | |
516 | wire [2:0] fdin; | |
517 | wire [1:0] so; | |
518 | ||
519 | input [2:0] din; | |
520 | input l1clk; | |
521 | input scan_in; | |
522 | ||
523 | ||
524 | input siclk; | |
525 | input soclk; | |
526 | ||
527 | output [2:0] dout; | |
528 | output scan_out; | |
529 | assign fdin[2:0] = din[2:0]; | |
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | dff #(3) d0_0 ( | |
537 | .l1clk(l1clk), | |
538 | .siclk(siclk), | |
539 | .soclk(soclk), | |
540 | .d(fdin[2:0]), | |
541 | .si({scan_in,so[1:0]}), | |
542 | .so({so[1:0],scan_out}), | |
543 | .q(dout[2:0]) | |
544 | ); | |
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | endmodule | |
558 | ||
559 | ||
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | // any PARAMS parms go into naming of macro | |
572 | ||
573 | module lsu_tlc_ctl_msff_ctl_macro__width_2 ( | |
574 | din, | |
575 | l1clk, | |
576 | scan_in, | |
577 | siclk, | |
578 | soclk, | |
579 | dout, | |
580 | scan_out); | |
581 | wire [1:0] fdin; | |
582 | wire [0:0] so; | |
583 | ||
584 | input [1:0] din; | |
585 | input l1clk; | |
586 | input scan_in; | |
587 | ||
588 | ||
589 | input siclk; | |
590 | input soclk; | |
591 | ||
592 | output [1:0] dout; | |
593 | output scan_out; | |
594 | assign fdin[1:0] = din[1:0]; | |
595 | ||
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | dff #(2) d0_0 ( | |
602 | .l1clk(l1clk), | |
603 | .siclk(siclk), | |
604 | .soclk(soclk), | |
605 | .d(fdin[1:0]), | |
606 | .si({scan_in,so[0:0]}), | |
607 | .so({so[0:0],scan_out}), | |
608 | .q(dout[1:0]) | |
609 | ); | |
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | endmodule | |
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | // Description: Spare gate macro for control blocks | |
633 | // | |
634 | // Param num controls the number of times the macro is added | |
635 | // flops=0 can be used to use only combination spare logic | |
636 | ||
637 | ||
638 | module lsu_tlc_ctl_spare_ctl_macro__num_1 ( | |
639 | l1clk, | |
640 | scan_in, | |
641 | siclk, | |
642 | soclk, | |
643 | scan_out); | |
644 | wire si_0; | |
645 | wire so_0; | |
646 | wire spare0_flop_unused; | |
647 | wire spare0_buf_32x_unused; | |
648 | wire spare0_nand3_8x_unused; | |
649 | wire spare0_inv_8x_unused; | |
650 | wire spare0_aoi22_4x_unused; | |
651 | wire spare0_buf_8x_unused; | |
652 | wire spare0_oai22_4x_unused; | |
653 | wire spare0_inv_16x_unused; | |
654 | wire spare0_nand2_16x_unused; | |
655 | wire spare0_nor3_4x_unused; | |
656 | wire spare0_nand2_8x_unused; | |
657 | wire spare0_buf_16x_unused; | |
658 | wire spare0_nor2_16x_unused; | |
659 | wire spare0_inv_32x_unused; | |
660 | ||
661 | ||
662 | input l1clk; | |
663 | input scan_in; | |
664 | input siclk; | |
665 | input soclk; | |
666 | output scan_out; | |
667 | ||
668 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
669 | .siclk(siclk), | |
670 | .soclk(soclk), | |
671 | .si(si_0), | |
672 | .so(so_0), | |
673 | .d(1'b0), | |
674 | .q(spare0_flop_unused)); | |
675 | assign si_0 = scan_in; | |
676 | ||
677 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
678 | .out(spare0_buf_32x_unused)); | |
679 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
680 | .in1(1'b1), | |
681 | .in2(1'b1), | |
682 | .out(spare0_nand3_8x_unused)); | |
683 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
684 | .out(spare0_inv_8x_unused)); | |
685 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
686 | .in01(1'b1), | |
687 | .in10(1'b1), | |
688 | .in11(1'b1), | |
689 | .out(spare0_aoi22_4x_unused)); | |
690 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
691 | .out(spare0_buf_8x_unused)); | |
692 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
693 | .in01(1'b1), | |
694 | .in10(1'b1), | |
695 | .in11(1'b1), | |
696 | .out(spare0_oai22_4x_unused)); | |
697 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
698 | .out(spare0_inv_16x_unused)); | |
699 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
700 | .in1(1'b1), | |
701 | .out(spare0_nand2_16x_unused)); | |
702 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
703 | .in1(1'b0), | |
704 | .in2(1'b0), | |
705 | .out(spare0_nor3_4x_unused)); | |
706 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
707 | .in1(1'b1), | |
708 | .out(spare0_nand2_8x_unused)); | |
709 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
710 | .out(spare0_buf_16x_unused)); | |
711 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
712 | .in1(1'b0), | |
713 | .out(spare0_nor2_16x_unused)); | |
714 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
715 | .out(spare0_inv_32x_unused)); | |
716 | assign scan_out = so_0; | |
717 | ||
718 | ||
719 | ||
720 | endmodule | |
721 |