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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_htc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_htc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | scan_out, | |
43 | lsu_mmu_pmen, | |
44 | spc_core_running_status, | |
45 | l15_mmu_cpkt, | |
46 | l15_mmu_valid, | |
47 | asi_tsb_ptr_req_valid, | |
48 | asi_tsb_ptr_req, | |
49 | asi_tsb_ptr_number, | |
50 | asd0_zero_context, | |
51 | asd1_zero_context, | |
52 | asi_wr_partition_id, | |
53 | asi_wr_data, | |
54 | asi_hwtw_config_0, | |
55 | asi_hwtw_config_1, | |
56 | asi_hwtw_config_2, | |
57 | asi_hwtw_config_3, | |
58 | asi_hwtw_config_4, | |
59 | asi_hwtw_config_5, | |
60 | asi_hwtw_config_6, | |
61 | asi_hwtw_config_7, | |
62 | asi_tsb_hwtw_enable_0, | |
63 | asi_tsb_hwtw_enable_1, | |
64 | htd_ra2pa_lower_hit_hw4, | |
65 | htd_ra2pa_upper_hit_hw4, | |
66 | htd_razero_hw4, | |
67 | htd_range_en_hw4, | |
68 | htd_zeroctx_m0, | |
69 | htd_zeroctx_hw1, | |
70 | htd_usectx0_hw1, | |
71 | htd_usectx1_hw1, | |
72 | htd_ranotpa_hw1, | |
73 | htd_ptr_hit0_hw1, | |
74 | htd_ptr_hit1_hw1, | |
75 | htd_ptr_hit2_hw1, | |
76 | htd_ctx_hit_hw1, | |
77 | htd_tte_ep_hw1, | |
78 | htd_dmiss_hw1, | |
79 | htd_pred0_idx_m0, | |
80 | htd_pred1_idx_m0, | |
81 | htd_pred0_m0, | |
82 | htd_pred1_m0, | |
83 | htd_dmiss, | |
84 | htd_sec_ctx, | |
85 | tlu_iht_request, | |
86 | tlu_dht_request, | |
87 | l15_mmu_grant, | |
88 | asi_mra_req_grant, | |
89 | tsm_rqv, | |
90 | tsm_tsb_miss_hw2, | |
91 | trs_rqv, | |
92 | trs_null_st, | |
93 | trs_waitrr3_st, | |
94 | trs_ecc_err, | |
95 | trs_ep_err, | |
96 | mel0_parity_err, | |
97 | mel1_parity_err, | |
98 | trs0_err_type, | |
99 | trs1_err_type, | |
100 | trs2_err_type, | |
101 | trs3_err_type, | |
102 | trs4_err_type, | |
103 | trs5_err_type, | |
104 | trs6_err_type, | |
105 | trs7_err_type, | |
106 | trs0_err_index, | |
107 | trs1_err_index, | |
108 | trs2_err_index, | |
109 | trs3_err_index, | |
110 | trs4_err_index, | |
111 | trs5_err_index, | |
112 | trs6_err_index, | |
113 | trs7_err_index, | |
114 | tlu_cerer_hwtwl2, | |
115 | tlu_cerer_hwtwmu, | |
116 | htc_core_running, | |
117 | htc_m1_clken, | |
118 | htc_hw3_clken, | |
119 | htc_hw4_clken, | |
120 | mmu_i_unauth_access, | |
121 | mmu_i_tsb_miss, | |
122 | mmu_d_tsb_miss, | |
123 | mmu_reload_done, | |
124 | mmu_use_context_0, | |
125 | mmu_use_context_1, | |
126 | mmu_sec_context, | |
127 | htc_mra_addr_in, | |
128 | htc_mra_rd_en, | |
129 | htc_wr_itlb_data_in, | |
130 | htc_wr_dtlb_data_in, | |
131 | htc_dtlb_clken, | |
132 | htc_itlb_clken, | |
133 | htc_zero_ctx_m2, | |
134 | htc_upd_pred_idx_hw2, | |
135 | htc_upd_grp, | |
136 | htc_upd_grp_x, | |
137 | htc_new_pred_bit, | |
138 | htc_wrpred0_hw2, | |
139 | htc_wrpred1_hw2, | |
140 | htc_wrpred2_hw2, | |
141 | htc_wrpred3_hw2, | |
142 | htc_tlb_miss_m, | |
143 | mmu_l15_cpkt, | |
144 | htc_l15_en, | |
145 | mmu_l15_valid, | |
146 | htc_wr_q0new_nogrant, | |
147 | htc_wr_q0new_grant, | |
148 | htc_wr_q1new, | |
149 | htc_shift_q1_grant, | |
150 | htc_wr_m3new, | |
151 | htc_wr_m3q0, | |
152 | htc_mra_sel_0, | |
153 | htc_sel_mra_lo, | |
154 | htc_conf_index_m2, | |
155 | htc_vld_tsbptr_m2, | |
156 | htc_rd_tteq, | |
157 | htc_ra2pahit_hw5, | |
158 | htc_ranotpax_hw5, | |
159 | htc_cindex_bit0, | |
160 | htc_cindex_bit1, | |
161 | htc_rrindex_bit0, | |
162 | htc_rrindex_bit1, | |
163 | htc_pid0_m0, | |
164 | htc_pid1_m0, | |
165 | htc_tsbrd_valid_m0, | |
166 | htc_thr_valid_hw3, | |
167 | htc_thr_prevalid_hw3, | |
168 | htc_va_rd_m2_in, | |
169 | htc_ranotpa_hw4, | |
170 | htc_data_rcvd_hw1, | |
171 | htc_tsb_hit_hw1, | |
172 | htc_tsb_done_hw2, | |
173 | htc_thr_valid_m1, | |
174 | htc_thr_valid_m0, | |
175 | htc_hwtw_burst, | |
176 | mmu_i_tte_outofrange, | |
177 | mmu_d_tte_outofrange, | |
178 | rr_ecc_err_type, | |
179 | cfg_ecc_err_type, | |
180 | l2_ecc_err_type, | |
181 | rr_ecc_err_hw5, | |
182 | cfg_ecc_err_m3, | |
183 | l2_ecc_err_hw1, | |
184 | htc_ep_miss_hw1, | |
185 | cfg_ecc_err_index, | |
186 | rr_ecc_err_index, | |
187 | mmu_i_eccerr, | |
188 | mmu_d_eccerr, | |
189 | mmu_i_l2cerr, | |
190 | mmu_d_l2cerr, | |
191 | htc_thr0_err_type, | |
192 | htc_thr1_err_type, | |
193 | htc_thr2_err_type, | |
194 | htc_thr3_err_type, | |
195 | htc_thr4_err_type, | |
196 | htc_thr5_err_type, | |
197 | htc_thr6_err_type, | |
198 | htc_thr7_err_type, | |
199 | htc_thr0_err_index, | |
200 | htc_thr1_err_index, | |
201 | htc_thr2_err_index, | |
202 | htc_thr3_err_index, | |
203 | htc_thr4_err_index, | |
204 | htc_thr5_err_index, | |
205 | htc_thr6_err_index, | |
206 | htc_thr7_err_index, | |
207 | mmu_pmu_l2ret, | |
208 | mmu_pmu_l2miss, | |
209 | mmu_pmu_dtlb, | |
210 | mmu_pmu_tid, | |
211 | spc_aclk_wmr, | |
212 | wmr_scan_in, | |
213 | wmr_scan_out); | |
214 | wire [7:0] htc_hwtw_mode_0; | |
215 | wire [7:0] htc_hwtw_mode_1; | |
216 | wire [7:0] htc_hwtw_pred; | |
217 | wire l1clk; | |
218 | wire pce_ov; | |
219 | wire stop; | |
220 | wire siclk; | |
221 | wire soclk; | |
222 | wire se; | |
223 | wire pmen_reg_scanin; | |
224 | wire pmen_reg_scanout; | |
225 | wire htc_mmu_pmen; | |
226 | wire tlb_miss_lat_scanin; | |
227 | wire tlb_miss_lat_scanout; | |
228 | wire [7:0] htc_tlb_miss_m0; | |
229 | wire [7:0] htd_dmiss_lat; | |
230 | wire tlb_cerer_lat_scanin; | |
231 | wire tlb_cerer_lat_scanout; | |
232 | wire hwtwl2_en; | |
233 | wire hwtwmu_en; | |
234 | wire [2:0] pid0_in; | |
235 | wire [2:0] pid0; | |
236 | wire [2:0] pid1_in; | |
237 | wire [2:0] pid1; | |
238 | wire [2:0] pid2_in; | |
239 | wire [2:0] pid2; | |
240 | wire [2:0] pid3_in; | |
241 | wire [2:0] pid3; | |
242 | wire [2:0] pid4_in; | |
243 | wire [2:0] pid4; | |
244 | wire [2:0] pid5_in; | |
245 | wire [2:0] pid5; | |
246 | wire [2:0] pid6_in; | |
247 | wire [2:0] pid6; | |
248 | wire [2:0] pid7_in; | |
249 | wire [2:0] pid7; | |
250 | wire pid0_lat_wmr_scanin; | |
251 | wire pid0_lat_wmr_scanout; | |
252 | wire pid1_lat_wmr_scanin; | |
253 | wire pid1_lat_wmr_scanout; | |
254 | wire pid2_lat_wmr_scanin; | |
255 | wire pid2_lat_wmr_scanout; | |
256 | wire pid3_lat_wmr_scanin; | |
257 | wire pid3_lat_wmr_scanout; | |
258 | wire pid4_lat_wmr_scanin; | |
259 | wire pid4_lat_wmr_scanout; | |
260 | wire pid5_lat_wmr_scanin; | |
261 | wire pid5_lat_wmr_scanout; | |
262 | wire pid6_lat_wmr_scanin; | |
263 | wire pid6_lat_wmr_scanout; | |
264 | wire pid7_lat_wmr_scanin; | |
265 | wire pid7_lat_wmr_scanout; | |
266 | wire [7:0] tsm_sel; | |
267 | wire [3:0] tsm_ptr0; | |
268 | wire [7:4] tsm_ptr1; | |
269 | wire tg0_valid; | |
270 | wire tg1_valid; | |
271 | wire sel_tg1; | |
272 | wire favor_tg1; | |
273 | wire [7:0] tsm_thrsel_m0; | |
274 | wire [7:0] trs_thrsel_hw2; | |
275 | wire tsm_thrsel_v; | |
276 | wire trs_thrsel_v; | |
277 | wire [7:0] tsm_valid_m0; | |
278 | wire [7:0] trs_valid_hw2; | |
279 | wire tsm_tg0_selected; | |
280 | wire tsm_tg1_selected; | |
281 | wire favor_tg1_in; | |
282 | wire favour_bit_reg_scanin; | |
283 | wire favour_bit_reg_scanout; | |
284 | wire [3:0] tsm_ptr0_in; | |
285 | wire [7:4] tsm_ptr1_in; | |
286 | wire tsm_ptr0_in_0_; | |
287 | wire tsm_ptr1_in_4_; | |
288 | wire ptr0_reg_scanin; | |
289 | wire ptr0_reg_scanout; | |
290 | wire tsm_ptr0_0_; | |
291 | wire ptr1_reg_scanin; | |
292 | wire ptr1_reg_scanout; | |
293 | wire tsm_ptr1_4_; | |
294 | wire zero_ctx; | |
295 | wire [7:0] incr_cindex_bit0; | |
296 | wire [7:0] incr_cindex_bit1; | |
297 | wire [7:0] next_cindex_bit0; | |
298 | wire [7:0] next_cindex_bit1; | |
299 | wire conf_idx_reg_scanin; | |
300 | wire conf_idx_reg_scanout; | |
301 | wire [7:0] incr_rrindex_bit0; | |
302 | wire [7:0] incr_rrindex_bit1; | |
303 | wire [7:0] next_rrindex_bit0; | |
304 | wire [7:0] next_rrindex_bit1; | |
305 | wire rr_idx_reg_scanin; | |
306 | wire rr_idx_reg_scanout; | |
307 | wire [1:0] conf_index; | |
308 | wire [7:0] cfg_done_m1; | |
309 | wire conf_rd_en; | |
310 | wire [2:0] conf_rd_thr_id; | |
311 | wire [4:0] conf_addr_in; | |
312 | wire [1:0] conf_mra_rd_en; | |
313 | wire [4:0] rr_addr_in; | |
314 | wire rr_rd_en; | |
315 | wire [1:0] rr_mra_rd_en; | |
316 | wire thr_valid_miss_lo_m0; | |
317 | wire thr_valid_miss_hi_m0; | |
318 | wire tsbrd_valid_m0; | |
319 | wire m1_stg_lat_scanin; | |
320 | wire m1_stg_lat_scanout; | |
321 | wire zero_ctx_m1; | |
322 | wire [1:0] conf_index_m1; | |
323 | wire [2:0] conf_addr_m1; | |
324 | wire conf_prevalid_lat_scanin; | |
325 | wire conf_prevalid_lat_scanout; | |
326 | wire [7:0] thr_prevalid_m1; | |
327 | wire tsbrd_z_m0; | |
328 | wire tsbrd_nz_m0; | |
329 | wire tsbptr_lat_scanin; | |
330 | wire tsbptr_lat_scanout; | |
331 | wire [0:0] tsbrd_tsbptr_m1; | |
332 | wire tsbrd_z_m1; | |
333 | wire tsbrd_nz_m1; | |
334 | wire [7:0] htc_tsbrd_valid_m1; | |
335 | wire asi_tsb_ptr_number_unused; | |
336 | wire predrow0_lat_scanin; | |
337 | wire predrow0_lat_scanout; | |
338 | wire [5:0] htd_pred0_idx_m1; | |
339 | wire [15:0] htd_pred0_m1; | |
340 | wire predrow1_lat_scanin; | |
341 | wire predrow1_lat_scanout; | |
342 | wire [5:0] htd_pred1_idx_m1; | |
343 | wire [15:0] htd_pred1_m1; | |
344 | wire tlbmiss_lat_scanin; | |
345 | wire tlbmiss_lat_scanout; | |
346 | wire [7:0] htc_tlb_miss_m1; | |
347 | wire tlbvalidmiss_lat_scanin; | |
348 | wire tlbvalidmiss_lat_scanout; | |
349 | wire thr_valid_miss_hi_m1; | |
350 | wire thr_valid_miss_lo_m1; | |
351 | wire [1:0] pred0_bit_m1; | |
352 | wire [1:0] pred1_bit_m1; | |
353 | wire [5:0] pred_idx0_in; | |
354 | wire [5:0] pred_idx0; | |
355 | wire [5:0] pred_idx1_in; | |
356 | wire [5:0] pred_idx1; | |
357 | wire [5:0] pred_idx2_in; | |
358 | wire [5:0] pred_idx2; | |
359 | wire [5:0] pred_idx3_in; | |
360 | wire [5:0] pred_idx3; | |
361 | wire [5:0] pred_idx4_in; | |
362 | wire [5:0] pred_idx4; | |
363 | wire [5:0] pred_idx5_in; | |
364 | wire [5:0] pred_idx5; | |
365 | wire [5:0] pred_idx6_in; | |
366 | wire [5:0] pred_idx6; | |
367 | wire [5:0] pred_idx7_in; | |
368 | wire [5:0] pred_idx7; | |
369 | wire [1:0] pred_bit0_in; | |
370 | wire [1:0] pred_bit0; | |
371 | wire [1:0] pred_bit1_in; | |
372 | wire [1:0] pred_bit1; | |
373 | wire [1:0] pred_bit2_in; | |
374 | wire [1:0] pred_bit2; | |
375 | wire [1:0] pred_bit3_in; | |
376 | wire [1:0] pred_bit3; | |
377 | wire [1:0] pred_bit4_in; | |
378 | wire [1:0] pred_bit4; | |
379 | wire [1:0] pred_bit5_in; | |
380 | wire [1:0] pred_bit5; | |
381 | wire [1:0] pred_bit6_in; | |
382 | wire [1:0] pred_bit6; | |
383 | wire [1:0] pred_bit7_in; | |
384 | wire [1:0] pred_bit7; | |
385 | wire pred0_lat_scanin; | |
386 | wire pred0_lat_scanout; | |
387 | wire pred1_lat_scanin; | |
388 | wire pred1_lat_scanout; | |
389 | wire pred2_lat_scanin; | |
390 | wire pred2_lat_scanout; | |
391 | wire pred3_lat_scanin; | |
392 | wire pred3_lat_scanout; | |
393 | wire pred4_lat_scanin; | |
394 | wire pred4_lat_scanout; | |
395 | wire pred5_lat_scanin; | |
396 | wire pred5_lat_scanout; | |
397 | wire pred6_lat_scanin; | |
398 | wire pred6_lat_scanout; | |
399 | wire pred7_lat_scanin; | |
400 | wire pred7_lat_scanout; | |
401 | wire room_avail_m1; | |
402 | wire cfg_read_tg0_m1; | |
403 | wire cfg_read_tg1_m1; | |
404 | wire htc_valid_m1; | |
405 | wire [7:0] thr_valid_m2_in; | |
406 | wire tsbrd_valid_m1; | |
407 | wire tsbrd_tg0_m1; | |
408 | wire tsbrd_tg1_m1; | |
409 | wire [1:0] htc_mra_sel; | |
410 | wire rr_read_tg1_hw3; | |
411 | wire rr_read_tg0_hw3; | |
412 | wire pred_en; | |
413 | wire [1:1] pred_bit_m1; | |
414 | wire conf_sel_mra_lo; | |
415 | wire conf_sel_mra_up; | |
416 | wire tsbrd_sel_mra_lo; | |
417 | wire tsbrd_sel_mra_up; | |
418 | wire htc_sel_mra_up; | |
419 | wire [1:0] conf_index_m2_in; | |
420 | wire hwtw_en_tg0; | |
421 | wire hwtw_en_tg1; | |
422 | wire hwtw_en_m2_in; | |
423 | wire m2_stg_lat2_scanin; | |
424 | wire m2_stg_lat2_scanout; | |
425 | wire hwtw_en_m2; | |
426 | wire cfg_read_tg0_m2; | |
427 | wire cfg_read_tg1_m2; | |
428 | wire zero_ctx_m2; | |
429 | wire [2:0] conf_addr_m2; | |
430 | wire [7:0] htc_thr_valid_m2; | |
431 | wire [2:0] vld_tsbptr_thr_id_m2; | |
432 | wire vld_tsbptr_rdy_m2; | |
433 | wire [7:0] htc_cfg_ecc_err_en_m2; | |
434 | wire [2:0] cfg_ecc_err_index_m2; | |
435 | wire m3_stg_lat1_scanin; | |
436 | wire m3_stg_lat1_scanout; | |
437 | wire cfg_read_tg0_m3; | |
438 | wire cfg_read_tg1_m3; | |
439 | wire [7:0] htc_cfg_ecc_err_en_m3; | |
440 | wire mel0_parity_err_m3; | |
441 | wire mel1_parity_err_m3; | |
442 | wire mra0_ecc_err_lat; | |
443 | wire mra1_ecc_err_lat; | |
444 | wire [1:0] mra0_err_type_lat; | |
445 | wire [1:0] mra1_err_type_lat; | |
446 | wire req_m2; | |
447 | wire [2:0] htc_l15_cpkt_15_13; | |
448 | wire [1:0] htc_l15_cpkt_9_8; | |
449 | wire [1:0] next_gkt_count; | |
450 | wire gkt_grant; | |
451 | wire mmu_l15_valid_int; | |
452 | wire [1:0] gkt_count; | |
453 | wire gkt_count_reg_scanin; | |
454 | wire gkt_count_reg_scanout; | |
455 | wire gkt_full; | |
456 | wire v0_in; | |
457 | wire v0; | |
458 | wire v1; | |
459 | wire v1_in; | |
460 | wire qv_reg_scanin; | |
461 | wire qv_reg_scanout; | |
462 | wire q0_val; | |
463 | wire q1_val; | |
464 | wire htc_wr_q0new; | |
465 | wire htc_shift_q1; | |
466 | wire [4:0] q1_cpkt_in; | |
467 | wire [4:0] q1_cpkt; | |
468 | wire q1cpkt_reg_scanin; | |
469 | wire q1cpkt_reg_scanout; | |
470 | wire [4:0] q0_cpkt_in; | |
471 | wire [4:0] q0_cpkt; | |
472 | wire q0cpkt_reg_scanin; | |
473 | wire q0cpkt_reg_scanout; | |
474 | wire htc_l15_valid; | |
475 | wire [2:0] mmu_l15_cpkt_in_15_13_in; | |
476 | wire [1:0] mmu_l15_cpkt_in_9_8_in; | |
477 | wire cpkt_reg_scanin; | |
478 | wire cpkt_reg_scanout; | |
479 | wire load_ret_hw0; | |
480 | wire [7:0] ret_tid_hw0; | |
481 | wire l2_err_hw0; | |
482 | wire [1:0] l2_ecc_err_type_hw0; | |
483 | wire [1:0] ret_tsbid_hw0; | |
484 | wire l2miss_hw0; | |
485 | wire l2_cerr_hw0; | |
486 | wire gkt_hw0_lat0_scanin; | |
487 | wire gkt_hw0_lat0_scanout; | |
488 | wire l2_cerr_hw1; | |
489 | wire l2_err_hw1; | |
490 | wire load_ret_hw1; | |
491 | wire [7:0] ret_tid_hw1; | |
492 | wire [1:0] ret_tsbid_hw1; | |
493 | wire l2miss_hw1; | |
494 | wire [2:0] mmutid_hw1; | |
495 | wire htd_ptr_hit_hw1; | |
496 | wire ctx_hit; | |
497 | wire ep_hit; | |
498 | wire raw_tsb_hit_hw1; | |
499 | wire raw_ep_miss_hw1; | |
500 | wire [7:0] tsb_done_hw1; | |
501 | wire [7:0] d_l2_cerr; | |
502 | wire [7:0] i_l2_cerr; | |
503 | wire final_l2_cerr_lat_scanin; | |
504 | wire final_l2_cerr_lat_scanout; | |
505 | wire tsb_hit_lat_scanin; | |
506 | wire tsb_hit_lat_scanout; | |
507 | wire [7:0] htc_tsb_hit_hw2; | |
508 | wire ep_miss_lat_scanin; | |
509 | wire ep_miss_lat_scanout; | |
510 | wire [7:0] htc_ep_miss_hw2; | |
511 | wire tsb_done_lat_scanin; | |
512 | wire tsb_done_lat_scanout; | |
513 | wire [7:0] tsb_done_nocfg_hw2; | |
514 | wire cfg_ecc_lat_scanin; | |
515 | wire cfg_ecc_lat_scanout; | |
516 | wire [7:0] cfg_ecc_err_m4; | |
517 | wire tsbid_lat_scanin; | |
518 | wire tsbid_lat_scanout; | |
519 | wire [1:0] ret_tsbid_hw2; | |
520 | wire [7:0] htd_ranotpa_in; | |
521 | wire [7:0] htd_ranotpa; | |
522 | wire [7:0] htd_zeroctx_in; | |
523 | wire [7:0] htd_zeroctx; | |
524 | wire [7:0] htd_usectx0_in; | |
525 | wire [7:0] htd_usectx0; | |
526 | wire [7:0] htd_usectx1_in; | |
527 | wire [7:0] htd_usectx1; | |
528 | wire tsb0_lat_scanin; | |
529 | wire tsb0_lat_scanout; | |
530 | wire [1:0] rr_index; | |
531 | wire [7:0] thr_valid_hw2; | |
532 | wire [7:0] rr_done_hw3; | |
533 | wire [2:0] rr_rd_thr_id; | |
534 | wire [5:0] upd_pred_idx; | |
535 | wire [1:0] upd_pred_bit; | |
536 | wire [1:0] ret_tsbnum_hw2; | |
537 | wire inc_pred; | |
538 | wire dec_pred; | |
539 | wire pred_upd_en; | |
540 | wire rr_addr_hw2_lat_scanin; | |
541 | wire rr_addr_hw2_lat_scanout; | |
542 | wire [2:0] rr_addr_hw3; | |
543 | wire rr_index_hw2_lat_scanin; | |
544 | wire rr_index_hw2_lat_scanout; | |
545 | wire [1:0] rr_index_hw3; | |
546 | wire rr_prevalid_lat_scanin; | |
547 | wire rr_prevalid_lat_scanout; | |
548 | wire stg_hw3_lat_scanin; | |
549 | wire stg_hw3_lat_scanout; | |
550 | wire rr_read_tg0_hw4; | |
551 | wire rr_read_tg1_hw4; | |
552 | wire [2:0] rr_addr_hw4; | |
553 | wire thr_valid_hw3_lat_scanin; | |
554 | wire thr_valid_hw3_lat_scanout; | |
555 | wire [7:0] htc_thr_valid_hw4; | |
556 | wire ra2pahit_raw; | |
557 | wire [7:0] htc_thr_ra_valid_hw4; | |
558 | wire [7:0] ra2pahit_thr_hw4; | |
559 | wire [7:0] disable_ra2pahit_st; | |
560 | wire [7:0] htc_ranotpax_hw4; | |
561 | wire [7:0] disable_ra2pahit_st_in; | |
562 | wire htc_zeroctx_hw4; | |
563 | wire htc_usectx0_hw4; | |
564 | wire htc_usectx1_hw4; | |
565 | wire htc_sec_ctx_hw4; | |
566 | wire htc_new_use_ctx0_hw4; | |
567 | wire htc_new_use_ctx1_hw4; | |
568 | wire [2:0] rr_ecc_err_index_hw4; | |
569 | wire [7:0] tlb_clken_hw4; | |
570 | wire [7:0] htc_dtlb_clken_hw4; | |
571 | wire [7:0] htc_itlb_clken_hw4; | |
572 | wire rr_ranotpax_hw4_lat_scanin; | |
573 | wire rr_ranotpax_hw4_lat_scanout; | |
574 | wire [7:0] htc_thr_ra_valid_hw5; | |
575 | wire ra2pahit_st_lat_scanin; | |
576 | wire ra2pahit_st_lat_scanout; | |
577 | wire ra2pahit_lat_scanin; | |
578 | wire ra2pahit_lat_scanout; | |
579 | wire [7:0] ra2pahit_hw5; | |
580 | wire hw4_stg_lat1_scanin; | |
581 | wire hw4_stg_lat1_scanout; | |
582 | wire rr_read_tg0_hw5; | |
583 | wire rr_read_tg1_hw5; | |
584 | wire hw4_stg_lat2_scanin; | |
585 | wire hw4_stg_lat2_scanout; | |
586 | wire [7:0] tlb_wr_en; | |
587 | wire [7:0] mmu_reload_done_din; | |
588 | wire [7:0] i_tte_outofrange; | |
589 | wire [7:0] d_tte_outofrange; | |
590 | wire [7:0] final_ecc_err_hw5; | |
591 | wire [7:0] i_ecc_err; | |
592 | wire [7:0] d_ecc_err; | |
593 | wire stg_hw5_lat_scanin; | |
594 | wire stg_hw5_lat_scanout; | |
595 | wire outofrangemiss_lat_scanin; | |
596 | wire outofrangemiss_lat_scanout; | |
597 | wire final_ecc_err_lat_scanin; | |
598 | wire final_ecc_err_lat_scanout; | |
599 | wire err_type_lat_scanin; | |
600 | wire err_type_lat_scanout; | |
601 | wire err_index_lat_scanin; | |
602 | wire err_index_lat_scanout; | |
603 | wire [7:0] i_unauth_access; | |
604 | wire [7:0] i_tsb_miss; | |
605 | wire [7:0] d_tsb_miss; | |
606 | wire tsbmiss_lat_scanin; | |
607 | wire tsbmiss_lat_scanout; | |
608 | wire [5:0] l15_mmu_cpkt_unused; | |
609 | wire spares_scanin; | |
610 | wire spares_scanout; | |
611 | ||
612 | ||
613 | input l2clk; | |
614 | input scan_in; | |
615 | input tcu_pce_ov; // scan signals | |
616 | input spc_aclk; | |
617 | input spc_bclk; | |
618 | input tcu_scan_en; | |
619 | output scan_out; | |
620 | ||
621 | ||
622 | input lsu_mmu_pmen; | |
623 | input [7:0] spc_core_running_status; | |
624 | ||
625 | ||
626 | ||
627 | input [17:0] l15_mmu_cpkt; | |
628 | input l15_mmu_valid; | |
629 | ||
630 | // tsbptr requests | |
631 | input asi_tsb_ptr_req_valid; | |
632 | input [2:0] asi_tsb_ptr_req; | |
633 | input [1:0] asi_tsb_ptr_number; | |
634 | input asd0_zero_context; | |
635 | input asd1_zero_context; | |
636 | ||
637 | ||
638 | // partition id | |
639 | input [7:0] asi_wr_partition_id; | |
640 | input [2:0] asi_wr_data; | |
641 | ||
642 | // tsb prediction mode bits 00 - seq no pred, 01 - burst, 10 - seq with pred, 11 - burst | |
643 | input [1:0] asi_hwtw_config_0; | |
644 | input [1:0] asi_hwtw_config_1; | |
645 | input [1:0] asi_hwtw_config_2; | |
646 | input [1:0] asi_hwtw_config_3; | |
647 | input [1:0] asi_hwtw_config_4; | |
648 | input [1:0] asi_hwtw_config_5; | |
649 | input [1:0] asi_hwtw_config_6; | |
650 | input [1:0] asi_hwtw_config_7; | |
651 | ||
652 | //input mra0_data_38; | |
653 | //input mra1_data_38; | |
654 | //input mra0_data_77; | |
655 | //input mra1_data_77; | |
656 | ||
657 | input [1:0] asi_tsb_hwtw_enable_0; // tg0 | |
658 | input [1:0] asi_tsb_hwtw_enable_1; // tg1 | |
659 | ||
660 | ||
661 | ||
662 | // *** HTC_DP Interface *** | |
663 | input htd_ra2pa_lower_hit_hw4; | |
664 | input htd_ra2pa_upper_hit_hw4; | |
665 | input htd_razero_hw4; | |
666 | ||
667 | ||
668 | input htd_range_en_hw4; | |
669 | ||
670 | input [7:0] htd_zeroctx_m0; // zero context indicator | |
671 | ||
672 | ||
673 | input htd_zeroctx_hw1; // ignore context on return data | |
674 | input htd_usectx0_hw1; // ignore context on return data | |
675 | input htd_usectx1_hw1; // ignore context on return data | |
676 | input htd_ranotpa_hw1; | |
677 | input htd_ptr_hit0_hw1; // partial VPN(37:22) of rcvd TTE matches with VPN of request recvd | |
678 | input htd_ptr_hit1_hw1; // partial VPN(47:38) of rcvd TTE matches with VPN of request recvd | |
679 | input htd_ptr_hit2_hw1; // VPN(47) of rcvd TTE matches with VPN[63:48] | |
680 | input htd_ctx_hit_hw1; // CTX of of rcvd TTE matches with CTX of request recvd | |
681 | input htd_tte_ep_hw1; // EP bit from TTE | |
682 | input htd_dmiss_hw1; // dmiss for the thread whose tte is being returned | |
683 | ||
684 | ||
685 | input [5:0] htd_pred0_idx_m0; | |
686 | input [5:0] htd_pred1_idx_m0; | |
687 | ||
688 | input [15:0] htd_pred0_m0; | |
689 | input [15:0] htd_pred1_m0; | |
690 | ||
691 | ||
692 | input [7:0] htd_dmiss; // Dmiss indicator from htd queue | |
693 | input [7:0] htd_sec_ctx; // Secondary context indicator from htd queue | |
694 | ||
695 | ||
696 | ||
697 | // *** TLU Interface for ITLB/DTLB Miss *** | |
698 | input [7:0] tlu_iht_request; | |
699 | input [7:0] tlu_dht_request; | |
700 | ||
701 | ||
702 | // *** Gasket/L15 Interface *** | |
703 | input l15_mmu_grant; | |
704 | ||
705 | input asi_mra_req_grant; | |
706 | ||
707 | // TLB Miss State Machine & TLB Reg Control State Machine Interface | |
708 | input [7:0] tsm_rqv; | |
709 | input [7:0] tsm_tsb_miss_hw2; | |
710 | ||
711 | input [7:0] trs_rqv; | |
712 | input [7:0] trs_null_st; | |
713 | input [7:0] trs_waitrr3_st; | |
714 | input [7:0] trs_ecc_err; | |
715 | input [7:0] trs_ep_err; | |
716 | ||
717 | // ECC interface | |
718 | input mel0_parity_err; | |
719 | input mel1_parity_err; | |
720 | ||
721 | ||
722 | input [2:0] trs0_err_type; | |
723 | input [2:0] trs1_err_type; | |
724 | input [2:0] trs2_err_type; | |
725 | input [2:0] trs3_err_type; | |
726 | input [2:0] trs4_err_type; | |
727 | input [2:0] trs5_err_type; | |
728 | input [2:0] trs6_err_type; | |
729 | input [2:0] trs7_err_type; | |
730 | ||
731 | input [2:0] trs0_err_index; | |
732 | input [2:0] trs1_err_index; | |
733 | input [2:0] trs2_err_index; | |
734 | input [2:0] trs3_err_index; | |
735 | input [2:0] trs4_err_index; | |
736 | input [2:0] trs5_err_index; | |
737 | input [2:0] trs6_err_index; | |
738 | input [2:0] trs7_err_index; | |
739 | ||
740 | ||
741 | input tlu_cerer_hwtwl2; // record enable bit of L2 errors | |
742 | input tlu_cerer_hwtwmu; // record enable bit for mra uncorrectable | |
743 | ||
744 | ||
745 | output [7:0] htc_core_running; | |
746 | output htc_m1_clken; | |
747 | output htc_hw3_clken; | |
748 | output htc_hw4_clken; | |
749 | ||
750 | ||
751 | output [7:0] mmu_i_unauth_access; // I-TSB has EP off, tsm goes to NULL | |
752 | output [7:0] mmu_i_tsb_miss; // I-TSB Miss indication going to TLU, tsm goes to NULL | |
753 | output [7:0] mmu_d_tsb_miss; // D-TSB Miss indication going to TLU, tsm goes to NULL | |
754 | output [7:0] mmu_reload_done; //Successful write of TLB registers with correct TTE | |
755 | //Not asserted if TSB Miss occurs | |
756 | output mmu_use_context_0; // new use_context_0 and 1 bits. | |
757 | output mmu_use_context_1; | |
758 | output mmu_sec_context; | |
759 | ||
760 | ||
761 | ||
762 | // *** MMU Reg. Array Interface *** | |
763 | output [4:0] htc_mra_addr_in; // Address for mra read | |
764 | output [1:0] htc_mra_rd_en; // Read TSB Conf/RR,Offset Register | |
765 | ||
766 | output [7:0] htc_wr_itlb_data_in; // Enable for writing to ITLB DATAIN register | |
767 | output [7:0] htc_wr_dtlb_data_in; // Enable for writing to DTLB DATAIN register | |
768 | output [7:0] htc_dtlb_clken; | |
769 | output [7:0] htc_itlb_clken; | |
770 | ||
771 | ||
772 | output htc_zero_ctx_m2; // ignore context of request recvd, saved in htd queue | |
773 | ||
774 | output [5:3] htc_upd_pred_idx_hw2; | |
775 | output [7:0] htc_upd_grp; | |
776 | output [7:0] htc_upd_grp_x; | |
777 | output [1:0] htc_new_pred_bit; | |
778 | ||
779 | ||
780 | ||
781 | output htc_wrpred0_hw2; | |
782 | output htc_wrpred1_hw2; | |
783 | output htc_wrpred2_hw2; | |
784 | output htc_wrpred3_hw2; | |
785 | ||
786 | ||
787 | ||
788 | output [7:0] htc_tlb_miss_m; | |
789 | ||
790 | ||
791 | ||
792 | // pkt sent to gkt | |
793 | output [4:0] mmu_l15_cpkt; | |
794 | output htc_l15_en; | |
795 | output mmu_l15_valid; | |
796 | ||
797 | ||
798 | // buffer ctl signals | |
799 | output htc_wr_q0new_nogrant; | |
800 | output htc_wr_q0new_grant; | |
801 | output htc_wr_q1new; | |
802 | output htc_shift_q1_grant; | |
803 | output htc_wr_m3new; | |
804 | output htc_wr_m3q0; | |
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | output htc_mra_sel_0; | |
811 | output htc_sel_mra_lo; | |
812 | ||
813 | ||
814 | ||
815 | output [1:0] htc_conf_index_m2; // conf_index used to latch tsb config data | |
816 | output [7:0] htc_vld_tsbptr_m2; // valid tsbptr being sent to gkt | |
817 | output [7:0] htc_rd_tteq; // used to mux out the data returned, which is saved in queue in htd | |
818 | ||
819 | ||
820 | output [7:0] htc_ra2pahit_hw5; | |
821 | output [7:0] htc_ranotpax_hw5; | |
822 | ||
823 | // index signals to tsm/trs | |
824 | ||
825 | output [7:0] htc_cindex_bit0; | |
826 | output [7:0] htc_cindex_bit1; | |
827 | output [7:0] htc_rrindex_bit0; | |
828 | output [7:0] htc_rrindex_bit1; | |
829 | ||
830 | ||
831 | // interface to htd | |
832 | ||
833 | ||
834 | output [2:0] htc_pid0_m0; | |
835 | output [2:0] htc_pid1_m0; | |
836 | ||
837 | output [7:0] htc_tsbrd_valid_m0; | |
838 | ||
839 | ||
840 | output [7:0] htc_thr_valid_hw3; | |
841 | output [7:0] htc_thr_prevalid_hw3; | |
842 | output [7:0] htc_va_rd_m2_in; | |
843 | output htc_ranotpa_hw4; | |
844 | ||
845 | output [7:0] htc_data_rcvd_hw1; | |
846 | ||
847 | output [7:0] htc_tsb_hit_hw1; | |
848 | output [7:0] htc_tsb_done_hw2; | |
849 | output [7:0] htc_thr_valid_m1; // valid req in m1, which has asi_grant and gkt_room_avail | |
850 | output [7:0] htc_thr_valid_m0; // valid req in m0 | |
851 | ||
852 | output [7:0] htc_hwtw_burst; | |
853 | ||
854 | ||
855 | output [7:0] mmu_i_tte_outofrange; | |
856 | output [7:0] mmu_d_tte_outofrange; | |
857 | ||
858 | ||
859 | output [1:0] rr_ecc_err_type; | |
860 | output [1:0] cfg_ecc_err_type; | |
861 | output [1:0] l2_ecc_err_type; | |
862 | output [7:0] rr_ecc_err_hw5; | |
863 | output [7:0] cfg_ecc_err_m3; | |
864 | output [7:0] l2_ecc_err_hw1; | |
865 | ||
866 | output [7:0] htc_ep_miss_hw1; | |
867 | ||
868 | output [2:0] cfg_ecc_err_index; | |
869 | output [2:0] rr_ecc_err_index; | |
870 | ||
871 | ||
872 | ||
873 | output [7:0] mmu_i_eccerr; | |
874 | output [7:0] mmu_d_eccerr; | |
875 | ||
876 | output [7:0] mmu_i_l2cerr; | |
877 | output [7:0] mmu_d_l2cerr; | |
878 | ||
879 | output [2:0] htc_thr0_err_type; | |
880 | output [2:0] htc_thr1_err_type; | |
881 | output [2:0] htc_thr2_err_type; | |
882 | output [2:0] htc_thr3_err_type; | |
883 | output [2:0] htc_thr4_err_type; | |
884 | output [2:0] htc_thr5_err_type; | |
885 | output [2:0] htc_thr6_err_type; | |
886 | output [2:0] htc_thr7_err_type; | |
887 | ||
888 | output [2:0] htc_thr0_err_index; | |
889 | output [2:0] htc_thr1_err_index; | |
890 | output [2:0] htc_thr2_err_index; | |
891 | output [2:0] htc_thr3_err_index; | |
892 | output [2:0] htc_thr4_err_index; | |
893 | output [2:0] htc_thr5_err_index; | |
894 | output [2:0] htc_thr6_err_index; | |
895 | output [2:0] htc_thr7_err_index; | |
896 | ||
897 | // output pmu signals | |
898 | ||
899 | output mmu_pmu_l2ret; | |
900 | output mmu_pmu_l2miss; | |
901 | output mmu_pmu_dtlb; | |
902 | output [2:0] mmu_pmu_tid; | |
903 | ||
904 | input spc_aclk_wmr; // Warm reset (non)scan | |
905 | input wmr_scan_in; | |
906 | ||
907 | output wmr_scan_out; // Warm reset (non)scan | |
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | assign htc_hwtw_mode_0[7:0] = {asi_hwtw_config_7[0],asi_hwtw_config_6[0],asi_hwtw_config_5[0],asi_hwtw_config_4[0], | |
914 | asi_hwtw_config_3[0],asi_hwtw_config_2[0],asi_hwtw_config_1[0],asi_hwtw_config_0[0]}; | |
915 | assign htc_hwtw_mode_1[7:0] = {asi_hwtw_config_7[1],asi_hwtw_config_6[1],asi_hwtw_config_5[1],asi_hwtw_config_4[1], | |
916 | asi_hwtw_config_3[1],asi_hwtw_config_2[1],asi_hwtw_config_1[1],asi_hwtw_config_0[1]}; | |
917 | ||
918 | assign htc_hwtw_burst[7:0] = htc_hwtw_mode_0[7:0]; | |
919 | assign htc_hwtw_pred[7:0] = ~htc_hwtw_mode_0[7:0] & htc_hwtw_mode_1[7:0]; | |
920 | ||
921 | ||
922 | /////////////////////////////////////////////////// | |
923 | // clock header | |
924 | /////////////////////////////////////////////////// | |
925 | mmu_htc_ctl_l1clkhdr_ctl_macro clkgen | |
926 | ( | |
927 | .l2clk(l2clk), | |
928 | .l1en (1'b1 ), | |
929 | .l1clk(l1clk), | |
930 | .pce_ov(pce_ov), | |
931 | .stop(stop), | |
932 | .se(se) | |
933 | ); | |
934 | ||
935 | // scan renames | |
936 | assign pce_ov = tcu_pce_ov; | |
937 | assign stop = 1'b0; | |
938 | assign siclk = spc_aclk; | |
939 | assign soclk = spc_bclk; | |
940 | assign se = tcu_scan_en; | |
941 | ||
942 | // end scan | |
943 | ||
944 | mmu_htc_ctl_msff_ctl_macro__width_9 pmen_reg | |
945 | ( | |
946 | .scan_in(pmen_reg_scanin), | |
947 | .scan_out(pmen_reg_scanout), | |
948 | .l1clk (l1clk), | |
949 | .din ({lsu_mmu_pmen,spc_core_running_status[7:0]}), | |
950 | .dout ({htc_mmu_pmen,htc_core_running[7:0]}), | |
951 | .siclk(siclk), | |
952 | .soclk(soclk) | |
953 | ); | |
954 | ||
955 | ||
956 | // flop htd_dmiss | |
957 | mmu_htc_ctl_msff_ctl_macro__width_16 tlb_miss_lat | |
958 | ( | |
959 | .scan_in(tlb_miss_lat_scanin), | |
960 | .scan_out(tlb_miss_lat_scanout), | |
961 | .l1clk( l1clk ), | |
962 | .din ({htc_tlb_miss_m[7:0], htd_dmiss[7:0]}), | |
963 | .dout ({htc_tlb_miss_m0[7:0], htd_dmiss_lat[7:0]}), | |
964 | .siclk(siclk), | |
965 | .soclk(soclk) | |
966 | ); | |
967 | ||
968 | ||
969 | mmu_htc_ctl_msff_ctl_macro__width_2 tlb_cerer_lat | |
970 | ( | |
971 | .scan_in(tlb_cerer_lat_scanin), | |
972 | .scan_out(tlb_cerer_lat_scanout), | |
973 | .l1clk( l1clk ), | |
974 | .din ({tlu_cerer_hwtwl2,tlu_cerer_hwtwmu}), | |
975 | .dout ({hwtwl2_en, hwtwmu_en}), | |
976 | .siclk(siclk), | |
977 | .soclk(soclk) | |
978 | ); | |
979 | ||
980 | ||
981 | // latch the partition id for each thread. | |
982 | assign pid0_in[2:0] = ({3{asi_wr_partition_id[0]}} & asi_wr_data[2:0]) | | |
983 | ({3{~asi_wr_partition_id[0]}} & pid0[2:0]); | |
984 | ||
985 | assign pid1_in[2:0] = ({3{asi_wr_partition_id[1]}} & asi_wr_data[2:0]) | | |
986 | ({3{~asi_wr_partition_id[1]}} & pid1[2:0]); | |
987 | ||
988 | assign pid2_in[2:0] = ({3{asi_wr_partition_id[2]}} & asi_wr_data[2:0]) | | |
989 | ({3{~asi_wr_partition_id[2]}} & pid2[2:0]); | |
990 | ||
991 | assign pid3_in[2:0] = ({3{asi_wr_partition_id[3]}} & asi_wr_data[2:0]) | | |
992 | ({3{~asi_wr_partition_id[3]}} & pid3[2:0]); | |
993 | ||
994 | assign pid4_in[2:0] = ({3{asi_wr_partition_id[4]}} & asi_wr_data[2:0]) | | |
995 | ({3{~asi_wr_partition_id[4]}} & pid4[2:0]); | |
996 | ||
997 | assign pid5_in[2:0] = ({3{asi_wr_partition_id[5]}} & asi_wr_data[2:0]) | | |
998 | ({3{~asi_wr_partition_id[5]}} & pid5[2:0]); | |
999 | ||
1000 | assign pid6_in[2:0] = ({3{asi_wr_partition_id[6]}} & asi_wr_data[2:0]) | | |
1001 | ({3{~asi_wr_partition_id[6]}} & pid6[2:0]); | |
1002 | ||
1003 | assign pid7_in[2:0] = ({3{asi_wr_partition_id[7]}} & asi_wr_data[2:0]) | | |
1004 | ({3{~asi_wr_partition_id[7]}} & pid7[2:0]); | |
1005 | ||
1006 | mmu_htc_ctl_msff_ctl_macro__width_3 pid0_lat (// FS:wmr_protect | |
1007 | .scan_in(pid0_lat_wmr_scanin), | |
1008 | .scan_out(pid0_lat_wmr_scanout), | |
1009 | .siclk(spc_aclk_wmr), | |
1010 | .l1clk( l1clk), | |
1011 | .din ({pid0_in[2:0]}), | |
1012 | .dout ({pid0[2:0]}), | |
1013 | .soclk(soclk) | |
1014 | ); | |
1015 | ||
1016 | mmu_htc_ctl_msff_ctl_macro__width_3 pid1_lat (// FS:wmr_protect | |
1017 | .scan_in(pid1_lat_wmr_scanin), | |
1018 | .scan_out(pid1_lat_wmr_scanout), | |
1019 | .siclk(spc_aclk_wmr), | |
1020 | .l1clk( l1clk), | |
1021 | .din ({pid1_in[2:0]}), | |
1022 | .dout ({pid1[2:0]}), | |
1023 | .soclk(soclk) | |
1024 | ); | |
1025 | ||
1026 | mmu_htc_ctl_msff_ctl_macro__width_3 pid2_lat (// FS:wmr_protect | |
1027 | .scan_in(pid2_lat_wmr_scanin), | |
1028 | .scan_out(pid2_lat_wmr_scanout), | |
1029 | .siclk(spc_aclk_wmr), | |
1030 | .l1clk( l1clk), | |
1031 | .din ({pid2_in[2:0]}), | |
1032 | .dout ({pid2[2:0]}), | |
1033 | .soclk(soclk) | |
1034 | ); | |
1035 | ||
1036 | mmu_htc_ctl_msff_ctl_macro__width_3 pid3_lat (// FS:wmr_protect | |
1037 | .scan_in(pid3_lat_wmr_scanin), | |
1038 | .scan_out(pid3_lat_wmr_scanout), | |
1039 | .siclk(spc_aclk_wmr), | |
1040 | .l1clk( l1clk), | |
1041 | .din ({pid3_in[2:0]}), | |
1042 | .dout ({pid3[2:0]}), | |
1043 | .soclk(soclk) | |
1044 | ); | |
1045 | ||
1046 | mmu_htc_ctl_msff_ctl_macro__width_3 pid4_lat (// FS:wmr_protect | |
1047 | .scan_in(pid4_lat_wmr_scanin), | |
1048 | .scan_out(pid4_lat_wmr_scanout), | |
1049 | .siclk(spc_aclk_wmr), | |
1050 | .l1clk( l1clk), | |
1051 | .din ({pid4_in[2:0]}), | |
1052 | .dout ({pid4[2:0]}), | |
1053 | .soclk(soclk) | |
1054 | ); | |
1055 | ||
1056 | mmu_htc_ctl_msff_ctl_macro__width_3 pid5_lat (// FS:wmr_protect | |
1057 | .scan_in(pid5_lat_wmr_scanin), | |
1058 | .scan_out(pid5_lat_wmr_scanout), | |
1059 | .siclk(spc_aclk_wmr), | |
1060 | .l1clk( l1clk), | |
1061 | .din ({pid5_in[2:0]}), | |
1062 | .dout ({pid5[2:0]}), | |
1063 | .soclk(soclk) | |
1064 | ); | |
1065 | ||
1066 | mmu_htc_ctl_msff_ctl_macro__width_3 pid6_lat (// FS:wmr_protect | |
1067 | .scan_in(pid6_lat_wmr_scanin), | |
1068 | .scan_out(pid6_lat_wmr_scanout), | |
1069 | .siclk(spc_aclk_wmr), | |
1070 | .l1clk( l1clk), | |
1071 | .din ({pid6_in[2:0]}), | |
1072 | .dout ({pid6[2:0]}), | |
1073 | .soclk(soclk) | |
1074 | ); | |
1075 | ||
1076 | mmu_htc_ctl_msff_ctl_macro__width_3 pid7_lat (// FS:wmr_protect | |
1077 | .scan_in(pid7_lat_wmr_scanin), | |
1078 | .scan_out(pid7_lat_wmr_scanout), | |
1079 | .siclk(spc_aclk_wmr), | |
1080 | .l1clk( l1clk), | |
1081 | .din ({pid7_in[2:0]}), | |
1082 | .dout ({pid7[2:0]}), | |
1083 | .soclk(soclk) | |
1084 | ); | |
1085 | ||
1086 | ||
1087 | // mra ecc errors | |
1088 | /////////////////////////////////////////////////// | |
1089 | // Set the ECC ERROR TYPE | |
1090 | // 110 MRA Correctable | |
1091 | // 101 MRA Uncorrectable | |
1092 | // 001 L2 correctable | |
1093 | // 010 L2 uncorrectable | |
1094 | // 011 L2 Not Data | |
1095 | // latch the first ecc error and hold it. | |
1096 | /////////////////////////////////////////////////// | |
1097 | //assign mra0_ecc_err = (med0_cecc & hwtwmc_en) | (med0_uecc & hwtwmu_en); | |
1098 | //assign mra1_ecc_err = (med1_cecc & hwtwmc_en) | (med1_uecc & hwtwmu_en); | |
1099 | //assign mra0_err_type[1:0] = {(med0_cecc & hwtwmc_en),(med0_uecc & hwtwmu_en)}; | |
1100 | //assign mra1_err_type[1:0] = {(med1_cecc & hwtwmc_en),(med1_uecc & hwtwmu_en)}; | |
1101 | ||
1102 | ||
1103 | ||
1104 | ///////////////////////////////////////////////////////////////////// | |
1105 | // | |
1106 | // | Update TTE | Req. Arb. | MRA Access | TSB Ptr Gen. | TTE Req to LSU | | |
1107 | // | Request Q | Cfg. Rd. | Cycle | | | | |
1108 | // | | to MRA | | | | | |
1109 | // | | | | | | | |
1110 | // | M | M0 | M1 | M2 | M3 | | |
1111 | // | |
1112 | ///////////////////////////////////////////////////////////////////// | |
1113 | ||
1114 | ///////////////////////////////////////////////////////////////////// | |
1115 | // TTE Request Queue Controls (M) | |
1116 | ///////////////////////////////////////////////////////////////////// | |
1117 | assign htc_tlb_miss_m[7:0] = tlu_iht_request[7:0] | tlu_dht_request[7:0]; | |
1118 | ||
1119 | // mux out the pid for two thread groups in M0 | |
1120 | ||
1121 | assign htc_pid0_m0[2:0] = ({3{htc_tlb_miss_m0[0]}} & pid0[2:0]) | | |
1122 | ({3{htc_tlb_miss_m0[1]}} & pid1[2:0]) | | |
1123 | ({3{htc_tlb_miss_m0[2]}} & pid2[2:0]) | | |
1124 | ({3{htc_tlb_miss_m0[3]}} & pid3[2:0]); | |
1125 | ||
1126 | assign htc_pid1_m0[2:0] = ({3{htc_tlb_miss_m0[4]}} & pid4[2:0]) | | |
1127 | ({3{htc_tlb_miss_m0[5]}} & pid5[2:0]) | | |
1128 | ({3{htc_tlb_miss_m0[6]}} & pid6[2:0]) | | |
1129 | ({3{htc_tlb_miss_m0[7]}} & pid7[2:0]); | |
1130 | ||
1131 | ||
1132 | ///////////////////////////////////////////////////////////////////// | |
1133 | // Request Arbitration (M0) | |
1134 | // Confg. Reg. Read Req to MRA | |
1135 | ///////////////////////////////////////////////////////////////////// | |
1136 | // ARBITRATION logic | |
1137 | // Every cycle, at most one thread is selected for accessing MRA. | |
1138 | // Threads could be accessing MRA for TSB config read on tlb miss, or | |
1139 | // Range register read when tte comes back. | |
1140 | ||
1141 | // Threads requesting range register read are (trs_reqv) are given higher priority | |
1142 | // than threads requesting tsb config (tsm_rqv). | |
1143 | ||
1144 | // Threads requesting range register read are prioritized statically with thread | |
1145 | // 0 having highest priority and thread 7 having least. There is no issue about | |
1146 | // live lock, because all threads requesting RR would have to be completed before | |
1147 | // a new thread can request a tsb. And a thread cannot request a RR until it has | |
1148 | // gone through the process of reading TSB and fetching TTE from L2. | |
1149 | ||
1150 | // Threads requesting TSB config cannot be statically prioritized because it can | |
1151 | // lead to a potential live lock. If all threads are missing in TLB at all times, | |
1152 | // Thread 0 can read TSB, get TTE, read RR, and get another TLB miss, before THR 7 | |
1153 | // has had a chance to go out and read its TSB config. So we cannot use static priority | |
1154 | // for TSB config reads. | |
1155 | ||
1156 | // TSB config reads will be prioritized by dividing the threads into 2 groups. | |
1157 | // A single favor bit will select alternatingly between the 2 groups. | |
1158 | // Within a group, the threads will be prioritized based on a 4-bit rotating pointer. | |
1159 | // The pointer always points to the thread with highest priority, and it gets updated | |
1160 | // when a thread gets selected. The pointer updates such that the selected thread will | |
1161 | // have the least priority. | |
1162 | ||
1163 | assign tsm_sel[0] = (tsm_ptr0[1] & ~tsm_rqv[1] & ~tsm_rqv[2] & ~tsm_rqv[3] & tsm_rqv[0]) | | |
1164 | (tsm_ptr0[2] & ~tsm_rqv[2] & ~tsm_rqv[3] & tsm_rqv[0]) | | |
1165 | (tsm_ptr0[3] & ~tsm_rqv[3] & tsm_rqv[0]) | | |
1166 | (tsm_ptr0[0] & tsm_rqv[0]); | |
1167 | ||
1168 | ||
1169 | ||
1170 | assign tsm_sel[1] = (tsm_ptr0[2] & ~tsm_rqv[2] & ~tsm_rqv[3] & ~tsm_rqv[0] & tsm_rqv[1]) | | |
1171 | (tsm_ptr0[3] & ~tsm_rqv[3] & ~tsm_rqv[0] & tsm_rqv[1]) | | |
1172 | (tsm_ptr0[0] & ~tsm_rqv[0] & tsm_rqv[1]) | | |
1173 | (tsm_ptr0[1] & tsm_rqv[1]); | |
1174 | ||
1175 | ||
1176 | assign tsm_sel[2] = (tsm_ptr0[3] & ~tsm_rqv[3] & ~tsm_rqv[0] & ~tsm_rqv[1] & tsm_rqv[2]) | | |
1177 | (tsm_ptr0[0] & ~tsm_rqv[0] & ~tsm_rqv[1] & tsm_rqv[2]) | | |
1178 | (tsm_ptr0[1] & ~tsm_rqv[1] & tsm_rqv[2]) | | |
1179 | (tsm_ptr0[2] & tsm_rqv[2]); | |
1180 | ||
1181 | assign tsm_sel[3] = (tsm_ptr0[0] & ~tsm_rqv[0] & ~tsm_rqv[1] & ~tsm_rqv[2] & tsm_rqv[3]) | | |
1182 | (tsm_ptr0[1] & ~tsm_rqv[1] & ~tsm_rqv[2] & tsm_rqv[3]) | | |
1183 | (tsm_ptr0[2] & ~tsm_rqv[2] & tsm_rqv[3]) | | |
1184 | (tsm_ptr0[3] & tsm_rqv[3]); | |
1185 | ||
1186 | ||
1187 | ||
1188 | assign tsm_sel[4] = (tsm_ptr1[5] & ~tsm_rqv[5] & ~tsm_rqv[6] & ~tsm_rqv[7] & tsm_rqv[4]) | | |
1189 | (tsm_ptr1[6] & ~tsm_rqv[6] & ~tsm_rqv[7] & tsm_rqv[4]) | | |
1190 | (tsm_ptr1[7] & ~tsm_rqv[7] & tsm_rqv[4]) | | |
1191 | (tsm_ptr1[4] & tsm_rqv[4]); | |
1192 | ||
1193 | assign tsm_sel[5] = (tsm_ptr1[6] & ~tsm_rqv[6] & ~tsm_rqv[7] & ~tsm_rqv[4] & tsm_rqv[5]) | | |
1194 | (tsm_ptr1[7] & ~tsm_rqv[7] & ~tsm_rqv[4] & tsm_rqv[5]) | | |
1195 | (tsm_ptr1[4] & ~tsm_rqv[4] & tsm_rqv[5]) | | |
1196 | (tsm_ptr1[5] & tsm_rqv[5]); | |
1197 | ||
1198 | assign tsm_sel[6] = (tsm_ptr1[7] & ~tsm_rqv[7] & ~tsm_rqv[4] & ~tsm_rqv[5] & tsm_rqv[6]) | | |
1199 | (tsm_ptr1[4] & ~tsm_rqv[4] & ~tsm_rqv[5] & tsm_rqv[6]) | | |
1200 | (tsm_ptr1[5] & ~tsm_rqv[5] & tsm_rqv[6]) | | |
1201 | (tsm_ptr1[6] & tsm_rqv[6]); | |
1202 | ||
1203 | assign tsm_sel[7] = (tsm_ptr1[4] & ~tsm_rqv[4] & ~tsm_rqv[5] & ~tsm_rqv[6] & tsm_rqv[7]) | | |
1204 | (tsm_ptr1[5] & ~tsm_rqv[5] & ~tsm_rqv[6] & tsm_rqv[7]) | | |
1205 | (tsm_ptr1[6] & ~tsm_rqv[6] & tsm_rqv[7]) | | |
1206 | (tsm_ptr1[7] & tsm_rqv[7]); | |
1207 | ||
1208 | assign tg0_valid = |(tsm_rqv[3:0]); | |
1209 | assign tg1_valid = |(tsm_rqv[7:4]); | |
1210 | ||
1211 | assign sel_tg1 = (favor_tg1 & tg1_valid) | ~tg0_valid; | |
1212 | ||
1213 | assign tsm_thrsel_m0[7:0] = sel_tg1? ({tsm_sel[7:4],4'b0000}): ({4'b0000,tsm_sel[3:0]}); | |
1214 | ||
1215 | ||
1216 | assign trs_thrsel_hw2[0] = trs_rqv[0]; | |
1217 | assign trs_thrsel_hw2[1] = trs_rqv[1] & ~trs_rqv[0]; | |
1218 | assign trs_thrsel_hw2[2] = trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1219 | assign trs_thrsel_hw2[3] = trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1220 | assign trs_thrsel_hw2[4] = trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1221 | assign trs_thrsel_hw2[5] = trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1222 | assign trs_thrsel_hw2[6] = trs_rqv[6] & ~trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1223 | assign trs_thrsel_hw2[7] = trs_rqv[7] & ~trs_rqv[6] & ~trs_rqv[5] & ~trs_rqv[4] & ~trs_rqv[3] & ~trs_rqv[2] & ~trs_rqv[1] & ~trs_rqv[0]; | |
1224 | ||
1225 | assign tsm_thrsel_v = |(tsm_rqv[7:0]) & ~|(trs_rqv[7:0]); | |
1226 | assign trs_thrsel_v = |(trs_rqv[7:0]); | |
1227 | ||
1228 | assign tsm_valid_m0[7:0] = tsm_thrsel_m0[7:0] & ({8{tsm_thrsel_v}}); | |
1229 | assign trs_valid_hw2[7:0] = trs_thrsel_hw2[7:0] & ({8{trs_thrsel_v}}); | |
1230 | ||
1231 | ||
1232 | ||
1233 | //0in bits_on -var {tsm_valid_m0[7:0],trs_valid_hw2[7:0]} -max 1 | |
1234 | //0in bits_on -var {tsm_sel[3:0]} -max 1 | |
1235 | //0in bits_on -var {tsm_sel[7:4]} -max 1 | |
1236 | ||
1237 | // update the favor bit based on the thread group selected | |
1238 | // it is possible that none of the thread groups got selected | |
1239 | ||
1240 | assign tsm_tg0_selected = |(tsm_valid_m0[3:0]); | |
1241 | assign tsm_tg1_selected = |(tsm_valid_m0[7:4]); | |
1242 | ||
1243 | assign favor_tg1_in = (favor_tg1 & ~tsm_tg1_selected) | tsm_tg0_selected; | |
1244 | ||
1245 | mmu_htc_ctl_msff_ctl_macro__width_1 favour_bit_reg ( | |
1246 | .scan_in(favour_bit_reg_scanin), | |
1247 | .scan_out(favour_bit_reg_scanout), | |
1248 | .l1clk( l1clk ), | |
1249 | .din (favor_tg1_in), | |
1250 | .dout (favor_tg1), | |
1251 | .siclk(siclk), | |
1252 | .soclk(soclk) | |
1253 | ); | |
1254 | ||
1255 | // update the tg0/tg1 pointers | |
1256 | assign tsm_ptr0_in[3:0] = tsm_tg0_selected ? ({tsm_valid_m0[2:0],tsm_valid_m0[3]}): tsm_ptr0[3:0]; | |
1257 | assign tsm_ptr1_in[7:4] = tsm_tg1_selected ? ({tsm_valid_m0[6:4],tsm_valid_m0[7]}): tsm_ptr1[7:4]; | |
1258 | ||
1259 | assign tsm_ptr0_in_0_ = ~tsm_ptr0_in[0]; | |
1260 | assign tsm_ptr1_in_4_ = ~tsm_ptr1_in[4]; | |
1261 | ||
1262 | mmu_htc_ctl_msff_ctl_macro__width_4 ptr0_reg ( | |
1263 | .scan_in(ptr0_reg_scanin), | |
1264 | .scan_out(ptr0_reg_scanout), | |
1265 | .l1clk( l1clk ), | |
1266 | .din ({tsm_ptr0_in[3:1],tsm_ptr0_in_0_}), | |
1267 | .dout ({tsm_ptr0[3:1],tsm_ptr0_0_}), | |
1268 | .siclk(siclk), | |
1269 | .soclk(soclk) | |
1270 | ); | |
1271 | ||
1272 | mmu_htc_ctl_msff_ctl_macro__width_4 ptr1_reg ( | |
1273 | .scan_in(ptr1_reg_scanin), | |
1274 | .scan_out(ptr1_reg_scanout), | |
1275 | .l1clk( l1clk ), | |
1276 | .din ({tsm_ptr1_in[7:5],tsm_ptr1_in_4_}), | |
1277 | .dout ({tsm_ptr1[7:5],tsm_ptr1_4_}), | |
1278 | .siclk(siclk), | |
1279 | .soclk(soclk) | |
1280 | ); | |
1281 | ||
1282 | assign tsm_ptr0[0] = ~tsm_ptr0_0_; | |
1283 | assign tsm_ptr1[4] = ~tsm_ptr1_4_; | |
1284 | ||
1285 | ||
1286 | // *************************************************************** // | |
1287 | // Context Value Decode | |
1288 | // *************************************************************** // | |
1289 | //assign zero_ctx = ~|htd_ctx_sel_m0[12:00]; | |
1290 | ||
1291 | assign zero_ctx = |(tsm_thrsel_m0[7:0] & htd_zeroctx_m0[7:0]); | |
1292 | ||
1293 | //******************************************************************************** | |
1294 | // Configuration Register Index | |
1295 | // Increment the index on every grant, else hold. | |
1296 | //******************************************************************************** | |
1297 | ||
1298 | //assign incr_cindex0[1:0] =({2{~cindex0[01] & ~cindex0[00]}} & 2'b01) | | |
1299 | // ({2{~cindex0[01] & cindex0[00]}} & 2'b10) | | |
1300 | // ({2{ cindex0[01] & ~cindex0[00]}} & 2'b11) | | |
1301 | // ({2{ cindex0[01] & cindex0[00]}} & 2'b00) ; | |
1302 | ||
1303 | //assign next_cindex0[1:0] = ({2{thr_valid_m1[0]}} & incr_cindex0[1:0]) | | |
1304 | // ({2{tlb_miss_m0[0]}} & 2'b00) | | |
1305 | // ({2{(~tlb_miss_m0[0] & ~thr_valid_m1[0])}} & cindex0[1:0]); | |
1306 | ||
1307 | assign incr_cindex_bit0[7:0] = ~htc_cindex_bit0[7:0]; | |
1308 | assign incr_cindex_bit1[7:0] = htc_cindex_bit1[7:0] ^ htc_cindex_bit0[7:0]; | |
1309 | ||
1310 | assign next_cindex_bit0[7:0] = (htc_thr_valid_m1[7:0] & incr_cindex_bit0[7:0]) | | |
1311 | (htc_tlb_miss_m0[7:0] & 8'b0) | | |
1312 | (~htc_thr_valid_m1[7:0] & ~htc_tlb_miss_m0[7:0] & htc_cindex_bit0[7:0]); | |
1313 | ||
1314 | assign next_cindex_bit1[7:0] = (htc_thr_valid_m1[7:0] & incr_cindex_bit1[7:0]) | | |
1315 | (htc_tlb_miss_m0[7:0] & 8'b0) | | |
1316 | (~htc_thr_valid_m1[7:0] & ~htc_tlb_miss_m0[7:0] & htc_cindex_bit1[7:0]); | |
1317 | ||
1318 | ||
1319 | ||
1320 | mmu_htc_ctl_msff_ctl_macro__width_16 conf_idx_reg ( | |
1321 | .scan_in(conf_idx_reg_scanin), | |
1322 | .scan_out(conf_idx_reg_scanout), | |
1323 | .l1clk(l1clk), | |
1324 | .din ({next_cindex_bit0[7:0],next_cindex_bit1[7:0]}), | |
1325 | .dout ({htc_cindex_bit0[7:0],htc_cindex_bit1[7:0]}), | |
1326 | .siclk(siclk), | |
1327 | .soclk(soclk) | |
1328 | ); | |
1329 | ||
1330 | ||
1331 | //******************************************************************************** | |
1332 | // RealRange Register Index | |
1333 | //******************************************************************************** | |
1334 | //assign incr_index[1:0] = ({2{~rrindex[01] & ~rrindex[00]}} & 2'b01) | | |
1335 | // ({2{~rrindex[01] & rrindex[00]}} & 2'b10) | | |
1336 | // ({2{ rrindex[01] & ~rrindex[00]}} & 2'b11) | | |
1337 | // ({2{ rrindex[01] & rrindex[00]}} & 2'b00) ; | |
1338 | // | |
1339 | //assign next_rrindex[1:0] = ({2{thr_valid_hw3}} & incr_index[1:0]) | | |
1340 | // ({2{null_state}} & 2'b00) | | |
1341 | // ({2{(~null_state & ~thr_valid_hw3)}} & rrindex[1:0]); | |
1342 | ||
1343 | ||
1344 | assign incr_rrindex_bit0[7:0] = ~htc_rrindex_bit0[7:0]; | |
1345 | assign incr_rrindex_bit1[7:0] = htc_rrindex_bit1[7:0] ^ htc_rrindex_bit0[7:0]; | |
1346 | ||
1347 | assign next_rrindex_bit0[7:0] = (htc_thr_valid_hw3[7:0] & incr_rrindex_bit0[7:0]) | | |
1348 | (trs_null_st[7:0] & 8'b0) | | |
1349 | (~htc_thr_valid_hw3[7:0] & ~trs_null_st[7:0] & htc_rrindex_bit0[7:0]); | |
1350 | ||
1351 | assign next_rrindex_bit1[7:0] = (htc_thr_valid_hw3[7:0] & incr_rrindex_bit1[7:0]) | | |
1352 | (trs_null_st[7:0] & 8'b0) | | |
1353 | (~htc_thr_valid_hw3[7:0] & ~trs_null_st[7:0] & htc_rrindex_bit1[7:0]); | |
1354 | ||
1355 | ||
1356 | ||
1357 | mmu_htc_ctl_msff_ctl_macro__width_16 rr_idx_reg ( | |
1358 | .scan_in(rr_idx_reg_scanin), | |
1359 | .scan_out(rr_idx_reg_scanout), | |
1360 | .l1clk(l1clk), | |
1361 | .din ({next_rrindex_bit0[7:0],next_rrindex_bit1[7:0]}), | |
1362 | .dout ({htc_rrindex_bit0[7:0],htc_rrindex_bit1[7:0]}), | |
1363 | .siclk(siclk), | |
1364 | .soclk(soclk) | |
1365 | ); | |
1366 | ||
1367 | ||
1368 | ||
1369 | //******************************************************************************** | |
1370 | // Read Configuration Register (M0) | |
1371 | //******************************************************************************** | |
1372 | // MRA Layout | |
1373 | // Bit 2 of tid[2:0] selects mra1/mra0 | |
1374 | // Bit tid[1:0] form address[4:3] of MRA_ADDR | |
1375 | // MRA_ADDR[2:0] Data | |
1376 | // | |
1377 | // 000 unused[3:0],z_tsb_conf_0[77:39],z_tsb_conf_1[38:0] | |
1378 | // 001 unused[3:0],z_tsb_conf_2[77:39],z_tsb_conf_3[38:0] | |
1379 | // 010 unused[3:0],nz_tsb_conf_0[77:39],nz_tsb_conf_1[38:0] | |
1380 | // 011 unused[3:0],nz_tsb_conf_2[77:39],nz_tsb_conf_3[38:0] | |
1381 | // 100 RR0[81:27],PhyOff0[25:0] | |
1382 | // 101 RR1[81:27],PhyOff1[25:0] | |
1383 | // 110 RR2[81:27],PhyOff2[25:0] | |
1384 | // 111 RR3[81:27],PhyOff3[25:0] | |
1385 | ||
1386 | assign conf_index[1:0] = ({next_cindex_bit1[0],next_cindex_bit0[0]} & {2{tsm_thrsel_m0[0]}}) | | |
1387 | ({next_cindex_bit1[1],next_cindex_bit0[1]} & {2{tsm_thrsel_m0[1]}}) | | |
1388 | ({next_cindex_bit1[2],next_cindex_bit0[2]} & {2{tsm_thrsel_m0[2]}}) | | |
1389 | ({next_cindex_bit1[3],next_cindex_bit0[3]} & {2{tsm_thrsel_m0[3]}}) | | |
1390 | ({next_cindex_bit1[4],next_cindex_bit0[4]} & {2{tsm_thrsel_m0[4]}}) | | |
1391 | ({next_cindex_bit1[5],next_cindex_bit0[5]} & {2{tsm_thrsel_m0[5]}}) | | |
1392 | ({next_cindex_bit1[6],next_cindex_bit0[6]} & {2{tsm_thrsel_m0[6]}}) | | |
1393 | ({next_cindex_bit1[7],next_cindex_bit0[7]} & {2{tsm_thrsel_m0[7]}}) ; | |
1394 | ||
1395 | ||
1396 | assign htc_thr_valid_m0[7:0] = (tsm_valid_m0[7:0] & ~htc_tsb_done_hw2[7:0] & ~cfg_done_m1[7:0]); | |
1397 | assign conf_rd_en = |(htc_thr_valid_m0[7:0]); | |
1398 | ||
1399 | assign conf_rd_thr_id[0] = tsm_thrsel_m0[1] | tsm_thrsel_m0[3] | tsm_thrsel_m0[5] | tsm_thrsel_m0[7]; | |
1400 | assign conf_rd_thr_id[1] = tsm_thrsel_m0[2] | tsm_thrsel_m0[3] | tsm_thrsel_m0[6] | tsm_thrsel_m0[7]; | |
1401 | assign conf_rd_thr_id[2] = tsm_thrsel_m0[4] | tsm_thrsel_m0[5] | tsm_thrsel_m0[6] | tsm_thrsel_m0[7]; | |
1402 | ||
1403 | // conf_addr_in[4:0] | |
1404 | // 4:3 - tid in a TG | |
1405 | // 2:0 - tsb conf reg id | |
1406 | assign conf_addr_in[4:3] = conf_rd_thr_id[1:0]; | |
1407 | assign conf_addr_in[2] = 1'b0; | |
1408 | assign conf_addr_in[1] = ~zero_ctx; | |
1409 | assign conf_addr_in[0] = conf_index[1]; | |
1410 | // mra_rd_en = 01 for TG0, mra_rd_en=10 for TG1 | |
1411 | assign conf_mra_rd_en[1:0] = {conf_rd_thr_id[2],~conf_rd_thr_id[2]}; | |
1412 | ||
1413 | ||
1414 | //0in bits_on -var {conf_rd_en, rr_rd_en} -max 1 | |
1415 | assign htc_mra_addr_in[4:0] = (conf_addr_in[4:0] & {5{conf_rd_en}}) | | |
1416 | (rr_addr_in[4:0] & {5{rr_rd_en}}); | |
1417 | assign htc_mra_rd_en[1:0] = (conf_mra_rd_en[1:0] & {2{conf_rd_en}}) | | |
1418 | (rr_mra_rd_en[1:0] & {2{rr_rd_en}}); | |
1419 | ||
1420 | // detect the condition where the thread selected is the same as the one which has tlbmiss | |
1421 | assign thr_valid_miss_lo_m0 = (htc_thr_valid_m0[3:0] == htc_tlb_miss_m0[3:0]) & |(htc_thr_valid_m0[3:0]); | |
1422 | assign thr_valid_miss_hi_m0 = (htc_thr_valid_m0[7:4] == htc_tlb_miss_m0[7:4]) & |(htc_thr_valid_m0[7:4]); | |
1423 | ||
1424 | ||
1425 | ||
1426 | //******************************************************************************** | |
1427 | // PROCESS TSBPTR READ REQUEST (M0) | |
1428 | //******************************************************************************** | |
1429 | assign tsbrd_valid_m0 = asi_tsb_ptr_req_valid; | |
1430 | ||
1431 | // decode tsbptr request | |
1432 | assign htc_tsbrd_valid_m0[0] = ~asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1433 | assign htc_tsbrd_valid_m0[1] = ~asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1434 | assign htc_tsbrd_valid_m0[2] = ~asi_tsb_ptr_req[2] & asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1435 | assign htc_tsbrd_valid_m0[3] = ~asi_tsb_ptr_req[2] & asi_tsb_ptr_req[1] & asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1436 | assign htc_tsbrd_valid_m0[4] = asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1437 | assign htc_tsbrd_valid_m0[5] = asi_tsb_ptr_req[2] & ~asi_tsb_ptr_req[1] & asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1438 | assign htc_tsbrd_valid_m0[6] = asi_tsb_ptr_req[2] & asi_tsb_ptr_req[1] & ~asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1439 | assign htc_tsbrd_valid_m0[7] = asi_tsb_ptr_req[2] & asi_tsb_ptr_req[1] & asi_tsb_ptr_req[0] & tsbrd_valid_m0; | |
1440 | ||
1441 | ||
1442 | mmu_htc_ctl_msff_ctl_macro__width_6 m1_stg_lat | |
1443 | ( | |
1444 | .scan_in(m1_stg_lat_scanin), | |
1445 | .scan_out(m1_stg_lat_scanout), | |
1446 | .l1clk( l1clk ), | |
1447 | .din ({zero_ctx, conf_index[1:0], conf_addr_in[2:0]}), | |
1448 | .dout ({zero_ctx_m1, conf_index_m1[1:0], conf_addr_m1[2:0]}), | |
1449 | .siclk(siclk), | |
1450 | .soclk(soclk) | |
1451 | ); | |
1452 | ||
1453 | mmu_htc_ctl_msff_ctl_macro__width_8 conf_prevalid_lat | |
1454 | ( | |
1455 | .scan_in(conf_prevalid_lat_scanin), | |
1456 | .scan_out(conf_prevalid_lat_scanout), | |
1457 | .l1clk ( l1clk ), | |
1458 | .din (htc_thr_valid_m0[7:0]), | |
1459 | .dout (thr_prevalid_m1[7:0]), | |
1460 | .siclk(siclk), | |
1461 | .soclk(soclk) | |
1462 | ); | |
1463 | ||
1464 | assign tsbrd_z_m0 = | |
1465 | ( asd0_zero_context & ~asi_tsb_ptr_req[2] & tsbrd_valid_m0) | | |
1466 | ( asd1_zero_context & asi_tsb_ptr_req[2] & tsbrd_valid_m0) ; | |
1467 | ||
1468 | assign tsbrd_nz_m0 = | |
1469 | (~asd0_zero_context & ~asi_tsb_ptr_req[2] & tsbrd_valid_m0) | | |
1470 | (~asd1_zero_context & asi_tsb_ptr_req[2] & tsbrd_valid_m0) ; | |
1471 | ||
1472 | // latch tsbptr read requests | |
1473 | mmu_htc_ctl_msff_ctl_macro__width_11 tsbptr_lat | |
1474 | ( | |
1475 | .scan_in(tsbptr_lat_scanin), | |
1476 | .scan_out(tsbptr_lat_scanout), | |
1477 | .l1clk ( l1clk ), | |
1478 | .din ({asi_tsb_ptr_number[0], tsbrd_z_m0, tsbrd_nz_m0, htc_tsbrd_valid_m0[7:0]}), | |
1479 | .dout ({tsbrd_tsbptr_m1[0], tsbrd_z_m1, tsbrd_nz_m1, htc_tsbrd_valid_m1[7:0]}), | |
1480 | .siclk(siclk), | |
1481 | .soclk(soclk) | |
1482 | ); | |
1483 | ||
1484 | ||
1485 | assign asi_tsb_ptr_number_unused =asi_tsb_ptr_number[1]; | |
1486 | ||
1487 | ||
1488 | //******************************************************************************** | |
1489 | // LATCH THE PREDICTION ROW READ OUT in mmu_htd_dp (M0) | |
1490 | // ALSO LATCH THE INDEX | |
1491 | //******************************************************************************** | |
1492 | mmu_htc_ctl_msff_ctl_macro__width_22 predrow0_lat | |
1493 | ( | |
1494 | .scan_in(predrow0_lat_scanin), | |
1495 | .scan_out(predrow0_lat_scanout), | |
1496 | .l1clk ( l1clk ), | |
1497 | .din ({htd_pred0_idx_m0[5:0],htd_pred0_m0[15:0]}), | |
1498 | .dout ({htd_pred0_idx_m1[5:0],htd_pred0_m1[15:0]}), | |
1499 | .siclk(siclk), | |
1500 | .soclk(soclk) | |
1501 | ); | |
1502 | ||
1503 | mmu_htc_ctl_msff_ctl_macro__width_22 predrow1_lat | |
1504 | ( | |
1505 | .scan_in(predrow1_lat_scanin), | |
1506 | .scan_out(predrow1_lat_scanout), | |
1507 | .l1clk ( l1clk ), | |
1508 | .din ({htd_pred1_idx_m0[5:0],htd_pred1_m0[15:0]}), | |
1509 | .dout ({htd_pred1_idx_m1[5:0],htd_pred1_m1[15:0]}), | |
1510 | .siclk(siclk), | |
1511 | .soclk(soclk) | |
1512 | ); | |
1513 | ||
1514 | ||
1515 | mmu_htc_ctl_msff_ctl_macro__width_8 tlbmiss_lat | |
1516 | ( | |
1517 | .scan_in(tlbmiss_lat_scanin), | |
1518 | .scan_out(tlbmiss_lat_scanout), | |
1519 | .l1clk ( l1clk ), | |
1520 | .din ({htc_tlb_miss_m0[7:0]}), | |
1521 | .dout ({htc_tlb_miss_m1[7:0]}), | |
1522 | .siclk(siclk), | |
1523 | .soclk(soclk) | |
1524 | ); | |
1525 | ||
1526 | mmu_htc_ctl_msff_ctl_macro__width_2 tlbvalidmiss_lat | |
1527 | ( | |
1528 | .scan_in(tlbvalidmiss_lat_scanin), | |
1529 | .scan_out(tlbvalidmiss_lat_scanout), | |
1530 | .l1clk ( l1clk ), | |
1531 | .din ({thr_valid_miss_hi_m0,thr_valid_miss_lo_m0}), | |
1532 | .dout ({thr_valid_miss_hi_m1,thr_valid_miss_lo_m1}), | |
1533 | .siclk(siclk), | |
1534 | .soclk(soclk) | |
1535 | ); | |
1536 | ||
1537 | //0in bits_on -var {thr_valid_miss_hi_m1, thr_valid_miss_lo_m1} -max 1 | |
1538 | ||
1539 | ||
1540 | ||
1541 | //******************************************************************************** | |
1542 | // READ OUT PREDICTION TABLE AND STORE THE INDEX AND PREDICTION HISTORY IN | |
1543 | // A TABLE (M1) | |
1544 | //******************************************************************************** | |
1545 | // Read out the TSB prediction table for the two tlb misses, | |
1546 | // and write them to a register | |
1547 | ||
1548 | // Logically prediction table has 64 entries, each entry is 2 bits. | |
1549 | // If MSB=1, then predict TSB 1, else predict TSB 0. | |
1550 | // The table is arranged as 4 registers, each 32 bits wide, in htd | |
1551 | // Bits [5:4] of pred_idx select, 1 of 4 registers in htd (htd_pred_m1[31:0]), | |
1552 | // and bits [3:0] select 2 bits out of the 32 bits. | |
1553 | ||
1554 | ||
1555 | // thread group 0 | |
1556 | assign pred0_bit_m1[1:0] = ({2{~htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[1:0]) | | |
1557 | ({2{~htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & htd_pred0_idx_m1[0]}} & htd_pred0_m1[3:2]) | | |
1558 | ({2{~htd_pred0_idx_m1[2] & htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[5:4]) | | |
1559 | ({2{~htd_pred0_idx_m1[2] & htd_pred0_idx_m1[1] & htd_pred0_idx_m1[0]}} & htd_pred0_m1[7:6]) | | |
1560 | ({2{ htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[9:8]) | | |
1561 | ({2{ htd_pred0_idx_m1[2] & ~htd_pred0_idx_m1[1] & htd_pred0_idx_m1[0]}} & htd_pred0_m1[11:10]) | | |
1562 | ({2{ htd_pred0_idx_m1[2] & htd_pred0_idx_m1[1] & ~htd_pred0_idx_m1[0]}} & htd_pred0_m1[13:12]) | | |
1563 | ({2{ htd_pred0_idx_m1[2] & htd_pred0_idx_m1[1] & htd_pred0_idx_m1[0]}} & htd_pred0_m1[15:14]); | |
1564 | ||
1565 | //thread group1 | |
1566 | assign pred1_bit_m1[1:0] = ({2{~htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[1:0]) | | |
1567 | ({2{~htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & htd_pred1_idx_m1[0]}} & htd_pred1_m1[3:2]) | | |
1568 | ({2{~htd_pred1_idx_m1[2] & htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[5:4]) | | |
1569 | ({2{~htd_pred1_idx_m1[2] & htd_pred1_idx_m1[1] & htd_pred1_idx_m1[0]}} & htd_pred1_m1[7:6]) | | |
1570 | ({2{ htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[9:8]) | | |
1571 | ({2{ htd_pred1_idx_m1[2] & ~htd_pred1_idx_m1[1] & htd_pred1_idx_m1[0]}} & htd_pred1_m1[11:10]) | | |
1572 | ({2{ htd_pred1_idx_m1[2] & htd_pred1_idx_m1[1] & ~htd_pred1_idx_m1[0]}} & htd_pred1_m1[13:12]) | | |
1573 | ({2{ htd_pred1_idx_m1[2] & htd_pred1_idx_m1[1] & htd_pred1_idx_m1[0]}} & htd_pred1_m1[15:14]); | |
1574 | ||
1575 | ||
1576 | // use tlb_miss_m1 to latch the prediction address and prediction bits for the thread whose | |
1577 | // request is being sent out. This will be used to predict the TSB and will be used to update the prediction | |
1578 | // table on a tsb hit. | |
1579 | assign pred_idx0_in[5:0] = ({6{htc_tlb_miss_m1[0]}} & htd_pred0_idx_m1[5:0]) | | |
1580 | ({6{~htc_tlb_miss_m1[0]}} & pred_idx0[5:0]); | |
1581 | assign pred_idx1_in[5:0] = ({6{htc_tlb_miss_m1[1]}} & htd_pred0_idx_m1[5:0]) | | |
1582 | ({6{~htc_tlb_miss_m1[1]}} & pred_idx1[5:0]); | |
1583 | assign pred_idx2_in[5:0] = ({6{htc_tlb_miss_m1[2]}} & htd_pred0_idx_m1[5:0]) | | |
1584 | ({6{~htc_tlb_miss_m1[2]}} & pred_idx2[5:0]); | |
1585 | assign pred_idx3_in[5:0] = ({6{htc_tlb_miss_m1[3]}} & htd_pred0_idx_m1[5:0]) | | |
1586 | ({6{~htc_tlb_miss_m1[3]}} & pred_idx3[5:0]); | |
1587 | assign pred_idx4_in[5:0] = ({6{htc_tlb_miss_m1[4]}} & htd_pred1_idx_m1[5:0]) | | |
1588 | ({6{~htc_tlb_miss_m1[4]}} & pred_idx4[5:0]); | |
1589 | assign pred_idx5_in[5:0] = ({6{htc_tlb_miss_m1[5]}} & htd_pred1_idx_m1[5:0]) | | |
1590 | ({6{~htc_tlb_miss_m1[5]}} & pred_idx5[5:0]); | |
1591 | assign pred_idx6_in[5:0] = ({6{htc_tlb_miss_m1[6]}} & htd_pred1_idx_m1[5:0]) | | |
1592 | ({6{~htc_tlb_miss_m1[6]}} & pred_idx6[5:0]); | |
1593 | assign pred_idx7_in[5:0] = ({6{htc_tlb_miss_m1[7]}} & htd_pred1_idx_m1[5:0]) | | |
1594 | ({6{~htc_tlb_miss_m1[7]}} & pred_idx7[5:0]); | |
1595 | ||
1596 | assign pred_bit0_in[1:0] = ({2{htc_tlb_miss_m1[0]}} & pred0_bit_m1[1:0]) | | |
1597 | ({2{~htc_tlb_miss_m1[0]}} & pred_bit0[1:0]); | |
1598 | assign pred_bit1_in[1:0] = ({2{htc_tlb_miss_m1[1]}} & pred0_bit_m1[1:0]) | | |
1599 | ({2{~htc_tlb_miss_m1[1]}} & pred_bit1[1:0]); | |
1600 | assign pred_bit2_in[1:0] = ({2{htc_tlb_miss_m1[2]}} & pred0_bit_m1[1:0]) | | |
1601 | ({2{~htc_tlb_miss_m1[2]}} & pred_bit2[1:0]); | |
1602 | assign pred_bit3_in[1:0] = ({2{htc_tlb_miss_m1[3]}} & pred0_bit_m1[1:0]) | | |
1603 | ({2{~htc_tlb_miss_m1[3]}} & pred_bit3[1:0]); | |
1604 | assign pred_bit4_in[1:0] = ({2{htc_tlb_miss_m1[4]}} & pred1_bit_m1[1:0]) | | |
1605 | ({2{~htc_tlb_miss_m1[4]}} & pred_bit4[1:0]); | |
1606 | assign pred_bit5_in[1:0] = ({2{htc_tlb_miss_m1[5]}} & pred1_bit_m1[1:0]) | | |
1607 | ({2{~htc_tlb_miss_m1[5]}} & pred_bit5[1:0]); | |
1608 | assign pred_bit6_in[1:0] = ({2{htc_tlb_miss_m1[6]}} & pred1_bit_m1[1:0]) | | |
1609 | ({2{~htc_tlb_miss_m1[6]}} & pred_bit6[1:0]); | |
1610 | assign pred_bit7_in[1:0] = ({2{htc_tlb_miss_m1[7]}} & pred1_bit_m1[1:0]) | | |
1611 | ({2{~htc_tlb_miss_m1[7]}} & pred_bit7[1:0]); | |
1612 | ||
1613 | mmu_htc_ctl_msff_ctl_macro__width_8 pred0_lat | |
1614 | ( | |
1615 | .scan_in(pred0_lat_scanin), | |
1616 | .scan_out(pred0_lat_scanout), | |
1617 | .l1clk( l1clk), | |
1618 | .din ({pred_idx0_in[5:0], pred_bit0_in[1:0]}), | |
1619 | .dout ({pred_idx0[5:0], pred_bit0[1:0]}), | |
1620 | .siclk(siclk), | |
1621 | .soclk(soclk) | |
1622 | ); | |
1623 | ||
1624 | mmu_htc_ctl_msff_ctl_macro__width_8 pred1_lat | |
1625 | ( | |
1626 | .scan_in(pred1_lat_scanin), | |
1627 | .scan_out(pred1_lat_scanout), | |
1628 | .l1clk( l1clk), | |
1629 | .din ({pred_idx1_in[5:0], pred_bit1_in[1:0]}), | |
1630 | .dout ({pred_idx1[5:0], pred_bit1[1:0]}), | |
1631 | .siclk(siclk), | |
1632 | .soclk(soclk) | |
1633 | ); | |
1634 | ||
1635 | mmu_htc_ctl_msff_ctl_macro__width_8 pred2_lat | |
1636 | ( | |
1637 | .scan_in(pred2_lat_scanin), | |
1638 | .scan_out(pred2_lat_scanout), | |
1639 | .l1clk( l1clk), | |
1640 | .din ({pred_idx2_in[5:0], pred_bit2_in[1:0]}), | |
1641 | .dout ({pred_idx2[5:0], pred_bit2[1:0]}), | |
1642 | .siclk(siclk), | |
1643 | .soclk(soclk) | |
1644 | ); | |
1645 | ||
1646 | mmu_htc_ctl_msff_ctl_macro__width_8 pred3_lat | |
1647 | ( | |
1648 | .scan_in(pred3_lat_scanin), | |
1649 | .scan_out(pred3_lat_scanout), | |
1650 | .l1clk( l1clk), | |
1651 | .din ({pred_idx3_in[5:0], pred_bit3_in[1:0]}), | |
1652 | .dout ({pred_idx3[5:0], pred_bit3[1:0]}), | |
1653 | .siclk(siclk), | |
1654 | .soclk(soclk) | |
1655 | ); | |
1656 | ||
1657 | mmu_htc_ctl_msff_ctl_macro__width_8 pred4_lat | |
1658 | ( | |
1659 | .scan_in(pred4_lat_scanin), | |
1660 | .scan_out(pred4_lat_scanout), | |
1661 | .l1clk( l1clk), | |
1662 | .din ({pred_idx4_in[5:0], pred_bit4_in[1:0]}), | |
1663 | .dout ({pred_idx4[5:0], pred_bit4[1:0]}), | |
1664 | .siclk(siclk), | |
1665 | .soclk(soclk) | |
1666 | ); | |
1667 | ||
1668 | mmu_htc_ctl_msff_ctl_macro__width_8 pred5_lat | |
1669 | ( | |
1670 | .scan_in(pred5_lat_scanin), | |
1671 | .scan_out(pred5_lat_scanout), | |
1672 | .l1clk( l1clk), | |
1673 | .din ({pred_idx5_in[5:0], pred_bit5_in[1:0]}), | |
1674 | .dout ({pred_idx5[5:0], pred_bit5[1:0]}), | |
1675 | .siclk(siclk), | |
1676 | .soclk(soclk) | |
1677 | ); | |
1678 | ||
1679 | mmu_htc_ctl_msff_ctl_macro__width_8 pred6_lat | |
1680 | ( | |
1681 | .scan_in(pred6_lat_scanin), | |
1682 | .scan_out(pred6_lat_scanout), | |
1683 | .l1clk( l1clk), | |
1684 | .din ({pred_idx6_in[5:0], pred_bit6_in[1:0]}), | |
1685 | .dout ({pred_idx6[5:0], pred_bit6[1:0]}), | |
1686 | .siclk(siclk), | |
1687 | .soclk(soclk) | |
1688 | ); | |
1689 | ||
1690 | mmu_htc_ctl_msff_ctl_macro__width_8 pred7_lat | |
1691 | ( | |
1692 | .scan_in(pred7_lat_scanin), | |
1693 | .scan_out(pred7_lat_scanout), | |
1694 | .l1clk( l1clk), | |
1695 | .din ({pred_idx7_in[5:0], pred_bit7_in[1:0]}), | |
1696 | .dout ({pred_idx7[5:0], pred_bit7[1:0]}), | |
1697 | .siclk(siclk), | |
1698 | .soclk(soclk) | |
1699 | ); | |
1700 | ||
1701 | ||
1702 | ///////////////////////////////////////////////////////////////////// | |
1703 | // MRA Access Cycle (M1) | |
1704 | ///////////////////////////////////////////////////////////////////// | |
1705 | assign htc_thr_valid_m1[7:0] = ({8{asi_mra_req_grant & room_avail_m1}} & thr_prevalid_m1[7:0]); | |
1706 | // cfg_done comes on for 1 cycle after the last cfg is read. | |
1707 | assign cfg_done_m1[7:0] = {8{conf_index_m1[1] & conf_index_m1[0]}} & htc_thr_valid_m1[7:0]; | |
1708 | ||
1709 | assign cfg_read_tg0_m1 = |(htc_thr_valid_m1[3:0]); | |
1710 | assign cfg_read_tg1_m1 = |(htc_thr_valid_m1[7:4]); | |
1711 | assign htc_valid_m1 = |(htc_thr_valid_m1[7:0]); | |
1712 | ||
1713 | ||
1714 | assign thr_valid_m2_in[7:0] = htc_thr_valid_m1[7:0] & ~htc_tsb_done_hw2[7:0]; | |
1715 | ||
1716 | ||
1717 | assign tsbrd_valid_m1 = tsbrd_z_m1 | tsbrd_nz_m1; | |
1718 | assign tsbrd_tg0_m1 = ~(|(htc_tsbrd_valid_m1[7:4])) & tsbrd_valid_m1; | |
1719 | assign tsbrd_tg1_m1 = (|(htc_tsbrd_valid_m1[7:4])) & tsbrd_valid_m1; | |
1720 | ||
1721 | //assign htc_va_rd_m2_in[7:0] = thr_valid_m2_in[7:0] | htc_tsbrd_valid_m1[7:0]; | |
1722 | assign htc_va_rd_m2_in[7:0] = htc_thr_valid_m1[7:0] | htc_tsbrd_valid_m1[7:0]; | |
1723 | ||
1724 | assign htc_m1_clken = (|(htc_va_rd_m2_in[7:0])) | ~htc_mmu_pmen; | |
1725 | ||
1726 | //0in bits_on -var {cfg_read_tg0_m1, cfg_read_tg1_m1, rr_read_tg0_hw3, rr_read_tg1_hw3, tsbrd_tg0_m1, tsbrd_tg1_m1} -max 1 | |
1727 | assign htc_mra_sel[1] = (cfg_read_tg1_m1 | rr_read_tg1_hw3 | tsbrd_tg1_m1 ); | |
1728 | assign htc_mra_sel[0] = (cfg_read_tg0_m1 | rr_read_tg0_hw3 | tsbrd_tg0_m1 ); | |
1729 | ||
1730 | ||
1731 | // If prediction is disabled, then | |
1732 | // if conf_index == 00 then read tsb0 => sel_mra_up | |
1733 | // if conf_index == 01 then read tsb1 => sel_mra_lo | |
1734 | // if conf_index == 10 then read tsb2 => sel_mra_up | |
1735 | // if conf_index == 11 then read tsb3 => sel_mra_lo | |
1736 | ||
1737 | // If prediction is enabled, then | |
1738 | // if conf_index == 00 and ~pred_bit[1] then read tsb0 => sel_mra_up | |
1739 | // if conf_index == 00 and pred_bit[1] then read tsb1 => sel_mra_lo | |
1740 | // if conf_index == 01 and ~pred_bit[1] then read tsb1 => sel_mra_lo | |
1741 | // if conf_index == 01 and pred_bit[1] then read tsb0 => sel_mra_up | |
1742 | // if conf_index == 10 then read tsb2 => sel_mra_up | |
1743 | // if conf_index == 11 then read tsb3 => sel_mra_lo | |
1744 | ||
1745 | ||
1746 | ||
1747 | //0in bits_on -var {conf_sel_mra_lo, conf_sel_mra_up} -max 1 | |
1748 | ||
1749 | assign pred_en = |(htc_hwtw_pred[7:0] & htc_thr_valid_m1[7:0]); | |
1750 | ||
1751 | // read out prediction bits | |
1752 | // If thr_prevalid is same as the one which had a tlbmiss in m0 (thr_valid_miss_lo or thr_valid_miss_hi), | |
1753 | // then use pred0_bit_m1 or pred1_bit_m1, else get the prediction information from latched data (pred_bit7-0) | |
1754 | assign pred_bit_m1[1] = (thr_valid_miss_lo_m1 & pred0_bit_m1[1]) | | |
1755 | (thr_valid_miss_hi_m1 & pred1_bit_m1[1]) | | |
1756 | (thr_prevalid_m1[0] & ~thr_valid_miss_lo_m1 & pred_bit0[1]) | | |
1757 | (thr_prevalid_m1[1] & ~thr_valid_miss_lo_m1 & pred_bit1[1]) | | |
1758 | (thr_prevalid_m1[2] & ~thr_valid_miss_lo_m1 & pred_bit2[1]) | | |
1759 | (thr_prevalid_m1[3] & ~thr_valid_miss_lo_m1 & pred_bit3[1]) | | |
1760 | (thr_prevalid_m1[4] & ~thr_valid_miss_hi_m1 & pred_bit4[1]) | | |
1761 | (thr_prevalid_m1[5] & ~thr_valid_miss_hi_m1 & pred_bit5[1]) | | |
1762 | (thr_prevalid_m1[6] & ~thr_valid_miss_hi_m1 & pred_bit6[1]) | | |
1763 | (thr_prevalid_m1[7] & ~thr_valid_miss_hi_m1 & pred_bit7[1]); | |
1764 | ||
1765 | ||
1766 | assign conf_sel_mra_lo = ((~pred_en & conf_index_m1[0]) | | |
1767 | (conf_index_m1[1] & conf_index_m1[0]) | | |
1768 | (pred_en & ~pred_bit_m1[1] & ~conf_index_m1[1] & conf_index_m1[0]) | | |
1769 | (pred_en & pred_bit_m1[1] & ~conf_index_m1[1] & ~conf_index_m1[0])) & htc_valid_m1; | |
1770 | ||
1771 | assign conf_sel_mra_up = ((~pred_en & ~conf_index_m1[0]) | | |
1772 | (conf_index_m1[1] & ~conf_index_m1[0]) | | |
1773 | (pred_en & ~pred_bit_m1[1] & ~conf_index_m1[1] & ~conf_index_m1[0]) | | |
1774 | (pred_en & pred_bit_m1[1] & ~conf_index_m1[1] & conf_index_m1[0])) & htc_valid_m1; | |
1775 | ||
1776 | ||
1777 | ||
1778 | assign tsbrd_sel_mra_lo = tsbrd_tsbptr_m1[0] & tsbrd_valid_m1; | |
1779 | assign tsbrd_sel_mra_up = ~tsbrd_tsbptr_m1[0] & tsbrd_valid_m1; | |
1780 | ||
1781 | assign htc_sel_mra_lo = conf_sel_mra_lo | tsbrd_sel_mra_lo; | |
1782 | assign htc_sel_mra_up = conf_sel_mra_up | tsbrd_sel_mra_up; | |
1783 | ||
1784 | //0in bits_on -var {conf_sel_mra_lo, conf_sel_mra_up, tsbrd_sel_mra_lo, tsbrd_sel_mra_up} -max 1 | |
1785 | ||
1786 | // conf_index_m2 should reflect the real tsb ptr being read. | |
1787 | // It is used to keep track of tsb ptrs being returned out of order. | |
1788 | // it is the function of tsb prediction and conf_index_m1. | |
1789 | assign conf_index_m2_in[1:0] = {2{htc_valid_m1}} & conf_index_m1[1:0]; | |
1790 | ||
1791 | ||
1792 | //asi_tsb_hwtw_en_0[0] : hwtw_en for tg0, tsb0,tsb2 | |
1793 | //asi_tsb_hwtw_en_0[1] : hwtw_en for tg0, tsb1,tsb3 | |
1794 | ||
1795 | assign hwtw_en_tg0 = (htc_sel_mra_lo & asi_tsb_hwtw_enable_0[1]) | | |
1796 | (htc_sel_mra_up & asi_tsb_hwtw_enable_0[0]); | |
1797 | ||
1798 | assign hwtw_en_tg1 = (htc_sel_mra_lo & asi_tsb_hwtw_enable_1[1]) | | |
1799 | (htc_sel_mra_up & asi_tsb_hwtw_enable_1[0]); | |
1800 | ||
1801 | //assign mra_data_38 = (htc_mra_sel[0] & mra0_data_38) | | |
1802 | // (htc_mra_sel[1] & mra1_data_38); | |
1803 | ||
1804 | //assign mra_data_77 = (htc_mra_sel[0] & mra0_data_77) | | |
1805 | // (htc_mra_sel[1] & mra1_data_77); | |
1806 | ||
1807 | ||
1808 | assign hwtw_en_m2_in = (htc_mra_sel[0] & hwtw_en_tg0) | | |
1809 | (htc_mra_sel[1] & hwtw_en_tg1); | |
1810 | ||
1811 | assign htc_mra_sel_0 = htc_mra_sel[0]; | |
1812 | ||
1813 | //assign hwtw_en_m2_in = asi_tsb_hwtw_enable; | |
1814 | ||
1815 | ||
1816 | ||
1817 | mmu_htc_ctl_msff_ctl_macro__width_17 m2_stg_lat2 ( | |
1818 | .scan_in(m2_stg_lat2_scanin), | |
1819 | .scan_out(m2_stg_lat2_scanout), | |
1820 | .l1clk( l1clk ), | |
1821 | .din ({hwtw_en_m2_in, cfg_read_tg0_m1, cfg_read_tg1_m1, zero_ctx_m1, conf_index_m2_in[1:0], conf_addr_m1[2:0], thr_valid_m2_in[7:0]}), | |
1822 | .dout({hwtw_en_m2, cfg_read_tg0_m2, cfg_read_tg1_m2, zero_ctx_m2, htc_conf_index_m2[1:0], conf_addr_m2[2:0], htc_thr_valid_m2[7:0]}), | |
1823 | .siclk(siclk), | |
1824 | .soclk(soclk) | |
1825 | ); | |
1826 | ||
1827 | ||
1828 | ||
1829 | ///////////////////////////////////////////////////////////////////// | |
1830 | // TSB Pointer Generation (M2) | |
1831 | ///////////////////////////////////////////////////////////////////// | |
1832 | ||
1833 | assign htc_zero_ctx_m2 = zero_ctx_m2; | |
1834 | ||
1835 | //assign htc_ignore_ctx_m2 = ~zero_ctx_m2 & (htd_cfg_usc0_m2 | htd_cfg_usc1_m2) ; | |
1836 | ||
1837 | // Valid tsbptr exists if | |
1838 | // => thr_valid_m2 | |
1839 | // => no tsb_hit in m2 cycle | |
1840 | // => & hwtw is enable (else we don't need to send the request to gasket) | |
1841 | ||
1842 | // cancel tsbptr if tsb_hit_hw2 | |
1843 | assign htc_vld_tsbptr_m2[0] = htc_thr_valid_m2[0] & ~htc_tsb_done_hw2[0] & hwtw_en_m2; | |
1844 | assign htc_vld_tsbptr_m2[1] = htc_thr_valid_m2[1] & ~htc_tsb_done_hw2[1] & hwtw_en_m2; | |
1845 | assign htc_vld_tsbptr_m2[2] = htc_thr_valid_m2[2] & ~htc_tsb_done_hw2[2] & hwtw_en_m2; | |
1846 | assign htc_vld_tsbptr_m2[3] = htc_thr_valid_m2[3] & ~htc_tsb_done_hw2[3] & hwtw_en_m2; | |
1847 | assign htc_vld_tsbptr_m2[4] = htc_thr_valid_m2[4] & ~htc_tsb_done_hw2[4] & hwtw_en_m2; | |
1848 | assign htc_vld_tsbptr_m2[5] = htc_thr_valid_m2[5] & ~htc_tsb_done_hw2[5] & hwtw_en_m2; | |
1849 | assign htc_vld_tsbptr_m2[6] = htc_thr_valid_m2[6] & ~htc_tsb_done_hw2[6] & hwtw_en_m2; | |
1850 | assign htc_vld_tsbptr_m2[7] = htc_thr_valid_m2[7] & ~htc_tsb_done_hw2[7] & hwtw_en_m2; | |
1851 | ||
1852 | assign vld_tsbptr_thr_id_m2[0] = htc_vld_tsbptr_m2[1] | htc_vld_tsbptr_m2[3] | htc_vld_tsbptr_m2[5] | htc_vld_tsbptr_m2[7] ; | |
1853 | assign vld_tsbptr_thr_id_m2[1] = htc_vld_tsbptr_m2[2] | htc_vld_tsbptr_m2[3] | htc_vld_tsbptr_m2[6] | htc_vld_tsbptr_m2[7] ; | |
1854 | assign vld_tsbptr_thr_id_m2[2] = htc_vld_tsbptr_m2[4] | htc_vld_tsbptr_m2[5] | htc_vld_tsbptr_m2[6] | htc_vld_tsbptr_m2[7] ; | |
1855 | ||
1856 | assign vld_tsbptr_rdy_m2 = |(htc_vld_tsbptr_m2[7:0]); | |
1857 | ||
1858 | ||
1859 | // for ecc_err on MRA read, we need to report the error even if hwtw is not enabled in the tsb. | |
1860 | // | |
1861 | // Do not enable cfg_ecc_err if tsb_miss has already been signalled. | |
1862 | // This can happen if the last cfg read has hwtw disabled, and all prior cfg reads have completed and | |
1863 | // have resulted in tsb miss. In this case we signal a tsbmiss without waiting for the parity error | |
1864 | // check on the last cfg read. | |
1865 | assign htc_cfg_ecc_err_en_m2[7:0] = htc_thr_valid_m2[7:0] & ~htc_tsb_done_hw2[7:0] & ~tsm_tsb_miss_hw2[7:0]; | |
1866 | ||
1867 | assign cfg_ecc_err_index_m2[2:0] = conf_addr_m2[2:0]; | |
1868 | ||
1869 | ||
1870 | mmu_htc_ctl_msff_ctl_macro__width_13 m3_stg_lat1 | |
1871 | ( | |
1872 | .scan_in(m3_stg_lat1_scanin), | |
1873 | .scan_out(m3_stg_lat1_scanout), | |
1874 | .l1clk( l1clk ), | |
1875 | .din ({cfg_read_tg0_m2, cfg_read_tg1_m2, htc_cfg_ecc_err_en_m2[7:0], | |
1876 | cfg_ecc_err_index_m2[2:0]}), | |
1877 | .dout ({cfg_read_tg0_m3, cfg_read_tg1_m3, htc_cfg_ecc_err_en_m3[7:0], | |
1878 | cfg_ecc_err_index[2:0]}), | |
1879 | .siclk(siclk), | |
1880 | .soclk(soclk) | |
1881 | ); | |
1882 | ||
1883 | assign mel0_parity_err_m3 = mel0_parity_err; | |
1884 | assign mel1_parity_err_m3 = mel1_parity_err; | |
1885 | ||
1886 | ||
1887 | assign mra0_ecc_err_lat = (mel0_parity_err_m3 & hwtwmu_en); | |
1888 | assign mra1_ecc_err_lat = (mel1_parity_err_m3 & hwtwmu_en); | |
1889 | assign mra0_err_type_lat[1:0] = {(mel0_parity_err_m3 & hwtwmu_en), 1'b0}; | |
1890 | assign mra1_err_type_lat[1:0] = {(mel1_parity_err_m3 & hwtwmu_en), 1'b0}; | |
1891 | ||
1892 | assign cfg_ecc_err_m3[7:0] = {8{((cfg_read_tg0_m3 & mra0_ecc_err_lat) | (cfg_read_tg1_m3 & mra1_ecc_err_lat))}} & | |
1893 | htc_cfg_ecc_err_en_m3[7:0] & ~htc_tsb_done_hw2[7:0] & ~tsm_tsb_miss_hw2[7:0]; | |
1894 | ||
1895 | assign cfg_ecc_err_type[1:0] = ({2{cfg_read_tg0_m3}} & mra0_err_type_lat[1:0]) | | |
1896 | ({2{cfg_read_tg1_m3}} & mra1_err_type_lat[1:0]); | |
1897 | ||
1898 | ///////////////////////////////////////////////////////////////////// | |
1899 | // TTE Req to Gasket (M3) | |
1900 | // tte read request is sent to gasket in M3. This is when the tsbptr is | |
1901 | // available. | |
1902 | // When a request is M0 in cycle 0, a grant for it will not be available | |
1903 | // until late in cycle 4. | |
1904 | // MMU has a two entry FIFO, q0 and q1, where requests are queued if they cannot be | |
1905 | // sent to gasket. | |
1906 | // Once two requests have been sent to gkt and q0 and q1 are full, no more | |
1907 | // requests can come down the pipe until gkt gives a grant. The cycle after grant, | |
1908 | // a new req can be valid in M1. | |
1909 | ///////////////////////////////////////////////////////////////////// | |
1910 | //------------------------------------------------------------------- | |
1911 | // | 0 | 1 | 2 | 3 | 4 | 5 | 6 | 7 | | | |
1912 | //------------------------------------------------------------------- | |
1913 | // M0 |RQA |RQB |RQC |RQD |RQE |RQE |RQE |RQE | RQF | RQG | RQH | | |
1914 | // | | | | | | | | | | | | | | |
1915 | //------------------------------------------------------------------------------------ | |
1916 | // M1 |IN |RQA |RQB |RQC |RQD | | | |RQE | RQF | RQG | RQH | | |
1917 | // | | | | | | | | | | | | | | |
1918 | //------------------------------------------------------------------------------------ | |
1919 | // M2 | | |RQA |RQB |RQC |RQD | | | |RQE | RQF | RQG | RQH | | |
1920 | // | | | | | | | | | | | | | | |
1921 | //------------------------------------------------------------------------------------ | |
1922 | // M3 | | | |RQA |RQB |RQC |RQD | | | | RQE | RQF | RQG | RQH | | |
1923 | // | | | | | | | | | | | | | | |
1924 | //----------------------------------------------------------------------------------------------- | |
1925 | // mmu_l15| | | |RQA |RQB | | | |RQC |RQD | RQE | RQF | RQG | RQH | | |
1926 | // _valid | | | | | | | | | | | | | | |
1927 | //----------------------------------------------------------------------------------------------- | |
1928 | // grant | | | | | | | | A | B | C | D | E | | |
1929 | // | | | | | | | | | | | | | | |
1930 | //----------------------------------------------------------------------------------------------- | |
1931 | // | | | | | | | | | | | | | | |
1932 | //FIFO | | | |ct =0|ct =1|ct =2|ct =2|ct =2|ct =2|ct =2|ct =2|ct =1|ct =0| | |
1933 | // | | | |q0=0 |q0=0 |q0=C |q0=C |q0=C |q0=D |q0=E |q0=0 |q0=0 |q0=0 | | |
1934 | // | | | |q1=0 |q1=0 |q1=0 |q1=D |q1=D |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 | | |
1935 | //----------------------------------------------------------------------------------------------- | |
1936 | // room | 1 | 1 | 1 | 1 | 1 | 0 | 0 | 0 | 1 | 1 | 1 | 1 | 1 | |
1937 | // | | | | | | | | | | | | | | |
1938 | //----------------------------------------------------------------------------------------------- | |
1939 | ||
1940 | //---------------------------------------------------------------------------------------------------- | |
1941 | // M0 |RQA |RQB |RQC |RQD | RQE | RQF | RQG | RQH | RQI | RQI | | |
1942 | // | | | | | | | | | | | | | | |
1943 | //---------------------------------------------------------------------------------------------------------- | |
1944 | // M1 | |RQA |RQB |RQC |RQD |RQE | RQF | RQG | RQH | | RQI | RQJ | | |
1945 | // | | | | | | | | | | | | | | | |
1946 | //---------------------------------------------------------------------------------------------------------- | |
1947 | // M2 | | |RQA |RQB |RQC |RQD |RQE | RQF | RQG | RQH | | RQI | RQJ | | |
1948 | // | | | | | | | | | | | | | | | | |
1949 | //---------------------------------------------------------------------------------------------------------- | |
1950 | // M3 | | | |RQA |RQB |RQC |RQD |RQE | RQF | RQG | RQH | | RQI | RQJ | | |
1951 | // | | | | | | | | | | | | | | | | | |
1952 | //---------------------------------------------------------------------------------------------------------- | |
1953 | // mmu_l15| | | |RQA |RQB |RQC |RQD |RQE | RQF | RQG | RQH | | RQI | RQJ | | |
1954 | // _valid | | | | | | | | | | | | | | | | | |
1955 | //---------------------------------------------------------------------------------------------------------- | |
1956 | // grant | | | | |A | B | C | D | | E | F | G | H | | I | J | |
1957 | // | | | | | | | | | | | | | | | | | |
1958 | //---------------------------------------------------------------------------------------------------------- | |
1959 | //FIFO | | | | ct=0| ct=1| ct=1| ct=1| ct=1| ct=1| ct=2| ct=2| ct=2| ct=1| ct=1| ct=2| | |
1960 | // | | | |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 |q0=0 | | |
1961 | // | | | |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 |q1=0 | | |
1962 | //---------------------------------------------------------------------------------------------------------- | |
1963 | // room | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 1 | 0 | 1 | 1 | 1 | 1 | |
1964 | // | | | | | | | | | | | | | | |
1965 | //---------------------------------------------------------------------------------------------------------- | |
1966 | ||
1967 | assign req_m2 = vld_tsbptr_rdy_m2; | |
1968 | assign htc_l15_cpkt_15_13[2:0] = vld_tsbptr_thr_id_m2[2:0]; //tid | |
1969 | assign htc_l15_cpkt_9_8[1:0] = htc_conf_index_m2[1:0]; //tag | |
1970 | ||
1971 | ///////////////////////////////////////////////////////////////////// | |
1972 | // Tracking GKT buffers | |
1973 | // to be able to send a new request out in the cycle after grant, use | |
1974 | // next_gkt_count. | |
1975 | ///////////////////////////////////////////////////////////////////// | |
1976 | assign next_gkt_count[1:0] = ({2{~gkt_grant & ~mmu_l15_valid_int}} & gkt_count[1:0]) | | |
1977 | ({2{ gkt_grant & mmu_l15_valid_int}} & gkt_count[1:0]) | | |
1978 | ({2{~gkt_grant & mmu_l15_valid_int}} & (gkt_count[1:0]+2'b01)) | | |
1979 | ({2{ gkt_grant & ~mmu_l15_valid_int}} & (gkt_count[1:0]-2'b01)); | |
1980 | ||
1981 | mmu_htc_ctl_msff_ctl_macro__width_2 gkt_count_reg ( | |
1982 | .scan_in(gkt_count_reg_scanin), | |
1983 | .scan_out(gkt_count_reg_scanout), | |
1984 | .l1clk( l1clk ), | |
1985 | .din (next_gkt_count[1:0]), | |
1986 | .dout(gkt_count[1:0]), | |
1987 | .siclk(siclk), | |
1988 | .soclk(soclk) | |
1989 | ); | |
1990 | ||
1991 | assign gkt_full = next_gkt_count[1]; | |
1992 | ||
1993 | ///////////////////////////////////////////////////////////////////// | |
1994 | // q0 and q1 valids | |
1995 | ///////////////////////////////////////////////////////////////////// | |
1996 | assign v0_in = (gkt_full & req_m2 ) | //new | |
1997 | (v0 & ~v1 & gkt_grant & req_m2) | //new | |
1998 | (v0 & ~gkt_grant) | //hold | |
1999 | (v1 & gkt_grant); //shft | |
2000 | ||
2001 | assign v1_in = (v0 & req_m2 & ~gkt_grant) | //new | |
2002 | (v1 & req_m2) | //new | |
2003 | (v1 & ~gkt_grant); //hold | |
2004 | ||
2005 | mmu_htc_ctl_msff_ctl_macro__width_2 qv_reg ( | |
2006 | .scan_in(qv_reg_scanin), | |
2007 | .scan_out(qv_reg_scanout), | |
2008 | .l1clk( l1clk ), | |
2009 | .din ({v0_in, v1_in}), | |
2010 | .dout({v0,v1}), | |
2011 | .siclk(siclk), | |
2012 | .soclk(soclk) | |
2013 | ); | |
2014 | ||
2015 | assign q0_val = v0; | |
2016 | assign q1_val = v1; | |
2017 | ||
2018 | ///////////////////////////////////////////////////////////////////// | |
2019 | // q0 and q1 buffer ctl | |
2020 | // optimize to make minimum use of grant | |
2021 | ///////////////////////////////////////////////////////////////////// | |
2022 | assign htc_wr_q1new = req_m2; | |
2023 | ||
2024 | assign htc_wr_q0new = (~v0 & req_m2) | | |
2025 | (v0 & ~v1 & gkt_grant & req_m2); | |
2026 | assign htc_wr_q0new_nogrant = (~v0 & req_m2); | |
2027 | ||
2028 | assign htc_wr_q0new_grant = (~v0 & req_m2) | | |
2029 | (v0 & ~v1 & req_m2); | |
2030 | ||
2031 | // shift from q1 to q0 if q1 is valid and we get grant. | |
2032 | assign htc_shift_q1 = v1 & gkt_grant; | |
2033 | //assign htc_shift_q1_nogrant = 1'b0; | |
2034 | ||
2035 | assign htc_shift_q1_grant = v1; | |
2036 | ||
2037 | //0in bits_on -var {htc_wr_q0new_grant, htc_shift_q1_grant} -max 1 | |
2038 | //0in bits_on -var {htc_wr_q0new, htc_shift_q1} -max 1 | |
2039 | ||
2040 | ||
2041 | // (htc_wr_q0new | htc_shift_q1) is very late to be used as an enable for q0 | |
2042 | // Instead used htc_q0_en which is an early signal but does not get | |
2043 | // use grant | |
2044 | //assign htc_q0_clken = v0 | v1 | req_m2 | ~htc_mmu_pmen; | |
2045 | ||
2046 | ||
2047 | // implement q0 and q1 for cpkt | |
2048 | assign q1_cpkt_in[4:0] = ({5{htc_wr_q1new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) | | |
2049 | ({5{~htc_wr_q1new}} & q1_cpkt[4:0]); | |
2050 | ||
2051 | mmu_htc_ctl_msff_ctl_macro__width_5 q1cpkt_reg ( | |
2052 | .scan_in(q1cpkt_reg_scanin), | |
2053 | .scan_out(q1cpkt_reg_scanout), | |
2054 | .l1clk( l1clk ), | |
2055 | .din (q1_cpkt_in[4:0]), | |
2056 | .dout(q1_cpkt[4:0]), | |
2057 | .siclk(siclk), | |
2058 | .soclk(soclk) | |
2059 | ); | |
2060 | ||
2061 | assign q0_cpkt_in[4:0] = ({5{htc_wr_q0new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) | | |
2062 | ({5{htc_shift_q1}} & q1_cpkt[4:0]) | | |
2063 | ({5{~htc_wr_q0new & ~htc_shift_q1}} & q0_cpkt[4:0]) ; | |
2064 | ||
2065 | mmu_htc_ctl_msff_ctl_macro__width_5 q0cpkt_reg ( | |
2066 | .scan_in(q0cpkt_reg_scanin), | |
2067 | .scan_out(q0cpkt_reg_scanout), | |
2068 | .l1clk( l1clk ), | |
2069 | .din (q0_cpkt_in[4:0]), | |
2070 | .dout(q0_cpkt[4:0]), | |
2071 | .siclk(siclk), | |
2072 | .soclk(soclk) | |
2073 | ); | |
2074 | ///////////////////////////////////////////////////////////////////// | |
2075 | // output valid control and output buffer control (m3reg) | |
2076 | ///////////////////////////////////////////////////////////////////// | |
2077 | // htc_l15_valid is flopped and sent out as mmu_l15_valid | |
2078 | assign htc_l15_valid = ((req_m2 | q0_val) & ~gkt_full); | |
2079 | ||
2080 | // htc_l15_valid is very late to be used as an enable to htd output flop. | |
2081 | // Instead used htc_l15_en which is an early signal but does not get | |
2082 | // turned off if gkt is full | |
2083 | assign htc_l15_en = req_m2 | q0_val; | |
2084 | ||
2085 | assign htc_wr_m3new = ~q0_val & req_m2; | |
2086 | assign htc_wr_m3q0 = q0_val; | |
2087 | ||
2088 | assign {mmu_l15_cpkt_in_15_13_in[2:0],mmu_l15_cpkt_in_9_8_in[1:0]} = ({5{htc_wr_m3new}} & {htc_l15_cpkt_15_13[2:0],htc_l15_cpkt_9_8[1:0]}) | | |
2089 | ({5{htc_wr_m3q0}} & q0_cpkt[4:0]); | |
2090 | mmu_htc_ctl_msff_ctl_macro__width_7 cpkt_reg ( | |
2091 | .scan_in(cpkt_reg_scanin), | |
2092 | .scan_out(cpkt_reg_scanout), | |
2093 | .l1clk( l1clk ), | |
2094 | .din ({htc_l15_valid, htc_l15_valid, mmu_l15_cpkt_in_15_13_in[2:0],mmu_l15_cpkt_in_9_8_in[1:0]}), | |
2095 | .dout({mmu_l15_valid, mmu_l15_valid_int, mmu_l15_cpkt[2:0],mmu_l15_cpkt[4:3]}), | |
2096 | .siclk(siclk), | |
2097 | .soclk(soclk) | |
2098 | ); | |
2099 | ||
2100 | ||
2101 | // actual mmu pkt format: | |
2102 | //assign mmu_l15_cpkt[25] = mmu_l15_valid; | |
2103 | //assign mmu_l15_cpkt[24:20] = 5'b01000; //rqtyp | |
2104 | //assign mmu_l15_cpkt[19] = 1'b1; //nc | |
2105 | //assign mmu_l15_cpkt[18:16] = cpuid[2:0]; //cpuid | |
2106 | //assign mmu_l15_cpkt[15:13] = tid | |
2107 | //assign mmu_l15_cpkt[12:10] = 3'b000; //inv,pf,bis | |
2108 | //assign mmu_l15_cpkt[9:7] = mmuid | |
2109 | //assign mmu_l15_cpkt[7:0] = 8'b0; //size | |
2110 | ||
2111 | // since only tid and mmuid need to be sent to the gkt, they are compressed to form a 5 bit mmu pkt | |
2112 | // gkt will form the final mmu pkt | |
2113 | ||
2114 | ||
2115 | //msff_ctl_macro grant_lat (width=8) | |
2116 | //( | |
2117 | // .scan_in(grant_lat_scanin), | |
2118 | // .scan_out(grant_lat_scanout), | |
2119 | // .l1clk( l1clk ), | |
2120 | // .din ({grant_del[6:0],l15_mmu_grant}), | |
2121 | // .dout({grant_del[7:0]}) | |
2122 | //); | |
2123 | ||
2124 | assign gkt_grant = l15_mmu_grant; | |
2125 | //assign gkt_grant = grant_del[5]; | |
2126 | ||
2127 | ||
2128 | ///////////////////////////////////////////////////////////////////// | |
2129 | ///////////////////////////////////////////////////////////////////// | |
2130 | // ROOM AVAILABLE SIGNAL | |
2131 | // If room is not available, then the request is killed in M1 stage. | |
2132 | // i.e thr_valid_m1 will not come on. | |
2133 | // Also, cindex will not be incremented. | |
2134 | // room is available for a request in m1 in following cases: | |
2135 | // 1. gkt is not full | |
2136 | // 2. gkt is full, q0 is empty, and there is no request either in m3 or m2 | |
2137 | // 3. gkt is full, q1 is empty, and there is no request in m3 and m2 | |
2138 | ///////////////////////////////////////////////////////////////////// | |
2139 | assign room_avail_m1 = (~gkt_count[1]) | | |
2140 | (~q0_val & (~mmu_l15_valid_int | ~req_m2)) | | |
2141 | (~q1_val & ~mmu_l15_valid_int & ~req_m2); | |
2142 | ||
2143 | ///////////////////////////////////////////////////////////////////// | |
2144 | ||
2145 | ||
2146 | ///////////////////////////////////////////////////////////////////// | |
2147 | // L15 to MMU Interface | |
2148 | ///////////////////////////////////////////////////////////////////// | |
2149 | // | |
2150 | ///////////////////////////////////////////////////////////////////// | |
2151 | // TRS STATE: | NULL | VREQ | VREQ | WAITRR2 | WAITRR3 | | |
2152 | // | HW0 | HW1 | HW2 | HW3 | HW4 | HW5 | HW6 | |
2153 | // | | | | | | | | |
2154 | // | L15 Return | CAM VPN & | arb | MRA Access | RangeCheck| ra2pahit | WriteTLB | |
2155 | // | Data | Context | RR rd_en | asi_grant | | | | |
2156 | // | | TSB hit/Miss | | | | outofrange| mmu_outofrange | |
2157 | // | | | | | | | mmu_ecc_err | |
2158 | // | | | tsb_miss |mmu_tsb_miss | | | | |
2159 | // | | | | | | | | |
2160 | // | |
2161 | ///////////////////////////////////////////////////////////////////// | |
2162 | ||
2163 | ///////////////////////////////////////////////////////////////////// | |
2164 | // HW0 | |
2165 | ///////////////////////////////////////////////////////////////////// | |
2166 | ||
2167 | assign load_ret_hw0 = l15_mmu_valid & (l15_mmu_cpkt[17:14] == 4'b0101); | |
2168 | assign ret_tid_hw0[7:0] = {(l15_mmu_cpkt[8] & l15_mmu_cpkt[7] & l15_mmu_cpkt[6]), | |
2169 | (l15_mmu_cpkt[8] & l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]), | |
2170 | (l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] & l15_mmu_cpkt[6]), | |
2171 | (l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]), | |
2172 | (~l15_mmu_cpkt[8] & l15_mmu_cpkt[7] & l15_mmu_cpkt[6]), | |
2173 | (~l15_mmu_cpkt[8] & l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6]), | |
2174 | (~l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] & l15_mmu_cpkt[6]), | |
2175 | (~l15_mmu_cpkt[8] & ~l15_mmu_cpkt[7] & ~l15_mmu_cpkt[6])}; | |
2176 | ||
2177 | // only flag uncorrectable and not data errors. In case of correctable errors, | |
2178 | // just report them asynchronously to tlu. | |
2179 | assign l2_err_hw0 = l15_mmu_cpkt[11] & hwtwl2_en; | |
2180 | assign l2_ecc_err_type_hw0[1:0] = {l15_mmu_cpkt[11],l15_mmu_cpkt[10]}; | |
2181 | assign ret_tsbid_hw0[1:0] = l15_mmu_cpkt[4:3]; | |
2182 | assign l2miss_hw0 = l15_mmu_cpkt[13]; | |
2183 | ||
2184 | assign l2_cerr_hw0 = ~l15_mmu_cpkt[11] & l15_mmu_cpkt[10] & hwtwl2_en; | |
2185 | ||
2186 | ||
2187 | // latch data coming from gkt | |
2188 | mmu_htc_ctl_msff_ctl_macro__width_19 gkt_hw0_lat0 | |
2189 | ( | |
2190 | .scan_in(gkt_hw0_lat0_scanin), | |
2191 | .scan_out(gkt_hw0_lat0_scanout), | |
2192 | .l1clk ( l1clk ), | |
2193 | .din ({l2_cerr_hw0, l2_err_hw0,l2_ecc_err_type_hw0[1:0],load_ret_hw0,ret_tid_hw0[7:0],ret_tsbid_hw0[1:0],l2miss_hw0, l15_mmu_cpkt[8:6]}), | |
2194 | .dout ({l2_cerr_hw1, l2_err_hw1,l2_ecc_err_type[1:0],load_ret_hw1,ret_tid_hw1[7:0],ret_tsbid_hw1[1:0],l2miss_hw1, mmutid_hw1[2:0]}), | |
2195 | .siclk(siclk), | |
2196 | .soclk(soclk) | |
2197 | ); | |
2198 | ||
2199 | ||
2200 | ///////////////////////////////////////////////////////////////////// | |
2201 | // TSB Hit/Miss Logic (HW1) | |
2202 | ///////////////////////////////////////////////////////////////////// | |
2203 | assign htd_ptr_hit_hw1 = htd_ptr_hit2_hw1 & htd_ptr_hit1_hw1 & htd_ptr_hit0_hw1; | |
2204 | //assign ctx_hit = htd_ignore_ctx_hw1 | htd_ctx_hit_hw1; | |
2205 | assign ctx_hit = (~htd_zeroctx_hw1 & (htd_usectx0_hw1 | htd_usectx1_hw1)) | htd_ctx_hit_hw1; | |
2206 | ||
2207 | // an I side tablewalk can hit only if EP bit is set. | |
2208 | assign ep_hit = htd_dmiss_hw1 | htd_tte_ep_hw1; | |
2209 | ||
2210 | ||
2211 | assign raw_tsb_hit_hw1 = ctx_hit & htd_ptr_hit_hw1 & ep_hit; | |
2212 | assign raw_ep_miss_hw1 = ctx_hit & htd_ptr_hit_hw1 & ~ep_hit; | |
2213 | ||
2214 | assign htc_data_rcvd_hw1[7:0] = ret_tid_hw1[7:0] & {8{load_ret_hw1}}; | |
2215 | ||
2216 | // qualify tsb_hit with no l2err | |
2217 | assign htc_tsb_hit_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{raw_tsb_hit_hw1 & ~l2_err_hw1}}); | |
2218 | assign htc_ep_miss_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{raw_ep_miss_hw1 & ~l2_err_hw1}}); | |
2219 | assign l2_ecc_err_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{l2_err_hw1}}); | |
2220 | ||
2221 | ||
2222 | // tsb processing is done if tsb_hit, or ep_miss, or l2_err | |
2223 | ||
2224 | assign tsb_done_hw1[7:0] = (htc_data_rcvd_hw1[7:0] & {8{raw_tsb_hit_hw1 | raw_ep_miss_hw1 | l2_err_hw1}}); | |
2225 | ||
2226 | assign d_l2_cerr[7:0] = htc_data_rcvd_hw1[7:0] & {8{l2_cerr_hw1}} & htd_dmiss_lat[7:0]; | |
2227 | assign i_l2_cerr[7:0] = htc_data_rcvd_hw1[7:0] & {8{l2_cerr_hw1}} & ~htd_dmiss_lat[7:0]; | |
2228 | ||
2229 | ||
2230 | // Form signals for pmu | |
2231 | assign mmu_pmu_l2ret = load_ret_hw1; | |
2232 | assign mmu_pmu_l2miss = l2miss_hw1; | |
2233 | assign mmu_pmu_dtlb = htd_dmiss_hw1; | |
2234 | assign mmu_pmu_tid[2:0] = mmutid_hw1[2:0]; | |
2235 | ||
2236 | ||
2237 | mmu_htc_ctl_msff_ctl_macro__width_16 final_l2_cerr_lat ( | |
2238 | .scan_in(final_l2_cerr_lat_scanin), | |
2239 | .scan_out(final_l2_cerr_lat_scanout), | |
2240 | .l1clk( l1clk ), | |
2241 | .din ({i_l2_cerr[7:0], d_l2_cerr[7:0]}), | |
2242 | .dout({mmu_i_l2cerr[7:0], mmu_d_l2cerr[7:0]}), | |
2243 | .siclk(siclk), | |
2244 | .soclk(soclk) | |
2245 | ); | |
2246 | ||
2247 | ||
2248 | mmu_htc_ctl_msff_ctl_macro__width_8 tsb_hit_lat ( | |
2249 | .scan_in(tsb_hit_lat_scanin), | |
2250 | .scan_out(tsb_hit_lat_scanout), | |
2251 | .l1clk ( l1clk ), | |
2252 | .din ({htc_tsb_hit_hw1[7:0]}), | |
2253 | .dout ({htc_tsb_hit_hw2[7:0]}), | |
2254 | .siclk(siclk), | |
2255 | .soclk(soclk) | |
2256 | ); | |
2257 | ||
2258 | mmu_htc_ctl_msff_ctl_macro__width_8 ep_miss_lat ( | |
2259 | .scan_in(ep_miss_lat_scanin), | |
2260 | .scan_out(ep_miss_lat_scanout), | |
2261 | .l1clk ( l1clk ), | |
2262 | .din ({htc_ep_miss_hw1[7:0]}), | |
2263 | .dout ({htc_ep_miss_hw2[7:0]}), | |
2264 | .siclk(siclk), | |
2265 | .soclk(soclk) | |
2266 | ); | |
2267 | ||
2268 | mmu_htc_ctl_msff_ctl_macro__width_8 tsb_done_lat ( | |
2269 | .scan_in(tsb_done_lat_scanin), | |
2270 | .scan_out(tsb_done_lat_scanout), | |
2271 | .l1clk ( l1clk ), | |
2272 | .din ({tsb_done_hw1[7:0]}), | |
2273 | .dout ({tsb_done_nocfg_hw2[7:0]}), | |
2274 | .siclk(siclk), | |
2275 | .soclk(soclk) | |
2276 | ); | |
2277 | ||
2278 | mmu_htc_ctl_msff_ctl_macro__width_8 cfg_ecc_lat ( | |
2279 | .scan_in(cfg_ecc_lat_scanin), | |
2280 | .scan_out(cfg_ecc_lat_scanout), | |
2281 | .l1clk ( l1clk ), | |
2282 | .din ({cfg_ecc_err_m3[7:0]}), | |
2283 | .dout ({cfg_ecc_err_m4[7:0]}), | |
2284 | .siclk(siclk), | |
2285 | .soclk(soclk) | |
2286 | ); | |
2287 | ||
2288 | assign htc_tsb_done_hw2[7:0] = tsb_done_nocfg_hw2[7:0] | cfg_ecc_err_m4[7:0]; | |
2289 | ||
2290 | ||
2291 | mmu_htc_ctl_msff_ctl_macro__width_2 tsbid_lat | |
2292 | ( | |
2293 | .scan_in(tsbid_lat_scanin), | |
2294 | .scan_out(tsbid_lat_scanout), | |
2295 | .l1clk ( l1clk ), | |
2296 | .din (ret_tsbid_hw1[1:0]), | |
2297 | .dout (ret_tsbid_hw2[1:0]), | |
2298 | .siclk(siclk), | |
2299 | .soclk(soclk) | |
2300 | ); | |
2301 | ||
2302 | ||
2303 | // latch the tsb config values on a tsb hit | |
2304 | ||
2305 | assign htd_ranotpa_in[0] = (trs_null_st[0] & htd_ranotpa_hw1) | (~trs_null_st[0] & htd_ranotpa[0]); | |
2306 | assign htd_ranotpa_in[1] = (trs_null_st[1] & htd_ranotpa_hw1) | (~trs_null_st[1] & htd_ranotpa[1]); | |
2307 | assign htd_ranotpa_in[2] = (trs_null_st[2] & htd_ranotpa_hw1) | (~trs_null_st[2] & htd_ranotpa[2]); | |
2308 | assign htd_ranotpa_in[3] = (trs_null_st[3] & htd_ranotpa_hw1) | (~trs_null_st[3] & htd_ranotpa[3]); | |
2309 | assign htd_ranotpa_in[4] = (trs_null_st[4] & htd_ranotpa_hw1) | (~trs_null_st[4] & htd_ranotpa[4]); | |
2310 | assign htd_ranotpa_in[5] = (trs_null_st[5] & htd_ranotpa_hw1) | (~trs_null_st[5] & htd_ranotpa[5]); | |
2311 | assign htd_ranotpa_in[6] = (trs_null_st[6] & htd_ranotpa_hw1) | (~trs_null_st[6] & htd_ranotpa[6]); | |
2312 | assign htd_ranotpa_in[7] = (trs_null_st[7] & htd_ranotpa_hw1) | (~trs_null_st[7] & htd_ranotpa[7]); | |
2313 | ||
2314 | assign htd_zeroctx_in[0] = (trs_null_st[0] & htd_zeroctx_hw1) | (~trs_null_st[0] & htd_zeroctx[0]); | |
2315 | assign htd_zeroctx_in[1] = (trs_null_st[1] & htd_zeroctx_hw1) | (~trs_null_st[1] & htd_zeroctx[1]); | |
2316 | assign htd_zeroctx_in[2] = (trs_null_st[2] & htd_zeroctx_hw1) | (~trs_null_st[2] & htd_zeroctx[2]); | |
2317 | assign htd_zeroctx_in[3] = (trs_null_st[3] & htd_zeroctx_hw1) | (~trs_null_st[3] & htd_zeroctx[3]); | |
2318 | assign htd_zeroctx_in[4] = (trs_null_st[4] & htd_zeroctx_hw1) | (~trs_null_st[4] & htd_zeroctx[4]); | |
2319 | assign htd_zeroctx_in[5] = (trs_null_st[5] & htd_zeroctx_hw1) | (~trs_null_st[5] & htd_zeroctx[5]); | |
2320 | assign htd_zeroctx_in[6] = (trs_null_st[6] & htd_zeroctx_hw1) | (~trs_null_st[6] & htd_zeroctx[6]); | |
2321 | assign htd_zeroctx_in[7] = (trs_null_st[7] & htd_zeroctx_hw1) | (~trs_null_st[7] & htd_zeroctx[7]); | |
2322 | ||
2323 | assign htd_usectx0_in[0] = (trs_null_st[0] & htd_usectx0_hw1) | (~trs_null_st[0] & htd_usectx0[0]); | |
2324 | assign htd_usectx0_in[1] = (trs_null_st[1] & htd_usectx0_hw1) | (~trs_null_st[1] & htd_usectx0[1]); | |
2325 | assign htd_usectx0_in[2] = (trs_null_st[2] & htd_usectx0_hw1) | (~trs_null_st[2] & htd_usectx0[2]); | |
2326 | assign htd_usectx0_in[3] = (trs_null_st[3] & htd_usectx0_hw1) | (~trs_null_st[3] & htd_usectx0[3]); | |
2327 | assign htd_usectx0_in[4] = (trs_null_st[4] & htd_usectx0_hw1) | (~trs_null_st[4] & htd_usectx0[4]); | |
2328 | assign htd_usectx0_in[5] = (trs_null_st[5] & htd_usectx0_hw1) | (~trs_null_st[5] & htd_usectx0[5]); | |
2329 | assign htd_usectx0_in[6] = (trs_null_st[6] & htd_usectx0_hw1) | (~trs_null_st[6] & htd_usectx0[6]); | |
2330 | assign htd_usectx0_in[7] = (trs_null_st[7] & htd_usectx0_hw1) | (~trs_null_st[7] & htd_usectx0[7]); | |
2331 | ||
2332 | assign htd_usectx1_in[0] = (trs_null_st[0] & htd_usectx1_hw1) | (~trs_null_st[0] & htd_usectx1[0]); | |
2333 | assign htd_usectx1_in[1] = (trs_null_st[1] & htd_usectx1_hw1) | (~trs_null_st[1] & htd_usectx1[1]); | |
2334 | assign htd_usectx1_in[2] = (trs_null_st[2] & htd_usectx1_hw1) | (~trs_null_st[2] & htd_usectx1[2]); | |
2335 | assign htd_usectx1_in[3] = (trs_null_st[3] & htd_usectx1_hw1) | (~trs_null_st[3] & htd_usectx1[3]); | |
2336 | assign htd_usectx1_in[4] = (trs_null_st[4] & htd_usectx1_hw1) | (~trs_null_st[4] & htd_usectx1[4]); | |
2337 | assign htd_usectx1_in[5] = (trs_null_st[5] & htd_usectx1_hw1) | (~trs_null_st[5] & htd_usectx1[5]); | |
2338 | assign htd_usectx1_in[6] = (trs_null_st[6] & htd_usectx1_hw1) | (~trs_null_st[6] & htd_usectx1[6]); | |
2339 | assign htd_usectx1_in[7] = (trs_null_st[7] & htd_usectx1_hw1) | (~trs_null_st[7] & htd_usectx1[7]); | |
2340 | ||
2341 | ||
2342 | mmu_htc_ctl_msff_ctl_macro__width_32 tsb0_lat | |
2343 | ( | |
2344 | .scan_in(tsb0_lat_scanin), | |
2345 | .scan_out(tsb0_lat_scanout), | |
2346 | .l1clk( l1clk), | |
2347 | .din ({htd_ranotpa_in[7:0], htd_zeroctx_in[7:0], htd_usectx0_in[7:0], htd_usectx1_in[7:0]}), | |
2348 | .dout ({htd_ranotpa[7:0], htd_zeroctx[7:0], htd_usectx0[7:0], htd_usectx1[7:0]}), | |
2349 | .siclk(siclk), | |
2350 | .soclk(soclk) | |
2351 | ); | |
2352 | ||
2353 | ||
2354 | ||
2355 | //******************************************************************************** | |
2356 | // Real Range Register & Physical Offset Register Read (HW2) | |
2357 | //******************************************************************************** | |
2358 | ||
2359 | assign rr_index[1:0] = ({next_rrindex_bit1[0],next_rrindex_bit0[0]} & {2{trs_thrsel_hw2[0]}}) | | |
2360 | ({next_rrindex_bit1[1],next_rrindex_bit0[1]} & {2{trs_thrsel_hw2[1]}}) | | |
2361 | ({next_rrindex_bit1[2],next_rrindex_bit0[2]} & {2{trs_thrsel_hw2[2]}}) | | |
2362 | ({next_rrindex_bit1[3],next_rrindex_bit0[3]} & {2{trs_thrsel_hw2[3]}}) | | |
2363 | ({next_rrindex_bit1[4],next_rrindex_bit0[4]} & {2{trs_thrsel_hw2[4]}}) | | |
2364 | ({next_rrindex_bit1[5],next_rrindex_bit0[5]} & {2{trs_thrsel_hw2[5]}}) | | |
2365 | ({next_rrindex_bit1[6],next_rrindex_bit0[6]} & {2{trs_thrsel_hw2[6]}}) | | |
2366 | ({next_rrindex_bit1[7],next_rrindex_bit0[7]} & {2{trs_thrsel_hw2[7]}}) ; | |
2367 | ||
2368 | assign thr_valid_hw2[7:0] = (trs_valid_hw2[7:0] & ~rr_done_hw3[7:0]); | |
2369 | assign rr_rd_en = |(thr_valid_hw2[7:0]); | |
2370 | ||
2371 | assign rr_rd_thr_id[0] = trs_thrsel_hw2[1] | trs_thrsel_hw2[3] | trs_thrsel_hw2[5] | trs_thrsel_hw2[7]; | |
2372 | assign rr_rd_thr_id[1] = trs_thrsel_hw2[2] | trs_thrsel_hw2[3] | trs_thrsel_hw2[6] | trs_thrsel_hw2[7]; | |
2373 | assign rr_rd_thr_id[2] = trs_thrsel_hw2[4] | trs_thrsel_hw2[5] | trs_thrsel_hw2[6] | trs_thrsel_hw2[7]; | |
2374 | assign rr_addr_in[4:0] = {rr_rd_thr_id[1:0], 1'b1, rr_index[1:0]}; | |
2375 | // mra_rd_en = 01 for TG0, mra_rd_en=10 for TG1 | |
2376 | assign rr_mra_rd_en[1:0] = {rr_rd_thr_id[2],~rr_rd_thr_id[2]}; | |
2377 | ||
2378 | ||
2379 | //******************************************************************************** | |
2380 | // Update TSB Predciton bits based on tsbhit_hw2 (HW2) | |
2381 | //******************************************************************************** | |
2382 | ||
2383 | // mux out the index and prediction bits saved for each thread on tsb hit | |
2384 | assign upd_pred_idx[5:0] = ({6{htc_tsb_hit_hw2[0]}} & pred_idx0[5:0]) | | |
2385 | ({6{htc_tsb_hit_hw2[1]}} & pred_idx1[5:0]) | | |
2386 | ({6{htc_tsb_hit_hw2[2]}} & pred_idx2[5:0]) | | |
2387 | ({6{htc_tsb_hit_hw2[3]}} & pred_idx3[5:0]) | | |
2388 | ({6{htc_tsb_hit_hw2[4]}} & pred_idx4[5:0]) | | |
2389 | ({6{htc_tsb_hit_hw2[5]}} & pred_idx5[5:0]) | | |
2390 | ({6{htc_tsb_hit_hw2[6]}} & pred_idx6[5:0]) | | |
2391 | ({6{htc_tsb_hit_hw2[7]}} & pred_idx7[5:0]); | |
2392 | ||
2393 | assign htc_upd_pred_idx_hw2[5:3] = upd_pred_idx[5:3]; | |
2394 | ||
2395 | ||
2396 | assign upd_pred_bit[1:0] = ({2{htc_tsb_hit_hw2[0]}} & pred_bit0[1:0]) | | |
2397 | ({2{htc_tsb_hit_hw2[1]}} & pred_bit1[1:0]) | | |
2398 | ({2{htc_tsb_hit_hw2[2]}} & pred_bit2[1:0]) | | |
2399 | ({2{htc_tsb_hit_hw2[3]}} & pred_bit3[1:0]) | | |
2400 | ({2{htc_tsb_hit_hw2[4]}} & pred_bit4[1:0]) | | |
2401 | ({2{htc_tsb_hit_hw2[5]}} & pred_bit5[1:0]) | | |
2402 | ({2{htc_tsb_hit_hw2[6]}} & pred_bit6[1:0]) | | |
2403 | ({2{htc_tsb_hit_hw2[7]}} & pred_bit7[1:0]); | |
2404 | ||
2405 | ||
2406 | // determine the config reg corresponding to tsb_hit. The return id is not | |
2407 | // sufficient because in case of prediction, the ID does not identify the | |
2408 | // tsb config reg. | |
2409 | ||
2410 | // if (tsbnum[1]) {tsbnum[1:0] = tsbid[1:0]} | |
2411 | // else if (pred_bit[1] == 0) { tsbnum[1:0] = tsbid[1:0] } | |
2412 | // else if ((pred_bit[1] == 1) && (tsbid[1:0] == 2'b00) {tsbnum[1:0] = 2'b01} | |
2413 | // else if ((pred_bit[1] == 1) && (tsbid[1:0] == 2'b01) {tsbnum[1:0] = 2'b00} | |
2414 | ||
2415 | assign ret_tsbnum_hw2[1:0] = ({2{~upd_pred_bit[1] | ret_tsbid_hw2[1]}} & ret_tsbid_hw2[1:0]) | | |
2416 | ({2{upd_pred_bit[1] & ~ret_tsbid_hw2[1] & ~ret_tsbid_hw2[0]}} & 2'b01) | | |
2417 | ({2{upd_pred_bit[1] & ~ret_tsbid_hw2[1] & ret_tsbid_hw2[0]}} & 2'b00); | |
2418 | ||
2419 | ||
2420 | assign inc_pred = (ret_tsbnum_hw2[1:0] == 2'b01) & (upd_pred_bit[1:0] != 2'b11); // inc pred count if tsb hit on tsbptr1, saturate at 3 | |
2421 | assign dec_pred = (ret_tsbnum_hw2[1:0] == 2'b00) & (upd_pred_bit[1:0] != 2'b00); // dec pred count if tsb hit on tsbptr0, saturate at 0 | |
2422 | ||
2423 | assign htc_new_pred_bit[1:0] = ({2{inc_pred}} & (upd_pred_bit[1:0] + 2'b01)) | | |
2424 | ({2{dec_pred}} & (upd_pred_bit[1:0] - 2'b01)) | | |
2425 | ({2{~inc_pred & ~dec_pred}} & (upd_pred_bit[1:0])); | |
2426 | ||
2427 | // create the new prediction row | |
2428 | assign htc_upd_grp[0] = ~upd_pred_idx[2] & ~upd_pred_idx[1] & ~upd_pred_idx[0]; | |
2429 | assign htc_upd_grp[1] = ~upd_pred_idx[2] & ~upd_pred_idx[1] & upd_pred_idx[0]; | |
2430 | assign htc_upd_grp[2] = ~upd_pred_idx[2] & upd_pred_idx[1] & ~upd_pred_idx[0]; | |
2431 | assign htc_upd_grp[3] = ~upd_pred_idx[2] & upd_pred_idx[1] & upd_pred_idx[0]; | |
2432 | assign htc_upd_grp[4] = upd_pred_idx[2] & ~upd_pred_idx[1] & ~upd_pred_idx[0]; | |
2433 | assign htc_upd_grp[5] = upd_pred_idx[2] & ~upd_pred_idx[1] & upd_pred_idx[0]; | |
2434 | assign htc_upd_grp[6] = upd_pred_idx[2] & upd_pred_idx[1] & ~upd_pred_idx[0]; | |
2435 | assign htc_upd_grp[7] = upd_pred_idx[2] & upd_pred_idx[1] & upd_pred_idx[0]; | |
2436 | ||
2437 | assign htc_upd_grp_x[7:0] = ~htc_upd_grp[7:0]; | |
2438 | ||
2439 | ||
2440 | ||
2441 | assign pred_upd_en = |(htc_tsb_hit_hw2[7:0] & htc_hwtw_pred[7:0]); | |
2442 | ||
2443 | assign htc_wrpred0_hw2 = ~upd_pred_idx[5] & ~upd_pred_idx[4] & pred_upd_en; | |
2444 | assign htc_wrpred1_hw2 = ~upd_pred_idx[5] & upd_pred_idx[4] & pred_upd_en; | |
2445 | assign htc_wrpred2_hw2 = upd_pred_idx[5] & ~upd_pred_idx[4] & pred_upd_en; | |
2446 | assign htc_wrpred3_hw2 = upd_pred_idx[5] & upd_pred_idx[4] & pred_upd_en; | |
2447 | ||
2448 | ||
2449 | ||
2450 | mmu_htc_ctl_msff_ctl_macro__width_3 rr_addr_hw2_lat | |
2451 | ( | |
2452 | .scan_in(rr_addr_hw2_lat_scanin), | |
2453 | .scan_out(rr_addr_hw2_lat_scanout), | |
2454 | .l1clk ( l1clk ), | |
2455 | .din (rr_addr_in[2:0]), | |
2456 | .dout (rr_addr_hw3[2:0]), | |
2457 | .siclk(siclk), | |
2458 | .soclk(soclk) | |
2459 | ); | |
2460 | ||
2461 | mmu_htc_ctl_msff_ctl_macro__width_2 rr_index_hw2_lat | |
2462 | ( | |
2463 | .scan_in(rr_index_hw2_lat_scanin), | |
2464 | .scan_out(rr_index_hw2_lat_scanout), | |
2465 | .l1clk ( l1clk ), | |
2466 | .din (rr_index[1:0]), | |
2467 | .dout (rr_index_hw3[1:0]), | |
2468 | .siclk(siclk), | |
2469 | .soclk(soclk) | |
2470 | ); | |
2471 | ||
2472 | mmu_htc_ctl_msff_ctl_macro__width_8 rr_prevalid_lat | |
2473 | ( | |
2474 | .scan_in(rr_prevalid_lat_scanin), | |
2475 | .scan_out(rr_prevalid_lat_scanout), | |
2476 | .l1clk ( l1clk ), | |
2477 | .din (thr_valid_hw2[7:0]), | |
2478 | .dout (htc_thr_prevalid_hw3[7:0]), | |
2479 | .siclk(siclk), | |
2480 | .soclk(soclk) | |
2481 | ); | |
2482 | ||
2483 | ///////////////////////////////////////////////////////////////////// | |
2484 | // MRA Access Cycle - For RR and Physical Offset(HW3) | |
2485 | ///////////////////////////////////////////////////////////////////// | |
2486 | // real range valid | |
2487 | assign htc_thr_valid_hw3[7:0] = ({8{asi_mra_req_grant}} & htc_thr_prevalid_hw3[7:0]); | |
2488 | assign rr_done_hw3[7:0] = {8{rr_index_hw3[1] & rr_index_hw3[0]}} & htc_thr_valid_hw3[7:0]; | |
2489 | ||
2490 | assign rr_read_tg0_hw3 = |(htc_thr_valid_hw3[3:0]); | |
2491 | assign rr_read_tg1_hw3 = |(htc_thr_valid_hw3[7:4]); | |
2492 | assign htc_hw3_clken = (|(htc_thr_valid_hw3[7:0])) | ~htc_mmu_pmen; | |
2493 | ||
2494 | ||
2495 | mmu_htc_ctl_msff_ctl_macro__width_5 stg_hw3_lat ( | |
2496 | .scan_in(stg_hw3_lat_scanin), | |
2497 | .scan_out(stg_hw3_lat_scanout), | |
2498 | .l1clk ( l1clk ), | |
2499 | .din ({rr_read_tg0_hw3, rr_read_tg1_hw3, rr_addr_hw3[2:0]}), | |
2500 | .dout ({rr_read_tg0_hw4, rr_read_tg1_hw4, rr_addr_hw4[2:0]}), | |
2501 | .siclk(siclk), | |
2502 | .soclk(soclk) | |
2503 | ); | |
2504 | ||
2505 | // should be free running | |
2506 | mmu_htc_ctl_msff_ctl_macro__width_8 thr_valid_hw3_lat ( | |
2507 | .scan_in(thr_valid_hw3_lat_scanin), | |
2508 | .scan_out(thr_valid_hw3_lat_scanout), | |
2509 | .l1clk ( l1clk ), | |
2510 | .din ({htc_thr_valid_hw3[7:0]}), | |
2511 | .dout ({htc_thr_valid_hw4[7:0]}), | |
2512 | .siclk(siclk), | |
2513 | .soclk(soclk) | |
2514 | ); | |
2515 | ||
2516 | ///////////////////////////////////////////////////////////////////// | |
2517 | // Range Checking & RA --> PA (HW4) | |
2518 | // Perform RA --> PA for Sun4u format | |
2519 | // Check if RA is within Real Range for give thread | |
2520 | ///////////////////////////////////////////////////////////////////// | |
2521 | // do not generate a ra2pahit if ep_mask=0 for I side twalk | |
2522 | assign ra2pahit_raw = htd_ra2pa_lower_hit_hw4 & htd_ra2pa_upper_hit_hw4 & htd_razero_hw4 & htd_range_en_hw4; | |
2523 | ||
2524 | // signal ra2pahit if | |
2525 | // ranotpa is set | |
2526 | // no ecc err on mra read | |
2527 | // allow only one ra2pahit per thread | |
2528 | ||
2529 | //0in bits_on -var {ra2pahit_thr_hw4[7:0]} -max 1 | |
2530 | ||
2531 | assign htc_thr_ra_valid_hw4[7:0] = htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0]; | |
2532 | ||
2533 | ||
2534 | assign ra2pahit_thr_hw4[7:0] = htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0] & {8{ra2pahit_raw}} & | |
2535 | ~rr_ecc_err_hw5[7:0] & ~disable_ra2pahit_st[7:0]; | |
2536 | ||
2537 | assign htc_ranotpax_hw4[7:0] = (~htd_ranotpa[7:0] & htc_thr_valid_hw4[7:0] & ~disable_ra2pahit_st[7:0] & ~rr_ecc_err_hw5[7:0]); | |
2538 | ||
2539 | // disable ra2pahit after the first hit, or eccerr, or ~ranotpa | |
2540 | assign disable_ra2pahit_st_in[7:0] = (ra2pahit_thr_hw4[7:0] | htc_ranotpax_hw4[7:0] | disable_ra2pahit_st[7:0] | rr_ecc_err_hw5[7:0]) & ~trs_null_st[7:0]; | |
2541 | ||
2542 | ||
2543 | assign htc_ranotpa_hw4 = |(htd_ranotpa[7:0] & htc_thr_valid_hw4[7:0]); | |
2544 | assign htc_zeroctx_hw4 = |(htd_zeroctx[7:0] & htc_thr_valid_hw4[7:0]); | |
2545 | assign htc_usectx0_hw4 = |(htd_usectx0[7:0] & htc_thr_valid_hw4[7:0]); | |
2546 | assign htc_usectx1_hw4 = |(htd_usectx1[7:0] & htc_thr_valid_hw4[7:0]); | |
2547 | assign htc_sec_ctx_hw4 = |(htd_sec_ctx[7:0] & htc_thr_valid_hw4[7:0]); | |
2548 | // from prm | |
2549 | // hwtalk ignores use_ctx0 and use_ctx1 if it is a zero context. | |
2550 | // If it is a non-zero context, and use_ctx_0 is 1, hw twalk writes the value of context reg 0 to tlb. | |
2551 | // If it is a non-zero context, and use_ctx_0 is 0, and use_ctx_1 is 1, hw twalk writes the | |
2552 | // value of context reg 1 to tlb. | |
2553 | ||
2554 | assign htc_new_use_ctx0_hw4 = ~htc_zeroctx_hw4 & htc_usectx0_hw4; | |
2555 | assign htc_new_use_ctx1_hw4 = ~htc_zeroctx_hw4 & ~htc_usectx0_hw4 & htc_usectx1_hw4; | |
2556 | ||
2557 | ||
2558 | //assign rr_ecc_err = (rr_read_tg0_hw4 & mra0_ecc_err) | | |
2559 | // (rr_read_tg1_hw4 & mra1_ecc_err); | |
2560 | ||
2561 | //assign rr_ecc_err_hw4[7:0] = ({8{rr_ecc_err}} & htc_thr_valid_hw4[7:0] & htd_ranotpa[7:0]); | |
2562 | //assign rr_ecc_err_type_hw4[1:0] = ({2{rr_read_tg0_hw4}} & mra0_err_type[1:0]) | | |
2563 | // ({2{rr_read_tg1_hw4}} & mra1_err_type[1:0]); | |
2564 | ||
2565 | assign rr_ecc_err_index_hw4[2:0] = rr_addr_hw4[2:0]; | |
2566 | ||
2567 | assign htc_hw4_clken = (|(htc_thr_valid_hw4[7:0])) | ~htc_mmu_pmen; | |
2568 | ||
2569 | // create a speculative tlb write signal for power management | |
2570 | // use flopped version of htd_dmiss. | |
2571 | assign tlb_clken_hw4[7:0] = ra2pahit_thr_hw4[7:0] | htc_ranotpax_hw4[7:0]; | |
2572 | assign htc_dtlb_clken_hw4[7:0] = (tlb_clken_hw4[7:0] & htd_dmiss_lat[7:0]) | {8{~htc_mmu_pmen}}; | |
2573 | assign htc_itlb_clken_hw4[7:0] = (tlb_clken_hw4[7:0] & ~htd_dmiss_lat[7:0]) | {8{~htc_mmu_pmen}}; | |
2574 | ||
2575 | mmu_htc_ctl_msff_ctl_macro__width_16 rr_ranotpax_hw4_lat ( | |
2576 | .scan_in(rr_ranotpax_hw4_lat_scanin), | |
2577 | .scan_out(rr_ranotpax_hw4_lat_scanout), | |
2578 | .l1clk( l1clk ), | |
2579 | .din ({htc_ranotpax_hw4[7:0], htc_thr_ra_valid_hw4[7:0]}), | |
2580 | .dout ({htc_ranotpax_hw5[7:0], htc_thr_ra_valid_hw5[7:0]}), | |
2581 | .siclk(siclk), | |
2582 | .soclk(soclk) | |
2583 | ); | |
2584 | ||
2585 | mmu_htc_ctl_msff_ctl_macro__width_8 ra2pahit_st_lat ( | |
2586 | .scan_in(ra2pahit_st_lat_scanin), | |
2587 | .scan_out(ra2pahit_st_lat_scanout), | |
2588 | .l1clk( l1clk ), | |
2589 | .din ({disable_ra2pahit_st_in[7:0]}), | |
2590 | .dout ({disable_ra2pahit_st[7:0]}), | |
2591 | .siclk(siclk), | |
2592 | .soclk(soclk) | |
2593 | ); | |
2594 | ||
2595 | mmu_htc_ctl_msff_ctl_macro__width_8 ra2pahit_lat ( | |
2596 | .scan_in(ra2pahit_lat_scanin), | |
2597 | .scan_out(ra2pahit_lat_scanout), | |
2598 | .l1clk( l1clk ), | |
2599 | .din ({ra2pahit_thr_hw4[7:0]}), | |
2600 | .dout ({ra2pahit_hw5[7:0]}), | |
2601 | .siclk(siclk), | |
2602 | .soclk(soclk) | |
2603 | ); | |
2604 | ||
2605 | mmu_htc_ctl_msff_ctl_macro__width_8 hw4_stg_lat1 | |
2606 | ( | |
2607 | .scan_in(hw4_stg_lat1_scanin), | |
2608 | .scan_out(hw4_stg_lat1_scanout), | |
2609 | .l1clk( l1clk ), | |
2610 | .din ({rr_read_tg0_hw4, rr_read_tg1_hw4, rr_ecc_err_index_hw4[2:0], htc_new_use_ctx0_hw4, htc_new_use_ctx1_hw4, htc_sec_ctx_hw4}), | |
2611 | .dout ({rr_read_tg0_hw5, rr_read_tg1_hw5, rr_ecc_err_index[2:0], mmu_use_context_0, mmu_use_context_1, mmu_sec_context}), | |
2612 | .siclk(siclk), | |
2613 | .soclk(soclk) | |
2614 | ); | |
2615 | ||
2616 | mmu_htc_ctl_msff_ctl_macro__width_16 hw4_stg_lat2 | |
2617 | ( | |
2618 | .scan_in(hw4_stg_lat2_scanin), | |
2619 | .scan_out(hw4_stg_lat2_scanout), | |
2620 | .l1clk( l1clk ), | |
2621 | .din ({htc_dtlb_clken_hw4[7:0],htc_itlb_clken_hw4[7:0]}), | |
2622 | .dout ({htc_dtlb_clken[7:0],htc_itlb_clken[7:0]}), | |
2623 | .siclk(siclk), | |
2624 | .soclk(soclk) | |
2625 | ); | |
2626 | ||
2627 | //assign rr_ecc_err = (rr_read_tg0_hw4 & mra0_ecc_err) | | |
2628 | // (rr_read_tg1_hw4 & mra1_ecc_err); | |
2629 | ||
2630 | assign rr_ecc_err_hw5[7:0] = ({8{((rr_read_tg0_hw5 & mra0_ecc_err_lat) | (rr_read_tg1_hw5 & mra1_ecc_err_lat))}} & | |
2631 | htc_thr_ra_valid_hw5[7:0]); | |
2632 | assign rr_ecc_err_type[1:0] = ({2{rr_read_tg0_hw5}} & mra0_err_type_lat[1:0]) | | |
2633 | ({2{rr_read_tg1_hw5}} & mra1_err_type_lat[1:0]); | |
2634 | ||
2635 | ///////////////////////////////////////////////////////////////////// | |
2636 | // => generate tlb write enable (HW5) | |
2637 | // => write into I/D TLB DataIn and Tag Access Register | |
2638 | // => generate out of range signals, ecc err signals | |
2639 | ///////////////////////////////////////////////////////////////////// | |
2640 | ||
2641 | //0in bits_on -var {tlb_wr_en[7:0]} -max 1 | |
2642 | ||
2643 | assign htc_ra2pahit_hw5[7:0] = ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0]; | |
2644 | ||
2645 | assign tlb_wr_en[7:0] = (htc_ra2pahit_hw5[7:0]) | | |
2646 | (htc_ranotpax_hw5[7:0]); | |
2647 | ||
2648 | assign htc_rd_tteq[7:0] = tlb_wr_en[7:0]; | |
2649 | ||
2650 | ||
2651 | assign htc_wr_itlb_data_in[7:0] = ~htd_dmiss_lat[7:0] & tlb_wr_en[7:0]; | |
2652 | assign htc_wr_dtlb_data_in[7:0] = htd_dmiss_lat[7:0] & tlb_wr_en[7:0]; | |
2653 | ||
2654 | assign mmu_reload_done_din[7:0] = tlb_wr_en[7:0]; | |
2655 | ||
2656 | ||
2657 | // Out of range is qualified with ranotpa and ~ecc_err in trs. | |
2658 | ||
2659 | assign i_tte_outofrange[7:0] = trs_waitrr3_st[7:0] & ~ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0] & ~htd_dmiss_lat[7:0]; | |
2660 | assign d_tte_outofrange[7:0] = trs_waitrr3_st[7:0] & ~ra2pahit_hw5[7:0] & ~rr_ecc_err_hw5[7:0] & htd_dmiss_lat[7:0]; | |
2661 | ||
2662 | ||
2663 | ||
2664 | assign final_ecc_err_hw5[7:0] = trs_ecc_err[7:0]; | |
2665 | ||
2666 | ||
2667 | assign i_ecc_err[7:0] = final_ecc_err_hw5[7:0] & ~htd_dmiss_lat[7:0]; | |
2668 | assign d_ecc_err[7:0] = final_ecc_err_hw5[7:0] & htd_dmiss_lat[7:0]; | |
2669 | ||
2670 | ||
2671 | // should be free running latch | |
2672 | mmu_htc_ctl_msff_ctl_macro__width_8 stg_hw5_lat ( | |
2673 | .scan_in(stg_hw5_lat_scanin), | |
2674 | .scan_out(stg_hw5_lat_scanout), | |
2675 | .l1clk( l1clk ), | |
2676 | .din ({mmu_reload_done_din[7:0]}), | |
2677 | .dout ({mmu_reload_done[7:0]}), | |
2678 | .siclk(siclk), | |
2679 | .soclk(soclk) | |
2680 | ); | |
2681 | ||
2682 | // should be free running latch | |
2683 | mmu_htc_ctl_msff_ctl_macro__width_16 outofrangemiss_lat ( | |
2684 | .scan_in(outofrangemiss_lat_scanin), | |
2685 | .scan_out(outofrangemiss_lat_scanout), | |
2686 | .l1clk( l1clk ), | |
2687 | .din ({i_tte_outofrange[7:0], d_tte_outofrange[7:0]}), | |
2688 | .dout({mmu_i_tte_outofrange[7:0], mmu_d_tte_outofrange[7:0]}), | |
2689 | .siclk(siclk), | |
2690 | .soclk(soclk) | |
2691 | ); | |
2692 | ||
2693 | // should be free running latch | |
2694 | mmu_htc_ctl_msff_ctl_macro__width_16 final_ecc_err_lat ( | |
2695 | .scan_in(final_ecc_err_lat_scanin), | |
2696 | .scan_out(final_ecc_err_lat_scanout), | |
2697 | .l1clk( l1clk ), | |
2698 | .din ({i_ecc_err[7:0], d_ecc_err[7:0]}), | |
2699 | .dout({mmu_i_eccerr[7:0], mmu_d_eccerr[7:0]}), | |
2700 | .siclk(siclk), | |
2701 | .soclk(soclk) | |
2702 | ); | |
2703 | ||
2704 | mmu_htc_ctl_msff_ctl_macro__width_24 err_type_lat ( | |
2705 | .scan_in(err_type_lat_scanin), | |
2706 | .scan_out(err_type_lat_scanout), | |
2707 | .l1clk( l1clk), | |
2708 | .din ({trs0_err_type[2:0], | |
2709 | trs1_err_type[2:0], | |
2710 | trs2_err_type[2:0], | |
2711 | trs3_err_type[2:0], | |
2712 | trs4_err_type[2:0], | |
2713 | trs5_err_type[2:0], | |
2714 | trs6_err_type[2:0], | |
2715 | trs7_err_type[2:0]}), | |
2716 | .dout({htc_thr0_err_type[2:0], | |
2717 | htc_thr1_err_type[2:0], | |
2718 | htc_thr2_err_type[2:0], | |
2719 | htc_thr3_err_type[2:0], | |
2720 | htc_thr4_err_type[2:0], | |
2721 | htc_thr5_err_type[2:0], | |
2722 | htc_thr6_err_type[2:0], | |
2723 | htc_thr7_err_type[2:0]}), | |
2724 | .siclk(siclk), | |
2725 | .soclk(soclk) | |
2726 | ); | |
2727 | ||
2728 | mmu_htc_ctl_msff_ctl_macro__width_24 err_index_lat ( | |
2729 | .scan_in(err_index_lat_scanin), | |
2730 | .scan_out(err_index_lat_scanout), | |
2731 | .l1clk( l1clk), | |
2732 | .din ({trs0_err_index[2:0], | |
2733 | trs1_err_index[2:0], | |
2734 | trs2_err_index[2:0], | |
2735 | trs3_err_index[2:0], | |
2736 | trs4_err_index[2:0], | |
2737 | trs5_err_index[2:0], | |
2738 | trs6_err_index[2:0], | |
2739 | trs7_err_index[2:0]}), | |
2740 | .dout({htc_thr0_err_index[2:0], | |
2741 | htc_thr1_err_index[2:0], | |
2742 | htc_thr2_err_index[2:0], | |
2743 | htc_thr3_err_index[2:0], | |
2744 | htc_thr4_err_index[2:0], | |
2745 | htc_thr5_err_index[2:0], | |
2746 | htc_thr6_err_index[2:0], | |
2747 | htc_thr7_err_index[2:0]}), | |
2748 | .siclk(siclk), | |
2749 | .soclk(soclk) | |
2750 | ); | |
2751 | /////////////////////////////////////////////////////////////////////// | |
2752 | /////////////////////////////////////////////////////////////////////// | |
2753 | // report exception due to ep miss | |
2754 | assign i_unauth_access[7:0] = trs_ep_err[7:0]; | |
2755 | ||
2756 | ||
2757 | ||
2758 | /////////////////////////////////////////////////////////////////////// | |
2759 | // Signal tsb_miss in hw2 | |
2760 | ///////////////////////////////////////////////////////////////////// | |
2761 | assign i_tsb_miss[7:0] = tsm_tsb_miss_hw2[7:0] & ~htd_dmiss_lat[7:0] & ~htc_ep_miss_hw2[7:0]; | |
2762 | assign d_tsb_miss[7:0] = tsm_tsb_miss_hw2[7:0] & htd_dmiss_lat[7:0]; | |
2763 | ||
2764 | ||
2765 | ||
2766 | mmu_htc_ctl_msff_ctl_macro__width_24 tsbmiss_lat ( | |
2767 | .scan_in(tsbmiss_lat_scanin), | |
2768 | .scan_out(tsbmiss_lat_scanout), | |
2769 | .l1clk( l1clk ), | |
2770 | .din ({i_unauth_access[7:0], i_tsb_miss[7:0], d_tsb_miss[7:0]}), | |
2771 | .dout({mmu_i_unauth_access[7:0], mmu_i_tsb_miss[7:0], mmu_d_tsb_miss[7:0]}), | |
2772 | .siclk(siclk), | |
2773 | .soclk(soclk) | |
2774 | ); | |
2775 | ||
2776 | ||
2777 | ||
2778 | assign l15_mmu_cpkt_unused[5:0] = {l15_mmu_cpkt[2:0],l15_mmu_cpkt[5],l15_mmu_cpkt[9],l15_mmu_cpkt[12]}; | |
2779 | ||
2780 | //////////////////////////////////////////////////////// | |
2781 | // SPARE CELLS | |
2782 | //////////////////////////////////////////////////////// | |
2783 | mmu_htc_ctl_spare_ctl_macro__num_7 spares ( | |
2784 | .scan_in(spares_scanin), | |
2785 | .scan_out(spares_scanout), | |
2786 | .l1clk (l1clk), | |
2787 | .siclk(siclk), | |
2788 | .soclk(soclk) | |
2789 | ); | |
2790 | //////////////////////////////////////////////////////// | |
2791 | ||
2792 | supply0 vss; | |
2793 | supply1 vdd; | |
2794 | ||
2795 | // fixscan start: | |
2796 | assign pmen_reg_scanin = scan_in ; | |
2797 | assign tlb_miss_lat_scanin = pmen_reg_scanout ; | |
2798 | assign tlb_cerer_lat_scanin = tlb_miss_lat_scanout ; | |
2799 | assign favour_bit_reg_scanin = tlb_cerer_lat_scanout ; | |
2800 | assign ptr0_reg_scanin = favour_bit_reg_scanout ; | |
2801 | assign ptr1_reg_scanin = ptr0_reg_scanout ; | |
2802 | assign conf_idx_reg_scanin = ptr1_reg_scanout ; | |
2803 | assign rr_idx_reg_scanin = conf_idx_reg_scanout ; | |
2804 | assign m1_stg_lat_scanin = rr_idx_reg_scanout ; | |
2805 | assign conf_prevalid_lat_scanin = m1_stg_lat_scanout ; | |
2806 | assign tsbptr_lat_scanin = conf_prevalid_lat_scanout; | |
2807 | assign predrow0_lat_scanin = tsbptr_lat_scanout ; | |
2808 | assign predrow1_lat_scanin = predrow0_lat_scanout ; | |
2809 | assign tlbmiss_lat_scanin = predrow1_lat_scanout ; | |
2810 | assign tlbvalidmiss_lat_scanin = tlbmiss_lat_scanout ; | |
2811 | assign pred0_lat_scanin = tlbvalidmiss_lat_scanout ; | |
2812 | assign pred1_lat_scanin = pred0_lat_scanout ; | |
2813 | assign pred2_lat_scanin = pred1_lat_scanout ; | |
2814 | assign pred3_lat_scanin = pred2_lat_scanout ; | |
2815 | assign pred4_lat_scanin = pred3_lat_scanout ; | |
2816 | assign pred5_lat_scanin = pred4_lat_scanout ; | |
2817 | assign pred6_lat_scanin = pred5_lat_scanout ; | |
2818 | assign pred7_lat_scanin = pred6_lat_scanout ; | |
2819 | assign m2_stg_lat2_scanin = pred7_lat_scanout ; | |
2820 | assign m3_stg_lat1_scanin = m2_stg_lat2_scanout ; | |
2821 | assign gkt_count_reg_scanin = m3_stg_lat1_scanout ; | |
2822 | assign qv_reg_scanin = gkt_count_reg_scanout ; | |
2823 | assign q1cpkt_reg_scanin = qv_reg_scanout ; | |
2824 | assign q0cpkt_reg_scanin = q1cpkt_reg_scanout ; | |
2825 | assign cpkt_reg_scanin = q0cpkt_reg_scanout ; | |
2826 | assign gkt_hw0_lat0_scanin = cpkt_reg_scanout ; | |
2827 | assign final_l2_cerr_lat_scanin = gkt_hw0_lat0_scanout ; | |
2828 | assign tsb_hit_lat_scanin = final_l2_cerr_lat_scanout; | |
2829 | assign ep_miss_lat_scanin = tsb_hit_lat_scanout ; | |
2830 | assign tsb_done_lat_scanin = ep_miss_lat_scanout ; | |
2831 | assign cfg_ecc_lat_scanin = tsb_done_lat_scanout ; | |
2832 | assign tsbid_lat_scanin = cfg_ecc_lat_scanout ; | |
2833 | assign tsb0_lat_scanin = tsbid_lat_scanout ; | |
2834 | assign rr_addr_hw2_lat_scanin = tsb0_lat_scanout ; | |
2835 | assign rr_index_hw2_lat_scanin = rr_addr_hw2_lat_scanout ; | |
2836 | assign rr_prevalid_lat_scanin = rr_index_hw2_lat_scanout ; | |
2837 | assign stg_hw3_lat_scanin = rr_prevalid_lat_scanout ; | |
2838 | assign thr_valid_hw3_lat_scanin = stg_hw3_lat_scanout ; | |
2839 | assign rr_ranotpax_hw4_lat_scanin = thr_valid_hw3_lat_scanout; | |
2840 | assign ra2pahit_st_lat_scanin = rr_ranotpax_hw4_lat_scanout; | |
2841 | assign ra2pahit_lat_scanin = ra2pahit_st_lat_scanout ; | |
2842 | assign hw4_stg_lat1_scanin = ra2pahit_lat_scanout ; | |
2843 | assign hw4_stg_lat2_scanin = hw4_stg_lat1_scanout ; | |
2844 | assign stg_hw5_lat_scanin = hw4_stg_lat2_scanout ; | |
2845 | assign outofrangemiss_lat_scanin = stg_hw5_lat_scanout ; | |
2846 | assign final_ecc_err_lat_scanin = outofrangemiss_lat_scanout; | |
2847 | assign err_type_lat_scanin = final_ecc_err_lat_scanout; | |
2848 | assign err_index_lat_scanin = err_type_lat_scanout ; | |
2849 | assign tsbmiss_lat_scanin = err_index_lat_scanout ; | |
2850 | assign spares_scanin = tsbmiss_lat_scanout ; | |
2851 | assign scan_out = spares_scanout ; | |
2852 | ||
2853 | assign pid0_lat_wmr_scanin = wmr_scan_in ; | |
2854 | assign pid1_lat_wmr_scanin = pid0_lat_wmr_scanout ; | |
2855 | assign pid2_lat_wmr_scanin = pid1_lat_wmr_scanout ; | |
2856 | assign pid3_lat_wmr_scanin = pid2_lat_wmr_scanout ; | |
2857 | assign pid4_lat_wmr_scanin = pid3_lat_wmr_scanout ; | |
2858 | assign pid5_lat_wmr_scanin = pid4_lat_wmr_scanout ; | |
2859 | assign pid6_lat_wmr_scanin = pid5_lat_wmr_scanout ; | |
2860 | assign pid7_lat_wmr_scanin = pid6_lat_wmr_scanout ; | |
2861 | assign wmr_scan_out = pid7_lat_wmr_scanout ; | |
2862 | // fixscan end: | |
2863 | endmodule | |
2864 | ||
2865 | ||
2866 | ||
2867 | ||
2868 | ||
2869 | ||
2870 | // any PARAMS parms go into naming of macro | |
2871 | ||
2872 | module mmu_htc_ctl_l1clkhdr_ctl_macro ( | |
2873 | l2clk, | |
2874 | l1en, | |
2875 | pce_ov, | |
2876 | stop, | |
2877 | se, | |
2878 | l1clk); | |
2879 | ||
2880 | ||
2881 | input l2clk; | |
2882 | input l1en; | |
2883 | input pce_ov; | |
2884 | input stop; | |
2885 | input se; | |
2886 | output l1clk; | |
2887 | ||
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | cl_sc1_l1hdr_8x c_0 ( | |
2893 | ||
2894 | ||
2895 | .l2clk(l2clk), | |
2896 | .pce(l1en), | |
2897 | .l1clk(l1clk), | |
2898 | .se(se), | |
2899 | .pce_ov(pce_ov), | |
2900 | .stop(stop) | |
2901 | ); | |
2902 | ||
2903 | ||
2904 | ||
2905 | endmodule | |
2906 | ||
2907 | ||
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 | ||
2916 | ||
2917 | ||
2918 | ||
2919 | // any PARAMS parms go into naming of macro | |
2920 | ||
2921 | module mmu_htc_ctl_msff_ctl_macro__width_9 ( | |
2922 | din, | |
2923 | l1clk, | |
2924 | scan_in, | |
2925 | siclk, | |
2926 | soclk, | |
2927 | dout, | |
2928 | scan_out); | |
2929 | wire [8:0] fdin; | |
2930 | wire [7:0] so; | |
2931 | ||
2932 | input [8:0] din; | |
2933 | input l1clk; | |
2934 | input scan_in; | |
2935 | ||
2936 | ||
2937 | input siclk; | |
2938 | input soclk; | |
2939 | ||
2940 | output [8:0] dout; | |
2941 | output scan_out; | |
2942 | assign fdin[8:0] = din[8:0]; | |
2943 | ||
2944 | ||
2945 | ||
2946 | ||
2947 | ||
2948 | ||
2949 | dff #(9) d0_0 ( | |
2950 | .l1clk(l1clk), | |
2951 | .siclk(siclk), | |
2952 | .soclk(soclk), | |
2953 | .d(fdin[8:0]), | |
2954 | .si({scan_in,so[7:0]}), | |
2955 | .so({so[7:0],scan_out}), | |
2956 | .q(dout[8:0]) | |
2957 | ); | |
2958 | ||
2959 | ||
2960 | ||
2961 | ||
2962 | ||
2963 | ||
2964 | ||
2965 | ||
2966 | ||
2967 | ||
2968 | ||
2969 | ||
2970 | endmodule | |
2971 | ||
2972 | ||
2973 | ||
2974 | ||
2975 | ||
2976 | ||
2977 | ||
2978 | ||
2979 | ||
2980 | ||
2981 | ||
2982 | ||
2983 | ||
2984 | // any PARAMS parms go into naming of macro | |
2985 | ||
2986 | module mmu_htc_ctl_msff_ctl_macro__width_16 ( | |
2987 | din, | |
2988 | l1clk, | |
2989 | scan_in, | |
2990 | siclk, | |
2991 | soclk, | |
2992 | dout, | |
2993 | scan_out); | |
2994 | wire [15:0] fdin; | |
2995 | wire [14:0] so; | |
2996 | ||
2997 | input [15:0] din; | |
2998 | input l1clk; | |
2999 | input scan_in; | |
3000 | ||
3001 | ||
3002 | input siclk; | |
3003 | input soclk; | |
3004 | ||
3005 | output [15:0] dout; | |
3006 | output scan_out; | |
3007 | assign fdin[15:0] = din[15:0]; | |
3008 | ||
3009 | ||
3010 | ||
3011 | ||
3012 | ||
3013 | ||
3014 | dff #(16) d0_0 ( | |
3015 | .l1clk(l1clk), | |
3016 | .siclk(siclk), | |
3017 | .soclk(soclk), | |
3018 | .d(fdin[15:0]), | |
3019 | .si({scan_in,so[14:0]}), | |
3020 | .so({so[14:0],scan_out}), | |
3021 | .q(dout[15:0]) | |
3022 | ); | |
3023 | ||
3024 | ||
3025 | ||
3026 | ||
3027 | ||
3028 | ||
3029 | ||
3030 | ||
3031 | ||
3032 | ||
3033 | ||
3034 | ||
3035 | endmodule | |
3036 | ||
3037 | ||
3038 | ||
3039 | ||
3040 | ||
3041 | ||
3042 | ||
3043 | ||
3044 | ||
3045 | ||
3046 | ||
3047 | ||
3048 | ||
3049 | // any PARAMS parms go into naming of macro | |
3050 | ||
3051 | module mmu_htc_ctl_msff_ctl_macro__width_2 ( | |
3052 | din, | |
3053 | l1clk, | |
3054 | scan_in, | |
3055 | siclk, | |
3056 | soclk, | |
3057 | dout, | |
3058 | scan_out); | |
3059 | wire [1:0] fdin; | |
3060 | wire [0:0] so; | |
3061 | ||
3062 | input [1:0] din; | |
3063 | input l1clk; | |
3064 | input scan_in; | |
3065 | ||
3066 | ||
3067 | input siclk; | |
3068 | input soclk; | |
3069 | ||
3070 | output [1:0] dout; | |
3071 | output scan_out; | |
3072 | assign fdin[1:0] = din[1:0]; | |
3073 | ||
3074 | ||
3075 | ||
3076 | ||
3077 | ||
3078 | ||
3079 | dff #(2) d0_0 ( | |
3080 | .l1clk(l1clk), | |
3081 | .siclk(siclk), | |
3082 | .soclk(soclk), | |
3083 | .d(fdin[1:0]), | |
3084 | .si({scan_in,so[0:0]}), | |
3085 | .so({so[0:0],scan_out}), | |
3086 | .q(dout[1:0]) | |
3087 | ); | |
3088 | ||
3089 | ||
3090 | ||
3091 | ||
3092 | ||
3093 | ||
3094 | ||
3095 | ||
3096 | ||
3097 | ||
3098 | ||
3099 | ||
3100 | endmodule | |
3101 | ||
3102 | ||
3103 | ||
3104 | ||
3105 | ||
3106 | ||
3107 | ||
3108 | ||
3109 | ||
3110 | ||
3111 | ||
3112 | ||
3113 | ||
3114 | // any PARAMS parms go into naming of macro | |
3115 | ||
3116 | module mmu_htc_ctl_msff_ctl_macro__width_3 ( | |
3117 | din, | |
3118 | l1clk, | |
3119 | scan_in, | |
3120 | siclk, | |
3121 | soclk, | |
3122 | dout, | |
3123 | scan_out); | |
3124 | wire [2:0] fdin; | |
3125 | wire [1:0] so; | |
3126 | ||
3127 | input [2:0] din; | |
3128 | input l1clk; | |
3129 | input scan_in; | |
3130 | ||
3131 | ||
3132 | input siclk; | |
3133 | input soclk; | |
3134 | ||
3135 | output [2:0] dout; | |
3136 | output scan_out; | |
3137 | assign fdin[2:0] = din[2:0]; | |
3138 | ||
3139 | ||
3140 | ||
3141 | ||
3142 | ||
3143 | ||
3144 | dff #(3) d0_0 ( | |
3145 | .l1clk(l1clk), | |
3146 | .siclk(siclk), | |
3147 | .soclk(soclk), | |
3148 | .d(fdin[2:0]), | |
3149 | .si({scan_in,so[1:0]}), | |
3150 | .so({so[1:0],scan_out}), | |
3151 | .q(dout[2:0]) | |
3152 | ); | |
3153 | ||
3154 | ||
3155 | ||
3156 | ||
3157 | ||
3158 | ||
3159 | ||
3160 | ||
3161 | ||
3162 | ||
3163 | ||
3164 | ||
3165 | endmodule | |
3166 | ||
3167 | ||
3168 | ||
3169 | ||
3170 | ||
3171 | ||
3172 | ||
3173 | ||
3174 | ||
3175 | ||
3176 | ||
3177 | ||
3178 | ||
3179 | // any PARAMS parms go into naming of macro | |
3180 | ||
3181 | module mmu_htc_ctl_msff_ctl_macro__width_1 ( | |
3182 | din, | |
3183 | l1clk, | |
3184 | scan_in, | |
3185 | siclk, | |
3186 | soclk, | |
3187 | dout, | |
3188 | scan_out); | |
3189 | wire [0:0] fdin; | |
3190 | ||
3191 | input [0:0] din; | |
3192 | input l1clk; | |
3193 | input scan_in; | |
3194 | ||
3195 | ||
3196 | input siclk; | |
3197 | input soclk; | |
3198 | ||
3199 | output [0:0] dout; | |
3200 | output scan_out; | |
3201 | assign fdin[0:0] = din[0:0]; | |
3202 | ||
3203 | ||
3204 | ||
3205 | ||
3206 | ||
3207 | ||
3208 | dff #(1) d0_0 ( | |
3209 | .l1clk(l1clk), | |
3210 | .siclk(siclk), | |
3211 | .soclk(soclk), | |
3212 | .d(fdin[0:0]), | |
3213 | .si(scan_in), | |
3214 | .so(scan_out), | |
3215 | .q(dout[0:0]) | |
3216 | ); | |
3217 | ||
3218 | ||
3219 | ||
3220 | ||
3221 | ||
3222 | ||
3223 | ||
3224 | ||
3225 | ||
3226 | ||
3227 | ||
3228 | ||
3229 | endmodule | |
3230 | ||
3231 | ||
3232 | ||
3233 | ||
3234 | ||
3235 | ||
3236 | ||
3237 | ||
3238 | ||
3239 | ||
3240 | ||
3241 | ||
3242 | ||
3243 | // any PARAMS parms go into naming of macro | |
3244 | ||
3245 | module mmu_htc_ctl_msff_ctl_macro__width_4 ( | |
3246 | din, | |
3247 | l1clk, | |
3248 | scan_in, | |
3249 | siclk, | |
3250 | soclk, | |
3251 | dout, | |
3252 | scan_out); | |
3253 | wire [3:0] fdin; | |
3254 | wire [2:0] so; | |
3255 | ||
3256 | input [3:0] din; | |
3257 | input l1clk; | |
3258 | input scan_in; | |
3259 | ||
3260 | ||
3261 | input siclk; | |
3262 | input soclk; | |
3263 | ||
3264 | output [3:0] dout; | |
3265 | output scan_out; | |
3266 | assign fdin[3:0] = din[3:0]; | |
3267 | ||
3268 | ||
3269 | ||
3270 | ||
3271 | ||
3272 | ||
3273 | dff #(4) d0_0 ( | |
3274 | .l1clk(l1clk), | |
3275 | .siclk(siclk), | |
3276 | .soclk(soclk), | |
3277 | .d(fdin[3:0]), | |
3278 | .si({scan_in,so[2:0]}), | |
3279 | .so({so[2:0],scan_out}), | |
3280 | .q(dout[3:0]) | |
3281 | ); | |
3282 | ||
3283 | ||
3284 | ||
3285 | ||
3286 | ||
3287 | ||
3288 | ||
3289 | ||
3290 | ||
3291 | ||
3292 | ||
3293 | ||
3294 | endmodule | |
3295 | ||
3296 | ||
3297 | ||
3298 | ||
3299 | ||
3300 | ||
3301 | ||
3302 | ||
3303 | ||
3304 | ||
3305 | ||
3306 | ||
3307 | ||
3308 | // any PARAMS parms go into naming of macro | |
3309 | ||
3310 | module mmu_htc_ctl_msff_ctl_macro__width_6 ( | |
3311 | din, | |
3312 | l1clk, | |
3313 | scan_in, | |
3314 | siclk, | |
3315 | soclk, | |
3316 | dout, | |
3317 | scan_out); | |
3318 | wire [5:0] fdin; | |
3319 | wire [4:0] so; | |
3320 | ||
3321 | input [5:0] din; | |
3322 | input l1clk; | |
3323 | input scan_in; | |
3324 | ||
3325 | ||
3326 | input siclk; | |
3327 | input soclk; | |
3328 | ||
3329 | output [5:0] dout; | |
3330 | output scan_out; | |
3331 | assign fdin[5:0] = din[5:0]; | |
3332 | ||
3333 | ||
3334 | ||
3335 | ||
3336 | ||
3337 | ||
3338 | dff #(6) d0_0 ( | |
3339 | .l1clk(l1clk), | |
3340 | .siclk(siclk), | |
3341 | .soclk(soclk), | |
3342 | .d(fdin[5:0]), | |
3343 | .si({scan_in,so[4:0]}), | |
3344 | .so({so[4:0],scan_out}), | |
3345 | .q(dout[5:0]) | |
3346 | ); | |
3347 | ||
3348 | ||
3349 | ||
3350 | ||
3351 | ||
3352 | ||
3353 | ||
3354 | ||
3355 | ||
3356 | ||
3357 | ||
3358 | ||
3359 | endmodule | |
3360 | ||
3361 | ||
3362 | ||
3363 | ||
3364 | ||
3365 | ||
3366 | ||
3367 | ||
3368 | ||
3369 | ||
3370 | ||
3371 | ||
3372 | ||
3373 | // any PARAMS parms go into naming of macro | |
3374 | ||
3375 | module mmu_htc_ctl_msff_ctl_macro__width_8 ( | |
3376 | din, | |
3377 | l1clk, | |
3378 | scan_in, | |
3379 | siclk, | |
3380 | soclk, | |
3381 | dout, | |
3382 | scan_out); | |
3383 | wire [7:0] fdin; | |
3384 | wire [6:0] so; | |
3385 | ||
3386 | input [7:0] din; | |
3387 | input l1clk; | |
3388 | input scan_in; | |
3389 | ||
3390 | ||
3391 | input siclk; | |
3392 | input soclk; | |
3393 | ||
3394 | output [7:0] dout; | |
3395 | output scan_out; | |
3396 | assign fdin[7:0] = din[7:0]; | |
3397 | ||
3398 | ||
3399 | ||
3400 | ||
3401 | ||
3402 | ||
3403 | dff #(8) d0_0 ( | |
3404 | .l1clk(l1clk), | |
3405 | .siclk(siclk), | |
3406 | .soclk(soclk), | |
3407 | .d(fdin[7:0]), | |
3408 | .si({scan_in,so[6:0]}), | |
3409 | .so({so[6:0],scan_out}), | |
3410 | .q(dout[7:0]) | |
3411 | ); | |
3412 | ||
3413 | ||
3414 | ||
3415 | ||
3416 | ||
3417 | ||
3418 | ||
3419 | ||
3420 | ||
3421 | ||
3422 | ||
3423 | ||
3424 | endmodule | |
3425 | ||
3426 | ||
3427 | ||
3428 | ||
3429 | ||
3430 | ||
3431 | ||
3432 | ||
3433 | ||
3434 | ||
3435 | ||
3436 | ||
3437 | ||
3438 | // any PARAMS parms go into naming of macro | |
3439 | ||
3440 | module mmu_htc_ctl_msff_ctl_macro__width_11 ( | |
3441 | din, | |
3442 | l1clk, | |
3443 | scan_in, | |
3444 | siclk, | |
3445 | soclk, | |
3446 | dout, | |
3447 | scan_out); | |
3448 | wire [10:0] fdin; | |
3449 | wire [9:0] so; | |
3450 | ||
3451 | input [10:0] din; | |
3452 | input l1clk; | |
3453 | input scan_in; | |
3454 | ||
3455 | ||
3456 | input siclk; | |
3457 | input soclk; | |
3458 | ||
3459 | output [10:0] dout; | |
3460 | output scan_out; | |
3461 | assign fdin[10:0] = din[10:0]; | |
3462 | ||
3463 | ||
3464 | ||
3465 | ||
3466 | ||
3467 | ||
3468 | dff #(11) d0_0 ( | |
3469 | .l1clk(l1clk), | |
3470 | .siclk(siclk), | |
3471 | .soclk(soclk), | |
3472 | .d(fdin[10:0]), | |
3473 | .si({scan_in,so[9:0]}), | |
3474 | .so({so[9:0],scan_out}), | |
3475 | .q(dout[10:0]) | |
3476 | ); | |
3477 | ||
3478 | ||
3479 | ||
3480 | ||
3481 | ||
3482 | ||
3483 | ||
3484 | ||
3485 | ||
3486 | ||
3487 | ||
3488 | ||
3489 | endmodule | |
3490 | ||
3491 | ||
3492 | ||
3493 | ||
3494 | ||
3495 | ||
3496 | ||
3497 | ||
3498 | ||
3499 | ||
3500 | ||
3501 | ||
3502 | ||
3503 | // any PARAMS parms go into naming of macro | |
3504 | ||
3505 | module mmu_htc_ctl_msff_ctl_macro__width_22 ( | |
3506 | din, | |
3507 | l1clk, | |
3508 | scan_in, | |
3509 | siclk, | |
3510 | soclk, | |
3511 | dout, | |
3512 | scan_out); | |
3513 | wire [21:0] fdin; | |
3514 | wire [20:0] so; | |
3515 | ||
3516 | input [21:0] din; | |
3517 | input l1clk; | |
3518 | input scan_in; | |
3519 | ||
3520 | ||
3521 | input siclk; | |
3522 | input soclk; | |
3523 | ||
3524 | output [21:0] dout; | |
3525 | output scan_out; | |
3526 | assign fdin[21:0] = din[21:0]; | |
3527 | ||
3528 | ||
3529 | ||
3530 | ||
3531 | ||
3532 | ||
3533 | dff #(22) d0_0 ( | |
3534 | .l1clk(l1clk), | |
3535 | .siclk(siclk), | |
3536 | .soclk(soclk), | |
3537 | .d(fdin[21:0]), | |
3538 | .si({scan_in,so[20:0]}), | |
3539 | .so({so[20:0],scan_out}), | |
3540 | .q(dout[21:0]) | |
3541 | ); | |
3542 | ||
3543 | ||
3544 | ||
3545 | ||
3546 | ||
3547 | ||
3548 | ||
3549 | ||
3550 | ||
3551 | ||
3552 | ||
3553 | ||
3554 | endmodule | |
3555 | ||
3556 | ||
3557 | ||
3558 | ||
3559 | ||
3560 | ||
3561 | ||
3562 | ||
3563 | ||
3564 | ||
3565 | ||
3566 | ||
3567 | ||
3568 | // any PARAMS parms go into naming of macro | |
3569 | ||
3570 | module mmu_htc_ctl_msff_ctl_macro__width_17 ( | |
3571 | din, | |
3572 | l1clk, | |
3573 | scan_in, | |
3574 | siclk, | |
3575 | soclk, | |
3576 | dout, | |
3577 | scan_out); | |
3578 | wire [16:0] fdin; | |
3579 | wire [15:0] so; | |
3580 | ||
3581 | input [16:0] din; | |
3582 | input l1clk; | |
3583 | input scan_in; | |
3584 | ||
3585 | ||
3586 | input siclk; | |
3587 | input soclk; | |
3588 | ||
3589 | output [16:0] dout; | |
3590 | output scan_out; | |
3591 | assign fdin[16:0] = din[16:0]; | |
3592 | ||
3593 | ||
3594 | ||
3595 | ||
3596 | ||
3597 | ||
3598 | dff #(17) d0_0 ( | |
3599 | .l1clk(l1clk), | |
3600 | .siclk(siclk), | |
3601 | .soclk(soclk), | |
3602 | .d(fdin[16:0]), | |
3603 | .si({scan_in,so[15:0]}), | |
3604 | .so({so[15:0],scan_out}), | |
3605 | .q(dout[16:0]) | |
3606 | ); | |
3607 | ||
3608 | ||
3609 | ||
3610 | ||
3611 | ||
3612 | ||
3613 | ||
3614 | ||
3615 | ||
3616 | ||
3617 | ||
3618 | ||
3619 | endmodule | |
3620 | ||
3621 | ||
3622 | ||
3623 | ||
3624 | ||
3625 | ||
3626 | ||
3627 | ||
3628 | ||
3629 | ||
3630 | ||
3631 | ||
3632 | ||
3633 | // any PARAMS parms go into naming of macro | |
3634 | ||
3635 | module mmu_htc_ctl_msff_ctl_macro__width_13 ( | |
3636 | din, | |
3637 | l1clk, | |
3638 | scan_in, | |
3639 | siclk, | |
3640 | soclk, | |
3641 | dout, | |
3642 | scan_out); | |
3643 | wire [12:0] fdin; | |
3644 | wire [11:0] so; | |
3645 | ||
3646 | input [12:0] din; | |
3647 | input l1clk; | |
3648 | input scan_in; | |
3649 | ||
3650 | ||
3651 | input siclk; | |
3652 | input soclk; | |
3653 | ||
3654 | output [12:0] dout; | |
3655 | output scan_out; | |
3656 | assign fdin[12:0] = din[12:0]; | |
3657 | ||
3658 | ||
3659 | ||
3660 | ||
3661 | ||
3662 | ||
3663 | dff #(13) d0_0 ( | |
3664 | .l1clk(l1clk), | |
3665 | .siclk(siclk), | |
3666 | .soclk(soclk), | |
3667 | .d(fdin[12:0]), | |
3668 | .si({scan_in,so[11:0]}), | |
3669 | .so({so[11:0],scan_out}), | |
3670 | .q(dout[12:0]) | |
3671 | ); | |
3672 | ||
3673 | ||
3674 | ||
3675 | ||
3676 | ||
3677 | ||
3678 | ||
3679 | ||
3680 | ||
3681 | ||
3682 | ||
3683 | ||
3684 | endmodule | |
3685 | ||
3686 | ||
3687 | ||
3688 | ||
3689 | ||
3690 | ||
3691 | ||
3692 | ||
3693 | ||
3694 | ||
3695 | ||
3696 | ||
3697 | ||
3698 | // any PARAMS parms go into naming of macro | |
3699 | ||
3700 | module mmu_htc_ctl_msff_ctl_macro__width_5 ( | |
3701 | din, | |
3702 | l1clk, | |
3703 | scan_in, | |
3704 | siclk, | |
3705 | soclk, | |
3706 | dout, | |
3707 | scan_out); | |
3708 | wire [4:0] fdin; | |
3709 | wire [3:0] so; | |
3710 | ||
3711 | input [4:0] din; | |
3712 | input l1clk; | |
3713 | input scan_in; | |
3714 | ||
3715 | ||
3716 | input siclk; | |
3717 | input soclk; | |
3718 | ||
3719 | output [4:0] dout; | |
3720 | output scan_out; | |
3721 | assign fdin[4:0] = din[4:0]; | |
3722 | ||
3723 | ||
3724 | ||
3725 | ||
3726 | ||
3727 | ||
3728 | dff #(5) d0_0 ( | |
3729 | .l1clk(l1clk), | |
3730 | .siclk(siclk), | |
3731 | .soclk(soclk), | |
3732 | .d(fdin[4:0]), | |
3733 | .si({scan_in,so[3:0]}), | |
3734 | .so({so[3:0],scan_out}), | |
3735 | .q(dout[4:0]) | |
3736 | ); | |
3737 | ||
3738 | ||
3739 | ||
3740 | ||
3741 | ||
3742 | ||
3743 | ||
3744 | ||
3745 | ||
3746 | ||
3747 | ||
3748 | ||
3749 | endmodule | |
3750 | ||
3751 | ||
3752 | ||
3753 | ||
3754 | ||
3755 | ||
3756 | ||
3757 | ||
3758 | ||
3759 | ||
3760 | ||
3761 | ||
3762 | ||
3763 | // any PARAMS parms go into naming of macro | |
3764 | ||
3765 | module mmu_htc_ctl_msff_ctl_macro__width_7 ( | |
3766 | din, | |
3767 | l1clk, | |
3768 | scan_in, | |
3769 | siclk, | |
3770 | soclk, | |
3771 | dout, | |
3772 | scan_out); | |
3773 | wire [6:0] fdin; | |
3774 | wire [5:0] so; | |
3775 | ||
3776 | input [6:0] din; | |
3777 | input l1clk; | |
3778 | input scan_in; | |
3779 | ||
3780 | ||
3781 | input siclk; | |
3782 | input soclk; | |
3783 | ||
3784 | output [6:0] dout; | |
3785 | output scan_out; | |
3786 | assign fdin[6:0] = din[6:0]; | |
3787 | ||
3788 | ||
3789 | ||
3790 | ||
3791 | ||
3792 | ||
3793 | dff #(7) d0_0 ( | |
3794 | .l1clk(l1clk), | |
3795 | .siclk(siclk), | |
3796 | .soclk(soclk), | |
3797 | .d(fdin[6:0]), | |
3798 | .si({scan_in,so[5:0]}), | |
3799 | .so({so[5:0],scan_out}), | |
3800 | .q(dout[6:0]) | |
3801 | ); | |
3802 | ||
3803 | ||
3804 | ||
3805 | ||
3806 | ||
3807 | ||
3808 | ||
3809 | ||
3810 | ||
3811 | ||
3812 | ||
3813 | ||
3814 | endmodule | |
3815 | ||
3816 | ||
3817 | ||
3818 | ||
3819 | ||
3820 | ||
3821 | ||
3822 | ||
3823 | ||
3824 | ||
3825 | ||
3826 | ||
3827 | ||
3828 | // any PARAMS parms go into naming of macro | |
3829 | ||
3830 | module mmu_htc_ctl_msff_ctl_macro__width_19 ( | |
3831 | din, | |
3832 | l1clk, | |
3833 | scan_in, | |
3834 | siclk, | |
3835 | soclk, | |
3836 | dout, | |
3837 | scan_out); | |
3838 | wire [18:0] fdin; | |
3839 | wire [17:0] so; | |
3840 | ||
3841 | input [18:0] din; | |
3842 | input l1clk; | |
3843 | input scan_in; | |
3844 | ||
3845 | ||
3846 | input siclk; | |
3847 | input soclk; | |
3848 | ||
3849 | output [18:0] dout; | |
3850 | output scan_out; | |
3851 | assign fdin[18:0] = din[18:0]; | |
3852 | ||
3853 | ||
3854 | ||
3855 | ||
3856 | ||
3857 | ||
3858 | dff #(19) d0_0 ( | |
3859 | .l1clk(l1clk), | |
3860 | .siclk(siclk), | |
3861 | .soclk(soclk), | |
3862 | .d(fdin[18:0]), | |
3863 | .si({scan_in,so[17:0]}), | |
3864 | .so({so[17:0],scan_out}), | |
3865 | .q(dout[18:0]) | |
3866 | ); | |
3867 | ||
3868 | ||
3869 | ||
3870 | ||
3871 | ||
3872 | ||
3873 | ||
3874 | ||
3875 | ||
3876 | ||
3877 | ||
3878 | ||
3879 | endmodule | |
3880 | ||
3881 | ||
3882 | ||
3883 | ||
3884 | ||
3885 | ||
3886 | ||
3887 | ||
3888 | ||
3889 | ||
3890 | ||
3891 | ||
3892 | ||
3893 | // any PARAMS parms go into naming of macro | |
3894 | ||
3895 | module mmu_htc_ctl_msff_ctl_macro__width_32 ( | |
3896 | din, | |
3897 | l1clk, | |
3898 | scan_in, | |
3899 | siclk, | |
3900 | soclk, | |
3901 | dout, | |
3902 | scan_out); | |
3903 | wire [31:0] fdin; | |
3904 | wire [30:0] so; | |
3905 | ||
3906 | input [31:0] din; | |
3907 | input l1clk; | |
3908 | input scan_in; | |
3909 | ||
3910 | ||
3911 | input siclk; | |
3912 | input soclk; | |
3913 | ||
3914 | output [31:0] dout; | |
3915 | output scan_out; | |
3916 | assign fdin[31:0] = din[31:0]; | |
3917 | ||
3918 | ||
3919 | ||
3920 | ||
3921 | ||
3922 | ||
3923 | dff #(32) d0_0 ( | |
3924 | .l1clk(l1clk), | |
3925 | .siclk(siclk), | |
3926 | .soclk(soclk), | |
3927 | .d(fdin[31:0]), | |
3928 | .si({scan_in,so[30:0]}), | |
3929 | .so({so[30:0],scan_out}), | |
3930 | .q(dout[31:0]) | |
3931 | ); | |
3932 | ||
3933 | ||
3934 | ||
3935 | ||
3936 | ||
3937 | ||
3938 | ||
3939 | ||
3940 | ||
3941 | ||
3942 | ||
3943 | ||
3944 | endmodule | |
3945 | ||
3946 | ||
3947 | ||
3948 | ||
3949 | ||
3950 | ||
3951 | ||
3952 | ||
3953 | ||
3954 | ||
3955 | ||
3956 | ||
3957 | ||
3958 | // any PARAMS parms go into naming of macro | |
3959 | ||
3960 | module mmu_htc_ctl_msff_ctl_macro__width_24 ( | |
3961 | din, | |
3962 | l1clk, | |
3963 | scan_in, | |
3964 | siclk, | |
3965 | soclk, | |
3966 | dout, | |
3967 | scan_out); | |
3968 | wire [23:0] fdin; | |
3969 | wire [22:0] so; | |
3970 | ||
3971 | input [23:0] din; | |
3972 | input l1clk; | |
3973 | input scan_in; | |
3974 | ||
3975 | ||
3976 | input siclk; | |
3977 | input soclk; | |
3978 | ||
3979 | output [23:0] dout; | |
3980 | output scan_out; | |
3981 | assign fdin[23:0] = din[23:0]; | |
3982 | ||
3983 | ||
3984 | ||
3985 | ||
3986 | ||
3987 | ||
3988 | dff #(24) d0_0 ( | |
3989 | .l1clk(l1clk), | |
3990 | .siclk(siclk), | |
3991 | .soclk(soclk), | |
3992 | .d(fdin[23:0]), | |
3993 | .si({scan_in,so[22:0]}), | |
3994 | .so({so[22:0],scan_out}), | |
3995 | .q(dout[23:0]) | |
3996 | ); | |
3997 | ||
3998 | ||
3999 | ||
4000 | ||
4001 | ||
4002 | ||
4003 | ||
4004 | ||
4005 | ||
4006 | ||
4007 | ||
4008 | ||
4009 | endmodule | |
4010 | ||
4011 | ||
4012 | ||
4013 | ||
4014 | ||
4015 | ||
4016 | ||
4017 | ||
4018 | ||
4019 | // Description: Spare gate macro for control blocks | |
4020 | // | |
4021 | // Param num controls the number of times the macro is added | |
4022 | // flops=0 can be used to use only combination spare logic | |
4023 | ||
4024 | ||
4025 | module mmu_htc_ctl_spare_ctl_macro__num_7 ( | |
4026 | l1clk, | |
4027 | scan_in, | |
4028 | siclk, | |
4029 | soclk, | |
4030 | scan_out); | |
4031 | wire si_0; | |
4032 | wire so_0; | |
4033 | wire spare0_flop_unused; | |
4034 | wire spare0_buf_32x_unused; | |
4035 | wire spare0_nand3_8x_unused; | |
4036 | wire spare0_inv_8x_unused; | |
4037 | wire spare0_aoi22_4x_unused; | |
4038 | wire spare0_buf_8x_unused; | |
4039 | wire spare0_oai22_4x_unused; | |
4040 | wire spare0_inv_16x_unused; | |
4041 | wire spare0_nand2_16x_unused; | |
4042 | wire spare0_nor3_4x_unused; | |
4043 | wire spare0_nand2_8x_unused; | |
4044 | wire spare0_buf_16x_unused; | |
4045 | wire spare0_nor2_16x_unused; | |
4046 | wire spare0_inv_32x_unused; | |
4047 | wire si_1; | |
4048 | wire so_1; | |
4049 | wire spare1_flop_unused; | |
4050 | wire spare1_buf_32x_unused; | |
4051 | wire spare1_nand3_8x_unused; | |
4052 | wire spare1_inv_8x_unused; | |
4053 | wire spare1_aoi22_4x_unused; | |
4054 | wire spare1_buf_8x_unused; | |
4055 | wire spare1_oai22_4x_unused; | |
4056 | wire spare1_inv_16x_unused; | |
4057 | wire spare1_nand2_16x_unused; | |
4058 | wire spare1_nor3_4x_unused; | |
4059 | wire spare1_nand2_8x_unused; | |
4060 | wire spare1_buf_16x_unused; | |
4061 | wire spare1_nor2_16x_unused; | |
4062 | wire spare1_inv_32x_unused; | |
4063 | wire si_2; | |
4064 | wire so_2; | |
4065 | wire spare2_flop_unused; | |
4066 | wire spare2_buf_32x_unused; | |
4067 | wire spare2_nand3_8x_unused; | |
4068 | wire spare2_inv_8x_unused; | |
4069 | wire spare2_aoi22_4x_unused; | |
4070 | wire spare2_buf_8x_unused; | |
4071 | wire spare2_oai22_4x_unused; | |
4072 | wire spare2_inv_16x_unused; | |
4073 | wire spare2_nand2_16x_unused; | |
4074 | wire spare2_nor3_4x_unused; | |
4075 | wire spare2_nand2_8x_unused; | |
4076 | wire spare2_buf_16x_unused; | |
4077 | wire spare2_nor2_16x_unused; | |
4078 | wire spare2_inv_32x_unused; | |
4079 | wire si_3; | |
4080 | wire so_3; | |
4081 | wire spare3_flop_unused; | |
4082 | wire spare3_buf_32x_unused; | |
4083 | wire spare3_nand3_8x_unused; | |
4084 | wire spare3_inv_8x_unused; | |
4085 | wire spare3_aoi22_4x_unused; | |
4086 | wire spare3_buf_8x_unused; | |
4087 | wire spare3_oai22_4x_unused; | |
4088 | wire spare3_inv_16x_unused; | |
4089 | wire spare3_nand2_16x_unused; | |
4090 | wire spare3_nor3_4x_unused; | |
4091 | wire spare3_nand2_8x_unused; | |
4092 | wire spare3_buf_16x_unused; | |
4093 | wire spare3_nor2_16x_unused; | |
4094 | wire spare3_inv_32x_unused; | |
4095 | wire si_4; | |
4096 | wire so_4; | |
4097 | wire spare4_flop_unused; | |
4098 | wire spare4_buf_32x_unused; | |
4099 | wire spare4_nand3_8x_unused; | |
4100 | wire spare4_inv_8x_unused; | |
4101 | wire spare4_aoi22_4x_unused; | |
4102 | wire spare4_buf_8x_unused; | |
4103 | wire spare4_oai22_4x_unused; | |
4104 | wire spare4_inv_16x_unused; | |
4105 | wire spare4_nand2_16x_unused; | |
4106 | wire spare4_nor3_4x_unused; | |
4107 | wire spare4_nand2_8x_unused; | |
4108 | wire spare4_buf_16x_unused; | |
4109 | wire spare4_nor2_16x_unused; | |
4110 | wire spare4_inv_32x_unused; | |
4111 | wire si_5; | |
4112 | wire so_5; | |
4113 | wire spare5_flop_unused; | |
4114 | wire spare5_buf_32x_unused; | |
4115 | wire spare5_nand3_8x_unused; | |
4116 | wire spare5_inv_8x_unused; | |
4117 | wire spare5_aoi22_4x_unused; | |
4118 | wire spare5_buf_8x_unused; | |
4119 | wire spare5_oai22_4x_unused; | |
4120 | wire spare5_inv_16x_unused; | |
4121 | wire spare5_nand2_16x_unused; | |
4122 | wire spare5_nor3_4x_unused; | |
4123 | wire spare5_nand2_8x_unused; | |
4124 | wire spare5_buf_16x_unused; | |
4125 | wire spare5_nor2_16x_unused; | |
4126 | wire spare5_inv_32x_unused; | |
4127 | wire si_6; | |
4128 | wire so_6; | |
4129 | wire spare6_flop_unused; | |
4130 | wire spare6_buf_32x_unused; | |
4131 | wire spare6_nand3_8x_unused; | |
4132 | wire spare6_inv_8x_unused; | |
4133 | wire spare6_aoi22_4x_unused; | |
4134 | wire spare6_buf_8x_unused; | |
4135 | wire spare6_oai22_4x_unused; | |
4136 | wire spare6_inv_16x_unused; | |
4137 | wire spare6_nand2_16x_unused; | |
4138 | wire spare6_nor3_4x_unused; | |
4139 | wire spare6_nand2_8x_unused; | |
4140 | wire spare6_buf_16x_unused; | |
4141 | wire spare6_nor2_16x_unused; | |
4142 | wire spare6_inv_32x_unused; | |
4143 | ||
4144 | ||
4145 | input l1clk; | |
4146 | input scan_in; | |
4147 | input siclk; | |
4148 | input soclk; | |
4149 | output scan_out; | |
4150 | ||
4151 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
4152 | .siclk(siclk), | |
4153 | .soclk(soclk), | |
4154 | .si(si_0), | |
4155 | .so(so_0), | |
4156 | .d(1'b0), | |
4157 | .q(spare0_flop_unused)); | |
4158 | assign si_0 = scan_in; | |
4159 | ||
4160 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
4161 | .out(spare0_buf_32x_unused)); | |
4162 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
4163 | .in1(1'b1), | |
4164 | .in2(1'b1), | |
4165 | .out(spare0_nand3_8x_unused)); | |
4166 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
4167 | .out(spare0_inv_8x_unused)); | |
4168 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
4169 | .in01(1'b1), | |
4170 | .in10(1'b1), | |
4171 | .in11(1'b1), | |
4172 | .out(spare0_aoi22_4x_unused)); | |
4173 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
4174 | .out(spare0_buf_8x_unused)); | |
4175 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
4176 | .in01(1'b1), | |
4177 | .in10(1'b1), | |
4178 | .in11(1'b1), | |
4179 | .out(spare0_oai22_4x_unused)); | |
4180 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
4181 | .out(spare0_inv_16x_unused)); | |
4182 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
4183 | .in1(1'b1), | |
4184 | .out(spare0_nand2_16x_unused)); | |
4185 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
4186 | .in1(1'b0), | |
4187 | .in2(1'b0), | |
4188 | .out(spare0_nor3_4x_unused)); | |
4189 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
4190 | .in1(1'b1), | |
4191 | .out(spare0_nand2_8x_unused)); | |
4192 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
4193 | .out(spare0_buf_16x_unused)); | |
4194 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
4195 | .in1(1'b0), | |
4196 | .out(spare0_nor2_16x_unused)); | |
4197 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
4198 | .out(spare0_inv_32x_unused)); | |
4199 | ||
4200 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
4201 | .siclk(siclk), | |
4202 | .soclk(soclk), | |
4203 | .si(si_1), | |
4204 | .so(so_1), | |
4205 | .d(1'b0), | |
4206 | .q(spare1_flop_unused)); | |
4207 | assign si_1 = so_0; | |
4208 | ||
4209 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
4210 | .out(spare1_buf_32x_unused)); | |
4211 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
4212 | .in1(1'b1), | |
4213 | .in2(1'b1), | |
4214 | .out(spare1_nand3_8x_unused)); | |
4215 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
4216 | .out(spare1_inv_8x_unused)); | |
4217 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
4218 | .in01(1'b1), | |
4219 | .in10(1'b1), | |
4220 | .in11(1'b1), | |
4221 | .out(spare1_aoi22_4x_unused)); | |
4222 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
4223 | .out(spare1_buf_8x_unused)); | |
4224 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
4225 | .in01(1'b1), | |
4226 | .in10(1'b1), | |
4227 | .in11(1'b1), | |
4228 | .out(spare1_oai22_4x_unused)); | |
4229 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
4230 | .out(spare1_inv_16x_unused)); | |
4231 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
4232 | .in1(1'b1), | |
4233 | .out(spare1_nand2_16x_unused)); | |
4234 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
4235 | .in1(1'b0), | |
4236 | .in2(1'b0), | |
4237 | .out(spare1_nor3_4x_unused)); | |
4238 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
4239 | .in1(1'b1), | |
4240 | .out(spare1_nand2_8x_unused)); | |
4241 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
4242 | .out(spare1_buf_16x_unused)); | |
4243 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
4244 | .in1(1'b0), | |
4245 | .out(spare1_nor2_16x_unused)); | |
4246 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
4247 | .out(spare1_inv_32x_unused)); | |
4248 | ||
4249 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
4250 | .siclk(siclk), | |
4251 | .soclk(soclk), | |
4252 | .si(si_2), | |
4253 | .so(so_2), | |
4254 | .d(1'b0), | |
4255 | .q(spare2_flop_unused)); | |
4256 | assign si_2 = so_1; | |
4257 | ||
4258 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
4259 | .out(spare2_buf_32x_unused)); | |
4260 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
4261 | .in1(1'b1), | |
4262 | .in2(1'b1), | |
4263 | .out(spare2_nand3_8x_unused)); | |
4264 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
4265 | .out(spare2_inv_8x_unused)); | |
4266 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
4267 | .in01(1'b1), | |
4268 | .in10(1'b1), | |
4269 | .in11(1'b1), | |
4270 | .out(spare2_aoi22_4x_unused)); | |
4271 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
4272 | .out(spare2_buf_8x_unused)); | |
4273 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
4274 | .in01(1'b1), | |
4275 | .in10(1'b1), | |
4276 | .in11(1'b1), | |
4277 | .out(spare2_oai22_4x_unused)); | |
4278 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
4279 | .out(spare2_inv_16x_unused)); | |
4280 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
4281 | .in1(1'b1), | |
4282 | .out(spare2_nand2_16x_unused)); | |
4283 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
4284 | .in1(1'b0), | |
4285 | .in2(1'b0), | |
4286 | .out(spare2_nor3_4x_unused)); | |
4287 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
4288 | .in1(1'b1), | |
4289 | .out(spare2_nand2_8x_unused)); | |
4290 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
4291 | .out(spare2_buf_16x_unused)); | |
4292 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
4293 | .in1(1'b0), | |
4294 | .out(spare2_nor2_16x_unused)); | |
4295 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
4296 | .out(spare2_inv_32x_unused)); | |
4297 | ||
4298 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
4299 | .siclk(siclk), | |
4300 | .soclk(soclk), | |
4301 | .si(si_3), | |
4302 | .so(so_3), | |
4303 | .d(1'b0), | |
4304 | .q(spare3_flop_unused)); | |
4305 | assign si_3 = so_2; | |
4306 | ||
4307 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
4308 | .out(spare3_buf_32x_unused)); | |
4309 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
4310 | .in1(1'b1), | |
4311 | .in2(1'b1), | |
4312 | .out(spare3_nand3_8x_unused)); | |
4313 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
4314 | .out(spare3_inv_8x_unused)); | |
4315 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
4316 | .in01(1'b1), | |
4317 | .in10(1'b1), | |
4318 | .in11(1'b1), | |
4319 | .out(spare3_aoi22_4x_unused)); | |
4320 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
4321 | .out(spare3_buf_8x_unused)); | |
4322 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
4323 | .in01(1'b1), | |
4324 | .in10(1'b1), | |
4325 | .in11(1'b1), | |
4326 | .out(spare3_oai22_4x_unused)); | |
4327 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
4328 | .out(spare3_inv_16x_unused)); | |
4329 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
4330 | .in1(1'b1), | |
4331 | .out(spare3_nand2_16x_unused)); | |
4332 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
4333 | .in1(1'b0), | |
4334 | .in2(1'b0), | |
4335 | .out(spare3_nor3_4x_unused)); | |
4336 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
4337 | .in1(1'b1), | |
4338 | .out(spare3_nand2_8x_unused)); | |
4339 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
4340 | .out(spare3_buf_16x_unused)); | |
4341 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
4342 | .in1(1'b0), | |
4343 | .out(spare3_nor2_16x_unused)); | |
4344 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
4345 | .out(spare3_inv_32x_unused)); | |
4346 | ||
4347 | cl_sc1_msff_8x spare4_flop (.l1clk(l1clk), | |
4348 | .siclk(siclk), | |
4349 | .soclk(soclk), | |
4350 | .si(si_4), | |
4351 | .so(so_4), | |
4352 | .d(1'b0), | |
4353 | .q(spare4_flop_unused)); | |
4354 | assign si_4 = so_3; | |
4355 | ||
4356 | cl_u1_buf_32x spare4_buf_32x (.in(1'b1), | |
4357 | .out(spare4_buf_32x_unused)); | |
4358 | cl_u1_nand3_8x spare4_nand3_8x (.in0(1'b1), | |
4359 | .in1(1'b1), | |
4360 | .in2(1'b1), | |
4361 | .out(spare4_nand3_8x_unused)); | |
4362 | cl_u1_inv_8x spare4_inv_8x (.in(1'b1), | |
4363 | .out(spare4_inv_8x_unused)); | |
4364 | cl_u1_aoi22_4x spare4_aoi22_4x (.in00(1'b1), | |
4365 | .in01(1'b1), | |
4366 | .in10(1'b1), | |
4367 | .in11(1'b1), | |
4368 | .out(spare4_aoi22_4x_unused)); | |
4369 | cl_u1_buf_8x spare4_buf_8x (.in(1'b1), | |
4370 | .out(spare4_buf_8x_unused)); | |
4371 | cl_u1_oai22_4x spare4_oai22_4x (.in00(1'b1), | |
4372 | .in01(1'b1), | |
4373 | .in10(1'b1), | |
4374 | .in11(1'b1), | |
4375 | .out(spare4_oai22_4x_unused)); | |
4376 | cl_u1_inv_16x spare4_inv_16x (.in(1'b1), | |
4377 | .out(spare4_inv_16x_unused)); | |
4378 | cl_u1_nand2_16x spare4_nand2_16x (.in0(1'b1), | |
4379 | .in1(1'b1), | |
4380 | .out(spare4_nand2_16x_unused)); | |
4381 | cl_u1_nor3_4x spare4_nor3_4x (.in0(1'b0), | |
4382 | .in1(1'b0), | |
4383 | .in2(1'b0), | |
4384 | .out(spare4_nor3_4x_unused)); | |
4385 | cl_u1_nand2_8x spare4_nand2_8x (.in0(1'b1), | |
4386 | .in1(1'b1), | |
4387 | .out(spare4_nand2_8x_unused)); | |
4388 | cl_u1_buf_16x spare4_buf_16x (.in(1'b1), | |
4389 | .out(spare4_buf_16x_unused)); | |
4390 | cl_u1_nor2_16x spare4_nor2_16x (.in0(1'b0), | |
4391 | .in1(1'b0), | |
4392 | .out(spare4_nor2_16x_unused)); | |
4393 | cl_u1_inv_32x spare4_inv_32x (.in(1'b1), | |
4394 | .out(spare4_inv_32x_unused)); | |
4395 | ||
4396 | cl_sc1_msff_8x spare5_flop (.l1clk(l1clk), | |
4397 | .siclk(siclk), | |
4398 | .soclk(soclk), | |
4399 | .si(si_5), | |
4400 | .so(so_5), | |
4401 | .d(1'b0), | |
4402 | .q(spare5_flop_unused)); | |
4403 | assign si_5 = so_4; | |
4404 | ||
4405 | cl_u1_buf_32x spare5_buf_32x (.in(1'b1), | |
4406 | .out(spare5_buf_32x_unused)); | |
4407 | cl_u1_nand3_8x spare5_nand3_8x (.in0(1'b1), | |
4408 | .in1(1'b1), | |
4409 | .in2(1'b1), | |
4410 | .out(spare5_nand3_8x_unused)); | |
4411 | cl_u1_inv_8x spare5_inv_8x (.in(1'b1), | |
4412 | .out(spare5_inv_8x_unused)); | |
4413 | cl_u1_aoi22_4x spare5_aoi22_4x (.in00(1'b1), | |
4414 | .in01(1'b1), | |
4415 | .in10(1'b1), | |
4416 | .in11(1'b1), | |
4417 | .out(spare5_aoi22_4x_unused)); | |
4418 | cl_u1_buf_8x spare5_buf_8x (.in(1'b1), | |
4419 | .out(spare5_buf_8x_unused)); | |
4420 | cl_u1_oai22_4x spare5_oai22_4x (.in00(1'b1), | |
4421 | .in01(1'b1), | |
4422 | .in10(1'b1), | |
4423 | .in11(1'b1), | |
4424 | .out(spare5_oai22_4x_unused)); | |
4425 | cl_u1_inv_16x spare5_inv_16x (.in(1'b1), | |
4426 | .out(spare5_inv_16x_unused)); | |
4427 | cl_u1_nand2_16x spare5_nand2_16x (.in0(1'b1), | |
4428 | .in1(1'b1), | |
4429 | .out(spare5_nand2_16x_unused)); | |
4430 | cl_u1_nor3_4x spare5_nor3_4x (.in0(1'b0), | |
4431 | .in1(1'b0), | |
4432 | .in2(1'b0), | |
4433 | .out(spare5_nor3_4x_unused)); | |
4434 | cl_u1_nand2_8x spare5_nand2_8x (.in0(1'b1), | |
4435 | .in1(1'b1), | |
4436 | .out(spare5_nand2_8x_unused)); | |
4437 | cl_u1_buf_16x spare5_buf_16x (.in(1'b1), | |
4438 | .out(spare5_buf_16x_unused)); | |
4439 | cl_u1_nor2_16x spare5_nor2_16x (.in0(1'b0), | |
4440 | .in1(1'b0), | |
4441 | .out(spare5_nor2_16x_unused)); | |
4442 | cl_u1_inv_32x spare5_inv_32x (.in(1'b1), | |
4443 | .out(spare5_inv_32x_unused)); | |
4444 | ||
4445 | cl_sc1_msff_8x spare6_flop (.l1clk(l1clk), | |
4446 | .siclk(siclk), | |
4447 | .soclk(soclk), | |
4448 | .si(si_6), | |
4449 | .so(so_6), | |
4450 | .d(1'b0), | |
4451 | .q(spare6_flop_unused)); | |
4452 | assign si_6 = so_5; | |
4453 | ||
4454 | cl_u1_buf_32x spare6_buf_32x (.in(1'b1), | |
4455 | .out(spare6_buf_32x_unused)); | |
4456 | cl_u1_nand3_8x spare6_nand3_8x (.in0(1'b1), | |
4457 | .in1(1'b1), | |
4458 | .in2(1'b1), | |
4459 | .out(spare6_nand3_8x_unused)); | |
4460 | cl_u1_inv_8x spare6_inv_8x (.in(1'b1), | |
4461 | .out(spare6_inv_8x_unused)); | |
4462 | cl_u1_aoi22_4x spare6_aoi22_4x (.in00(1'b1), | |
4463 | .in01(1'b1), | |
4464 | .in10(1'b1), | |
4465 | .in11(1'b1), | |
4466 | .out(spare6_aoi22_4x_unused)); | |
4467 | cl_u1_buf_8x spare6_buf_8x (.in(1'b1), | |
4468 | .out(spare6_buf_8x_unused)); | |
4469 | cl_u1_oai22_4x spare6_oai22_4x (.in00(1'b1), | |
4470 | .in01(1'b1), | |
4471 | .in10(1'b1), | |
4472 | .in11(1'b1), | |
4473 | .out(spare6_oai22_4x_unused)); | |
4474 | cl_u1_inv_16x spare6_inv_16x (.in(1'b1), | |
4475 | .out(spare6_inv_16x_unused)); | |
4476 | cl_u1_nand2_16x spare6_nand2_16x (.in0(1'b1), | |
4477 | .in1(1'b1), | |
4478 | .out(spare6_nand2_16x_unused)); | |
4479 | cl_u1_nor3_4x spare6_nor3_4x (.in0(1'b0), | |
4480 | .in1(1'b0), | |
4481 | .in2(1'b0), | |
4482 | .out(spare6_nor3_4x_unused)); | |
4483 | cl_u1_nand2_8x spare6_nand2_8x (.in0(1'b1), | |
4484 | .in1(1'b1), | |
4485 | .out(spare6_nand2_8x_unused)); | |
4486 | cl_u1_buf_16x spare6_buf_16x (.in(1'b1), | |
4487 | .out(spare6_buf_16x_unused)); | |
4488 | cl_u1_nor2_16x spare6_nor2_16x (.in0(1'b0), | |
4489 | .in1(1'b0), | |
4490 | .out(spare6_nor2_16x_unused)); | |
4491 | cl_u1_inv_32x spare6_inv_32x (.in(1'b1), | |
4492 | .out(spare6_inv_32x_unused)); | |
4493 | assign scan_out = so_6; | |
4494 | ||
4495 | ||
4496 | ||
4497 | endmodule | |
4498 |