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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_seg_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_seg_dp ( | |
36 | data_in, | |
37 | ecc_out); | |
38 | wire [66:0] d; | |
39 | wire [35:0] check0_bus; | |
40 | wire check0_3; | |
41 | wire check0_2; | |
42 | wire check0_1; | |
43 | wire check0_0; | |
44 | wire c0; | |
45 | wire [35:0] check1_bus; | |
46 | wire check1_3; | |
47 | wire check1_2; | |
48 | wire check1_1; | |
49 | wire check1_0; | |
50 | wire c1; | |
51 | wire [34:0] check2_bus; | |
52 | wire check2_3; | |
53 | wire check2_2; | |
54 | wire check2_1; | |
55 | wire check2_0; | |
56 | wire c2; | |
57 | wire [33:0] check3_bus; | |
58 | wire check3_3; | |
59 | wire check3_2; | |
60 | wire check3_1; | |
61 | wire check3_0; | |
62 | wire c3; | |
63 | wire [30:0] check4_bus; | |
64 | wire c4; | |
65 | wire [30:0] check5_bus; | |
66 | wire c5; | |
67 | wire [9:0] check6_bus; | |
68 | wire c6; | |
69 | wire [35:0] check7_bus; | |
70 | wire check7_3; | |
71 | wire check7_2; | |
72 | wire check7_1; | |
73 | wire check7_0; | |
74 | wire c7; | |
75 | ||
76 | ||
77 | ||
78 | input [66:0] data_in; // Used for generation and checking | |
79 | ||
80 | output [7:0] ecc_out; // Used for generation and checking | |
81 | ||
82 | ||
83 | ||
84 | ////////////////////////////////////////////////////////////////////////////// | |
85 | ||
86 | // Position Binary | |
87 | // 1 0000001 C0 | |
88 | // 2 0000010 C1 | |
89 | // 3 0000011 D0 | |
90 | // | |
91 | // 4 0000100 C2 | |
92 | // 5 0000101 D1 | |
93 | // 6 0000110 D2 | |
94 | // 7 0000111 D3 | |
95 | // | |
96 | // 8 0001000 C3 | |
97 | // 9 0001001 D4 | |
98 | // 10 0001010 D5 | |
99 | // 11 0001011 D6 | |
100 | // 12 0001100 D7 | |
101 | // ... ... | |
102 | // 15 0001111 D10 | |
103 | // | |
104 | // 16 0010000 C4 | |
105 | // 17 0010001 D11 | |
106 | // ... ... | |
107 | // 20 0010100 D14 | |
108 | // ... ... | |
109 | // 24 0011000 D18 | |
110 | // ... ... | |
111 | // 28 0011100 D22 | |
112 | // ... ... | |
113 | // 31 0011111 D25 | |
114 | // | |
115 | // 32 0100000 C5 | |
116 | // 33 0100001 D26 | |
117 | // ... ... | |
118 | // 36 0100100 D29 | |
119 | // ... ... | |
120 | // 40 0101000 D33 | |
121 | // ... ... | |
122 | // 44 0101100 D37 | |
123 | // ... ... | |
124 | // 48 0110000 D41 | |
125 | // ... ... | |
126 | // 52 0110100 D45 | |
127 | // ... ... | |
128 | // 56 0111000 D49 | |
129 | // ... ... | |
130 | // 60 0111100 D53 | |
131 | // ... ... | |
132 | // 63 0111111 D56 | |
133 | // | |
134 | // 64 1000000 C6 | |
135 | // 65 1000001 D57 | |
136 | // ... ... | |
137 | // 68 1000100 D60 | |
138 | // ... ... | |
139 | // 72 1001000 D64 | |
140 | // 73 1001001 D65 | |
141 | // 74 1001010 D66 | |
142 | // | |
143 | // 75 1001011 C7 | |
144 | ||
145 | assign d[66:0] = | |
146 | data_in[66:0]; | |
147 | ||
148 | ||
149 | ||
150 | // All odd positions (LSB of position set) | |
151 | assign check0_bus[35:0] = | |
152 | {d[65], d[63], d[61], d[59], d[57], | |
153 | d[56], d[54], d[52], d[50], d[48], d[46], d[44], d[42], | |
154 | d[40], d[38], d[36], d[34], d[32], d[30], d[28], d[26], | |
155 | d[25], d[23], d[21], d[19], d[17], d[15], d[13], d[11], | |
156 | d[10], d[8], d[6], d[4], | |
157 | d[3], d[1], | |
158 | d[0]}; | |
159 | ||
160 | mmu_seg_dp_prty_macro__width_8 check0_3_pty ( | |
161 | .din (check0_bus [31:24] ), | |
162 | .dout (check0_3 ) | |
163 | ); | |
164 | ||
165 | mmu_seg_dp_prty_macro__width_8 check0_2_pty ( | |
166 | .din (check0_bus [23:16] ), | |
167 | .dout (check0_2 ) | |
168 | ); | |
169 | ||
170 | mmu_seg_dp_prty_macro__width_8 check0_1_pty ( | |
171 | .din (check0_bus [15:8] ), | |
172 | .dout (check0_1 ) | |
173 | ); | |
174 | ||
175 | mmu_seg_dp_prty_macro__width_8 check0_0_pty ( | |
176 | .din (check0_bus [7:0] ), | |
177 | .dout (check0_0 ) | |
178 | ); | |
179 | ||
180 | mmu_seg_dp_prty_macro__width_8 check0_pty ( | |
181 | .din ({check0_bus [35:32], | |
182 | check0_3 , | |
183 | check0_2 , | |
184 | check0_1 , | |
185 | check0_0 }), | |
186 | .dout (c0 ) | |
187 | ); | |
188 | ||
189 | ||
190 | ||
191 | // All positions with secondmost LSB set | |
192 | assign check1_bus[35:0] = | |
193 | {d[66 ], d[63:62], d[59:58], | |
194 | d[56:55], d[52:51], d[48:47], d[44:43], | |
195 | d[40:39], d[36:35], d[32:31], d[28:27], | |
196 | d[25:24], d[21:20], d[17:16], d[13:12], | |
197 | d[10:9], d[6:5], | |
198 | d[3:2], | |
199 | d[0]}; | |
200 | ||
201 | mmu_seg_dp_prty_macro__width_8 check1_3_pty ( | |
202 | .din (check1_bus [31:24] ), | |
203 | .dout (check1_3 ) | |
204 | ); | |
205 | ||
206 | mmu_seg_dp_prty_macro__width_8 check1_2_pty ( | |
207 | .din (check1_bus [23:16] ), | |
208 | .dout (check1_2 ) | |
209 | ); | |
210 | ||
211 | mmu_seg_dp_prty_macro__width_8 check1_1_pty ( | |
212 | .din (check1_bus [15:8] ), | |
213 | .dout (check1_1 ) | |
214 | ); | |
215 | ||
216 | mmu_seg_dp_prty_macro__width_8 check1_0_pty ( | |
217 | .din (check1_bus [7:0] ), | |
218 | .dout (check1_0 ) | |
219 | ); | |
220 | ||
221 | mmu_seg_dp_prty_macro__width_8 check1_pty ( | |
222 | .din ({check1_bus [35:32], | |
223 | check1_3 , | |
224 | check1_2 , | |
225 | check1_1 , | |
226 | check1_0 }), | |
227 | .dout (c1 ) | |
228 | ); | |
229 | ||
230 | ||
231 | ||
232 | // All positions with thirdmost LSB set | |
233 | assign check2_bus[34:0] = | |
234 | {d[63:60], | |
235 | d[56:53], d[48:45], d[40:37], d[32:29], | |
236 | d[25:22], d[17:14], | |
237 | d[10:7], | |
238 | d[3:1]}; | |
239 | ||
240 | mmu_seg_dp_prty_macro__width_8 check2_3_pty ( | |
241 | .din (check2_bus [31:24] ), | |
242 | .dout (check2_3 ) | |
243 | ); | |
244 | ||
245 | mmu_seg_dp_prty_macro__width_8 check2_2_pty ( | |
246 | .din (check2_bus [23:16] ), | |
247 | .dout (check2_2 ) | |
248 | ); | |
249 | ||
250 | mmu_seg_dp_prty_macro__width_8 check2_1_pty ( | |
251 | .din (check2_bus [15:8] ), | |
252 | .dout (check2_1 ) | |
253 | ); | |
254 | ||
255 | mmu_seg_dp_prty_macro__width_8 check2_0_pty ( | |
256 | .din (check2_bus [7:0] ), | |
257 | .dout (check2_0 ) | |
258 | ); | |
259 | ||
260 | mmu_seg_dp_prty_macro__width_8 check2_pty ( | |
261 | .din ({{1 {1'b0}} , | |
262 | check2_bus [34:32], | |
263 | check2_3 , | |
264 | check2_2 , | |
265 | check2_1 , | |
266 | check2_0 }), | |
267 | .dout (c2 ) | |
268 | ); | |
269 | ||
270 | ||
271 | ||
272 | // All positions with fourthmost LSB set | |
273 | assign check3_bus[33:0] = | |
274 | {d[66:64], | |
275 | d[56:49], d[40:33], | |
276 | d[25:18], | |
277 | d[10:4]}; | |
278 | ||
279 | mmu_seg_dp_prty_macro__width_8 check3_3_pty ( | |
280 | .din (check3_bus [31:24] ), | |
281 | .dout (check3_3 ) | |
282 | ); | |
283 | ||
284 | mmu_seg_dp_prty_macro__width_8 check3_2_pty ( | |
285 | .din (check3_bus [23:16] ), | |
286 | .dout (check3_2 ) | |
287 | ); | |
288 | ||
289 | mmu_seg_dp_prty_macro__width_8 check3_1_pty ( | |
290 | .din (check3_bus [15:8] ), | |
291 | .dout (check3_1 ) | |
292 | ); | |
293 | ||
294 | mmu_seg_dp_prty_macro__width_8 check3_0_pty ( | |
295 | .din (check3_bus [7:0] ), | |
296 | .dout (check3_0 ) | |
297 | ); | |
298 | ||
299 | mmu_seg_dp_prty_macro__width_8 check3_pty ( | |
300 | .din ({{2 {1'b0}} , | |
301 | check3_bus [33:32], | |
302 | check3_3 , | |
303 | check3_2 , | |
304 | check3_1 , | |
305 | check3_0 }), | |
306 | .dout (c3 ) | |
307 | ); | |
308 | ||
309 | ||
310 | // All positions with fifthmost LSB set | |
311 | assign check4_bus[30:0] = | |
312 | {d[56:41], | |
313 | d[25:11]}; | |
314 | ||
315 | mmu_seg_dp_prty_macro__width_32 check4_pty ( | |
316 | .din ({{1 {1'b0}} , | |
317 | check4_bus [30:0]}), | |
318 | .dout (c4 ) | |
319 | ); | |
320 | ||
321 | ||
322 | ||
323 | // All positions with sixthmost LSB set | |
324 | assign check5_bus[30:0] = | |
325 | {d[56:26]}; | |
326 | ||
327 | mmu_seg_dp_prty_macro__width_32 check5_pty ( | |
328 | .din ({{1 {1'b0}} , | |
329 | check5_bus [30:0]}), | |
330 | .dout (c5 ) | |
331 | ); | |
332 | ||
333 | ||
334 | ||
335 | // All positions with seventhmost LSB set | |
336 | assign check6_bus[9:0] = | |
337 | {d[66:57]}; | |
338 | ||
339 | mmu_seg_dp_prty_macro__width_16 check6_pty ( | |
340 | .din ({{6 {1'b0}} , | |
341 | check6_bus [9:0]}), | |
342 | .dout (c6 ) | |
343 | ); | |
344 | ||
345 | ||
346 | ||
347 | // Parity of the whole word (including check bits) | |
348 | //assign check7_bus[73:00] = | |
349 | // {d[66:00], c0, c1, c2, c3, c4, c5, c6}; | |
350 | // But in generation this simplifies to | |
351 | // (all d bits with even parity binary positions) | |
352 | ||
353 | assign check7_bus[35:0] = | |
354 | // 72 71 68 66 65 63 60 58 57 | |
355 | {d[64], d[63], d[60], d[58], d[57], d[56], d[53], d[51], d[50], | |
356 | // 54 53 51 48 46 45 43 40 39 | |
357 | d[47], d[46], d[44], d[41], d[39], d[38], d[36], d[33], d[32], | |
358 | // 36 34 33 30 29 27 24 23 20 | |
359 | d[29], d[27], d[26], d[24], d[23], d[21], d[18], d[17], d[14], | |
360 | // 18 17 15 12 10 9 6 5 3 | |
361 | d[12], d[11], d[10], d[7], d[5], d[4], d[2], d[1], d[0]}; | |
362 | ||
363 | mmu_seg_dp_prty_macro__width_8 check7_3_pty ( | |
364 | .din (check7_bus [31:24] ), | |
365 | .dout (check7_3 ) | |
366 | ); | |
367 | ||
368 | mmu_seg_dp_prty_macro__width_8 check7_2_pty ( | |
369 | .din (check7_bus [23:16] ), | |
370 | .dout (check7_2 ) | |
371 | ); | |
372 | ||
373 | mmu_seg_dp_prty_macro__width_8 check7_1_pty ( | |
374 | .din (check7_bus [15:8] ), | |
375 | .dout (check7_1 ) | |
376 | ); | |
377 | ||
378 | mmu_seg_dp_prty_macro__width_8 check7_0_pty ( | |
379 | .din (check7_bus [7:0] ), | |
380 | .dout (check7_0 ) | |
381 | ); | |
382 | ||
383 | mmu_seg_dp_prty_macro__width_8 check7_pty ( | |
384 | .din ({check7_bus [35:32], | |
385 | check7_3 , | |
386 | check7_2 , | |
387 | check7_1 , | |
388 | check7_0 }), | |
389 | .dout (c7 ) | |
390 | ); | |
391 | ||
392 | assign ecc_out[7:0] = | |
393 | {c7, c6, c5, c4, c3, c2, c1, c0}; | |
394 | ||
395 | ||
396 | ||
397 | ||
398 | supply0 vss; // <- port for ground | |
399 | supply1 vdd; // <- port for power | |
400 | ||
401 | endmodule | |
402 | ||
403 | ||
404 | ||
405 | // | |
406 | // parity macro (even parity) | |
407 | // | |
408 | // | |
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | module mmu_seg_dp_prty_macro__width_8 ( | |
415 | din, | |
416 | dout); | |
417 | input [7:0] din; | |
418 | output dout; | |
419 | ||
420 | ||
421 | ||
422 | ||
423 | ||
424 | ||
425 | ||
426 | prty #(8) m0_0 ( | |
427 | .in(din[7:0]), | |
428 | .out(dout) | |
429 | ); | |
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 | endmodule | |
441 | ||
442 | ||
443 | ||
444 | ||
445 | ||
446 | // | |
447 | // parity macro (even parity) | |
448 | // | |
449 | // | |
450 | ||
451 | ||
452 | ||
453 | ||
454 | ||
455 | module mmu_seg_dp_prty_macro__width_32 ( | |
456 | din, | |
457 | dout); | |
458 | input [31:0] din; | |
459 | output dout; | |
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | prty #(32) m0_0 ( | |
468 | .in(din[31:0]), | |
469 | .out(dout) | |
470 | ); | |
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | endmodule | |
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | // | |
488 | // parity macro (even parity) | |
489 | // | |
490 | // | |
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | module mmu_seg_dp_prty_macro__width_16 ( | |
497 | din, | |
498 | dout); | |
499 | input [15:0] din; | |
500 | output dout; | |
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | prty #(16) m0_0 ( | |
509 | .in(din[15:0]), | |
510 | .out(dout) | |
511 | ); | |
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 | ||
522 | endmodule | |
523 | ||
524 | ||
525 | ||
526 |