projects / OpenSPARC-T2-DV / blame
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1 | // ========== Copyright Header Begin ========================================== |
| 2 | // | |
| 3 | // OpenSPARC T2 Processor File: mmu_tmc_ctl.v | |
| 4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
| 5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
| 6 | // | |
| 7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
| 8 | // | |
| 9 | // This program is free software; you can redistribute it and/or modify | |
| 10 | // it under the terms of the GNU General Public License as published by | |
| 11 | // the Free Software Foundation; version 2 of the License. | |
| 12 | // | |
| 13 | // This program is distributed in the hope that it will be useful, | |
| 14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
| 15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
| 16 | // GNU General Public License for more details. | |
| 17 | // | |
| 18 | // You should have received a copy of the GNU General Public License | |
| 19 | // along with this program; if not, write to the Free Software | |
| 20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
| 21 | // | |
| 22 | // For the avoidance of doubt, and except that if any non-GPL license | |
| 23 | // choice is available it will apply instead, Sun elects to use only | |
| 24 | // the General Public License version 2 (GPLv2) at this time for any | |
| 25 | // software where a choice of GPL license versions is made | |
| 26 | // available with the language indicating that GPLv2 or any later version | |
| 27 | // may be used, or where a choice of which version of the GPL is applied is | |
| 28 | // otherwise unspecified. | |
| 29 | // | |
| 30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
| 31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
| 32 | // have any questions. | |
| 33 | // | |
| 34 | // ========== Copyright Header End ============================================ | |
| 35 | module mmu_tmc_ctl ( | |
| 36 | l2clk, | |
| 37 | scan_in, | |
| 38 | tcu_pce_ov, | |
| 39 | spc_aclk, | |
| 40 | spc_bclk, | |
| 41 | tcu_scan_en, | |
| 42 | htc_data_rcvd_hw1, | |
| 43 | htc_tlb_miss_m, | |
| 44 | htc_tsb_done_hw2, | |
| 45 | htc_vld_tsbptr_m2, | |
| 46 | htc_thr_valid_m1, | |
| 47 | htc_thr_valid_m0, | |
| 48 | htc_hwtw_burst, | |
| 49 | htc_cindex_bit0, | |
| 50 | htc_cindex_bit1, | |
| 51 | trs_eperr_st, | |
| 52 | trs_eccerr_st, | |
| 53 | tsm_tsb_miss_hw2, | |
| 54 | tsm_rqv, | |
| 55 | tsm_waitfortte, | |
| 56 | scan_out); | |
| 57 | wire pce_ov; | |
| 58 | wire stop; | |
| 59 | wire se; | |
| 60 | wire siclk; | |
| 61 | wire soclk; | |
| 62 | wire l1clk; | |
| 63 | wire tsm0_scanin; | |
| 64 | wire tsm0_scanout; | |
| 65 | wire tsm1_scanin; | |
| 66 | wire tsm1_scanout; | |
| 67 | wire tsm2_scanin; | |
| 68 | wire tsm2_scanout; | |
| 69 | wire tsm3_scanin; | |
| 70 | wire tsm3_scanout; | |
| 71 | wire tsm4_scanin; | |
| 72 | wire tsm4_scanout; | |
| 73 | wire tsm5_scanin; | |
| 74 | wire tsm5_scanout; | |
| 75 | wire tsm6_scanin; | |
| 76 | wire tsm6_scanout; | |
| 77 | wire tsm7_scanin; | |
| 78 | wire tsm7_scanout; | |
| 79 | wire spares_scanin; | |
| 80 | wire spares_scanout; | |
| 81 | ||
| 82 | ||
| 83 | input l2clk; | |
| 84 | input scan_in; | |
| 85 | input tcu_pce_ov; // scan signals | |
| 86 | input spc_aclk; | |
| 87 | input spc_bclk; | |
| 88 | input tcu_scan_en; | |
| 89 | ||
| 90 | input [7:0] htc_data_rcvd_hw1; | |
| 91 | input [7:0] htc_tlb_miss_m; | |
| 92 | input [7:0] htc_tsb_done_hw2; | |
| 93 | input [7:0] htc_vld_tsbptr_m2; | |
| 94 | input [7:0] htc_thr_valid_m1; | |
| 95 | input [7:0] htc_thr_valid_m0; | |
| 96 | input [7:0] htc_hwtw_burst; | |
| 97 | ||
| 98 | input [7:0] htc_cindex_bit0; | |
| 99 | input [7:0] htc_cindex_bit1; | |
| 100 | ||
| 101 | ||
| 102 | input [7:0] trs_eperr_st; | |
| 103 | ||
| 104 | input [7:0] trs_eccerr_st; | |
| 105 | ||
| 106 | output [7:0] tsm_tsb_miss_hw2; | |
| 107 | output [7:0] tsm_rqv; | |
| 108 | ||
| 109 | output [7:0] tsm_waitfortte; | |
| 110 | ||
| 111 | output scan_out; | |
| 112 | ||
| 113 | assign pce_ov = tcu_pce_ov; | |
| 114 | assign stop = 1'b0; | |
| 115 | assign se = tcu_scan_en; | |
| 116 | ||
| 117 | assign siclk = spc_aclk; | |
| 118 | assign soclk = spc_bclk; | |
| 119 | ||
| 120 | ||
| 121 | /////////////////////////////////////////////////// | |
| 122 | // clock header | |
| 123 | /////////////////////////////////////////////////// | |
| 124 | mmu_tmc_ctl_l1clkhdr_ctl_macro clkgen ( | |
| 125 | .l2clk(l2clk), | |
| 126 | .l1en (1'b1), | |
| 127 | .l1clk(l1clk), | |
| 128 | .pce_ov(pce_ov), | |
| 129 | .stop(stop), | |
| 130 | .se(se) | |
| 131 | ); | |
| 132 | ||
| 133 | ||
| 134 | /* mmu_tsm_ctl AUTO_TEMPLATE | |
| 135 | ( | |
| 136 | .tlb_miss_m(htc_tlb_miss_m[@]), | |
| 137 | .cindex_bit0(htc_cindex_bit0[@]), | |
| 138 | .cindex_bit1(htc_cindex_bit1[@]), | |
| 139 | ||
| 140 | .data_rcvd_hw1(htc_data_rcvd_hw1[@]), | |
| 141 | .thr_valid_m1(htc_thr_valid_m1[@]), | |
| 142 | .thr_valid_m0(htc_thr_valid_m0[@]), | |
| 143 | .hwtw_burst(htc_hwtw_burst[@]), | |
| 144 | .tsb_done_hw2(htc_tsb_done_hw2[@]), | |
| 145 | .tsb_vld_tsbptr_m2(htc_vld_tsbptr_m2[@]), | |
| 146 | ||
| 147 | .tsm_tsb_miss_hw2(tsm_tsb_miss_hw2[@]), | |
| 148 | .tsm_rqv(tsm_rqv[@]), | |
| 149 | .tsm_waitfortte(tsm_waitfortte[@]), | |
| 150 | .trs_eperr_st(trs_eperr_st[@]), | |
| 151 | .trs_eccerr_st(trs_eccerr_st[@])); | |
| 152 | */ | |
| 153 | ||
| 154 | mmu_tsm_ctl tsm0 (/*AUTOINST*/ | |
| 155 | // Outputs | |
| 156 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[0]), // Templated | |
| 157 | .tsm_rqv (tsm_rqv[0]), // Templated | |
| 158 | .tsm_waitfortte (tsm_waitfortte[0]), // Templated | |
| 159 | // Inputs | |
| 160 | .scan_in(tsm0_scanin), | |
| 161 | .scan_out(tsm0_scanout), | |
| 162 | .l1clk (l1clk), | |
| 163 | .data_rcvd_hw1 (htc_data_rcvd_hw1[0]), // Templated | |
| 164 | .thr_valid_m1 (htc_thr_valid_m1[0]), // Templated | |
| 165 | .thr_valid_m0 (htc_thr_valid_m0[0]), // Templated | |
| 166 | .hwtw_burst (htc_hwtw_burst[0]), // Templated | |
| 167 | .tlb_miss_m (htc_tlb_miss_m[0]), // Templated | |
| 168 | .cindex_bit0 (htc_cindex_bit0[0]), // Templated | |
| 169 | .cindex_bit1 (htc_cindex_bit1[0]), // Templated | |
| 170 | .tsb_done_hw2 (htc_tsb_done_hw2[0]), // Templated | |
| 171 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[0]), // Templated | |
| 172 | .trs_eperr_st (trs_eperr_st[0]), // Templated | |
| 173 | .trs_eccerr_st (trs_eccerr_st[0]), | |
| 174 | .spc_aclk(spc_aclk), | |
| 175 | .spc_bclk(spc_bclk)); // Templated | |
| 176 | ||
| 177 | mmu_tsm_ctl tsm1 (/*AUTOINST*/ | |
| 178 | // Outputs | |
| 179 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[1]), // Templated | |
| 180 | .tsm_rqv (tsm_rqv[1]), // Templated | |
| 181 | .tsm_waitfortte (tsm_waitfortte[1]), // Templated | |
| 182 | // Inputs | |
| 183 | .scan_in(tsm1_scanin), | |
| 184 | .scan_out(tsm1_scanout), | |
| 185 | .l1clk (l1clk), | |
| 186 | .data_rcvd_hw1 (htc_data_rcvd_hw1[1]), // Templated | |
| 187 | .thr_valid_m1 (htc_thr_valid_m1[1]), // Templated | |
| 188 | .thr_valid_m0 (htc_thr_valid_m0[1]), // Templated | |
| 189 | .hwtw_burst (htc_hwtw_burst[1]), // Templated | |
| 190 | .tlb_miss_m (htc_tlb_miss_m[1]), // Templated | |
| 191 | .cindex_bit0 (htc_cindex_bit0[1]), // Templated | |
| 192 | .cindex_bit1 (htc_cindex_bit1[1]), // Templated | |
| 193 | .tsb_done_hw2 (htc_tsb_done_hw2[1]), // Templated | |
| 194 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[1]), // Templated | |
| 195 | .trs_eperr_st (trs_eperr_st[1]), // Templated | |
| 196 | .trs_eccerr_st (trs_eccerr_st[1]), | |
| 197 | .spc_aclk(spc_aclk), | |
| 198 | .spc_bclk(spc_bclk)); // Templated | |
| 199 | ||
| 200 | mmu_tsm_ctl tsm2 (/*AUTOINST*/ | |
| 201 | // Outputs | |
| 202 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[2]), // Templated | |
| 203 | .tsm_rqv (tsm_rqv[2]), // Templated | |
| 204 | .tsm_waitfortte (tsm_waitfortte[2]), // Templated | |
| 205 | // Inputs | |
| 206 | .scan_in(tsm2_scanin), | |
| 207 | .scan_out(tsm2_scanout), | |
| 208 | .l1clk (l1clk), | |
| 209 | .data_rcvd_hw1 (htc_data_rcvd_hw1[2]), // Templated | |
| 210 | .thr_valid_m1 (htc_thr_valid_m1[2]), // Templated | |
| 211 | .thr_valid_m0 (htc_thr_valid_m0[2]), // Templated | |
| 212 | .hwtw_burst (htc_hwtw_burst[2]), // Templated | |
| 213 | .tlb_miss_m (htc_tlb_miss_m[2]), // Templated | |
| 214 | .cindex_bit0 (htc_cindex_bit0[2]), // Templated | |
| 215 | .cindex_bit1 (htc_cindex_bit1[2]), // Templated | |
| 216 | .tsb_done_hw2 (htc_tsb_done_hw2[2]), // Templated | |
| 217 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[2]), // Templated | |
| 218 | .trs_eperr_st (trs_eperr_st[2]), // Templated | |
| 219 | .trs_eccerr_st (trs_eccerr_st[2]), | |
| 220 | .spc_aclk(spc_aclk), | |
| 221 | .spc_bclk(spc_bclk)); // Templated | |
| 222 | ||
| 223 | mmu_tsm_ctl tsm3 (/*AUTOINST*/ | |
| 224 | // Outputs | |
| 225 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[3]), // Templated | |
| 226 | .tsm_rqv (tsm_rqv[3]), // Templated | |
| 227 | .tsm_waitfortte (tsm_waitfortte[3]), // Templated | |
| 228 | // Inputs | |
| 229 | .scan_in(tsm3_scanin), | |
| 230 | .scan_out(tsm3_scanout), | |
| 231 | .l1clk (l1clk), | |
| 232 | .data_rcvd_hw1 (htc_data_rcvd_hw1[3]), // Templated | |
| 233 | .thr_valid_m1 (htc_thr_valid_m1[3]), // Templated | |
| 234 | .thr_valid_m0 (htc_thr_valid_m0[3]), // Templated | |
| 235 | .hwtw_burst (htc_hwtw_burst[3]), // Templated | |
| 236 | .tlb_miss_m (htc_tlb_miss_m[3]), // Templated | |
| 237 | .cindex_bit0 (htc_cindex_bit0[3]), // Templated | |
| 238 | .cindex_bit1 (htc_cindex_bit1[3]), // Templated | |
| 239 | .tsb_done_hw2 (htc_tsb_done_hw2[3]), // Templated | |
| 240 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[3]), // Templated | |
| 241 | .trs_eperr_st (trs_eperr_st[3]), // Templated | |
| 242 | .trs_eccerr_st (trs_eccerr_st[3]), | |
| 243 | .spc_aclk(spc_aclk), | |
| 244 | .spc_bclk(spc_bclk)); // Templated | |
| 245 | ||
| 246 | mmu_tsm_ctl tsm4 (/*AUTOINST*/ | |
| 247 | // Outputs | |
| 248 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[4]), // Templated | |
| 249 | .tsm_rqv (tsm_rqv[4]), // Templated | |
| 250 | .tsm_waitfortte (tsm_waitfortte[4]), // Templated | |
| 251 | // Inputs | |
| 252 | .scan_in(tsm4_scanin), | |
| 253 | .scan_out(tsm4_scanout), | |
| 254 | .l1clk (l1clk), | |
| 255 | .data_rcvd_hw1 (htc_data_rcvd_hw1[4]), // Templated | |
| 256 | .thr_valid_m1 (htc_thr_valid_m1[4]), // Templated | |
| 257 | .thr_valid_m0 (htc_thr_valid_m0[4]), // Templated | |
| 258 | .hwtw_burst (htc_hwtw_burst[4]), // Templated | |
| 259 | .tlb_miss_m (htc_tlb_miss_m[4]), // Templated | |
| 260 | .cindex_bit0 (htc_cindex_bit0[4]), // Templated | |
| 261 | .cindex_bit1 (htc_cindex_bit1[4]), // Templated | |
| 262 | .tsb_done_hw2 (htc_tsb_done_hw2[4]), // Templated | |
| 263 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[4]), // Templated | |
| 264 | ||
| 265 | .trs_eperr_st (trs_eperr_st[4]), // Templated | |
| 266 | .trs_eccerr_st (trs_eccerr_st[4]), | |
| 267 | .spc_aclk(spc_aclk), | |
| 268 | .spc_bclk(spc_bclk)); // Templated | |
| 269 | ||
| 270 | mmu_tsm_ctl tsm5 (/*AUTOINST*/ | |
| 271 | // Outputs | |
| 272 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[5]), // Templated | |
| 273 | .tsm_rqv (tsm_rqv[5]), // Templated | |
| 274 | .tsm_waitfortte (tsm_waitfortte[5]), // Templated | |
| 275 | // Inputs | |
| 276 | .scan_in(tsm5_scanin), | |
| 277 | .scan_out(tsm5_scanout), | |
| 278 | .l1clk (l1clk), | |
| 279 | .data_rcvd_hw1 (htc_data_rcvd_hw1[5]), // Templated | |
| 280 | .thr_valid_m1 (htc_thr_valid_m1[5]), // Templated | |
| 281 | .thr_valid_m0 (htc_thr_valid_m0[5]), // Templated | |
| 282 | .hwtw_burst (htc_hwtw_burst[5]), // Templated | |
| 283 | .tlb_miss_m (htc_tlb_miss_m[5]), // Templated | |
| 284 | .cindex_bit0 (htc_cindex_bit0[5]), // Templated | |
| 285 | .cindex_bit1 (htc_cindex_bit1[5]), // Templated | |
| 286 | .tsb_done_hw2 (htc_tsb_done_hw2[5]), // Templated | |
| 287 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[5]), // Templated | |
| 288 | ||
| 289 | .trs_eperr_st (trs_eperr_st[5]), // Templated | |
| 290 | .trs_eccerr_st (trs_eccerr_st[5]), | |
| 291 | .spc_aclk(spc_aclk), | |
| 292 | .spc_bclk(spc_bclk)); // Templated | |
| 293 | ||
| 294 | mmu_tsm_ctl tsm6 (/*AUTOINST*/ | |
| 295 | // Outputs | |
| 296 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[6]), // Templated | |
| 297 | .tsm_rqv (tsm_rqv[6]), // Templated | |
| 298 | .tsm_waitfortte (tsm_waitfortte[6]), // Templated | |
| 299 | // Inputs | |
| 300 | .scan_in(tsm6_scanin), | |
| 301 | .scan_out(tsm6_scanout), | |
| 302 | .l1clk (l1clk), | |
| 303 | .data_rcvd_hw1 (htc_data_rcvd_hw1[6]), // Templated | |
| 304 | .thr_valid_m1 (htc_thr_valid_m1[6]), // Templated | |
| 305 | .thr_valid_m0 (htc_thr_valid_m0[6]), // Templated | |
| 306 | .hwtw_burst (htc_hwtw_burst[6]), // Templated | |
| 307 | .tlb_miss_m (htc_tlb_miss_m[6]), // Templated | |
| 308 | .cindex_bit0 (htc_cindex_bit0[6]), // Templated | |
| 309 | .cindex_bit1 (htc_cindex_bit1[6]), // Templated | |
| 310 | .tsb_done_hw2 (htc_tsb_done_hw2[6]), // Templated | |
| 311 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[6]), // Templated | |
| 312 | .trs_eperr_st (trs_eperr_st[6]), // Templated | |
| 313 | .trs_eccerr_st (trs_eccerr_st[6]), | |
| 314 | .spc_aclk(spc_aclk), | |
| 315 | .spc_bclk(spc_bclk)); // Templated | |
| 316 | ||
| 317 | mmu_tsm_ctl tsm7 (/*AUTOINST*/ | |
| 318 | // Outputs | |
| 319 | .tsm_tsb_miss_hw2 (tsm_tsb_miss_hw2[7]), // Templated | |
| 320 | .tsm_rqv (tsm_rqv[7]), // Templated | |
| 321 | .tsm_waitfortte (tsm_waitfortte[7]), // Templated | |
| 322 | // Inputs | |
| 323 | .scan_in(tsm7_scanin), | |
| 324 | .scan_out(tsm7_scanout), | |
| 325 | .l1clk (l1clk), | |
| 326 | .data_rcvd_hw1 (htc_data_rcvd_hw1[7]), // Templated | |
| 327 | .thr_valid_m1 (htc_thr_valid_m1[7]), // Templated | |
| 328 | .thr_valid_m0 (htc_thr_valid_m0[7]), // Templated | |
| 329 | .hwtw_burst (htc_hwtw_burst[7]), // Templated | |
| 330 | .tlb_miss_m (htc_tlb_miss_m[7]), // Templated | |
| 331 | .cindex_bit0 (htc_cindex_bit0[7]), // Templated | |
| 332 | .cindex_bit1 (htc_cindex_bit1[7]), // Templated | |
| 333 | .tsb_done_hw2 (htc_tsb_done_hw2[7]), // Templated | |
| 334 | .vld_tsbptr_m2 (htc_vld_tsbptr_m2[7]), // Templated | |
| 335 | .trs_eperr_st (trs_eperr_st[7]), // Templated | |
| 336 | .trs_eccerr_st (trs_eccerr_st[7]), | |
| 337 | .spc_aclk(spc_aclk), | |
| 338 | .spc_bclk(spc_bclk)); // Templated | |
| 339 | ||
| 340 | //////////////////////////////////////////////////////// | |
| 341 | // SPARE CELLS | |
| 342 | //////////////////////////////////////////////////////// | |
| 343 | mmu_tmc_ctl_spare_ctl_macro__num_3 spares ( | |
| 344 | .scan_in(spares_scanin), | |
| 345 | .scan_out(spares_scanout), | |
| 346 | .l1clk (l1clk), | |
| 347 | .siclk(siclk), | |
| 348 | .soclk(soclk) | |
| 349 | ); | |
| 350 | //////////////////////////////////////////////////////// | |
| 351 | ||
| 352 | // fixscan start: | |
| 353 | assign tsm0_scanin = scan_in ; | |
| 354 | assign tsm1_scanin = tsm0_scanout ; | |
| 355 | assign tsm2_scanin = tsm1_scanout ; | |
| 356 | assign tsm3_scanin = tsm2_scanout ; | |
| 357 | assign tsm4_scanin = tsm3_scanout ; | |
| 358 | assign tsm5_scanin = tsm4_scanout ; | |
| 359 | assign tsm6_scanin = tsm5_scanout ; | |
| 360 | assign tsm7_scanin = tsm6_scanout ; | |
| 361 | assign spares_scanin = tsm7_scanout ; | |
| 362 | assign scan_out = spares_scanout ; | |
| 363 | ||
| 364 | // fixscan end: | |
| 365 | endmodule | |
| 366 | ||
| 367 | // Local Variables: | |
| 368 | // verilog-library-directories:("." "v") | |
| 369 | // End: | |
| 370 | ||
| 371 | ||
| 372 | ||
| 373 | ||
| 374 | ||
| 375 | ||
| 376 | // any PARAMS parms go into naming of macro | |
| 377 | ||
| 378 | module mmu_tmc_ctl_l1clkhdr_ctl_macro ( | |
| 379 | l2clk, | |
| 380 | l1en, | |
| 381 | pce_ov, | |
| 382 | stop, | |
| 383 | se, | |
| 384 | l1clk); | |
| 385 | ||
| 386 | ||
| 387 | input l2clk; | |
| 388 | input l1en; | |
| 389 | input pce_ov; | |
| 390 | input stop; | |
| 391 | input se; | |
| 392 | output l1clk; | |
| 393 | ||
| 394 | ||
| 395 | ||
| 396 | ||
| 397 | ||
| 398 | cl_sc1_l1hdr_8x c_0 ( | |
| 399 | ||
| 400 | ||
| 401 | .l2clk(l2clk), | |
| 402 | .pce(l1en), | |
| 403 | .l1clk(l1clk), | |
| 404 | .se(se), | |
| 405 | .pce_ov(pce_ov), | |
| 406 | .stop(stop) | |
| 407 | ); | |
| 408 | ||
| 409 | ||
| 410 | ||
| 411 | endmodule | |
| 412 | ||
| 413 | ||
| 414 | ||
| 415 | ||
| 416 | ||
| 417 | // any PARAMS parms go into naming of macro | |
| 418 | ||
| 419 | module mmu_tmc_ctl_msff_ctl_macro__width_1 ( | |
| 420 | din, | |
| 421 | l1clk, | |
| 422 | scan_in, | |
| 423 | siclk, | |
| 424 | soclk, | |
| 425 | dout, | |
| 426 | scan_out); | |
| 427 | wire [0:0] fdin; | |
| 428 | ||
| 429 | input [0:0] din; | |
| 430 | input l1clk; | |
| 431 | input scan_in; | |
| 432 | ||
| 433 | ||
| 434 | input siclk; | |
| 435 | input soclk; | |
| 436 | ||
| 437 | output [0:0] dout; | |
| 438 | output scan_out; | |
| 439 | assign fdin[0:0] = din[0:0]; | |
| 440 | ||
| 441 | ||
| 442 | ||
| 443 | ||
| 444 | ||
| 445 | ||
| 446 | dff #(1) d0_0 ( | |
| 447 | .l1clk(l1clk), | |
| 448 | .siclk(siclk), | |
| 449 | .soclk(soclk), | |
| 450 | .d(fdin[0:0]), | |
| 451 | .si(scan_in), | |
| 452 | .so(scan_out), | |
| 453 | .q(dout[0:0]) | |
| 454 | ); | |
| 455 | ||
| 456 | ||
| 457 | ||
| 458 | ||
| 459 | ||
| 460 | ||
| 461 | ||
| 462 | ||
| 463 | ||
| 464 | ||
| 465 | ||
| 466 | ||
| 467 | endmodule | |
| 468 | ||
| 469 | ||
| 470 | ||
| 471 | ||
| 472 | ||
| 473 | ||
| 474 | ||
| 475 | ||
| 476 | ||
| 477 | ||
| 478 | ||
| 479 | ||
| 480 | ||
| 481 | // any PARAMS parms go into naming of macro | |
| 482 | ||
| 483 | module mmu_tmc_ctl_msff_ctl_macro__width_4 ( | |
| 484 | din, | |
| 485 | l1clk, | |
| 486 | scan_in, | |
| 487 | siclk, | |
| 488 | soclk, | |
| 489 | dout, | |
| 490 | scan_out); | |
| 491 | wire [3:0] fdin; | |
| 492 | wire [2:0] so; | |
| 493 | ||
| 494 | input [3:0] din; | |
| 495 | input l1clk; | |
| 496 | input scan_in; | |
| 497 | ||
| 498 | ||
| 499 | input siclk; | |
| 500 | input soclk; | |
| 501 | ||
| 502 | output [3:0] dout; | |
| 503 | output scan_out; | |
| 504 | assign fdin[3:0] = din[3:0]; | |
| 505 | ||
| 506 | ||
| 507 | ||
| 508 | ||
| 509 | ||
| 510 | ||
| 511 | dff #(4) d0_0 ( | |
| 512 | .l1clk(l1clk), | |
| 513 | .siclk(siclk), | |
| 514 | .soclk(soclk), | |
| 515 | .d(fdin[3:0]), | |
| 516 | .si({scan_in,so[2:0]}), | |
| 517 | .so({so[2:0],scan_out}), | |
| 518 | .q(dout[3:0]) | |
| 519 | ); | |
| 520 | ||
| 521 | ||
| 522 | ||
| 523 | ||
| 524 | ||
| 525 | ||
| 526 | ||
| 527 | ||
| 528 | ||
| 529 | ||
| 530 | ||
| 531 | ||
| 532 | endmodule | |
| 533 | ||
| 534 | ||
| 535 | ||
| 536 | ||
| 537 | ||
| 538 | ||
| 539 | ||
| 540 | ||
| 541 | ||
| 542 | // Description: Spare gate macro for control blocks | |
| 543 | // | |
| 544 | // Param num controls the number of times the macro is added | |
| 545 | // flops=0 can be used to use only combination spare logic | |
| 546 | ||
| 547 | ||
| 548 | module mmu_tmc_ctl_spare_ctl_macro__num_3 ( | |
| 549 | l1clk, | |
| 550 | scan_in, | |
| 551 | siclk, | |
| 552 | soclk, | |
| 553 | scan_out); | |
| 554 | wire si_0; | |
| 555 | wire so_0; | |
| 556 | wire spare0_flop_unused; | |
| 557 | wire spare0_buf_32x_unused; | |
| 558 | wire spare0_nand3_8x_unused; | |
| 559 | wire spare0_inv_8x_unused; | |
| 560 | wire spare0_aoi22_4x_unused; | |
| 561 | wire spare0_buf_8x_unused; | |
| 562 | wire spare0_oai22_4x_unused; | |
| 563 | wire spare0_inv_16x_unused; | |
| 564 | wire spare0_nand2_16x_unused; | |
| 565 | wire spare0_nor3_4x_unused; | |
| 566 | wire spare0_nand2_8x_unused; | |
| 567 | wire spare0_buf_16x_unused; | |
| 568 | wire spare0_nor2_16x_unused; | |
| 569 | wire spare0_inv_32x_unused; | |
| 570 | wire si_1; | |
| 571 | wire so_1; | |
| 572 | wire spare1_flop_unused; | |
| 573 | wire spare1_buf_32x_unused; | |
| 574 | wire spare1_nand3_8x_unused; | |
| 575 | wire spare1_inv_8x_unused; | |
| 576 | wire spare1_aoi22_4x_unused; | |
| 577 | wire spare1_buf_8x_unused; | |
| 578 | wire spare1_oai22_4x_unused; | |
| 579 | wire spare1_inv_16x_unused; | |
| 580 | wire spare1_nand2_16x_unused; | |
| 581 | wire spare1_nor3_4x_unused; | |
| 582 | wire spare1_nand2_8x_unused; | |
| 583 | wire spare1_buf_16x_unused; | |
| 584 | wire spare1_nor2_16x_unused; | |
| 585 | wire spare1_inv_32x_unused; | |
| 586 | wire si_2; | |
| 587 | wire so_2; | |
| 588 | wire spare2_flop_unused; | |
| 589 | wire spare2_buf_32x_unused; | |
| 590 | wire spare2_nand3_8x_unused; | |
| 591 | wire spare2_inv_8x_unused; | |
| 592 | wire spare2_aoi22_4x_unused; | |
| 593 | wire spare2_buf_8x_unused; | |
| 594 | wire spare2_oai22_4x_unused; | |
| 595 | wire spare2_inv_16x_unused; | |
| 596 | wire spare2_nand2_16x_unused; | |
| 597 | wire spare2_nor3_4x_unused; | |
| 598 | wire spare2_nand2_8x_unused; | |
| 599 | wire spare2_buf_16x_unused; | |
| 600 | wire spare2_nor2_16x_unused; | |
| 601 | wire spare2_inv_32x_unused; | |
| 602 | ||
| 603 | ||
| 604 | input l1clk; | |
| 605 | input scan_in; | |
| 606 | input siclk; | |
| 607 | input soclk; | |
| 608 | output scan_out; | |
| 609 | ||
| 610 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
| 611 | .siclk(siclk), | |
| 612 | .soclk(soclk), | |
| 613 | .si(si_0), | |
| 614 | .so(so_0), | |
| 615 | .d(1'b0), | |
| 616 | .q(spare0_flop_unused)); | |
| 617 | assign si_0 = scan_in; | |
| 618 | ||
| 619 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
| 620 | .out(spare0_buf_32x_unused)); | |
| 621 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
| 622 | .in1(1'b1), | |
| 623 | .in2(1'b1), | |
| 624 | .out(spare0_nand3_8x_unused)); | |
| 625 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
| 626 | .out(spare0_inv_8x_unused)); | |
| 627 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
| 628 | .in01(1'b1), | |
| 629 | .in10(1'b1), | |
| 630 | .in11(1'b1), | |
| 631 | .out(spare0_aoi22_4x_unused)); | |
| 632 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
| 633 | .out(spare0_buf_8x_unused)); | |
| 634 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
| 635 | .in01(1'b1), | |
| 636 | .in10(1'b1), | |
| 637 | .in11(1'b1), | |
| 638 | .out(spare0_oai22_4x_unused)); | |
| 639 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
| 640 | .out(spare0_inv_16x_unused)); | |
| 641 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
| 642 | .in1(1'b1), | |
| 643 | .out(spare0_nand2_16x_unused)); | |
| 644 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
| 645 | .in1(1'b0), | |
| 646 | .in2(1'b0), | |
| 647 | .out(spare0_nor3_4x_unused)); | |
| 648 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
| 649 | .in1(1'b1), | |
| 650 | .out(spare0_nand2_8x_unused)); | |
| 651 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
| 652 | .out(spare0_buf_16x_unused)); | |
| 653 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
| 654 | .in1(1'b0), | |
| 655 | .out(spare0_nor2_16x_unused)); | |
| 656 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
| 657 | .out(spare0_inv_32x_unused)); | |
| 658 | ||
| 659 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
| 660 | .siclk(siclk), | |
| 661 | .soclk(soclk), | |
| 662 | .si(si_1), | |
| 663 | .so(so_1), | |
| 664 | .d(1'b0), | |
| 665 | .q(spare1_flop_unused)); | |
| 666 | assign si_1 = so_0; | |
| 667 | ||
| 668 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
| 669 | .out(spare1_buf_32x_unused)); | |
| 670 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
| 671 | .in1(1'b1), | |
| 672 | .in2(1'b1), | |
| 673 | .out(spare1_nand3_8x_unused)); | |
| 674 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
| 675 | .out(spare1_inv_8x_unused)); | |
| 676 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
| 677 | .in01(1'b1), | |
| 678 | .in10(1'b1), | |
| 679 | .in11(1'b1), | |
| 680 | .out(spare1_aoi22_4x_unused)); | |
| 681 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
| 682 | .out(spare1_buf_8x_unused)); | |
| 683 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
| 684 | .in01(1'b1), | |
| 685 | .in10(1'b1), | |
| 686 | .in11(1'b1), | |
| 687 | .out(spare1_oai22_4x_unused)); | |
| 688 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
| 689 | .out(spare1_inv_16x_unused)); | |
| 690 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
| 691 | .in1(1'b1), | |
| 692 | .out(spare1_nand2_16x_unused)); | |
| 693 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
| 694 | .in1(1'b0), | |
| 695 | .in2(1'b0), | |
| 696 | .out(spare1_nor3_4x_unused)); | |
| 697 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
| 698 | .in1(1'b1), | |
| 699 | .out(spare1_nand2_8x_unused)); | |
| 700 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
| 701 | .out(spare1_buf_16x_unused)); | |
| 702 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
| 703 | .in1(1'b0), | |
| 704 | .out(spare1_nor2_16x_unused)); | |
| 705 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
| 706 | .out(spare1_inv_32x_unused)); | |
| 707 | ||
| 708 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
| 709 | .siclk(siclk), | |
| 710 | .soclk(soclk), | |
| 711 | .si(si_2), | |
| 712 | .so(so_2), | |
| 713 | .d(1'b0), | |
| 714 | .q(spare2_flop_unused)); | |
| 715 | assign si_2 = so_1; | |
| 716 | ||
| 717 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
| 718 | .out(spare2_buf_32x_unused)); | |
| 719 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
| 720 | .in1(1'b1), | |
| 721 | .in2(1'b1), | |
| 722 | .out(spare2_nand3_8x_unused)); | |
| 723 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
| 724 | .out(spare2_inv_8x_unused)); | |
| 725 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
| 726 | .in01(1'b1), | |
| 727 | .in10(1'b1), | |
| 728 | .in11(1'b1), | |
| 729 | .out(spare2_aoi22_4x_unused)); | |
| 730 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
| 731 | .out(spare2_buf_8x_unused)); | |
| 732 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
| 733 | .in01(1'b1), | |
| 734 | .in10(1'b1), | |
| 735 | .in11(1'b1), | |
| 736 | .out(spare2_oai22_4x_unused)); | |
| 737 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
| 738 | .out(spare2_inv_16x_unused)); | |
| 739 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
| 740 | .in1(1'b1), | |
| 741 | .out(spare2_nand2_16x_unused)); | |
| 742 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
| 743 | .in1(1'b0), | |
| 744 | .in2(1'b0), | |
| 745 | .out(spare2_nor3_4x_unused)); | |
| 746 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
| 747 | .in1(1'b1), | |
| 748 | .out(spare2_nand2_8x_unused)); | |
| 749 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
| 750 | .out(spare2_buf_16x_unused)); | |
| 751 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
| 752 | .in1(1'b0), | |
| 753 | .out(spare2_nor2_16x_unused)); | |
| 754 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
| 755 | .out(spare2_inv_32x_unused)); | |
| 756 | assign scan_out = so_2; | |
| 757 | ||
| 758 | ||
| 759 | ||
| 760 | endmodule | |
| 761 |