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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_trc_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_trc_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | tcu_pce_ov, | |
39 | spc_aclk, | |
40 | spc_bclk, | |
41 | tcu_scan_en, | |
42 | htc_tsb_hit_hw1, | |
43 | htc_thr_valid_hw3, | |
44 | htc_ra2pahit_hw5, | |
45 | htc_ranotpax_hw5, | |
46 | tsm_waitfortte, | |
47 | htc_ep_miss_hw1, | |
48 | htc_rrindex_bit0, | |
49 | htc_rrindex_bit1, | |
50 | l2_ecc_err_hw1, | |
51 | cfg_ecc_err_m3, | |
52 | rr_ecc_err_hw5, | |
53 | l2_ecc_err_type, | |
54 | cfg_ecc_err_type, | |
55 | rr_ecc_err_type, | |
56 | cfg_ecc_err_index, | |
57 | rr_ecc_err_index, | |
58 | trs_rqv, | |
59 | trs_null_st, | |
60 | trs_waitrr3_st, | |
61 | trs_ep_err, | |
62 | trs_ecc_err, | |
63 | trs0_err_type, | |
64 | trs1_err_type, | |
65 | trs2_err_type, | |
66 | trs3_err_type, | |
67 | trs4_err_type, | |
68 | trs5_err_type, | |
69 | trs6_err_type, | |
70 | trs7_err_type, | |
71 | trs0_err_index, | |
72 | trs1_err_index, | |
73 | trs2_err_index, | |
74 | trs3_err_index, | |
75 | trs4_err_index, | |
76 | trs5_err_index, | |
77 | trs6_err_index, | |
78 | trs7_err_index, | |
79 | trs_eccerr_st, | |
80 | trs_eperr_st, | |
81 | scan_out); | |
82 | wire pce_ov; | |
83 | wire stop; | |
84 | wire se; | |
85 | wire siclk; | |
86 | wire soclk; | |
87 | wire l1clk; | |
88 | wire trs0_scanin; | |
89 | wire trs0_scanout; | |
90 | wire trs1_scanin; | |
91 | wire trs1_scanout; | |
92 | wire trs2_scanin; | |
93 | wire trs2_scanout; | |
94 | wire trs3_scanin; | |
95 | wire trs3_scanout; | |
96 | wire trs4_scanin; | |
97 | wire trs4_scanout; | |
98 | wire trs5_scanin; | |
99 | wire trs5_scanout; | |
100 | wire trs6_scanin; | |
101 | wire trs6_scanout; | |
102 | wire trs7_scanin; | |
103 | wire trs7_scanout; | |
104 | wire spares_scanin; | |
105 | wire spares_scanout; | |
106 | ||
107 | ||
108 | input l2clk; | |
109 | input scan_in; | |
110 | input tcu_pce_ov; // scan signals | |
111 | input spc_aclk; | |
112 | input spc_bclk; | |
113 | input tcu_scan_en; | |
114 | ||
115 | ||
116 | input [7:0] htc_tsb_hit_hw1; | |
117 | input [7:0] htc_thr_valid_hw3; | |
118 | input [7:0] htc_ra2pahit_hw5; | |
119 | input [7:0] htc_ranotpax_hw5; | |
120 | input [7:0] tsm_waitfortte; | |
121 | input [7:0] htc_ep_miss_hw1; | |
122 | input [7:0] htc_rrindex_bit0; | |
123 | input [7:0] htc_rrindex_bit1; | |
124 | ||
125 | ||
126 | input [7:0] l2_ecc_err_hw1; | |
127 | input [7:0] cfg_ecc_err_m3; | |
128 | input [7:0] rr_ecc_err_hw5; | |
129 | ||
130 | input [1:0] l2_ecc_err_type; | |
131 | input [1:0] cfg_ecc_err_type; | |
132 | input [1:0] rr_ecc_err_type; | |
133 | ||
134 | input [2:0] cfg_ecc_err_index; | |
135 | input [2:0] rr_ecc_err_index; | |
136 | ||
137 | ||
138 | ||
139 | output [7:0] trs_rqv; | |
140 | output [7:0] trs_null_st; | |
141 | output [7:0] trs_waitrr3_st; | |
142 | output [7:0] trs_ep_err; | |
143 | output [7:0] trs_ecc_err; | |
144 | output [2:0] trs0_err_type; | |
145 | output [2:0] trs1_err_type; | |
146 | output [2:0] trs2_err_type; | |
147 | output [2:0] trs3_err_type; | |
148 | output [2:0] trs4_err_type; | |
149 | output [2:0] trs5_err_type; | |
150 | output [2:0] trs6_err_type; | |
151 | output [2:0] trs7_err_type; | |
152 | output [2:0] trs0_err_index; | |
153 | output [2:0] trs1_err_index; | |
154 | output [2:0] trs2_err_index; | |
155 | output [2:0] trs3_err_index; | |
156 | output [2:0] trs4_err_index; | |
157 | output [2:0] trs5_err_index; | |
158 | output [2:0] trs6_err_index; | |
159 | output [2:0] trs7_err_index; | |
160 | ||
161 | output [7:0] trs_eccerr_st; | |
162 | output [7:0] trs_eperr_st; | |
163 | ||
164 | output scan_out; | |
165 | ||
166 | assign pce_ov = tcu_pce_ov; | |
167 | assign stop = 1'b0; | |
168 | assign se = tcu_scan_en; | |
169 | ||
170 | assign siclk = spc_aclk; | |
171 | assign soclk = spc_bclk; | |
172 | ||
173 | ||
174 | /////////////////////////////////////////////////// | |
175 | // clock header | |
176 | /////////////////////////////////////////////////// | |
177 | mmu_trc_ctl_l1clkhdr_ctl_macro clkgen ( | |
178 | .l2clk(l2clk), | |
179 | .l1en (1'b1), | |
180 | .l1clk(l1clk), | |
181 | .pce_ov(pce_ov), | |
182 | .stop(stop), | |
183 | .se(se) | |
184 | ); | |
185 | ||
186 | ||
187 | /* | |
188 | // mmu_trs_ctl AUTO_TEMPLATE | |
189 | ( | |
190 | .ep_miss_hw1(htc_ep_miss_hw1[@]), | |
191 | .rrindex_bit0(htc_rrindex_bit0[@]), | |
192 | .rrindex_bit1(htc_rrindex_bit1[@]), | |
193 | .l2_ecc_err_hw1(l2_ecc_err_hw1[@]), | |
194 | .cfg_ecc_err_m3(cfg_ecc_err_m3[@]), | |
195 | .rr_ecc_err_hw5(rr_ecc_err_hw5[@]), | |
196 | .tsb_hit_hw1(htc_tsb_hit_hw1[@]), | |
197 | .thr_valid_hw3(htc_thr_valid_hw3[@]), | |
198 | .tsm_waitfortte(tsm_waitfortte[@]), | |
199 | .ra2pahit_hw5(htc_ra2pahit_hw5[@]), | |
200 | .ranotpax_hw5(htc_ranotpax_hw5[@]), | |
201 | .trs_null_st(trs_null_st[@]), | |
202 | .trs_waitrr3_st(trs_waitrr3_st[@]), | |
203 | .trs_rqv(trs_rqv[@]), | |
204 | .trs_ecc_err(trs_ecc_err[@]), | |
205 | .trs_ep_err(trs_ecc_err[@]), | |
206 | .trs_err_type(trs@_err_type[2:0]), | |
207 | .trs_err_index(trs@_err_index[2:0]), | |
208 | .trs_eperr_st (trs_eperr_st[@]), | |
209 | .trs_eccerr_st (trs_eccerr_st[@]), | |
210 | ); | |
211 | */ | |
212 | ||
213 | mmu_trs_ctl trs0 ( | |
214 | /*AUTOINST*/ | |
215 | // Outputs | |
216 | .trs_rqv (trs_rqv[0]), // Templated | |
217 | .trs_null_st (trs_null_st[0]), // Templated | |
218 | .trs_waitrr3_st (trs_waitrr3_st[0]), // Templated | |
219 | .trs_ecc_err (trs_ecc_err[0]), // Templated | |
220 | .trs_err_type (trs0_err_type[2:0]), // Templated | |
221 | .trs_err_index (trs0_err_index[2:0]), // Templated | |
222 | .trs_ep_err (trs_ep_err[0]), // Templated | |
223 | .trs_eperr_st (trs_eperr_st[0]), // Templated | |
224 | .trs_eccerr_st (trs_eccerr_st[0]), // Templated | |
225 | // Inputs | |
226 | .scan_in(trs0_scanin), | |
227 | .scan_out(trs0_scanout), | |
228 | .l1clk (l1clk), | |
229 | .tsb_hit_hw1 (htc_tsb_hit_hw1[0]), // Templated | |
230 | .thr_valid_hw3 (htc_thr_valid_hw3[0]), // Templated | |
231 | .ra2pahit_hw5 (htc_ra2pahit_hw5[0]), // Templated | |
232 | .ranotpax_hw5 (htc_ranotpax_hw5[0]), // Templated | |
233 | .tsm_waitfortte (tsm_waitfortte[0]), // Templated | |
234 | .ep_miss_hw1 (htc_ep_miss_hw1[0]), // Templated | |
235 | .rrindex_bit0 (htc_rrindex_bit0[0]), // Templated | |
236 | .rrindex_bit1 (htc_rrindex_bit1[0]), // Templated | |
237 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[0]), // Templated | |
238 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[0]), // Templated | |
239 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[0]), // Templated | |
240 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
241 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
242 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
243 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
244 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
245 | .spc_aclk(spc_aclk), | |
246 | .spc_bclk(spc_bclk)); | |
247 | ||
248 | mmu_trs_ctl trs1 (/*AUTOINST*/ | |
249 | // Outputs | |
250 | .trs_rqv (trs_rqv[1]), // Templated | |
251 | .trs_null_st (trs_null_st[1]), // Templated | |
252 | .trs_waitrr3_st (trs_waitrr3_st[1]), // Templated | |
253 | .trs_ecc_err (trs_ecc_err[1]), // Templated | |
254 | .trs_err_type (trs1_err_type[2:0]), // Templated | |
255 | .trs_err_index (trs1_err_index[2:0]), // Templated | |
256 | .trs_ep_err (trs_ep_err[1]), // Templated | |
257 | .trs_eperr_st (trs_eperr_st[1]), // Templated | |
258 | .trs_eccerr_st (trs_eccerr_st[1]), // Templated | |
259 | // Inputs | |
260 | .scan_in(trs1_scanin), | |
261 | .scan_out(trs1_scanout), | |
262 | .l1clk (l1clk), | |
263 | .tsb_hit_hw1 (htc_tsb_hit_hw1[1]), // Templated | |
264 | .thr_valid_hw3 (htc_thr_valid_hw3[1]), // Templated | |
265 | .ra2pahit_hw5 (htc_ra2pahit_hw5[1]), // Templated | |
266 | .ranotpax_hw5 (htc_ranotpax_hw5[1]), // Templated | |
267 | .tsm_waitfortte (tsm_waitfortte[1]), // Templated | |
268 | .ep_miss_hw1 (htc_ep_miss_hw1[1]), // Templated | |
269 | .rrindex_bit0 (htc_rrindex_bit0[1]), // Templated | |
270 | .rrindex_bit1 (htc_rrindex_bit1[1]), // Templated | |
271 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[1]), // Templated | |
272 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[1]), // Templated | |
273 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[1]), // Templated | |
274 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
275 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
276 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
277 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
278 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
279 | .spc_aclk(spc_aclk), | |
280 | .spc_bclk(spc_bclk)); | |
281 | mmu_trs_ctl trs2 ( | |
282 | /*AUTOINST*/ | |
283 | // Outputs | |
284 | .trs_rqv (trs_rqv[2]), // Templated | |
285 | .trs_null_st (trs_null_st[2]), // Templated | |
286 | .trs_waitrr3_st (trs_waitrr3_st[2]), // Templated | |
287 | .trs_ecc_err (trs_ecc_err[2]), // Templated | |
288 | .trs_err_type (trs2_err_type[2:0]), // Templated | |
289 | .trs_err_index (trs2_err_index[2:0]), // Templated | |
290 | .trs_ep_err (trs_ep_err[2]), // Templated | |
291 | .trs_eperr_st (trs_eperr_st[2]), // Templated | |
292 | .trs_eccerr_st (trs_eccerr_st[2]), // Templated | |
293 | // Inputs | |
294 | .scan_in(trs2_scanin), | |
295 | .scan_out(trs2_scanout), | |
296 | .l1clk (l1clk), | |
297 | .tsb_hit_hw1 (htc_tsb_hit_hw1[2]), // Templated | |
298 | .thr_valid_hw3 (htc_thr_valid_hw3[2]), // Templated | |
299 | .ra2pahit_hw5 (htc_ra2pahit_hw5[2]), // Templated | |
300 | .ranotpax_hw5 (htc_ranotpax_hw5[2]), // Templated | |
301 | .tsm_waitfortte (tsm_waitfortte[2]), // Templated | |
302 | .ep_miss_hw1 (htc_ep_miss_hw1[2]), // Templated | |
303 | .rrindex_bit0 (htc_rrindex_bit0[2]), // Templated | |
304 | .rrindex_bit1 (htc_rrindex_bit1[2]), // Templated | |
305 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[2]), // Templated | |
306 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[2]), // Templated | |
307 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[2]), // Templated | |
308 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
309 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
310 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
311 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
312 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
313 | .spc_aclk(spc_aclk), | |
314 | .spc_bclk(spc_bclk)); | |
315 | mmu_trs_ctl trs3 ( | |
316 | /*AUTOINST*/ | |
317 | // Outputs | |
318 | .trs_rqv (trs_rqv[3]), // Templated | |
319 | .trs_null_st (trs_null_st[3]), // Templated | |
320 | .trs_waitrr3_st (trs_waitrr3_st[3]), // Templated | |
321 | .trs_ecc_err (trs_ecc_err[3]), // Templated | |
322 | .trs_err_type (trs3_err_type[2:0]), // Templated | |
323 | .trs_err_index (trs3_err_index[2:0]), // Templated | |
324 | .trs_ep_err (trs_ep_err[3]), // Templated | |
325 | .trs_eperr_st (trs_eperr_st[3]), // Templated | |
326 | .trs_eccerr_st (trs_eccerr_st[3]), // Templated | |
327 | // Inputs | |
328 | .scan_in(trs3_scanin), | |
329 | .scan_out(trs3_scanout), | |
330 | .l1clk (l1clk), | |
331 | .tsb_hit_hw1 (htc_tsb_hit_hw1[3]), // Templated | |
332 | .thr_valid_hw3 (htc_thr_valid_hw3[3]), // Templated | |
333 | .ra2pahit_hw5 (htc_ra2pahit_hw5[3]), // Templated | |
334 | .ranotpax_hw5 (htc_ranotpax_hw5[3]), // Templated | |
335 | .tsm_waitfortte (tsm_waitfortte[3]), // Templated | |
336 | .ep_miss_hw1 (htc_ep_miss_hw1[3]), // Templated | |
337 | .rrindex_bit0 (htc_rrindex_bit0[3]), // Templated | |
338 | .rrindex_bit1 (htc_rrindex_bit1[3]), // Templated | |
339 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[3]), // Templated | |
340 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[3]), // Templated | |
341 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[3]), // Templated | |
342 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
343 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
344 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
345 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
346 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
347 | .spc_aclk(spc_aclk), | |
348 | .spc_bclk(spc_bclk)); | |
349 | mmu_trs_ctl trs4 ( | |
350 | /*AUTOINST*/ | |
351 | // Outputs | |
352 | .trs_rqv (trs_rqv[4]), // Templated | |
353 | .trs_null_st (trs_null_st[4]), // Templated | |
354 | .trs_waitrr3_st (trs_waitrr3_st[4]), // Templated | |
355 | .trs_ecc_err (trs_ecc_err[4]), // Templated | |
356 | .trs_err_type (trs4_err_type[2:0]), // Templated | |
357 | .trs_err_index (trs4_err_index[2:0]), // Templated | |
358 | .trs_ep_err (trs_ep_err[4]), // Templated | |
359 | .trs_eperr_st (trs_eperr_st[4]), // Templated | |
360 | .trs_eccerr_st (trs_eccerr_st[4]), // Templated | |
361 | // Inputs | |
362 | .scan_in(trs4_scanin), | |
363 | .scan_out(trs4_scanout), | |
364 | .l1clk (l1clk), | |
365 | .tsb_hit_hw1 (htc_tsb_hit_hw1[4]), // Templated | |
366 | .thr_valid_hw3 (htc_thr_valid_hw3[4]), // Templated | |
367 | .ra2pahit_hw5 (htc_ra2pahit_hw5[4]), // Templated | |
368 | .ranotpax_hw5 (htc_ranotpax_hw5[4]), // Templated | |
369 | .tsm_waitfortte (tsm_waitfortte[4]), // Templated | |
370 | .ep_miss_hw1 (htc_ep_miss_hw1[4]), // Templated | |
371 | .rrindex_bit0 (htc_rrindex_bit0[4]), // Templated | |
372 | .rrindex_bit1 (htc_rrindex_bit1[4]), // Templated | |
373 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[4]), // Templated | |
374 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[4]), // Templated | |
375 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[4]), // Templated | |
376 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
377 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
378 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
379 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
380 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
381 | .spc_aclk(spc_aclk), | |
382 | .spc_bclk(spc_bclk)); | |
383 | mmu_trs_ctl trs5 ( | |
384 | /*AUTOINST*/ | |
385 | // Outputs | |
386 | .trs_rqv (trs_rqv[5]), // Templated | |
387 | .trs_null_st (trs_null_st[5]), // Templated | |
388 | .trs_waitrr3_st (trs_waitrr3_st[5]), // Templated | |
389 | .trs_ecc_err (trs_ecc_err[5]), // Templated | |
390 | .trs_err_type (trs5_err_type[2:0]), // Templated | |
391 | .trs_err_index (trs5_err_index[2:0]), // Templated | |
392 | .trs_ep_err (trs_ep_err[5]), // Templated | |
393 | .trs_eperr_st (trs_eperr_st[5]), // Templated | |
394 | .trs_eccerr_st (trs_eccerr_st[5]), // Templated | |
395 | // Inputs | |
396 | .scan_in(trs5_scanin), | |
397 | .scan_out(trs5_scanout), | |
398 | .l1clk (l1clk), | |
399 | .tsb_hit_hw1 (htc_tsb_hit_hw1[5]), // Templated | |
400 | .thr_valid_hw3 (htc_thr_valid_hw3[5]), // Templated | |
401 | .ra2pahit_hw5 (htc_ra2pahit_hw5[5]), // Templated | |
402 | .ranotpax_hw5 (htc_ranotpax_hw5[5]), // Templated | |
403 | .tsm_waitfortte (tsm_waitfortte[5]), // Templated | |
404 | .ep_miss_hw1 (htc_ep_miss_hw1[5]), // Templated | |
405 | .rrindex_bit0 (htc_rrindex_bit0[5]), // Templated | |
406 | .rrindex_bit1 (htc_rrindex_bit1[5]), // Templated | |
407 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[5]), // Templated | |
408 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[5]), // Templated | |
409 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[5]), // Templated | |
410 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
411 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
412 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
413 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
414 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
415 | .spc_aclk(spc_aclk), | |
416 | .spc_bclk(spc_bclk)); | |
417 | mmu_trs_ctl trs6 ( | |
418 | /*AUTOINST*/ | |
419 | // Outputs | |
420 | .trs_rqv (trs_rqv[6]), // Templated | |
421 | .trs_null_st (trs_null_st[6]), // Templated | |
422 | .trs_waitrr3_st (trs_waitrr3_st[6]), // Templated | |
423 | .trs_ecc_err (trs_ecc_err[6]), // Templated | |
424 | .trs_err_type (trs6_err_type[2:0]), // Templated | |
425 | .trs_err_index (trs6_err_index[2:0]), // Templated | |
426 | .trs_ep_err (trs_ep_err[6]), // Templated | |
427 | .trs_eperr_st (trs_eperr_st[6]), // Templated | |
428 | .trs_eccerr_st (trs_eccerr_st[6]), // Templated | |
429 | // Inputs | |
430 | .scan_in(trs6_scanin), | |
431 | .scan_out(trs6_scanout), | |
432 | .l1clk (l1clk), | |
433 | .tsb_hit_hw1 (htc_tsb_hit_hw1[6]), // Templated | |
434 | .thr_valid_hw3 (htc_thr_valid_hw3[6]), // Templated | |
435 | .ra2pahit_hw5 (htc_ra2pahit_hw5[6]), // Templated | |
436 | .ranotpax_hw5 (htc_ranotpax_hw5[6]), // Templated | |
437 | .tsm_waitfortte (tsm_waitfortte[6]), // Templated | |
438 | .ep_miss_hw1 (htc_ep_miss_hw1[6]), // Templated | |
439 | .rrindex_bit0 (htc_rrindex_bit0[6]), // Templated | |
440 | .rrindex_bit1 (htc_rrindex_bit1[6]), // Templated | |
441 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[6]), // Templated | |
442 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[6]), // Templated | |
443 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[6]), // Templated | |
444 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
445 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
446 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
447 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
448 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
449 | .spc_aclk(spc_aclk), | |
450 | .spc_bclk(spc_bclk)); | |
451 | mmu_trs_ctl trs7 ( | |
452 | /*AUTOINST*/ | |
453 | // Outputs | |
454 | .trs_rqv (trs_rqv[7]), // Templated | |
455 | .trs_null_st (trs_null_st[7]), // Templated | |
456 | .trs_waitrr3_st (trs_waitrr3_st[7]), // Templated | |
457 | .trs_ecc_err (trs_ecc_err[7]), // Templated | |
458 | .trs_err_type (trs7_err_type[2:0]), // Templated | |
459 | .trs_err_index (trs7_err_index[2:0]), // Templated | |
460 | .trs_ep_err (trs_ep_err[7]), // Templated | |
461 | .trs_eperr_st (trs_eperr_st[7]), // Templated | |
462 | .trs_eccerr_st (trs_eccerr_st[7]), // Templated | |
463 | // Inputs | |
464 | .scan_in(trs7_scanin), | |
465 | .scan_out(trs7_scanout), | |
466 | .l1clk (l1clk), | |
467 | .tsb_hit_hw1 (htc_tsb_hit_hw1[7]), // Templated | |
468 | .thr_valid_hw3 (htc_thr_valid_hw3[7]), // Templated | |
469 | .ra2pahit_hw5 (htc_ra2pahit_hw5[7]), // Templated | |
470 | .ranotpax_hw5 (htc_ranotpax_hw5[7]), // Templated | |
471 | .tsm_waitfortte (tsm_waitfortte[7]), // Templated | |
472 | .ep_miss_hw1 (htc_ep_miss_hw1[7]), // Templated | |
473 | .rrindex_bit0 (htc_rrindex_bit0[7]), // Templated | |
474 | .rrindex_bit1 (htc_rrindex_bit1[7]), // Templated | |
475 | .l2_ecc_err_hw1 (l2_ecc_err_hw1[7]), // Templated | |
476 | .cfg_ecc_err_m3 (cfg_ecc_err_m3[7]), // Templated | |
477 | .rr_ecc_err_hw5 (rr_ecc_err_hw5[7]), // Templated | |
478 | .l2_ecc_err_type (l2_ecc_err_type[1:0]), | |
479 | .cfg_ecc_err_type (cfg_ecc_err_type[1:0]), | |
480 | .rr_ecc_err_type (rr_ecc_err_type[1:0]), | |
481 | .cfg_ecc_err_index (cfg_ecc_err_index[2:0]), | |
482 | .rr_ecc_err_index (rr_ecc_err_index[2:0]), | |
483 | .spc_aclk(spc_aclk), | |
484 | .spc_bclk(spc_bclk)); | |
485 | ||
486 | //////////////////////////////////////////////////////// | |
487 | // SPARE CELLS | |
488 | //////////////////////////////////////////////////////// | |
489 | mmu_trc_ctl_spare_ctl_macro__num_2 spares ( | |
490 | .scan_in(spares_scanin), | |
491 | .scan_out(spares_scanout), | |
492 | .l1clk (l1clk), | |
493 | .siclk(siclk), | |
494 | .soclk(soclk) | |
495 | ); | |
496 | //////////////////////////////////////////////////////// | |
497 | ||
498 | // fixscan start: | |
499 | assign trs0_scanin = scan_in ; | |
500 | assign trs1_scanin = trs0_scanout ; | |
501 | assign trs2_scanin = trs1_scanout ; | |
502 | assign trs3_scanin = trs2_scanout ; | |
503 | assign trs4_scanin = trs3_scanout ; | |
504 | assign trs5_scanin = trs4_scanout ; | |
505 | assign trs6_scanin = trs5_scanout ; | |
506 | assign trs7_scanin = trs6_scanout ; | |
507 | assign spares_scanin = trs7_scanout ; | |
508 | assign scan_out = spares_scanout ; | |
509 | ||
510 | // fixscan end: | |
511 | endmodule | |
512 | ||
513 | // Local Variables: | |
514 | // verilog-library-directories:("." "v") | |
515 | // End: | |
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 | ||
522 | // any PARAMS parms go into naming of macro | |
523 | ||
524 | module mmu_trc_ctl_l1clkhdr_ctl_macro ( | |
525 | l2clk, | |
526 | l1en, | |
527 | pce_ov, | |
528 | stop, | |
529 | se, | |
530 | l1clk); | |
531 | ||
532 | ||
533 | input l2clk; | |
534 | input l1en; | |
535 | input pce_ov; | |
536 | input stop; | |
537 | input se; | |
538 | output l1clk; | |
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | cl_sc1_l1hdr_8x c_0 ( | |
545 | ||
546 | ||
547 | .l2clk(l2clk), | |
548 | .pce(l1en), | |
549 | .l1clk(l1clk), | |
550 | .se(se), | |
551 | .pce_ov(pce_ov), | |
552 | .stop(stop) | |
553 | ); | |
554 | ||
555 | ||
556 | ||
557 | endmodule | |
558 | ||
559 | ||
560 | ||
561 | ||
562 | // any PARAMS parms go into naming of macro | |
563 | ||
564 | module mmu_trc_ctl_msff_ctl_macro__width_1 ( | |
565 | din, | |
566 | l1clk, | |
567 | scan_in, | |
568 | siclk, | |
569 | soclk, | |
570 | dout, | |
571 | scan_out); | |
572 | wire [0:0] fdin; | |
573 | ||
574 | input [0:0] din; | |
575 | input l1clk; | |
576 | input scan_in; | |
577 | ||
578 | ||
579 | input siclk; | |
580 | input soclk; | |
581 | ||
582 | output [0:0] dout; | |
583 | output scan_out; | |
584 | assign fdin[0:0] = din[0:0]; | |
585 | ||
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | dff #(1) d0_0 ( | |
592 | .l1clk(l1clk), | |
593 | .siclk(siclk), | |
594 | .soclk(soclk), | |
595 | .d(fdin[0:0]), | |
596 | .si(scan_in), | |
597 | .so(scan_out), | |
598 | .q(dout[0:0]) | |
599 | ); | |
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | endmodule | |
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | // any PARAMS parms go into naming of macro | |
627 | ||
628 | module mmu_trc_ctl_msff_ctl_macro__width_3 ( | |
629 | din, | |
630 | l1clk, | |
631 | scan_in, | |
632 | siclk, | |
633 | soclk, | |
634 | dout, | |
635 | scan_out); | |
636 | wire [2:0] fdin; | |
637 | wire [1:0] so; | |
638 | ||
639 | input [2:0] din; | |
640 | input l1clk; | |
641 | input scan_in; | |
642 | ||
643 | ||
644 | input siclk; | |
645 | input soclk; | |
646 | ||
647 | output [2:0] dout; | |
648 | output scan_out; | |
649 | assign fdin[2:0] = din[2:0]; | |
650 | ||
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | dff #(3) d0_0 ( | |
657 | .l1clk(l1clk), | |
658 | .siclk(siclk), | |
659 | .soclk(soclk), | |
660 | .d(fdin[2:0]), | |
661 | .si({scan_in,so[1:0]}), | |
662 | .so({so[1:0],scan_out}), | |
663 | .q(dout[2:0]) | |
664 | ); | |
665 | ||
666 | ||
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | endmodule | |
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | // Description: Spare gate macro for control blocks | |
688 | // | |
689 | // Param num controls the number of times the macro is added | |
690 | // flops=0 can be used to use only combination spare logic | |
691 | ||
692 | ||
693 | module mmu_trc_ctl_spare_ctl_macro__num_2 ( | |
694 | l1clk, | |
695 | scan_in, | |
696 | siclk, | |
697 | soclk, | |
698 | scan_out); | |
699 | wire si_0; | |
700 | wire so_0; | |
701 | wire spare0_flop_unused; | |
702 | wire spare0_buf_32x_unused; | |
703 | wire spare0_nand3_8x_unused; | |
704 | wire spare0_inv_8x_unused; | |
705 | wire spare0_aoi22_4x_unused; | |
706 | wire spare0_buf_8x_unused; | |
707 | wire spare0_oai22_4x_unused; | |
708 | wire spare0_inv_16x_unused; | |
709 | wire spare0_nand2_16x_unused; | |
710 | wire spare0_nor3_4x_unused; | |
711 | wire spare0_nand2_8x_unused; | |
712 | wire spare0_buf_16x_unused; | |
713 | wire spare0_nor2_16x_unused; | |
714 | wire spare0_inv_32x_unused; | |
715 | wire si_1; | |
716 | wire so_1; | |
717 | wire spare1_flop_unused; | |
718 | wire spare1_buf_32x_unused; | |
719 | wire spare1_nand3_8x_unused; | |
720 | wire spare1_inv_8x_unused; | |
721 | wire spare1_aoi22_4x_unused; | |
722 | wire spare1_buf_8x_unused; | |
723 | wire spare1_oai22_4x_unused; | |
724 | wire spare1_inv_16x_unused; | |
725 | wire spare1_nand2_16x_unused; | |
726 | wire spare1_nor3_4x_unused; | |
727 | wire spare1_nand2_8x_unused; | |
728 | wire spare1_buf_16x_unused; | |
729 | wire spare1_nor2_16x_unused; | |
730 | wire spare1_inv_32x_unused; | |
731 | ||
732 | ||
733 | input l1clk; | |
734 | input scan_in; | |
735 | input siclk; | |
736 | input soclk; | |
737 | output scan_out; | |
738 | ||
739 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
740 | .siclk(siclk), | |
741 | .soclk(soclk), | |
742 | .si(si_0), | |
743 | .so(so_0), | |
744 | .d(1'b0), | |
745 | .q(spare0_flop_unused)); | |
746 | assign si_0 = scan_in; | |
747 | ||
748 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
749 | .out(spare0_buf_32x_unused)); | |
750 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
751 | .in1(1'b1), | |
752 | .in2(1'b1), | |
753 | .out(spare0_nand3_8x_unused)); | |
754 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
755 | .out(spare0_inv_8x_unused)); | |
756 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
757 | .in01(1'b1), | |
758 | .in10(1'b1), | |
759 | .in11(1'b1), | |
760 | .out(spare0_aoi22_4x_unused)); | |
761 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
762 | .out(spare0_buf_8x_unused)); | |
763 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
764 | .in01(1'b1), | |
765 | .in10(1'b1), | |
766 | .in11(1'b1), | |
767 | .out(spare0_oai22_4x_unused)); | |
768 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
769 | .out(spare0_inv_16x_unused)); | |
770 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
771 | .in1(1'b1), | |
772 | .out(spare0_nand2_16x_unused)); | |
773 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
774 | .in1(1'b0), | |
775 | .in2(1'b0), | |
776 | .out(spare0_nor3_4x_unused)); | |
777 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
778 | .in1(1'b1), | |
779 | .out(spare0_nand2_8x_unused)); | |
780 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
781 | .out(spare0_buf_16x_unused)); | |
782 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
783 | .in1(1'b0), | |
784 | .out(spare0_nor2_16x_unused)); | |
785 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
786 | .out(spare0_inv_32x_unused)); | |
787 | ||
788 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
789 | .siclk(siclk), | |
790 | .soclk(soclk), | |
791 | .si(si_1), | |
792 | .so(so_1), | |
793 | .d(1'b0), | |
794 | .q(spare1_flop_unused)); | |
795 | assign si_1 = so_0; | |
796 | ||
797 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
798 | .out(spare1_buf_32x_unused)); | |
799 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
800 | .in1(1'b1), | |
801 | .in2(1'b1), | |
802 | .out(spare1_nand3_8x_unused)); | |
803 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
804 | .out(spare1_inv_8x_unused)); | |
805 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
806 | .in01(1'b1), | |
807 | .in10(1'b1), | |
808 | .in11(1'b1), | |
809 | .out(spare1_aoi22_4x_unused)); | |
810 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
811 | .out(spare1_buf_8x_unused)); | |
812 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
813 | .in01(1'b1), | |
814 | .in10(1'b1), | |
815 | .in11(1'b1), | |
816 | .out(spare1_oai22_4x_unused)); | |
817 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
818 | .out(spare1_inv_16x_unused)); | |
819 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
820 | .in1(1'b1), | |
821 | .out(spare1_nand2_16x_unused)); | |
822 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
823 | .in1(1'b0), | |
824 | .in2(1'b0), | |
825 | .out(spare1_nor3_4x_unused)); | |
826 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
827 | .in1(1'b1), | |
828 | .out(spare1_nand2_8x_unused)); | |
829 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
830 | .out(spare1_buf_16x_unused)); | |
831 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
832 | .in1(1'b0), | |
833 | .out(spare1_nor2_16x_unused)); | |
834 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
835 | .out(spare1_inv_32x_unused)); | |
836 | assign scan_out = so_1; | |
837 | ||
838 | ||
839 | ||
840 | endmodule | |
841 |