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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: mmu_tsm_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module mmu_tsm_ctl ( | |
36 | l1clk, | |
37 | scan_in, | |
38 | spc_aclk, | |
39 | spc_bclk, | |
40 | data_rcvd_hw1, | |
41 | tlb_miss_m, | |
42 | tsb_done_hw2, | |
43 | vld_tsbptr_m2, | |
44 | thr_valid_m1, | |
45 | thr_valid_m0, | |
46 | cindex_bit0, | |
47 | cindex_bit1, | |
48 | hwtw_burst, | |
49 | trs_eperr_st, | |
50 | trs_eccerr_st, | |
51 | tsm_tsb_miss_hw2, | |
52 | tsm_rqv, | |
53 | tsm_waitfortte, | |
54 | scan_out); | |
55 | wire siclk; | |
56 | wire soclk; | |
57 | wire [1:0] cindex; | |
58 | wire goto_null_state; | |
59 | wire null_state; | |
60 | wire validreq_state; | |
61 | wire seqm1_state; | |
62 | wire seqm2_state; | |
63 | wire cfgdone_state; | |
64 | wire ttewait_state; | |
65 | wire next_null_state; | |
66 | wire next_null_state_; | |
67 | wire null_state_; | |
68 | wire null_state_reg_scanin; | |
69 | wire null_state_reg_scanout; | |
70 | wire goto_validreq_state; | |
71 | wire outstanding_miss_state; | |
72 | wire next_validreq_state; | |
73 | wire validreq_state_reg_scanin; | |
74 | wire validreq_state_reg_scanout; | |
75 | wire goto_seqm1_state; | |
76 | wire next_seqm1_state; | |
77 | wire seqm1_state_reg_scanin; | |
78 | wire seqm1_state_reg_scanout; | |
79 | wire goto_seqm2_state; | |
80 | wire next_seqm2_state; | |
81 | wire seqm2_state_reg_scanin; | |
82 | wire seqm2_state_reg_scanout; | |
83 | wire goto_cfgdone_state; | |
84 | wire next_cfgdone_state; | |
85 | wire cfgdone_state_reg_scanin; | |
86 | wire cfgdone_state_reg_scanout; | |
87 | wire goto_ttewait_state; | |
88 | wire next_ttewait_state; | |
89 | wire ttewait_state_reg_scanin; | |
90 | wire ttewait_state_reg_scanout; | |
91 | wire goto_outstanding_miss_state; | |
92 | wire next_outstanding_miss_state; | |
93 | wire outstanding_miss_state_reg_scanin; | |
94 | wire outstanding_miss_state_reg_scanout; | |
95 | wire data_rcvd_lat_scanin; | |
96 | wire data_rcvd_lat_scanout; | |
97 | wire data_rcvd_hw1_ff; | |
98 | wire req_enq; | |
99 | wire req_deq; | |
100 | wire [3:0] next_bal; | |
101 | wire [3:0] bal; | |
102 | wire bal_lat_scanin; | |
103 | wire bal_lat_scanout; | |
104 | ||
105 | ||
106 | input l1clk; | |
107 | input scan_in; | |
108 | input spc_aclk; | |
109 | input spc_bclk; | |
110 | ||
111 | input data_rcvd_hw1; // data back from gkt, from htc | |
112 | input tlb_miss_m; // indicates tlb miss, from htc | |
113 | input tsb_done_hw2; // indicates tsb hit, from htc | |
114 | input vld_tsbptr_m2; // indicates valid tsbptr | |
115 | input thr_valid_m1; // valid req in M1 which got asi grant and room avail | |
116 | input thr_valid_m0; // valid req in M0 | |
117 | ||
118 | input cindex_bit0; | |
119 | input cindex_bit1; | |
120 | ||
121 | ||
122 | input hwtw_burst; // hwtw is in burst mode | |
123 | ||
124 | // mra read, and data available. | |
125 | input trs_eperr_st; // trs is in ep miss err state | |
126 | ||
127 | input trs_eccerr_st; // trs is in eccerr state | |
128 | ||
129 | output tsm_tsb_miss_hw2; // no tsb hit on any of the 4 tsb | |
130 | output tsm_rqv; // request is valid, in REQ or CFG_RD | |
131 | output tsm_waitfortte; // all tte not received | |
132 | output scan_out; | |
133 | ||
134 | assign siclk = spc_aclk; | |
135 | assign soclk = spc_bclk; | |
136 | ||
137 | ||
138 | ||
139 | assign cindex[1:0] = {cindex_bit1, cindex_bit0}; | |
140 | ||
141 | /////////////////////////////////////////////////// | |
142 | // CASE STATEMENT DESCRIPTION OF TSM MACHINE | |
143 | /////////////////////////////////////////////////// | |
144 | ||
145 | // tsb_done_hw2 = tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4; | |
146 | //case(`TSM_STATE) | |
147 | // `NULL_ST: | |
148 | // if (~tlb_miss_m) | |
149 | // next_state = `NULL_ST; | |
150 | // else | |
151 | // next_state = `VALIDREQ_ST; | |
152 | // | |
153 | // `VALIDREQ_ST: | |
154 | // begin | |
155 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte) | |
156 | // next_state = `NULL_ST; | |
157 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
158 | // next_state = `TTEWAIT_ST; | |
159 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & burst_mode & (~(cindex[1:0] ==2'b11 & thr_valid_m1))) | |
160 | // next_state = `VALIDREQ_ST; | |
161 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~burst_mode & ~thr_valid_m0) | |
162 | // next_state = `VALIDREQ_ST; | |
163 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~burst_mode & thr_valid_m0) | |
164 | // next_state = `SEQM1_ST; | |
165 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & (cindex[1:0] ==2'b11 & thr_valid_m1)) | |
166 | // next_state = `CFGDONE_ST; | |
167 | // end | |
168 | // | |
169 | // `SEQM1_ST: | |
170 | // begin | |
171 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte) | |
172 | // next_state = `NULL_ST; | |
173 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
174 | // next_state = `TTEWAIT_ST; | |
175 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~thr_valid_m1) | |
176 | // next_state = `VALIDREQ_ST; | |
177 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & thr_valid_m1 & (cindex[1:0] ==2'b11)) | |
178 | // next_state = `CFGDONE_ST; | |
179 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & thr_valid_m1 & ~(cindex[1:0] ==2'b11)) | |
180 | // next_state = `SEQM2_ST; | |
181 | // end | |
182 | // | |
183 | // `SEQM2_ST: | |
184 | // begin | |
185 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte) | |
186 | // next_state = `NULL_ST; | |
187 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
188 | // next_state = `TTEWAIT_ST; | |
189 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & ~tsm_waitfortte) | |
190 | // next_state = `VALIDREQ_ST; | |
191 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
192 | // next_state = `SEQM2_ST; | |
193 | // end | |
194 | // | |
195 | // `CFGDONE_ST: | |
196 | // begin | |
197 | // if (~tsm_waitfortte) | |
198 | // next_state = `NULL_ST; | |
199 | // if ((tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
200 | // next_state = `TTEWAIT_ST; | |
201 | // if (~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & tsm_waitfortte) | |
202 | // next_state = `CFGDONE_ST; | |
203 | // end | |
204 | // | |
205 | // `TTEWAIT_ST: | |
206 | // begin | |
207 | // if (tlb_miss_m) | |
208 | // next_state = `OUTMISSWAIT_ST; | |
209 | // if (~tsm_waitfortte & ~tlb_miss_m) | |
210 | // next_state = `NULL_ST; | |
211 | // if (tsm_waitfortte & ~tlb_miss_m) | |
212 | // next_state = `TTEWAIT_ST; | |
213 | // end | |
214 | // | |
215 | // `OUTMISSWAIT_ST: | |
216 | // begin | |
217 | // if (tsm_waitfortte) | |
218 | // next_state = `OUTMISSWAIT_ST; | |
219 | // else | |
220 | // next_state = `VALIDREQ_ST; | |
221 | // end | |
222 | //endcase // case(`TSM_STATE) | |
223 | ||
224 | ||
225 | ||
226 | // 0in one_hot -var {null_state,validreq_state,seqm1_state,seqm2_state,cfgdone_state,ttewait_state,outstanding_miss_state} | |
227 | /////////////////////////////////////////////////// | |
228 | // Null State (NULL_ST) | |
229 | /////////////////////////////////////////////////// | |
230 | // Goto null state if either of following is true | |
231 | // => NULL_ST and no tlb miss | |
232 | // => VALIDREQ_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte | |
233 | // => SEQM1_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and all no outstanding tte | |
234 | // => SEQM2_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and all no outstanding tte | |
235 | // => CFGDONE_ST and no outstanding tte | |
236 | // => TTEWAIT_ST and no tlb miss and no outstanding tte | |
237 | ||
238 | // Leave null state if either of following is true | |
239 | // => tlb miss occurs (goto validreq state) | |
240 | ||
241 | assign goto_null_state = (null_state & ~tlb_miss_m) | | |
242 | (validreq_state & tsb_done_hw2 & ~tsm_waitfortte) | | |
243 | (seqm1_state & tsb_done_hw2 & ~tsm_waitfortte) | | |
244 | (seqm2_state & tsb_done_hw2 & ~tsm_waitfortte) | | |
245 | (cfgdone_state & ~tsm_waitfortte) | //irrespective of tsb_hit_hw2 | |
246 | (ttewait_state & ~tsm_waitfortte & ~tlb_miss_m); | |
247 | ||
248 | assign next_null_state = goto_null_state; | |
249 | assign next_null_state_ = ~next_null_state; | |
250 | assign null_state = ~null_state_; | |
251 | ||
252 | mmu_tsm_ctl_msff_ctl_macro__width_1 null_state_reg ( | |
253 | .scan_in(null_state_reg_scanin), | |
254 | .scan_out(null_state_reg_scanout), | |
255 | .l1clk(l1clk), | |
256 | .din (next_null_state_), | |
257 | .dout (null_state_), | |
258 | .siclk(siclk), | |
259 | .soclk(soclk) | |
260 | ); | |
261 | ||
262 | /////////////////////////////////////////////////// | |
263 | // Valid Req State (VALIDREQ_ST) | |
264 | /////////////////////////////////////////////////// | |
265 | // Goto valid req. state if either of following is true | |
266 | // => VALIDREQ_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and burst mode and all tsb cfg not read | |
267 | // => VALIDREQ_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~burst mode and current thread not selected | |
268 | // => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~thr_valid_m1 (req did not get a grant from asi). | |
269 | // => SEQM2_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte | |
270 | // => NULL_ST and tlb_miss_m | |
271 | // => OUTMISSWAIT_ST and no outstanding tte | |
272 | ||
273 | // Leave valid req. state if either of following is true | |
274 | // => VALIDREQ_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST) | |
275 | // => VALIDREQ_ST and all req are read (go to CFGDONE_ST) | |
276 | // => VALIDREQ_ST and not burst mode and current thread selected (thr_valid_m0) (go to SEQM1_ST) | |
277 | ||
278 | assign goto_validreq_state = (validreq_state & ~tsb_done_hw2 & hwtw_burst & ~(cindex[1] & cindex[0] & thr_valid_m1)) | | |
279 | (validreq_state & ~tsb_done_hw2 & ~hwtw_burst & ~thr_valid_m0) | | |
280 | (seqm1_state & ~tsb_done_hw2 & ~thr_valid_m1) | | |
281 | (seqm2_state & ~tsb_done_hw2 & ~tsm_waitfortte) | | |
282 | (null_state & tlb_miss_m) | | |
283 | (outstanding_miss_state & ~tsm_waitfortte); | |
284 | assign next_validreq_state = goto_validreq_state; | |
285 | ||
286 | ||
287 | mmu_tsm_ctl_msff_ctl_macro__width_1 validreq_state_reg ( | |
288 | .scan_in(validreq_state_reg_scanin), | |
289 | .scan_out(validreq_state_reg_scanout), | |
290 | .l1clk(l1clk), | |
291 | .din (next_validreq_state), | |
292 | .dout (validreq_state), | |
293 | .siclk(siclk), | |
294 | .soclk(soclk) | |
295 | ); | |
296 | ||
297 | /////////////////////////////////////////////////// | |
298 | // Sequential M1 State (SEQM1_ST) | |
299 | /////////////////////////////////////////////////// | |
300 | // Goto sequential M1 state if either of following is true | |
301 | // => VALIDREQ_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and not burst mode and current thread selected | |
302 | ||
303 | // Leave sequential M1 state if either of following is true | |
304 | // => SEQM1_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST) | |
305 | // => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and ~thr_valid_m1 (req was not granted), (go to VALIDREQ_ST) | |
306 | // => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and thr_valid_m1 (go to SEQM2_ST or CFGDONE_ST) | |
307 | ||
308 | assign goto_seqm1_state = (validreq_state & ~tsb_done_hw2 & ~hwtw_burst & thr_valid_m0); | |
309 | assign next_seqm1_state = goto_seqm1_state; | |
310 | ||
311 | ||
312 | mmu_tsm_ctl_msff_ctl_macro__width_1 seqm1_state_reg ( | |
313 | .scan_in(seqm1_state_reg_scanin), | |
314 | .scan_out(seqm1_state_reg_scanout), | |
315 | .l1clk(l1clk), | |
316 | .din (next_seqm1_state), | |
317 | .dout (seqm1_state), | |
318 | .siclk(siclk), | |
319 | .soclk(soclk) | |
320 | ); | |
321 | ||
322 | /////////////////////////////////////////////////// | |
323 | // Sequential M2 State (SEQM2_ST) | |
324 | /////////////////////////////////////////////////// | |
325 | // Goto sequential M2 state if either of following is true | |
326 | // => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and thr_valid_m1 & all cfg not read | |
327 | // => SEQM2_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
328 | ||
329 | // Leave sequential M2 state if either of following is true | |
330 | // => SEQM2_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) (go to NULL_ST or TTEWAIT_ST) | |
331 | // => SEQM2_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and no outstanding tte (go to VALIDREQ_ST) | |
332 | ||
333 | assign goto_seqm2_state = (seqm1_state & ~tsb_done_hw2 & thr_valid_m1 & ~(cindex[1] & cindex[0])) | | |
334 | (seqm2_state & ~tsb_done_hw2 & tsm_waitfortte); | |
335 | assign next_seqm2_state = goto_seqm2_state; | |
336 | ||
337 | ||
338 | mmu_tsm_ctl_msff_ctl_macro__width_1 seqm2_state_reg ( | |
339 | .scan_in(seqm2_state_reg_scanin), | |
340 | .scan_out(seqm2_state_reg_scanout), | |
341 | .l1clk(l1clk), | |
342 | .din (next_seqm2_state), | |
343 | .dout (seqm2_state), | |
344 | .siclk(siclk), | |
345 | .soclk(soclk) | |
346 | ); | |
347 | ||
348 | /////////////////////////////////////////////////// | |
349 | // AllConfigRead State (CFGDONE_ST) | |
350 | /////////////////////////////////////////////////// | |
351 | // Goto all TSB read state if either of following is true | |
352 | // => VALIDREQ_ST and burst mode and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & all cfg read | |
353 | // => SEQM1_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) & all cfg read | |
354 | // => CFGDONE_ST and ~(tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
355 | ||
356 | // Leave all CFG read state if either of following is true | |
357 | // => CFGDONE_ST and all no outstanding TTE (go to NULL_ST) | |
358 | // => CFGDONE_ST and TSB hit and outstanding TTE (go to TTEWAIT_ST) | |
359 | ||
360 | assign goto_cfgdone_state = (cfgdone_state & ~tsb_done_hw2 & tsm_waitfortte) | | |
361 | (validreq_state & ~tsb_done_hw2 & hwtw_burst & cindex[1] & cindex[0] & thr_valid_m1) | | |
362 | (seqm1_state & ~tsb_done_hw2 & cindex[1] & cindex[0] & thr_valid_m1); | |
363 | ||
364 | ||
365 | assign next_cfgdone_state = goto_cfgdone_state; | |
366 | ||
367 | ||
368 | mmu_tsm_ctl_msff_ctl_macro__width_1 cfgdone_state_reg ( | |
369 | .scan_in(cfgdone_state_reg_scanin), | |
370 | .scan_out(cfgdone_state_reg_scanout), | |
371 | .l1clk(l1clk), | |
372 | .din (next_cfgdone_state), | |
373 | .dout (cfgdone_state), | |
374 | .siclk(siclk), | |
375 | .soclk(soclk) | |
376 | ); | |
377 | ||
378 | /////////////////////////////////////////////////// | |
379 | // TTE Wait State (TTEWAIT_ST) | |
380 | // go to this state on (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4). | |
381 | /////////////////////////////////////////////////// | |
382 | // Goto TTEWAIT_ST state if either of following is true | |
383 | // => TTEWAIT_ST and no tlb miss and outstanding tte | |
384 | // => VALIDREQ_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
385 | // => SEQM1_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
386 | // => SEQM2_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
387 | // => CFGDONE_ST and (tsb_hit_hw2|ep_miss_hw2|l2_ecc_err_hw2|cfg_ecc_err_m4) and outstanding tte | |
388 | ||
389 | // Leave TTEWAIT_ST state if either of following is true | |
390 | // => TTEWAIT_ST and tlb miss (go to OUTMISSWAIT_ST) | |
391 | // => TTEWAIT_ST and no tlb miss and no outstanding tte (go to NULL_ST) | |
392 | ||
393 | assign goto_ttewait_state = (ttewait_state & ~tlb_miss_m & tsm_waitfortte) | | |
394 | (validreq_state & tsb_done_hw2 & tsm_waitfortte) | | |
395 | (seqm1_state & tsb_done_hw2 & tsm_waitfortte) | | |
396 | (seqm2_state & tsb_done_hw2 & tsm_waitfortte) | | |
397 | (cfgdone_state & tsb_done_hw2 & tsm_waitfortte); | |
398 | ||
399 | assign next_ttewait_state = goto_ttewait_state; | |
400 | ||
401 | ||
402 | mmu_tsm_ctl_msff_ctl_macro__width_1 ttewait_state_reg ( | |
403 | .scan_in(ttewait_state_reg_scanin), | |
404 | .scan_out(ttewait_state_reg_scanout), | |
405 | .l1clk(l1clk), | |
406 | .din (next_ttewait_state), | |
407 | .dout (ttewait_state), | |
408 | .siclk(siclk), | |
409 | .soclk(soclk) | |
410 | ); | |
411 | ||
412 | /////////////////////////////////////////////////// | |
413 | // Outstanding Miss State (OUTMISSWAIT_ST) | |
414 | // Indicates TTEWAIT_ST and a tlb_miss_m (can happen when we | |
415 | // have a tsb hit, thread gets restarted, but all tte's are not done for | |
416 | // the original miss) | |
417 | /////////////////////////////////////////////////// | |
418 | // Goto all OUTMISSWAIT_ST if either of following is true | |
419 | // => OUTMISSWAIT_ST and not all TTE received (tsm_waitfortte) | |
420 | // => TTEWAIT_ST and tlb_miss_m | |
421 | ||
422 | assign goto_outstanding_miss_state = (outstanding_miss_state & tsm_waitfortte) | | |
423 | (ttewait_state & tlb_miss_m); | |
424 | ||
425 | assign next_outstanding_miss_state = goto_outstanding_miss_state; | |
426 | ||
427 | ||
428 | mmu_tsm_ctl_msff_ctl_macro__width_1 outstanding_miss_state_reg ( | |
429 | .scan_in(outstanding_miss_state_reg_scanin), | |
430 | .scan_out(outstanding_miss_state_reg_scanout), | |
431 | .l1clk(l1clk), | |
432 | .din (next_outstanding_miss_state), | |
433 | .dout (outstanding_miss_state), | |
434 | .siclk(siclk), | |
435 | .soclk(soclk) | |
436 | ); | |
437 | ||
438 | /////////////////////////////////////////////////// | |
439 | // End of State machine | |
440 | /////////////////////////////////////////////////// | |
441 | ||
442 | /////////////////////////////////////////////////// | |
443 | // EnQ/DeQ TTEs | |
444 | // Keeping track of outstanding TTE requests. | |
445 | // Increment the counter on every request sent out (vld_tsbptr_m2), | |
446 | // Decrement the counter on every data recvd, (data_rcvd_hw1) | |
447 | /////////////////////////////////////////////////// | |
448 | mmu_tsm_ctl_msff_ctl_macro__width_1 data_rcvd_lat ( | |
449 | .scan_in(data_rcvd_lat_scanin), | |
450 | .scan_out(data_rcvd_lat_scanout), | |
451 | .l1clk(l1clk), | |
452 | .din (data_rcvd_hw1), | |
453 | .dout (data_rcvd_hw1_ff), | |
454 | .siclk(siclk), | |
455 | .soclk(soclk) | |
456 | ); | |
457 | assign req_enq = vld_tsbptr_m2 & ~data_rcvd_hw1_ff; | |
458 | assign req_deq = data_rcvd_hw1_ff & ~vld_tsbptr_m2; | |
459 | ||
460 | //0in bits_on -var {req_enq, req_deq} -max 1; | |
461 | assign next_bal[3:0] = ({4{req_enq & ~bal[3] & ~bal[2] & ~bal[1] & ~bal[0]}} & 4'b0001) | | |
462 | ({4{req_enq & ~bal[3] & ~bal[2] & ~bal[1] & bal[0]}} & 4'b0011) | | |
463 | ({4{req_enq & ~bal[3] & ~bal[2] & bal[1] & bal[0]}} & 4'b0111) | | |
464 | ({4{req_enq & ~bal[3] & bal[2] & bal[1] & bal[0]}} & 4'b1111) | | |
465 | ({4{req_deq & bal[3] & bal[2] & bal[1] & bal[0]}} & 4'b0111) | | |
466 | ({4{req_deq & ~bal[3] & bal[2] & bal[1] & bal[0]}} & 4'b0011) | | |
467 | ({4{req_deq & ~bal[3] & ~bal[2] & bal[1] & bal[0]}} & 4'b0001) | | |
468 | ({4{req_deq & ~bal[3] & ~bal[2] & ~bal[1] & bal[0]}} & 4'b0000) | | |
469 | ({4{~req_deq & ~req_enq}} & bal[3:0]); | |
470 | ||
471 | mmu_tsm_ctl_msff_ctl_macro__width_4 bal_lat ( | |
472 | .scan_in(bal_lat_scanin), | |
473 | .scan_out(bal_lat_scanout), | |
474 | .l1clk(l1clk), | |
475 | .din ({next_bal[3:0]}), | |
476 | .dout ({bal[3:0]}), | |
477 | .siclk(siclk), | |
478 | .soclk(soclk) | |
479 | ); | |
480 | ||
481 | /////////////////////////////////////////////////// | |
482 | // State Machine Outputs | |
483 | /////////////////////////////////////////////////// | |
484 | assign tsm_tsb_miss_hw2 = ~tsm_waitfortte & cfgdone_state & ~tsb_done_hw2 & ~trs_eccerr_st & ~trs_eperr_st; | |
485 | assign tsm_rqv = validreq_state; | |
486 | assign tsm_waitfortte = |next_bal[3:0]; | |
487 | ||
488 | ||
489 | supply0 vss; | |
490 | supply1 vdd; | |
491 | ||
492 | // fixscan start: | |
493 | assign null_state_reg_scanin = scan_in ; | |
494 | assign validreq_state_reg_scanin = null_state_reg_scanout ; | |
495 | assign seqm1_state_reg_scanin = validreq_state_reg_scanout; | |
496 | assign seqm2_state_reg_scanin = seqm1_state_reg_scanout ; | |
497 | assign cfgdone_state_reg_scanin = seqm2_state_reg_scanout ; | |
498 | assign ttewait_state_reg_scanin = cfgdone_state_reg_scanout; | |
499 | assign outstanding_miss_state_reg_scanin = ttewait_state_reg_scanout; | |
500 | assign data_rcvd_lat_scanin = outstanding_miss_state_reg_scanout; | |
501 | assign bal_lat_scanin = data_rcvd_lat_scanout ; | |
502 | assign scan_out = bal_lat_scanout ; | |
503 | // fixscan end: | |
504 | endmodule | |
505 | ||
506 | ||
507 | ||
508 | ||
509 | ||
510 | ||
511 | // any PARAMS parms go into naming of macro | |
512 | ||
513 | module mmu_tsm_ctl_msff_ctl_macro__width_1 ( | |
514 | din, | |
515 | l1clk, | |
516 | scan_in, | |
517 | siclk, | |
518 | soclk, | |
519 | dout, | |
520 | scan_out); | |
521 | wire [0:0] fdin; | |
522 | ||
523 | input [0:0] din; | |
524 | input l1clk; | |
525 | input scan_in; | |
526 | ||
527 | ||
528 | input siclk; | |
529 | input soclk; | |
530 | ||
531 | output [0:0] dout; | |
532 | output scan_out; | |
533 | assign fdin[0:0] = din[0:0]; | |
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | dff #(1) d0_0 ( | |
541 | .l1clk(l1clk), | |
542 | .siclk(siclk), | |
543 | .soclk(soclk), | |
544 | .d(fdin[0:0]), | |
545 | .si(scan_in), | |
546 | .so(scan_out), | |
547 | .q(dout[0:0]) | |
548 | ); | |
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | endmodule | |
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | ||
574 | ||
575 | // any PARAMS parms go into naming of macro | |
576 | ||
577 | module mmu_tsm_ctl_msff_ctl_macro__width_4 ( | |
578 | din, | |
579 | l1clk, | |
580 | scan_in, | |
581 | siclk, | |
582 | soclk, | |
583 | dout, | |
584 | scan_out); | |
585 | wire [3:0] fdin; | |
586 | wire [2:0] so; | |
587 | ||
588 | input [3:0] din; | |
589 | input l1clk; | |
590 | input scan_in; | |
591 | ||
592 | ||
593 | input siclk; | |
594 | input soclk; | |
595 | ||
596 | output [3:0] dout; | |
597 | output scan_out; | |
598 | assign fdin[3:0] = din[3:0]; | |
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | dff #(4) d0_0 ( | |
606 | .l1clk(l1clk), | |
607 | .siclk(siclk), | |
608 | .soclk(soclk), | |
609 | .d(fdin[3:0]), | |
610 | .si({scan_in,so[2:0]}), | |
611 | .so({so[2:0],scan_out}), | |
612 | .q(dout[3:0]) | |
613 | ); | |
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | ||
625 | ||
626 | endmodule | |
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 |