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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pku_swl_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module pku_swl_ctl ( | |
36 | tlu_halted, | |
37 | dec_block_store_stall, | |
38 | dec_ierr_d, | |
39 | tcu_do_mode, | |
40 | lsu_pku_pmen, | |
41 | spc_core_running_status, | |
42 | lsu_spec_enable, | |
43 | ifu_ibuffer_write_c, | |
44 | ifu_buf0_inst, | |
45 | lsu_stb_alloc, | |
46 | lsu_stb_dealloc, | |
47 | lsu_block_store_kill, | |
48 | swl_divide_wait_all, | |
49 | fgu_divide_completion, | |
50 | ifu_buf0_valid_p, | |
51 | ifu_upper_buffer_valid_p, | |
52 | pku_raw_pick_p, | |
53 | tlu_flush_ifu, | |
54 | tlu_retry_state, | |
55 | dec_valid_d, | |
56 | dec_decode_d, | |
57 | dec_true_valid_e, | |
58 | lsu_sync, | |
59 | lsu_complete, | |
60 | dec_br_taken_e, | |
61 | l2clk, | |
62 | scan_in, | |
63 | tcu_pce_ov, | |
64 | spc_aclk, | |
65 | spc_bclk, | |
66 | tcu_scan_en, | |
67 | swl_ready_p, | |
68 | swl_spec_ready_p, | |
69 | pku_inst_cnt_brtaken0, | |
70 | pku_inst_cnt_brtaken1, | |
71 | pku_annul_ds_dcti_brtaken0_e, | |
72 | pku_annul_ds_dcti_brtaken1_e, | |
73 | pku_load_flush_w, | |
74 | pku_flush_upper_buffer, | |
75 | pku_flush_buffer0, | |
76 | pku_valid_e, | |
77 | pku_flush_m, | |
78 | pku_flush_b, | |
79 | pku_flush_lm, | |
80 | pku_flush_lb, | |
81 | pku_flush_f1, | |
82 | pku_flush_f2, | |
83 | pku_ds_e, | |
84 | swl_divide_wait, | |
85 | swl_cancel_pick_p, | |
86 | pku_quiesce, | |
87 | scan_out, | |
88 | pku_lsu_p, | |
89 | pku_fgu_p, | |
90 | pku_pdist_p, | |
91 | pku_twocycle_p, | |
92 | pku_idest_p, | |
93 | pku_fdest_p, | |
94 | pku_fsrc_rd_p, | |
95 | pku_isrc_rs1_p, | |
96 | pku_isrc_rs2_p, | |
97 | pku_isrc_rd_p); | |
98 | wire l1clk; | |
99 | wire spares_scanin; | |
100 | wire spares_scanout; | |
101 | wire pce_ov; | |
102 | wire stop; | |
103 | wire siclk; | |
104 | wire soclk; | |
105 | wire se; | |
106 | wire illegal_p; | |
107 | wire [31:0] i; | |
108 | wire isrc_rs1_u; | |
109 | wire isrc_rs2_u; | |
110 | wire isrc_rd_u; | |
111 | wire idest_u; | |
112 | wire fsrc_rs1_u; | |
113 | wire fsrc_rs2_u; | |
114 | wire fsrc_rd_u; | |
115 | wire fdest_u; | |
116 | wire fgu_u; | |
117 | wire dcti_u; | |
118 | wire specbr_u; | |
119 | wire specld_u; | |
120 | wire specfp_u; | |
121 | wire lsu_u; | |
122 | wire postsync_u; | |
123 | wire div_u; | |
124 | wire pdist_u; | |
125 | wire condbr_u; | |
126 | wire callclass_u; | |
127 | wire fccsrc_u; | |
128 | wire fsrsync_u; | |
129 | wire twocycle_u; | |
130 | wire bkick_u; | |
131 | wire fbkick_u; | |
132 | wire fccdest_u; | |
133 | wire fpdest_single_u; | |
134 | wire fpdest_double_u; | |
135 | wire fpsrc_single_u; | |
136 | wire fpsrc_double_u; | |
137 | wire store_u; | |
138 | wire windowsync_u; | |
139 | wire fsrc_rs1_p; | |
140 | wire fsrc_rs2_p; | |
141 | wire dcti_p; | |
142 | wire specbr_p; | |
143 | wire specld_p; | |
144 | wire specfp_p; | |
145 | wire postsync_p; | |
146 | wire do_mode_f; | |
147 | wire div_p; | |
148 | wire condbr_p; | |
149 | wire callclass_p; | |
150 | wire fccsrc_p; | |
151 | wire fsrsync_p; | |
152 | wire bkick_p; | |
153 | wire fbkick_p; | |
154 | wire fccdest_p; | |
155 | wire fpdest_single_p; | |
156 | wire fpdest_double_p; | |
157 | wire fpsrc_single_p; | |
158 | wire fpsrc_double_p; | |
159 | wire store_p; | |
160 | wire windowsync_p; | |
161 | wire do_modef_scanin; | |
162 | wire do_modef_scanout; | |
163 | wire l1clk_pm1; | |
164 | wire [4:0] rs1; | |
165 | wire [4:0] rs2; | |
166 | wire [4:0] rd; | |
167 | wire annul; | |
168 | wire vld_p; | |
169 | wire vld_1; | |
170 | wire valid; | |
171 | wire vld_d; | |
172 | wire vld_e; | |
173 | wire vld_m; | |
174 | wire vld_b; | |
175 | wire vld_w; | |
176 | wire vld_f4; | |
177 | wire vld_f5; | |
178 | wire vld_fb; | |
179 | wire lsu_sync_wait; | |
180 | wire pick_clken; | |
181 | wire vldraw_d; | |
182 | wire vldraw_e; | |
183 | wire vldraw_m; | |
184 | wire ext_flush; | |
185 | wire thread_active; | |
186 | wire l1clk_pm2; | |
187 | wire active_clken; | |
188 | wire external_flushf_scanin; | |
189 | wire external_flushf_scanout; | |
190 | wire lsu_ext_flush_in; | |
191 | wire lsu_ext_flushf_scanin; | |
192 | wire lsu_ext_flushf_scanout; | |
193 | wire lsu_ext_flush_w; | |
194 | wire divide_wait_outstanding; | |
195 | wire fpdouble_wait; | |
196 | wire fpdest_single_d; | |
197 | wire fpdest_single_e; | |
198 | wire fpdest_single_m; | |
199 | wire lsu_b; | |
200 | wire fpdest_single_b; | |
201 | wire lsu_w; | |
202 | wire fpdest_single_w; | |
203 | wire lsu_f4; | |
204 | wire fpdest_single_f4; | |
205 | wire fpdouble_cancel; | |
206 | wire lsu_f5; | |
207 | wire fpdest_single_f5; | |
208 | wire fpsingle_wait; | |
209 | wire fpdest_double_d; | |
210 | wire fpdest_double_e; | |
211 | wire fpdest_double_m; | |
212 | wire fpdest_double_b; | |
213 | wire fpdest_double_w; | |
214 | wire fpdest_double_f4; | |
215 | wire fpsingle_cancel; | |
216 | wire fpdest_double_f5; | |
217 | wire fccdep_wait; | |
218 | wire fccdest_d; | |
219 | wire fccdest_e; | |
220 | wire fccdest_m; | |
221 | wire fccdep_cancel; | |
222 | wire fccdest_b; | |
223 | wire fsrsync_wait; | |
224 | wire fgu_d; | |
225 | wire fgu_e; | |
226 | wire fgu_m; | |
227 | wire fgu_b; | |
228 | wire fgu_w; | |
229 | wire fsrsync_cancel; | |
230 | wire check_rs1_d; | |
231 | wire idest_d; | |
232 | wire specld_d; | |
233 | wire fdest_d; | |
234 | wire check_rs2_d; | |
235 | wire check_rd_d; | |
236 | wire check_rs1_e; | |
237 | wire idest_e; | |
238 | wire specld_e; | |
239 | wire fdest_e; | |
240 | wire check_rs2_e; | |
241 | wire check_rd_e; | |
242 | wire check_rs1_m; | |
243 | wire fdest_m; | |
244 | wire check_rs2_m; | |
245 | wire check_rd_m; | |
246 | wire check_rs1_b; | |
247 | wire fdest_b; | |
248 | wire check_rs2_b; | |
249 | wire check_rd_b; | |
250 | wire check_rs1_w; | |
251 | wire fdest_w; | |
252 | wire check_rs2_w; | |
253 | wire check_rd_w; | |
254 | wire cmp_rs1_rd_d; | |
255 | wire [4:0] rd_d; | |
256 | wire cmp_rs2_rd_d; | |
257 | wire cmp_rd_rd_d; | |
258 | wire cmp_rs1_rd_e; | |
259 | wire [4:0] rd_e; | |
260 | wire cmp_rs2_rd_e; | |
261 | wire cmp_rd_rd_e; | |
262 | wire cmp_rs1_rd_m; | |
263 | wire [4:0] rd_m; | |
264 | wire cmp_rs2_rd_m; | |
265 | wire cmp_rd_rd_m; | |
266 | wire cmp_rs1_rd_b; | |
267 | wire [4:0] rd_b; | |
268 | wire cmp_rs2_rd_b; | |
269 | wire cmp_rd_rd_b; | |
270 | wire cmp_rs1_rd_w; | |
271 | wire [4:0] rd_w; | |
272 | wire cmp_rs2_rd_w; | |
273 | wire cmp_rd_rd_w; | |
274 | wire dependent_cancel; | |
275 | wire wait_rs1_d; | |
276 | wire wait_rs2_d; | |
277 | wire wait_rd_d; | |
278 | wire wait_rs1_e; | |
279 | wire wait_rs2_e; | |
280 | wire wait_rd_e; | |
281 | wire wait_rd_m; | |
282 | wire wait_rd_b; | |
283 | wire dependent_wait; | |
284 | wire tlu_retryf_scanin; | |
285 | wire tlu_retryf_scanout; | |
286 | wire retry_state; | |
287 | wire block_store_stallf_scanin; | |
288 | wire block_store_stallf_scanout; | |
289 | wire [1:0] block_store_stall; | |
290 | wire full_scnt; | |
291 | wire lsu_sync_raw_w; | |
292 | wire dcti_d; | |
293 | wire dcti_e; | |
294 | wire any_twocycle_m; | |
295 | wire divide_wait1; | |
296 | wire stb_cancel; | |
297 | wire ldst_sync_single; | |
298 | wire ldst_sync_ldfsr; | |
299 | wire restore_scnt; | |
300 | wire pick_raw_p; | |
301 | wire pick_p; | |
302 | wire actual_pick_p; | |
303 | wire flush_p; | |
304 | wire actual_raw_pick_p; | |
305 | wire rawflush_p; | |
306 | wire set_postsync; | |
307 | wire clear_postsync; | |
308 | wire postsync_d; | |
309 | wire flush_d; | |
310 | wire postsync_e; | |
311 | wire flush_e; | |
312 | wire bkick_w; | |
313 | wire fbkick_fb; | |
314 | wire br_mispredict_m; | |
315 | wire callclass_m; | |
316 | wire bkick_m; | |
317 | wire postsync_in; | |
318 | wire post_sync; | |
319 | wire post_syncf_scanin; | |
320 | wire post_syncf_scanout; | |
321 | wire spec_enf_scanin; | |
322 | wire spec_enf_scanout; | |
323 | wire spec_en; | |
324 | wire active_threadf_scanin; | |
325 | wire active_threadf_scanout; | |
326 | wire set_postsync_ns; | |
327 | wire clear_postsync_ns; | |
328 | wire specbr_m; | |
329 | wire specld_b; | |
330 | wire fpvld_w2; | |
331 | wire lsu_sync_w; | |
332 | wire postsync_ns_in; | |
333 | wire postsync_ns; | |
334 | wire postsync_nsf_scanin; | |
335 | wire postsync_nsf_scanout; | |
336 | wire set_dep_wait; | |
337 | wire clear_dep_wait; | |
338 | wire dep_wait_in; | |
339 | wire set_dcti_wait; | |
340 | wire clear_dcti_wait; | |
341 | wire dcti_wait_in; | |
342 | wire set_dcti_couple_wait; | |
343 | wire clear_dcti_couple_wait; | |
344 | wire dcti_couple_wait_in; | |
345 | wire flush_div; | |
346 | wire div_d; | |
347 | wire div_e; | |
348 | wire set_divide_wait_in; | |
349 | wire clear_divide_wait_in; | |
350 | wire divide_wait_in; | |
351 | wire divide_waitf_scanin; | |
352 | wire divide_waitf_scanout; | |
353 | wire divide_wait1f_scanin; | |
354 | wire divide_wait1f_scanout; | |
355 | wire otherdivide_wait_in; | |
356 | wire lsu_completef_scanin; | |
357 | wire lsu_completef_scanout; | |
358 | wire lsu_complete_d1; | |
359 | wire lsu_complete_d2; | |
360 | wire set_lsu_sync_wait; | |
361 | wire clear_lsu_sync_wait; | |
362 | wire lsu_sync_wait_in; | |
363 | wire lsu_sync_waitf_scanin; | |
364 | wire lsu_sync_waitf_scanout; | |
365 | wire clear_lsu_sync_single; | |
366 | wire ldst_sync_single_in; | |
367 | wire ldst_sync_singlef_scanin; | |
368 | wire ldst_sync_singlef_scanout; | |
369 | wire clear_lsu_sync_ldfsr; | |
370 | wire fsrsync_w; | |
371 | wire specld_w; | |
372 | wire idest_w; | |
373 | wire ldst_sync_ldfsr_in; | |
374 | wire ldst_sync_ldfsrf_scanin; | |
375 | wire ldst_sync_ldfsrf_scanout; | |
376 | wire br_flush1_in; | |
377 | wire br_mispredict_e; | |
378 | wire brflush1_f_scanin; | |
379 | wire brflush1_f_scanout; | |
380 | wire br_flush1; | |
381 | wire br_flush2_in; | |
382 | wire brflush2_f_scanin; | |
383 | wire brflush2_f_scanout; | |
384 | wire brflush2; | |
385 | wire not_annul_ds1_in; | |
386 | wire annul_ds_dcti_e; | |
387 | wire not_annul_ds1_f_scanin; | |
388 | wire not_annul_ds1_f_scanout; | |
389 | wire not_annul_ds1; | |
390 | wire not_annul_ds2_in; | |
391 | wire not_annul_ds2_f_scanin; | |
392 | wire not_annul_ds2_f_scanout; | |
393 | wire not_annul_ds2; | |
394 | wire store_ds1_in; | |
395 | wire pick_store_d; | |
396 | wire store_ds1_f_scanin; | |
397 | wire store_ds1_f_scanout; | |
398 | wire store_ds1; | |
399 | wire store_ds2_in; | |
400 | wire store_ds2_f_scanin; | |
401 | wire store_ds2_f_scanout; | |
402 | wire store_ds2; | |
403 | wire store_ds; | |
404 | wire pick_store_p; | |
405 | wire late_flush_p; | |
406 | wire pickstoref_scanin; | |
407 | wire pickstoref_scanout; | |
408 | wire alloc_scnt; | |
409 | wire dealloc_scnt; | |
410 | wire inc_scnt_raw; | |
411 | wire dec_scnt_raw; | |
412 | wire hold_scnt_raw; | |
413 | wire annul_store_in; | |
414 | wire annul_store_f_scanin; | |
415 | wire annul_store_f_scanout; | |
416 | wire annul_store_d; | |
417 | wire inc_scnt; | |
418 | wire dec1_scnt; | |
419 | wire hold_scnt; | |
420 | wire dec2_scnt; | |
421 | wire inc2_ccnt; | |
422 | wire inc_ccnt_raw; | |
423 | wire inc1_ccnt; | |
424 | wire hold_ccnt_raw; | |
425 | wire hold_ccnt; | |
426 | wire dec_ccnt_raw; | |
427 | wire dec1_ccnt; | |
428 | wire [3:0] ccnt_in; | |
429 | wire [3:0] ccnt; | |
430 | wire [3:0] scnt_in; | |
431 | wire [3:0] scnt; | |
432 | wire scnt_f_scanin; | |
433 | wire scnt_f_scanout; | |
434 | wire alloc_ccnt; | |
435 | wire dealloc_ccnt; | |
436 | wire [3:0] ccnt_raw_in; | |
437 | wire ccnt_f_scanin; | |
438 | wire ccnt_f_scanout; | |
439 | wire stb_wait_in; | |
440 | wire rdy_in; | |
441 | wire spec_in; | |
442 | wire vld_d_in; | |
443 | wire specbr_d_in; | |
444 | wire specld_d_in; | |
445 | wire vld_e_in; | |
446 | wire specbr_e_in; | |
447 | wire specld_e_in; | |
448 | wire vld_m_in; | |
449 | wire specld_m_in; | |
450 | wire vld_b_in; | |
451 | wire specld_b_in; | |
452 | wire vld_w_in; | |
453 | wire specld_w_in; | |
454 | wire ready_in; | |
455 | wire readyf_scanin; | |
456 | wire readyf_scanout; | |
457 | wire spec_ready_in; | |
458 | wire spec_readyf_scanin; | |
459 | wire spec_readyf_scanout; | |
460 | wire allds_actual_p; | |
461 | wire allds_p; | |
462 | wire allds_is_p; | |
463 | wire allds_actual_d; | |
464 | wire allds_d; | |
465 | wire allds_is_d; | |
466 | wire allds_p_in; | |
467 | wire allds_p_f_scanin; | |
468 | wire allds_p_f_scanout; | |
469 | wire allds_d_in; | |
470 | wire allds_d_f_scanin; | |
471 | wire allds_d_f_scanout; | |
472 | wire allds_e_in; | |
473 | wire allds_e_f_scanin; | |
474 | wire allds_e_f_scanout; | |
475 | wire set_vld_d; | |
476 | wire clear_vld_d; | |
477 | wire vld_df_scanin; | |
478 | wire vld_df_scanout; | |
479 | wire vld_ef_scanin; | |
480 | wire vld_ef_scanout; | |
481 | wire valid_e; | |
482 | wire valid_e_in; | |
483 | wire valid_ef_scanin; | |
484 | wire valid_ef_scanout; | |
485 | wire vld_mf_scanin; | |
486 | wire vld_mf_scanout; | |
487 | wire flush_m; | |
488 | wire vld_bf_scanin; | |
489 | wire vld_bf_scanout; | |
490 | wire flush_b; | |
491 | wire vld_wf_scanin; | |
492 | wire vld_wf_scanout; | |
493 | wire fpvld_w1_in; | |
494 | wire specfp_w; | |
495 | wire fpvld_w1f_scanin; | |
496 | wire fpvld_w1f_scanout; | |
497 | wire fpvld_w1; | |
498 | wire fpvld_w2_in; | |
499 | wire fpvld_w2f_scanin; | |
500 | wire fpvld_w2f_scanout; | |
501 | wire set_vldraw_d; | |
502 | wire clear_vldraw_d; | |
503 | wire rawflush_d; | |
504 | wire vldraw_d_in; | |
505 | wire vldraw_df_scanin; | |
506 | wire vldraw_df_scanout; | |
507 | wire vldraw_e_in; | |
508 | wire vldraw_ef_scanin; | |
509 | wire vldraw_ef_scanout; | |
510 | wire vldraw_m_in; | |
511 | wire vldraw_mf_scanin; | |
512 | wire vldraw_mf_scanout; | |
513 | wire annul_ds_dcti_mf_scanin; | |
514 | wire annul_ds_dcti_mf_scanout; | |
515 | wire annul_ds_dcti_m; | |
516 | wire vldcnt_e_brtaken0_in; | |
517 | wire vldcnt_e_brtaken1_in; | |
518 | wire vldcnt_m_in; | |
519 | wire vld_f4_in; | |
520 | wire flush_w; | |
521 | wire vld_f4f_scanin; | |
522 | wire vld_f4f_scanout; | |
523 | wire vld_f5_in; | |
524 | wire flush_f4; | |
525 | wire vld_f5f_scanin; | |
526 | wire vld_f5f_scanout; | |
527 | wire vld_fb_in; | |
528 | wire flush_f5; | |
529 | wire vld_fbf_scanin; | |
530 | wire vld_fbf_scanout; | |
531 | wire any_twocycle_p; | |
532 | wire [23:0] data_d_in; | |
533 | wire [23:0] data_d; | |
534 | wire data_df_scanin; | |
535 | wire data_df_scanout; | |
536 | wire any_twocycle_d; | |
537 | wire bkick_d; | |
538 | wire lsu_d; | |
539 | wire fbkick_d; | |
540 | wire specfp_d; | |
541 | wire condbr_d; | |
542 | wire callclass_d; | |
543 | wire annul_d; | |
544 | wire specbr_d; | |
545 | wire specld_m; | |
546 | wire rdf_scanin; | |
547 | wire rdf_scanout; | |
548 | wire anytwocyclef_scanin; | |
549 | wire anytwocyclef_scanout; | |
550 | wire any_twocycle_e; | |
551 | wire specldf_scanin; | |
552 | wire specldf_scanout; | |
553 | wire postsyncf_scanin; | |
554 | wire postsyncf_scanout; | |
555 | wire divf_scanin; | |
556 | wire divf_scanout; | |
557 | wire dctif_scanin; | |
558 | wire dctif_scanout; | |
559 | wire specbref_scanin; | |
560 | wire specbref_scanout; | |
561 | wire specbr_e; | |
562 | wire specbrmf_scanin; | |
563 | wire specbrmf_scanout; | |
564 | wire annulf_scanin; | |
565 | wire annulf_scanout; | |
566 | wire annul_e; | |
567 | wire callclassf_scanin; | |
568 | wire callclassf_scanout; | |
569 | wire callclass_e; | |
570 | wire condbrf_scanin; | |
571 | wire condbrf_scanout; | |
572 | wire condbr_e; | |
573 | wire idestf_scanin; | |
574 | wire idestf_scanout; | |
575 | wire idest_m; | |
576 | wire idest_b; | |
577 | wire fdestf_scanin; | |
578 | wire fdestf_scanout; | |
579 | wire specfpf_scanin; | |
580 | wire specfpf_scanout; | |
581 | wire specfp_e; | |
582 | wire specfp_m; | |
583 | wire specfp_b; | |
584 | wire fbkickf_scanin; | |
585 | wire fbkickf_scanout; | |
586 | wire fbkick_e; | |
587 | wire fbkick_m; | |
588 | wire fbkick_b; | |
589 | wire fbkick_w; | |
590 | wire fbkick_f4; | |
591 | wire fbkick_f5; | |
592 | wire fgu_d_in; | |
593 | wire fguf_scanin; | |
594 | wire fguf_scanout; | |
595 | wire bkickf_scanin; | |
596 | wire bkickf_scanout; | |
597 | wire bkick_e; | |
598 | wire bkick_b; | |
599 | wire fpdest_doublef_scanin; | |
600 | wire fpdest_doublef_scanout; | |
601 | wire fpdest_singlef_scanin; | |
602 | wire fpdest_singlef_scanout; | |
603 | wire fccdestf_scanin; | |
604 | wire fccdestf_scanout; | |
605 | wire lsu_d_in; | |
606 | wire lsuf_scanin; | |
607 | wire lsuf_scanout; | |
608 | wire lsu_e; | |
609 | wire lsu_m; | |
610 | wire lsu_sync_early; | |
611 | wire lsu_sync_in; | |
612 | wire lsu_syncf_scanin; | |
613 | wire lsu_syncf_scanout; | |
614 | wire lsu_sync_raw_in; | |
615 | wire lsu_sync_rawf_scanin; | |
616 | wire lsu_sync_rawf_scanout; | |
617 | wire flush_f3; | |
618 | wire br_mispredict_m_in; | |
619 | wire br_mispredict_mf_scanin; | |
620 | wire br_mispredict_mf_scanout; | |
621 | wire flush_m_in; | |
622 | wire flush_mf_scanin; | |
623 | wire flush_mf_scanout; | |
624 | wire [6:0] i_unused; | |
625 | ||
626 | ||
627 | input tlu_halted; // put thread in halt state by gating off ready signals | |
628 | ||
629 | input dec_block_store_stall; // there is a block store stall in effect at the d stage for this thread | |
630 | ||
631 | input dec_ierr_d; // an inst error has occured at d stage: illegal, parity or ifetch error | |
632 | ||
633 | input tcu_do_mode; | |
634 | ||
635 | input lsu_pku_pmen; // power management enable for pku | |
636 | ||
637 | input spc_core_running_status; // thread is active | |
638 | input lsu_spec_enable; // enable speculation; assume this is serializing (if not pipeline it) | |
639 | ||
640 | input ifu_ibuffer_write_c; // ifu is writing 1 or more instructions into the ibuffers | |
641 | input [31:0] ifu_buf0_inst; // oldest instruction at pick | |
642 | ||
643 | input lsu_stb_alloc; // lsu has allocated store in stb; sent in b_stage; increment ccnt by 1 | |
644 | input lsu_stb_dealloc; // lsu is deallocating store in stb; decrement sscnt,ccnt by 1 | |
645 | input lsu_block_store_kill; // error occured during block store; use this to set scnt=ccnt=0 | |
646 | ||
647 | input [7:0] swl_divide_wait_all; // divide block for all threads (cycle detected) | |
648 | ||
649 | input fgu_divide_completion; // divide completion for any thread | |
650 | ||
651 | ||
652 | //input ibuffer_write; // any write to the ibuffer (C stage) - REMOVED because it didn't make timing | |
653 | ||
654 | input ifu_buf0_valid_p; // ifu_buf0_valid_p for instruction buffer | |
655 | input ifu_upper_buffer_valid_p; // ifu_upper_buffer_valid_p for instruction buffer | |
656 | ||
657 | ||
658 | input pku_raw_pick_p; // unqualified pick for this thread | |
659 | input tlu_flush_ifu; // flush this thread (traps) | |
660 | ||
661 | input tlu_retry_state; // IF the first part of a retry, must let it go even in dcti w/out DS (part of address optimization) | |
662 | input dec_valid_d; // inst is valid at decode for relevant TG | |
663 | input dec_decode_d; // decoded inst at decode for relevant TG | |
664 | ||
665 | input dec_true_valid_e; // take illegals and other exceptions into account | |
666 | ||
667 | input lsu_sync; // lsu needs thread to resync due to dcache_miss, ASI register access, etc. | |
668 | input lsu_complete; // completion of lsu sync event | |
669 | ||
670 | input dec_br_taken_e; // br is taken for e stage (br mispredict) | |
671 | ||
672 | input l2clk; | |
673 | input scan_in; | |
674 | input tcu_pce_ov; // scan signals | |
675 | input spc_aclk; | |
676 | input spc_bclk; | |
677 | input tcu_scan_en; | |
678 | ||
679 | output swl_ready_p; // non-speculative ready state | |
680 | output swl_spec_ready_p; // speculative ready state, past a br or load | |
681 | ||
682 | ||
683 | output [1:0] pku_inst_cnt_brtaken0; // count of inst at e,m,b pipe stages (to dec) | |
684 | output [1:0] pku_inst_cnt_brtaken1; // count of inst at e,m,b pipe stages (to dec) | |
685 | ||
686 | output pku_annul_ds_dcti_brtaken0_e; // the DS of the dcti at e stage is annulled | |
687 | output pku_annul_ds_dcti_brtaken1_e; // the DS of the dcti at e stage is annulled | |
688 | ||
689 | output pku_load_flush_w; // lsu flush to fetch (fetch the npc of the load) | |
690 | ||
691 | output pku_flush_upper_buffer; // flush signals directly off a flop to IB's | |
692 | output pku_flush_buffer0; // kill valid for buffer 0 ALSO force shift of IB's | |
693 | ||
694 | output pku_valid_e; // this thread has a valid instruction at the e stage (to dec) | |
695 | ||
696 | output pku_flush_m; // tell trap to flush m | |
697 | output pku_flush_b; // tell trap to flush b | |
698 | ||
699 | output pku_flush_lm; // flush signals unique to the lsu | |
700 | output pku_flush_lb; | |
701 | ||
702 | output pku_flush_f1; // flush signals unique to the fgu | |
703 | output pku_flush_f2; | |
704 | ||
705 | output pku_ds_e; // the instruction at e stage is a DS | |
706 | ||
707 | output swl_divide_wait; // this thread is waiting on divide; send out to all other threads | |
708 | ||
709 | output swl_cancel_pick_p; // cancel pick of this thread due to hazard | |
710 | ||
711 | output pku_quiesce; // quiesce signal for tlu | |
712 | ||
713 | output scan_out; | |
714 | ||
715 | ||
716 | output pku_lsu_p; // predecodes for the decode unit (for timing) | |
717 | output pku_fgu_p; | |
718 | output pku_pdist_p; | |
719 | output pku_twocycle_p; | |
720 | output pku_idest_p; | |
721 | output pku_fdest_p; | |
722 | output pku_fsrc_rd_p; | |
723 | output pku_isrc_rs1_p; | |
724 | output pku_isrc_rs2_p; | |
725 | output pku_isrc_rd_p; | |
726 | ||
727 | // l1clk: no power management; clock always runs | |
728 | ||
729 | pku_swl_ctl_l1clkhdr_ctl_macro clkgen ( | |
730 | .l1en (1'b1 ), | |
731 | .l1clk(l1clk), | |
732 | .l2clk(l2clk), | |
733 | .pce_ov(pce_ov), | |
734 | .stop(stop), | |
735 | .se(se) | |
736 | ); | |
737 | ||
738 | pku_swl_ctl_spare_ctl_macro__num_4 spares ( | |
739 | .scan_in(spares_scanin), | |
740 | .scan_out(spares_scanout), | |
741 | .l1clk (l1clk), | |
742 | .siclk(siclk), | |
743 | .soclk(soclk) | |
744 | ); | |
745 | ||
746 | // scan renames | |
747 | assign pce_ov = tcu_pce_ov; | |
748 | assign stop = 1'b0; | |
749 | assign siclk = spc_aclk; | |
750 | assign soclk = spc_bclk; | |
751 | assign se = tcu_scan_en; | |
752 | // end scan | |
753 | ||
754 | // all illegals are mapped to this before they are written into the icache | |
755 | assign illegal_p = ~i[31] & ~i[30] & ~i[24] & ~i[23] & ~i[22]; | |
756 | ||
757 | // --- autogenerated by n2decode view=pku Wed Aug 10 15:04:21 CDT 2005 | |
758 | ||
759 | assign isrc_rs1_u = (i[31]&!i[21]&i[20]&!i[19]) | (i[31]&!i[21]&!i[17]&i[16]) | ( | |
760 | i[31]&!i[21]&!i[19]&!i[16]&!i[13]) | (i[31]&!i[22]&!i[20]&!i[19] | |
761 | &!i[13]&!i[12]&!i[6]&!i[5]) | (i[31]&!i[22]&i[20]&!i[12]&!i[11]&!i[10]) | ( | |
762 | i[31]&!i[28]&!i[22]&!i[19]&i[13]) | (i[31]&!i[26]&!i[22]&!i[19]&i[13]) | ( | |
763 | !i[30]&!i[24]&i[23]&i[22]) | (i[31]&i[21]&i[20]&i[19]) | (i[31]&i[22] | |
764 | &!i[20]&i[19]) | (i[31]&i[23]&!i[21]&i[20]) | (!i[30]&i[23]&i[22] | |
765 | &!i[20]) | (i[31]&!i[23]&!i[22]) | (i[31]&!i[24]) | (i[31]&i[30]) | ( | |
766 | i[31]&i[19]&!i[9]&i[7]); | |
767 | ||
768 | assign isrc_rs2_u = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&!i[22]&!i[21] | |
769 | &!i[19]&!i[13]) | (i[31]&i[23]&i[22]&!i[21]&!i[13]) | (i[31]&i[23] | |
770 | &i[22]&!i[20]&!i[13]) | (i[31]&!i[22]&i[20]&!i[13]&!i[12]&!i[11] | |
771 | &!i[10]) | (i[31]&!i[23]&i[21]&!i[13]) | (i[31]&i[30]&!i[13]) | ( | |
772 | i[31]&!i[24]&!i[13]) | (i[31]&!i[23]&!i[22]&!i[13]); | |
773 | ||
774 | assign isrc_rd_u = (i[31]&i[30]&i[22]&i[21]&i[20]) | (i[31]&i[30]&i[22]&i[21] | |
775 | &!i[19]) | (i[31]&i[30]&!i[24]&!i[22]&i[21]); | |
776 | ||
777 | assign idest_u = (i[31]&!i[30]&!i[23]&i[20]&!i[19]) | (i[31]&!i[30]&!i[23]&!i[19] | |
778 | &!i[17]) | (i[31]&!i[30]&!i[23]&!i[20]&i[19]) | (i[31]&!i[30]&!i[13] | |
779 | &!i[11]&!i[10]&i[9]) | (i[31]&!i[30]&!i[22]&i[21]&i[20]&!i[12]&!i[11] | |
780 | &!i[9]) | (i[31]&!i[30]&i[22]&i[21]&i[16]) | (i[30]&i[24]&i[22]&!i[19]) | ( | |
781 | i[30]&!i[24]&i[22]&i[19]) | (i[31]&!i[30]&!i[23]&!i[19]&!i[16]) | ( | |
782 | i[30]&!i[24]&!i[21]) | (i[24]&i[23]&i[22]&!i[20]&!i[19]) | (i[31] | |
783 | &!i[30]&i[22]&i[21]&i[19]) | (!i[30]&!i[23]&!i[22]) | (i[31]&!i[30] | |
784 | &!i[24]) | (!i[31]&i[30]); | |
785 | ||
786 | assign fsrc_rs1_u = (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[7]&!i[6]) | ( | |
787 | i[31]&!i[30]&!i[13]&!i[12]&i[9]&!i[8]&i[5]) | (i[31]&!i[30]&i[20] | |
788 | &!i[13]&i[10]&!i[9]&i[8]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[9] | |
789 | &i[8]&!i[5]) | (i[31]&!i[30]&!i[19]&!i[13]&i[11]&i[10]&i[7]&!i[6]) | ( | |
790 | i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[7]&i[6]) | (i[31]&!i[30]&i[20] | |
791 | &!i[19]&!i[13]&!i[11]&i[10]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[20] | |
792 | &!i[19]&!i[13]&!i[12]&i[11]) | (i[31]&!i[30]&!i[13]&!i[12]&i[11]&i[9] | |
793 | &!i[8]); | |
794 | ||
795 | assign fsrc_rs2_u = (i[31]&!i[30]&!i[13]&i[11]&i[8]&!i[6]) | (i[31]&!i[30]&!i[13] | |
796 | &i[11]&!i[8]&i[6]) | (i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[7]) | (i[31] | |
797 | &!i[30]&!i[13]&i[11]&!i[9]&i[7]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11] | |
798 | &!i[10]) | (i[31]&!i[30]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30] | |
799 | &i[24]&i[23]&!i[22]&i[21]&!i[20]); | |
800 | ||
801 | assign fsrc_rd_u = (i[31]&i[30]&i[24]&!i[22]&i[21]&!i[19]) | (i[31]&i[30]&i[24] | |
802 | &i[21]&i[20]&i[19]); | |
803 | ||
804 | assign fdest_u = (i[31]&!i[30]&!i[13]&i[10]&i[9]) | (i[31]&!i[30]&i[24]&i[23] | |
805 | &!i[22]&i[21]&!i[20]&!i[9]) | (i[31]&!i[30]&!i[22]&!i[19]&!i[13] | |
806 | &i[11]) | (i[31]&i[30]&i[24]&!i[21]&i[20]) | (i[31]&i[30]&i[24]&!i[21] | |
807 | &!i[19]); | |
808 | ||
809 | assign fgu_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]) | ( | |
810 | i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30]&!i[22] | |
811 | &!i[13]&i[11]) | (i[31]&!i[30]&!i[22]&!i[13]&i[10]) | (i[31]&!i[30] | |
812 | &i[22]&i[21]&!i[20]&i[19]) | (i[31]&!i[30]&i[24]&i[23]&i[21]&!i[20]) | ( | |
813 | i[31]&i[30]&i[24]&!i[22]&i[21]) | (i[31]&!i[30]&!i[24]&i[22]&i[19]) | ( | |
814 | i[31]&!i[30]&!i[24]&i[22]&i[20]) | (i[31]&i[24]&!i[22]&i[21]&!i[20] | |
815 | &!i[19]); | |
816 | ||
817 | assign dcti_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[23]) | (!i[31] | |
818 | &i[22]) | (!i[31]&i[30]); | |
819 | ||
820 | assign specbr_u = (!i[31]&!i[30]&i[22]) | (!i[31]&!i[30]&i[23]); | |
821 | ||
822 | assign specld_u = (i[31]&i[30]&!i[21]); | |
823 | ||
824 | assign specfp_u = (i[31]&!i[30]&!i[13]&i[12]&i[5]) | (i[31]&!i[30]&!i[13]&i[10] | |
825 | &i[9]) | (i[31]&!i[30]&!i[22]&!i[13]&i[11]) | (i[31]&!i[30]&i[24] | |
826 | &i[23]&!i[22]&i[21]&!i[20]); | |
827 | ||
828 | assign lsu_u = (i[31]&i[24]&!i[23]&i[22]&i[20]&!i[19]&i[16]) | (i[31]&i[24] | |
829 | &!i[23]&i[22]&!i[21]&!i[17]&i[16]) | (i[31]&i[24]&!i[23]&i[22]&!i[21] | |
830 | &!i[20]&i[19]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&!i[19]&!i[16]) | ( | |
831 | i[31]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | (i[31]&!i[28]&i[24]&i[23] | |
832 | &!i[22]&!i[21]&!i[19]) | (i[31]&i[24]&i[23]&i[20]&i[19]) | (i[31] | |
833 | &i[29]&i[24]&i[23]&!i[22]&!i[21]) | (i[31]&i[24]&!i[23]&i[22]&!i[21] | |
834 | &i[1]) | (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[5]) | (i[31]&i[24]&!i[23] | |
835 | &i[22]&!i[21]&i[6]) | (i[31]&i[30]); | |
836 | ||
837 | assign postsync_u = (i[31]&i[24]&i[22]&!i[21]&!i[20]&i[6]) | (i[31]&i[24]&i[22] | |
838 | &!i[21]&!i[20]&i[5]) | (i[31]&i[24]&i[22]&!i[21]&!i[20]&i[1]) | ( | |
839 | i[31]&i[24]&i[22]&!i[21]&!i[20]&!i[17]) | (i[31]&i[24]&i[22]&!i[21] | |
840 | &!i[20]&!i[15]) | (i[31]&i[24]&i[20]&!i[19]&!i[13]&!i[11]&i[10]&!i[9]) | ( | |
841 | i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[21]&!i[20]) | (i[24]&i[23]&i[22] | |
842 | &i[21]) | (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[21]&!i[20]) | (i[31] | |
843 | &!i[30]&i[24]&!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (i[31]&!i[30] | |
844 | &i[24]&i[23]&!i[22]&!i[21]&i[20]) | (i[31]&i[24]&!i[23]&i[22]&i[20] | |
845 | &!i[19]) | (i[24]&i[23]&i[22]&!i[20]) | (i[31]&!i[30]&i[22]&!i[21] | |
846 | &i[19]) | (i[30]&i[24]&!i[20]&i[19]) | (i[30]&i[22]&i[21]&i[19]) | ( | |
847 | i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[20]) | (!i[31]&i[30]); | |
848 | ||
849 | assign div_u = (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[11]&i[10]) | (i[31]&!i[30] | |
850 | &!i[20]&!i[13]&i[8]&i[7]) | (i[31]&!i[30]&!i[23]&i[22]&i[21]&!i[20] | |
851 | &i[19]) | (i[31]&!i[30]&!i[24]&i[22]&i[21]&i[20]); | |
852 | ||
853 | assign pdist_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]); | |
854 | ||
855 | assign condbr_u = (!i[31]&!i[30]&i[27]&i[22]) | (!i[31]&!i[30]&i[25]&i[22]) | ( | |
856 | !i[31]&!i[30]&i[26]&i[22]) | (!i[31]&!i[30]&i[27]&i[23]) | (!i[31] | |
857 | &!i[30]&i[25]&i[23]) | (!i[31]&!i[30]&i[26]&i[23]); | |
858 | ||
859 | assign callclass_u = (i[24]&i[23]&i[22]&!i[21]&!i[20]) | (!i[31]&i[30]); | |
860 | ||
861 | assign fccsrc_u = (!i[30]&i[24]&i[23]&!i[22]&i[21]&i[19]&!i[13]&!i[9]&!i[7]) | ( | |
862 | !i[30]&i[24]&!i[23]&i[22]&i[21]&!i[20]&!i[19]&!i[18]) | (!i[31]&!i[30] | |
863 | &i[24]&i[23]) | (!i[31]&!i[30]&i[24]&i[22]); | |
864 | ||
865 | assign fsrsync_u = (i[31]&!i[30]&!i[13]&!i[11]&i[9]&i[8]&i[7]&!i[5]) | (i[31] | |
866 | &i[30]&i[24]&!i[22]&!i[20]&i[19]); | |
867 | ||
868 | assign twocycle_u = (i[31]&i[30]&i[24]&i[22]&!i[19]) | (i[31]&i[30]&!i[24]&!i[22] | |
869 | &i[21]&i[20]&i[19]); | |
870 | ||
871 | assign bkick_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&i[19]) | (i[31]&i[24] | |
872 | &i[23]&!i[21]&!i[20]&i[19]) | (i[31]&i[30]&i[24]&!i[22]&!i[20]&i[19]); | |
873 | ||
874 | assign fbkick_u = (i[31]&!i[30]&i[20]&!i[19]&!i[13]&!i[11]&i[10]&!i[9]) | ( | |
875 | i[31]&i[24]&!i[23]&i[22]&i[21]&i[20]&!i[19]) | (i[31]&!i[30]&i[24] | |
876 | &!i[23]&!i[22]&i[21]&!i[20]&!i[19]) | (!i[30]&i[24]&i[23]&i[22]&i[21] | |
877 | &!i[20]) | (i[31]&!i[30]&!i[24]&i[22]&!i[21]&i[19]) | (i[31]&!i[30] | |
878 | &!i[24]&i[22]&!i[21]&i[20]); | |
879 | ||
880 | assign fccdest_u = (i[31]&!i[30]&i[19]&!i[13]&i[9]); | |
881 | ||
882 | assign fpdest_single_u = (i[31]&!i[30]&!i[19]&!i[13]&i[12]&i[7]) | (i[31]&!i[30] | |
883 | &!i[13]&i[9]&i[8]&i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[9]&i[8]&i[7] | |
884 | &i[5]) | (i[31]&!i[30]&!i[20]&!i[13]&!i[11]&i[10]&i[5]) | (i[31] | |
885 | &!i[30]&!i[22]&!i[19]&!i[13]&i[12]&i[11]&!i[8]) | (i[31]&!i[30]&!i[19] | |
886 | &!i[13]&i[11]&!i[8]&i[5]) | (i[31]&i[24]&i[23]&!i[22]&!i[20]&i[19] | |
887 | &!i[9]&i[5]) | (i[31]&!i[30]&!i[20]&!i[19]&!i[13]&!i[12]&!i[10]&i[5]) | ( | |
888 | i[31]&!i[30]&i[20]&!i[13]&i[11]&i[10]&i[5]) | (i[31]&i[30]&i[24] | |
889 | &!i[22]&!i[19]); | |
890 | ||
891 | assign fpdest_double_u = (i[31]&!i[30]&!i[22]&!i[20]&!i[19]&!i[13]&i[12]&!i[9] | |
892 | &!i[7]) | (i[31]&!i[30]&i[19]&!i[13]&i[9]) | (i[31]&!i[30]&!i[20] | |
893 | &!i[19]&!i[13]&i[11]&i[10]) | (i[31]&i[24]&!i[22]&i[19]&!i[13]&i[6]) | ( | |
894 | i[31]&!i[30]&!i[13]&i[10]&i[9]&!i[5]) | (i[31]&!i[30]&!i[13]&!i[11] | |
895 | &i[10]&i[9]&!i[7]&!i[6]) | (i[31]&!i[30]&i[20]&!i[13]&i[11]&!i[10] | |
896 | &i[8]) | (i[31]&!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[8]) | (i[31]&!i[30] | |
897 | &i[24]&i[23]&!i[22]&i[21]&!i[20]&!i[11]&i[6]) | (i[31]&i[30]&i[24] | |
898 | &i[20]&i[19]) | (i[31]&!i[30]&!i[22]&!i[13]&!i[12]&i[11]&!i[5]); | |
899 | ||
900 | assign fpsrc_single_u = (i[31]&!i[30]&!i[22]&!i[13]&i[12]&i[11]&!i[6]) | (i[31] | |
901 | &!i[30]&!i[13]&!i[11]&i[10]&i[9]&!i[6]&!i[5]) | (i[31]&!i[30]&!i[13] | |
902 | &i[10]&i[8]&!i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[8]&i[6] | |
903 | &i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[7]&i[6]&i[5]) | (i[31]&!i[30] | |
904 | &!i[13]&i[10]&!i[8]&i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11] | |
905 | &i[7]&!i[6]&i[5]) | (i[31]&!i[30]&!i[13]&i[11]&!i[9]&i[8]&i[5]) | ( | |
906 | i[31]&!i[30]&!i[13]&i[9]&!i[8]&!i[7]&i[5]) | (i[31]&i[24]&i[23]&!i[22] | |
907 | &i[21]&!i[20]&i[5]) | (i[31]&i[30]&i[24]&!i[22]&!i[19]); | |
908 | ||
909 | assign fpsrc_double_u = (i[31]&!i[30]&!i[13]&!i[11]&i[8]&i[7]) | (i[31]&!i[30] | |
910 | &!i[13]&!i[11]&i[10]&i[8]&i[6]) | (i[31]&!i[30]&!i[13]&i[10]&!i[9] | |
911 | &i[8]&!i[5]) | (i[31]&!i[30]&!i[22]&!i[13]&!i[11]&i[10]&!i[8]&!i[7] | |
912 | &!i[6]) | (i[31]&!i[30]&!i[13]&i[10]&i[7]&!i[6]&!i[5]) | (i[31]&!i[30] | |
913 | &i[20]&!i[13]&i[11]&i[8]&!i[6]&!i[5]) | (i[31]&!i[30]&!i[13]&!i[11] | |
914 | &i[10]&i[7]&i[6]) | (i[31]&!i[30]&!i[13]&i[10]&!i[7]&i[6]&!i[5]) | ( | |
915 | i[31]&!i[30]&!i[13]&i[11]&i[9]&!i[8]&!i[5]) | (i[31]&!i[30]&!i[13] | |
916 | &i[11]&!i[9]&i[6]&!i[5]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&i[21] | |
917 | &!i[20]&!i[11]&!i[5]) | (i[31]&i[30]&i[24]&i[20]&i[19]); | |
918 | ||
919 | assign store_u = (i[31]&!i[30]&!i[26]&i[24]&i[23]&!i[22]&!i[21]&!i[19]) | ( | |
920 | i[31]&i[30]&i[21]&!i[19]) | (i[31]&!i[30]&!i[28]&i[24]&i[23]&!i[22] | |
921 | &!i[21]&!i[19]) | (i[31]&!i[30]&i[24]&i[23]&!i[22]&!i[21]&i[20]) | ( | |
922 | i[31]&i[30]&!i[22]&i[21]) | (i[31]&i[30]&!i[24]&i[21]); | |
923 | ||
924 | assign windowsync_u = (i[31]&i[24]&!i[23]&i[22]&!i[21]&i[20]&i[19]) | (!i[30] | |
925 | &i[24]&i[23]&i[22]&i[21]&!i[20]) | (!i[30]&i[24]&i[23]&i[22]&!i[20] | |
926 | &i[19]); | |
927 | ||
928 | // end autogeneration | |
929 | ||
930 | ||
931 | assign pku_isrc_rs1_p = isrc_rs1_u & ~illegal_p; | |
932 | assign pku_isrc_rs2_p = isrc_rs2_u & ~illegal_p; | |
933 | assign pku_isrc_rd_p = isrc_rd_u & ~illegal_p; | |
934 | assign pku_idest_p = idest_u & ~illegal_p; | |
935 | assign fsrc_rs1_p = fsrc_rs1_u & ~illegal_p; | |
936 | assign fsrc_rs2_p = fsrc_rs2_u & ~illegal_p; | |
937 | assign pku_fsrc_rd_p = fsrc_rd_u & ~illegal_p; | |
938 | assign pku_fdest_p = fdest_u & ~illegal_p; | |
939 | assign pku_fgu_p = fgu_u & ~illegal_p; | |
940 | assign dcti_p = dcti_u & ~illegal_p; | |
941 | assign specbr_p = specbr_u & ~illegal_p; | |
942 | assign specld_p = specld_u & ~illegal_p; | |
943 | assign specfp_p = specfp_u & ~illegal_p; | |
944 | assign pku_lsu_p = lsu_u & ~illegal_p; | |
945 | assign postsync_p = postsync_u & ~do_mode_f & ~illegal_p; | |
946 | assign div_p = div_u & ~illegal_p; | |
947 | assign pku_pdist_p = pdist_u & ~illegal_p; | |
948 | assign condbr_p = condbr_u & ~illegal_p; | |
949 | assign callclass_p = callclass_u & ~illegal_p; | |
950 | assign fccsrc_p = fccsrc_u & ~illegal_p; | |
951 | assign fsrsync_p = fsrsync_u & ~illegal_p; | |
952 | assign pku_twocycle_p = twocycle_u & ~illegal_p; | |
953 | assign bkick_p = bkick_u & ~illegal_p; | |
954 | assign fbkick_p = fbkick_u & ~illegal_p; | |
955 | assign fccdest_p = fccdest_u & ~illegal_p; | |
956 | assign fpdest_single_p = fpdest_single_u & ~fsrc_rd_u & ~illegal_p; // store-floats don't have a fpdest | |
957 | assign fpdest_double_p = fpdest_double_u & ~fsrc_rd_u & ~illegal_p; | |
958 | assign fpsrc_single_p = fpsrc_single_u & ~illegal_p; | |
959 | assign fpsrc_double_p = fpsrc_double_u & ~illegal_p; | |
960 | assign store_p = store_u & ~illegal_p; | |
961 | assign windowsync_p = windowsync_u & ~illegal_p; | |
962 | ||
963 | pku_swl_ctl_msff_ctl_macro__width_1 do_modef ( | |
964 | .scan_in(do_modef_scanin), | |
965 | .scan_out(do_modef_scanout), | |
966 | .l1clk(l1clk_pm1), | |
967 | .din (tcu_do_mode), | |
968 | .dout (do_mode_f), | |
969 | .siclk(siclk), | |
970 | .soclk(soclk) | |
971 | ); | |
972 | ||
973 | ||
974 | ||
975 | assign i[31:0] = ifu_buf0_inst[31:0]; | |
976 | ||
977 | assign rs1[4:0] = i[18:14]; | |
978 | assign rs2[4:0] = i[4:0]; | |
979 | assign rd[4:0] = i[29:25]; | |
980 | ||
981 | assign annul = i[29]; | |
982 | ||
983 | // instruction buffers will be flushing this cycle; qualify input valids for this flush cycle | |
984 | assign vld_p = ifu_buf0_valid_p & ~pku_flush_buffer0; | |
985 | assign vld_1 = ifu_upper_buffer_valid_p & ~pku_flush_upper_buffer; | |
986 | ||
987 | // quiesce signal | |
988 | ||
989 | assign valid = (ifu_buf0_valid_p | vld_d | vld_e | vld_m | vld_b | vld_w | | |
990 | vld_f4 | vld_f5 | vld_fb | | |
991 | swl_divide_wait | lsu_sync_wait); | |
992 | ||
993 | assign pku_quiesce = ~valid; | |
994 | ||
995 | // l1clk_pm2: fine grain power management; shut down clocks whenver pick is idle | |
996 | ||
997 | assign pick_clken = (((ifu_buf0_valid_p & (swl_ready_p | swl_spec_ready_p)) | // valid inst and ready to pick | |
998 | vldraw_d | vldraw_e | vldraw_m | // must get inst cnts right | |
999 | vld_d | vld_e | vld_m | vld_b | vld_w | | |
1000 | vld_f4 | vld_f5 | vld_fb | // clock fgu ops down the pipe | |
1001 | ext_flush) & thread_active) | ~lsu_pku_pmen; | |
1002 | ||
1003 | pku_swl_ctl_l1clkhdr_ctl_macro clkgenpm ( | |
1004 | .l1en (pick_clken ), | |
1005 | .l1clk(l1clk_pm2), | |
1006 | .l2clk(l2clk), | |
1007 | .pce_ov(pce_ov), | |
1008 | .stop(stop), | |
1009 | .se(se) | |
1010 | ); | |
1011 | ||
1012 | // l1clk_pm1: coarse grain power management; shut down clocks if thread is not active | |
1013 | ||
1014 | assign active_clken = thread_active | ~lsu_pku_pmen; | |
1015 | ||
1016 | pku_swl_ctl_l1clkhdr_ctl_macro clkgenactive ( | |
1017 | .l1en (active_clken ), | |
1018 | .l1clk(l1clk_pm1), | |
1019 | .l2clk(l2clk), | |
1020 | .pce_ov(pce_ov), | |
1021 | .stop(stop), | |
1022 | .se(se) | |
1023 | ); | |
1024 | ||
1025 | ||
1026 | pku_swl_ctl_msff_ctl_macro__width_1 external_flushf ( | |
1027 | .scan_in(external_flushf_scanin), | |
1028 | .scan_out(external_flushf_scanout), | |
1029 | .l1clk(l1clk_pm1), | |
1030 | .din (tlu_flush_ifu), | |
1031 | .dout (ext_flush), | |
1032 | .siclk(siclk), | |
1033 | .soclk(soclk) | |
1034 | ); | |
1035 | ||
1036 | assign lsu_ext_flush_in = tlu_flush_ifu | lsu_sync; | |
1037 | ||
1038 | pku_swl_ctl_msff_ctl_macro__width_1 lsu_ext_flushf ( | |
1039 | .scan_in(lsu_ext_flushf_scanin), | |
1040 | .scan_out(lsu_ext_flushf_scanout), | |
1041 | .l1clk(l1clk_pm1), | |
1042 | .din (lsu_ext_flush_in), | |
1043 | .dout (lsu_ext_flush_w), | |
1044 | .siclk(siclk), | |
1045 | .soclk(soclk) | |
1046 | ); | |
1047 | ||
1048 | // 0in bits_on -var swl_divide_wait_all[7:0] -max 2 | |
1049 | assign divide_wait_outstanding = |swl_divide_wait_all[7:0]; | |
1050 | ||
1051 | ||
1052 | // dependency logic to prevent fpdest_single followed by fpsrc_double | |
1053 | // no way to bypass partial result | |
1054 | ||
1055 | assign fpdouble_wait = (fpsrc_double_p & vld_d & fpdest_single_d) | | |
1056 | (fpsrc_double_p & vld_e & fpdest_single_e) | | |
1057 | (fpsrc_double_p & vld_m & fpdest_single_m) | | |
1058 | (fpsrc_double_p & vld_b & ~lsu_b & fpdest_single_b) | // no lsu hazards past b | |
1059 | (fpsrc_double_p & vld_w & ~lsu_w & fpdest_single_w) | | |
1060 | (fpsrc_double_p & vld_f4 & ~lsu_f4 & fpdest_single_f4); | |
1061 | ||
1062 | assign fpdouble_cancel = fpdouble_wait | | |
1063 | (fpsrc_double_p & vld_b & lsu_b & fpdest_single_b) | // if fpdest is load at b, cancel | |
1064 | (fpsrc_double_p & vld_f5 & ~lsu_f5 & fpdest_single_f5); | |
1065 | ||
1066 | // dependency logic to prevent fpdest_double followed by fpsrc_single | |
1067 | // don't want to deal with unscrambling the FP sources and destinations | |
1068 | ||
1069 | assign fpsingle_wait = (fpsrc_single_p & vld_d & fpdest_double_d) | | |
1070 | (fpsrc_single_p & vld_e & fpdest_double_e) | | |
1071 | (fpsrc_single_p & vld_m & fpdest_double_m) | | |
1072 | (fpsrc_single_p & vld_b & ~lsu_b & fpdest_double_b) | // no lsu hazards past b | |
1073 | (fpsrc_single_p & vld_w & ~lsu_w & fpdest_double_w) | | |
1074 | (fpsrc_single_p & vld_f4 & ~lsu_f4 & fpdest_double_f4); | |
1075 | ||
1076 | assign fpsingle_cancel = fpsingle_wait | | |
1077 | (fpsrc_single_p & vld_b & lsu_b & fpdest_double_b) | // if fpdest is load at b, cancel | |
1078 | (fpsrc_single_p & vld_f5 & ~lsu_f5 & fpdest_double_f5); | |
1079 | ||
1080 | // dependency logic for fcc : fbfcc, movcc, fmovcc | |
1081 | // FGU sends fcc's during F3/W stage; decode has 2 flop stages before E stage | |
1082 | assign fccdep_wait = (fccsrc_p & vld_d & fccdest_d) | | |
1083 | (fccsrc_p & vld_e & fccdest_e) | | |
1084 | (fccsrc_p & vld_m & fccdest_m); | |
1085 | ||
1086 | assign fccdep_cancel = fccdep_wait | | |
1087 | (fccsrc_p & vld_b & fccdest_b); | |
1088 | ||
1089 | // presync logic for ldfsr, stfsr (wait for all fgu op to advance past f5) | |
1090 | // ldfsr has same presync timing as stfsr | |
1091 | assign fsrsync_wait = (fsrsync_p & vld_d & fgu_d) | // wait on all fgus (including loads, fgu ints) | |
1092 | (fsrsync_p & vld_e & fgu_e) | | |
1093 | (fsrsync_p & vld_m & fgu_m) | | |
1094 | (fsrsync_p & vld_b & fgu_b) | | |
1095 | (fsrsync_p & vld_w & fgu_w) | | |
1096 | (fsrsync_p & vld_f4); | |
1097 | ||
1098 | assign fsrsync_cancel = fsrsync_wait | | |
1099 | (fsrsync_p & vld_f5); | |
1100 | ||
1101 | // fgu_op with dest { fgu fdest } | |
1102 | // load-int { lsu specld } | |
1103 | // load-float or fgu_op { fdest } | |
1104 | ||
1105 | // integer sources (rs1,rs2,rd) check against integer loads | |
1106 | // float sources (rs1,rs2,rd) check against float-loads and fgu_ops | |
1107 | // float loads have WAW hazard with prior fgu ops | |
1108 | ||
1109 | // dependency checking for integer and floats | |
1110 | assign check_rs1_d = (idest_d & specld_d & pku_isrc_rs1_p) | // check int rs1 VS int_load_d | |
1111 | (fdest_d & fsrc_rs1_p); // check fp rs1 VS fgu_op_d OR fgu_load_d | |
1112 | assign check_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) | // rs2 same as rs1 | |
1113 | (fdest_d & fsrc_rs2_p); | |
1114 | assign check_rd_d = (idest_d & specld_d & pku_isrc_rd_p) | // check int store VS prior int load | |
1115 | (fdest_d & pku_fsrc_rd_p) | // check fp store VS prior fgu_op OR fgu_load | |
1116 | (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p); // check float-load VS prior fgu_op WAW | |
1117 | ||
1118 | assign check_rs1_e = (idest_e & specld_e & pku_isrc_rs1_p) | // check int rs1 VS int_load_e | |
1119 | (fdest_e & fgu_e & fsrc_rs1_p ); // check fp rs1 VS fgu_op_e | |
1120 | assign check_rs2_e = (idest_e & specld_e & pku_isrc_rs2_p) | | |
1121 | (fdest_e & fgu_e & fsrc_rs2_p ); | |
1122 | assign check_rd_e = (idest_e & specld_e & pku_isrc_rd_p) | | |
1123 | (fdest_e & fgu_e & pku_fsrc_rd_p) | // check fp store VS prior fgu_op | |
1124 | (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p); // WAW | |
1125 | ||
1126 | assign check_rs1_m = (fdest_m & fgu_m & fsrc_rs1_p); // check fp rs1 VS fgu_op_m | |
1127 | assign check_rs2_m = (fdest_m & fgu_m & fsrc_rs2_p); | |
1128 | assign check_rd_m = (fdest_m & fgu_m & pku_fsrc_rd_p) | | |
1129 | (fdest_m & fgu_m & pku_fdest_p & pku_lsu_p); // WAW, load-float write delay one cycle so release after m stage | |
1130 | ||
1131 | assign check_rs1_b = (fdest_b & fgu_b & fsrc_rs1_p); // check fp rs1 VS fgu_op_b | |
1132 | assign check_rs2_b = (fdest_b & fgu_b & fsrc_rs2_p); | |
1133 | assign check_rd_b = (fdest_b & fgu_b & pku_fsrc_rd_p); | |
1134 | ||
1135 | assign check_rs1_w = (fdest_w & fgu_w & fsrc_rs1_p); // check fp rs1 VS fgu_op_w | |
1136 | assign check_rs2_w = (fdest_w & fgu_w & fsrc_rs2_p); | |
1137 | assign check_rd_w = (fdest_w & fgu_w & pku_fsrc_rd_p); | |
1138 | ||
1139 | assign cmp_rs1_rd_d = (rs1[4:0] == rd_d[4:0]); | |
1140 | assign cmp_rs2_rd_d = (rs2[4:0] == rd_d[4:0]); | |
1141 | assign cmp_rd_rd_d = ( rd[4:0] == rd_d[4:0]); | |
1142 | assign cmp_rs1_rd_e = (rs1[4:0] == rd_e[4:0]); | |
1143 | assign cmp_rs2_rd_e = (rs2[4:0] == rd_e[4:0]); | |
1144 | assign cmp_rd_rd_e = ( rd[4:0] == rd_e[4:0]); | |
1145 | assign cmp_rs1_rd_m = (rs1[4:0] == rd_m[4:0]); | |
1146 | assign cmp_rs2_rd_m = (rs2[4:0] == rd_m[4:0]); | |
1147 | assign cmp_rd_rd_m = ( rd[4:0] == rd_m[4:0]); | |
1148 | assign cmp_rs1_rd_b = (rs1[4:0] == rd_b[4:0]); | |
1149 | assign cmp_rs2_rd_b = (rs2[4:0] == rd_b[4:0]); | |
1150 | assign cmp_rd_rd_b = ( rd[4:0] == rd_b[4:0]); | |
1151 | assign cmp_rs1_rd_w = (rs1[4:0] == rd_w[4:0]); | |
1152 | assign cmp_rs2_rd_w = (rs2[4:0] == rd_w[4:0]); | |
1153 | assign cmp_rd_rd_w = ( rd[4:0] == rd_w[4:0]); | |
1154 | ||
1155 | // dependency checking is independent of enable/disable of speculation | |
1156 | assign dependent_cancel = ((cmp_rs1_rd_d & vld_d & check_rs1_d) | | |
1157 | (cmp_rs2_rd_d & vld_d & check_rs2_d) | | |
1158 | (cmp_rd_rd_d & vld_d & check_rd_d) | | |
1159 | (cmp_rs1_rd_e & vld_e & check_rs1_e) | | |
1160 | (cmp_rs2_rd_e & vld_e & check_rs2_e) | | |
1161 | (cmp_rd_rd_e & vld_e & check_rd_e) | | |
1162 | (cmp_rs1_rd_m & vld_m & check_rs1_m) | | |
1163 | (cmp_rs2_rd_m & vld_m & check_rs2_m) | | |
1164 | (cmp_rd_rd_m & vld_m & check_rd_m) | | |
1165 | (cmp_rs1_rd_b & vld_b & check_rs1_b) | | |
1166 | (cmp_rs2_rd_b & vld_b & check_rs2_b) | | |
1167 | (cmp_rd_rd_b & vld_b & check_rd_b) | | |
1168 | (cmp_rs1_rd_w & vld_w & check_rs1_w) | | |
1169 | (cmp_rs2_rd_w & vld_w & check_rs2_w) | | |
1170 | (cmp_rd_rd_w & vld_w & check_rd_w)); | |
1171 | ||
1172 | // wait exits 1 pipe stage earlier than the dependency logic | |
1173 | // * is the differences | |
1174 | // | |
1175 | // assign check_rs1_d = (idest_d & specld_d & pku_isrc_rs1_p) | | |
1176 | // (fdest_d & *fgu_d & fsrc_rs1_p); | |
1177 | // assign check_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) | | |
1178 | // (fdest_d & *fgu_d & fsrc_rs2_p); | |
1179 | // assign check_rd_d = (idest_d & specld_d & pku_isrc_rd_p) | | |
1180 | // (fdest_d & *fgu_d & pku_fsrc_rd_p) | | |
1181 | // (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p); | |
1182 | // | |
1183 | // assign check_rs1_e = * | |
1184 | // (fdest_e & fgu_e & fsrc_rs1_p ); | |
1185 | // assign check_rs2_e = * | |
1186 | // (fdest_e & fgu_e & fsrc_rs2_p ); | |
1187 | // assign check_rd_e = * | |
1188 | // (fdest_e & fgu_e & pku_fsrc_rd_p) | | |
1189 | // (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p); | |
1190 | // | |
1191 | // assign check_rs1_m = (fdest_m & fgu_m & fsrc_rs1_p); | |
1192 | // assign check_rs2_m = (fdest_m & fgu_m & fsrc_rs2_p); | |
1193 | // assign check_rd_m = (fdest_m & fgu_m & pku_fsrc_rd_p) | | |
1194 | // * | |
1195 | // | |
1196 | // assign check_rs1_b = (fdest_b & fgu_b & fsrc_rs1_p); | |
1197 | // assign check_rs2_b = (fdest_b & fgu_b & fsrc_rs2_p); | |
1198 | // assign check_rd_b = (fdest_b & fgu_b & pku_fsrc_rd_p); | |
1199 | // | |
1200 | // | |
1201 | // assign check_rs1_w = * | |
1202 | // assign check_rs2_w = * | |
1203 | // assign check_rd_w = * | |
1204 | ||
1205 | // fgu loads don't goto wait | |
1206 | // integer loads don't look at E stage to stay in wait | |
1207 | // fgus dont look at W stage to stay in wait | |
1208 | // fgu WAW dont look at B stage | |
1209 | ||
1210 | assign wait_rs1_d = (idest_d & specld_d & pku_isrc_rs1_p) | | |
1211 | (fdest_d & fgu_d & fsrc_rs1_p); | |
1212 | assign wait_rs2_d = (idest_d & specld_d & pku_isrc_rs2_p) | | |
1213 | (fdest_d & fgu_d & fsrc_rs2_p); | |
1214 | assign wait_rd_d = (idest_d & specld_d & pku_isrc_rd_p) | | |
1215 | (fdest_d & fgu_d & pku_fsrc_rd_p) | | |
1216 | (fdest_d & fgu_d & pku_fdest_p & pku_lsu_p); | |
1217 | ||
1218 | assign wait_rs1_e = (fdest_e & fgu_e & fsrc_rs1_p); | |
1219 | assign wait_rs2_e = (fdest_e & fgu_e & fsrc_rs2_p); | |
1220 | assign wait_rd_e = (fdest_e & fgu_e & pku_fsrc_rd_p) | | |
1221 | (fdest_e & fgu_e & pku_fdest_p & pku_lsu_p); | |
1222 | ||
1223 | assign wait_rd_m = (fdest_m & fgu_m & pku_fsrc_rd_p); | |
1224 | ||
1225 | assign wait_rd_b = (fdest_b & fgu_b & pku_fsrc_rd_p); | |
1226 | ||
1227 | assign dependent_wait = | |
1228 | (cmp_rs1_rd_d & vld_d & wait_rs1_d) | | |
1229 | (cmp_rs2_rd_d & vld_d & wait_rs2_d) | | |
1230 | (cmp_rd_rd_d & vld_d & wait_rd_d) | | |
1231 | (cmp_rs1_rd_e & vld_e & wait_rs1_e) | | |
1232 | (cmp_rs2_rd_e & vld_e & wait_rs2_e) | | |
1233 | (cmp_rd_rd_e & vld_e & wait_rd_e) | | |
1234 | (cmp_rs1_rd_m & vld_m & check_rs1_m) | | |
1235 | (cmp_rs2_rd_m & vld_m & check_rs2_m) | | |
1236 | (cmp_rd_rd_m & vld_m & wait_rd_m) | | |
1237 | (cmp_rs1_rd_b & vld_b & check_rs1_b) | | |
1238 | (cmp_rs2_rd_b & vld_b & check_rs2_b) | | |
1239 | (cmp_rd_rd_b & vld_b & wait_rd_b); | |
1240 | ||
1241 | ||
1242 | pku_swl_ctl_msff_ctl_macro__width_1 tlu_retryf ( | |
1243 | .scan_in(tlu_retryf_scanin), | |
1244 | .scan_out(tlu_retryf_scanout), | |
1245 | .l1clk(l1clk_pm1), | |
1246 | .din (tlu_retry_state), | |
1247 | .dout (retry_state), | |
1248 | .siclk(siclk), | |
1249 | .soclk(soclk) | |
1250 | ); | |
1251 | ||
1252 | ||
1253 | // block_store_stall | |
1254 | ||
1255 | pku_swl_ctl_msff_ctl_macro__width_2 block_store_stallf ( | |
1256 | .scan_in(block_store_stallf_scanin), | |
1257 | .scan_out(block_store_stallf_scanout), | |
1258 | .l1clk(l1clk_pm1), | |
1259 | .din ({dec_block_store_stall,block_store_stall[1]}), | |
1260 | .dout (block_store_stall[1:0]), | |
1261 | .siclk(siclk), | |
1262 | .soclk(soclk) | |
1263 | ); | |
1264 | ||
1265 | // on leading edge of block_store_stall set scnt to full state (4'b1000) | |
1266 | ||
1267 | assign full_scnt = ~block_store_stall[0] & block_store_stall[1]; | |
1268 | ||
1269 | // vld_p is not needed since pick cannot occur unless vld_p | |
1270 | // illegals are treated as normal instructions wrt cancel_pick | |
1271 | ||
1272 | assign swl_cancel_pick_p = (lsu_sync_raw_w) | // cycle lsu sync don't pick since lsu_sync_wait is not in effect yet | |
1273 | (dcti_p & ~vld_1 & ~retry_state) | // IF retry_state, let the DCTI go | |
1274 | (dcti_p & vld_d & dcti_d) | // for a DCTI pair, make sure we know the real DS | |
1275 | (dcti_p & ~vld_d & vld_e & dcti_e) | | |
1276 | (pku_twocycle_p & vld_d & specld_d & idest_d) | // can't let twocycle go if int load at decode stage | |
1277 | // we do NO dependency checking on second half of twocycle (e.g. STD) | |
1278 | (dependent_cancel) | // dependency checking | |
1279 | ||
1280 | // window ops needs at least 2 holes in front of them | |
1281 | // if an ecc error can be generated in the hole, it doesn't count as a hole (no flush_b for window_ops) | |
1282 | (windowsync_p & (vld_d | vld_e | (vld_m & any_twocycle_m) | divide_wait1 | block_store_stall[0])) | | |
1283 | ||
1284 | (fpsingle_cancel) | | |
1285 | (fpdouble_cancel) | | |
1286 | (fccdep_cancel) | | |
1287 | (fsrsync_cancel) | | |
1288 | (stb_cancel) | | |
1289 | (div_p & divide_wait_outstanding) | | |
1290 | (ldst_sync_single & fpsrc_double_p) | // can't let double go if single missed | |
1291 | (ldst_sync_ldfsr) | // wait one cycle on ldfsr that misses the cache | |
1292 | (restore_scnt & store_p); // cancel pick in this case; assume pick is too late to put into logic updating scnt | |
1293 | ||
1294 | // this is "early" version of the pick signal (pku_flush_buffer0 is cycle AFTER branch mispredict) | |
1295 | assign pick_raw_p = pku_raw_pick_p & ~swl_cancel_pick_p & ~(~dec_decode_d & dec_valid_d); | |
1296 | ||
1297 | assign pick_p = pick_raw_p & ~pku_flush_buffer0; | |
1298 | ||
1299 | // this is the final version of the pick signal taking DS into account (flush_p is SAME cycle as branch mispredict) | |
1300 | assign actual_pick_p = pick_p & ~flush_p; | |
1301 | ||
1302 | // this is for the address logic (dont include annuling) | |
1303 | assign actual_raw_pick_p = vld_p & pick_raw_p & ~rawflush_p; | |
1304 | ||
1305 | ||
1306 | // postsync wait conditions | |
1307 | assign set_postsync = actual_pick_p & postsync_p; | |
1308 | ||
1309 | assign clear_postsync = (postsync_d & flush_d) | // if postsync is flushed then clear | |
1310 | (postsync_e & flush_e) | | |
1311 | (vld_w & bkick_w) | // ldfsr,stfsr,save,restore,saved,restored,return | |
1312 | (vld_fb & fbkick_fb) | // all integer ops in fgu exit here | |
1313 | (br_mispredict_m & callclass_m & ~bkick_m) | // clear out JMPS,CALLS (but not RETURNS) | |
1314 | lsu_sync_raw_w | ext_flush; // done, retries will exit via ext_flush | |
1315 | ||
1316 | assign postsync_in = (post_sync & ~clear_postsync) | set_postsync; // priority set | |
1317 | ||
1318 | pku_swl_ctl_msff_ctl_macro__width_1 post_syncf ( | |
1319 | .scan_in(post_syncf_scanin), | |
1320 | .scan_out(post_syncf_scanout), | |
1321 | .l1clk(l1clk_pm2), | |
1322 | .din (postsync_in), | |
1323 | .dout (post_sync), | |
1324 | .siclk(siclk), | |
1325 | .soclk(soclk) | |
1326 | ); | |
1327 | ||
1328 | // lsu_spec_enable is static | |
1329 | ||
1330 | pku_swl_ctl_msff_ctl_macro__width_1 spec_enf ( | |
1331 | .scan_in(spec_enf_scanin), | |
1332 | .scan_out(spec_enf_scanout), | |
1333 | .l1clk(l1clk_pm1), | |
1334 | .din (lsu_spec_enable), | |
1335 | .dout (spec_en), | |
1336 | .siclk(siclk), | |
1337 | .soclk(soclk) | |
1338 | ); | |
1339 | ||
1340 | pku_swl_ctl_msff_ctl_macro__width_1 active_threadf ( | |
1341 | .scan_in(active_threadf_scanin), | |
1342 | .scan_out(active_threadf_scanout), | |
1343 | .l1clk(l1clk), | |
1344 | .din (spc_core_running_status), | |
1345 | .dout (thread_active), | |
1346 | .siclk(siclk), | |
1347 | .soclk(soclk) | |
1348 | ); | |
1349 | ||
1350 | // fgu asked that in non-spec mode we wait 1 more cycle before sending next op down pipe | |
1351 | ||
1352 | assign set_postsync_ns = actual_pick_p & ((specbr_p | specld_p | specfp_p) & ~spec_en); | |
1353 | ||
1354 | assign clear_postsync_ns = (vld_m & specbr_m) | | |
1355 | (vld_b & specld_b) | | |
1356 | fpvld_w2 | | |
1357 | ext_flush | br_mispredict_m | lsu_sync_w; | |
1358 | ||
1359 | assign postsync_ns_in = (postsync_ns | set_postsync_ns) & ~clear_postsync_ns; | |
1360 | ||
1361 | pku_swl_ctl_msff_ctl_macro__width_1 postsync_nsf ( | |
1362 | .scan_in(postsync_nsf_scanin), | |
1363 | .scan_out(postsync_nsf_scanout), | |
1364 | .l1clk(l1clk_pm2), | |
1365 | .din (postsync_ns_in), | |
1366 | .dout (postsync_ns), | |
1367 | .siclk(siclk), | |
1368 | .soclk(soclk) | |
1369 | ); | |
1370 | ||
1371 | ||
1372 | // any instruction that has dependency on prior instruction is not allowed into machine | |
1373 | // includes int and FP ops | |
1374 | // dep_wait is independent of spec_en | |
1375 | // fccdep_wait checks fcc dependencies | |
1376 | // fsrsync checks for fsr hazards | |
1377 | // fpdouble wait doesn't allow fpsrc_double to go if prior fpdest_single | |
1378 | assign set_dep_wait = vld_p & (dependent_wait | fccdep_wait | fsrsync_wait | fpdouble_wait | fpsingle_wait); | |
1379 | ||
1380 | assign clear_dep_wait = flush_p; | |
1381 | ||
1382 | assign dep_wait_in = set_dep_wait & ~clear_dep_wait; | |
1383 | ||
1384 | // dcti wait conditions (has delay slot) | |
1385 | ||
1386 | assign set_dcti_wait = dcti_p & vld_p & ~vld_1 & ~retry_state; | |
1387 | ||
1388 | assign clear_dcti_wait = ifu_ibuffer_write_c | flush_p; | |
1389 | ||
1390 | assign dcti_wait_in = set_dcti_wait & ~clear_dcti_wait; | |
1391 | ||
1392 | // dcti couple conditions (two dctis with delay slots) | |
1393 | // for this case, will be in wait state for dcti_e | |
1394 | ||
1395 | assign set_dcti_couple_wait = dcti_d & vld_d & dcti_p & vld_p; | |
1396 | ||
1397 | assign clear_dcti_couple_wait = flush_p; | |
1398 | ||
1399 | assign dcti_couple_wait_in = set_dcti_couple_wait & ~clear_dcti_couple_wait; | |
1400 | ||
1401 | // divide wait (as soon as you pick a divide goto wait) | |
1402 | // keep track of whether the divide is flushed or not | |
1403 | ||
1404 | assign flush_div = (((flush_d & div_d) | (flush_e & div_e)) & swl_divide_wait) | lsu_sync_w | ext_flush; | |
1405 | ||
1406 | assign set_divide_wait_in = actual_pick_p & div_p; | |
1407 | ||
1408 | assign clear_divide_wait_in = fgu_divide_completion | flush_div; | |
1409 | ||
1410 | assign divide_wait_in = (set_divide_wait_in | swl_divide_wait) & ~clear_divide_wait_in; | |
1411 | ||
1412 | pku_swl_ctl_msff_ctl_macro__width_1 divide_waitf ( | |
1413 | .scan_in(divide_waitf_scanin), | |
1414 | .scan_out(divide_waitf_scanout), | |
1415 | .l1clk(l1clk_pm1), | |
1416 | .din (divide_wait_in), | |
1417 | .dout (swl_divide_wait), | |
1418 | .siclk(siclk), | |
1419 | .soclk(soclk) | |
1420 | ); | |
1421 | ||
1422 | pku_swl_ctl_msff_ctl_macro__width_1 divide_wait1f ( | |
1423 | .scan_in(divide_wait1f_scanin), | |
1424 | .scan_out(divide_wait1f_scanout), | |
1425 | .l1clk(l1clk_pm1), | |
1426 | .din (swl_divide_wait), | |
1427 | .dout (divide_wait1), | |
1428 | .siclk(siclk), | |
1429 | .soclk(soclk) | |
1430 | ); | |
1431 | ||
1432 | // wait for other divide to finish before you try to pick this divide | |
1433 | assign otherdivide_wait_in = div_p & vld_p & divide_wait_outstanding & ~flush_p; | |
1434 | ||
1435 | pku_swl_ctl_msff_ctl_macro__width_2 lsu_completef ( | |
1436 | .scan_in(lsu_completef_scanin), | |
1437 | .scan_out(lsu_completef_scanout), | |
1438 | .l1clk(l1clk_pm1), | |
1439 | .din ({lsu_complete,lsu_complete_d1}), | |
1440 | .dout ({lsu_complete_d1,lsu_complete_d2}), | |
1441 | .siclk(siclk), | |
1442 | .soclk(soclk) | |
1443 | ); | |
1444 | ||
1445 | // lsu_sync has happened; wait for lsu_complete or thread is flushed (can't commit out-of-order) | |
1446 | assign set_lsu_sync_wait = lsu_sync_raw_w; | |
1447 | ||
1448 | assign clear_lsu_sync_wait = ext_flush | lsu_complete; | |
1449 | ||
1450 | assign lsu_sync_wait_in = (set_lsu_sync_wait | lsu_sync_wait) & ~clear_lsu_sync_wait; | |
1451 | ||
1452 | pku_swl_ctl_msff_ctl_macro__width_1 lsu_sync_waitf ( | |
1453 | .scan_in(lsu_sync_waitf_scanin), | |
1454 | .scan_out(lsu_sync_waitf_scanout), | |
1455 | .l1clk(l1clk_pm1), | |
1456 | .din (lsu_sync_wait_in), | |
1457 | .dout (lsu_sync_wait), | |
1458 | .siclk(siclk), | |
1459 | .soclk(soclk) | |
1460 | ); | |
1461 | ||
1462 | // FGU handles case where double is followed by single | |
1463 | // pick handles single followed by double | |
1464 | // wait a cycle to clear to make sure hazard free with subsequent fp double | |
1465 | assign clear_lsu_sync_single = ext_flush | lsu_complete_d2; | |
1466 | ||
1467 | assign ldst_sync_single_in = (lsu_sync_raw_w & ~clear_lsu_sync_single & fpdest_single_w) | | |
1468 | (~lsu_sync_raw_w & ~clear_lsu_sync_single & ldst_sync_single); | |
1469 | ||
1470 | pku_swl_ctl_msff_ctl_macro__width_1 ldst_sync_singlef ( | |
1471 | .scan_in(ldst_sync_singlef_scanin), | |
1472 | .scan_out(ldst_sync_singlef_scanout), | |
1473 | .l1clk(l1clk_pm1), | |
1474 | .din (ldst_sync_single_in), | |
1475 | .dout (ldst_sync_single), | |
1476 | .siclk(siclk), | |
1477 | .soclk(soclk) | |
1478 | ); | |
1479 | ||
1480 | ||
1481 | // wait a cycle if a ldfsr misses to make sure ccr's are updated correctly | |
1482 | assign clear_lsu_sync_ldfsr = ext_flush | lsu_complete_d2; | |
1483 | ||
1484 | // NOTE: load with no fdest and no idest MUST be ldfsr | |
1485 | assign fsrsync_w = specld_w & ~fdest_w & ~idest_w; | |
1486 | ||
1487 | assign ldst_sync_ldfsr_in = (lsu_sync_raw_w & ~clear_lsu_sync_ldfsr & fsrsync_w) | | |
1488 | (~lsu_sync_raw_w & ~clear_lsu_sync_ldfsr & ldst_sync_ldfsr); | |
1489 | ||
1490 | pku_swl_ctl_msff_ctl_macro__width_1 ldst_sync_ldfsrf ( | |
1491 | .scan_in(ldst_sync_ldfsrf_scanin), | |
1492 | .scan_out(ldst_sync_ldfsrf_scanout), | |
1493 | .l1clk(l1clk_pm1), | |
1494 | .din (ldst_sync_ldfsr_in), | |
1495 | .dout (ldst_sync_ldfsr), | |
1496 | .siclk(siclk), | |
1497 | .soclk(soclk) | |
1498 | ); | |
1499 | ||
1500 | // track stores down the pipe to the store buffer | |
1501 | ||
1502 | assign br_flush1_in = br_mispredict_e & ~(lsu_sync_w | ext_flush); | |
1503 | pku_swl_ctl_msff_ctl_macro__width_1 brflush1_f ( | |
1504 | .scan_in(brflush1_f_scanin), | |
1505 | .scan_out(brflush1_f_scanout), | |
1506 | .l1clk(l1clk_pm2), | |
1507 | .din (br_flush1_in), | |
1508 | .dout (br_flush1), | |
1509 | .siclk(siclk), | |
1510 | .soclk(soclk) | |
1511 | ); | |
1512 | ||
1513 | assign br_flush2_in = br_flush1 & ~(lsu_sync_w | ext_flush); | |
1514 | pku_swl_ctl_msff_ctl_macro__width_1 brflush2_f ( | |
1515 | .scan_in(brflush2_f_scanin), | |
1516 | .scan_out(brflush2_f_scanout), | |
1517 | .l1clk(l1clk_pm2), | |
1518 | .din (br_flush2_in), | |
1519 | .dout (brflush2), | |
1520 | .siclk(siclk), | |
1521 | .soclk(soclk) | |
1522 | ); | |
1523 | ||
1524 | assign not_annul_ds1_in = ~annul_ds_dcti_e; | |
1525 | pku_swl_ctl_msff_ctl_macro__width_1 not_annul_ds1_f ( | |
1526 | .scan_in(not_annul_ds1_f_scanin), | |
1527 | .scan_out(not_annul_ds1_f_scanout), | |
1528 | .l1clk(l1clk_pm2), | |
1529 | .din (not_annul_ds1_in), | |
1530 | .dout (not_annul_ds1), | |
1531 | .siclk(siclk), | |
1532 | .soclk(soclk) | |
1533 | ); | |
1534 | ||
1535 | assign not_annul_ds2_in = not_annul_ds1; | |
1536 | pku_swl_ctl_msff_ctl_macro__width_1 not_annul_ds2_f ( | |
1537 | .scan_in(not_annul_ds2_f_scanin), | |
1538 | .scan_out(not_annul_ds2_f_scanout), | |
1539 | .l1clk(l1clk_pm2), | |
1540 | .din (not_annul_ds2_in), | |
1541 | .dout (not_annul_ds2), | |
1542 | .siclk(siclk), | |
1543 | .soclk(soclk) | |
1544 | ); | |
1545 | ||
1546 | ||
1547 | //assign store_ds1_in = (br_mispredict_e & ~annul_ds_dcti_e & vld_d & pick_store_d) & ~(lsu_sync_w | ext_flush); | |
1548 | ||
1549 | assign store_ds1_in = (~annul_ds_dcti_e & vld_d & pick_store_d) & ~(lsu_sync_w | ext_flush); | |
1550 | ||
1551 | pku_swl_ctl_msff_ctl_macro__width_1 store_ds1_f ( | |
1552 | .scan_in(store_ds1_f_scanin), | |
1553 | .scan_out(store_ds1_f_scanout), | |
1554 | .l1clk(l1clk_pm2), | |
1555 | .din (store_ds1_in), | |
1556 | .dout (store_ds1), | |
1557 | .siclk(siclk), | |
1558 | .soclk(soclk) | |
1559 | ); | |
1560 | ||
1561 | assign store_ds2_in = (store_ds1 | (not_annul_ds1 & vld_d & pick_store_d)) & ~(lsu_sync_w | ext_flush); | |
1562 | ||
1563 | pku_swl_ctl_msff_ctl_macro__width_1 store_ds2_f ( | |
1564 | .scan_in(store_ds2_f_scanin), | |
1565 | .scan_out(store_ds2_f_scanout), | |
1566 | .l1clk(l1clk_pm2), | |
1567 | .din (store_ds2_in), | |
1568 | .dout (store_ds2), | |
1569 | .siclk(siclk), | |
1570 | .soclk(soclk) | |
1571 | ); | |
1572 | ||
1573 | assign store_ds = (store_ds2 | (not_annul_ds2 & vld_d & pick_store_d)) & ~(lsu_sync_w | ext_flush); | |
1574 | ||
1575 | assign restore_scnt = (brflush2 | lsu_sync_w | ext_flush); | |
1576 | ||
1577 | // delay allocation of store into the scnt for timing | |
1578 | assign pick_store_p = (pick_p & ~late_flush_p & store_p); | |
1579 | ||
1580 | pku_swl_ctl_msff_ctl_macro__width_1 pickstoref ( | |
1581 | .scan_in(pickstoref_scanin), | |
1582 | .scan_out(pickstoref_scanout), | |
1583 | .l1clk(l1clk_pm2), | |
1584 | .din (pick_store_p), | |
1585 | .dout (pick_store_d), | |
1586 | .siclk(siclk), | |
1587 | .soclk(soclk) | |
1588 | ); | |
1589 | ||
1590 | assign alloc_scnt = pick_store_d; | |
1591 | ||
1592 | assign dealloc_scnt = lsu_stb_dealloc; | |
1593 | ||
1594 | // take everything into account except for annuling stores | |
1595 | assign inc_scnt_raw = alloc_scnt & ~dealloc_scnt; | |
1596 | assign dec_scnt_raw = ~alloc_scnt & dealloc_scnt; | |
1597 | assign hold_scnt_raw = ~inc_scnt_raw & ~dec_scnt_raw; | |
1598 | ||
1599 | // take annuling into account | |
1600 | // if you annul a store then you need to decrement scnt by 1 | |
1601 | assign annul_store_in = annul_ds_dcti_e & vld_d & pick_store_d & ~restore_scnt & ~full_scnt; | |
1602 | ||
1603 | pku_swl_ctl_msff_ctl_macro__width_1 annul_store_f ( | |
1604 | .scan_in(annul_store_f_scanin), | |
1605 | .scan_out(annul_store_f_scanout), | |
1606 | .l1clk(l1clk_pm1), | |
1607 | .din (annul_store_in), | |
1608 | .dout (annul_store_d), | |
1609 | .siclk(siclk), | |
1610 | .soclk(soclk) | |
1611 | ); | |
1612 | ||
1613 | // take into account that the store may be annuled | |
1614 | ||
1615 | assign inc_scnt = (inc_scnt_raw & ~annul_store_d); | |
1616 | assign dec1_scnt = (dec_scnt_raw & ~annul_store_d) | (hold_scnt_raw & annul_store_d); | |
1617 | assign hold_scnt = (hold_scnt_raw & ~annul_store_d) | (inc_scnt_raw & annul_store_d); | |
1618 | assign dec2_scnt = (dec_scnt_raw & annul_store_d); | |
1619 | ||
1620 | // on a restore_scnt, pick must keep track of the DS is a store and whether it is annuled or not | |
1621 | ||
1622 | assign inc2_ccnt = (inc_ccnt_raw & store_ds); | |
1623 | assign inc1_ccnt = (inc_ccnt_raw & ~store_ds) | (hold_ccnt_raw & store_ds); | |
1624 | assign hold_ccnt = (hold_ccnt_raw & ~store_ds) | (dec_ccnt_raw & store_ds); | |
1625 | assign dec1_ccnt = (dec_ccnt_raw & ~store_ds); | |
1626 | ||
1627 | ||
1628 | assign ccnt_in[3:0] = ({4{hold_ccnt}} & ccnt[3:0]) | | |
1629 | ({4{inc2_ccnt}} & (ccnt[3:0]+4'b0010)) | | |
1630 | ({4{inc1_ccnt}} & (ccnt[3:0]+4'b0001)) | | |
1631 | ({4{dec1_ccnt}} & (ccnt[3:0]-4'b0001)); | |
1632 | ||
1633 | // 0in bits_on -var {hold_ccnt,inc2_ccnt,inc1_ccnt,dec1_ccnt} -max 1 -message "bad ccnt update" | |
1634 | ||
1635 | // compute scnt | |
1636 | assign scnt_in[3:0] = (({4{~restore_scnt & hold_scnt & ~full_scnt}} & scnt[3:0]) | | |
1637 | ({4{~restore_scnt & inc_scnt & ~full_scnt}} & (scnt[3:0]+4'b0001)) | | |
1638 | ({4{~restore_scnt & dec1_scnt & ~full_scnt}} & (scnt[3:0]-4'b0001)) | | |
1639 | ({4{~restore_scnt & dec2_scnt & ~full_scnt}} & (scnt[3:0]-4'b0010)) | | |
1640 | ({4{restore_scnt & ~full_scnt}} & ccnt_in[3:0]) | | |
1641 | ({4{full_scnt}} & 4'b1000)) & {4{~lsu_block_store_kill}}; | |
1642 | ||
1643 | // 0in bits_on -var {hold_scnt,inc_scnt,dec1_scnt} -max 1 -message "scnt selects not mutually exclusive" | |
1644 | ||
1645 | // 0in value -var scnt[3:0] -val 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 -message "scnt[3:0] illegal state" | |
1646 | ||
1647 | pku_swl_ctl_msff_ctl_macro__width_4 scnt_f ( | |
1648 | .scan_in(scnt_f_scanin), | |
1649 | .scan_out(scnt_f_scanout), | |
1650 | .l1clk(l1clk_pm1), | |
1651 | .din (scnt_in[3:0]), | |
1652 | .dout (scnt[3:0]), | |
1653 | .siclk(siclk), | |
1654 | .soclk(soclk) | |
1655 | ); | |
1656 | ||
1657 | assign alloc_ccnt = lsu_stb_alloc; | |
1658 | assign dealloc_ccnt = lsu_stb_dealloc; | |
1659 | ||
1660 | assign inc_ccnt_raw = alloc_ccnt & ~dealloc_ccnt; | |
1661 | assign dec_ccnt_raw = ~alloc_ccnt & dealloc_ccnt; | |
1662 | assign hold_ccnt_raw = ~inc_ccnt_raw & ~dec_ccnt_raw; | |
1663 | ||
1664 | assign ccnt_raw_in[3:0] = (({4{hold_ccnt_raw}} & ccnt[3:0]) | | |
1665 | ({4{inc_ccnt_raw}} & (ccnt[3:0]+4'b0001)) | | |
1666 | ({4{dec_ccnt_raw}} & (ccnt[3:0]-4'b0001))) & {4{~lsu_block_store_kill}}; | |
1667 | ||
1668 | ||
1669 | // 0in value -var ccnt[3:0] -val 4'b0000 4'b0001 4'b0010 4'b0011 4'b0100 4'b0101 4'b0110 4'b0111 4'b1000 -message "ccnt[3:0] illegal state" | |
1670 | ||
1671 | // 0in assert -var (~(ccnt[3:0]>scnt[3:0])) -message "unexpected ccnt[3:0] > scnt[3:0]" | |
1672 | ||
1673 | pku_swl_ctl_msff_ctl_macro__width_4 ccnt_f ( | |
1674 | .scan_in(ccnt_f_scanin), | |
1675 | .scan_out(ccnt_f_scanout), | |
1676 | .l1clk(l1clk_pm1), | |
1677 | .din (ccnt_raw_in[3:0]), | |
1678 | .dout (ccnt[3:0]), | |
1679 | .siclk(siclk), | |
1680 | .soclk(soclk) | |
1681 | ); | |
1682 | ||
1683 | // stb is full; cancel pick | |
1684 | //assign stb_cancel = (scnt[3] & store_p) | (scnt[2] & scnt[1] & scnt[0] & pick_store_d); | |
1685 | ||
1686 | assign stb_cancel = (scnt[3] | (scnt[2] & scnt[1] & scnt[0] & pick_store_d)) & store_p; | |
1687 | ||
1688 | assign stb_wait_in = stb_cancel; | |
1689 | ||
1690 | assign rdy_in = ~( lsu_sync_wait_in | | |
1691 | otherdivide_wait_in | | |
1692 | divide_wait_in | | |
1693 | postsync_in | | |
1694 | postsync_ns_in | | |
1695 | dep_wait_in | // wait due to dependency | |
1696 | stb_wait_in | | |
1697 | dcti_wait_in | | |
1698 | dcti_couple_wait_in ); | |
1699 | ||
1700 | // in multithread mode, added w stage to give load flush a chance before transitioning from spec to ready | |
1701 | ||
1702 | assign spec_in = (spec_en & vld_d_in & (specbr_d_in | specld_d_in)) | | |
1703 | (spec_en & vld_e_in & (specbr_e_in | specld_e_in)) | | |
1704 | (spec_en & vld_m_in & specld_m_in) | | |
1705 | (spec_en & vld_b_in & specld_b_in) | | |
1706 | (spec_en & vld_w_in & specld_w_in); | |
1707 | ||
1708 | ||
1709 | // 0in assert -var (~(tlu_halted & spec_in)) -message "spec_in must be 0 if tlu_halted is a 1" | |
1710 | ||
1711 | assign ready_in = rdy_in & ~tlu_halted & ~spec_in; | |
1712 | ||
1713 | pku_swl_ctl_msff_ctl_macro__width_1 readyf ( | |
1714 | .scan_in(readyf_scanin), | |
1715 | .scan_out(readyf_scanout), | |
1716 | .l1clk(l1clk_pm1), | |
1717 | .din (ready_in), | |
1718 | .dout (swl_ready_p), | |
1719 | .siclk(siclk), | |
1720 | .soclk(soclk) | |
1721 | ); | |
1722 | ||
1723 | // remove tlu_halted since spec_in must be 0 if tlu_halted is asserted | |
1724 | assign spec_ready_in = rdy_in & spec_in; | |
1725 | ||
1726 | pku_swl_ctl_msff_ctl_macro__width_1 spec_readyf ( | |
1727 | .scan_in(spec_readyf_scanin), | |
1728 | .scan_out(spec_readyf_scanout), | |
1729 | .l1clk(l1clk_pm1), | |
1730 | .din (spec_ready_in), | |
1731 | .dout (swl_spec_ready_p), | |
1732 | .siclk(siclk), | |
1733 | .soclk(soclk) | |
1734 | ); | |
1735 | ||
1736 | ||
1737 | // track all delay slots down the pipe for tlu | |
1738 | ||
1739 | assign allds_actual_p = (allds_p | allds_is_p) & ~(lsu_sync_w | ext_flush); | |
1740 | assign allds_actual_d = (allds_d | allds_is_d) & ~(lsu_sync_w | ext_flush); | |
1741 | ||
1742 | assign allds_p_in = ~actual_pick_p & allds_actual_p; | |
1743 | ||
1744 | pku_swl_ctl_msff_ctl_macro__width_1 allds_p_f ( | |
1745 | .scan_in(allds_p_f_scanin), | |
1746 | .scan_out(allds_p_f_scanout), | |
1747 | .l1clk(l1clk_pm2), | |
1748 | .din (allds_p_in), | |
1749 | .dout (allds_p), | |
1750 | .siclk(siclk), | |
1751 | .soclk(soclk) | |
1752 | ); | |
1753 | ||
1754 | assign allds_d_in = (actual_pick_p & allds_actual_p) | | |
1755 | (~dec_decode_d & allds_actual_d); | |
1756 | ||
1757 | pku_swl_ctl_msff_ctl_macro__width_1 allds_d_f ( | |
1758 | .scan_in(allds_d_f_scanin), | |
1759 | .scan_out(allds_d_f_scanout), | |
1760 | .l1clk(l1clk_pm2), | |
1761 | .din (allds_d_in), | |
1762 | .dout (allds_d), | |
1763 | .siclk(siclk), | |
1764 | .soclk(soclk) | |
1765 | ); | |
1766 | ||
1767 | assign allds_e_in = dec_decode_d & allds_actual_d; | |
1768 | ||
1769 | pku_swl_ctl_msff_ctl_macro__width_1 allds_e_f ( | |
1770 | .scan_in(allds_e_f_scanin), | |
1771 | .scan_out(allds_e_f_scanout), | |
1772 | .l1clk(l1clk_pm2), | |
1773 | .din (allds_e_in), | |
1774 | .dout (pku_ds_e), | |
1775 | .siclk(siclk), | |
1776 | .soclk(soclk) | |
1777 | ); | |
1778 | ||
1779 | // pipeline tracking | |
1780 | // decode, execute, memory(dcache access), writeback (hit/miss determination) | |
1781 | ||
1782 | // any flush will clear the proper valids the next cycle | |
1783 | ||
1784 | assign set_vld_d = actual_pick_p; | |
1785 | ||
1786 | assign clear_vld_d = dec_decode_d | flush_d; | |
1787 | ||
1788 | assign vld_d_in = (vld_d & ~clear_vld_d) | set_vld_d; | |
1789 | ||
1790 | pku_swl_ctl_msff_ctl_macro__width_1 vld_df ( | |
1791 | .scan_in(vld_df_scanin), | |
1792 | .scan_out(vld_df_scanout), | |
1793 | .l1clk(l1clk_pm2), | |
1794 | .din (vld_d_in), | |
1795 | .dout (vld_d), | |
1796 | .siclk(siclk), | |
1797 | .soclk(soclk) | |
1798 | ); | |
1799 | ||
1800 | ||
1801 | assign vld_e_in = vld_d & dec_decode_d & ~flush_d; | |
1802 | ||
1803 | pku_swl_ctl_msff_ctl_macro__width_1 vld_ef ( | |
1804 | .scan_in(vld_ef_scanin), | |
1805 | .scan_out(vld_ef_scanout), | |
1806 | .l1clk(l1clk_pm2), | |
1807 | .din (vld_e_in), | |
1808 | .dout (vld_e), | |
1809 | .siclk(siclk), | |
1810 | .soclk(soclk) | |
1811 | ); | |
1812 | ||
1813 | assign valid_e = vld_e & dec_true_valid_e; // final valid e taking exceptions into account | |
1814 | ||
1815 | assign valid_e_in = vld_e_in & ~lsu_sync & ~tlu_flush_ifu & ~annul_ds_dcti_e; | |
1816 | ||
1817 | pku_swl_ctl_msff_ctl_macro__width_1 valid_ef ( | |
1818 | .scan_in(valid_ef_scanin), | |
1819 | .scan_out(valid_ef_scanout), | |
1820 | .l1clk(l1clk_pm2), | |
1821 | .din (valid_e_in), | |
1822 | .dout (pku_valid_e), | |
1823 | .siclk(siclk), | |
1824 | .soclk(soclk) | |
1825 | ); | |
1826 | ||
1827 | assign vld_m_in = vld_e & ~flush_e; | |
1828 | ||
1829 | pku_swl_ctl_msff_ctl_macro__width_1 vld_mf ( | |
1830 | .scan_in(vld_mf_scanin), | |
1831 | .scan_out(vld_mf_scanout), | |
1832 | .l1clk(l1clk_pm2), | |
1833 | .din (vld_m_in), | |
1834 | .dout (vld_m), | |
1835 | .siclk(siclk), | |
1836 | .soclk(soclk) | |
1837 | ); | |
1838 | ||
1839 | assign vld_b_in = vld_m & ~flush_m; | |
1840 | ||
1841 | pku_swl_ctl_msff_ctl_macro__width_1 vld_bf ( | |
1842 | .scan_in(vld_bf_scanin), | |
1843 | .scan_out(vld_bf_scanout), | |
1844 | .l1clk(l1clk_pm2), | |
1845 | .din (vld_b_in), | |
1846 | .dout (vld_b), | |
1847 | .siclk(siclk), | |
1848 | .soclk(soclk) | |
1849 | ); | |
1850 | ||
1851 | assign vld_w_in = vld_b & ~flush_b; | |
1852 | ||
1853 | pku_swl_ctl_msff_ctl_macro__width_1 vld_wf ( | |
1854 | .scan_in(vld_wf_scanin), | |
1855 | .scan_out(vld_wf_scanout), | |
1856 | .l1clk(l1clk_pm2), | |
1857 | .din (vld_w_in), | |
1858 | .dout (vld_w), | |
1859 | .siclk(siclk), | |
1860 | .soclk(soclk) | |
1861 | ); | |
1862 | ||
1863 | assign fpvld_w1_in = vld_w & specfp_w & ~ext_flush; | |
1864 | ||
1865 | pku_swl_ctl_msff_ctl_macro__width_1 fpvld_w1f ( | |
1866 | .scan_in(fpvld_w1f_scanin), | |
1867 | .scan_out(fpvld_w1f_scanout), | |
1868 | .l1clk(l1clk_pm2), | |
1869 | .din (fpvld_w1_in), | |
1870 | .dout (fpvld_w1), | |
1871 | .siclk(siclk), | |
1872 | .soclk(soclk) | |
1873 | ); | |
1874 | ||
1875 | assign fpvld_w2_in = fpvld_w1 & ~ext_flush; | |
1876 | ||
1877 | pku_swl_ctl_msff_ctl_macro__width_1 fpvld_w2f ( | |
1878 | .scan_in(fpvld_w2f_scanin), | |
1879 | .scan_out(fpvld_w2f_scanout), | |
1880 | .l1clk(l1clk_pm2), | |
1881 | .din (fpvld_w2_in), | |
1882 | .dout (fpvld_w2), | |
1883 | .siclk(siclk), | |
1884 | .soclk(soclk) | |
1885 | ); | |
1886 | ||
1887 | // seperate pipeline for address tracking with no DS flushing | |
1888 | ||
1889 | assign set_vldraw_d = actual_raw_pick_p; | |
1890 | ||
1891 | assign clear_vldraw_d = dec_decode_d | rawflush_d; | |
1892 | ||
1893 | assign vldraw_d_in = (vldraw_d & ~clear_vldraw_d) | set_vldraw_d; | |
1894 | ||
1895 | pku_swl_ctl_msff_ctl_macro__width_1 vldraw_df ( | |
1896 | .scan_in(vldraw_df_scanin), | |
1897 | .scan_out(vldraw_df_scanout), | |
1898 | .l1clk(l1clk_pm2), | |
1899 | .din (vldraw_d_in), | |
1900 | .dout (vldraw_d), | |
1901 | .siclk(siclk), | |
1902 | .soclk(soclk) | |
1903 | ); | |
1904 | ||
1905 | assign vldraw_e_in = dec_decode_d & vldraw_d; | |
1906 | ||
1907 | pku_swl_ctl_msff_ctl_macro__width_1 vldraw_ef ( | |
1908 | .scan_in(vldraw_ef_scanin), | |
1909 | .scan_out(vldraw_ef_scanout), | |
1910 | .l1clk(l1clk_pm2), | |
1911 | .din (vldraw_e_in), | |
1912 | .dout (vldraw_e), | |
1913 | .siclk(siclk), | |
1914 | .soclk(soclk) | |
1915 | ); | |
1916 | ||
1917 | assign vldraw_m_in = vldraw_e; | |
1918 | ||
1919 | pku_swl_ctl_msff_ctl_macro__width_1 vldraw_mf ( | |
1920 | .scan_in(vldraw_mf_scanin), | |
1921 | .scan_out(vldraw_mf_scanout), | |
1922 | .l1clk(l1clk_pm2), | |
1923 | .din (vldraw_m_in), | |
1924 | .dout (vldraw_m), | |
1925 | .siclk(siclk), | |
1926 | .soclk(soclk) | |
1927 | ); | |
1928 | ||
1929 | // Include annulled instructions until branch is in W | |
1930 | // Since cnt is calculated a cycle ahead, count annulled until branch exits M | |
1931 | ||
1932 | pku_swl_ctl_msff_ctl_macro__width_1 annul_ds_dcti_mf ( | |
1933 | .scan_in(annul_ds_dcti_mf_scanin), | |
1934 | .scan_out(annul_ds_dcti_mf_scanout), | |
1935 | .l1clk(l1clk_pm2), | |
1936 | .din (annul_ds_dcti_e), | |
1937 | .dout ( annul_ds_dcti_m), | |
1938 | .siclk(siclk), | |
1939 | .soclk(soclk) | |
1940 | ); | |
1941 | ||
1942 | assign vldcnt_e_brtaken0_in = | |
1943 | ( pku_annul_ds_dcti_brtaken0_e & vldraw_e_in) | | |
1944 | ( annul_ds_dcti_m & vldraw_e_in) | | |
1945 | (~pku_annul_ds_dcti_brtaken0_e & ~annul_ds_dcti_m & vld_d & dec_decode_d); // dont need flush_d here | |
1946 | ||
1947 | assign vldcnt_e_brtaken1_in = | |
1948 | ( pku_annul_ds_dcti_brtaken1_e & vldraw_e_in) | | |
1949 | ( annul_ds_dcti_m & vldraw_e_in) | | |
1950 | (~pku_annul_ds_dcti_brtaken1_e & ~annul_ds_dcti_m & vld_d & dec_decode_d); // dont need flush_d here | |
1951 | ||
1952 | assign vldcnt_m_in = | |
1953 | ( annul_ds_dcti_m & vldraw_m_in) | | |
1954 | (~annul_ds_dcti_m & vld_m_in); | |
1955 | ||
1956 | assign pku_inst_cnt_brtaken0[1:0] = ({1'b0,vldcnt_e_brtaken0_in} + {1'b0,vldcnt_m_in} + {1'b0,vld_b_in}); | |
1957 | ||
1958 | assign pku_inst_cnt_brtaken1[1:0] = ({1'b0,vldcnt_e_brtaken1_in} + {1'b0,vldcnt_m_in} + {1'b0,vld_b_in}); | |
1959 | ||
1960 | // end address logic | |
1961 | ||
1962 | ||
1963 | // track down to fb to flush inst in the fgu on a trap | |
1964 | ||
1965 | assign vld_f4_in = vld_w & fgu_w & ~flush_w; | |
1966 | ||
1967 | pku_swl_ctl_msff_ctl_macro__width_1 vld_f4f ( | |
1968 | .scan_in(vld_f4f_scanin), | |
1969 | .scan_out(vld_f4f_scanout), | |
1970 | .l1clk(l1clk_pm2), | |
1971 | .din (vld_f4_in), | |
1972 | .dout (vld_f4), | |
1973 | .siclk(siclk), | |
1974 | .soclk(soclk) | |
1975 | ); | |
1976 | ||
1977 | assign vld_f5_in = vld_f4 & ~flush_f4; | |
1978 | ||
1979 | pku_swl_ctl_msff_ctl_macro__width_1 vld_f5f ( | |
1980 | .scan_in(vld_f5f_scanin), | |
1981 | .scan_out(vld_f5f_scanout), | |
1982 | .l1clk(l1clk_pm2), | |
1983 | .din (vld_f5_in), | |
1984 | .dout (vld_f5), | |
1985 | .siclk(siclk), | |
1986 | .soclk(soclk) | |
1987 | ); | |
1988 | ||
1989 | assign vld_fb_in = vld_f5 & ~flush_f5; | |
1990 | ||
1991 | pku_swl_ctl_msff_ctl_macro__width_1 vld_fbf ( | |
1992 | .scan_in(vld_fbf_scanin), | |
1993 | .scan_out(vld_fbf_scanout), | |
1994 | .l1clk(l1clk_pm2), | |
1995 | .din (vld_fb_in), | |
1996 | .dout (vld_fb), | |
1997 | .siclk(siclk), | |
1998 | .soclk(soclk) | |
1999 | ); | |
2000 | ||
2001 | // pipe raw data down the pipe | |
2002 | // speculate decode to avoid loading | |
2003 | // must qualify with vld's before using | |
2004 | ||
2005 | // anytwocycle - inst is twocycle or pdist | |
2006 | // postsync - inst is a postsync | |
2007 | // div - inst is a divide inst | |
2008 | // bkick - inst should be kicked out of wait a b stage | |
2009 | // fpdest_double - fp dest double precision | |
2010 | // fpdest_single - fp dest single precision | |
2011 | // fccdest - inst will modify fcc | |
2012 | // lsu - inst executed by lsu | |
2013 | // fgu - inst executed by fgu | |
2014 | // fbkick - inst should be kicked out of wait at fb stage | |
2015 | // specfp - inst is fgu that is speculated on | |
2016 | // fdest - inst has FP dest | |
2017 | // idest - inst has integer dest | |
2018 | // div - any divide (int or fpu) | |
2019 | // condbr_p - conditional branch | |
2020 | // callclass_p - one of call, jmp or return | |
2021 | // annul - annul bit | |
2022 | // specbr - branch that is speculated on if spec_en==1 | |
2023 | // dcti - has delay slot | |
2024 | // specld - integer load that is speculated on if spec_en==1 | |
2025 | // rd[4:0] - destination of load | |
2026 | ||
2027 | assign any_twocycle_p = pku_twocycle_p | pku_pdist_p; | |
2028 | ||
2029 | assign data_d_in[23:0] = ({24{pick_p}} & {any_twocycle_p,postsync_p,div_p,bkick_p,fpdest_double_p,fpdest_single_p,fccdest_p,pku_lsu_p,pku_fgu_p,fbkick_p,specfp_p,pku_fdest_p,pku_idest_p,condbr_p,callclass_p,annul,specbr_p,dcti_p,specld_p,rd[4:0]}) | | |
2030 | ({24{~pick_p}} & data_d[23:0]); | |
2031 | ||
2032 | assign specld_d_in = data_d_in[5]; | |
2033 | assign specbr_d_in = data_d_in[7]; | |
2034 | ||
2035 | pku_swl_ctl_msff_ctl_macro__width_24 data_df ( | |
2036 | .scan_in(data_df_scanin), | |
2037 | .scan_out(data_df_scanout), | |
2038 | .l1clk(l1clk_pm2), | |
2039 | .din (data_d_in[23:0]), | |
2040 | .dout (data_d[23:0]), | |
2041 | .siclk(siclk), | |
2042 | .soclk(soclk) | |
2043 | ); | |
2044 | ||
2045 | assign {any_twocycle_d,postsync_d,div_d,bkick_d,fpdest_double_d,fpdest_single_d,fccdest_d,lsu_d, | |
2046 | fgu_d,fbkick_d, | |
2047 | specfp_d,fdest_d,idest_d,condbr_d,callclass_d,annul_d, | |
2048 | specbr_d,dcti_d,specld_d,rd_d[4:0]} = data_d[23:0]; | |
2049 | ||
2050 | assign specbr_e_in = specbr_d; | |
2051 | ||
2052 | assign specld_e_in = specld_d; | |
2053 | assign specld_m_in = specld_e; | |
2054 | assign specld_b_in = specld_m; | |
2055 | assign specld_w_in = specld_b; | |
2056 | ||
2057 | ||
2058 | pku_swl_ctl_msff_ctl_macro__width_20 rdf ( | |
2059 | .scan_in(rdf_scanin), | |
2060 | .scan_out(rdf_scanout), | |
2061 | .l1clk(l1clk_pm2), | |
2062 | .din ({rd_d[4:0],rd_e[4:0],rd_m[4:0],rd_b[4:0]}), | |
2063 | .dout ({rd_e[4:0],rd_m[4:0],rd_b[4:0],rd_w[4:0]}), | |
2064 | .siclk(siclk), | |
2065 | .soclk(soclk) | |
2066 | ); | |
2067 | ||
2068 | pku_swl_ctl_msff_ctl_macro__width_2 anytwocyclef ( | |
2069 | .scan_in(anytwocyclef_scanin), | |
2070 | .scan_out(anytwocyclef_scanout), | |
2071 | .l1clk(l1clk_pm2), | |
2072 | .din ({any_twocycle_d,any_twocycle_e}), | |
2073 | .dout ({any_twocycle_e,any_twocycle_m}), | |
2074 | .siclk(siclk), | |
2075 | .soclk(soclk) | |
2076 | ); | |
2077 | ||
2078 | ||
2079 | pku_swl_ctl_msff_ctl_macro__width_4 specldf ( | |
2080 | .scan_in(specldf_scanin), | |
2081 | .scan_out(specldf_scanout), | |
2082 | .l1clk(l1clk_pm2), | |
2083 | .din ({specld_d,specld_e,specld_m,specld_b}), | |
2084 | .dout ({specld_e,specld_m,specld_b,specld_w}), | |
2085 | .siclk(siclk), | |
2086 | .soclk(soclk) | |
2087 | ); | |
2088 | ||
2089 | pku_swl_ctl_msff_ctl_macro__width_1 postsyncf ( | |
2090 | .scan_in(postsyncf_scanin), | |
2091 | .scan_out(postsyncf_scanout), | |
2092 | .l1clk(l1clk_pm2), | |
2093 | .din (postsync_d), | |
2094 | .dout (postsync_e), | |
2095 | .siclk(siclk), | |
2096 | .soclk(soclk) | |
2097 | ); | |
2098 | ||
2099 | pku_swl_ctl_msff_ctl_macro__width_1 divf ( | |
2100 | .scan_in(divf_scanin), | |
2101 | .scan_out(divf_scanout), | |
2102 | .l1clk(l1clk_pm2), | |
2103 | .din (div_d), | |
2104 | .dout (div_e), | |
2105 | .siclk(siclk), | |
2106 | .soclk(soclk) | |
2107 | ); | |
2108 | ||
2109 | pku_swl_ctl_msff_ctl_macro__width_1 dctif ( | |
2110 | .scan_in(dctif_scanin), | |
2111 | .scan_out(dctif_scanout), | |
2112 | .l1clk(l1clk_pm2), | |
2113 | .din (dcti_d), | |
2114 | .dout (dcti_e), | |
2115 | .siclk(siclk), | |
2116 | .soclk(soclk) | |
2117 | ); | |
2118 | ||
2119 | pku_swl_ctl_msff_ctl_macro__width_1 specbref ( | |
2120 | .scan_in(specbref_scanin), | |
2121 | .scan_out(specbref_scanout), | |
2122 | .l1clk(l1clk_pm2), | |
2123 | .din (specbr_d), | |
2124 | .dout (specbr_e), | |
2125 | .siclk(siclk), | |
2126 | .soclk(soclk) | |
2127 | ); | |
2128 | ||
2129 | pku_swl_ctl_msff_ctl_macro__width_1 specbrmf ( | |
2130 | .scan_in(specbrmf_scanin), | |
2131 | .scan_out(specbrmf_scanout), | |
2132 | .l1clk(l1clk_pm2), | |
2133 | .din (specbr_e), | |
2134 | .dout (specbr_m), | |
2135 | .siclk(siclk), | |
2136 | .soclk(soclk) | |
2137 | ); | |
2138 | ||
2139 | pku_swl_ctl_msff_ctl_macro__width_1 annulf ( | |
2140 | .scan_in(annulf_scanin), | |
2141 | .scan_out(annulf_scanout), | |
2142 | .l1clk(l1clk_pm2), | |
2143 | .din (annul_d), | |
2144 | .dout (annul_e), | |
2145 | .siclk(siclk), | |
2146 | .soclk(soclk) | |
2147 | ); | |
2148 | ||
2149 | pku_swl_ctl_msff_ctl_macro__width_2 callclassf ( | |
2150 | .scan_in(callclassf_scanin), | |
2151 | .scan_out(callclassf_scanout), | |
2152 | .l1clk(l1clk_pm2), | |
2153 | .din ({callclass_d,callclass_e}), | |
2154 | .dout ({callclass_e,callclass_m}), | |
2155 | .siclk(siclk), | |
2156 | .soclk(soclk) | |
2157 | ); | |
2158 | ||
2159 | pku_swl_ctl_msff_ctl_macro__width_1 condbrf ( | |
2160 | .scan_in(condbrf_scanin), | |
2161 | .scan_out(condbrf_scanout), | |
2162 | .l1clk(l1clk_pm2), | |
2163 | .din (condbr_d), | |
2164 | .dout (condbr_e), | |
2165 | .siclk(siclk), | |
2166 | .soclk(soclk) | |
2167 | ); | |
2168 | ||
2169 | pku_swl_ctl_msff_ctl_macro__width_4 idestf ( | |
2170 | .scan_in(idestf_scanin), | |
2171 | .scan_out(idestf_scanout), | |
2172 | .l1clk(l1clk_pm2), | |
2173 | .din ({idest_d,idest_e,idest_m,idest_b}), | |
2174 | .dout ({idest_e,idest_m,idest_b,idest_w}), | |
2175 | .siclk(siclk), | |
2176 | .soclk(soclk) | |
2177 | ); | |
2178 | ||
2179 | pku_swl_ctl_msff_ctl_macro__width_4 fdestf ( | |
2180 | .scan_in(fdestf_scanin), | |
2181 | .scan_out(fdestf_scanout), | |
2182 | .l1clk(l1clk_pm2), | |
2183 | .din ({fdest_d,fdest_e,fdest_m,fdest_b}), | |
2184 | .dout ({fdest_e,fdest_m,fdest_b,fdest_w}), | |
2185 | .siclk(siclk), | |
2186 | .soclk(soclk) | |
2187 | ); | |
2188 | ||
2189 | pku_swl_ctl_msff_ctl_macro__width_4 specfpf ( | |
2190 | .scan_in(specfpf_scanin), | |
2191 | .scan_out(specfpf_scanout), | |
2192 | .l1clk(l1clk_pm2), | |
2193 | .din ({specfp_d,specfp_e,specfp_m,specfp_b}), | |
2194 | .dout ({specfp_e,specfp_m,specfp_b,specfp_w}), | |
2195 | .siclk(siclk), | |
2196 | .soclk(soclk) | |
2197 | ); | |
2198 | ||
2199 | pku_swl_ctl_msff_ctl_macro__width_7 fbkickf ( | |
2200 | .scan_in(fbkickf_scanin), | |
2201 | .scan_out(fbkickf_scanout), | |
2202 | .l1clk(l1clk_pm2), | |
2203 | .din ({fbkick_d,fbkick_e,fbkick_m,fbkick_b,fbkick_w,fbkick_f4,fbkick_f5}), | |
2204 | .dout ({fbkick_e,fbkick_m,fbkick_b,fbkick_w,fbkick_f4,fbkick_f5,fbkick_fb}), | |
2205 | .siclk(siclk), | |
2206 | .soclk(soclk) | |
2207 | ); | |
2208 | ||
2209 | // on an inst error dec forces all decodes to zero; make pku forget fgu if there is one | |
2210 | ||
2211 | assign fgu_d_in = fgu_d & ~dec_ierr_d & vld_d; | |
2212 | ||
2213 | ||
2214 | pku_swl_ctl_msff_ctl_macro__width_4 fguf ( | |
2215 | .scan_in(fguf_scanin), | |
2216 | .scan_out(fguf_scanout), | |
2217 | .l1clk(l1clk_pm2), | |
2218 | .din ({fgu_d_in,fgu_e,fgu_m,fgu_b}), | |
2219 | .dout ({fgu_e,fgu_m,fgu_b,fgu_w}), | |
2220 | .siclk(siclk), | |
2221 | .soclk(soclk) | |
2222 | ); | |
2223 | ||
2224 | pku_swl_ctl_msff_ctl_macro__width_4 bkickf ( | |
2225 | .scan_in(bkickf_scanin), | |
2226 | .scan_out(bkickf_scanout), | |
2227 | .l1clk(l1clk_pm2), | |
2228 | .din ({bkick_d,bkick_e,bkick_m,bkick_b}), | |
2229 | .dout ({bkick_e,bkick_m,bkick_b,bkick_w}), | |
2230 | .siclk(siclk), | |
2231 | .soclk(soclk) | |
2232 | ); | |
2233 | ||
2234 | pku_swl_ctl_msff_ctl_macro__width_6 fpdest_doublef ( | |
2235 | .scan_in(fpdest_doublef_scanin), | |
2236 | .scan_out(fpdest_doublef_scanout), | |
2237 | .l1clk(l1clk_pm2), | |
2238 | .din ({fpdest_double_d,fpdest_double_e,fpdest_double_m,fpdest_double_b,fpdest_double_w,fpdest_double_f4}), | |
2239 | .dout ({fpdest_double_e,fpdest_double_m,fpdest_double_b,fpdest_double_w,fpdest_double_f4,fpdest_double_f5}), | |
2240 | .siclk(siclk), | |
2241 | .soclk(soclk) | |
2242 | ); | |
2243 | ||
2244 | pku_swl_ctl_msff_ctl_macro__width_6 fpdest_singlef ( | |
2245 | .scan_in(fpdest_singlef_scanin), | |
2246 | .scan_out(fpdest_singlef_scanout), | |
2247 | .l1clk(l1clk_pm2), | |
2248 | .din ({fpdest_single_d,fpdest_single_e,fpdest_single_m,fpdest_single_b,fpdest_single_w,fpdest_single_f4}), | |
2249 | .dout ({fpdest_single_e,fpdest_single_m,fpdest_single_b,fpdest_single_w,fpdest_single_f4,fpdest_single_f5}), | |
2250 | .siclk(siclk), | |
2251 | .soclk(soclk) | |
2252 | ); | |
2253 | ||
2254 | pku_swl_ctl_msff_ctl_macro__width_3 fccdestf ( | |
2255 | .scan_in(fccdestf_scanin), | |
2256 | .scan_out(fccdestf_scanout), | |
2257 | .l1clk(l1clk_pm2), | |
2258 | .din ({fccdest_d,fccdest_e,fccdest_m}), | |
2259 | .dout ({fccdest_e,fccdest_m,fccdest_b}), | |
2260 | .siclk(siclk), | |
2261 | .soclk(soclk) | |
2262 | ); | |
2263 | ||
2264 | // on an inst error dec forces all decodes to zero; make pku forget a load if there is one | |
2265 | ||
2266 | assign lsu_d_in = lsu_d & ~dec_ierr_d & vld_d; | |
2267 | ||
2268 | pku_swl_ctl_msff_ctl_macro__width_6 lsuf ( | |
2269 | .scan_in(lsuf_scanin), | |
2270 | .scan_out(lsuf_scanout), | |
2271 | .l1clk(l1clk_pm2), | |
2272 | .din ({lsu_d_in,lsu_e,lsu_m,lsu_b,lsu_w,lsu_f4}), | |
2273 | .dout ({lsu_e,lsu_m,lsu_b,lsu_w,lsu_f4,lsu_f5}), | |
2274 | .siclk(siclk), | |
2275 | .soclk(soclk) | |
2276 | ); | |
2277 | ||
2278 | // logic to generate internal flushes | |
2279 | // on a flush, all vld latches and wait states clear out the same cycle | |
2280 | // externally, the flush happens 1 cycle later off flop | |
2281 | ||
2282 | // this signal will be late, flop before using | |
2283 | // only sync if something actually went down the pipe after the load | |
2284 | ||
2285 | assign lsu_sync_early = ~pku_flush_lb & (vld_d_in | vld_e_in | vld_m_in | vld_b_in); | |
2286 | ||
2287 | assign lsu_sync_in = lsu_sync & lsu_sync_early; | |
2288 | ||
2289 | pku_swl_ctl_msff_ctl_macro__width_1 lsu_syncf ( | |
2290 | .scan_in(lsu_syncf_scanin), | |
2291 | .scan_out(lsu_syncf_scanout), | |
2292 | .l1clk(l1clk_pm2), | |
2293 | .din (lsu_sync_in), | |
2294 | .dout (lsu_sync_w), | |
2295 | .siclk(siclk), | |
2296 | .soclk(soclk) | |
2297 | ); | |
2298 | ||
2299 | assign lsu_sync_raw_in = lsu_sync & ~pku_flush_lb; | |
2300 | ||
2301 | pku_swl_ctl_msff_ctl_macro__width_1 lsu_sync_rawf ( | |
2302 | .scan_in(lsu_sync_rawf_scanin), | |
2303 | .scan_out(lsu_sync_rawf_scanout), | |
2304 | .l1clk(l1clk_pm2), | |
2305 | .din (lsu_sync_raw_in), | |
2306 | .dout (lsu_sync_raw_w), | |
2307 | .siclk(siclk), | |
2308 | .soclk(soclk) | |
2309 | ); | |
2310 | ||
2311 | // all branches that are taken are cti's | |
2312 | ||
2313 | assign br_mispredict_e = valid_e & dec_br_taken_e; | |
2314 | ||
2315 | // callclass = { call, jmpl, return } for which delay slot is never annuled | |
2316 | // for condbr's only not-taken can be annuled | |
2317 | // all unconditional branches can be annuled | |
2318 | ||
2319 | // rework for timing | |
2320 | // assign annul_ds_dcti_e = ((valid_e & annul_e & condbr_e & ~dec_br_taken_e) | // condbr not taken with a==1 | |
2321 | // (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e)); // branch always with a==1 | |
2322 | ||
2323 | assign pku_annul_ds_dcti_brtaken0_e = ((valid_e & annul_e & condbr_e) | | |
2324 | (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e)); | |
2325 | ||
2326 | assign pku_annul_ds_dcti_brtaken1_e = (valid_e & dcti_e & annul_e & ~condbr_e & ~callclass_e); | |
2327 | ||
2328 | assign annul_ds_dcti_e = (~dec_br_taken_e & pku_annul_ds_dcti_brtaken0_e) | | |
2329 | ( dec_br_taken_e & pku_annul_ds_dcti_brtaken1_e); | |
2330 | ||
2331 | ||
2332 | assign allds_is_p = valid_e & dec_br_taken_e & ~annul_ds_dcti_e & ~vld_d; | |
2333 | assign allds_is_d = valid_e & dec_br_taken_e & ~annul_ds_dcti_e & vld_d; | |
2334 | ||
2335 | // generate flush signals | |
2336 | ||
2337 | // flush internally and externally 1 cycle after event | |
2338 | ||
2339 | // pick can occur in a flush_p situation | |
2340 | // ideally, squash it but dcache_miss or dec_br_taken_e is probably too late ... lru is updated in this case | |
2341 | ||
2342 | // annul_ds_dcti_e flushes the delay slot as needed | |
2343 | // br_mispredict_e flushes everything but the delay slot | |
2344 | // lsu_sync_w flushes everything | |
2345 | ||
2346 | ||
2347 | // late flush using the late br_mispredict and br annul signals | |
2348 | assign late_flush_p = (br_mispredict_e & vld_d) | | |
2349 | (annul_ds_dcti_e & ~vld_d) | | |
2350 | (lsu_sync_w) | | |
2351 | (ext_flush); | |
2352 | ||
2353 | ||
2354 | assign flush_p = (br_mispredict_m & (vld_d | vld_e)) | | |
2355 | (annul_ds_dcti_m & ~vld_d & ~vld_e) | | |
2356 | (lsu_sync_w) | | |
2357 | (ext_flush); | |
2358 | ||
2359 | // for the address logic; no annuling | |
2360 | assign rawflush_p = (br_mispredict_m & (vld_d | vld_e)) | | |
2361 | (lsu_sync_w) | | |
2362 | (ext_flush); | |
2363 | ||
2364 | // all br's that can mispredict are dcti's | |
2365 | ||
2366 | // annul covers br_mispredict_e as well since all branches that mispredict are dctis & annul has precedence over br_mispredict_e | |
2367 | ||
2368 | assign flush_d = (br_mispredict_m & vld_d & vld_e) | | |
2369 | (annul_ds_dcti_m & vld_d & ~vld_e) | | |
2370 | (lsu_sync_w) | | |
2371 | (ext_flush); | |
2372 | ||
2373 | assign rawflush_d = (lsu_sync_w) | | |
2374 | (ext_flush); | |
2375 | ||
2376 | assign flush_e = lsu_ext_flush_w | (annul_ds_dcti_m & vld_e); | |
2377 | assign flush_m = lsu_ext_flush_w; | |
2378 | assign flush_b = lsu_ext_flush_w; | |
2379 | ||
2380 | assign flush_w = ext_flush; | |
2381 | ||
2382 | assign flush_f3 = ext_flush; // internal flush signals | |
2383 | assign flush_f4 = flush_f3; | |
2384 | assign flush_f5 = flush_f3; | |
2385 | ||
2386 | ||
2387 | // external flush signals to IFU | |
2388 | // prioritize so only 1 can fire at a time | |
2389 | // IFU will get trap flush separately | |
2390 | ||
2391 | assign pku_load_flush_w = lsu_sync_w; | |
2392 | ||
2393 | // external flush signals to the instruction buffers | |
2394 | ||
2395 | ||
2396 | // change this logic to always flush the buffers the cycle after the flush event occurs | |
2397 | ||
2398 | assign br_mispredict_m_in = br_mispredict_e; | |
2399 | ||
2400 | pku_swl_ctl_msff_ctl_macro__width_1 br_mispredict_mf ( | |
2401 | .scan_in(br_mispredict_mf_scanin), | |
2402 | .scan_out(br_mispredict_mf_scanout), | |
2403 | .l1clk(l1clk_pm2), | |
2404 | .din (br_mispredict_m_in), | |
2405 | .dout (br_mispredict_m), | |
2406 | .siclk(siclk), | |
2407 | .soclk(soclk) | |
2408 | ); | |
2409 | ||
2410 | assign pku_flush_upper_buffer = br_mispredict_m | lsu_sync_w | ext_flush; | |
2411 | ||
2412 | assign pku_flush_buffer0 = flush_p; | |
2413 | ||
2414 | // on trap will clear out thread in trap unit | |
2415 | ||
2416 | assign flush_m_in = (vld_m_in & tlu_flush_ifu) | | |
2417 | (vld_m_in & lsu_sync); | |
2418 | ||
2419 | // generate right off flop for timing | |
2420 | pku_swl_ctl_msff_ctl_macro__width_1 flush_mf ( | |
2421 | .scan_in(flush_mf_scanin), | |
2422 | .scan_out(flush_mf_scanout), | |
2423 | .l1clk(l1clk_pm2), | |
2424 | .din (flush_m_in), | |
2425 | .dout (pku_flush_m), | |
2426 | .siclk(siclk), | |
2427 | .soclk(soclk) | |
2428 | ); | |
2429 | ||
2430 | assign pku_flush_b = vld_b & lsu_ext_flush_w; | |
2431 | ||
2432 | // trap handles w stage | |
2433 | assign pku_flush_lm = vld_m & lsu_m & lsu_ext_flush_w; | |
2434 | assign pku_flush_lb = vld_b & lsu_b & lsu_ext_flush_w; | |
2435 | ||
2436 | // flush signals to the fgu; trap handles f3 which is w stage | |
2437 | assign pku_flush_f1 = vld_m & fgu_m & lsu_ext_flush_w; | |
2438 | assign pku_flush_f2 = vld_b & fgu_b & lsu_ext_flush_w; | |
2439 | ||
2440 | ||
2441 | // unused bits | |
2442 | assign i_unused[6:0] = {i[15],i[14],i[4:0]}; | |
2443 | ||
2444 | supply0 vss; | |
2445 | supply1 vdd; | |
2446 | ||
2447 | // fixscan start: | |
2448 | assign spares_scanin = scan_in ; | |
2449 | assign do_modef_scanin = spares_scanout ; | |
2450 | assign external_flushf_scanin = do_modef_scanout ; | |
2451 | assign lsu_ext_flushf_scanin = external_flushf_scanout ; | |
2452 | assign tlu_retryf_scanin = lsu_ext_flushf_scanout ; | |
2453 | assign block_store_stallf_scanin = tlu_retryf_scanout ; | |
2454 | assign post_syncf_scanin = block_store_stallf_scanout; | |
2455 | assign spec_enf_scanin = post_syncf_scanout ; | |
2456 | assign active_threadf_scanin = spec_enf_scanout ; | |
2457 | assign postsync_nsf_scanin = active_threadf_scanout ; | |
2458 | assign divide_waitf_scanin = postsync_nsf_scanout ; | |
2459 | assign divide_wait1f_scanin = divide_waitf_scanout ; | |
2460 | assign lsu_completef_scanin = divide_wait1f_scanout ; | |
2461 | assign lsu_sync_waitf_scanin = lsu_completef_scanout ; | |
2462 | assign ldst_sync_singlef_scanin = lsu_sync_waitf_scanout ; | |
2463 | assign ldst_sync_ldfsrf_scanin = ldst_sync_singlef_scanout; | |
2464 | assign brflush1_f_scanin = ldst_sync_ldfsrf_scanout ; | |
2465 | assign brflush2_f_scanin = brflush1_f_scanout ; | |
2466 | assign not_annul_ds1_f_scanin = brflush2_f_scanout ; | |
2467 | assign not_annul_ds2_f_scanin = not_annul_ds1_f_scanout ; | |
2468 | assign store_ds1_f_scanin = not_annul_ds2_f_scanout ; | |
2469 | assign store_ds2_f_scanin = store_ds1_f_scanout ; | |
2470 | assign pickstoref_scanin = store_ds2_f_scanout ; | |
2471 | assign annul_store_f_scanin = pickstoref_scanout ; | |
2472 | assign scnt_f_scanin = annul_store_f_scanout ; | |
2473 | assign ccnt_f_scanin = scnt_f_scanout ; | |
2474 | assign readyf_scanin = ccnt_f_scanout ; | |
2475 | assign spec_readyf_scanin = readyf_scanout ; | |
2476 | assign allds_p_f_scanin = spec_readyf_scanout ; | |
2477 | assign allds_d_f_scanin = allds_p_f_scanout ; | |
2478 | assign allds_e_f_scanin = allds_d_f_scanout ; | |
2479 | assign vld_df_scanin = allds_e_f_scanout ; | |
2480 | assign vld_ef_scanin = vld_df_scanout ; | |
2481 | assign valid_ef_scanin = vld_ef_scanout ; | |
2482 | assign vld_mf_scanin = valid_ef_scanout ; | |
2483 | assign vld_bf_scanin = vld_mf_scanout ; | |
2484 | assign vld_wf_scanin = vld_bf_scanout ; | |
2485 | assign fpvld_w1f_scanin = vld_wf_scanout ; | |
2486 | assign fpvld_w2f_scanin = fpvld_w1f_scanout ; | |
2487 | assign vldraw_df_scanin = fpvld_w2f_scanout ; | |
2488 | assign vldraw_ef_scanin = vldraw_df_scanout ; | |
2489 | assign vldraw_mf_scanin = vldraw_ef_scanout ; | |
2490 | assign annul_ds_dcti_mf_scanin = vldraw_mf_scanout ; | |
2491 | assign vld_f4f_scanin = annul_ds_dcti_mf_scanout ; | |
2492 | assign vld_f5f_scanin = vld_f4f_scanout ; | |
2493 | assign vld_fbf_scanin = vld_f5f_scanout ; | |
2494 | assign data_df_scanin = vld_fbf_scanout ; | |
2495 | assign rdf_scanin = data_df_scanout ; | |
2496 | assign anytwocyclef_scanin = rdf_scanout ; | |
2497 | assign specldf_scanin = anytwocyclef_scanout ; | |
2498 | assign postsyncf_scanin = specldf_scanout ; | |
2499 | assign divf_scanin = postsyncf_scanout ; | |
2500 | assign dctif_scanin = divf_scanout ; | |
2501 | assign specbref_scanin = dctif_scanout ; | |
2502 | assign specbrmf_scanin = specbref_scanout ; | |
2503 | assign annulf_scanin = specbrmf_scanout ; | |
2504 | assign callclassf_scanin = annulf_scanout ; | |
2505 | assign condbrf_scanin = callclassf_scanout ; | |
2506 | assign idestf_scanin = condbrf_scanout ; | |
2507 | assign fdestf_scanin = idestf_scanout ; | |
2508 | assign specfpf_scanin = fdestf_scanout ; | |
2509 | assign fbkickf_scanin = specfpf_scanout ; | |
2510 | assign fguf_scanin = fbkickf_scanout ; | |
2511 | assign bkickf_scanin = fguf_scanout ; | |
2512 | assign fpdest_doublef_scanin = bkickf_scanout ; | |
2513 | assign fpdest_singlef_scanin = fpdest_doublef_scanout ; | |
2514 | assign fccdestf_scanin = fpdest_singlef_scanout ; | |
2515 | assign lsuf_scanin = fccdestf_scanout ; | |
2516 | assign lsu_syncf_scanin = lsuf_scanout ; | |
2517 | assign lsu_sync_rawf_scanin = lsu_syncf_scanout ; | |
2518 | assign br_mispredict_mf_scanin = lsu_sync_rawf_scanout ; | |
2519 | assign flush_mf_scanin = br_mispredict_mf_scanout ; | |
2520 | assign scan_out = flush_mf_scanout ; | |
2521 | // fixscan end: | |
2522 | endmodule | |
2523 | ||
2524 | ||
2525 | ||
2526 | ||
2527 | ||
2528 | ||
2529 | ||
2530 | // any PARAMS parms go into naming of macro | |
2531 | ||
2532 | module pku_swl_ctl_l1clkhdr_ctl_macro ( | |
2533 | l2clk, | |
2534 | l1en, | |
2535 | pce_ov, | |
2536 | stop, | |
2537 | se, | |
2538 | l1clk); | |
2539 | ||
2540 | ||
2541 | input l2clk; | |
2542 | input l1en; | |
2543 | input pce_ov; | |
2544 | input stop; | |
2545 | input se; | |
2546 | output l1clk; | |
2547 | ||
2548 | ||
2549 | ||
2550 | ||
2551 | ||
2552 | cl_sc1_l1hdr_8x c_0 ( | |
2553 | ||
2554 | ||
2555 | .l2clk(l2clk), | |
2556 | .pce(l1en), | |
2557 | .l1clk(l1clk), | |
2558 | .se(se), | |
2559 | .pce_ov(pce_ov), | |
2560 | .stop(stop) | |
2561 | ); | |
2562 | ||
2563 | ||
2564 | ||
2565 | endmodule | |
2566 | ||
2567 | ||
2568 | ||
2569 | ||
2570 | ||
2571 | ||
2572 | ||
2573 | ||
2574 | ||
2575 | // Description: Spare gate macro for control blocks | |
2576 | // | |
2577 | // Param num controls the number of times the macro is added | |
2578 | // flops=0 can be used to use only combination spare logic | |
2579 | ||
2580 | ||
2581 | module pku_swl_ctl_spare_ctl_macro__num_4 ( | |
2582 | l1clk, | |
2583 | scan_in, | |
2584 | siclk, | |
2585 | soclk, | |
2586 | scan_out); | |
2587 | wire si_0; | |
2588 | wire so_0; | |
2589 | wire spare0_flop_unused; | |
2590 | wire spare0_buf_32x_unused; | |
2591 | wire spare0_nand3_8x_unused; | |
2592 | wire spare0_inv_8x_unused; | |
2593 | wire spare0_aoi22_4x_unused; | |
2594 | wire spare0_buf_8x_unused; | |
2595 | wire spare0_oai22_4x_unused; | |
2596 | wire spare0_inv_16x_unused; | |
2597 | wire spare0_nand2_16x_unused; | |
2598 | wire spare0_nor3_4x_unused; | |
2599 | wire spare0_nand2_8x_unused; | |
2600 | wire spare0_buf_16x_unused; | |
2601 | wire spare0_nor2_16x_unused; | |
2602 | wire spare0_inv_32x_unused; | |
2603 | wire si_1; | |
2604 | wire so_1; | |
2605 | wire spare1_flop_unused; | |
2606 | wire spare1_buf_32x_unused; | |
2607 | wire spare1_nand3_8x_unused; | |
2608 | wire spare1_inv_8x_unused; | |
2609 | wire spare1_aoi22_4x_unused; | |
2610 | wire spare1_buf_8x_unused; | |
2611 | wire spare1_oai22_4x_unused; | |
2612 | wire spare1_inv_16x_unused; | |
2613 | wire spare1_nand2_16x_unused; | |
2614 | wire spare1_nor3_4x_unused; | |
2615 | wire spare1_nand2_8x_unused; | |
2616 | wire spare1_buf_16x_unused; | |
2617 | wire spare1_nor2_16x_unused; | |
2618 | wire spare1_inv_32x_unused; | |
2619 | wire si_2; | |
2620 | wire so_2; | |
2621 | wire spare2_flop_unused; | |
2622 | wire spare2_buf_32x_unused; | |
2623 | wire spare2_nand3_8x_unused; | |
2624 | wire spare2_inv_8x_unused; | |
2625 | wire spare2_aoi22_4x_unused; | |
2626 | wire spare2_buf_8x_unused; | |
2627 | wire spare2_oai22_4x_unused; | |
2628 | wire spare2_inv_16x_unused; | |
2629 | wire spare2_nand2_16x_unused; | |
2630 | wire spare2_nor3_4x_unused; | |
2631 | wire spare2_nand2_8x_unused; | |
2632 | wire spare2_buf_16x_unused; | |
2633 | wire spare2_nor2_16x_unused; | |
2634 | wire spare2_inv_32x_unused; | |
2635 | wire si_3; | |
2636 | wire so_3; | |
2637 | wire spare3_flop_unused; | |
2638 | wire spare3_buf_32x_unused; | |
2639 | wire spare3_nand3_8x_unused; | |
2640 | wire spare3_inv_8x_unused; | |
2641 | wire spare3_aoi22_4x_unused; | |
2642 | wire spare3_buf_8x_unused; | |
2643 | wire spare3_oai22_4x_unused; | |
2644 | wire spare3_inv_16x_unused; | |
2645 | wire spare3_nand2_16x_unused; | |
2646 | wire spare3_nor3_4x_unused; | |
2647 | wire spare3_nand2_8x_unused; | |
2648 | wire spare3_buf_16x_unused; | |
2649 | wire spare3_nor2_16x_unused; | |
2650 | wire spare3_inv_32x_unused; | |
2651 | ||
2652 | ||
2653 | input l1clk; | |
2654 | input scan_in; | |
2655 | input siclk; | |
2656 | input soclk; | |
2657 | output scan_out; | |
2658 | ||
2659 | cl_sc1_msff_8x spare0_flop (.l1clk(l1clk), | |
2660 | .siclk(siclk), | |
2661 | .soclk(soclk), | |
2662 | .si(si_0), | |
2663 | .so(so_0), | |
2664 | .d(1'b0), | |
2665 | .q(spare0_flop_unused)); | |
2666 | assign si_0 = scan_in; | |
2667 | ||
2668 | cl_u1_buf_32x spare0_buf_32x (.in(1'b1), | |
2669 | .out(spare0_buf_32x_unused)); | |
2670 | cl_u1_nand3_8x spare0_nand3_8x (.in0(1'b1), | |
2671 | .in1(1'b1), | |
2672 | .in2(1'b1), | |
2673 | .out(spare0_nand3_8x_unused)); | |
2674 | cl_u1_inv_8x spare0_inv_8x (.in(1'b1), | |
2675 | .out(spare0_inv_8x_unused)); | |
2676 | cl_u1_aoi22_4x spare0_aoi22_4x (.in00(1'b1), | |
2677 | .in01(1'b1), | |
2678 | .in10(1'b1), | |
2679 | .in11(1'b1), | |
2680 | .out(spare0_aoi22_4x_unused)); | |
2681 | cl_u1_buf_8x spare0_buf_8x (.in(1'b1), | |
2682 | .out(spare0_buf_8x_unused)); | |
2683 | cl_u1_oai22_4x spare0_oai22_4x (.in00(1'b1), | |
2684 | .in01(1'b1), | |
2685 | .in10(1'b1), | |
2686 | .in11(1'b1), | |
2687 | .out(spare0_oai22_4x_unused)); | |
2688 | cl_u1_inv_16x spare0_inv_16x (.in(1'b1), | |
2689 | .out(spare0_inv_16x_unused)); | |
2690 | cl_u1_nand2_16x spare0_nand2_16x (.in0(1'b1), | |
2691 | .in1(1'b1), | |
2692 | .out(spare0_nand2_16x_unused)); | |
2693 | cl_u1_nor3_4x spare0_nor3_4x (.in0(1'b0), | |
2694 | .in1(1'b0), | |
2695 | .in2(1'b0), | |
2696 | .out(spare0_nor3_4x_unused)); | |
2697 | cl_u1_nand2_8x spare0_nand2_8x (.in0(1'b1), | |
2698 | .in1(1'b1), | |
2699 | .out(spare0_nand2_8x_unused)); | |
2700 | cl_u1_buf_16x spare0_buf_16x (.in(1'b1), | |
2701 | .out(spare0_buf_16x_unused)); | |
2702 | cl_u1_nor2_16x spare0_nor2_16x (.in0(1'b0), | |
2703 | .in1(1'b0), | |
2704 | .out(spare0_nor2_16x_unused)); | |
2705 | cl_u1_inv_32x spare0_inv_32x (.in(1'b1), | |
2706 | .out(spare0_inv_32x_unused)); | |
2707 | ||
2708 | cl_sc1_msff_8x spare1_flop (.l1clk(l1clk), | |
2709 | .siclk(siclk), | |
2710 | .soclk(soclk), | |
2711 | .si(si_1), | |
2712 | .so(so_1), | |
2713 | .d(1'b0), | |
2714 | .q(spare1_flop_unused)); | |
2715 | assign si_1 = so_0; | |
2716 | ||
2717 | cl_u1_buf_32x spare1_buf_32x (.in(1'b1), | |
2718 | .out(spare1_buf_32x_unused)); | |
2719 | cl_u1_nand3_8x spare1_nand3_8x (.in0(1'b1), | |
2720 | .in1(1'b1), | |
2721 | .in2(1'b1), | |
2722 | .out(spare1_nand3_8x_unused)); | |
2723 | cl_u1_inv_8x spare1_inv_8x (.in(1'b1), | |
2724 | .out(spare1_inv_8x_unused)); | |
2725 | cl_u1_aoi22_4x spare1_aoi22_4x (.in00(1'b1), | |
2726 | .in01(1'b1), | |
2727 | .in10(1'b1), | |
2728 | .in11(1'b1), | |
2729 | .out(spare1_aoi22_4x_unused)); | |
2730 | cl_u1_buf_8x spare1_buf_8x (.in(1'b1), | |
2731 | .out(spare1_buf_8x_unused)); | |
2732 | cl_u1_oai22_4x spare1_oai22_4x (.in00(1'b1), | |
2733 | .in01(1'b1), | |
2734 | .in10(1'b1), | |
2735 | .in11(1'b1), | |
2736 | .out(spare1_oai22_4x_unused)); | |
2737 | cl_u1_inv_16x spare1_inv_16x (.in(1'b1), | |
2738 | .out(spare1_inv_16x_unused)); | |
2739 | cl_u1_nand2_16x spare1_nand2_16x (.in0(1'b1), | |
2740 | .in1(1'b1), | |
2741 | .out(spare1_nand2_16x_unused)); | |
2742 | cl_u1_nor3_4x spare1_nor3_4x (.in0(1'b0), | |
2743 | .in1(1'b0), | |
2744 | .in2(1'b0), | |
2745 | .out(spare1_nor3_4x_unused)); | |
2746 | cl_u1_nand2_8x spare1_nand2_8x (.in0(1'b1), | |
2747 | .in1(1'b1), | |
2748 | .out(spare1_nand2_8x_unused)); | |
2749 | cl_u1_buf_16x spare1_buf_16x (.in(1'b1), | |
2750 | .out(spare1_buf_16x_unused)); | |
2751 | cl_u1_nor2_16x spare1_nor2_16x (.in0(1'b0), | |
2752 | .in1(1'b0), | |
2753 | .out(spare1_nor2_16x_unused)); | |
2754 | cl_u1_inv_32x spare1_inv_32x (.in(1'b1), | |
2755 | .out(spare1_inv_32x_unused)); | |
2756 | ||
2757 | cl_sc1_msff_8x spare2_flop (.l1clk(l1clk), | |
2758 | .siclk(siclk), | |
2759 | .soclk(soclk), | |
2760 | .si(si_2), | |
2761 | .so(so_2), | |
2762 | .d(1'b0), | |
2763 | .q(spare2_flop_unused)); | |
2764 | assign si_2 = so_1; | |
2765 | ||
2766 | cl_u1_buf_32x spare2_buf_32x (.in(1'b1), | |
2767 | .out(spare2_buf_32x_unused)); | |
2768 | cl_u1_nand3_8x spare2_nand3_8x (.in0(1'b1), | |
2769 | .in1(1'b1), | |
2770 | .in2(1'b1), | |
2771 | .out(spare2_nand3_8x_unused)); | |
2772 | cl_u1_inv_8x spare2_inv_8x (.in(1'b1), | |
2773 | .out(spare2_inv_8x_unused)); | |
2774 | cl_u1_aoi22_4x spare2_aoi22_4x (.in00(1'b1), | |
2775 | .in01(1'b1), | |
2776 | .in10(1'b1), | |
2777 | .in11(1'b1), | |
2778 | .out(spare2_aoi22_4x_unused)); | |
2779 | cl_u1_buf_8x spare2_buf_8x (.in(1'b1), | |
2780 | .out(spare2_buf_8x_unused)); | |
2781 | cl_u1_oai22_4x spare2_oai22_4x (.in00(1'b1), | |
2782 | .in01(1'b1), | |
2783 | .in10(1'b1), | |
2784 | .in11(1'b1), | |
2785 | .out(spare2_oai22_4x_unused)); | |
2786 | cl_u1_inv_16x spare2_inv_16x (.in(1'b1), | |
2787 | .out(spare2_inv_16x_unused)); | |
2788 | cl_u1_nand2_16x spare2_nand2_16x (.in0(1'b1), | |
2789 | .in1(1'b1), | |
2790 | .out(spare2_nand2_16x_unused)); | |
2791 | cl_u1_nor3_4x spare2_nor3_4x (.in0(1'b0), | |
2792 | .in1(1'b0), | |
2793 | .in2(1'b0), | |
2794 | .out(spare2_nor3_4x_unused)); | |
2795 | cl_u1_nand2_8x spare2_nand2_8x (.in0(1'b1), | |
2796 | .in1(1'b1), | |
2797 | .out(spare2_nand2_8x_unused)); | |
2798 | cl_u1_buf_16x spare2_buf_16x (.in(1'b1), | |
2799 | .out(spare2_buf_16x_unused)); | |
2800 | cl_u1_nor2_16x spare2_nor2_16x (.in0(1'b0), | |
2801 | .in1(1'b0), | |
2802 | .out(spare2_nor2_16x_unused)); | |
2803 | cl_u1_inv_32x spare2_inv_32x (.in(1'b1), | |
2804 | .out(spare2_inv_32x_unused)); | |
2805 | ||
2806 | cl_sc1_msff_8x spare3_flop (.l1clk(l1clk), | |
2807 | .siclk(siclk), | |
2808 | .soclk(soclk), | |
2809 | .si(si_3), | |
2810 | .so(so_3), | |
2811 | .d(1'b0), | |
2812 | .q(spare3_flop_unused)); | |
2813 | assign si_3 = so_2; | |
2814 | ||
2815 | cl_u1_buf_32x spare3_buf_32x (.in(1'b1), | |
2816 | .out(spare3_buf_32x_unused)); | |
2817 | cl_u1_nand3_8x spare3_nand3_8x (.in0(1'b1), | |
2818 | .in1(1'b1), | |
2819 | .in2(1'b1), | |
2820 | .out(spare3_nand3_8x_unused)); | |
2821 | cl_u1_inv_8x spare3_inv_8x (.in(1'b1), | |
2822 | .out(spare3_inv_8x_unused)); | |
2823 | cl_u1_aoi22_4x spare3_aoi22_4x (.in00(1'b1), | |
2824 | .in01(1'b1), | |
2825 | .in10(1'b1), | |
2826 | .in11(1'b1), | |
2827 | .out(spare3_aoi22_4x_unused)); | |
2828 | cl_u1_buf_8x spare3_buf_8x (.in(1'b1), | |
2829 | .out(spare3_buf_8x_unused)); | |
2830 | cl_u1_oai22_4x spare3_oai22_4x (.in00(1'b1), | |
2831 | .in01(1'b1), | |
2832 | .in10(1'b1), | |
2833 | .in11(1'b1), | |
2834 | .out(spare3_oai22_4x_unused)); | |
2835 | cl_u1_inv_16x spare3_inv_16x (.in(1'b1), | |
2836 | .out(spare3_inv_16x_unused)); | |
2837 | cl_u1_nand2_16x spare3_nand2_16x (.in0(1'b1), | |
2838 | .in1(1'b1), | |
2839 | .out(spare3_nand2_16x_unused)); | |
2840 | cl_u1_nor3_4x spare3_nor3_4x (.in0(1'b0), | |
2841 | .in1(1'b0), | |
2842 | .in2(1'b0), | |
2843 | .out(spare3_nor3_4x_unused)); | |
2844 | cl_u1_nand2_8x spare3_nand2_8x (.in0(1'b1), | |
2845 | .in1(1'b1), | |
2846 | .out(spare3_nand2_8x_unused)); | |
2847 | cl_u1_buf_16x spare3_buf_16x (.in(1'b1), | |
2848 | .out(spare3_buf_16x_unused)); | |
2849 | cl_u1_nor2_16x spare3_nor2_16x (.in0(1'b0), | |
2850 | .in1(1'b0), | |
2851 | .out(spare3_nor2_16x_unused)); | |
2852 | cl_u1_inv_32x spare3_inv_32x (.in(1'b1), | |
2853 | .out(spare3_inv_32x_unused)); | |
2854 | assign scan_out = so_3; | |
2855 | ||
2856 | ||
2857 | ||
2858 | endmodule | |
2859 | ||
2860 | ||
2861 | ||
2862 | ||
2863 | ||
2864 | ||
2865 | // any PARAMS parms go into naming of macro | |
2866 | ||
2867 | module pku_swl_ctl_msff_ctl_macro__width_1 ( | |
2868 | din, | |
2869 | l1clk, | |
2870 | scan_in, | |
2871 | siclk, | |
2872 | soclk, | |
2873 | dout, | |
2874 | scan_out); | |
2875 | wire [0:0] fdin; | |
2876 | ||
2877 | input [0:0] din; | |
2878 | input l1clk; | |
2879 | input scan_in; | |
2880 | ||
2881 | ||
2882 | input siclk; | |
2883 | input soclk; | |
2884 | ||
2885 | output [0:0] dout; | |
2886 | output scan_out; | |
2887 | assign fdin[0:0] = din[0:0]; | |
2888 | ||
2889 | ||
2890 | ||
2891 | ||
2892 | ||
2893 | ||
2894 | dff #(1) d0_0 ( | |
2895 | .l1clk(l1clk), | |
2896 | .siclk(siclk), | |
2897 | .soclk(soclk), | |
2898 | .d(fdin[0:0]), | |
2899 | .si(scan_in), | |
2900 | .so(scan_out), | |
2901 | .q(dout[0:0]) | |
2902 | ); | |
2903 | ||
2904 | ||
2905 | ||
2906 | ||
2907 | ||
2908 | ||
2909 | ||
2910 | ||
2911 | ||
2912 | ||
2913 | ||
2914 | ||
2915 | endmodule | |
2916 | ||
2917 | ||
2918 | ||
2919 | ||
2920 | ||
2921 | ||
2922 | ||
2923 | ||
2924 | ||
2925 | ||
2926 | ||
2927 | ||
2928 | ||
2929 | // any PARAMS parms go into naming of macro | |
2930 | ||
2931 | module pku_swl_ctl_msff_ctl_macro__width_2 ( | |
2932 | din, | |
2933 | l1clk, | |
2934 | scan_in, | |
2935 | siclk, | |
2936 | soclk, | |
2937 | dout, | |
2938 | scan_out); | |
2939 | wire [1:0] fdin; | |
2940 | wire [0:0] so; | |
2941 | ||
2942 | input [1:0] din; | |
2943 | input l1clk; | |
2944 | input scan_in; | |
2945 | ||
2946 | ||
2947 | input siclk; | |
2948 | input soclk; | |
2949 | ||
2950 | output [1:0] dout; | |
2951 | output scan_out; | |
2952 | assign fdin[1:0] = din[1:0]; | |
2953 | ||
2954 | ||
2955 | ||
2956 | ||
2957 | ||
2958 | ||
2959 | dff #(2) d0_0 ( | |
2960 | .l1clk(l1clk), | |
2961 | .siclk(siclk), | |
2962 | .soclk(soclk), | |
2963 | .d(fdin[1:0]), | |
2964 | .si({scan_in,so[0:0]}), | |
2965 | .so({so[0:0],scan_out}), | |
2966 | .q(dout[1:0]) | |
2967 | ); | |
2968 | ||
2969 | ||
2970 | ||
2971 | ||
2972 | ||
2973 | ||
2974 | ||
2975 | ||
2976 | ||
2977 | ||
2978 | ||
2979 | ||
2980 | endmodule | |
2981 | ||
2982 | ||
2983 | ||
2984 | ||
2985 | ||
2986 | ||
2987 | ||
2988 | ||
2989 | ||
2990 | ||
2991 | ||
2992 | ||
2993 | ||
2994 | // any PARAMS parms go into naming of macro | |
2995 | ||
2996 | module pku_swl_ctl_msff_ctl_macro__width_4 ( | |
2997 | din, | |
2998 | l1clk, | |
2999 | scan_in, | |
3000 | siclk, | |
3001 | soclk, | |
3002 | dout, | |
3003 | scan_out); | |
3004 | wire [3:0] fdin; | |
3005 | wire [2:0] so; | |
3006 | ||
3007 | input [3:0] din; | |
3008 | input l1clk; | |
3009 | input scan_in; | |
3010 | ||
3011 | ||
3012 | input siclk; | |
3013 | input soclk; | |
3014 | ||
3015 | output [3:0] dout; | |
3016 | output scan_out; | |
3017 | assign fdin[3:0] = din[3:0]; | |
3018 | ||
3019 | ||
3020 | ||
3021 | ||
3022 | ||
3023 | ||
3024 | dff #(4) d0_0 ( | |
3025 | .l1clk(l1clk), | |
3026 | .siclk(siclk), | |
3027 | .soclk(soclk), | |
3028 | .d(fdin[3:0]), | |
3029 | .si({scan_in,so[2:0]}), | |
3030 | .so({so[2:0],scan_out}), | |
3031 | .q(dout[3:0]) | |
3032 | ); | |
3033 | ||
3034 | ||
3035 | ||
3036 | ||
3037 | ||
3038 | ||
3039 | ||
3040 | ||
3041 | ||
3042 | ||
3043 | ||
3044 | ||
3045 | endmodule | |
3046 | ||
3047 | ||
3048 | ||
3049 | ||
3050 | ||
3051 | ||
3052 | ||
3053 | ||
3054 | ||
3055 | ||
3056 | ||
3057 | ||
3058 | ||
3059 | // any PARAMS parms go into naming of macro | |
3060 | ||
3061 | module pku_swl_ctl_msff_ctl_macro__width_24 ( | |
3062 | din, | |
3063 | l1clk, | |
3064 | scan_in, | |
3065 | siclk, | |
3066 | soclk, | |
3067 | dout, | |
3068 | scan_out); | |
3069 | wire [23:0] fdin; | |
3070 | wire [22:0] so; | |
3071 | ||
3072 | input [23:0] din; | |
3073 | input l1clk; | |
3074 | input scan_in; | |
3075 | ||
3076 | ||
3077 | input siclk; | |
3078 | input soclk; | |
3079 | ||
3080 | output [23:0] dout; | |
3081 | output scan_out; | |
3082 | assign fdin[23:0] = din[23:0]; | |
3083 | ||
3084 | ||
3085 | ||
3086 | ||
3087 | ||
3088 | ||
3089 | dff #(24) d0_0 ( | |
3090 | .l1clk(l1clk), | |
3091 | .siclk(siclk), | |
3092 | .soclk(soclk), | |
3093 | .d(fdin[23:0]), | |
3094 | .si({scan_in,so[22:0]}), | |
3095 | .so({so[22:0],scan_out}), | |
3096 | .q(dout[23:0]) | |
3097 | ); | |
3098 | ||
3099 | ||
3100 | ||
3101 | ||
3102 | ||
3103 | ||
3104 | ||
3105 | ||
3106 | ||
3107 | ||
3108 | ||
3109 | ||
3110 | endmodule | |
3111 | ||
3112 | ||
3113 | ||
3114 | ||
3115 | ||
3116 | ||
3117 | ||
3118 | ||
3119 | ||
3120 | ||
3121 | ||
3122 | ||
3123 | ||
3124 | // any PARAMS parms go into naming of macro | |
3125 | ||
3126 | module pku_swl_ctl_msff_ctl_macro__width_20 ( | |
3127 | din, | |
3128 | l1clk, | |
3129 | scan_in, | |
3130 | siclk, | |
3131 | soclk, | |
3132 | dout, | |
3133 | scan_out); | |
3134 | wire [19:0] fdin; | |
3135 | wire [18:0] so; | |
3136 | ||
3137 | input [19:0] din; | |
3138 | input l1clk; | |
3139 | input scan_in; | |
3140 | ||
3141 | ||
3142 | input siclk; | |
3143 | input soclk; | |
3144 | ||
3145 | output [19:0] dout; | |
3146 | output scan_out; | |
3147 | assign fdin[19:0] = din[19:0]; | |
3148 | ||
3149 | ||
3150 | ||
3151 | ||
3152 | ||
3153 | ||
3154 | dff #(20) d0_0 ( | |
3155 | .l1clk(l1clk), | |
3156 | .siclk(siclk), | |
3157 | .soclk(soclk), | |
3158 | .d(fdin[19:0]), | |
3159 | .si({scan_in,so[18:0]}), | |
3160 | .so({so[18:0],scan_out}), | |
3161 | .q(dout[19:0]) | |
3162 | ); | |
3163 | ||
3164 | ||
3165 | ||
3166 | ||
3167 | ||
3168 | ||
3169 | ||
3170 | ||
3171 | ||
3172 | ||
3173 | ||
3174 | ||
3175 | endmodule | |
3176 | ||
3177 | ||
3178 | ||
3179 | ||
3180 | ||
3181 | ||
3182 | ||
3183 | ||
3184 | ||
3185 | ||
3186 | ||
3187 | ||
3188 | ||
3189 | // any PARAMS parms go into naming of macro | |
3190 | ||
3191 | module pku_swl_ctl_msff_ctl_macro__width_7 ( | |
3192 | din, | |
3193 | l1clk, | |
3194 | scan_in, | |
3195 | siclk, | |
3196 | soclk, | |
3197 | dout, | |
3198 | scan_out); | |
3199 | wire [6:0] fdin; | |
3200 | wire [5:0] so; | |
3201 | ||
3202 | input [6:0] din; | |
3203 | input l1clk; | |
3204 | input scan_in; | |
3205 | ||
3206 | ||
3207 | input siclk; | |
3208 | input soclk; | |
3209 | ||
3210 | output [6:0] dout; | |
3211 | output scan_out; | |
3212 | assign fdin[6:0] = din[6:0]; | |
3213 | ||
3214 | ||
3215 | ||
3216 | ||
3217 | ||
3218 | ||
3219 | dff #(7) d0_0 ( | |
3220 | .l1clk(l1clk), | |
3221 | .siclk(siclk), | |
3222 | .soclk(soclk), | |
3223 | .d(fdin[6:0]), | |
3224 | .si({scan_in,so[5:0]}), | |
3225 | .so({so[5:0],scan_out}), | |
3226 | .q(dout[6:0]) | |
3227 | ); | |
3228 | ||
3229 | ||
3230 | ||
3231 | ||
3232 | ||
3233 | ||
3234 | ||
3235 | ||
3236 | ||
3237 | ||
3238 | ||
3239 | ||
3240 | endmodule | |
3241 | ||
3242 | ||
3243 | ||
3244 | ||
3245 | ||
3246 | ||
3247 | ||
3248 | ||
3249 | ||
3250 | ||
3251 | ||
3252 | ||
3253 | ||
3254 | // any PARAMS parms go into naming of macro | |
3255 | ||
3256 | module pku_swl_ctl_msff_ctl_macro__width_6 ( | |
3257 | din, | |
3258 | l1clk, | |
3259 | scan_in, | |
3260 | siclk, | |
3261 | soclk, | |
3262 | dout, | |
3263 | scan_out); | |
3264 | wire [5:0] fdin; | |
3265 | wire [4:0] so; | |
3266 | ||
3267 | input [5:0] din; | |
3268 | input l1clk; | |
3269 | input scan_in; | |
3270 | ||
3271 | ||
3272 | input siclk; | |
3273 | input soclk; | |
3274 | ||
3275 | output [5:0] dout; | |
3276 | output scan_out; | |
3277 | assign fdin[5:0] = din[5:0]; | |
3278 | ||
3279 | ||
3280 | ||
3281 | ||
3282 | ||
3283 | ||
3284 | dff #(6) d0_0 ( | |
3285 | .l1clk(l1clk), | |
3286 | .siclk(siclk), | |
3287 | .soclk(soclk), | |
3288 | .d(fdin[5:0]), | |
3289 | .si({scan_in,so[4:0]}), | |
3290 | .so({so[4:0],scan_out}), | |
3291 | .q(dout[5:0]) | |
3292 | ); | |
3293 | ||
3294 | ||
3295 | ||
3296 | ||
3297 | ||
3298 | ||
3299 | ||
3300 | ||
3301 | ||
3302 | ||
3303 | ||
3304 | ||
3305 | endmodule | |
3306 | ||
3307 | ||
3308 | ||
3309 | ||
3310 | ||
3311 | ||
3312 | ||
3313 | ||
3314 | ||
3315 | ||
3316 | ||
3317 | ||
3318 | ||
3319 | // any PARAMS parms go into naming of macro | |
3320 | ||
3321 | module pku_swl_ctl_msff_ctl_macro__width_3 ( | |
3322 | din, | |
3323 | l1clk, | |
3324 | scan_in, | |
3325 | siclk, | |
3326 | soclk, | |
3327 | dout, | |
3328 | scan_out); | |
3329 | wire [2:0] fdin; | |
3330 | wire [1:0] so; | |
3331 | ||
3332 | input [2:0] din; | |
3333 | input l1clk; | |
3334 | input scan_in; | |
3335 | ||
3336 | ||
3337 | input siclk; | |
3338 | input soclk; | |
3339 | ||
3340 | output [2:0] dout; | |
3341 | output scan_out; | |
3342 | assign fdin[2:0] = din[2:0]; | |
3343 | ||
3344 | ||
3345 | ||
3346 | ||
3347 | ||
3348 | ||
3349 | dff #(3) d0_0 ( | |
3350 | .l1clk(l1clk), | |
3351 | .siclk(siclk), | |
3352 | .soclk(soclk), | |
3353 | .d(fdin[2:0]), | |
3354 | .si({scan_in,so[1:0]}), | |
3355 | .so({so[1:0],scan_out}), | |
3356 | .q(dout[2:0]) | |
3357 | ); | |
3358 | ||
3359 | ||
3360 | ||
3361 | ||
3362 | ||
3363 | ||
3364 | ||
3365 | ||
3366 | ||
3367 | ||
3368 | ||
3369 | ||
3370 | endmodule | |
3371 | ||
3372 | ||
3373 | ||
3374 | ||
3375 | ||
3376 | ||
3377 | ||
3378 |