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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: pmu.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module pmu ( | |
36 | in_rngl_cdbus, | |
37 | l2clk, | |
38 | scan_in, | |
39 | tcu_pce_ov, | |
40 | spc_bclk, | |
41 | spc_aclk, | |
42 | tcu_scan_en, | |
43 | lsu_pmu_pmen, | |
44 | lsu_asi_clken, | |
45 | scan_out, | |
46 | pmu_rngl_cdbus, | |
47 | dec_pmu_instr0_type_d, | |
48 | dec_pmu_instr1_type_d, | |
49 | lsu_pmu_mem_type_b, | |
50 | dec_br_taken_e, | |
51 | dec_lsu_sel0_d, | |
52 | mmu_pmu_l2ret, | |
53 | mmu_pmu_l2miss, | |
54 | mmu_pmu_dtlb, | |
55 | mmu_pmu_tid, | |
56 | l15_pmu_xbar_optype, | |
57 | spu_pmu_cwq_busy, | |
58 | spu_pmu_cwq_tid, | |
59 | spu_pmu_ma_busy, | |
60 | tlu_pmu_pstate_priv, | |
61 | tlu_pmu_hpstate_hpriv, | |
62 | tlu_pmu_trap_taken, | |
63 | tlu_pmu_trap_mask_e, | |
64 | dec_valid_e, | |
65 | dec_flush_m, | |
66 | dec_flush_b, | |
67 | tlu_flush_pmu_b, | |
68 | tlu_flush_pmu_w, | |
69 | pmu_tlu_trap_m, | |
70 | pmu_tlu_debug_event, | |
71 | pmu_lsu_dcmiss_trap_m, | |
72 | pmu_lsu_dtmiss_trap_m, | |
73 | pmu_lsu_l2dmiss_trap_m); | |
74 | wire pmu_pdp_dp_scanin; | |
75 | wire pmu_pdp_dp_scanout; | |
76 | wire pmu_pct_ctl_scanin; | |
77 | wire pmu_pct_ctl_scanout; | |
78 | wire [7:0] pct_rd_pic; | |
79 | wire pct_rd_a_pic; | |
80 | wire pct_rd_pic_pcr; | |
81 | wire pct_bypass_asi; | |
82 | wire [31:0] pct_pcr_data; | |
83 | wire pct_exception; | |
84 | wire [7:0] pct_pic_clken; | |
85 | wire pct_pic07_w2_clken; | |
86 | wire [7:0] pct_wr_pic_w2; | |
87 | wire [6:0] pct_incr_pic_w1; | |
88 | wire pct_incr_asi_w1; | |
89 | wire [3:0] pct_pich07_add_w2; | |
90 | wire [3:0] pct_picl07_add_w2; | |
91 | wire pmu_asi_clken; | |
92 | wire [31:0] pdp_asi_din_to_pctl; | |
93 | wire [7:0] pdp_asi_ctlin_to_pctl_15_8; | |
94 | wire [4:0] pdp_asi_ctlin_to_pctl_4_0; | |
95 | wire pdp_pich_cout07; | |
96 | wire pdp_picl_cout07; | |
97 | wire [7:0] pdp_pich_wrap; | |
98 | wire [7:0] pdp_picl_wrap; | |
99 | ||
100 | ||
101 | input [64:0] in_rngl_cdbus; // ASI local ring data in | |
102 | ||
103 | input l2clk; | |
104 | input scan_in; | |
105 | input tcu_pce_ov; // scan signals | |
106 | input spc_bclk; | |
107 | input spc_aclk; | |
108 | input tcu_scan_en; | |
109 | ||
110 | // Power management | |
111 | input lsu_pmu_pmen; | |
112 | input lsu_asi_clken; | |
113 | ||
114 | output scan_out; | |
115 | ||
116 | output [64:0] pmu_rngl_cdbus; // ASI local ring data out | |
117 | ||
118 | // Instruction decode events | |
119 | input [12:0] dec_pmu_instr0_type_d; // {12 - valid; 11:10 - tid; 9:0 - {atomic_d, l2imiss, itmiss, icmiss, other, %sethi, store, load, FGU, branch}} | |
120 | input [12:0] dec_pmu_instr1_type_d; | |
121 | input [5:0] lsu_pmu_mem_type_b; // {5:3 - tid (use for l2miss only); 2:0 - {l2 d-miss, dt_miss, d-cache miss}} | |
122 | input [1:0] dec_br_taken_e; // branch taken indicator | |
123 | input dec_lsu_sel0_d; // select tg0 for LSU tid | |
124 | ||
125 | // MMU activity (excluding ITLB/DTLB misses) | |
126 | input mmu_pmu_l2ret; // indicates l2 data to MMU | |
127 | input mmu_pmu_l2miss; // indicates the return pkt had l2 miss | |
128 | input mmu_pmu_dtlb; // indicates that return pkt is for D-side table walk | |
129 | input [2:0] mmu_pmu_tid; // thread id | |
130 | ||
131 | // Crossbar activity | |
132 | input [6:0] l15_pmu_xbar_optype; // {6 - valid; 5:3 - tid; 2:0 - {111 - mastore; 110 - maload; 101 - ifetch; 100 - mmuld; 011 - cwqstore; 010 - cwqload; 001 - cpustore; 000 - cpuld}} | |
133 | ||
134 | // SPU activity | |
135 | input [4:0] spu_pmu_cwq_busy; // CWQ busy {rc4,hash,des,crc,aes} | |
136 | input [2:0] spu_pmu_cwq_tid; | |
137 | input [3:0] spu_pmu_ma_busy; // {3 - busy/idle; 2:0 - tid} | |
138 | ||
139 | // state bits to decide when counters should record | |
140 | input [7:0] tlu_pmu_pstate_priv; // pstate.priv for each thread (bit 7 == thread 7) | |
141 | input [7:0] tlu_pmu_hpstate_hpriv; // hpstate.hpriv (ditto) | |
142 | ||
143 | // PMU trap is taken, reset the counter if "-"ve. | |
144 | input [7:0] tlu_pmu_trap_taken; | |
145 | input [1:0] tlu_pmu_trap_mask_e; // True if TLU enabled for PMU trap {1 - tg1; 0 - tg0} | |
146 | ||
147 | // Flushes from IFU and TLU | |
148 | input [1:0] dec_valid_e; // bit 1 is for TG1, 0 for TG0; | |
149 | //instr valid in the e-stage (taken flush_e into consideration?) | |
150 | ||
151 | input [1:0] dec_flush_m; // bit 1 is for TG1, 0 for TG0 | |
152 | input [1:0] dec_flush_b; // bit 1 is for TG1, 0 for TG0 | |
153 | input [1:0] tlu_flush_pmu_b; // bit 1 is for TG1, 0 for TG0 | |
154 | input [1:0] tlu_flush_pmu_w; // bit 1 is for TG1, 0 for TG0 | |
155 | ||
156 | // Signals to tell TLU if we may/should trap due to counter overflow | |
157 | output [7:0] pmu_tlu_trap_m; // Sent at beginning of M to TLU | |
158 | output [7:0] pmu_tlu_debug_event; // Tell trap if a perf. monitor event occurred to soft/hard stop/trigger on | |
159 | ||
160 | // Signals to LSU for trap on DCmiss, DTmiss, L2Dmiss | |
161 | output pmu_lsu_dcmiss_trap_m; | |
162 | output pmu_lsu_dtmiss_trap_m; | |
163 | output [7:0] pmu_lsu_l2dmiss_trap_m; | |
164 | ||
165 | pmu_pdp_dp pmu_pdp_dp( | |
166 | .scan_in(pmu_pdp_dp_scanin), | |
167 | .scan_out(pmu_pdp_dp_scanout), | |
168 | .l2clk(l2clk), | |
169 | .pmu_rngl_cdbus(pmu_rngl_cdbus[63:0]), | |
170 | .tcu_pce_ov(tcu_pce_ov), | |
171 | .spc_aclk(spc_aclk), | |
172 | .spc_bclk(spc_bclk), | |
173 | .tcu_scan_en(tcu_scan_en), | |
174 | .in_rngl_cdbus(in_rngl_cdbus[63:0]), | |
175 | .pct_rd_pic(pct_rd_pic[7:0]), | |
176 | .pct_rd_a_pic(pct_rd_a_pic), | |
177 | .pct_rd_pic_pcr(pct_rd_pic_pcr), | |
178 | .pct_bypass_asi(pct_bypass_asi), | |
179 | .pct_pcr_data(pct_pcr_data[31:0]), | |
180 | .pct_exception(pct_exception), | |
181 | .pct_pic_clken(pct_pic_clken[7:0]), | |
182 | .pct_pic07_w2_clken(pct_pic07_w2_clken), | |
183 | .pct_wr_pic_w2(pct_wr_pic_w2[7:0]), | |
184 | .pct_incr_pic_w1(pct_incr_pic_w1[6:0]), | |
185 | .pct_incr_asi_w1(pct_incr_asi_w1), | |
186 | .pct_pich07_add_w2(pct_pich07_add_w2[3:0]), | |
187 | .pct_picl07_add_w2(pct_picl07_add_w2[3:0]), | |
188 | .pmu_asi_clken(pmu_asi_clken), | |
189 | .pdp_asi_din_to_pctl(pdp_asi_din_to_pctl[31:0]), | |
190 | .pdp_asi_ctlin_to_pctl_15_8(pdp_asi_ctlin_to_pctl_15_8[7:0]), | |
191 | .pdp_asi_ctlin_to_pctl_4_0(pdp_asi_ctlin_to_pctl_4_0[4:0]), | |
192 | .pdp_pich_cout07(pdp_pich_cout07), | |
193 | .pdp_picl_cout07(pdp_picl_cout07), | |
194 | .pdp_pich_wrap(pdp_pich_wrap[7:0]), | |
195 | .pdp_picl_wrap(pdp_picl_wrap[7:0]) | |
196 | ); | |
197 | ||
198 | pmu_pct_ctl pmu_pct_ctl( | |
199 | .in_rngl_cdbus_ctl_ndata(in_rngl_cdbus[64]), | |
200 | .pct_rngl_cdbus_ctl_ndata(pmu_rngl_cdbus[64]), | |
201 | .scan_in(pmu_pct_ctl_scanin), | |
202 | .scan_out(pmu_pct_ctl_scanout), | |
203 | .l2clk(l2clk), | |
204 | .tcu_pce_ov(tcu_pce_ov), | |
205 | .spc_aclk(spc_aclk), | |
206 | .spc_bclk(spc_bclk), | |
207 | .tcu_scan_en(tcu_scan_en), | |
208 | .lsu_asi_clken(lsu_asi_clken), | |
209 | .lsu_pmu_pmen(lsu_pmu_pmen), | |
210 | .dec_pmu_instr0_type_d(dec_pmu_instr0_type_d[12:0]), | |
211 | .dec_pmu_instr1_type_d(dec_pmu_instr1_type_d[12:0]), | |
212 | .dec_br_taken_e(dec_br_taken_e[1:0]), | |
213 | .lsu_pmu_mem_type_b(lsu_pmu_mem_type_b[5:0]), | |
214 | .dec_lsu_sel0_d(dec_lsu_sel0_d), | |
215 | .mmu_pmu_l2ret(mmu_pmu_l2ret), | |
216 | .mmu_pmu_l2miss(mmu_pmu_l2miss), | |
217 | .mmu_pmu_dtlb(mmu_pmu_dtlb), | |
218 | .mmu_pmu_tid(mmu_pmu_tid[2:0]), | |
219 | .l15_pmu_xbar_optype(l15_pmu_xbar_optype[6:0]), | |
220 | .spu_pmu_cwq_busy(spu_pmu_cwq_busy[4:0]), | |
221 | .spu_pmu_cwq_tid(spu_pmu_cwq_tid[2:0]), | |
222 | .spu_pmu_ma_busy(spu_pmu_ma_busy[3:0]), | |
223 | .tlu_pmu_pstate_priv(tlu_pmu_pstate_priv[7:0]), | |
224 | .tlu_pmu_hpstate_hpriv(tlu_pmu_hpstate_hpriv[7:0]), | |
225 | .tlu_pmu_trap_taken(tlu_pmu_trap_taken[7:0]), | |
226 | .tlu_pmu_trap_mask_e(tlu_pmu_trap_mask_e[1:0]), | |
227 | .tlu_flush_pmu_b(tlu_flush_pmu_b[1:0]), | |
228 | .tlu_flush_pmu_w(tlu_flush_pmu_w[1:0]), | |
229 | .dec_valid_e(dec_valid_e[1:0]), | |
230 | .dec_flush_m(dec_flush_m[1:0]), | |
231 | .dec_flush_b(dec_flush_b[1:0]), | |
232 | .pdp_pich_cout07(pdp_pich_cout07), | |
233 | .pdp_picl_cout07(pdp_picl_cout07), | |
234 | .pdp_pich_wrap(pdp_pich_wrap[7:0]), | |
235 | .pdp_picl_wrap(pdp_picl_wrap[7:0]), | |
236 | .pdp_asi_ctlin_to_pctl_15_8(pdp_asi_ctlin_to_pctl_15_8[7:0]), | |
237 | .pdp_asi_ctlin_to_pctl_4_0(pdp_asi_ctlin_to_pctl_4_0[4:0]), | |
238 | .pdp_asi_din_to_pctl(pdp_asi_din_to_pctl[31:0]), | |
239 | .pmu_tlu_trap_m(pmu_tlu_trap_m[7:0]), | |
240 | .pmu_tlu_debug_event(pmu_tlu_debug_event[7:0]), | |
241 | .pct_pich07_add_w2(pct_pich07_add_w2[3:0]), | |
242 | .pct_picl07_add_w2(pct_picl07_add_w2[3:0]), | |
243 | .pmu_lsu_dcmiss_trap_m(pmu_lsu_dcmiss_trap_m), | |
244 | .pmu_lsu_dtmiss_trap_m(pmu_lsu_dtmiss_trap_m), | |
245 | .pmu_lsu_l2dmiss_trap_m(pmu_lsu_l2dmiss_trap_m[7:0]), | |
246 | .pct_rd_pic(pct_rd_pic[7:0]), | |
247 | .pct_rd_a_pic(pct_rd_a_pic), | |
248 | .pct_rd_pic_pcr(pct_rd_pic_pcr), | |
249 | .pct_bypass_asi(pct_bypass_asi), | |
250 | .pct_pcr_data(pct_pcr_data[31:0]), | |
251 | .pct_exception(pct_exception), | |
252 | .pct_wr_pic_w2(pct_wr_pic_w2[7:0]), | |
253 | .pct_incr_pic_w1(pct_incr_pic_w1[6:0]), | |
254 | .pct_incr_asi_w1(pct_incr_asi_w1), | |
255 | .pct_pic_clken(pct_pic_clken[7:0]), | |
256 | .pct_pic07_w2_clken(pct_pic07_w2_clken), | |
257 | .pmu_asi_clken(pmu_asi_clken) | |
258 | ); | |
259 | ||
260 | // fixscan start: | |
261 | assign pmu_pdp_dp_scanin = scan_in ; | |
262 | assign pmu_pct_ctl_scanin = pmu_pdp_dp_scanout ; | |
263 | assign scan_out = pmu_pct_ctl_scanout ; | |
264 | // fixscan end: | |
265 | endmodule | |
266 |