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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tlu_tsb_dp.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tlu_tsb_dp ( | |
36 | tsb_in, | |
37 | wr_en_in, | |
38 | ecc_error, | |
39 | tsb_out, | |
40 | wr_en_out); | |
41 | wire [67:0] evb_in; | |
42 | wire [67:0] evb_out; | |
43 | wire [135:0] tsb_ou; | |
44 | wire [67:0] odb_in; | |
45 | wire [67:0] odb_out; | |
46 | wire wr_en_in_; | |
47 | ||
48 | ||
49 | ||
50 | input [135:0] tsb_in; | |
51 | input wr_en_in; | |
52 | input ecc_error; | |
53 | ||
54 | output [135:0] tsb_out; | |
55 | output wr_en_out; | |
56 | ||
57 | ||
58 | ||
59 | ||
60 | //////////////////////////////////////////////////////////////////////////////// | |
61 | // | |
62 | // The compiled SRAM used for the trap stack array is arranged so that | |
63 | // din[000] is in bit 1 | |
64 | // din[001] is in bit 2 | |
65 | // din[002] is in bit 2 | |
66 | // din[003] is in bit 3 | |
67 | // din[004] is in bit 3 | |
68 | // etc. | |
69 | // (pre-mirror) | |
70 | // | |
71 | // Also, data bits 135:134 wire to SRAM pins 151:150 | |
72 | // ECC bits 15:000 wire to SRAM pins 149:134 | |
73 | // data bits 133:000 wire to SRAM pins 133:000 | |
74 | // The SRAM has its controls between bits 76 and 75 | |
75 | ||
76 | assign evb_in[67:0] = | |
77 | { tsb_in[134], tsb_in[132], tsb_in[130], | |
78 | tsb_in[128], tsb_in[126], tsb_in[124], tsb_in[122], tsb_in[120], | |
79 | tsb_in[118], tsb_in[116], tsb_in[114], tsb_in[112], tsb_in[110], | |
80 | tsb_in[108], tsb_in[106], tsb_in[104], tsb_in[102], tsb_in[100], | |
81 | tsb_in[98], tsb_in[96], tsb_in[94], tsb_in[92], tsb_in[90], | |
82 | tsb_in[88], tsb_in[86], tsb_in[84], tsb_in[82], tsb_in[80], | |
83 | tsb_in[78], tsb_in[76], tsb_in[74], tsb_in[72], tsb_in[70], | |
84 | tsb_in[68], tsb_in[66], tsb_in[64], tsb_in[62], tsb_in[60], | |
85 | tsb_in[58], tsb_in[56], tsb_in[54], tsb_in[52], tsb_in[50], | |
86 | tsb_in[48], tsb_in[46], tsb_in[44], tsb_in[42], tsb_in[40], | |
87 | tsb_in[38], tsb_in[36], tsb_in[34], tsb_in[32], tsb_in[30], | |
88 | tsb_in[28], tsb_in[26], tsb_in[24], tsb_in[22], tsb_in[20], | |
89 | tsb_in[18], tsb_in[16], tsb_in[14], tsb_in[12], tsb_in[10], | |
90 | tsb_in[8], tsb_in[6], tsb_in[4], tsb_in[2], tsb_in[0]}; | |
91 | ||
92 | tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 even_data_bits_buf ( | |
93 | .din (evb_in [67:0] ), | |
94 | .dout (evb_out [67:0] ) | |
95 | ); | |
96 | ||
97 | assign { tsb_ou[134], tsb_ou[132], tsb_ou[130], | |
98 | tsb_ou[128], tsb_ou[126], tsb_ou[124], tsb_ou[122], tsb_ou[120], | |
99 | tsb_ou[118], tsb_ou[116], tsb_ou[114], tsb_ou[112], tsb_ou[110], | |
100 | tsb_ou[108], tsb_ou[106], tsb_ou[104], tsb_ou[102], tsb_ou[100], | |
101 | tsb_ou[98], tsb_ou[96], tsb_ou[94], tsb_ou[92], tsb_ou[90], | |
102 | tsb_ou[88], tsb_ou[86], tsb_ou[84], tsb_ou[82], tsb_ou[80], | |
103 | tsb_ou[78], tsb_ou[76], tsb_ou[74], tsb_ou[72], tsb_ou[70], | |
104 | tsb_ou[68], tsb_ou[66], tsb_ou[64], tsb_ou[62], tsb_ou[60], | |
105 | tsb_ou[58], tsb_ou[56], tsb_ou[54], tsb_ou[52], tsb_ou[50], | |
106 | tsb_ou[48], tsb_ou[46], tsb_ou[44], tsb_ou[42], tsb_ou[40], | |
107 | tsb_ou[38], tsb_ou[36], tsb_ou[34], tsb_ou[32], tsb_ou[30], | |
108 | tsb_ou[28], tsb_ou[26], tsb_ou[24], tsb_ou[22], tsb_ou[20], | |
109 | tsb_ou[18], tsb_ou[16], tsb_ou[14], tsb_ou[12], tsb_ou[10], | |
110 | tsb_ou[8], tsb_ou[6], tsb_ou[4], tsb_ou[2], tsb_ou[0]} = | |
111 | evb_out[67:0]; | |
112 | ||
113 | ||
114 | ||
115 | assign odb_in[67:0] = | |
116 | { tsb_in[135], tsb_in[133], tsb_in[131], | |
117 | tsb_in[129], tsb_in[127], tsb_in[125], tsb_in[123], tsb_in[121], | |
118 | tsb_in[119], tsb_in[117], tsb_in[115], tsb_in[113], tsb_in[111], | |
119 | tsb_in[109], tsb_in[107], tsb_in[105], tsb_in[103], tsb_in[101], | |
120 | tsb_in[99], tsb_in[97], tsb_in[95], tsb_in[93], tsb_in[91], | |
121 | tsb_in[89], tsb_in[87], tsb_in[85], tsb_in[83], tsb_in[81], | |
122 | tsb_in[79], tsb_in[77], tsb_in[75], tsb_in[73], tsb_in[71], | |
123 | tsb_in[69], tsb_in[67], tsb_in[65], tsb_in[63], tsb_in[61], | |
124 | tsb_in[59], tsb_in[57], tsb_in[55], tsb_in[53], tsb_in[51], | |
125 | tsb_in[49], tsb_in[47], tsb_in[45], tsb_in[43], tsb_in[41], | |
126 | tsb_in[39], tsb_in[37], tsb_in[35], tsb_in[33], tsb_in[31], | |
127 | tsb_in[29], tsb_in[27], tsb_in[25], tsb_in[23], tsb_in[21], | |
128 | tsb_in[19], tsb_in[17], tsb_in[15], tsb_in[13], tsb_in[11], | |
129 | tsb_in[9], tsb_in[7], tsb_in[5], tsb_in[3], tsb_in[1]}; | |
130 | ||
131 | tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 odd_data_bits_buf ( | |
132 | .din (odb_in [67:0] ), | |
133 | .dout (odb_out [67:0] ) | |
134 | ); | |
135 | ||
136 | assign { tsb_ou[135], tsb_ou[133], tsb_ou[131], | |
137 | tsb_ou[129], tsb_ou[127], tsb_ou[125], tsb_ou[123], tsb_ou[121], | |
138 | tsb_ou[119], tsb_ou[117], tsb_ou[115], tsb_ou[113], tsb_ou[111], | |
139 | tsb_ou[109], tsb_ou[107], tsb_ou[105], tsb_ou[103], tsb_ou[101], | |
140 | tsb_ou[99], tsb_ou[97], tsb_ou[95], tsb_ou[93], tsb_ou[91], | |
141 | tsb_ou[89], tsb_ou[87], tsb_ou[85], tsb_ou[83], tsb_ou[81], | |
142 | tsb_ou[79], tsb_ou[77], tsb_ou[75], tsb_ou[73], tsb_ou[71], | |
143 | tsb_ou[69], tsb_ou[67], tsb_ou[65], tsb_ou[63], tsb_ou[61], | |
144 | tsb_ou[59], tsb_ou[57], tsb_ou[55], tsb_ou[53], tsb_ou[51], | |
145 | tsb_ou[49], tsb_ou[47], tsb_ou[45], tsb_ou[43], tsb_ou[41], | |
146 | tsb_ou[39], tsb_ou[37], tsb_ou[35], tsb_ou[33], tsb_ou[31], | |
147 | tsb_ou[29], tsb_ou[27], tsb_ou[25], tsb_ou[23], tsb_ou[21], | |
148 | tsb_ou[19], tsb_ou[17], tsb_ou[15], tsb_ou[13], tsb_ou[11], | |
149 | tsb_ou[9], tsb_ou[7], tsb_ou[5], tsb_ou[3], tsb_ou[1]} = | |
150 | odb_out[67:0]; | |
151 | ||
152 | assign tsb_out[135:0] = | |
153 | tsb_ou[135:0]; | |
154 | ||
155 | ||
156 | ||
157 | // The wr_en should be spaced 3 bits away from bit 76 | |
158 | // wr_en_out = wr_en_in & ~ecc_error = ~(~wr_en_in | ecc_error) | |
159 | ||
160 | tlu_tsb_dp_inv_macro__stack_2r__width_1 wr_en_in_b_inv ( // stack=none not supported | |
161 | .din (wr_en_in ), | |
162 | .dout (wr_en_in_ ) | |
163 | ); | |
164 | ||
165 | tlu_tsb_dp_nor_macro__ports_2__stack_2r__width_1 wr_en_out_nor (//stack=none not supported | |
166 | .din0 (ecc_error ), | |
167 | .din1 (wr_en_in_ ), | |
168 | .dout (wr_en_out ) | |
169 | ); | |
170 | ||
171 | ||
172 | ||
173 | ||
174 | ||
175 | endmodule | |
176 | ||
177 | ||
178 | ||
179 | ||
180 | // | |
181 | // buff macro | |
182 | // | |
183 | // | |
184 | ||
185 | ||
186 | ||
187 | ||
188 | ||
189 | module tlu_tsb_dp_buff_macro__minbuff_1__stack_none__width_68 ( | |
190 | din, | |
191 | dout); | |
192 | input [67:0] din; | |
193 | output [67:0] dout; | |
194 | ||
195 | ||
196 | ||
197 | ||
198 | ||
199 | ||
200 | buff #(68) d0_0 ( | |
201 | .in(din[67:0]), | |
202 | .out(dout[67:0]) | |
203 | ); | |
204 | ||
205 | ||
206 | ||
207 | ||
208 | ||
209 | ||
210 | ||
211 | ||
212 | endmodule | |
213 | ||
214 | ||
215 | ||
216 | ||
217 | ||
218 | // | |
219 | // invert macro | |
220 | // | |
221 | // | |
222 | ||
223 | ||
224 | ||
225 | ||
226 | ||
227 | module tlu_tsb_dp_inv_macro__stack_2r__width_1 ( | |
228 | din, | |
229 | dout); | |
230 | input [0:0] din; | |
231 | output [0:0] dout; | |
232 | ||
233 | ||
234 | ||
235 | ||
236 | ||
237 | ||
238 | inv #(1) d0_0 ( | |
239 | .in(din[0:0]), | |
240 | .out(dout[0:0]) | |
241 | ); | |
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | ||
250 | ||
251 | endmodule | |
252 | ||
253 | ||
254 | ||
255 | ||
256 | ||
257 | // | |
258 | // nor macro for ports = 2,3 | |
259 | // | |
260 | // | |
261 | ||
262 | ||
263 | ||
264 | ||
265 | ||
266 | module tlu_tsb_dp_nor_macro__ports_2__stack_2r__width_1 ( | |
267 | din0, | |
268 | din1, | |
269 | dout); | |
270 | input [0:0] din0; | |
271 | input [0:0] din1; | |
272 | output [0:0] dout; | |
273 | ||
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | nor2 #(1) d0_0 ( | |
280 | .in0(din0[0:0]), | |
281 | .in1(din1[0:0]), | |
282 | .out(dout[0:0]) | |
283 | ); | |
284 | ||
285 | ||
286 | ||
287 | ||
288 | ||
289 | ||
290 | ||
291 | endmodule | |
292 | ||
293 | ||
294 | ||
295 |