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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_dmo_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module tcu_dmo_ctl ( | |
36 | l2clk, | |
37 | scan_in, | |
38 | scan_out, | |
39 | tcu_int_se, | |
40 | tcu_int_aclk, | |
41 | tcu_int_bclk, | |
42 | tcu_int_ce, | |
43 | tcu_pce_ov, | |
44 | io_cmp_sync_en_local, | |
45 | cmp_io2x_sync_en_local, | |
46 | mbist_start_io_sync, | |
47 | tcu_mio_dmo_data, | |
48 | tcu_mio_dmo_sync, | |
49 | tcu_mio_mbist_done, | |
50 | tcu_mio_mbist_fail, | |
51 | tcu_mio_jtag_membist_mode, | |
52 | spc4_dmo_dout, | |
53 | spc6_dmo_dout, | |
54 | dmo_coresel, | |
55 | dmo_dcmuxctl, | |
56 | dmo_icmuxctl, | |
57 | l2t4_dmo_dout, | |
58 | l2t6_dmo_dout, | |
59 | dmo_l2tsel, | |
60 | dmo_tagmuxctl, | |
61 | rtx_tcu_dmo_data_out, | |
62 | tds_tcu_dmo_dout, | |
63 | rdp_tcu_dmo_dout, | |
64 | tcu_rtx_dmo_ctl, | |
65 | jtag_dmo_enable, | |
66 | jtag_dmo_control_upd, | |
67 | jtag_dmo_control, | |
68 | dmo_cfg, | |
69 | mbist_all_done, | |
70 | mbist_one_fail); | |
71 | wire l1en; | |
72 | wire pce_ov; | |
73 | wire stop; | |
74 | wire se; | |
75 | wire siclk; | |
76 | wire soclk; | |
77 | wire l1clk; | |
78 | wire dmo_spc4din_reg_scanin; | |
79 | wire dmo_spc4din_reg_scanout; | |
80 | wire [35:0] spc4_dmo_data; | |
81 | wire dmo_spc6din_reg_scanin; | |
82 | wire dmo_spc6din_reg_scanout; | |
83 | wire [35:0] spc6_dmo_data; | |
84 | wire dmo_l2t4din_reg_scanin; | |
85 | wire dmo_l2t4din_reg_scanout; | |
86 | wire [38:0] l2t4_dmo_data; | |
87 | wire dmo_l2t6din_reg_scanin; | |
88 | wire dmo_l2t6din_reg_scanout; | |
89 | wire [38:0] l2t6_dmo_data; | |
90 | wire dmo_rtxdin_reg_scanin; | |
91 | wire dmo_rtxdin_reg_scanout; | |
92 | wire [39:0] rtx_dmo_data; | |
93 | wire dmo_rdpdin_reg_scanin; | |
94 | wire dmo_rdpdin_reg_scanout; | |
95 | wire [39:0] rdp_dmo_data; | |
96 | wire dmo_tdsdin_reg_scanin; | |
97 | wire dmo_tdsdin_reg_scanout; | |
98 | wire [39:0] tds_dmo_data; | |
99 | wire spcl2t_sel; | |
100 | wire [15:0] dmo_control; | |
101 | wire [1:0] spcl2tag_ctl; | |
102 | wire [1:0] niu_ctl; | |
103 | wire spc4_sel; | |
104 | wire spc6_sel; | |
105 | wire l2t4_sel; | |
106 | wire l2t6_sel; | |
107 | wire l2tag_sel; | |
108 | wire rtx_sel; | |
109 | wire rdp_sel; | |
110 | wire tds_sel; | |
111 | wire [35:0] spc_data; | |
112 | wire [38:0] l2t_data; | |
113 | wire [38:0] spcl2t_data; | |
114 | wire [39:0] niu_data; | |
115 | wire [39:0] dmo_data; | |
116 | wire dmo_sampledata_reg_scanin; | |
117 | wire dmo_sampledata_reg_scanout; | |
118 | wire sample_data; | |
119 | wire [39:0] dmo_sampled_data; | |
120 | wire [31:0] sr_out; | |
121 | wire dmo_io2xdata_reg_scanin; | |
122 | wire dmo_io2xdata_reg_scanout; | |
123 | wire [39:0] dmo_sampled_data_io2x; | |
124 | wire dmo_sr_reg_scanin; | |
125 | wire dmo_sr_reg_scanout; | |
126 | wire [31:0] sr_next; | |
127 | wire shift; | |
128 | wire dmoctl_upd; | |
129 | wire jtag_dmo_enable_io2x_sync; | |
130 | wire start_dmo; | |
131 | wire dmo_muxctl_reg_scanin; | |
132 | wire dmo_muxctl_reg_scanout; | |
133 | wire [15:0] dmo_ctl_next; | |
134 | wire dmo_ensync_reg_scanin; | |
135 | wire dmo_ensync_reg_scanout; | |
136 | wire jtag_dmo_enable_sync; | |
137 | wire dmo_dmoen_reg_scanin; | |
138 | wire dmo_dmoen_reg_scanout; | |
139 | wire dmo_updsync_reg_scanin; | |
140 | wire dmo_updsync_reg_scanout; | |
141 | wire jtag_dmo_control_upd_sync; | |
142 | wire dmo_dmosync_reg_scanin; | |
143 | wire dmo_dmosync_reg_scanout; | |
144 | wire dmo_sync_next; | |
145 | wire dmo_sync; | |
146 | wire dmo_dmosyncout_reg_scanin; | |
147 | wire dmo_dmosyncout_reg_scanout; | |
148 | wire dmo_dmodf_reg_scanin; | |
149 | wire dmo_dmodf_reg_scanout; | |
150 | wire done; | |
151 | wire fail; | |
152 | wire mbist_start_io2x_sync; | |
153 | wire done_sync; | |
154 | wire fail_sync; | |
155 | wire mbist_start_pulse; | |
156 | ||
157 | ||
158 | input l2clk; | |
159 | ||
160 | // Scan input/output for this block | |
161 | input scan_in; | |
162 | output scan_out; | |
163 | // Scan Controls | |
164 | input tcu_int_se; | |
165 | input tcu_int_aclk; | |
166 | input tcu_int_bclk; | |
167 | input tcu_int_ce; | |
168 | input tcu_pce_ov; | |
169 | ||
170 | // Synchronizer enables | |
171 | input io_cmp_sync_en_local; | |
172 | input cmp_io2x_sync_en_local; | |
173 | // MBIST Start from mbist controller | |
174 | input mbist_start_io_sync; | |
175 | ||
176 | // MIO Interface | |
177 | output [39:0] tcu_mio_dmo_data; | |
178 | output tcu_mio_dmo_sync; | |
179 | output tcu_mio_mbist_done; | |
180 | output tcu_mio_mbist_fail; | |
181 | output tcu_mio_jtag_membist_mode; | |
182 | ||
183 | // Core Interface | |
184 | input [35:0] spc4_dmo_dout; | |
185 | input [35:0] spc6_dmo_dout; | |
186 | output [5:0] dmo_coresel; | |
187 | output dmo_dcmuxctl; | |
188 | output dmo_icmuxctl; | |
189 | ||
190 | // L2Tag Interface | |
191 | input [38:0] l2t4_dmo_dout; | |
192 | input [38:0] l2t6_dmo_dout; | |
193 | output [5:0] dmo_l2tsel; | |
194 | output dmo_tagmuxctl; | |
195 | ||
196 | // NIU Interface | |
197 | input [39:0] rtx_tcu_dmo_data_out; | |
198 | input [39:0] tds_tcu_dmo_dout; | |
199 | input [39:0] rdp_tcu_dmo_dout; | |
200 | ||
201 | output [2:0] tcu_rtx_dmo_ctl; | |
202 | ||
203 | // JTAG Interface | |
204 | input jtag_dmo_enable; // enables DMO port | |
205 | input jtag_dmo_control_upd; | |
206 | input [47:0] jtag_dmo_control; | |
207 | output [47:0] dmo_cfg; | |
208 | ||
209 | // Done, Fail from mbist | |
210 | input mbist_all_done; | |
211 | input mbist_one_fail; | |
212 | ||
213 | //******************************************************************** | |
214 | // Scan reassigns | |
215 | //******************************************************************** | |
216 | assign l1en = tcu_int_ce; // 1'b1; | |
217 | assign pce_ov = tcu_pce_ov; // 1'b1; | |
218 | assign stop = 1'b0; | |
219 | assign se = tcu_int_se; | |
220 | assign siclk = tcu_int_aclk; | |
221 | assign soclk = tcu_int_bclk; | |
222 | ||
223 | tcu_dmo_ctl_l1clkhdr_ctl_macro dmo_clkgen | |
224 | ( .l2clk (l2clk), | |
225 | .l1clk (l1clk), | |
226 | .l1en(l1en), | |
227 | .pce_ov(pce_ov), | |
228 | .stop(stop), | |
229 | .se(se) ); | |
230 | ||
231 | //******************************************************************* | |
232 | // Incoming BIST Data from SPC Cores 4 & 6 | |
233 | //******************************************************************* | |
234 | tcu_dmo_ctl_msff_ctl_macro__width_36 dmo_spc4din_reg | |
235 | ( | |
236 | .scan_in(dmo_spc4din_reg_scanin), | |
237 | .scan_out(dmo_spc4din_reg_scanout), | |
238 | .l1clk (l1clk), | |
239 | .din (spc4_dmo_dout[35:0]), | |
240 | .dout (spc4_dmo_data[35:0]), | |
241 | .siclk(siclk), | |
242 | .soclk(soclk) | |
243 | ); | |
244 | tcu_dmo_ctl_msff_ctl_macro__width_36 dmo_spc6din_reg | |
245 | ( | |
246 | .scan_in(dmo_spc6din_reg_scanin), | |
247 | .scan_out(dmo_spc6din_reg_scanout), | |
248 | .l1clk (l1clk), | |
249 | .din (spc6_dmo_dout[35:0]), | |
250 | .dout (spc6_dmo_data[35:0]), | |
251 | .siclk(siclk), | |
252 | .soclk(soclk) | |
253 | ); | |
254 | ||
255 | //******************************************************************* | |
256 | // Incoming BIST Data from L2 Tags 4 & 6 | |
257 | //******************************************************************* | |
258 | tcu_dmo_ctl_msff_ctl_macro__width_39 dmo_l2t4din_reg | |
259 | ( | |
260 | .scan_in(dmo_l2t4din_reg_scanin), | |
261 | .scan_out(dmo_l2t4din_reg_scanout), | |
262 | .l1clk (l1clk), | |
263 | .din (l2t4_dmo_dout[38:0]), | |
264 | .dout (l2t4_dmo_data[38:0]), | |
265 | .siclk(siclk), | |
266 | .soclk(soclk) | |
267 | ); | |
268 | tcu_dmo_ctl_msff_ctl_macro__width_39 dmo_l2t6din_reg | |
269 | ( | |
270 | .scan_in(dmo_l2t6din_reg_scanin), | |
271 | .scan_out(dmo_l2t6din_reg_scanout), | |
272 | .l1clk (l1clk), | |
273 | .din (l2t6_dmo_dout[38:0]), | |
274 | .dout (l2t6_dmo_data[38:0]), | |
275 | .siclk(siclk), | |
276 | .soclk(soclk) | |
277 | ); | |
278 | ||
279 | //******************************************************************* | |
280 | // Incoming BIST Data from RTX, RDP & TDS (all NIU) | |
281 | // Synchronized into cmp clock domain from IO clock domain | |
282 | //******************************************************************* | |
283 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 dmo_rtxdin_reg | |
284 | ( | |
285 | .scan_in(dmo_rtxdin_reg_scanin), | |
286 | .scan_out(dmo_rtxdin_reg_scanout), | |
287 | .l1clk (l1clk), | |
288 | .en (io_cmp_sync_en_local), | |
289 | .din (rtx_tcu_dmo_data_out[39:0]), | |
290 | .dout (rtx_dmo_data[39:0]), | |
291 | .siclk(siclk), | |
292 | .soclk(soclk) | |
293 | ); | |
294 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 dmo_rdpdin_reg | |
295 | ( | |
296 | .scan_in(dmo_rdpdin_reg_scanin), | |
297 | .scan_out(dmo_rdpdin_reg_scanout), | |
298 | .l1clk (l1clk), | |
299 | .en (io_cmp_sync_en_local), | |
300 | .din (rdp_tcu_dmo_dout[39:0]), | |
301 | .dout (rdp_dmo_data[39:0]), | |
302 | .siclk(siclk), | |
303 | .soclk(soclk) | |
304 | ); | |
305 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 dmo_tdsdin_reg | |
306 | ( | |
307 | .scan_in(dmo_tdsdin_reg_scanin), | |
308 | .scan_out(dmo_tdsdin_reg_scanout), | |
309 | .l1clk (l1clk), | |
310 | .en (io_cmp_sync_en_local), | |
311 | .din (tds_tcu_dmo_dout[39:0]), | |
312 | .dout (tds_dmo_data[39:0]), | |
313 | .siclk(siclk), | |
314 | .soclk(soclk) | |
315 | ); | |
316 | ||
317 | //******************************************************************* | |
318 | // Assign jtag register values to control signals | |
319 | //******************************************************************* | |
320 | ||
321 | assign spcl2t_sel = dmo_control[15]; | |
322 | ||
323 | assign spcl2tag_ctl[1:0] = dmo_control[14:13]; | |
324 | assign niu_ctl[1:0] = dmo_control[12:11]; | |
325 | ||
326 | assign tcu_rtx_dmo_ctl[2:0]= dmo_control[10:8]; | |
327 | ||
328 | assign dmo_dcmuxctl = dmo_control[7]; | |
329 | assign dmo_icmuxctl = dmo_control[6]; | |
330 | assign dmo_coresel[5:0] = dmo_control[5:0]; | |
331 | ||
332 | assign dmo_tagmuxctl = dmo_control[6]; // same as core's? | |
333 | assign dmo_l2tsel = dmo_control[5:0]; // same as coresel | |
334 | ||
335 | //******************************************************************* | |
336 | // Incoming BIST Data from RTX, RDP & TDS (all NIU) | |
337 | // Synchronized into cmp clock domain from IO clock domain | |
338 | //******************************************************************* | |
339 | ||
340 | assign spc4_sel = ~spcl2tag_ctl[1] & ~spcl2tag_ctl[0]; | |
341 | assign spc6_sel = ~spcl2tag_ctl[1] & spcl2tag_ctl[0]; | |
342 | assign l2t4_sel = spcl2tag_ctl[1] & ~spcl2tag_ctl[0]; | |
343 | assign l2t6_sel = spcl2tag_ctl[1] & spcl2tag_ctl[0]; | |
344 | assign l2tag_sel = spcl2tag_ctl[1]; | |
345 | ||
346 | assign rtx_sel = ~niu_ctl[1] & ~niu_ctl[0]; | |
347 | assign rdp_sel = ~niu_ctl[1] & niu_ctl[0]; | |
348 | assign tds_sel = niu_ctl[1] & ~niu_ctl[0]; | |
349 | ||
350 | // Multiplex core & l2tag dmo data | |
351 | assign spc_data[35:0] = spc4_sel ? spc4_dmo_data[35:0] | |
352 | : spc6_sel ? spc6_dmo_data[35:0] : 36'b0; | |
353 | ||
354 | assign l2t_data[38:0] = l2t4_sel ? l2t4_dmo_data[38:0] | |
355 | : l2t6_sel ? l2t6_dmo_data[38:0] : 39'b0; | |
356 | ||
357 | ||
358 | assign spcl2t_data[38:0] = l2tag_sel ? l2t_data[38:0] : {3'b0,spc_data[35:0]}; | |
359 | ||
360 | // Multiplex NIU dmo data | |
361 | assign niu_data[39:0] = rtx_sel ? rtx_dmo_data[39:0] | |
362 | : rdp_sel ? rdp_dmo_data[39:0] | |
363 | : tds_sel ? tds_dmo_data[39:0] | |
364 | : 40'b0; | |
365 | ||
366 | // Select between core/l2tag and NIU | |
367 | assign dmo_data[39:0] = spcl2t_sel ? {1'b0,spcl2t_data[38:0]} : niu_data[39:0]; | |
368 | ||
369 | //******************************************************************* | |
370 | // Sample DMO Data | |
371 | //******************************************************************* | |
372 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 dmo_sampledata_reg | |
373 | ( | |
374 | .scan_in(dmo_sampledata_reg_scanin), | |
375 | .scan_out(dmo_sampledata_reg_scanout), | |
376 | .l1clk (l1clk), | |
377 | .en (sample_data), | |
378 | .din (dmo_data[39:0]), | |
379 | .dout (dmo_sampled_data[39:0]), | |
380 | .siclk(siclk), | |
381 | .soclk(soclk) | |
382 | ); | |
383 | ||
384 | assign sample_data = sr_out[31]; | |
385 | ||
386 | //******************************************************************* | |
387 | // Send Sample DMO Data to MIO in IO2X Domain | |
388 | //******************************************************************* | |
389 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 dmo_io2xdata_reg | |
390 | ( | |
391 | .scan_in(dmo_io2xdata_reg_scanin), | |
392 | .scan_out(dmo_io2xdata_reg_scanout), | |
393 | .l1clk (l1clk), | |
394 | .en (cmp_io2x_sync_en_local), | |
395 | .din (dmo_sampled_data[39:0]), | |
396 | .dout (dmo_sampled_data_io2x[39:0]), | |
397 | .siclk(siclk), | |
398 | .soclk(soclk) | |
399 | ); | |
400 | ||
401 | assign tcu_mio_dmo_data[39:0] = dmo_sampled_data_io2x[39:0]; | |
402 | ||
403 | //******************************************************************* | |
404 | // Shift Register to Generate Sample Points for DMO Data | |
405 | // Uses bits 31:16 of JTAG DMO Register | |
406 | //******************************************************************* | |
407 | tcu_dmo_ctl_msff_ctl_macro__width_32 dmo_sr_reg | |
408 | ( | |
409 | .scan_in(dmo_sr_reg_scanin), | |
410 | .scan_out(dmo_sr_reg_scanout), | |
411 | .l1clk (l1clk), | |
412 | .din (sr_next[31:0]), | |
413 | .dout (sr_out[31:0]), | |
414 | .siclk(siclk), | |
415 | .soclk(soclk) | |
416 | ); | |
417 | ||
418 | assign sr_next[31:0] = shift ? {sr_out[0],sr_out[31:1]} | |
419 | : dmoctl_upd ? jtag_dmo_control[47:16] | |
420 | : sr_out[31:0]; | |
421 | ||
422 | assign shift = jtag_dmo_enable_io2x_sync & start_dmo; | |
423 | ||
424 | //******************************************************************* | |
425 | // Mux Controls for DMO Data | |
426 | // Uses bits 15:0 of JTAG DMO Register | |
427 | //******************************************************************* | |
428 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_16 dmo_muxctl_reg | |
429 | ( | |
430 | .scan_in(dmo_muxctl_reg_scanin), | |
431 | .scan_out(dmo_muxctl_reg_scanout), | |
432 | .l1clk (l1clk), | |
433 | .en (cmp_io2x_sync_en_local), | |
434 | .din (dmo_ctl_next[15:0]), | |
435 | .dout (dmo_control[15:0]), | |
436 | .siclk(siclk), | |
437 | .soclk(soclk) | |
438 | ); | |
439 | ||
440 | assign dmo_ctl_next[15:0] = dmoctl_upd ? jtag_dmo_control[15:0] | |
441 | : dmo_control[15:0]; | |
442 | ||
443 | assign dmo_cfg[47:0] = {sr_out[31:0],dmo_control[15:0]}; // to jtag | |
444 | ||
445 | //******************************************************************** | |
446 | // DMO Enable from JTAG (TCK Clock Domain) | |
447 | //******************************************************************** | |
448 | cl_sc1_clksyncff_4x dmo_en_sync_reg | |
449 | ( | |
450 | .si (dmo_ensync_reg_scanin), | |
451 | .so (dmo_ensync_reg_scanout), | |
452 | .l1clk (l1clk), | |
453 | .d (jtag_dmo_enable), | |
454 | .q (jtag_dmo_enable_sync), | |
455 | .siclk(siclk), | |
456 | .soclk(soclk) | |
457 | ); | |
458 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_1 dmo_dmoen_reg | |
459 | ( | |
460 | .scan_in(dmo_dmoen_reg_scanin), | |
461 | .scan_out(dmo_dmoen_reg_scanout), | |
462 | .l1clk (l1clk), | |
463 | .en (cmp_io2x_sync_en_local), | |
464 | .din (jtag_dmo_enable_sync), | |
465 | .dout (jtag_dmo_enable_io2x_sync), | |
466 | .siclk(siclk), | |
467 | .soclk(soclk) | |
468 | ); | |
469 | ||
470 | ||
471 | assign tcu_mio_jtag_membist_mode = jtag_dmo_enable_io2x_sync; | |
472 | ||
473 | assign start_dmo = mbist_start_io_sync; | |
474 | //assign start_dmo = jtag_dmo_enable_io2x_sync; //mbist_start_io_sync; | |
475 | // mbist_start_io_sync is mbist_start from mbist_ctl synch'ed with cmp_io_sync_en | |
476 | ||
477 | //******************************************************************** | |
478 | // Synchronizers for Updates from JTAG (TCK Clock Domain) | |
479 | //******************************************************************** | |
480 | cl_sc1_clksyncff_4x dmo_upd_sync_reg | |
481 | ( | |
482 | .si (dmo_updsync_reg_scanin), | |
483 | .so (dmo_updsync_reg_scanout), | |
484 | .l1clk (l1clk), | |
485 | .d (jtag_dmo_control_upd), | |
486 | .q (jtag_dmo_control_upd_sync), | |
487 | .siclk(siclk), | |
488 | .soclk(soclk) | |
489 | ); | |
490 | assign dmoctl_upd = jtag_dmo_control_upd_sync; | |
491 | ||
492 | //******************************************************************* | |
493 | // Generate mbist_sync to MIO; this runs at 1/2 frequency of data | |
494 | // going to MIO, for tester to tell where/when data is valid | |
495 | //******************************************************************* | |
496 | tcu_dmo_ctl_msff_ctl_macro__clr__1__width_1 dmo_dmosync_reg | |
497 | ( | |
498 | .scan_in(dmo_dmosync_reg_scanin), | |
499 | .scan_out(dmo_dmosync_reg_scanout), | |
500 | .l1clk (l1clk), | |
501 | .clr_ (shift), | |
502 | .din (dmo_sync_next), | |
503 | .dout (dmo_sync), | |
504 | .siclk(siclk), | |
505 | .soclk(soclk) | |
506 | ); | |
507 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_1 dmo_dmosyncout_reg | |
508 | ( | |
509 | .scan_in(dmo_dmosyncout_reg_scanin), | |
510 | .scan_out(dmo_dmosyncout_reg_scanout), | |
511 | .l1clk (l1clk), | |
512 | .en (cmp_io2x_sync_en_local), | |
513 | .din (dmo_sync), | |
514 | .dout (tcu_mio_dmo_sync), | |
515 | .siclk(siclk), | |
516 | .soclk(soclk) | |
517 | ); | |
518 | ||
519 | assign dmo_sync_next = sample_data ? ~dmo_sync : dmo_sync; | |
520 | ||
521 | //******************************************************************* | |
522 | // Generate mbist_done, mbist_fail to MIO; | |
523 | //******************************************************************* | |
524 | tcu_dmo_ctl_msff_ctl_macro__en_1__width_3 dmo_dmodf_reg | |
525 | ( | |
526 | .scan_in(dmo_dmodf_reg_scanin), | |
527 | .scan_out(dmo_dmodf_reg_scanout), | |
528 | .l1clk (l1clk), | |
529 | .en (cmp_io2x_sync_en_local), | |
530 | .din ({mbist_start_io_sync, done, fail}), | |
531 | .dout ({mbist_start_io2x_sync, done_sync, fail_sync}), | |
532 | .siclk(siclk), | |
533 | .soclk(soclk) | |
534 | ); | |
535 | ||
536 | assign mbist_start_pulse = mbist_start_io_sync & ~mbist_start_io2x_sync; | |
537 | assign done = mbist_start_pulse | mbist_all_done; | |
538 | assign fail = mbist_start_pulse | mbist_one_fail; | |
539 | ||
540 | assign tcu_mio_mbist_done = done_sync; | |
541 | assign tcu_mio_mbist_fail = fail_sync; | |
542 | ||
543 | // fixscan start: | |
544 | assign dmo_spc4din_reg_scanin = scan_in ; | |
545 | assign dmo_spc6din_reg_scanin = dmo_spc4din_reg_scanout ; | |
546 | assign dmo_l2t4din_reg_scanin = dmo_spc6din_reg_scanout ; | |
547 | assign dmo_l2t6din_reg_scanin = dmo_l2t4din_reg_scanout ; | |
548 | assign dmo_rtxdin_reg_scanin = dmo_l2t6din_reg_scanout ; | |
549 | assign dmo_rdpdin_reg_scanin = dmo_rtxdin_reg_scanout ; | |
550 | assign dmo_tdsdin_reg_scanin = dmo_rdpdin_reg_scanout ; | |
551 | assign dmo_sampledata_reg_scanin = dmo_tdsdin_reg_scanout ; | |
552 | assign dmo_io2xdata_reg_scanin = dmo_sampledata_reg_scanout; | |
553 | assign dmo_sr_reg_scanin = dmo_io2xdata_reg_scanout ; | |
554 | assign dmo_muxctl_reg_scanin = dmo_sr_reg_scanout ; | |
555 | assign dmo_ensync_reg_scanin = dmo_muxctl_reg_scanout ; | |
556 | assign dmo_dmoen_reg_scanin = dmo_ensync_reg_scanout ; | |
557 | assign dmo_updsync_reg_scanin = dmo_dmoen_reg_scanout ; | |
558 | assign dmo_dmosync_reg_scanin = dmo_updsync_reg_scanout ; | |
559 | assign dmo_dmosyncout_reg_scanin = dmo_dmosync_reg_scanout ; | |
560 | assign dmo_dmodf_reg_scanin = dmo_dmosyncout_reg_scanout ; | |
561 | assign scan_out = dmo_dmodf_reg_scanout ; | |
562 | // fixscan end: | |
563 | endmodule | |
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | // any PARAMS parms go into naming of macro | |
571 | ||
572 | module tcu_dmo_ctl_l1clkhdr_ctl_macro ( | |
573 | l2clk, | |
574 | l1en, | |
575 | pce_ov, | |
576 | stop, | |
577 | se, | |
578 | l1clk); | |
579 | ||
580 | ||
581 | input l2clk; | |
582 | input l1en; | |
583 | input pce_ov; | |
584 | input stop; | |
585 | input se; | |
586 | output l1clk; | |
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | cl_sc1_l1hdr_8x c_0 ( | |
593 | ||
594 | ||
595 | .l2clk(l2clk), | |
596 | .pce(l1en), | |
597 | .l1clk(l1clk), | |
598 | .se(se), | |
599 | .pce_ov(pce_ov), | |
600 | .stop(stop) | |
601 | ); | |
602 | ||
603 | ||
604 | ||
605 | endmodule | |
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | // any PARAMS parms go into naming of macro | |
620 | ||
621 | module tcu_dmo_ctl_msff_ctl_macro__width_36 ( | |
622 | din, | |
623 | l1clk, | |
624 | scan_in, | |
625 | siclk, | |
626 | soclk, | |
627 | dout, | |
628 | scan_out); | |
629 | wire [35:0] fdin; | |
630 | wire [34:0] so; | |
631 | ||
632 | input [35:0] din; | |
633 | input l1clk; | |
634 | input scan_in; | |
635 | ||
636 | ||
637 | input siclk; | |
638 | input soclk; | |
639 | ||
640 | output [35:0] dout; | |
641 | output scan_out; | |
642 | assign fdin[35:0] = din[35:0]; | |
643 | ||
644 | ||
645 | ||
646 | ||
647 | ||
648 | ||
649 | dff #(36) d0_0 ( | |
650 | .l1clk(l1clk), | |
651 | .siclk(siclk), | |
652 | .soclk(soclk), | |
653 | .d(fdin[35:0]), | |
654 | .si({scan_in,so[34:0]}), | |
655 | .so({so[34:0],scan_out}), | |
656 | .q(dout[35:0]) | |
657 | ); | |
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | ||
670 | endmodule | |
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | // any PARAMS parms go into naming of macro | |
685 | ||
686 | module tcu_dmo_ctl_msff_ctl_macro__width_39 ( | |
687 | din, | |
688 | l1clk, | |
689 | scan_in, | |
690 | siclk, | |
691 | soclk, | |
692 | dout, | |
693 | scan_out); | |
694 | wire [38:0] fdin; | |
695 | wire [37:0] so; | |
696 | ||
697 | input [38:0] din; | |
698 | input l1clk; | |
699 | input scan_in; | |
700 | ||
701 | ||
702 | input siclk; | |
703 | input soclk; | |
704 | ||
705 | output [38:0] dout; | |
706 | output scan_out; | |
707 | assign fdin[38:0] = din[38:0]; | |
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | dff #(39) d0_0 ( | |
715 | .l1clk(l1clk), | |
716 | .siclk(siclk), | |
717 | .soclk(soclk), | |
718 | .d(fdin[38:0]), | |
719 | .si({scan_in,so[37:0]}), | |
720 | .so({so[37:0],scan_out}), | |
721 | .q(dout[38:0]) | |
722 | ); | |
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | ||
733 | ||
734 | ||
735 | endmodule | |
736 | ||
737 | ||
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | ||
748 | ||
749 | // any PARAMS parms go into naming of macro | |
750 | ||
751 | module tcu_dmo_ctl_msff_ctl_macro__en_1__width_40 ( | |
752 | din, | |
753 | en, | |
754 | l1clk, | |
755 | scan_in, | |
756 | siclk, | |
757 | soclk, | |
758 | dout, | |
759 | scan_out); | |
760 | wire [39:0] fdin; | |
761 | wire [38:0] so; | |
762 | ||
763 | input [39:0] din; | |
764 | input en; | |
765 | input l1clk; | |
766 | input scan_in; | |
767 | ||
768 | ||
769 | input siclk; | |
770 | input soclk; | |
771 | ||
772 | output [39:0] dout; | |
773 | output scan_out; | |
774 | assign fdin[39:0] = (din[39:0] & {40{en}}) | (dout[39:0] & ~{40{en}}); | |
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | dff #(40) d0_0 ( | |
782 | .l1clk(l1clk), | |
783 | .siclk(siclk), | |
784 | .soclk(soclk), | |
785 | .d(fdin[39:0]), | |
786 | .si({scan_in,so[38:0]}), | |
787 | .so({so[38:0],scan_out}), | |
788 | .q(dout[39:0]) | |
789 | ); | |
790 | ||
791 | ||
792 | ||
793 | ||
794 | ||
795 | ||
796 | ||
797 | ||
798 | ||
799 | ||
800 | ||
801 | ||
802 | endmodule | |
803 | ||
804 | ||
805 | ||
806 | ||
807 | ||
808 | ||
809 | ||
810 | ||
811 | ||
812 | ||
813 | ||
814 | ||
815 | ||
816 | // any PARAMS parms go into naming of macro | |
817 | ||
818 | module tcu_dmo_ctl_msff_ctl_macro__width_32 ( | |
819 | din, | |
820 | l1clk, | |
821 | scan_in, | |
822 | siclk, | |
823 | soclk, | |
824 | dout, | |
825 | scan_out); | |
826 | wire [31:0] fdin; | |
827 | wire [30:0] so; | |
828 | ||
829 | input [31:0] din; | |
830 | input l1clk; | |
831 | input scan_in; | |
832 | ||
833 | ||
834 | input siclk; | |
835 | input soclk; | |
836 | ||
837 | output [31:0] dout; | |
838 | output scan_out; | |
839 | assign fdin[31:0] = din[31:0]; | |
840 | ||
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | dff #(32) d0_0 ( | |
847 | .l1clk(l1clk), | |
848 | .siclk(siclk), | |
849 | .soclk(soclk), | |
850 | .d(fdin[31:0]), | |
851 | .si({scan_in,so[30:0]}), | |
852 | .so({so[30:0],scan_out}), | |
853 | .q(dout[31:0]) | |
854 | ); | |
855 | ||
856 | ||
857 | ||
858 | ||
859 | ||
860 | ||
861 | ||
862 | ||
863 | ||
864 | ||
865 | ||
866 | ||
867 | endmodule | |
868 | ||
869 | ||
870 | ||
871 | ||
872 | ||
873 | ||
874 | ||
875 | ||
876 | ||
877 | ||
878 | ||
879 | ||
880 | ||
881 | // any PARAMS parms go into naming of macro | |
882 | ||
883 | module tcu_dmo_ctl_msff_ctl_macro__en_1__width_16 ( | |
884 | din, | |
885 | en, | |
886 | l1clk, | |
887 | scan_in, | |
888 | siclk, | |
889 | soclk, | |
890 | dout, | |
891 | scan_out); | |
892 | wire [15:0] fdin; | |
893 | wire [14:0] so; | |
894 | ||
895 | input [15:0] din; | |
896 | input en; | |
897 | input l1clk; | |
898 | input scan_in; | |
899 | ||
900 | ||
901 | input siclk; | |
902 | input soclk; | |
903 | ||
904 | output [15:0] dout; | |
905 | output scan_out; | |
906 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
907 | ||
908 | ||
909 | ||
910 | ||
911 | ||
912 | ||
913 | dff #(16) d0_0 ( | |
914 | .l1clk(l1clk), | |
915 | .siclk(siclk), | |
916 | .soclk(soclk), | |
917 | .d(fdin[15:0]), | |
918 | .si({scan_in,so[14:0]}), | |
919 | .so({so[14:0],scan_out}), | |
920 | .q(dout[15:0]) | |
921 | ); | |
922 | ||
923 | ||
924 | ||
925 | ||
926 | ||
927 | ||
928 | ||
929 | ||
930 | ||
931 | ||
932 | ||
933 | ||
934 | endmodule | |
935 | ||
936 | ||
937 | ||
938 | ||
939 | ||
940 | ||
941 | ||
942 | ||
943 | ||
944 | ||
945 | ||
946 | ||
947 | ||
948 | // any PARAMS parms go into naming of macro | |
949 | ||
950 | module tcu_dmo_ctl_msff_ctl_macro__en_1__width_1 ( | |
951 | din, | |
952 | en, | |
953 | l1clk, | |
954 | scan_in, | |
955 | siclk, | |
956 | soclk, | |
957 | dout, | |
958 | scan_out); | |
959 | wire [0:0] fdin; | |
960 | ||
961 | input [0:0] din; | |
962 | input en; | |
963 | input l1clk; | |
964 | input scan_in; | |
965 | ||
966 | ||
967 | input siclk; | |
968 | input soclk; | |
969 | ||
970 | output [0:0] dout; | |
971 | output scan_out; | |
972 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
973 | ||
974 | ||
975 | ||
976 | ||
977 | ||
978 | ||
979 | dff #(1) d0_0 ( | |
980 | .l1clk(l1clk), | |
981 | .siclk(siclk), | |
982 | .soclk(soclk), | |
983 | .d(fdin[0:0]), | |
984 | .si(scan_in), | |
985 | .so(scan_out), | |
986 | .q(dout[0:0]) | |
987 | ); | |
988 | ||
989 | ||
990 | ||
991 | ||
992 | ||
993 | ||
994 | ||
995 | ||
996 | ||
997 | ||
998 | ||
999 | ||
1000 | endmodule | |
1001 | ||
1002 | ||
1003 | ||
1004 | ||
1005 | ||
1006 | ||
1007 | ||
1008 | ||
1009 | ||
1010 | ||
1011 | ||
1012 | ||
1013 | ||
1014 | // any PARAMS parms go into naming of macro | |
1015 | ||
1016 | module tcu_dmo_ctl_msff_ctl_macro__clr__1__width_1 ( | |
1017 | din, | |
1018 | clr_, | |
1019 | l1clk, | |
1020 | scan_in, | |
1021 | siclk, | |
1022 | soclk, | |
1023 | dout, | |
1024 | scan_out); | |
1025 | wire [0:0] fdin; | |
1026 | ||
1027 | input [0:0] din; | |
1028 | input clr_; | |
1029 | input l1clk; | |
1030 | input scan_in; | |
1031 | ||
1032 | ||
1033 | input siclk; | |
1034 | input soclk; | |
1035 | ||
1036 | output [0:0] dout; | |
1037 | output scan_out; | |
1038 | assign fdin[0:0] = din[0:0] & ~{1{(~clr_)}}; | |
1039 | ||
1040 | ||
1041 | ||
1042 | ||
1043 | ||
1044 | ||
1045 | dff #(1) d0_0 ( | |
1046 | .l1clk(l1clk), | |
1047 | .siclk(siclk), | |
1048 | .soclk(soclk), | |
1049 | .d(fdin[0:0]), | |
1050 | .si(scan_in), | |
1051 | .so(scan_out), | |
1052 | .q(dout[0:0]) | |
1053 | ); | |
1054 | ||
1055 | ||
1056 | ||
1057 | ||
1058 | ||
1059 | ||
1060 | ||
1061 | ||
1062 | ||
1063 | ||
1064 | ||
1065 | ||
1066 | endmodule | |
1067 | ||
1068 | ||
1069 | ||
1070 | ||
1071 | ||
1072 | ||
1073 | ||
1074 | ||
1075 | ||
1076 | ||
1077 | ||
1078 | ||
1079 | ||
1080 | // any PARAMS parms go into naming of macro | |
1081 | ||
1082 | module tcu_dmo_ctl_msff_ctl_macro__en_1__width_3 ( | |
1083 | din, | |
1084 | en, | |
1085 | l1clk, | |
1086 | scan_in, | |
1087 | siclk, | |
1088 | soclk, | |
1089 | dout, | |
1090 | scan_out); | |
1091 | wire [2:0] fdin; | |
1092 | wire [1:0] so; | |
1093 | ||
1094 | input [2:0] din; | |
1095 | input en; | |
1096 | input l1clk; | |
1097 | input scan_in; | |
1098 | ||
1099 | ||
1100 | input siclk; | |
1101 | input soclk; | |
1102 | ||
1103 | output [2:0] dout; | |
1104 | output scan_out; | |
1105 | assign fdin[2:0] = (din[2:0] & {3{en}}) | (dout[2:0] & ~{3{en}}); | |
1106 | ||
1107 | ||
1108 | ||
1109 | ||
1110 | ||
1111 | ||
1112 | dff #(3) d0_0 ( | |
1113 | .l1clk(l1clk), | |
1114 | .siclk(siclk), | |
1115 | .soclk(soclk), | |
1116 | .d(fdin[2:0]), | |
1117 | .si({scan_in,so[1:0]}), | |
1118 | .so({so[1:0],scan_out}), | |
1119 | .q(dout[2:0]) | |
1120 | ); | |
1121 | ||
1122 | ||
1123 | ||
1124 | ||
1125 | ||
1126 | ||
1127 | ||
1128 | ||
1129 | ||
1130 | ||
1131 | ||
1132 | ||
1133 | endmodule | |
1134 | ||
1135 | ||
1136 | ||
1137 | ||
1138 | ||
1139 | ||
1140 | ||
1141 |