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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_ucbbusin8_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define UCB_BUS_WIDTH 8 | |
36 | `define UCB_BUS_WIDTH_M1 7 | |
37 | `define CYC_NUM 16 | |
38 | `define CYC_NUM_M1 15 | |
39 | ||
40 | module tcu_ucbbusin8_ctl ( | |
41 | iol2clk, | |
42 | scan_in, | |
43 | scan_out, | |
44 | tcu_int_ce, | |
45 | tcu_pce_ov, | |
46 | tcu_clk_stop, | |
47 | tcu_siclk_in, | |
48 | tcu_soclk_in, | |
49 | tcu_scan_en, | |
50 | vld, | |
51 | data, | |
52 | stall, | |
53 | indata_buf_vld, | |
54 | indata_buf, | |
55 | stall_a1) ; | |
56 | wire stall_d1_; | |
57 | wire stall_d1; | |
58 | wire vld_d1_ff_scanin; | |
59 | wire vld_d1_ff_scanout; | |
60 | wire vld_d1; | |
61 | wire l1clk; | |
62 | wire data_d1_ff_scanin; | |
63 | wire data_d1_ff_scanout; | |
64 | wire [7:0] data_d1; | |
65 | wire stall_ff_scanin; | |
66 | wire stall_ff_scanout; | |
67 | wire stall_d1_ff_scanin; | |
68 | wire stall_d1_ff_scanout; | |
69 | wire skid_buf0_en; | |
70 | wire vld_buf0_ff_scanin; | |
71 | wire vld_buf0_ff_scanout; | |
72 | wire vld_buf0; | |
73 | wire data_buf0_ff_scanin; | |
74 | wire data_buf0_ff_scanout; | |
75 | wire [7:0] data_buf0; | |
76 | wire skid_buf1_en_ff_scanin; | |
77 | wire skid_buf1_en_ff_scanout; | |
78 | wire skid_buf1_en; | |
79 | wire vld_buf1_ff_scanin; | |
80 | wire vld_buf1_ff_scanout; | |
81 | wire vld_buf1; | |
82 | wire data_buf1_ff_scanin; | |
83 | wire data_buf1_ff_scanout; | |
84 | wire [7:0] data_buf1; | |
85 | wire skid_buf0_sel; | |
86 | wire skid_buf1_sel_ff_scanin; | |
87 | wire skid_buf1_sel_ff_scanout; | |
88 | wire skid_buf1_sel; | |
89 | wire vld_mux; | |
90 | wire [7:0] data_mux; | |
91 | wire [15:0] indata_vec_next; | |
92 | wire [15:0] indata_vec; | |
93 | wire stall_a1_; | |
94 | wire indata_vec_ff_scanin; | |
95 | wire indata_vec_ff_scanout; | |
96 | wire [127:0] indata_buf_next; | |
97 | wire indata_buf_ff_scanin; | |
98 | wire indata_buf_ff_scanout; | |
99 | wire indata_vec0_d1_ff_scanin; | |
100 | wire indata_vec0_d1_ff_scanout; | |
101 | wire indata_vec0_d1; | |
102 | wire siclk; | |
103 | wire soclk; | |
104 | wire l1en; | |
105 | wire pce_ov; | |
106 | wire stop; | |
107 | wire se; | |
108 | ||
109 | ||
110 | //////////////////////////////////////////////////////////////////////// | |
111 | // Signal declarations | |
112 | //////////////////////////////////////////////////////////////////////// | |
113 | // Global interface | |
114 | input iol2clk; | |
115 | input scan_in; | |
116 | output scan_out; | |
117 | input tcu_int_ce; | |
118 | input tcu_pce_ov; | |
119 | input tcu_clk_stop; | |
120 | input tcu_siclk_in; | |
121 | input tcu_soclk_in; | |
122 | input tcu_scan_en; | |
123 | ||
124 | // UCB bus interface | |
125 | input vld; | |
126 | input [`UCB_BUS_WIDTH_M1 :0] data; | |
127 | output stall; | |
128 | ||
129 | ||
130 | // Local interface | |
131 | output indata_buf_vld; | |
132 | output [127:0] indata_buf; | |
133 | input stall_a1; | |
134 | ||
135 | ||
136 | // Internal signals | |
137 | ||
138 | ||
139 | //////////////////////////////////////////////////////////////////////// | |
140 | // Code starts here | |
141 | //////////////////////////////////////////////////////////////////////// | |
142 | /************************************************************ | |
143 | * UCB bus interface flops | |
144 | * This is to make signals going between IOB and UCB flop-to-flop | |
145 | * to improve timing. | |
146 | ************************************************************/ | |
147 | assign stall_d1_ = ~stall_d1; | |
148 | ||
149 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_d1_ff | |
150 | ( | |
151 | .scan_in(vld_d1_ff_scanin), | |
152 | .scan_out(vld_d1_ff_scanout), | |
153 | .dout (vld_d1), | |
154 | .l1clk (l1clk), | |
155 | .en (stall_d1_), | |
156 | .din (vld), | |
157 | .siclk(siclk), | |
158 | .soclk(soclk) | |
159 | ); | |
160 | ||
161 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_d1_ff | |
162 | ( | |
163 | .scan_in(data_d1_ff_scanin), | |
164 | .scan_out(data_d1_ff_scanout), | |
165 | .dout (data_d1[`UCB_BUS_WIDTH_M1 :0]), | |
166 | .l1clk (l1clk), | |
167 | .en (stall_d1_), | |
168 | .din (data[`UCB_BUS_WIDTH_M1 :0]), | |
169 | .siclk(siclk), | |
170 | .soclk(soclk) | |
171 | ); | |
172 | ||
173 | tcu_ucbbusin8_ctl_msff_ctl_macro__width_1 stall_ff | |
174 | ( | |
175 | .scan_in(stall_ff_scanin), | |
176 | .scan_out(stall_ff_scanout), | |
177 | .dout (stall), | |
178 | .l1clk (l1clk), | |
179 | .din (stall_a1), | |
180 | .siclk(siclk), | |
181 | .soclk(soclk) | |
182 | ); | |
183 | ||
184 | tcu_ucbbusin8_ctl_msff_ctl_macro__width_1 stall_d1_ff | |
185 | ( | |
186 | .scan_in(stall_d1_ff_scanin), | |
187 | .scan_out(stall_d1_ff_scanout), | |
188 | .dout (stall_d1), | |
189 | .l1clk (l1clk), | |
190 | .din (stall), | |
191 | .siclk(siclk), | |
192 | .soclk(soclk) | |
193 | ); | |
194 | ||
195 | ||
196 | /************************************************************ | |
197 | * Skid buffer | |
198 | * We need a two deep skid buffer to handle stalling. | |
199 | ************************************************************/ | |
200 | // Assertion: stall has to be deasserted for more than 1 cycle | |
201 | // ie time between two separate stalls has to be | |
202 | // at least two cycles. Otherwise, contents from | |
203 | // skid buffer will be lost. | |
204 | ||
205 | // Buffer 0 | |
206 | assign skid_buf0_en = stall_a1 & ~stall; | |
207 | ||
208 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_buf0_ff | |
209 | ( | |
210 | .scan_in(vld_buf0_ff_scanin), | |
211 | .scan_out(vld_buf0_ff_scanout), | |
212 | .dout (vld_buf0), | |
213 | .l1clk (l1clk), | |
214 | .en (skid_buf0_en), | |
215 | .din (vld_d1), | |
216 | .siclk(siclk), | |
217 | .soclk(soclk) | |
218 | ); | |
219 | ||
220 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_buf0_ff | |
221 | ( | |
222 | .scan_in(data_buf0_ff_scanin), | |
223 | .scan_out(data_buf0_ff_scanout), | |
224 | .dout (data_buf0[`UCB_BUS_WIDTH_M1 :0]), | |
225 | .l1clk (l1clk), | |
226 | .en (skid_buf0_en), | |
227 | .din (data_d1[`UCB_BUS_WIDTH_M1 :0]), | |
228 | .siclk(siclk), | |
229 | .soclk(soclk) | |
230 | ); | |
231 | ||
232 | // Buffer 1 | |
233 | tcu_ucbbusin8_ctl_msff_ctl_macro__width_1 skid_buf1_en_ff | |
234 | ( | |
235 | .scan_in(skid_buf1_en_ff_scanin), | |
236 | .scan_out(skid_buf1_en_ff_scanout), | |
237 | .dout (skid_buf1_en), | |
238 | .l1clk (l1clk), | |
239 | .din (skid_buf0_en), | |
240 | .siclk(siclk), | |
241 | .soclk(soclk) | |
242 | ); | |
243 | ||
244 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 vld_buf1_ff | |
245 | ( | |
246 | .scan_in(vld_buf1_ff_scanin), | |
247 | .scan_out(vld_buf1_ff_scanout), | |
248 | .dout (vld_buf1), | |
249 | .l1clk (l1clk), | |
250 | .en (skid_buf1_en), | |
251 | .din (vld_d1), | |
252 | .siclk(siclk), | |
253 | .soclk(soclk) | |
254 | ); | |
255 | ||
256 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 data_buf1_ff | |
257 | ( | |
258 | .scan_in(data_buf1_ff_scanin), | |
259 | .scan_out(data_buf1_ff_scanout), | |
260 | .dout (data_buf1[`UCB_BUS_WIDTH_M1 :0]), | |
261 | .l1clk (l1clk), | |
262 | .en (skid_buf1_en), | |
263 | .din (data_d1[`UCB_BUS_WIDTH_M1 :0]), | |
264 | .siclk(siclk), | |
265 | .soclk(soclk) | |
266 | ); | |
267 | ||
268 | ||
269 | /************************************************************ | |
270 | * Mux between skid buffer and interface flop | |
271 | ************************************************************/ | |
272 | // Assertion: stall has to be deasserted for more than 1 cycle | |
273 | // ie time between two separate stalls has to be | |
274 | // at least two cycles. Otherwise, contents from | |
275 | // skid buffer will be lost. | |
276 | ||
277 | assign skid_buf0_sel = ~stall_a1 & stall; | |
278 | ||
279 | tcu_ucbbusin8_ctl_msff_ctl_macro__width_1 skid_buf1_sel_ff | |
280 | ( | |
281 | .scan_in(skid_buf1_sel_ff_scanin), | |
282 | .scan_out(skid_buf1_sel_ff_scanout), | |
283 | .dout (skid_buf1_sel), | |
284 | .l1clk (l1clk), | |
285 | .din (skid_buf0_sel), | |
286 | .siclk(siclk), | |
287 | .soclk(soclk) | |
288 | ); | |
289 | ||
290 | assign vld_mux = skid_buf0_sel ? vld_buf0 : | |
291 | skid_buf1_sel ? vld_buf1 : | |
292 | vld_d1; | |
293 | ||
294 | assign data_mux[`UCB_BUS_WIDTH_M1 :0] = skid_buf0_sel ? data_buf0[`UCB_BUS_WIDTH_M1 :0] : | |
295 | skid_buf1_sel ? data_buf1[`UCB_BUS_WIDTH_M1 :0] : | |
296 | data_d1[`UCB_BUS_WIDTH_M1 :0]; | |
297 | ||
298 | ||
299 | /************************************************************ | |
300 | * Assemble inbound data | |
301 | ************************************************************/ | |
302 | // valid vector | |
303 | assign indata_vec_next[`CYC_NUM_M1:0] = {vld_mux, indata_vec[`CYC_NUM_M1 :1]}; | |
304 | ||
305 | assign stall_a1_ = ~stall_a1; | |
306 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_16 indata_vec_ff | |
307 | ( | |
308 | .scan_in(indata_vec_ff_scanin), | |
309 | .scan_out(indata_vec_ff_scanout), | |
310 | .dout (indata_vec[`CYC_NUM_M1 :0]), | |
311 | .l1clk (l1clk), | |
312 | .en (stall_a1_), | |
313 | .din (indata_vec_next[`CYC_NUM_M1 :0]), | |
314 | .siclk(siclk), | |
315 | .soclk(soclk) | |
316 | ); | |
317 | ||
318 | // data buffer | |
319 | assign indata_buf_next[127:0] = {data_mux[`UCB_BUS_WIDTH_M1 :0], indata_buf[127:`UCB_BUS_WIDTH ]}; | |
320 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_128 indata_buf_ff | |
321 | ( | |
322 | .scan_in(indata_buf_ff_scanin), | |
323 | .scan_out(indata_buf_ff_scanout), | |
324 | .dout (indata_buf[127:0]), | |
325 | .l1clk (l1clk), | |
326 | .en (stall_a1_), | |
327 | .din (indata_buf_next[127:0]), | |
328 | .siclk(siclk), | |
329 | .soclk(soclk) | |
330 | ); | |
331 | ||
332 | // detect a new packet | |
333 | tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 indata_vec0_d1_ff | |
334 | ( | |
335 | .scan_in(indata_vec0_d1_ff_scanin), | |
336 | .scan_out(indata_vec0_d1_ff_scanout), | |
337 | .dout (indata_vec0_d1), | |
338 | .l1clk (l1clk), | |
339 | .en (stall_a1_), | |
340 | .din (indata_vec[0]), | |
341 | .siclk(siclk), | |
342 | .soclk(soclk) | |
343 | ); | |
344 | ||
345 | assign indata_buf_vld = indata_vec[0] & ~indata_vec0_d1; | |
346 | ||
347 | ||
348 | ||
349 | /**** adding clock header ****/ | |
350 | tcu_ucbbusin8_ctl_l1clkhdr_ctl_macro clkgen ( | |
351 | .l2clk (iol2clk), | |
352 | .l1clk (l1clk), | |
353 | .l1en(l1en), | |
354 | .pce_ov(pce_ov), | |
355 | .stop(stop), | |
356 | .se(se) | |
357 | ); | |
358 | ||
359 | /*** building tcu port ***/ | |
360 | assign siclk = tcu_siclk_in; | |
361 | assign soclk = tcu_soclk_in; | |
362 | assign l1en = tcu_int_ce; // 1'b1 | |
363 | assign pce_ov = tcu_pce_ov; | |
364 | assign stop = tcu_clk_stop; | |
365 | assign se = tcu_scan_en; | |
366 | ||
367 | // fixscan start: | |
368 | assign vld_d1_ff_scanin = scan_in ; | |
369 | assign data_d1_ff_scanin = vld_d1_ff_scanout ; | |
370 | assign stall_ff_scanin = data_d1_ff_scanout ; | |
371 | assign stall_d1_ff_scanin = stall_ff_scanout ; | |
372 | assign vld_buf0_ff_scanin = stall_d1_ff_scanout ; | |
373 | assign data_buf0_ff_scanin = vld_buf0_ff_scanout ; | |
374 | assign skid_buf1_en_ff_scanin = data_buf0_ff_scanout ; | |
375 | assign vld_buf1_ff_scanin = skid_buf1_en_ff_scanout ; | |
376 | assign data_buf1_ff_scanin = vld_buf1_ff_scanout ; | |
377 | assign skid_buf1_sel_ff_scanin = data_buf1_ff_scanout ; | |
378 | assign indata_vec_ff_scanin = skid_buf1_sel_ff_scanout ; | |
379 | assign indata_buf_ff_scanin = indata_vec_ff_scanout ; | |
380 | assign indata_vec0_d1_ff_scanin = indata_buf_ff_scanout ; | |
381 | assign scan_out = indata_vec0_d1_ff_scanout; | |
382 | // fixscan end: | |
383 | endmodule // ucb_bus_in | |
384 | ||
385 | ||
386 | ||
387 | ||
388 | ||
389 | ||
390 | // any PARAMS parms go into naming of macro | |
391 | ||
392 | module tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_1 ( | |
393 | din, | |
394 | en, | |
395 | l1clk, | |
396 | scan_in, | |
397 | siclk, | |
398 | soclk, | |
399 | dout, | |
400 | scan_out); | |
401 | wire [0:0] fdin; | |
402 | ||
403 | input [0:0] din; | |
404 | input en; | |
405 | input l1clk; | |
406 | input scan_in; | |
407 | ||
408 | ||
409 | input siclk; | |
410 | input soclk; | |
411 | ||
412 | output [0:0] dout; | |
413 | output scan_out; | |
414 | assign fdin[0:0] = (din[0:0] & {1{en}}) | (dout[0:0] & ~{1{en}}); | |
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | ||
421 | dff #(1) d0_0 ( | |
422 | .l1clk(l1clk), | |
423 | .siclk(siclk), | |
424 | .soclk(soclk), | |
425 | .d(fdin[0:0]), | |
426 | .si(scan_in), | |
427 | .so(scan_out), | |
428 | .q(dout[0:0]) | |
429 | ); | |
430 | ||
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 | ||
441 | ||
442 | endmodule | |
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | ||
449 | ||
450 | ||
451 | ||
452 | ||
453 | ||
454 | ||
455 | ||
456 | // any PARAMS parms go into naming of macro | |
457 | ||
458 | module tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_8 ( | |
459 | din, | |
460 | en, | |
461 | l1clk, | |
462 | scan_in, | |
463 | siclk, | |
464 | soclk, | |
465 | dout, | |
466 | scan_out); | |
467 | wire [7:0] fdin; | |
468 | wire [6:0] so; | |
469 | ||
470 | input [7:0] din; | |
471 | input en; | |
472 | input l1clk; | |
473 | input scan_in; | |
474 | ||
475 | ||
476 | input siclk; | |
477 | input soclk; | |
478 | ||
479 | output [7:0] dout; | |
480 | output scan_out; | |
481 | assign fdin[7:0] = (din[7:0] & {8{en}}) | (dout[7:0] & ~{8{en}}); | |
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | dff #(8) d0_0 ( | |
489 | .l1clk(l1clk), | |
490 | .siclk(siclk), | |
491 | .soclk(soclk), | |
492 | .d(fdin[7:0]), | |
493 | .si({scan_in,so[6:0]}), | |
494 | .so({so[6:0],scan_out}), | |
495 | .q(dout[7:0]) | |
496 | ); | |
497 | ||
498 | ||
499 | ||
500 | ||
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | endmodule | |
510 | ||
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | ||
518 | ||
519 | ||
520 | ||
521 | ||
522 | ||
523 | // any PARAMS parms go into naming of macro | |
524 | ||
525 | module tcu_ucbbusin8_ctl_msff_ctl_macro__width_1 ( | |
526 | din, | |
527 | l1clk, | |
528 | scan_in, | |
529 | siclk, | |
530 | soclk, | |
531 | dout, | |
532 | scan_out); | |
533 | wire [0:0] fdin; | |
534 | ||
535 | input [0:0] din; | |
536 | input l1clk; | |
537 | input scan_in; | |
538 | ||
539 | ||
540 | input siclk; | |
541 | input soclk; | |
542 | ||
543 | output [0:0] dout; | |
544 | output scan_out; | |
545 | assign fdin[0:0] = din[0:0]; | |
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | dff #(1) d0_0 ( | |
553 | .l1clk(l1clk), | |
554 | .siclk(siclk), | |
555 | .soclk(soclk), | |
556 | .d(fdin[0:0]), | |
557 | .si(scan_in), | |
558 | .so(scan_out), | |
559 | .q(dout[0:0]) | |
560 | ); | |
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | endmodule | |
574 | ||
575 | ||
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | ||
582 | ||
583 | ||
584 | ||
585 | ||
586 | ||
587 | // any PARAMS parms go into naming of macro | |
588 | ||
589 | module tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_16 ( | |
590 | din, | |
591 | en, | |
592 | l1clk, | |
593 | scan_in, | |
594 | siclk, | |
595 | soclk, | |
596 | dout, | |
597 | scan_out); | |
598 | wire [15:0] fdin; | |
599 | wire [14:0] so; | |
600 | ||
601 | input [15:0] din; | |
602 | input en; | |
603 | input l1clk; | |
604 | input scan_in; | |
605 | ||
606 | ||
607 | input siclk; | |
608 | input soclk; | |
609 | ||
610 | output [15:0] dout; | |
611 | output scan_out; | |
612 | assign fdin[15:0] = (din[15:0] & {16{en}}) | (dout[15:0] & ~{16{en}}); | |
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | dff #(16) d0_0 ( | |
620 | .l1clk(l1clk), | |
621 | .siclk(siclk), | |
622 | .soclk(soclk), | |
623 | .d(fdin[15:0]), | |
624 | .si({scan_in,so[14:0]}), | |
625 | .so({so[14:0],scan_out}), | |
626 | .q(dout[15:0]) | |
627 | ); | |
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | endmodule | |
641 | ||
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | ||
653 | ||
654 | // any PARAMS parms go into naming of macro | |
655 | ||
656 | module tcu_ucbbusin8_ctl_msff_ctl_macro__en_1__width_128 ( | |
657 | din, | |
658 | en, | |
659 | l1clk, | |
660 | scan_in, | |
661 | siclk, | |
662 | soclk, | |
663 | dout, | |
664 | scan_out); | |
665 | wire [127:0] fdin; | |
666 | wire [126:0] so; | |
667 | ||
668 | input [127:0] din; | |
669 | input en; | |
670 | input l1clk; | |
671 | input scan_in; | |
672 | ||
673 | ||
674 | input siclk; | |
675 | input soclk; | |
676 | ||
677 | output [127:0] dout; | |
678 | output scan_out; | |
679 | assign fdin[127:0] = (din[127:0] & {128{en}}) | (dout[127:0] & ~{128{en}}); | |
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | dff #(128) d0_0 ( | |
687 | .l1clk(l1clk), | |
688 | .siclk(siclk), | |
689 | .soclk(soclk), | |
690 | .d(fdin[127:0]), | |
691 | .si({scan_in,so[126:0]}), | |
692 | .so({so[126:0],scan_out}), | |
693 | .q(dout[127:0]) | |
694 | ); | |
695 | ||
696 | ||
697 | ||
698 | ||
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | endmodule | |
708 | ||
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | ||
720 | ||
721 | // any PARAMS parms go into naming of macro | |
722 | ||
723 | module tcu_ucbbusin8_ctl_l1clkhdr_ctl_macro ( | |
724 | l2clk, | |
725 | l1en, | |
726 | pce_ov, | |
727 | stop, | |
728 | se, | |
729 | l1clk); | |
730 | ||
731 | ||
732 | input l2clk; | |
733 | input l1en; | |
734 | input pce_ov; | |
735 | input stop; | |
736 | input se; | |
737 | output l1clk; | |
738 | ||
739 | ||
740 | ||
741 | ||
742 | ||
743 | cl_sc1_l1hdr_8x c_0 ( | |
744 | ||
745 | ||
746 | .l2clk(l2clk), | |
747 | .pce(l1en), | |
748 | .l1clk(l1clk), | |
749 | .se(se), | |
750 | .pce_ov(pce_ov), | |
751 | .stop(stop) | |
752 | ); | |
753 | ||
754 | ||
755 | ||
756 | endmodule | |
757 | ||
758 | ||
759 | ||
760 | ||
761 | ||
762 | ||
763 | ||
764 |