Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tcu_ucbbusout8_ctl.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define UCB_BUS_WIDTH 8 | |
36 | `define UCB_BUS_WIDTH_M1 7 | |
37 | `define CYC_NUM 16 | |
38 | `define CYC_NUM_M1 15 | |
39 | ||
40 | module tcu_ucbbusout8_ctl ( | |
41 | iol2clk, | |
42 | scan_in, | |
43 | scan_out, | |
44 | tcu_int_ce, | |
45 | tcu_pce_ov, | |
46 | tcu_clk_stop, | |
47 | tcu_siclk_in, | |
48 | tcu_soclk_in, | |
49 | tcu_scan_en, | |
50 | vld, | |
51 | data, | |
52 | stall, | |
53 | outdata_buf_busy, | |
54 | outdata_buf_in, | |
55 | outdata_vec_in, | |
56 | outdata_buf_wr) ; | |
57 | wire [15:0] outdata_vec; | |
58 | wire [127:0] outdata_buf; | |
59 | wire stall_d1_ff_scanin; | |
60 | wire stall_d1_ff_scanout; | |
61 | wire stall_d1; | |
62 | wire l1clk; | |
63 | wire load_outdata; | |
64 | wire shift_outdata; | |
65 | wire [15:0] outdata_vec_next; | |
66 | wire outdata_vec_ff_scanin; | |
67 | wire outdata_vec_ff_scanout; | |
68 | wire [127:0] outdata_buf_next; | |
69 | wire outdata_buf_ff_scanin; | |
70 | wire outdata_buf_ff_scanout; | |
71 | wire siclk; | |
72 | wire soclk; | |
73 | wire l1en; | |
74 | wire pce_ov; | |
75 | wire stop; | |
76 | wire se; | |
77 | ||
78 | ||
79 | // Globals | |
80 | input iol2clk; | |
81 | input scan_in; | |
82 | output scan_out; | |
83 | input tcu_int_ce; | |
84 | input tcu_pce_ov; | |
85 | input tcu_clk_stop; | |
86 | input tcu_siclk_in; | |
87 | input tcu_soclk_in; | |
88 | input tcu_scan_en; | |
89 | ||
90 | // UCB bus interface | |
91 | output vld; | |
92 | output [`UCB_BUS_WIDTH_M1 :0] data; | |
93 | input stall; | |
94 | ||
95 | // Local interface | |
96 | output outdata_buf_busy; | |
97 | input [127:0] outdata_buf_in; | |
98 | input [`CYC_NUM_M1 :0] outdata_vec_in; | |
99 | input outdata_buf_wr; | |
100 | ||
101 | // Local signals | |
102 | ||
103 | //////////////////////////////////////////////////////////////////////// | |
104 | // Code starts here | |
105 | //////////////////////////////////////////////////////////////////////// | |
106 | /************************************************************ | |
107 | * UCB bus interface flops | |
108 | ************************************************************/ | |
109 | assign vld = outdata_vec[0]; | |
110 | assign data[`UCB_BUS_WIDTH_M1 :0] = outdata_buf[`UCB_BUS_WIDTH_M1 :0]; | |
111 | ||
112 | tcu_ucbbusout8_ctl_msff_ctl_macro__width_1 stall_d1_ff | |
113 | ( | |
114 | .scan_in(stall_d1_ff_scanin), | |
115 | .scan_out(stall_d1_ff_scanout), | |
116 | .dout (stall_d1), | |
117 | .l1clk (l1clk), | |
118 | .din (stall), | |
119 | .siclk(siclk), | |
120 | .soclk(soclk) | |
121 | ); | |
122 | ||
123 | /************************************************************ | |
124 | * Outbound Data | |
125 | ************************************************************/ | |
126 | // accept new data only if there is none being processed | |
127 | assign load_outdata = outdata_buf_wr & ~outdata_buf_busy; | |
128 | ||
129 | assign outdata_buf_busy = outdata_vec[0] | stall_d1; | |
130 | ||
131 | assign shift_outdata = outdata_vec[0] & ~stall_d1; | |
132 | ||
133 | assign outdata_vec_next[`CYC_NUM_M1 :0] = | |
134 | load_outdata ? outdata_vec_in[`CYC_NUM_M1 :0] : | |
135 | shift_outdata ? {1'b0,outdata_vec[`CYC_NUM_M1 :1]} : | |
136 | outdata_vec[`CYC_NUM_M1 :0] ; | |
137 | ||
138 | tcu_ucbbusout8_ctl_msff_ctl_macro__width_16 outdata_vec_ff | |
139 | ( | |
140 | .scan_in(outdata_vec_ff_scanin), | |
141 | .scan_out(outdata_vec_ff_scanout), | |
142 | .dout (outdata_vec[`CYC_NUM_M1 :0]), | |
143 | .l1clk (l1clk), | |
144 | .din (outdata_vec_next[`CYC_NUM_M1 :0]), | |
145 | .siclk(siclk), | |
146 | .soclk(soclk) | |
147 | ); | |
148 | ||
149 | assign outdata_buf_next[127:0] = load_outdata ? outdata_buf_in[127:0] : | |
150 | shift_outdata ? (outdata_buf[127:0] >> `UCB_BUS_WIDTH ) : | |
151 | outdata_buf[127:0] ; | |
152 | ||
153 | tcu_ucbbusout8_ctl_msff_ctl_macro__width_128 outdata_buf_ff | |
154 | ( | |
155 | .scan_in(outdata_buf_ff_scanin), | |
156 | .scan_out(outdata_buf_ff_scanout), | |
157 | .dout (outdata_buf[127:0]), | |
158 | .l1clk (l1clk), | |
159 | .din (outdata_buf_next[127:0]), | |
160 | .siclk(siclk), | |
161 | .soclk(soclk) | |
162 | ); | |
163 | ||
164 | ||
165 | ||
166 | /**** adding clock header ****/ | |
167 | tcu_ucbbusout8_ctl_l1clkhdr_ctl_macro clkgen ( | |
168 | .l2clk (iol2clk), | |
169 | .l1clk (l1clk), | |
170 | .l1en(l1en), | |
171 | .pce_ov(pce_ov), | |
172 | .stop(stop), | |
173 | .se(se) | |
174 | ); | |
175 | ||
176 | /*** building tcu port ***/ | |
177 | assign siclk = tcu_siclk_in; | |
178 | assign soclk = tcu_soclk_in; | |
179 | assign l1en = tcu_int_ce; // 1'1b | |
180 | assign pce_ov = tcu_pce_ov; | |
181 | assign stop = tcu_clk_stop; | |
182 | assign se = tcu_scan_en; | |
183 | ||
184 | // fixscan start: | |
185 | assign stall_d1_ff_scanin = scan_in ; | |
186 | assign outdata_vec_ff_scanin = stall_d1_ff_scanout ; | |
187 | assign outdata_buf_ff_scanin = outdata_vec_ff_scanout ; | |
188 | assign scan_out = outdata_buf_ff_scanout ; | |
189 | // fixscan end: | |
190 | endmodule // ucb_bus_out | |
191 | ||
192 | ||
193 | ||
194 | ||
195 | ||
196 | ||
197 | ||
198 | ||
199 | ||
200 | ||
201 | ||
202 | ||
203 | // any PARAMS parms go into naming of macro | |
204 | ||
205 | module tcu_ucbbusout8_ctl_msff_ctl_macro__width_1 ( | |
206 | din, | |
207 | l1clk, | |
208 | scan_in, | |
209 | siclk, | |
210 | soclk, | |
211 | dout, | |
212 | scan_out); | |
213 | wire [0:0] fdin; | |
214 | ||
215 | input [0:0] din; | |
216 | input l1clk; | |
217 | input scan_in; | |
218 | ||
219 | ||
220 | input siclk; | |
221 | input soclk; | |
222 | ||
223 | output [0:0] dout; | |
224 | output scan_out; | |
225 | assign fdin[0:0] = din[0:0]; | |
226 | ||
227 | ||
228 | ||
229 | ||
230 | ||
231 | ||
232 | dff #(1) d0_0 ( | |
233 | .l1clk(l1clk), | |
234 | .siclk(siclk), | |
235 | .soclk(soclk), | |
236 | .d(fdin[0:0]), | |
237 | .si(scan_in), | |
238 | .so(scan_out), | |
239 | .q(dout[0:0]) | |
240 | ); | |
241 | ||
242 | ||
243 | ||
244 | ||
245 | ||
246 | ||
247 | ||
248 | ||
249 | ||
250 | ||
251 | ||
252 | ||
253 | endmodule | |
254 | ||
255 | ||
256 | ||
257 | ||
258 | ||
259 | ||
260 | ||
261 | ||
262 | ||
263 | ||
264 | ||
265 | ||
266 | ||
267 | // any PARAMS parms go into naming of macro | |
268 | ||
269 | module tcu_ucbbusout8_ctl_msff_ctl_macro__width_16 ( | |
270 | din, | |
271 | l1clk, | |
272 | scan_in, | |
273 | siclk, | |
274 | soclk, | |
275 | dout, | |
276 | scan_out); | |
277 | wire [15:0] fdin; | |
278 | wire [14:0] so; | |
279 | ||
280 | input [15:0] din; | |
281 | input l1clk; | |
282 | input scan_in; | |
283 | ||
284 | ||
285 | input siclk; | |
286 | input soclk; | |
287 | ||
288 | output [15:0] dout; | |
289 | output scan_out; | |
290 | assign fdin[15:0] = din[15:0]; | |
291 | ||
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | dff #(16) d0_0 ( | |
298 | .l1clk(l1clk), | |
299 | .siclk(siclk), | |
300 | .soclk(soclk), | |
301 | .d(fdin[15:0]), | |
302 | .si({scan_in,so[14:0]}), | |
303 | .so({so[14:0],scan_out}), | |
304 | .q(dout[15:0]) | |
305 | ); | |
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | ||
312 | ||
313 | ||
314 | ||
315 | ||
316 | ||
317 | ||
318 | endmodule | |
319 | ||
320 | ||
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | ||
330 | ||
331 | ||
332 | // any PARAMS parms go into naming of macro | |
333 | ||
334 | module tcu_ucbbusout8_ctl_msff_ctl_macro__width_128 ( | |
335 | din, | |
336 | l1clk, | |
337 | scan_in, | |
338 | siclk, | |
339 | soclk, | |
340 | dout, | |
341 | scan_out); | |
342 | wire [127:0] fdin; | |
343 | wire [126:0] so; | |
344 | ||
345 | input [127:0] din; | |
346 | input l1clk; | |
347 | input scan_in; | |
348 | ||
349 | ||
350 | input siclk; | |
351 | input soclk; | |
352 | ||
353 | output [127:0] dout; | |
354 | output scan_out; | |
355 | assign fdin[127:0] = din[127:0]; | |
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | dff #(128) d0_0 ( | |
363 | .l1clk(l1clk), | |
364 | .siclk(siclk), | |
365 | .soclk(soclk), | |
366 | .d(fdin[127:0]), | |
367 | .si({scan_in,so[126:0]}), | |
368 | .so({so[126:0],scan_out}), | |
369 | .q(dout[127:0]) | |
370 | ); | |
371 | ||
372 | ||
373 | ||
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | ||
381 | ||
382 | ||
383 | endmodule | |
384 | ||
385 | ||
386 | ||
387 | ||
388 | ||
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | // any PARAMS parms go into naming of macro | |
398 | ||
399 | module tcu_ucbbusout8_ctl_l1clkhdr_ctl_macro ( | |
400 | l2clk, | |
401 | l1en, | |
402 | pce_ov, | |
403 | stop, | |
404 | se, | |
405 | l1clk); | |
406 | ||
407 | ||
408 | input l2clk; | |
409 | input l1en; | |
410 | input pce_ov; | |
411 | input stop; | |
412 | input se; | |
413 | output l1clk; | |
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | cl_sc1_l1hdr_8x c_0 ( | |
420 | ||
421 | ||
422 | .l2clk(l2clk), | |
423 | .pce(l1en), | |
424 | .l1clk(l1clk), | |
425 | .se(se), | |
426 | .pce_ov(pce_ov), | |
427 | .stop(stop) | |
428 | ); | |
429 | ||
430 | ||
431 | ||
432 | endmodule | |
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | ||
439 | ||
440 |