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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / design / sys / iop / tds / rtl / tds.v
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AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: tds.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35// VPERL: PERL_BEG
36// $VPERL_PORT_COMM = 1;
37// # $VPERL_INST_COMM = 2;
38//
39// &MODULE ("tds");
40// #------------------------------------------------------------
41// #-- Instantiations
42// #------------------------------------------------------------
43// &INSTANCE ("/vobs/neptune/design/niu/smx/rtl/niu_smx.v niu_smx", "niu_smx");
44// &INSTANCE ("/vobs/neptune/design/niu/tds/rtl/niu_meta_arb.v.new niu_meta_arb", "niu_meta_arb");
45// &INSTANCE ("/vobs/neptune/design/niu/tds/rtl/niu_tdmc.v.new niu_tdmc", "niu_tdmc");
46// &INSTANCE ("/vobs/neptune/design/niu/tds/rtl/tds_n2_efuhdr2_ctl.v", "tdmc_sram_header");
47// &INSTANCE ("/vobs/neptune/design/niu/tds/rtl/dmo_regs.v", "dmo_regs");
48// &INSTANCE ("/vobs/neptune/design/niu/n2_lib/clkgen_tds_io2x.v", "clkgen2x_tds");
49// &INSTANCE ("/vobs/neptune/design/niu/tds/rtl/tds_l2l1clk_io.v", "clkgen_tds");
50
51// #------------------------------------------------------------
52// #-- Special Ports
53// #------------------------------------------------------------
54// &FORCE ("output", "meta_dmc_resp_ready");
55// &FORCE ("output", "meta_dmc_resp_cmd[7:0]");
56// &FORCE ("output", "meta_dmc_resp_cmd_status[3:0]");
57// &FORCE ("output", "meta_dmc_resp_address[63:0]");
58// &FORCE ("output", "meta_dmc_resp_length[13:0]");
59// &FORCE ("output", "meta_dmc_resp_trans_id[5:0]");
60// &FORCE ("output", "meta_dmc_resp_port_num[1:0]");
61// &FORCE ("output", "meta_dmc_resp_dma_num[4:0]");
62// # &FORCE ("output", "meta_dmc_resp_client[7:0]");
63// # &FORCE ("output", "meta_dmc_data_valid[7:0]");
64// &FORCE ("output", "meta_dmc_data[127:0]");
65// &FORCE ("output", "meta_dmc_resp_byteenable[15:0]");
66// &FORCE ("output", "meta_dmc_data_status[3:0]");
67// # &FORCE ("output", "meta_dmc_resp_complete[7:0]");
68// # &FORCE ("output", "meta_dmc_resp_transfer_cmpl[7:0]");
69// &FORCE ("output", "meta_dmc_ack_ready");
70// &FORCE ("output", "meta_dmc_ack_cmd[7:0]");
71// &FORCE ("output", "meta_dmc_ack_cmd_status[3:0]");
72// &FORCE ("output", "meta_dmc_ack_dma_num[4:0]");
73// # &FORCE ("output", "meta_dmc_ack_client[7:0]");
74// &FORCE ("output", "dmc_meta1_req_trans_id[5:0]");
75// &FORCE ("output", "tds_tcu_dmo_dout[39:0]");
76
77// &FORCE ("output", "meta1_rdmc_rbr_resp_data[127:0]");
78// &FORCE ("output", "meta1_rdmc_rbr_resp_byteenable[15:0]");
79// &FORCE ("output", "meta1_rdmc_rbr_resp_cmd[7:0]");
80// &FORCE ("output", "meta1_rdmc_rbr_resp_cmd_status[3:0]");
81// &FORCE ("output", "meta1_rdmc_rbr_resp_dma_num[4:0]");
82// &FORCE ("output", "meta1_rdmc_rbr_resp_ready");
83
84// # &FORCE ("input", "txc_dmc_dma_pkt_size_err[23:0]");
85// # &FORCE ("input", "txc_dmc_dma_nack_pkt_rd[23:0]");
86// #-- &FORCE ("input", "txc_dmc_dma_pkt_size_err[15:0]");
87// &FORCE ("input", "txc_dmc_p0_dma_pkt_size_err[15:0]");
88// &FORCE ("input", "txc_dmc_p1_dma_pkt_size_err[15:0]");
89// &FORCE ("input", "txc_dmc_dma_nack_pkt_rd[15:0]");
90
91// #################################
92// # MBIST port:
93// #################################
94
95// &FORCE ("input", "tcu_scan_en");
96// &FORCE ("input", "tcu_aclk");
97// &FORCE ("input", "tcu_bclk");
98// &FORCE ("input", "tcu_tds_io_clk_stop");
99// &FORCE ("input", "tcu_pce_ov");
100
101// # Use for FF Scan Chain
102// &FORCE ("input", "scan_in");
103// &FORCE ("output", "scan_out");
104
105// # Use for MBIST Scan Chain
106// &FORCE ("input", "tds_mbist_scan_in");
107// &FORCE ("output", "tds_mbist_scan_out");
108
109// ################################
110// # clkgen_tds clkgen2x_tds
111// ################################
112// &FORCE ("input", "rst_por_");
113// # &FORCE ("input", "ccu_io_out"); change to gl_tds_io_out I6.1
114// # &FORCE ("input", "ccu_io2x_out");
115// # &FORCE ("input", "gclk");
116// &FORCE ("input", "gl_tds_io_out");
117// &FORCE ("input", "gl_tds_io2x_out");
118// &FORCE ("input", "cmp_gclk_c0_tds");
119// &FORCE ("input", "tcu_atpg_mode");
120// &FORCE ("input", "tcu_wr_inhibit");
121
122// ####################################
123// # SRAM Header
124// ####################################
125
126// &FORCE ("input", "efu_niu_ram_data");
127// &FORCE ("input", "efu_niu_ram_xfer_en");
128// &FORCE ("input", "efu_niu_ram_clr");
129
130// &FORCE ("output", "niu_efu_ram_data");
131// &FORCE ("output", "niu_efu_ram_xfer_en");
132
133// ####################################
134// # Split ports to connect RDP and RTX
135// ####################################
136// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_data[127:0]");
137// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_byteenable[15:0]");
138// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_cmd[7:0]");
139// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_cmd_status[3:0]");
140// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_dma_num[4:0]");
141// &FORCE ("wire", "x_meta1_rdmc_rbr_resp_ready");
142// &FORCE ("wire", "tds_tcu_dmo_data_out[39:0]");
143// &FORCE ("wire", "l1clk");
144// &FORCE ("wire", "iol2clk");
145// &FORCE ("wire", "io2xl2clk");
146// &FORCE ("wire", "ioclk_scan_out");
147// &FORCE ("wire", "io2xclk_scan_out");
148// &FORCE ("wire", "tds_pce_ov");
149
150// ####################################
151// # USE FOR UNCONNECT PORTS:
152// ####################################
153// &FORCE ("wire", "unconnected_1[10:7]");
154// &FORCE ("wire", "unconnected_2[10:2]");
155
156// &FORCE ("wire", "tds_array_wr_inhibit");
157
158// #------------------------------------------------------------
159// #-- Explicit connections
160// #------------------------------------------------------------
161// &CONNECT ("clkgen_tds.rst_por_", "rst_por_");
162// # Note: the ccu_*sync_en connections will be removed
163// # &CONNECT ("clkgen_tds.ccu_cmp_slow_sync_en", "ccu_cmp_io_sync_en");
164// # &CONNECT ("clkgen_tds.ccu_slow_cmp_sync_en", "ccu_io_cmp_sync_en");
165// # &CONNECT ("clkgen_tds.clk_ext", "1'b0");
166// # &CONNECT ("clkgen_tds.ccu_serdes_dtm", "1'b0");
167
168// &CONNECT ("clkgen_tds.ccu_div_ph", "gl_tds_io_out");
169// &CONNECT ("clkgen_tds.gclk", "cmp_gclk_c0_tds");
170// &CONNECT ("clkgen_tds.scan_en", "tcu_scan_en");
171// &CONNECT ("clkgen_tds.l1clk", "l1clk");
172// &CONNECT ("clkgen_tds.iol2clk", "iol2clk");
173// &CONNECT ("clkgen_tds.por_", "niu_reset_l");
174// &CONNECT ("clkgen_tds.scan_out", "ioclk_scan_out");
175// &CONNECT ("clkgen_tds.pce_ov", "tds_pce_ov");
176// &CONNECT ("clkgen_tds.tcu_atpg_mode", "tcu_atpg_mode");
177
178// # New pins I6.1
179// &CONNECT ("clkgen2x_tds.array_wr_inhibit", "");
180// &CONNECT ("clkgen2x_tds.tcu_atpg_mode", "tcu_atpg_mode");
181// &CONNECT ("clkgen2x_tds.tcu_wr_inhibit", "1'b0");
182
183// # Note: the ccu_*sync_en connections will be removed in I5.3
184// &CONNECT ("clkgen2x_tds.ccu_cmp_slow_sync_en", "1'b0");
185// &CONNECT ("clkgen2x_tds.ccu_slow_cmp_sync_en", "1'b0");
186
187// &CONNECT ("clkgen2x_tds.ccu_div_ph", "gl_tds_io2x_out");
188// &CONNECT ("clkgen2x_tds.rst_por_", "rst_por_");
189// &CONNECT ("clkgen2x_tds.gclk", "cmp_gclk_c0_tds");
190// &CONNECT ("clkgen2x_tds.l2clk", "io2xl2clk");
191
192// &CONNECT ("clkgen2x_tds.tcu_aclk", "aclk");
193// &CONNECT ("clkgen2x_tds.tcu_bclk", "bclk");
194// &CONNECT ("clkgen2x_tds.tcu_pce_ov", "tds_pce_ov");
195// &CONNECT ("clkgen2x_tds.scan_en", "tcu_scan_en");
196// &CONNECT ("clkgen2x_tds.scan_in", "ioclk_scan_out");
197// &CONNECT ("clkgen2x_tds.scan_out", "io2xclk_scan_out");
198
199// &CONNECT ("clkgen_tds.aclk", "aclk");
200// &CONNECT ("clkgen_tds.bclk", "bclk");
201// &CONNECT ("niu_tdmc.tcu_aclk", "aclk");
202// &CONNECT ("niu_tdmc.tcu_bclk", "bclk");
203// &CONNECT ("niu_smx.tcu_aclk", "aclk");
204// &CONNECT ("niu_smx.tcu_bclk", "bclk");
205// &CONNECT ("clkgen_tds.tcu_clk_stop", "tcu_tds_io_clk_stop");
206// &CONNECT ("clkgen2x_tds.tcu_clk_stop", "tcu_tds_io_clk_stop");
207
208// &CONNECT ("clkgen_tds.tcu_wr_inhibit", "tcu_wr_inhibit");
209// &CONNECT ("clkgen_tds.array_wr_inhibit", "tds_array_wr_inhibit");
210// &CONNECT ("clkgen_tds.wmr_protect", "");
211// &CONNECT ("clkgen_tds.wmr_", "");
212// &CONNECT ("clkgen_tds.cmp_slow_sync_en", "");
213// &CONNECT ("clkgen_tds.slow_cmp_sync_en", "");
214// &CONNECT ("clkgen_tds.aclk_wmr", "");
215// &CONNECT ("clkgen2x_tds.aclk_wmr", "");
216// &CONNECT ("clkgen2x_tds.aclk", "");
217// &CONNECT ("clkgen2x_tds.bclk", "");
218// &CONNECT ("clkgen2x_tds.por_", "");
219// &CONNECT ("clkgen2x_tds.pce_ov", "");
220// &CONNECT ("clkgen2x_tds.wmr_protect", "");
221// &CONNECT ("clkgen2x_tds.wmr_", "");
222// &CONNECT ("clkgen2x_tds.cmp_slow_sync_en", "");
223// &CONNECT ("clkgen2x_tds.slow_cmp_sync_en", "");
224
225// &CONNECT ("clkgen_tds.rst_wmr_protect", "1'b0");
226// &CONNECT ("clkgen_tds.rst_wmr_", "1'b1");
227// &CONNECT ("clkgen_tds.cluster_div_en", "1'b1");
228
229// &CONNECT ("clkgen2x_tds.rst_wmr_protect", "1'b0");
230// &CONNECT ("clkgen2x_tds.rst_wmr_", "1'b1");
231// &CONNECT ("clkgen2x_tds.cluster_div_en", "1'b1");
232// &CONNECT ("clkgen2x_tds.ccu_serdes_dtm", "1'b0");
233// &CONNECT ("clkgen2x_tds.clk_ext", "1'b0");
234
235// # TDMC EFUSE connections
236// &CONNECT ("niu_tdmc.hdr_sram_rvalue_tdmc", " hdr_sram_rvalue_tdmc[6:0]");
237// &CONNECT ("niu_tdmc.hdr_sram_rid_tdmc", "hdr_sram_rid_tdmc[1:0]");
238// &CONNECT ("niu_tdmc.hdr_sram_wr_en_tdmc", "hdr_sram_wr_en_tdmc");
239// &CONNECT ("niu_tdmc.hdr_sram_red_clr_tdmc", "hdr_sram_red_clr_tdmc");
240// &CONNECT ("niu_tdmc.sram_hdr_read_data_tdmc", "sram_hdr_read_data_tdmc[6:0]");
241// &CONNECT ("tdmc_sram_header.hdr_sram_rvalue", "{unconnected_1[10:7], hdr_sram_rvalue_tdmc[6:0]}");
242// &CONNECT ("tdmc_sram_header.hdr_sram_rid", "{unconnected_2[10:2], hdr_sram_rid_tdmc[1:0]}");
243// &CONNECT ("tdmc_sram_header.hdr_sram_wr_en", "hdr_sram_wr_en_tdmc");
244// &CONNECT ("tdmc_sram_header.hdr_sram_red_clr", "hdr_sram_red_clr_tdmc");
245// &CONNECT ("tdmc_sram_header.sram_hdr_read_data", "{4'b0, sram_hdr_read_data_tdmc[6:0]}");
246// &CONNECT ("tdmc_sram_header.l2clk", "l1clk");
247// &CONNECT ("tdmc_sram_header.tcu_clk_stop", "tcu_tds_io_clk_stop");
248
249// &CONNECT ("tdmc_sram_header.reset_l", "niu_reset_l");
250// &CONNECT ("tdmc_sram_header.efu_hdr_write_data", "efu_niu_ram_data");
251// &CONNECT ("tdmc_sram_header.efu_hdr_xfer_en", "efu_niu_ram_xfer_en");
252// &CONNECT ("tdmc_sram_header.efu_hdr_clr", "efu_niu_ram_clr");
253// &CONNECT ("tdmc_sram_header.hdr_efu_read_data", "niu_efu_ram_data");
254// &CONNECT ("tdmc_sram_header.hdr_efu_xfer_en", "niu_efu_ram_xfer_en");
255// &CONNECT ("tdmc_sram_header.tcu_aclk", "aclk");
256// &CONNECT ("tdmc_sram_header.tcu_bclk", "bclk");
257// &CONNECT ("tdmc_sram_header.tcu_pce_ov", "tds_pce_ov");
258// &CONNECT ("tdmc_sram_header.scan_in", "io2xclk_scan_out");
259// &CONNECT ("tdmc_sram_header.scan_out", "");
260// &CONNECT ("niu_tdmc.niu_clk", "l1clk");
261// &CONNECT ("niu_tdmc.iol2clk", "iol2clk");
262// # &CONNECT ("niu_tdmc.tcu_clk_stop", "tcu_tds_io_clk_stop");
263// &CONNECT ("niu_smx.niu_clk", "l1clk");
264// &CONNECT ("niu_smx.iol2clk", "iol2clk");
265// &CONNECT ("niu_meta_arb.niu_clk", "l1clk");
266// &CONNECT ("niu_meta_arb.dmc_meta1_req_transID", "dmc_meta1_req_trans_id[5:0]");
267// &CONNECT ("niu_meta_arb.meta_dmc_resp_transID","meta_dmc_resp_trans_id[5:0]");
268// &CONNECT ("niu_smx.dmc_meta1_req_transID", "dmc_meta1_req_trans_id[5:0]");
269// &CONNECT ("niu_smx.meta_dmc_resp_transID","meta_dmc_resp_trans_id[5:0]");
270
271// ####################################
272// # Split port connections:
273// ####################################
274
275// &CONNECT ("niu_smx.meta_dmc_data", "x_meta1_rdmc_rbr_resp_data[127:0]");
276// &CONNECT ("niu_smx.meta_dmc_resp_byteenable", "x_meta1_rdmc_rbr_resp_byteenable[15:0]");
277// &CONNECT ("niu_smx.meta_dmc_resp_cmd", "x_meta1_rdmc_rbr_resp_cmd[7:0]");
278// &CONNECT ("niu_smx.meta_dmc_resp_cmd_status", "x_meta1_rdmc_rbr_resp_cmd_status[3:0]");
279// &CONNECT ("niu_smx.meta_dmc_resp_dma_num", "x_meta1_rdmc_rbr_resp_dma_num[4:0]");
280// &CONNECT ("niu_smx.meta_dmc_resp_ready", "x_meta1_rdmc_rbr_resp_ready");
281
282// &CONNECT ("niu_tdmc.meta_dmc_data", "x_meta1_rdmc_rbr_resp_data[127:0]");
283// &CONNECT ("niu_tdmc.meta_dmc_resp_byteenable", "x_meta1_rdmc_rbr_resp_byteenable[15:0]");
284// &CONNECT ("niu_tdmc.meta_dmc_resp_cmd", "x_meta1_rdmc_rbr_resp_cmd[7:0]");
285// &CONNECT ("niu_tdmc.meta_dmc_resp_cmd_status", "x_meta1_rdmc_rbr_resp_cmd_status[3:0]");
286// &CONNECT ("niu_tdmc.meta_dmc_resp_dma_num", "x_meta1_rdmc_rbr_resp_dma_num[4:0]");
287// &CONNECT ("niu_tdmc.meta_dmc_resp_ready", "x_meta1_rdmc_rbr_resp_ready");
288
289// &CONNECT ("dmo_regs.niu_clk", "l1clk");
290// &CONNECT ("dmo_regs.dmo_out", "tds_tcu_dmo_dout[39:0]");
291// &CONNECT ("dmo_regs.dmo_in", "tds_tcu_dmo_data_out[39:0]");
292// &CONNECT ("niu_tdmc.l2clk_2x", "io2xl2clk");
293// &CONNECT ("niu_tdmc.tds_tcu_dmo_data_out", "tds_tcu_dmo_data_out[39:0]");
294
295// &CONNECT ("niu_smx.meta_dmc_resp_client_tdmc", "meta_dmc_resp_client_tdmc");
296// &CONNECT ("niu_smx.meta_dmc_resp_complete_tdmc", "meta_dmc_resp_complete_tdmc");
297// &CONNECT ("niu_smx.meta_dmc_resp_transfer_cmpl_tdmc", "meta_dmc_resp_transfer_cmpl_tdmc");
298// &CONNECT ("niu_smx.meta_dmc_data_valid_tdmc", "meta_dmc_data_valid_tdmc");
299// &CONNECT ("niu_smx.meta_dmc_ack_client_tdmc", "meta_dmc_ack_client_tdmc");
300// &CONNECT ("niu_tdmc.meta_dmc_resp_client", "meta_dmc_resp_client_tdmc");
301// &CONNECT ("niu_tdmc.meta_dmc_resp_complete", "meta_dmc_resp_complete_tdmc");
302// &CONNECT ("niu_tdmc.meta_dmc_resp_transfer_cmpl", "meta_dmc_resp_transfer_cmpl_tdmc");
303// &CONNECT ("niu_tdmc.meta_dmc_data_valid", "meta_dmc_data_valid_tdmc");
304// &CONNECT ("niu_tdmc.meta_dmc_ack_client", "meta_dmc_ack_client_tdmc");
305// &CONNECT ("niu_tdmc.dmc_meta_resp_accept", "tdmc_meta_resp_accept");
306// &CONNECT ("niu_tdmc.dmc_meta_ack_accept", "tdmc_meta_ack_accept");
307// &CONNECT ("niu_tdmc.meta_dmc_ack_complete", "meta_dmc_ack_complete");
308// &CONNECT ("niu_tdmc.txc_dmc_p0_dma_pkt_size_err","txc_dmc_p0_dma_pkt_size_err[15:0]");
309// &CONNECT ("niu_tdmc.txc_dmc_p1_dma_pkt_size_err","txc_dmc_p1_dma_pkt_size_err[15:0]");
310// #&CONNECT ("niu_tdmc.txc_dmc_dma_nack_pkt_rd","txc_dmc_dma_nack_pkt_rd[23:0]");
311// # - &CONNECT ("niu_tdmc.txc_dmc_dma_pkt_size_err","txc_dmc_dma_pkt_size_err[15:0]");
312// &CONNECT ("niu_tdmc.txc_dmc_dma_nack_pkt_rd","txc_dmc_dma_nack_pkt_rd[15:0]");
313// &CONNECT ("niu_tdmc.niu_reset_l","niu_reset_l");
314// &CONNECT ("niu_smx.niu_reset_l","niu_reset_l");
315// &CONNECT ("niu_meta_arb.niu_reset_l","niu_reset_l");
316// # &DECLARE ("wire", "tds_mbist_scan_in");
317// # &DECLARE ("wire", "tds_mbist_scan_out");
318// # &DECLARE ("wire", "tdmc2smx_mbist_scan");
319// &CONNECT ("niu_tdmc.tds_tdmc_mbist_scan_in", "tds_mbist_scan_in");
320// &CONNECT ("niu_tdmc.tds_tdmc_mbist_scan_out", "tds_smx_mbist_scan_in");
321// &CONNECT ("niu_smx.tds_smx_mbist_scan_in", "tds_smx_mbist_scan_in");
322// &CONNECT ("niu_smx.tds_smx_mbist_scan_out", "tds_mbist_scan_out");
323// &CONNECT ("niu_tdmc.tcu_array_wr_inhibit", "tds_array_wr_inhibit");
324// &CONNECT ("niu_smx.tcu_array_wr_inhibit", "tds_array_wr_inhibit");
325
326// VPERL: PERL_END
327// VPERL: GENERATED_BEG
328
329module tds (
330 cluster_arst_l,
331 cmp_gclk_c0_tds,
332 dbg1_niu_resume,
333 dbg1_niu_stall,
334 efu_niu_ram_clr,
335 efu_niu_ram_data,
336 efu_niu_ram_xfer_en,
337 gl_tds_io2x_out,
338 gl_tds_io_out,
339 ncu_niu_ctag_cei,
340 ncu_niu_ctag_uei,
341 ncu_niu_d_pei,
342 pio_arb_ctrl,
343 pio_arb_debug_vector,
344 pio_arb_dirtid_clr,
345 pio_arb_dirtid_enable,
346 pio_arb_np_threshold,
347 pio_arb_rd_threshold,
348 pio_clients_addr,
349 pio_clients_rd,
350 pio_clients_wdata,
351 pio_smx_cfg_data,
352 pio_smx_clear_intr,
353 pio_smx_ctrl,
354 pio_smx_debug_vector,
355 pio_tdmc_sel,
356 rbr_arb1_req,
357 rbr_arb1_req_address,
358 rbr_arb1_req_cmd,
359 rbr_arb1_req_dma_num,
360 rbr_arb1_req_func_num,
361 rbr_arb1_req_length,
362 rbr_arb1_req_port_num,
363 rcr_arb0_data,
364 rcr_arb0_data_valid,
365 rcr_arb0_req,
366 rcr_arb0_req_address,
367 rcr_arb0_req_byteenable,
368 rcr_arb0_req_cmd,
369 rcr_arb0_req_dma_num,
370 rcr_arb0_req_func_num,
371 rcr_arb0_req_length,
372 rcr_arb0_req_port_num,
373 rcr_arb0_status,
374 rcr_arb0_transfer_complete,
375 rdc_arb0_data,
376 rdc_arb0_data_valid,
377 rdc_arb0_req,
378 rdc_arb0_req_address,
379 rdc_arb0_req_byteenable,
380 rdc_arb0_req_cmd,
381 rdc_arb0_req_dma_num,
382 rdc_arb0_req_func_num,
383 rdc_arb0_req_length,
384 rdc_arb0_req_port_num,
385 rdc_arb0_status,
386 rdc_arb0_transfer_complete,
387 rdmc_meta_ack_accept,
388 rdmc_meta_resp_accept,
389 rst_por_,
390 scan_in,
391 sii_niu_bqdq,
392 sii_niu_oqdq,
393 sio_niu_data,
394 sio_niu_datareq,
395 sio_niu_hdr_vld,
396 sio_niu_parity,
397 tcu_aclk,
398 tcu_atpg_mode,
399 tcu_bclk,
400 tcu_div_bypass,
401 tcu_mbist_bisi_en,
402 tcu_mbist_user_mode,
403 tcu_pce_ov,
404 tcu_scan_en,
405 tcu_se_scancollar_in,
406 tcu_se_scancollar_out,
407 tcu_tds_io_clk_stop,
408 tcu_tds_smx_mbist_start,
409 tcu_tds_tdmc_mbist_start,
410 tcu_wr_inhibit,
411 tds_mbist_scan_in,
412 txc_arb1_req,
413 txc_arb1_req_address,
414 txc_arb1_req_cmd,
415 txc_arb1_req_dma_num,
416 txc_arb1_req_func_num,
417 txc_arb1_req_length,
418 txc_arb1_req_port_num,
419 txc_dmc_dma0_getnxtdesc,
420 txc_dmc_dma0_inc_head,
421 txc_dmc_dma0_inc_pkt_cnt,
422 txc_dmc_dma0_mark_bit,
423 txc_dmc_dma0_reset_done,
424 txc_dmc_dma10_getnxtdesc,
425 txc_dmc_dma10_inc_head,
426 txc_dmc_dma10_inc_pkt_cnt,
427 txc_dmc_dma10_mark_bit,
428 txc_dmc_dma10_reset_done,
429 txc_dmc_dma11_getnxtdesc,
430 txc_dmc_dma11_inc_head,
431 txc_dmc_dma11_inc_pkt_cnt,
432 txc_dmc_dma11_mark_bit,
433 txc_dmc_dma11_reset_done,
434 txc_dmc_dma12_getnxtdesc,
435 txc_dmc_dma12_inc_head,
436 txc_dmc_dma12_inc_pkt_cnt,
437 txc_dmc_dma12_mark_bit,
438 txc_dmc_dma12_reset_done,
439 txc_dmc_dma13_getnxtdesc,
440 txc_dmc_dma13_inc_head,
441 txc_dmc_dma13_inc_pkt_cnt,
442 txc_dmc_dma13_mark_bit,
443 txc_dmc_dma13_reset_done,
444 txc_dmc_dma14_getnxtdesc,
445 txc_dmc_dma14_inc_head,
446 txc_dmc_dma14_inc_pkt_cnt,
447 txc_dmc_dma14_mark_bit,
448 txc_dmc_dma14_reset_done,
449 txc_dmc_dma15_getnxtdesc,
450 txc_dmc_dma15_inc_head,
451 txc_dmc_dma15_inc_pkt_cnt,
452 txc_dmc_dma15_mark_bit,
453 txc_dmc_dma15_reset_done,
454 txc_dmc_dma1_getnxtdesc,
455 txc_dmc_dma1_inc_head,
456 txc_dmc_dma1_inc_pkt_cnt,
457 txc_dmc_dma1_mark_bit,
458 txc_dmc_dma1_reset_done,
459 txc_dmc_dma2_getnxtdesc,
460 txc_dmc_dma2_inc_head,
461 txc_dmc_dma2_inc_pkt_cnt,
462 txc_dmc_dma2_mark_bit,
463 txc_dmc_dma2_reset_done,
464 txc_dmc_dma3_getnxtdesc,
465 txc_dmc_dma3_inc_head,
466 txc_dmc_dma3_inc_pkt_cnt,
467 txc_dmc_dma3_mark_bit,
468 txc_dmc_dma3_reset_done,
469 txc_dmc_dma4_getnxtdesc,
470 txc_dmc_dma4_inc_head,
471 txc_dmc_dma4_inc_pkt_cnt,
472 txc_dmc_dma4_mark_bit,
473 txc_dmc_dma4_reset_done,
474 txc_dmc_dma5_getnxtdesc,
475 txc_dmc_dma5_inc_head,
476 txc_dmc_dma5_inc_pkt_cnt,
477 txc_dmc_dma5_mark_bit,
478 txc_dmc_dma5_reset_done,
479 txc_dmc_dma6_getnxtdesc,
480 txc_dmc_dma6_inc_head,
481 txc_dmc_dma6_inc_pkt_cnt,
482 txc_dmc_dma6_mark_bit,
483 txc_dmc_dma6_reset_done,
484 txc_dmc_dma7_getnxtdesc,
485 txc_dmc_dma7_inc_head,
486 txc_dmc_dma7_inc_pkt_cnt,
487 txc_dmc_dma7_mark_bit,
488 txc_dmc_dma7_reset_done,
489 txc_dmc_dma8_getnxtdesc,
490 txc_dmc_dma8_inc_head,
491 txc_dmc_dma8_inc_pkt_cnt,
492 txc_dmc_dma8_mark_bit,
493 txc_dmc_dma8_reset_done,
494 txc_dmc_dma9_getnxtdesc,
495 txc_dmc_dma9_inc_head,
496 txc_dmc_dma9_inc_pkt_cnt,
497 txc_dmc_dma9_mark_bit,
498 txc_dmc_dma9_reset_done,
499 txc_dmc_dma_nack_pkt_rd,
500 txc_dmc_nack_pkt_rd,
501 txc_dmc_nack_pkt_rd_addr,
502 txc_dmc_p0_dma_pkt_size_err,
503 txc_dmc_p0_pkt_size_err,
504 txc_dmc_p0_pkt_size_err_addr,
505 txc_dmc_p1_dma_pkt_size_err,
506 txc_dmc_p1_pkt_size_err,
507 txc_dmc_p1_pkt_size_err_addr,
508 txc_meta_resp_accept,
509 arb0_rcr_data_req,
510 arb0_rcr_req_accept,
511 arb0_rdc_data_req,
512 arb0_rdc_req_accept,
513 arb1_rbr_req_accept,
514 arb1_rbr_req_errors,
515 arb1_txc_req_accept,
516 arb_pio_all_npwdirty,
517 arb_pio_all_rddirty,
518 arb_pio_dirtid_npwstatus,
519 arb_pio_dirtid_rdstatus,
520 dmc_meta1_req_trans_id,
521 dmc_txc_dma0_active,
522 dmc_txc_dma0_cacheready,
523 dmc_txc_dma0_descriptor,
524 dmc_txc_dma0_eoflist,
525 dmc_txc_dma0_error,
526 dmc_txc_dma0_func_num,
527 dmc_txc_dma0_gotnxtdesc,
528 dmc_txc_dma0_page_handle,
529 dmc_txc_dma0_partial,
530 dmc_txc_dma0_reset_scheduled,
531 dmc_txc_dma10_active,
532 dmc_txc_dma10_cacheready,
533 dmc_txc_dma10_descriptor,
534 dmc_txc_dma10_eoflist,
535 dmc_txc_dma10_error,
536 dmc_txc_dma10_func_num,
537 dmc_txc_dma10_gotnxtdesc,
538 dmc_txc_dma10_page_handle,
539 dmc_txc_dma10_partial,
540 dmc_txc_dma10_reset_scheduled,
541 dmc_txc_dma11_active,
542 dmc_txc_dma11_cacheready,
543 dmc_txc_dma11_descriptor,
544 dmc_txc_dma11_eoflist,
545 dmc_txc_dma11_error,
546 dmc_txc_dma11_func_num,
547 dmc_txc_dma11_gotnxtdesc,
548 dmc_txc_dma11_page_handle,
549 dmc_txc_dma11_partial,
550 dmc_txc_dma11_reset_scheduled,
551 dmc_txc_dma12_active,
552 dmc_txc_dma12_cacheready,
553 dmc_txc_dma12_descriptor,
554 dmc_txc_dma12_eoflist,
555 dmc_txc_dma12_error,
556 dmc_txc_dma12_func_num,
557 dmc_txc_dma12_gotnxtdesc,
558 dmc_txc_dma12_page_handle,
559 dmc_txc_dma12_partial,
560 dmc_txc_dma12_reset_scheduled,
561 dmc_txc_dma13_active,
562 dmc_txc_dma13_cacheready,
563 dmc_txc_dma13_descriptor,
564 dmc_txc_dma13_eoflist,
565 dmc_txc_dma13_error,
566 dmc_txc_dma13_func_num,
567 dmc_txc_dma13_gotnxtdesc,
568 dmc_txc_dma13_page_handle,
569 dmc_txc_dma13_partial,
570 dmc_txc_dma13_reset_scheduled,
571 dmc_txc_dma14_active,
572 dmc_txc_dma14_cacheready,
573 dmc_txc_dma14_descriptor,
574 dmc_txc_dma14_eoflist,
575 dmc_txc_dma14_error,
576 dmc_txc_dma14_func_num,
577 dmc_txc_dma14_gotnxtdesc,
578 dmc_txc_dma14_page_handle,
579 dmc_txc_dma14_partial,
580 dmc_txc_dma14_reset_scheduled,
581 dmc_txc_dma15_active,
582 dmc_txc_dma15_cacheready,
583 dmc_txc_dma15_descriptor,
584 dmc_txc_dma15_eoflist,
585 dmc_txc_dma15_error,
586 dmc_txc_dma15_func_num,
587 dmc_txc_dma15_gotnxtdesc,
588 dmc_txc_dma15_page_handle,
589 dmc_txc_dma15_partial,
590 dmc_txc_dma15_reset_scheduled,
591 dmc_txc_dma1_active,
592 dmc_txc_dma1_cacheready,
593 dmc_txc_dma1_descriptor,
594 dmc_txc_dma1_eoflist,
595 dmc_txc_dma1_error,
596 dmc_txc_dma1_func_num,
597 dmc_txc_dma1_gotnxtdesc,
598 dmc_txc_dma1_page_handle,
599 dmc_txc_dma1_partial,
600 dmc_txc_dma1_reset_scheduled,
601 dmc_txc_dma2_active,
602 dmc_txc_dma2_cacheready,
603 dmc_txc_dma2_descriptor,
604 dmc_txc_dma2_eoflist,
605 dmc_txc_dma2_error,
606 dmc_txc_dma2_func_num,
607 dmc_txc_dma2_gotnxtdesc,
608 dmc_txc_dma2_page_handle,
609 dmc_txc_dma2_partial,
610 dmc_txc_dma2_reset_scheduled,
611 dmc_txc_dma3_active,
612 dmc_txc_dma3_cacheready,
613 dmc_txc_dma3_descriptor,
614 dmc_txc_dma3_eoflist,
615 dmc_txc_dma3_error,
616 dmc_txc_dma3_func_num,
617 dmc_txc_dma3_gotnxtdesc,
618 dmc_txc_dma3_page_handle,
619 dmc_txc_dma3_partial,
620 dmc_txc_dma3_reset_scheduled,
621 dmc_txc_dma4_active,
622 dmc_txc_dma4_cacheready,
623 dmc_txc_dma4_descriptor,
624 dmc_txc_dma4_eoflist,
625 dmc_txc_dma4_error,
626 dmc_txc_dma4_func_num,
627 dmc_txc_dma4_gotnxtdesc,
628 dmc_txc_dma4_page_handle,
629 dmc_txc_dma4_partial,
630 dmc_txc_dma4_reset_scheduled,
631 dmc_txc_dma5_active,
632 dmc_txc_dma5_cacheready,
633 dmc_txc_dma5_descriptor,
634 dmc_txc_dma5_eoflist,
635 dmc_txc_dma5_error,
636 dmc_txc_dma5_func_num,
637 dmc_txc_dma5_gotnxtdesc,
638 dmc_txc_dma5_page_handle,
639 dmc_txc_dma5_partial,
640 dmc_txc_dma5_reset_scheduled,
641 dmc_txc_dma6_active,
642 dmc_txc_dma6_cacheready,
643 dmc_txc_dma6_descriptor,
644 dmc_txc_dma6_eoflist,
645 dmc_txc_dma6_error,
646 dmc_txc_dma6_func_num,
647 dmc_txc_dma6_gotnxtdesc,
648 dmc_txc_dma6_page_handle,
649 dmc_txc_dma6_partial,
650 dmc_txc_dma6_reset_scheduled,
651 dmc_txc_dma7_active,
652 dmc_txc_dma7_cacheready,
653 dmc_txc_dma7_descriptor,
654 dmc_txc_dma7_eoflist,
655 dmc_txc_dma7_error,
656 dmc_txc_dma7_func_num,
657 dmc_txc_dma7_gotnxtdesc,
658 dmc_txc_dma7_page_handle,
659 dmc_txc_dma7_partial,
660 dmc_txc_dma7_reset_scheduled,
661 dmc_txc_dma8_active,
662 dmc_txc_dma8_cacheready,
663 dmc_txc_dma8_descriptor,
664 dmc_txc_dma8_eoflist,
665 dmc_txc_dma8_error,
666 dmc_txc_dma8_func_num,
667 dmc_txc_dma8_gotnxtdesc,
668 dmc_txc_dma8_page_handle,
669 dmc_txc_dma8_partial,
670 dmc_txc_dma8_reset_scheduled,
671 dmc_txc_dma9_active,
672 dmc_txc_dma9_cacheready,
673 dmc_txc_dma9_descriptor,
674 dmc_txc_dma9_eoflist,
675 dmc_txc_dma9_error,
676 dmc_txc_dma9_func_num,
677 dmc_txc_dma9_gotnxtdesc,
678 dmc_txc_dma9_page_handle,
679 dmc_txc_dma9_partial,
680 dmc_txc_dma9_reset_scheduled,
681 dmc_txc_tx_addr_md,
682 meta1_rdmc_rbr_resp_byteenable,
683 meta1_rdmc_rbr_resp_cmd,
684 meta1_rdmc_rbr_resp_cmd_status,
685 meta1_rdmc_rbr_resp_data,
686 meta1_rdmc_rbr_resp_dma_num,
687 meta1_rdmc_rbr_resp_ready,
688 meta_arb_debug_port,
689 meta_dmc_ack_client_rdmc,
690 meta_dmc_ack_cmd,
691 meta_dmc_ack_cmd_status,
692 meta_dmc_ack_dma_num,
693 meta_dmc_ack_ready,
694 meta_dmc_data,
695 meta_dmc_data_status,
696 meta_dmc_data_valid_rdmc,
697 meta_dmc_data_valid_txc,
698 meta_dmc_resp_address,
699 meta_dmc_resp_byteenable,
700 meta_dmc_resp_client_rdmc,
701 meta_dmc_resp_client_txc,
702 meta_dmc_resp_cmd,
703 meta_dmc_resp_cmd_status,
704 meta_dmc_resp_complete_rdmc,
705 meta_dmc_resp_complete_txc,
706 meta_dmc_resp_dma_num,
707 meta_dmc_resp_length,
708 meta_dmc_resp_port_num,
709 meta_dmc_resp_ready,
710 meta_dmc_resp_trans_id,
711 meta_dmc_resp_transfer_cmpl_rdmc,
712 meta_dmc_resp_transfer_cmpl_txc,
713 niu_dbg1_stall_ack,
714 niu_efu_ram_data,
715 niu_efu_ram_xfer_en,
716 niu_ncu_ctag_ce,
717 niu_ncu_ctag_ue,
718 niu_ncu_d_pe,
719 niu_sii_data,
720 niu_sii_datareq,
721 niu_sii_hdr_vld,
722 niu_sii_parity,
723 niu_sii_reqbypass,
724 niu_sio_dq,
725 scan_out,
726 smx_debug_port,
727 smx_pio_intr,
728 smx_pio_status,
729 tdmc_debug_port,
730 tdmc_pio_ack,
731 tdmc_pio_err,
732 tdmc_pio_intr,
733 tdmc_pio_rdata,
734 tds_mbist_scan_out,
735 tds_smx_tcu_mbist_done,
736 tds_smx_tcu_mbist_fail,
737 tds_tcu_dmo_dout,
738 tds_tdmc_tcu_mbist_done,
739 tds_tdmc_tcu_mbist_fail
740 );
741
742input cluster_arst_l;
743input cmp_gclk_c0_tds;
744input dbg1_niu_resume;
745input dbg1_niu_stall;
746input efu_niu_ram_clr;
747input efu_niu_ram_data;
748input efu_niu_ram_xfer_en;
749input gl_tds_io2x_out;
750input gl_tds_io_out;
751input ncu_niu_ctag_cei;
752input ncu_niu_ctag_uei;
753input ncu_niu_d_pei;
754input [31:0] pio_arb_ctrl;
755input [31:0] pio_arb_debug_vector;
756input pio_arb_dirtid_clr; // Clear all Dirty TID Entries
757input pio_arb_dirtid_enable; // Enable Dirty TID logic
758input [5:0] pio_arb_np_threshold; // np write threshold
759input [5:0] pio_arb_rd_threshold; // read threshold
760input [19:0] pio_clients_addr; // pio address
761input pio_clients_rd; // pio read
762input [63:0] pio_clients_wdata; // pio write data
763input [31:0] pio_smx_cfg_data; // static
764input pio_smx_clear_intr; // a pulse
765input [31:0] pio_smx_ctrl;
766input [31:0] pio_smx_debug_vector;
767input pio_tdmc_sel; // pio DMC select
768input rbr_arb1_req; // Req Command Request
769input [63:0] rbr_arb1_req_address; // Memory Address
770input [7:0] rbr_arb1_req_cmd; // Command Request
771input [4:0] rbr_arb1_req_dma_num; // Channel Number
772input [1:0] rbr_arb1_req_func_num; // Channel Number
773input [13:0] rbr_arb1_req_length; // Packet Length
774input [1:0] rbr_arb1_req_port_num; // Port Number
775input [127:0] rcr_arb0_data; // Transfer Data
776input rcr_arb0_data_valid; // Transfer Data Ack
777input rcr_arb0_req; // Req Command Request
778input [63:0] rcr_arb0_req_address; // Memory Address
779input [15:0] rcr_arb0_req_byteenable; // First/Last BE
780input [7:0] rcr_arb0_req_cmd; // Command Request
781input [4:0] rcr_arb0_req_dma_num; // Channel Number
782input [1:0] rcr_arb0_req_func_num; // Channel Number
783input [13:0] rcr_arb0_req_length; // Packet Length
784input [1:0] rcr_arb0_req_port_num; // Port Number
785input [3:0] rcr_arb0_status; // Transfer Data Status
786input rcr_arb0_transfer_complete; // Transfer Data Complete
787input [127:0] rdc_arb0_data; // Transfer Data
788input rdc_arb0_data_valid; // Transfer Data Ack
789input rdc_arb0_req; // Req Command Request
790input [63:0] rdc_arb0_req_address; // Memory Address
791input [15:0] rdc_arb0_req_byteenable; // First/Last BE
792input [7:0] rdc_arb0_req_cmd; // Command Request
793input [4:0] rdc_arb0_req_dma_num; // Channel Number
794input [1:0] rdc_arb0_req_func_num; // Channel Number
795input [13:0] rdc_arb0_req_length; // Packet Length
796input [1:0] rdc_arb0_req_port_num; // Port Number
797input [3:0] rdc_arb0_status; // Transfer Data Status
798input rdc_arb0_transfer_complete; // Transfer Data Complete
799input rdmc_meta_ack_accept; // bitwise client accept
800input rdmc_meta_resp_accept; // Valid TransID
801input rst_por_;
802input scan_in; // unused as of today - feb 10, 05
803input sii_niu_bqdq;
804input sii_niu_oqdq;
805input [127:0] sio_niu_data;
806input sio_niu_datareq;
807input sio_niu_hdr_vld;
808input [7:0] sio_niu_parity;
809input tcu_aclk;
810input tcu_atpg_mode;
811input tcu_bclk;
812input tcu_div_bypass; // bypasses clk divider to mux in ext clk
813input tcu_mbist_bisi_en;
814input tcu_mbist_user_mode;
815input tcu_pce_ov;
816input tcu_scan_en;
817input tcu_se_scancollar_in;
818input tcu_se_scancollar_out;
819input tcu_tds_io_clk_stop;
820input tcu_tds_smx_mbist_start;
821input tcu_tds_tdmc_mbist_start;
822input tcu_wr_inhibit;
823input tds_mbist_scan_in;
824input txc_arb1_req; // Req Command Request
825input [63:0] txc_arb1_req_address; // Memory Address
826input [7:0] txc_arb1_req_cmd; // Command Request
827input [4:0] txc_arb1_req_dma_num; // Channel Number
828input [1:0] txc_arb1_req_func_num; // Channel Number
829input [13:0] txc_arb1_req_length; // Packet Length
830input [1:0] txc_arb1_req_port_num; // Port Number
831input txc_dmc_dma0_getnxtdesc;
832input txc_dmc_dma0_inc_head;
833input txc_dmc_dma0_inc_pkt_cnt;
834input txc_dmc_dma0_mark_bit;
835input txc_dmc_dma0_reset_done;
836input txc_dmc_dma10_getnxtdesc;
837input txc_dmc_dma10_inc_head;
838input txc_dmc_dma10_inc_pkt_cnt;
839input txc_dmc_dma10_mark_bit;
840input txc_dmc_dma10_reset_done;
841input txc_dmc_dma11_getnxtdesc;
842input txc_dmc_dma11_inc_head;
843input txc_dmc_dma11_inc_pkt_cnt;
844input txc_dmc_dma11_mark_bit;
845input txc_dmc_dma11_reset_done;
846input txc_dmc_dma12_getnxtdesc;
847input txc_dmc_dma12_inc_head;
848input txc_dmc_dma12_inc_pkt_cnt;
849input txc_dmc_dma12_mark_bit;
850input txc_dmc_dma12_reset_done;
851input txc_dmc_dma13_getnxtdesc;
852input txc_dmc_dma13_inc_head;
853input txc_dmc_dma13_inc_pkt_cnt;
854input txc_dmc_dma13_mark_bit;
855input txc_dmc_dma13_reset_done;
856input txc_dmc_dma14_getnxtdesc;
857input txc_dmc_dma14_inc_head;
858input txc_dmc_dma14_inc_pkt_cnt;
859input txc_dmc_dma14_mark_bit;
860input txc_dmc_dma14_reset_done;
861input txc_dmc_dma15_getnxtdesc;
862input txc_dmc_dma15_inc_head;
863input txc_dmc_dma15_inc_pkt_cnt;
864input txc_dmc_dma15_mark_bit;
865input txc_dmc_dma15_reset_done;
866input txc_dmc_dma1_getnxtdesc;
867input txc_dmc_dma1_inc_head;
868input txc_dmc_dma1_inc_pkt_cnt;
869input txc_dmc_dma1_mark_bit;
870input txc_dmc_dma1_reset_done;
871input txc_dmc_dma2_getnxtdesc;
872input txc_dmc_dma2_inc_head;
873input txc_dmc_dma2_inc_pkt_cnt;
874input txc_dmc_dma2_mark_bit;
875input txc_dmc_dma2_reset_done;
876input txc_dmc_dma3_getnxtdesc;
877input txc_dmc_dma3_inc_head;
878input txc_dmc_dma3_inc_pkt_cnt;
879input txc_dmc_dma3_mark_bit;
880input txc_dmc_dma3_reset_done;
881input txc_dmc_dma4_getnxtdesc;
882input txc_dmc_dma4_inc_head;
883input txc_dmc_dma4_inc_pkt_cnt;
884input txc_dmc_dma4_mark_bit;
885input txc_dmc_dma4_reset_done;
886input txc_dmc_dma5_getnxtdesc;
887input txc_dmc_dma5_inc_head;
888input txc_dmc_dma5_inc_pkt_cnt;
889input txc_dmc_dma5_mark_bit;
890input txc_dmc_dma5_reset_done;
891input txc_dmc_dma6_getnxtdesc;
892input txc_dmc_dma6_inc_head;
893input txc_dmc_dma6_inc_pkt_cnt;
894input txc_dmc_dma6_mark_bit;
895input txc_dmc_dma6_reset_done;
896input txc_dmc_dma7_getnxtdesc;
897input txc_dmc_dma7_inc_head;
898input txc_dmc_dma7_inc_pkt_cnt;
899input txc_dmc_dma7_mark_bit;
900input txc_dmc_dma7_reset_done;
901input txc_dmc_dma8_getnxtdesc;
902input txc_dmc_dma8_inc_head;
903input txc_dmc_dma8_inc_pkt_cnt;
904input txc_dmc_dma8_mark_bit;
905input txc_dmc_dma8_reset_done;
906input txc_dmc_dma9_getnxtdesc;
907input txc_dmc_dma9_inc_head;
908input txc_dmc_dma9_inc_pkt_cnt;
909input txc_dmc_dma9_mark_bit;
910input txc_dmc_dma9_reset_done;
911input [15:0] txc_dmc_dma_nack_pkt_rd;
912input txc_dmc_nack_pkt_rd; // pulse to indicate error
913input [43:0] txc_dmc_nack_pkt_rd_addr;
914input [15:0] txc_dmc_p0_dma_pkt_size_err; // one-hot encoded
915input txc_dmc_p0_pkt_size_err; // pulse to indicate error
916input [43:0] txc_dmc_p0_pkt_size_err_addr;
917input [15:0] txc_dmc_p1_dma_pkt_size_err; // one-hot encoded
918input txc_dmc_p1_pkt_size_err; // pulse to indicate error
919input [43:0] txc_dmc_p1_pkt_size_err_addr;
920input txc_meta_resp_accept; // Valid TransID
921output arb0_rcr_data_req; // Memory line request
922output arb0_rcr_req_accept; // Response to REQ
923output arb0_rdc_data_req; // Memory line request
924output arb0_rdc_req_accept; // Response to REQ
925output arb1_rbr_req_accept; // Response to REQ
926output arb1_rbr_req_errors; // Error flag
927output arb1_txc_req_accept; // Response to REQ
928output arb_pio_all_npwdirty; // all dirty bin entries are dirty
929output arb_pio_all_rddirty; // all dirty bin entries are dirty
930output [5:0] arb_pio_dirtid_npwstatus; // count for number of np write TID's dirty
931output [5:0] arb_pio_dirtid_rdstatus; // count for number of read TID's dirty
932output [5:0] dmc_meta1_req_trans_id;
933output dmc_txc_dma0_active;
934output dmc_txc_dma0_cacheready;
935output [63:0] dmc_txc_dma0_descriptor;
936output dmc_txc_dma0_eoflist;
937output dmc_txc_dma0_error;
938output [1:0] dmc_txc_dma0_func_num;
939output dmc_txc_dma0_gotnxtdesc;
940output [19:0] dmc_txc_dma0_page_handle;
941output dmc_txc_dma0_partial;
942output dmc_txc_dma0_reset_scheduled;
943output dmc_txc_dma10_active;
944output dmc_txc_dma10_cacheready;
945output [63:0] dmc_txc_dma10_descriptor;
946output dmc_txc_dma10_eoflist;
947output dmc_txc_dma10_error;
948output [1:0] dmc_txc_dma10_func_num;
949output dmc_txc_dma10_gotnxtdesc;
950output [19:0] dmc_txc_dma10_page_handle;
951output dmc_txc_dma10_partial;
952output dmc_txc_dma10_reset_scheduled;
953output dmc_txc_dma11_active;
954output dmc_txc_dma11_cacheready;
955output [63:0] dmc_txc_dma11_descriptor;
956output dmc_txc_dma11_eoflist;
957output dmc_txc_dma11_error;
958output [1:0] dmc_txc_dma11_func_num;
959output dmc_txc_dma11_gotnxtdesc;
960output [19:0] dmc_txc_dma11_page_handle;
961output dmc_txc_dma11_partial;
962output dmc_txc_dma11_reset_scheduled;
963output dmc_txc_dma12_active;
964output dmc_txc_dma12_cacheready;
965output [63:0] dmc_txc_dma12_descriptor;
966output dmc_txc_dma12_eoflist;
967output dmc_txc_dma12_error;
968output [1:0] dmc_txc_dma12_func_num;
969output dmc_txc_dma12_gotnxtdesc;
970output [19:0] dmc_txc_dma12_page_handle;
971output dmc_txc_dma12_partial;
972output dmc_txc_dma12_reset_scheduled;
973output dmc_txc_dma13_active;
974output dmc_txc_dma13_cacheready;
975output [63:0] dmc_txc_dma13_descriptor;
976output dmc_txc_dma13_eoflist;
977output dmc_txc_dma13_error;
978output [1:0] dmc_txc_dma13_func_num;
979output dmc_txc_dma13_gotnxtdesc;
980output [19:0] dmc_txc_dma13_page_handle;
981output dmc_txc_dma13_partial;
982output dmc_txc_dma13_reset_scheduled;
983output dmc_txc_dma14_active;
984output dmc_txc_dma14_cacheready;
985output [63:0] dmc_txc_dma14_descriptor;
986output dmc_txc_dma14_eoflist;
987output dmc_txc_dma14_error;
988output [1:0] dmc_txc_dma14_func_num;
989output dmc_txc_dma14_gotnxtdesc;
990output [19:0] dmc_txc_dma14_page_handle;
991output dmc_txc_dma14_partial;
992output dmc_txc_dma14_reset_scheduled;
993output dmc_txc_dma15_active;
994output dmc_txc_dma15_cacheready;
995output [63:0] dmc_txc_dma15_descriptor;
996output dmc_txc_dma15_eoflist;
997output dmc_txc_dma15_error;
998output [1:0] dmc_txc_dma15_func_num;
999output dmc_txc_dma15_gotnxtdesc;
1000output [19:0] dmc_txc_dma15_page_handle;
1001output dmc_txc_dma15_partial;
1002output dmc_txc_dma15_reset_scheduled;
1003output dmc_txc_dma1_active;
1004output dmc_txc_dma1_cacheready;
1005output [63:0] dmc_txc_dma1_descriptor;
1006output dmc_txc_dma1_eoflist;
1007output dmc_txc_dma1_error;
1008output [1:0] dmc_txc_dma1_func_num;
1009output dmc_txc_dma1_gotnxtdesc;
1010output [19:0] dmc_txc_dma1_page_handle;
1011output dmc_txc_dma1_partial;
1012output dmc_txc_dma1_reset_scheduled;
1013output dmc_txc_dma2_active;
1014output dmc_txc_dma2_cacheready;
1015output [63:0] dmc_txc_dma2_descriptor;
1016output dmc_txc_dma2_eoflist;
1017output dmc_txc_dma2_error;
1018output [1:0] dmc_txc_dma2_func_num;
1019output dmc_txc_dma2_gotnxtdesc;
1020output [19:0] dmc_txc_dma2_page_handle;
1021output dmc_txc_dma2_partial;
1022output dmc_txc_dma2_reset_scheduled;
1023output dmc_txc_dma3_active;
1024output dmc_txc_dma3_cacheready;
1025output [63:0] dmc_txc_dma3_descriptor;
1026output dmc_txc_dma3_eoflist;
1027output dmc_txc_dma3_error;
1028output [1:0] dmc_txc_dma3_func_num;
1029output dmc_txc_dma3_gotnxtdesc;
1030output [19:0] dmc_txc_dma3_page_handle;
1031output dmc_txc_dma3_partial;
1032output dmc_txc_dma3_reset_scheduled;
1033output dmc_txc_dma4_active;
1034output dmc_txc_dma4_cacheready;
1035output [63:0] dmc_txc_dma4_descriptor;
1036output dmc_txc_dma4_eoflist;
1037output dmc_txc_dma4_error;
1038output [1:0] dmc_txc_dma4_func_num;
1039output dmc_txc_dma4_gotnxtdesc;
1040output [19:0] dmc_txc_dma4_page_handle;
1041output dmc_txc_dma4_partial;
1042output dmc_txc_dma4_reset_scheduled;
1043output dmc_txc_dma5_active;
1044output dmc_txc_dma5_cacheready;
1045output [63:0] dmc_txc_dma5_descriptor;
1046output dmc_txc_dma5_eoflist;
1047output dmc_txc_dma5_error;
1048output [1:0] dmc_txc_dma5_func_num;
1049output dmc_txc_dma5_gotnxtdesc;
1050output [19:0] dmc_txc_dma5_page_handle;
1051output dmc_txc_dma5_partial;
1052output dmc_txc_dma5_reset_scheduled;
1053output dmc_txc_dma6_active;
1054output dmc_txc_dma6_cacheready;
1055output [63:0] dmc_txc_dma6_descriptor;
1056output dmc_txc_dma6_eoflist;
1057output dmc_txc_dma6_error;
1058output [1:0] dmc_txc_dma6_func_num;
1059output dmc_txc_dma6_gotnxtdesc;
1060output [19:0] dmc_txc_dma6_page_handle;
1061output dmc_txc_dma6_partial;
1062output dmc_txc_dma6_reset_scheduled;
1063output dmc_txc_dma7_active;
1064output dmc_txc_dma7_cacheready;
1065output [63:0] dmc_txc_dma7_descriptor;
1066output dmc_txc_dma7_eoflist;
1067output dmc_txc_dma7_error;
1068output [1:0] dmc_txc_dma7_func_num;
1069output dmc_txc_dma7_gotnxtdesc;
1070output [19:0] dmc_txc_dma7_page_handle;
1071output dmc_txc_dma7_partial;
1072output dmc_txc_dma7_reset_scheduled;
1073output dmc_txc_dma8_active;
1074output dmc_txc_dma8_cacheready;
1075output [63:0] dmc_txc_dma8_descriptor;
1076output dmc_txc_dma8_eoflist;
1077output dmc_txc_dma8_error;
1078output [1:0] dmc_txc_dma8_func_num;
1079output dmc_txc_dma8_gotnxtdesc;
1080output [19:0] dmc_txc_dma8_page_handle;
1081output dmc_txc_dma8_partial;
1082output dmc_txc_dma8_reset_scheduled;
1083output dmc_txc_dma9_active;
1084output dmc_txc_dma9_cacheready;
1085output [63:0] dmc_txc_dma9_descriptor;
1086output dmc_txc_dma9_eoflist;
1087output dmc_txc_dma9_error;
1088output [1:0] dmc_txc_dma9_func_num;
1089output dmc_txc_dma9_gotnxtdesc;
1090output [19:0] dmc_txc_dma9_page_handle;
1091output dmc_txc_dma9_partial;
1092output dmc_txc_dma9_reset_scheduled;
1093output dmc_txc_tx_addr_md; // 1 would indicate 32bit addressing mode
1094output [15:0] meta1_rdmc_rbr_resp_byteenable;
1095output [7:0] meta1_rdmc_rbr_resp_cmd;
1096output [3:0] meta1_rdmc_rbr_resp_cmd_status;
1097output [127:0] meta1_rdmc_rbr_resp_data;
1098output [4:0] meta1_rdmc_rbr_resp_dma_num;
1099output meta1_rdmc_rbr_resp_ready;
1100output [31:0] meta_arb_debug_port;
1101output meta_dmc_ack_client_rdmc; // 4
1102output [7:0] meta_dmc_ack_cmd; // Command Request
1103output [3:0] meta_dmc_ack_cmd_status; // status in command phase
1104output [4:0] meta_dmc_ack_dma_num; // Channel Number
1105output meta_dmc_ack_ready; // Resp Command Request <--- all ack??
1106output [127:0] meta_dmc_data;
1107output [3:0] meta_dmc_data_status; // <- chg
1108output meta_dmc_data_valid_rdmc;
1109output meta_dmc_data_valid_txc;
1110output [63:0] meta_dmc_resp_address;
1111output [15:0] meta_dmc_resp_byteenable;
1112output meta_dmc_resp_client_rdmc;
1113output meta_dmc_resp_client_txc;
1114output [7:0] meta_dmc_resp_cmd;
1115output [3:0] meta_dmc_resp_cmd_status; // status in command phase
1116output meta_dmc_resp_complete_rdmc; // 5
1117output meta_dmc_resp_complete_txc; // 1
1118output [4:0] meta_dmc_resp_dma_num;
1119output [13:0] meta_dmc_resp_length;
1120output [1:0] meta_dmc_resp_port_num;
1121output meta_dmc_resp_ready;
1122output [5:0] meta_dmc_resp_trans_id;
1123output meta_dmc_resp_transfer_cmpl_rdmc;
1124output meta_dmc_resp_transfer_cmpl_txc;
1125output niu_dbg1_stall_ack;
1126output niu_efu_ram_data;
1127output niu_efu_ram_xfer_en;
1128output niu_ncu_ctag_ce;
1129output niu_ncu_ctag_ue;
1130output niu_ncu_d_pe;
1131output [127:0] niu_sii_data;
1132output niu_sii_datareq;
1133output niu_sii_hdr_vld;
1134output [7:0] niu_sii_parity;
1135output niu_sii_reqbypass;
1136output niu_sio_dq;
1137output scan_out; // unused as of today - feb 10, 05
1138output [31:0] smx_debug_port;
1139output smx_pio_intr; // level signal;
1140output [31:0] smx_pio_status; // status info related to intr
1141output [31:0] tdmc_debug_port;
1142output tdmc_pio_ack; // pio read data ack
1143output tdmc_pio_err; // pio read data error
1144output [63:0] tdmc_pio_intr;
1145output [63:0] tdmc_pio_rdata; // pio read data
1146output tds_mbist_scan_out;
1147output tds_smx_tcu_mbist_done;
1148output tds_smx_tcu_mbist_fail;
1149output [39:0] tds_tcu_dmo_dout;
1150output tds_tdmc_tcu_mbist_done;
1151output tds_tdmc_tcu_mbist_fail;
1152
1153wire [127:0] dmc_meta0_data;
1154wire [63:0] dmc_meta0_req_address;
1155wire [15:0] dmc_meta0_req_byteenable;
1156wire [63:0] dmc_meta1_req_address;
1157wire [127:0] tdmc_arb0_data;
1158wire [63:0] tdmc_arb0_req_address;
1159wire [15:0] tdmc_arb0_req_byteenable;
1160wire [63:0] tdmc_arb1_req_address;
1161wire [39:0] tds_tcu_dmo_data_out;
1162wire [15:0] x_meta1_rdmc_rbr_resp_byteenable;
1163wire [127:0] x_meta1_rdmc_rbr_resp_data;
1164wire aclk;
1165wire arb0_tdmc_data_req;
1166wire arb0_tdmc_req_accept;
1167wire arb1_tdmc_req_accept;
1168wire bclk;
1169wire dmc_meta0_data_valid;
1170wire dmc_meta0_req;
1171wire [7:0] dmc_meta0_req_client;
1172wire [7:0] dmc_meta0_req_cmd;
1173wire [4:0] dmc_meta0_req_dma_num;
1174wire [13:0] dmc_meta0_req_length;
1175wire [1:0] dmc_meta0_req_port_num;
1176wire [5:0] dmc_meta0_req_transID;
1177wire [3:0] dmc_meta0_status;
1178wire dmc_meta0_transfer_complete;
1179wire dmc_meta1_req;
1180wire [7:0] dmc_meta1_req_client;
1181wire [7:0] dmc_meta1_req_cmd;
1182wire [4:0] dmc_meta1_req_dma_num;
1183wire [13:0] dmc_meta1_req_length;
1184wire [1:0] dmc_meta1_req_port_num;
1185wire hdr_sram_red_clr_tdmc;
1186wire [1:0] hdr_sram_rid_tdmc;
1187wire [6:0] hdr_sram_rvalue_tdmc;
1188wire hdr_sram_wr_en_tdmc;
1189wire io2xclk_scan_out;
1190wire io2xl2clk;
1191wire ioclk_scan_out;
1192wire iol2clk;
1193wire l1clk;
1194wire meta_dmc0_data_req;
1195wire meta_dmc0_req_accept;
1196wire meta_dmc0_req_errors;
1197wire meta_dmc1_req_accept;
1198wire meta_dmc1_req_errors;
1199wire meta_dmc_ack_client_tdmc;
1200wire meta_dmc_ack_complete;
1201wire [5:0] meta_dmc_ack_transID;
1202wire [7:0] meta_dmc_ack_transfer_cmpl;
1203wire meta_dmc_data_valid_tdmc;
1204wire meta_dmc_resp_client_tdmc;
1205wire meta_dmc_resp_complete_tdmc;
1206wire [7:0] meta_dmc_resp_transfer_cmpl;
1207wire meta_dmc_resp_transfer_cmpl_tdmc;
1208wire niu_reset_l;
1209wire [6:0] sram_hdr_read_data_tdmc;
1210wire tdmc_arb0_data_valid;
1211wire tdmc_arb0_req;
1212wire [7:0] tdmc_arb0_req_cmd;
1213wire [4:0] tdmc_arb0_req_dma_num;
1214wire [1:0] tdmc_arb0_req_func_num;
1215wire [13:0] tdmc_arb0_req_length;
1216wire [1:0] tdmc_arb0_req_port_num;
1217wire [3:0] tdmc_arb0_status;
1218wire tdmc_arb0_transfer_complete;
1219wire tdmc_arb1_req;
1220wire [7:0] tdmc_arb1_req_cmd;
1221wire [4:0] tdmc_arb1_req_dma_num;
1222wire [1:0] tdmc_arb1_req_func_num;
1223wire [13:0] tdmc_arb1_req_length;
1224wire [1:0] tdmc_arb1_req_port_num;
1225wire tdmc_meta_ack_accept;
1226wire tdmc_meta_resp_accept;
1227wire tds_array_wr_inhibit;
1228wire tds_pce_ov;
1229wire tds_smx_mbist_scan_in;
1230wire [10:7] unconnected_1;
1231wire [10:2] unconnected_2;
1232wire [7:0] x_meta1_rdmc_rbr_resp_cmd;
1233wire [3:0] x_meta1_rdmc_rbr_resp_cmd_status;
1234wire [4:0] x_meta1_rdmc_rbr_resp_dma_num;
1235wire x_meta1_rdmc_rbr_resp_ready;
1236
1237niu_smx niu_smx (
1238 .niu_clk (l1clk),
1239 .iol2clk (iol2clk),
1240 .niu_reset_l (niu_reset_l),
1241 .niu_sii_hdr_vld (niu_sii_hdr_vld),
1242 .niu_sii_reqbypass (niu_sii_reqbypass),
1243 .niu_sii_datareq (niu_sii_datareq),
1244 .niu_sii_data (niu_sii_data[127:0]),
1245 .niu_sii_parity (niu_sii_parity[7:0]),
1246 .sii_niu_oqdq (sii_niu_oqdq),
1247 .sii_niu_bqdq (sii_niu_bqdq),
1248 .sio_niu_hdr_vld (sio_niu_hdr_vld),
1249 .sio_niu_datareq (sio_niu_datareq),
1250 .sio_niu_data (sio_niu_data[127:0]),
1251 .sio_niu_parity (sio_niu_parity[7:0]),
1252 .niu_sio_dq (niu_sio_dq),
1253 .dmc_meta0_req (dmc_meta0_req),
1254 .dmc_meta0_req_cmd (dmc_meta0_req_cmd[7:0]),
1255 .dmc_meta0_req_address (dmc_meta0_req_address[63:0]),
1256 .dmc_meta0_req_length (dmc_meta0_req_length[13:0]),
1257 .dmc_meta0_req_transID (dmc_meta0_req_transID[5:0]),
1258 .dmc_meta0_req_port_num (dmc_meta0_req_port_num[1:0]),
1259 .dmc_meta0_req_dma_num (dmc_meta0_req_dma_num[4:0]),
1260 .dmc_meta0_req_client (dmc_meta0_req_client[7:0]),
1261 .meta_dmc0_req_accept (meta_dmc0_req_accept),
1262 .meta_dmc0_req_errors (meta_dmc0_req_errors),
1263 .meta_dmc0_data_req (meta_dmc0_data_req),
1264 .dmc_meta0_data_valid (dmc_meta0_data_valid),
1265 .dmc_meta0_data (dmc_meta0_data[127:0]),
1266 .dmc_meta0_req_byteenable (dmc_meta0_req_byteenable[15:0]),
1267 .dmc_meta0_status (dmc_meta0_status[3:0]),
1268 .dmc_meta0_transfer_complete (dmc_meta0_transfer_complete),
1269 .dmc_meta1_req (dmc_meta1_req),
1270 .dmc_meta1_req_cmd (dmc_meta1_req_cmd[7:0]),
1271 .dmc_meta1_req_address (dmc_meta1_req_address[63:0]),
1272 .dmc_meta1_req_length (dmc_meta1_req_length[13:0]),
1273 .dmc_meta1_req_transID (dmc_meta1_req_trans_id[5:0]),
1274 .dmc_meta1_req_port_num (dmc_meta1_req_port_num[1:0]),
1275 .dmc_meta1_req_dma_num (dmc_meta1_req_dma_num[4:0]),
1276 .dmc_meta1_req_client (dmc_meta1_req_client[7:0]),
1277 .meta_dmc1_req_accept (meta_dmc1_req_accept),
1278 .meta_dmc1_req_errors (meta_dmc1_req_errors),
1279 .meta_dmc_resp_ready (x_meta1_rdmc_rbr_resp_ready),
1280 .meta_dmc_resp_cmd (x_meta1_rdmc_rbr_resp_cmd[7:0]),
1281 .meta_dmc_resp_cmd_status (x_meta1_rdmc_rbr_resp_cmd_status[3:0]),
1282 .meta_dmc_resp_address (meta_dmc_resp_address[63:0]),
1283 .meta_dmc_resp_length (meta_dmc_resp_length[13:0]),
1284 .meta_dmc_resp_transID (meta_dmc_resp_trans_id[5:0]),
1285 .meta_dmc_resp_port_num (meta_dmc_resp_port_num[1:0]),
1286 .meta_dmc_resp_dma_num (x_meta1_rdmc_rbr_resp_dma_num[4:0]),
1287 .meta_dmc_resp_client_txc (meta_dmc_resp_client_txc),
1288 .meta_dmc_resp_client_tdmc (meta_dmc_resp_client_tdmc),
1289 .meta_dmc_resp_client_rdmc (meta_dmc_resp_client_rdmc),
1290 .rdmc_meta_resp_accept (rdmc_meta_resp_accept),
1291 .txc_meta_resp_accept (txc_meta_resp_accept),
1292 .tdmc_meta_resp_accept (tdmc_meta_resp_accept),
1293 .meta_dmc_data_valid_txc (meta_dmc_data_valid_txc),
1294 .meta_dmc_data_valid_tdmc (meta_dmc_data_valid_tdmc),
1295 .meta_dmc_data_valid_rdmc (meta_dmc_data_valid_rdmc),
1296 .meta_dmc_data (x_meta1_rdmc_rbr_resp_data[127:0]),
1297 .meta_dmc_resp_byteenable (x_meta1_rdmc_rbr_resp_byteenable[15:0]),
1298 .meta_dmc_data_status (meta_dmc_data_status[3:0]),
1299 .meta_dmc_resp_complete_txc (meta_dmc_resp_complete_txc),
1300 .meta_dmc_resp_complete_tdmc (meta_dmc_resp_complete_tdmc),
1301 .meta_dmc_resp_complete_rdmc (meta_dmc_resp_complete_rdmc),
1302 .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl[7:0]),
1303 .meta_dmc_resp_transfer_cmpl_txc (meta_dmc_resp_transfer_cmpl_txc),
1304 .meta_dmc_resp_transfer_cmpl_tdmc (meta_dmc_resp_transfer_cmpl_tdmc),
1305 .meta_dmc_resp_transfer_cmpl_rdmc (meta_dmc_resp_transfer_cmpl_rdmc),
1306 .meta_dmc_ack_ready (meta_dmc_ack_ready),
1307 .meta_dmc_ack_cmd (meta_dmc_ack_cmd[7:0]),
1308 .meta_dmc_ack_cmd_status (meta_dmc_ack_cmd_status[3:0]),
1309 .meta_dmc_ack_dma_num (meta_dmc_ack_dma_num[4:0]),
1310 .meta_dmc_ack_transID (meta_dmc_ack_transID[5:0]),
1311 .meta_dmc_ack_client_tdmc (meta_dmc_ack_client_tdmc),
1312 .meta_dmc_ack_client_rdmc (meta_dmc_ack_client_rdmc),
1313 .meta_dmc_ack_complete (meta_dmc_ack_complete),
1314 .meta_dmc_ack_transfer_cmpl (meta_dmc_ack_transfer_cmpl[7:0]),
1315 .rdmc_meta_ack_accept (rdmc_meta_ack_accept),
1316 .tdmc_meta_ack_accept (tdmc_meta_ack_accept),
1317 .ncu_niu_ctag_uei (ncu_niu_ctag_uei),
1318 .ncu_niu_ctag_cei (ncu_niu_ctag_cei),
1319 .ncu_niu_d_pei (ncu_niu_d_pei),
1320 .niu_ncu_ctag_ue (niu_ncu_ctag_ue),
1321 .niu_ncu_ctag_ce (niu_ncu_ctag_ce),
1322 .niu_ncu_d_pe (niu_ncu_d_pe),
1323 .tcu_aclk (aclk),
1324 .tcu_bclk (bclk),
1325 .tcu_se_scancollar_in (tcu_se_scancollar_in),
1326 .tcu_array_wr_inhibit (tds_array_wr_inhibit),
1327 .tcu_mbist_user_mode (tcu_mbist_user_mode),
1328 .tds_smx_mbist_scan_in (tds_smx_mbist_scan_in),
1329 .tcu_tds_smx_mbist_start (tcu_tds_smx_mbist_start),
1330 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
1331 .tds_smx_tcu_mbist_fail (tds_smx_tcu_mbist_fail),
1332 .tds_smx_tcu_mbist_done (tds_smx_tcu_mbist_done),
1333 .tds_smx_mbist_scan_out (tds_mbist_scan_out),
1334 .pio_smx_cfg_data (pio_smx_cfg_data[31:0]),
1335 .smx_pio_intr (smx_pio_intr),
1336 .smx_pio_status (smx_pio_status[31:0]),
1337 .pio_smx_clear_intr (pio_smx_clear_intr),
1338 .pio_smx_ctrl (pio_smx_ctrl[31:0]),
1339 .pio_smx_debug_vector (pio_smx_debug_vector[31:0]),
1340 .dbg1_niu_stall (dbg1_niu_stall),
1341 .dbg1_niu_resume (dbg1_niu_resume),
1342 .niu_dbg1_stall_ack (niu_dbg1_stall_ack),
1343 .smx_debug_port (smx_debug_port[31:0])
1344 );
1345
1346niu_meta_arb niu_meta_arb (
1347 .meta_dmc0_data_req (meta_dmc0_data_req),
1348 .meta_dmc0_req_accept (meta_dmc0_req_accept),
1349 .meta_dmc0_req_errors (meta_dmc0_req_errors),
1350 .meta_dmc1_req_accept (meta_dmc1_req_accept),
1351 .meta_dmc1_req_errors (meta_dmc1_req_errors),
1352 .meta_dmc_ack_cmd_status (meta_dmc_ack_cmd_status[3:0]),
1353 .meta_dmc_ack_transID (meta_dmc_ack_transID[5:0]),
1354 .meta_dmc_ack_transfer_cmpl (meta_dmc_ack_transfer_cmpl[7:0]),
1355 .meta_dmc_resp_cmd_status (meta_dmc_resp_cmd_status[3:0]),
1356 .meta_dmc_resp_transID (meta_dmc_resp_trans_id[5:0]),
1357 .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl[7:0]),
1358 .pio_arb_ctrl (pio_arb_ctrl[31:0]),
1359 .pio_arb_debug_vector (pio_arb_debug_vector[31:0]),
1360 .pio_arb_dirtid_clr (pio_arb_dirtid_clr),
1361 .pio_arb_dirtid_enable (pio_arb_dirtid_enable),
1362 .pio_arb_np_threshold (pio_arb_np_threshold[5:0]),
1363 .pio_arb_rd_threshold (pio_arb_rd_threshold[5:0]),
1364 .rbr_arb1_req (rbr_arb1_req),
1365 .rbr_arb1_req_address (rbr_arb1_req_address[63:0]),
1366 .rbr_arb1_req_cmd (rbr_arb1_req_cmd[7:0]),
1367 .rbr_arb1_req_dma_num (rbr_arb1_req_dma_num[4:0]),
1368 .rbr_arb1_req_func_num (rbr_arb1_req_func_num[1:0]),
1369 .rbr_arb1_req_length (rbr_arb1_req_length[13:0]),
1370 .rbr_arb1_req_port_num (rbr_arb1_req_port_num[1:0]),
1371 .rcr_arb0_data (rcr_arb0_data[127:0]),
1372 .rcr_arb0_data_valid (rcr_arb0_data_valid),
1373 .rcr_arb0_req (rcr_arb0_req),
1374 .rcr_arb0_req_address (rcr_arb0_req_address[63:0]),
1375 .rcr_arb0_req_byteenable (rcr_arb0_req_byteenable[15:0]),
1376 .rcr_arb0_req_cmd (rcr_arb0_req_cmd[7:0]),
1377 .rcr_arb0_req_dma_num (rcr_arb0_req_dma_num[4:0]),
1378 .rcr_arb0_req_func_num (rcr_arb0_req_func_num[1:0]),
1379 .rcr_arb0_req_length (rcr_arb0_req_length[13:0]),
1380 .rcr_arb0_req_port_num (rcr_arb0_req_port_num[1:0]),
1381 .rcr_arb0_status (rcr_arb0_status[3:0]),
1382 .rcr_arb0_transfer_complete (rcr_arb0_transfer_complete),
1383 .rdc_arb0_data (rdc_arb0_data[127:0]),
1384 .rdc_arb0_data_valid (rdc_arb0_data_valid),
1385 .rdc_arb0_req (rdc_arb0_req),
1386 .rdc_arb0_req_address (rdc_arb0_req_address[63:0]),
1387 .rdc_arb0_req_byteenable (rdc_arb0_req_byteenable[15:0]),
1388 .rdc_arb0_req_cmd (rdc_arb0_req_cmd[7:0]),
1389 .rdc_arb0_req_dma_num (rdc_arb0_req_dma_num[4:0]),
1390 .rdc_arb0_req_func_num (rdc_arb0_req_func_num[1:0]),
1391 .rdc_arb0_req_length (rdc_arb0_req_length[13:0]),
1392 .rdc_arb0_req_port_num (rdc_arb0_req_port_num[1:0]),
1393 .rdc_arb0_status (rdc_arb0_status[3:0]),
1394 .rdc_arb0_transfer_complete (rdc_arb0_transfer_complete),
1395 .tdmc_arb0_data (tdmc_arb0_data[127:0]),
1396 .tdmc_arb0_data_valid (tdmc_arb0_data_valid),
1397 .tdmc_arb0_req (tdmc_arb0_req),
1398 .tdmc_arb0_req_address (tdmc_arb0_req_address[63:0]),
1399 .tdmc_arb0_req_byteenable (tdmc_arb0_req_byteenable[15:0]),
1400 .tdmc_arb0_req_cmd (tdmc_arb0_req_cmd[7:0]),
1401 .tdmc_arb0_req_dma_num (tdmc_arb0_req_dma_num[4:0]),
1402 .tdmc_arb0_req_func_num (tdmc_arb0_req_func_num[1:0]),
1403 .tdmc_arb0_req_length (tdmc_arb0_req_length[13:0]),
1404 .tdmc_arb0_req_port_num (tdmc_arb0_req_port_num[1:0]),
1405 .tdmc_arb0_status (tdmc_arb0_status[3:0]),
1406 .tdmc_arb0_transfer_complete (tdmc_arb0_transfer_complete),
1407 .tdmc_arb1_req (tdmc_arb1_req),
1408 .tdmc_arb1_req_address (tdmc_arb1_req_address[63:0]),
1409 .tdmc_arb1_req_cmd (tdmc_arb1_req_cmd[7:0]),
1410 .tdmc_arb1_req_dma_num (tdmc_arb1_req_dma_num[4:0]),
1411 .tdmc_arb1_req_func_num (tdmc_arb1_req_func_num[1:0]),
1412 .tdmc_arb1_req_length (tdmc_arb1_req_length[13:0]),
1413 .tdmc_arb1_req_port_num (tdmc_arb1_req_port_num[1:0]),
1414 .txc_arb1_req (txc_arb1_req),
1415 .txc_arb1_req_address (txc_arb1_req_address[63:0]),
1416 .txc_arb1_req_cmd (txc_arb1_req_cmd[7:0]),
1417 .txc_arb1_req_dma_num (txc_arb1_req_dma_num[4:0]),
1418 .txc_arb1_req_func_num (txc_arb1_req_func_num[1:0]),
1419 .txc_arb1_req_length (txc_arb1_req_length[13:0]),
1420 .txc_arb1_req_port_num (txc_arb1_req_port_num[1:0]),
1421 .arb0_rcr_data_req (arb0_rcr_data_req),
1422 .arb0_rcr_req_accept (arb0_rcr_req_accept),
1423 .arb0_rdc_data_req (arb0_rdc_data_req),
1424 .arb0_rdc_req_accept (arb0_rdc_req_accept),
1425 .arb0_tdmc_data_req (arb0_tdmc_data_req),
1426 .arb0_tdmc_req_accept (arb0_tdmc_req_accept),
1427 .arb1_rbr_req_accept (arb1_rbr_req_accept),
1428 .arb1_tdmc_req_accept (arb1_tdmc_req_accept),
1429 .arb1_txc_req_accept (arb1_txc_req_accept),
1430 .arb1_rbr_req_errors (arb1_rbr_req_errors),
1431 .arb_pio_all_npwdirty (arb_pio_all_npwdirty),
1432 .arb_pio_all_rddirty (arb_pio_all_rddirty),
1433 .arb_pio_dirtid_npwstatus (arb_pio_dirtid_npwstatus[5:0]),
1434 .arb_pio_dirtid_rdstatus (arb_pio_dirtid_rdstatus[5:0]),
1435 .dmc_meta0_data (dmc_meta0_data[127:0]),
1436 .dmc_meta0_data_valid (dmc_meta0_data_valid),
1437 .dmc_meta0_req (dmc_meta0_req),
1438 .dmc_meta0_req_address (dmc_meta0_req_address[63:0]),
1439 .dmc_meta0_req_byteenable (dmc_meta0_req_byteenable[15:0]),
1440 .dmc_meta0_req_client (dmc_meta0_req_client[7:0]),
1441 .dmc_meta0_req_cmd (dmc_meta0_req_cmd[7:0]),
1442 .dmc_meta0_req_dma_num (dmc_meta0_req_dma_num[4:0]),
1443 .dmc_meta0_req_length (dmc_meta0_req_length[13:0]),
1444 .dmc_meta0_req_port_num (dmc_meta0_req_port_num[1:0]),
1445 .dmc_meta0_req_transID (dmc_meta0_req_transID[5:0]),
1446 .dmc_meta0_status (dmc_meta0_status[3:0]),
1447 .dmc_meta0_transfer_complete (dmc_meta0_transfer_complete),
1448 .dmc_meta1_req (dmc_meta1_req),
1449 .dmc_meta1_req_address (dmc_meta1_req_address[63:0]),
1450 .dmc_meta1_req_client (dmc_meta1_req_client[7:0]),
1451 .dmc_meta1_req_cmd (dmc_meta1_req_cmd[7:0]),
1452 .dmc_meta1_req_dma_num (dmc_meta1_req_dma_num[4:0]),
1453 .dmc_meta1_req_length (dmc_meta1_req_length[13:0]),
1454 .dmc_meta1_req_port_num (dmc_meta1_req_port_num[1:0]),
1455 .dmc_meta1_req_transID (dmc_meta1_req_trans_id[5:0]),
1456 .meta_arb_debug_port (meta_arb_debug_port[31:0]),
1457 .niu_clk (l1clk),
1458 .niu_reset_l (niu_reset_l),
1459 .rdmc_meta_ack_accept (rdmc_meta_ack_accept),
1460 .tdmc_meta_ack_accept (tdmc_meta_ack_accept),
1461 .rdmc_meta_resp_accept (rdmc_meta_resp_accept),
1462 .tdmc_meta_resp_accept (tdmc_meta_resp_accept),
1463 .txc_meta_resp_accept (txc_meta_resp_accept)
1464 );
1465
1466niu_tdmc niu_tdmc (
1467 .niu_clk (l1clk),
1468 .niu_reset_l (niu_reset_l),
1469 .tdmc_debug_port (tdmc_debug_port[31:0]),
1470 .tcu_aclk (aclk),
1471 .tcu_bclk (bclk),
1472 .tcu_se_scancollar_in (tcu_se_scancollar_in),
1473 .tcu_se_scancollar_out (tcu_se_scancollar_out),
1474 .tcu_array_wr_inhibit (tds_array_wr_inhibit),
1475 .tcu_scan_en (tcu_scan_en),
1476 .tds_tdmc_mbist_scan_in (tds_mbist_scan_in),
1477 .tds_tdmc_mbist_scan_out (tds_smx_mbist_scan_in),
1478 .tcu_mbist_user_mode (tcu_mbist_user_mode),
1479 .tcu_tds_tdmc_mbist_start (tcu_tds_tdmc_mbist_start),
1480 .tcu_mbist_bisi_en (tcu_mbist_bisi_en),
1481 .tds_tdmc_tcu_mbist_fail (tds_tdmc_tcu_mbist_fail),
1482 .tds_tdmc_tcu_mbist_done (tds_tdmc_tcu_mbist_done),
1483 .l2clk_2x (io2xl2clk),
1484 .iol2clk (iol2clk),
1485 .hdr_sram_rvalue_tdmc ( hdr_sram_rvalue_tdmc[6:0]),
1486 .hdr_sram_rid_tdmc (hdr_sram_rid_tdmc[1:0]),
1487 .hdr_sram_wr_en_tdmc (hdr_sram_wr_en_tdmc),
1488 .hdr_sram_red_clr_tdmc (hdr_sram_red_clr_tdmc),
1489 .sram_hdr_read_data_tdmc (sram_hdr_read_data_tdmc[6:0]),
1490 .tds_tcu_dmo_data_out (tds_tcu_dmo_data_out[39:0]),
1491 .tdmc_arb1_req (tdmc_arb1_req),
1492 .tdmc_arb1_req_port_num (tdmc_arb1_req_port_num[1:0]),
1493 .tdmc_arb1_req_dma_num (tdmc_arb1_req_dma_num[4:0]),
1494 .tdmc_arb1_req_cmd (tdmc_arb1_req_cmd[7:0]),
1495 .tdmc_arb1_req_length (tdmc_arb1_req_length[13:0]),
1496 .tdmc_arb1_req_address (tdmc_arb1_req_address[63:0]),
1497 .dmc_meta_resp_accept (tdmc_meta_resp_accept),
1498 .tdmc_arb1_req_func_num (tdmc_arb1_req_func_num[1:0]),
1499 .arb1_tdmc_req_accept (arb1_tdmc_req_accept),
1500 .meta_dmc_resp_ready (x_meta1_rdmc_rbr_resp_ready),
1501 .meta_dmc_resp_client (meta_dmc_resp_client_tdmc),
1502 .meta_dmc_resp_complete (meta_dmc_resp_complete_tdmc),
1503 .meta_dmc_resp_transfer_cmpl (meta_dmc_resp_transfer_cmpl_tdmc),
1504 .meta_dmc_data_valid (meta_dmc_data_valid_tdmc),
1505 .meta_dmc_resp_dma_num (x_meta1_rdmc_rbr_resp_dma_num[4:0]),
1506 .meta_dmc_resp_length (meta_dmc_resp_length[13:0]),
1507 .meta_dmc_resp_byteenable (x_meta1_rdmc_rbr_resp_byteenable[15:0]),
1508 .meta_dmc_resp_address (meta_dmc_resp_address[63:0]),
1509 .meta_dmc_data (x_meta1_rdmc_rbr_resp_data[127:0]),
1510 .meta_dmc_resp_cmd (x_meta1_rdmc_rbr_resp_cmd[7:0]),
1511 .meta_dmc_resp_cmd_status (x_meta1_rdmc_rbr_resp_cmd_status[3:0]),
1512 .meta_dmc_data_status (meta_dmc_data_status[3:0]),
1513 .tdmc_arb0_data_valid (tdmc_arb0_data_valid),
1514 .tdmc_arb0_req (tdmc_arb0_req),
1515 .tdmc_arb0_transfer_complete (tdmc_arb0_transfer_complete),
1516 .tdmc_arb0_req_port_num (tdmc_arb0_req_port_num[1:0]),
1517 .tdmc_arb0_status (tdmc_arb0_status[3:0]),
1518 .tdmc_arb0_req_dma_num (tdmc_arb0_req_dma_num[4:0]),
1519 .tdmc_arb0_req_cmd (tdmc_arb0_req_cmd[7:0]),
1520 .tdmc_arb0_req_length (tdmc_arb0_req_length[13:0]),
1521 .tdmc_arb0_req_byteenable (tdmc_arb0_req_byteenable[15:0]),
1522 .tdmc_arb0_req_address (tdmc_arb0_req_address[63:0]),
1523 .tdmc_arb0_data (tdmc_arb0_data[127:0]),
1524 .tdmc_arb0_req_func_num (tdmc_arb0_req_func_num[1:0]),
1525 .dmc_meta_ack_accept (tdmc_meta_ack_accept),
1526 .arb0_tdmc_data_req (arb0_tdmc_data_req),
1527 .arb0_tdmc_req_accept (arb0_tdmc_req_accept),
1528 .meta_dmc_ack_ready (meta_dmc_ack_ready),
1529 .meta_dmc_ack_client (meta_dmc_ack_client_tdmc),
1530 .meta_dmc_ack_complete (meta_dmc_ack_complete),
1531 .meta_dmc_ack_dma_num (meta_dmc_ack_dma_num[4:0]),
1532 .meta_dmc_ack_cmd (meta_dmc_ack_cmd[7:0]),
1533 .meta_dmc_ack_cmd_status (meta_dmc_ack_cmd_status[3:0]),
1534 .tdmc_pio_ack (tdmc_pio_ack),
1535 .tdmc_pio_err (tdmc_pio_err),
1536 .tdmc_pio_rdata (tdmc_pio_rdata[63:0]),
1537 .tdmc_pio_intr (tdmc_pio_intr[63:0]),
1538 .pio_clients_rd (pio_clients_rd),
1539 .pio_tdmc_sel (pio_tdmc_sel),
1540 .pio_clients_addr (pio_clients_addr[19:0]),
1541 .pio_clients_wdata (pio_clients_wdata[63:0]),
1542 .txc_dmc_dma0_getnxtdesc (txc_dmc_dma0_getnxtdesc),
1543 .txc_dmc_dma0_inc_head (txc_dmc_dma0_inc_head),
1544 .txc_dmc_dma0_reset_done (txc_dmc_dma0_reset_done),
1545 .txc_dmc_dma0_mark_bit (txc_dmc_dma0_mark_bit),
1546 .txc_dmc_dma0_inc_pkt_cnt (txc_dmc_dma0_inc_pkt_cnt),
1547 .dmc_txc_dma0_active (dmc_txc_dma0_active),
1548 .dmc_txc_dma0_eoflist (dmc_txc_dma0_eoflist),
1549 .dmc_txc_dma0_error (dmc_txc_dma0_error),
1550 .dmc_txc_dma0_gotnxtdesc (dmc_txc_dma0_gotnxtdesc),
1551 .dmc_txc_dma0_cacheready (dmc_txc_dma0_cacheready),
1552 .dmc_txc_dma0_partial (dmc_txc_dma0_partial),
1553 .dmc_txc_dma0_reset_scheduled (dmc_txc_dma0_reset_scheduled),
1554 .dmc_txc_dma0_page_handle (dmc_txc_dma0_page_handle[19:0]),
1555 .dmc_txc_dma0_descriptor (dmc_txc_dma0_descriptor[63:0]),
1556 .txc_dmc_dma1_getnxtdesc (txc_dmc_dma1_getnxtdesc),
1557 .txc_dmc_dma1_inc_head (txc_dmc_dma1_inc_head),
1558 .txc_dmc_dma1_reset_done (txc_dmc_dma1_reset_done),
1559 .txc_dmc_dma1_mark_bit (txc_dmc_dma1_mark_bit),
1560 .txc_dmc_dma1_inc_pkt_cnt (txc_dmc_dma1_inc_pkt_cnt),
1561 .dmc_txc_dma1_active (dmc_txc_dma1_active),
1562 .dmc_txc_dma1_eoflist (dmc_txc_dma1_eoflist),
1563 .dmc_txc_dma1_error (dmc_txc_dma1_error),
1564 .dmc_txc_dma1_gotnxtdesc (dmc_txc_dma1_gotnxtdesc),
1565 .dmc_txc_dma1_cacheready (dmc_txc_dma1_cacheready),
1566 .dmc_txc_dma1_partial (dmc_txc_dma1_partial),
1567 .dmc_txc_dma1_reset_scheduled (dmc_txc_dma1_reset_scheduled),
1568 .dmc_txc_dma1_page_handle (dmc_txc_dma1_page_handle[19:0]),
1569 .dmc_txc_dma1_descriptor (dmc_txc_dma1_descriptor[63:0]),
1570 .txc_dmc_dma2_getnxtdesc (txc_dmc_dma2_getnxtdesc),
1571 .txc_dmc_dma2_inc_head (txc_dmc_dma2_inc_head),
1572 .txc_dmc_dma2_reset_done (txc_dmc_dma2_reset_done),
1573 .txc_dmc_dma2_mark_bit (txc_dmc_dma2_mark_bit),
1574 .txc_dmc_dma2_inc_pkt_cnt (txc_dmc_dma2_inc_pkt_cnt),
1575 .dmc_txc_dma2_active (dmc_txc_dma2_active),
1576 .dmc_txc_dma2_eoflist (dmc_txc_dma2_eoflist),
1577 .dmc_txc_dma2_error (dmc_txc_dma2_error),
1578 .dmc_txc_dma2_gotnxtdesc (dmc_txc_dma2_gotnxtdesc),
1579 .dmc_txc_dma2_cacheready (dmc_txc_dma2_cacheready),
1580 .dmc_txc_dma2_partial (dmc_txc_dma2_partial),
1581 .dmc_txc_dma2_reset_scheduled (dmc_txc_dma2_reset_scheduled),
1582 .dmc_txc_dma2_page_handle (dmc_txc_dma2_page_handle[19:0]),
1583 .dmc_txc_dma2_descriptor (dmc_txc_dma2_descriptor[63:0]),
1584 .txc_dmc_dma3_getnxtdesc (txc_dmc_dma3_getnxtdesc),
1585 .txc_dmc_dma3_inc_head (txc_dmc_dma3_inc_head),
1586 .txc_dmc_dma3_reset_done (txc_dmc_dma3_reset_done),
1587 .txc_dmc_dma3_mark_bit (txc_dmc_dma3_mark_bit),
1588 .txc_dmc_dma3_inc_pkt_cnt (txc_dmc_dma3_inc_pkt_cnt),
1589 .dmc_txc_dma3_active (dmc_txc_dma3_active),
1590 .dmc_txc_dma3_eoflist (dmc_txc_dma3_eoflist),
1591 .dmc_txc_dma3_error (dmc_txc_dma3_error),
1592 .dmc_txc_dma3_gotnxtdesc (dmc_txc_dma3_gotnxtdesc),
1593 .dmc_txc_dma3_cacheready (dmc_txc_dma3_cacheready),
1594 .dmc_txc_dma3_partial (dmc_txc_dma3_partial),
1595 .dmc_txc_dma3_reset_scheduled (dmc_txc_dma3_reset_scheduled),
1596 .dmc_txc_dma3_page_handle (dmc_txc_dma3_page_handle[19:0]),
1597 .dmc_txc_dma3_descriptor (dmc_txc_dma3_descriptor[63:0]),
1598 .txc_dmc_dma4_getnxtdesc (txc_dmc_dma4_getnxtdesc),
1599 .txc_dmc_dma4_inc_head (txc_dmc_dma4_inc_head),
1600 .txc_dmc_dma4_reset_done (txc_dmc_dma4_reset_done),
1601 .txc_dmc_dma4_mark_bit (txc_dmc_dma4_mark_bit),
1602 .txc_dmc_dma4_inc_pkt_cnt (txc_dmc_dma4_inc_pkt_cnt),
1603 .dmc_txc_dma4_active (dmc_txc_dma4_active),
1604 .dmc_txc_dma4_eoflist (dmc_txc_dma4_eoflist),
1605 .dmc_txc_dma4_error (dmc_txc_dma4_error),
1606 .dmc_txc_dma4_gotnxtdesc (dmc_txc_dma4_gotnxtdesc),
1607 .dmc_txc_dma4_cacheready (dmc_txc_dma4_cacheready),
1608 .dmc_txc_dma4_partial (dmc_txc_dma4_partial),
1609 .dmc_txc_dma4_reset_scheduled (dmc_txc_dma4_reset_scheduled),
1610 .dmc_txc_dma4_page_handle (dmc_txc_dma4_page_handle[19:0]),
1611 .dmc_txc_dma4_descriptor (dmc_txc_dma4_descriptor[63:0]),
1612 .txc_dmc_dma5_getnxtdesc (txc_dmc_dma5_getnxtdesc),
1613 .txc_dmc_dma5_inc_head (txc_dmc_dma5_inc_head),
1614 .txc_dmc_dma5_reset_done (txc_dmc_dma5_reset_done),
1615 .txc_dmc_dma5_mark_bit (txc_dmc_dma5_mark_bit),
1616 .txc_dmc_dma5_inc_pkt_cnt (txc_dmc_dma5_inc_pkt_cnt),
1617 .dmc_txc_dma5_active (dmc_txc_dma5_active),
1618 .dmc_txc_dma5_eoflist (dmc_txc_dma5_eoflist),
1619 .dmc_txc_dma5_error (dmc_txc_dma5_error),
1620 .dmc_txc_dma5_gotnxtdesc (dmc_txc_dma5_gotnxtdesc),
1621 .dmc_txc_dma5_cacheready (dmc_txc_dma5_cacheready),
1622 .dmc_txc_dma5_partial (dmc_txc_dma5_partial),
1623 .dmc_txc_dma5_reset_scheduled (dmc_txc_dma5_reset_scheduled),
1624 .dmc_txc_dma5_page_handle (dmc_txc_dma5_page_handle[19:0]),
1625 .dmc_txc_dma5_descriptor (dmc_txc_dma5_descriptor[63:0]),
1626 .txc_dmc_dma6_getnxtdesc (txc_dmc_dma6_getnxtdesc),
1627 .txc_dmc_dma6_inc_head (txc_dmc_dma6_inc_head),
1628 .txc_dmc_dma6_reset_done (txc_dmc_dma6_reset_done),
1629 .txc_dmc_dma6_mark_bit (txc_dmc_dma6_mark_bit),
1630 .txc_dmc_dma6_inc_pkt_cnt (txc_dmc_dma6_inc_pkt_cnt),
1631 .dmc_txc_dma6_active (dmc_txc_dma6_active),
1632 .dmc_txc_dma6_eoflist (dmc_txc_dma6_eoflist),
1633 .dmc_txc_dma6_error (dmc_txc_dma6_error),
1634 .dmc_txc_dma6_gotnxtdesc (dmc_txc_dma6_gotnxtdesc),
1635 .dmc_txc_dma6_cacheready (dmc_txc_dma6_cacheready),
1636 .dmc_txc_dma6_partial (dmc_txc_dma6_partial),
1637 .dmc_txc_dma6_reset_scheduled (dmc_txc_dma6_reset_scheduled),
1638 .dmc_txc_dma6_page_handle (dmc_txc_dma6_page_handle[19:0]),
1639 .dmc_txc_dma6_descriptor (dmc_txc_dma6_descriptor[63:0]),
1640 .txc_dmc_dma7_getnxtdesc (txc_dmc_dma7_getnxtdesc),
1641 .txc_dmc_dma7_inc_head (txc_dmc_dma7_inc_head),
1642 .txc_dmc_dma7_reset_done (txc_dmc_dma7_reset_done),
1643 .txc_dmc_dma7_mark_bit (txc_dmc_dma7_mark_bit),
1644 .txc_dmc_dma7_inc_pkt_cnt (txc_dmc_dma7_inc_pkt_cnt),
1645 .dmc_txc_dma7_active (dmc_txc_dma7_active),
1646 .dmc_txc_dma7_eoflist (dmc_txc_dma7_eoflist),
1647 .dmc_txc_dma7_error (dmc_txc_dma7_error),
1648 .dmc_txc_dma7_gotnxtdesc (dmc_txc_dma7_gotnxtdesc),
1649 .dmc_txc_dma7_cacheready (dmc_txc_dma7_cacheready),
1650 .dmc_txc_dma7_partial (dmc_txc_dma7_partial),
1651 .dmc_txc_dma7_reset_scheduled (dmc_txc_dma7_reset_scheduled),
1652 .dmc_txc_dma7_page_handle (dmc_txc_dma7_page_handle[19:0]),
1653 .dmc_txc_dma7_descriptor (dmc_txc_dma7_descriptor[63:0]),
1654 .txc_dmc_dma8_getnxtdesc (txc_dmc_dma8_getnxtdesc),
1655 .txc_dmc_dma8_inc_head (txc_dmc_dma8_inc_head),
1656 .txc_dmc_dma8_reset_done (txc_dmc_dma8_reset_done),
1657 .txc_dmc_dma8_mark_bit (txc_dmc_dma8_mark_bit),
1658 .txc_dmc_dma8_inc_pkt_cnt (txc_dmc_dma8_inc_pkt_cnt),
1659 .dmc_txc_dma8_active (dmc_txc_dma8_active),
1660 .dmc_txc_dma8_eoflist (dmc_txc_dma8_eoflist),
1661 .dmc_txc_dma8_error (dmc_txc_dma8_error),
1662 .dmc_txc_dma8_gotnxtdesc (dmc_txc_dma8_gotnxtdesc),
1663 .dmc_txc_dma8_cacheready (dmc_txc_dma8_cacheready),
1664 .dmc_txc_dma8_partial (dmc_txc_dma8_partial),
1665 .dmc_txc_dma8_reset_scheduled (dmc_txc_dma8_reset_scheduled),
1666 .dmc_txc_dma8_page_handle (dmc_txc_dma8_page_handle[19:0]),
1667 .dmc_txc_dma8_descriptor (dmc_txc_dma8_descriptor[63:0]),
1668 .txc_dmc_dma9_getnxtdesc (txc_dmc_dma9_getnxtdesc),
1669 .txc_dmc_dma9_inc_head (txc_dmc_dma9_inc_head),
1670 .txc_dmc_dma9_reset_done (txc_dmc_dma9_reset_done),
1671 .txc_dmc_dma9_mark_bit (txc_dmc_dma9_mark_bit),
1672 .txc_dmc_dma9_inc_pkt_cnt (txc_dmc_dma9_inc_pkt_cnt),
1673 .dmc_txc_dma9_active (dmc_txc_dma9_active),
1674 .dmc_txc_dma9_eoflist (dmc_txc_dma9_eoflist),
1675 .dmc_txc_dma9_error (dmc_txc_dma9_error),
1676 .dmc_txc_dma9_gotnxtdesc (dmc_txc_dma9_gotnxtdesc),
1677 .dmc_txc_dma9_cacheready (dmc_txc_dma9_cacheready),
1678 .dmc_txc_dma9_partial (dmc_txc_dma9_partial),
1679 .dmc_txc_dma9_reset_scheduled (dmc_txc_dma9_reset_scheduled),
1680 .dmc_txc_dma9_page_handle (dmc_txc_dma9_page_handle[19:0]),
1681 .dmc_txc_dma9_descriptor (dmc_txc_dma9_descriptor[63:0]),
1682 .txc_dmc_dma10_getnxtdesc (txc_dmc_dma10_getnxtdesc),
1683 .txc_dmc_dma10_inc_head (txc_dmc_dma10_inc_head),
1684 .txc_dmc_dma10_reset_done (txc_dmc_dma10_reset_done),
1685 .txc_dmc_dma10_mark_bit (txc_dmc_dma10_mark_bit),
1686 .txc_dmc_dma10_inc_pkt_cnt (txc_dmc_dma10_inc_pkt_cnt),
1687 .dmc_txc_dma10_active (dmc_txc_dma10_active),
1688 .dmc_txc_dma10_eoflist (dmc_txc_dma10_eoflist),
1689 .dmc_txc_dma10_error (dmc_txc_dma10_error),
1690 .dmc_txc_dma10_gotnxtdesc (dmc_txc_dma10_gotnxtdesc),
1691 .dmc_txc_dma10_cacheready (dmc_txc_dma10_cacheready),
1692 .dmc_txc_dma10_partial (dmc_txc_dma10_partial),
1693 .dmc_txc_dma10_reset_scheduled (dmc_txc_dma10_reset_scheduled),
1694 .dmc_txc_dma10_page_handle (dmc_txc_dma10_page_handle[19:0]),
1695 .dmc_txc_dma10_descriptor (dmc_txc_dma10_descriptor[63:0]),
1696 .txc_dmc_dma11_getnxtdesc (txc_dmc_dma11_getnxtdesc),
1697 .txc_dmc_dma11_inc_head (txc_dmc_dma11_inc_head),
1698 .txc_dmc_dma11_reset_done (txc_dmc_dma11_reset_done),
1699 .txc_dmc_dma11_mark_bit (txc_dmc_dma11_mark_bit),
1700 .txc_dmc_dma11_inc_pkt_cnt (txc_dmc_dma11_inc_pkt_cnt),
1701 .dmc_txc_dma11_active (dmc_txc_dma11_active),
1702 .dmc_txc_dma11_eoflist (dmc_txc_dma11_eoflist),
1703 .dmc_txc_dma11_error (dmc_txc_dma11_error),
1704 .dmc_txc_dma11_gotnxtdesc (dmc_txc_dma11_gotnxtdesc),
1705 .dmc_txc_dma11_cacheready (dmc_txc_dma11_cacheready),
1706 .dmc_txc_dma11_partial (dmc_txc_dma11_partial),
1707 .dmc_txc_dma11_reset_scheduled (dmc_txc_dma11_reset_scheduled),
1708 .dmc_txc_dma11_page_handle (dmc_txc_dma11_page_handle[19:0]),
1709 .dmc_txc_dma11_descriptor (dmc_txc_dma11_descriptor[63:0]),
1710 .txc_dmc_dma12_getnxtdesc (txc_dmc_dma12_getnxtdesc),
1711 .txc_dmc_dma12_inc_head (txc_dmc_dma12_inc_head),
1712 .txc_dmc_dma12_reset_done (txc_dmc_dma12_reset_done),
1713 .txc_dmc_dma12_mark_bit (txc_dmc_dma12_mark_bit),
1714 .txc_dmc_dma12_inc_pkt_cnt (txc_dmc_dma12_inc_pkt_cnt),
1715 .dmc_txc_dma12_active (dmc_txc_dma12_active),
1716 .dmc_txc_dma12_eoflist (dmc_txc_dma12_eoflist),
1717 .dmc_txc_dma12_error (dmc_txc_dma12_error),
1718 .dmc_txc_dma12_gotnxtdesc (dmc_txc_dma12_gotnxtdesc),
1719 .dmc_txc_dma12_cacheready (dmc_txc_dma12_cacheready),
1720 .dmc_txc_dma12_partial (dmc_txc_dma12_partial),
1721 .dmc_txc_dma12_reset_scheduled (dmc_txc_dma12_reset_scheduled),
1722 .dmc_txc_dma12_page_handle (dmc_txc_dma12_page_handle[19:0]),
1723 .dmc_txc_dma12_descriptor (dmc_txc_dma12_descriptor[63:0]),
1724 .txc_dmc_dma13_getnxtdesc (txc_dmc_dma13_getnxtdesc),
1725 .txc_dmc_dma13_inc_head (txc_dmc_dma13_inc_head),
1726 .txc_dmc_dma13_reset_done (txc_dmc_dma13_reset_done),
1727 .txc_dmc_dma13_mark_bit (txc_dmc_dma13_mark_bit),
1728 .txc_dmc_dma13_inc_pkt_cnt (txc_dmc_dma13_inc_pkt_cnt),
1729 .dmc_txc_dma13_active (dmc_txc_dma13_active),
1730 .dmc_txc_dma13_eoflist (dmc_txc_dma13_eoflist),
1731 .dmc_txc_dma13_error (dmc_txc_dma13_error),
1732 .dmc_txc_dma13_gotnxtdesc (dmc_txc_dma13_gotnxtdesc),
1733 .dmc_txc_dma13_cacheready (dmc_txc_dma13_cacheready),
1734 .dmc_txc_dma13_partial (dmc_txc_dma13_partial),
1735 .dmc_txc_dma13_reset_scheduled (dmc_txc_dma13_reset_scheduled),
1736 .dmc_txc_dma13_page_handle (dmc_txc_dma13_page_handle[19:0]),
1737 .dmc_txc_dma13_descriptor (dmc_txc_dma13_descriptor[63:0]),
1738 .txc_dmc_dma14_getnxtdesc (txc_dmc_dma14_getnxtdesc),
1739 .txc_dmc_dma14_inc_head (txc_dmc_dma14_inc_head),
1740 .txc_dmc_dma14_reset_done (txc_dmc_dma14_reset_done),
1741 .txc_dmc_dma14_mark_bit (txc_dmc_dma14_mark_bit),
1742 .txc_dmc_dma14_inc_pkt_cnt (txc_dmc_dma14_inc_pkt_cnt),
1743 .dmc_txc_dma14_active (dmc_txc_dma14_active),
1744 .dmc_txc_dma14_eoflist (dmc_txc_dma14_eoflist),
1745 .dmc_txc_dma14_error (dmc_txc_dma14_error),
1746 .dmc_txc_dma14_gotnxtdesc (dmc_txc_dma14_gotnxtdesc),
1747 .dmc_txc_dma14_cacheready (dmc_txc_dma14_cacheready),
1748 .dmc_txc_dma14_partial (dmc_txc_dma14_partial),
1749 .dmc_txc_dma14_reset_scheduled (dmc_txc_dma14_reset_scheduled),
1750 .dmc_txc_dma14_page_handle (dmc_txc_dma14_page_handle[19:0]),
1751 .dmc_txc_dma14_descriptor (dmc_txc_dma14_descriptor[63:0]),
1752 .txc_dmc_dma15_getnxtdesc (txc_dmc_dma15_getnxtdesc),
1753 .txc_dmc_dma15_inc_head (txc_dmc_dma15_inc_head),
1754 .txc_dmc_dma15_reset_done (txc_dmc_dma15_reset_done),
1755 .txc_dmc_dma15_mark_bit (txc_dmc_dma15_mark_bit),
1756 .txc_dmc_dma15_inc_pkt_cnt (txc_dmc_dma15_inc_pkt_cnt),
1757 .dmc_txc_dma15_active (dmc_txc_dma15_active),
1758 .dmc_txc_dma15_eoflist (dmc_txc_dma15_eoflist),
1759 .dmc_txc_dma15_error (dmc_txc_dma15_error),
1760 .dmc_txc_dma15_gotnxtdesc (dmc_txc_dma15_gotnxtdesc),
1761 .dmc_txc_dma15_cacheready (dmc_txc_dma15_cacheready),
1762 .dmc_txc_dma15_partial (dmc_txc_dma15_partial),
1763 .dmc_txc_dma15_reset_scheduled (dmc_txc_dma15_reset_scheduled),
1764 .dmc_txc_dma15_page_handle (dmc_txc_dma15_page_handle[19:0]),
1765 .dmc_txc_dma15_descriptor (dmc_txc_dma15_descriptor[63:0]),
1766 .dmc_txc_dma0_func_num (dmc_txc_dma0_func_num[1:0]),
1767 .dmc_txc_dma1_func_num (dmc_txc_dma1_func_num[1:0]),
1768 .dmc_txc_dma2_func_num (dmc_txc_dma2_func_num[1:0]),
1769 .dmc_txc_dma3_func_num (dmc_txc_dma3_func_num[1:0]),
1770 .dmc_txc_dma4_func_num (dmc_txc_dma4_func_num[1:0]),
1771 .dmc_txc_dma5_func_num (dmc_txc_dma5_func_num[1:0]),
1772 .dmc_txc_dma6_func_num (dmc_txc_dma6_func_num[1:0]),
1773 .dmc_txc_dma7_func_num (dmc_txc_dma7_func_num[1:0]),
1774 .dmc_txc_dma8_func_num (dmc_txc_dma8_func_num[1:0]),
1775 .dmc_txc_dma9_func_num (dmc_txc_dma9_func_num[1:0]),
1776 .dmc_txc_dma10_func_num (dmc_txc_dma10_func_num[1:0]),
1777 .dmc_txc_dma11_func_num (dmc_txc_dma11_func_num[1:0]),
1778 .dmc_txc_dma12_func_num (dmc_txc_dma12_func_num[1:0]),
1779 .dmc_txc_dma13_func_num (dmc_txc_dma13_func_num[1:0]),
1780 .dmc_txc_dma14_func_num (dmc_txc_dma14_func_num[1:0]),
1781 .dmc_txc_dma15_func_num (dmc_txc_dma15_func_num[1:0]),
1782 .dmc_txc_tx_addr_md (dmc_txc_tx_addr_md),
1783 .txc_dmc_dma_nack_pkt_rd (txc_dmc_dma_nack_pkt_rd[15:0]),
1784 .txc_dmc_nack_pkt_rd_addr (txc_dmc_nack_pkt_rd_addr[43:0]),
1785 .txc_dmc_nack_pkt_rd (txc_dmc_nack_pkt_rd),
1786 .txc_dmc_p0_dma_pkt_size_err (txc_dmc_p0_dma_pkt_size_err[15:0]),
1787 .txc_dmc_p0_pkt_size_err_addr (txc_dmc_p0_pkt_size_err_addr[43:0]),
1788 .txc_dmc_p0_pkt_size_err (txc_dmc_p0_pkt_size_err),
1789 .txc_dmc_p1_dma_pkt_size_err (txc_dmc_p1_dma_pkt_size_err[15:0]),
1790 .txc_dmc_p1_pkt_size_err_addr (txc_dmc_p1_pkt_size_err_addr[43:0]),
1791 .txc_dmc_p1_pkt_size_err (txc_dmc_p1_pkt_size_err)
1792 );
1793
1794tds_n2_efuhdr2_ctl tdmc_sram_header (
1795 .efu_hdr_write_data (efu_niu_ram_data),
1796 .efu_hdr_xfer_en (efu_niu_ram_xfer_en),
1797 .efu_hdr_clr (efu_niu_ram_clr),
1798 .hdr_efu_read_data (niu_efu_ram_data),
1799 .hdr_efu_xfer_en (niu_efu_ram_xfer_en),
1800 .hdr_sram_rvalue ({unconnected_1[10:7], hdr_sram_rvalue_tdmc[6:0]}),
1801 .hdr_sram_rid ({unconnected_2[10:2], hdr_sram_rid_tdmc[1:0]}),
1802 .hdr_sram_wr_en (hdr_sram_wr_en_tdmc),
1803 .hdr_sram_red_clr (hdr_sram_red_clr_tdmc),
1804 .sram_hdr_read_data ({4'b0, sram_hdr_read_data_tdmc[6:0]}),
1805 .reset_l (niu_reset_l),
1806 .l2clk (l1clk),
1807 .tcu_pce_ov (tds_pce_ov),
1808 .tcu_aclk (aclk),
1809 .tcu_bclk (bclk),
1810 .tcu_scan_en (tcu_scan_en),
1811 .tcu_clk_stop (tcu_tds_io_clk_stop),
1812 .scan_in (io2xclk_scan_out),
1813 .scan_out ()
1814 );
1815
1816dmo_regs dmo_regs (
1817 .niu_clk (l1clk),
1818 .dmo_in (tds_tcu_dmo_data_out[39:0]),
1819 .dmo_out (tds_tcu_dmo_dout[39:0])
1820 );
1821
1822clkgen_tds_io2x clkgen2x_tds (
1823 .l2clk (io2xl2clk),
1824 .aclk (),
1825 .bclk (),
1826 .scan_out (io2xclk_scan_out),
1827 .aclk_wmr (),
1828 .pce_ov (),
1829 .wmr_protect (),
1830 .wmr_ (),
1831 .por_ (),
1832 .cmp_slow_sync_en (),
1833 .slow_cmp_sync_en (),
1834 .array_wr_inhibit (),
1835 .tcu_atpg_mode (tcu_atpg_mode),
1836 .tcu_wr_inhibit (1'b0),
1837 .tcu_clk_stop (tcu_tds_io_clk_stop),
1838 .tcu_pce_ov (tds_pce_ov),
1839 .rst_wmr_protect (1'b0),
1840 .rst_wmr_ (1'b1),
1841 .rst_por_ (rst_por_),
1842 .ccu_cmp_slow_sync_en (1'b0),
1843 .ccu_slow_cmp_sync_en (1'b0),
1844 .tcu_div_bypass (tcu_div_bypass),
1845 .ccu_div_ph (gl_tds_io2x_out),
1846 .cluster_div_en (1'b1),
1847 .gclk (cmp_gclk_c0_tds),
1848 .cluster_arst_l (cluster_arst_l),
1849 .ccu_serdes_dtm (1'b0),
1850 .clk_ext (1'b0),
1851 .scan_en (tcu_scan_en),
1852 .scan_in (ioclk_scan_out),
1853 .tcu_aclk (aclk),
1854 .tcu_bclk (bclk)
1855 );
1856
1857tds_l2l1clk_io clkgen_tds (
1858 .array_wr_inhibit (tds_array_wr_inhibit),
1859 .l1clk (l1clk),
1860 .iol2clk (iol2clk),
1861 .aclk (aclk),
1862 .bclk (bclk),
1863 .scan_out (ioclk_scan_out),
1864 .aclk_wmr (),
1865 .pce_ov (tds_pce_ov),
1866 .wmr_protect (),
1867 .wmr_ (),
1868 .por_ (niu_reset_l),
1869 .cmp_slow_sync_en (),
1870 .slow_cmp_sync_en (),
1871 .tcu_atpg_mode (tcu_atpg_mode),
1872 .tcu_wr_inhibit (tcu_wr_inhibit),
1873 .tcu_clk_stop (tcu_tds_io_clk_stop),
1874 .tcu_pce_ov (tcu_pce_ov),
1875 .rst_wmr_protect (1'b0),
1876 .rst_wmr_ (1'b1),
1877 .rst_por_ (rst_por_),
1878 .tcu_div_bypass (tcu_div_bypass),
1879 .ccu_div_ph (gl_tds_io_out),
1880 .cluster_div_en (1'b1),
1881 .gclk (cmp_gclk_c0_tds),
1882 .cluster_arst_l (cluster_arst_l),
1883 .scan_en (tcu_scan_en),
1884 .scan_in (scan_in),
1885 .tcu_aclk (tcu_aclk),
1886 .tcu_bclk (tcu_bclk)
1887 );
1888// VPERL: GENERATED_END
1889
1890assign meta_dmc_data[127:0] = x_meta1_rdmc_rbr_resp_data[127:0];
1891assign meta_dmc_resp_byteenable[15:0] = x_meta1_rdmc_rbr_resp_byteenable[15:0];
1892assign meta_dmc_resp_cmd[7:0] = x_meta1_rdmc_rbr_resp_cmd[7:0];
1893assign meta_dmc_resp_cmd_status[3:0] = x_meta1_rdmc_rbr_resp_cmd_status[3:0];
1894assign meta_dmc_resp_dma_num[4:0] = x_meta1_rdmc_rbr_resp_dma_num[4:0];
1895assign meta_dmc_resp_ready = x_meta1_rdmc_rbr_resp_ready;
1896
1897assign meta1_rdmc_rbr_resp_data[127:0] = x_meta1_rdmc_rbr_resp_data[127:0];
1898assign meta1_rdmc_rbr_resp_byteenable[15:0] = x_meta1_rdmc_rbr_resp_byteenable[15:0];
1899assign meta1_rdmc_rbr_resp_cmd[7:0] = x_meta1_rdmc_rbr_resp_cmd[7:0];
1900assign meta1_rdmc_rbr_resp_cmd_status[3:0] = x_meta1_rdmc_rbr_resp_cmd_status[3:0];
1901assign meta1_rdmc_rbr_resp_dma_num[4:0] = x_meta1_rdmc_rbr_resp_dma_num[4:0];
1902assign meta1_rdmc_rbr_resp_ready = x_meta1_rdmc_rbr_resp_ready;
1903
1904endmodule
1905
Full OpenSPARC design & verification tarball including full HDL.