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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: tds_l2l1clk_io.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | /////////////////////////////////////////////////////////////////////////////// | |
36 | // tds_l2l1clk_io | |
37 | /////////////////////////////////////////////////////////////////////////////// | |
38 | ||
39 | module tds_l2l1clk_io ( | |
40 | array_wr_inhibit, | |
41 | tcu_atpg_mode, | |
42 | tcu_wr_inhibit, | |
43 | l1clk, | |
44 | iol2clk, | |
45 | aclk, | |
46 | bclk, | |
47 | scan_out, | |
48 | pce_ov, | |
49 | aclk_wmr, | |
50 | wmr_protect, | |
51 | wmr_, | |
52 | por_, | |
53 | cmp_slow_sync_en, | |
54 | slow_cmp_sync_en, | |
55 | tcu_clk_stop, | |
56 | tcu_pce_ov, | |
57 | rst_wmr_protect, | |
58 | rst_wmr_, | |
59 | rst_por_, | |
60 | // ccu_cmp_slow_sync_en, | |
61 | // ccu_slow_cmp_sync_en, | |
62 | tcu_div_bypass, | |
63 | ccu_div_ph, | |
64 | cluster_div_en, | |
65 | gclk, | |
66 | cluster_arst_l, | |
67 | // following two pin remove in I6.1 | |
68 | // clk_ext, | |
69 | // ccu_serdes_dtm, | |
70 | tcu_aclk, | |
71 | tcu_bclk, | |
72 | scan_en, | |
73 | scan_in | |
74 | ); | |
75 | ||
76 | ||
77 | // ************************** | |
78 | // port declaration | |
79 | // ************************** | |
80 | ||
81 | // clock & test out | |
82 | output array_wr_inhibit; | |
83 | output l1clk; // assume we do not need aclk, bclk outputs | |
84 | output iol2clk; // direct clock source to memory | |
85 | output aclk; // buffered version of aclk | |
86 | output bclk; // buffered version of bclk | |
87 | output scan_out; // unused as of today - feb 10, 05 | |
88 | output aclk_wmr; | |
89 | ||
90 | // pipelined out | |
91 | output pce_ov; // pce override to l1 header | |
92 | output wmr_protect; // warm reset protect | |
93 | output wmr_; // warm reset (active low) | |
94 | output por_; // power-on-reset | |
95 | output cmp_slow_sync_en; // cmp->slow clk sync pulse | |
96 | output slow_cmp_sync_en; // slow->cmp clk sync pulse | |
97 | ||
98 | // ctrl in (for pipelining) | |
99 | input tcu_atpg_mode; | |
100 | input tcu_wr_inhibit; | |
101 | input tcu_clk_stop; | |
102 | input tcu_pce_ov; | |
103 | input rst_wmr_protect; | |
104 | input rst_wmr_; | |
105 | input rst_por_; | |
106 | // input ccu_cmp_slow_sync_en; | |
107 | // input ccu_slow_cmp_sync_en; | |
108 | ||
109 | // ctrl in (for clock gen) | |
110 | input tcu_div_bypass; // bypasses clk divider to mux in ext clk | |
111 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) | |
112 | input cluster_div_en; // if enabled, l2clk is divided down | |
113 | ||
114 | // clock & test in | |
115 | input gclk; // global clk - this is either cmp or dr | |
116 | input cluster_arst_l; | |
117 | // input ccu_serdes_dtm; | |
118 | // input clk_ext; // external clk muxed in for ioclk bypass | |
119 | input scan_en; // unused as of today - feb 10, 05 | |
120 | input scan_in; // unused as of today - feb 10, 05 | |
121 | input tcu_aclk; | |
122 | input tcu_bclk; | |
123 | ||
124 | ||
125 | // ************************** | |
126 | // wire declaration | |
127 | // ************************** | |
128 | // wire l2clk; | |
129 | wire array_wr_inhibit; | |
130 | wire tcu_atpg_mode; | |
131 | wire tcu_wr_inhibit; | |
132 | wire iol2clk; | |
133 | wire aclk; | |
134 | wire bclk; | |
135 | wire scan_out; | |
136 | wire aclk_wmr; | |
137 | wire pce_ov; | |
138 | wire wmr_protect; | |
139 | wire wmr_; | |
140 | wire por_; | |
141 | wire cmp_slow_sync_en; | |
142 | wire slow_cmp_sync_en; | |
143 | wire tcu_clk_stop; | |
144 | wire tcu_pce_ov; | |
145 | wire rst_wmr_protect; | |
146 | wire rst_wmr_; | |
147 | wire rst_por_; | |
148 | // wire ccu_cmp_slow_sync_en; | |
149 | // wire ccu_slow_cmp_sync_en; | |
150 | wire tcu_div_bypass; | |
151 | wire ccu_div_ph; | |
152 | wire cluster_div_en; | |
153 | wire gclk; | |
154 | wire cluster_arst_l; | |
155 | // remove in I6.1 | |
156 | // wire clk_ext; | |
157 | // wire ccu_serdes_dtm; | |
158 | wire scan_en; | |
159 | wire scan_in; | |
160 | wire tcu_aclk; | |
161 | wire tcu_bclk; | |
162 | ||
163 | // ************************** | |
164 | // instantiations | |
165 | // ************************** | |
166 | clkgen_tds_io clkgen_tds_io ( | |
167 | .array_wr_inhibit(array_wr_inhibit), | |
168 | .tcu_atpg_mode(tcu_atpg_mode), | |
169 | .tcu_wr_inhibit(tcu_wr_inhibit), | |
170 | .l2clk(iol2clk), | |
171 | .aclk(aclk), | |
172 | .bclk(bclk), | |
173 | .scan_out(scan_out), | |
174 | .pce_ov(pce_ov), | |
175 | .aclk_wmr(aclk_wmr), | |
176 | .wmr_protect(wmr_protect), | |
177 | .wmr_(wmr_), | |
178 | .por_(por_), | |
179 | .cmp_slow_sync_en(cmp_slow_sync_en), | |
180 | .slow_cmp_sync_en(slow_cmp_sync_en), | |
181 | .tcu_clk_stop(tcu_clk_stop), | |
182 | .tcu_pce_ov(tcu_pce_ov), | |
183 | .rst_wmr_protect(rst_wmr_protect), | |
184 | .rst_wmr_(rst_wmr_), | |
185 | .rst_por_(rst_por_), | |
186 | // This pin will ground internal in the I5.3 release | |
187 | .ccu_cmp_slow_sync_en(1'b0), | |
188 | .ccu_slow_cmp_sync_en(1'b0), | |
189 | .tcu_div_bypass(tcu_div_bypass), | |
190 | .ccu_div_ph(ccu_div_ph), | |
191 | .cluster_div_en(cluster_div_en), | |
192 | .gclk(gclk), | |
193 | .cluster_arst_l(cluster_arst_l), | |
194 | // following two pins remove in I6.1 | |
195 | // .clk_ext(clk_ext), | |
196 | // .ccu_serdes_dtm(ccu_serdes_dtm), | |
197 | .tcu_aclk(tcu_aclk), | |
198 | .tcu_bclk(tcu_bclk), | |
199 | .scan_en(scan_en), | |
200 | .scan_in(scan_in) ); | |
201 | ||
202 | ||
203 | cl_a1_l1hdr_8x tds_l1clk_1 ( .l2clk(iol2clk), .se(scan_en), .pce(1'b1), | |
204 | .pce_ov(pce_ov), .stop(1'b0), .l1clk(l1clk) ); | |
205 | ||
206 | ||
207 | endmodule | |
208 |