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1 | # ========== Copyright Header Begin ========================================== |
2 | # | |
3 | # OpenSPARC T2 Processor File: run.scr | |
4 | # Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | # 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | # | |
7 | # * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | # | |
9 | # This program is free software; you can redistribute it and/or modify | |
10 | # it under the terms of the GNU General Public License as published by | |
11 | # the Free Software Foundation; version 2 of the License. | |
12 | # | |
13 | # This program is distributed in the hope that it will be useful, | |
14 | # but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | # MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | # GNU General Public License for more details. | |
17 | # | |
18 | # You should have received a copy of the GNU General Public License | |
19 | # along with this program; if not, write to the Free Software | |
20 | # Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | # | |
22 | # For the avoidance of doubt, and except that if any non-GPL license | |
23 | # choice is available it will apply instead, Sun elects to use only | |
24 | # the General Public License version 2 (GPLv2) at this time for any | |
25 | # software where a choice of GPL license versions is made | |
26 | # available with the language indicating that GPLv2 or any later version | |
27 | # may be used, or where a choice of which version of the GPL is applied is | |
28 | # otherwise unspecified. | |
29 | # | |
30 | # Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | # CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | # have any questions. | |
33 | # | |
34 | # ========== Copyright Header End ============================================ | |
35 | sh date | |
36 | sh hostname | |
37 | sh uptime | |
38 | ||
39 | remove_design -all | |
40 | ||
41 | if {[file exists template]} { | |
42 | sh rm -rf template | |
43 | } | |
44 | sh mkdir template | |
45 | if {![file exists gate]} { | |
46 | sh mkdir gate | |
47 | } | |
48 | if {![file exists log]} { | |
49 | sh mkdir log | |
50 | } | |
51 | ||
52 | ########################################################################### | |
53 | # 1. Setup from environment variables | |
54 | ########################################################################### | |
55 | ||
56 | set dv_root [sh echo \$DV_ROOT] | |
57 | set syn_home [sh echo \$SYN_LIB] | |
58 | ||
59 | source -echo -verbose script/user_cfg.scr | |
60 | ||
61 | set search_path [concat $search_path script/] | |
62 | ||
63 | set search_path [concat $syn_home \ | |
64 | $search_path ] | |
65 | ||
66 | foreach include_path $include_paths { | |
67 | set search_path [concat $search_path $dv_root/$include_path] | |
68 | } | |
69 | ||
70 | sh date | |
71 | ||
72 | set link_library [concat $link_library \ | |
73 | $mem_libs \ | |
74 | $black_box_designs] | |
75 | ||
76 | set target_library $syn_home/lsi_10k.db | |
77 | ||
78 | set target_library [concat $target_library \ | |
79 | $mem_libs] | |
80 | set hdlin_enable_vpp true | |
81 | set hdlin_auto_save_templates false | |
82 | define_design_lib WORK -path .template | |
83 | set verilogout_single_bit false | |
84 | set hdlout_internal_busses true | |
85 | set bus_naming_style {%s[%d]} | |
86 | set bus_inference_style $bus_naming_style | |
87 | ||
88 | echo $search_path | |
89 | ||
90 | ||
91 | ########################################################################### | |
92 | # 2. Read Designs | |
93 | ########################################################################### | |
94 | ||
95 | set all_rtl_files { } | |
96 | foreach rtl_file $rtl_files { | |
97 | set full_file_path $dv_root/$rtl_file | |
98 | set all_rtl_files [concat $all_rtl_files $full_file_path ] | |
99 | } | |
100 | ||
101 | analyze -format verilog -define RUNDC $all_rtl_files | |
102 | elaborate $top_module | |
103 | ||
104 | ##### | |
105 | ||
106 | if {[info exists mix_files] && ($mix_files != {}) } { | |
107 | foreach mix_file $mix_files { | |
108 | set index_beg [expr {[string last "/" $mix_file] + 1}] | |
109 | set mix_file_name [string range $mix_file $index_beg end] | |
110 | read_file -format verilog -define RUNDC gate/${mix_file_name}.exp | |
111 | } | |
112 | } | |
113 | set design_list [list] | |
114 | foreach_in_collection design_object [get_designs] { | |
115 | set design_name [get_object_name $design_object] | |
116 | lappend design_list $design_name | |
117 | } | |
118 | sh date | |
119 | current_design $top_module | |
120 | ||
121 | echo $top_module | |
122 | ||
123 | if {[get_designs -hier $dont_touch_modules] != {}} { | |
124 | set_dont_touch $dont_touch_modules | |
125 | } | |
126 | ||
127 | set dc_shell_status [ link ] | |
128 | if {$dc_shell_status == 0} { | |
129 | echo "****************************************************" | |
130 | echo "* ERROR!!!! Failed to Link...exiting prematurely. *" | |
131 | echo "****************************************************" | |
132 | quit | |
133 | } | |
134 | ||
135 | ########################################################################### | |
136 | # 3. Set up design constraints | |
137 | ########################################################################### | |
138 | ||
139 | current_design $top_module | |
140 | echo $top_module | |
141 | set clk_name_list [list] | |
142 | set ideal_inputs [list] | |
143 | foreach clk_spec $clk_list { | |
144 | set listcnt 0 | |
145 | set clk_port_pin {} | |
146 | set clk_name {} | |
147 | set clk_freq 0.0 | |
148 | set setup_skew $default_setup_skew | |
149 | set hold_skew $default_hold_skew | |
150 | set clock_transition $default_clk_transition | |
151 | set clk_is_port 1 | |
152 | foreach element $clk_spec { | |
153 | if {$listcnt == 0} { | |
154 | set clk_port_pin $element | |
155 | set clk_name $element | |
156 | } | |
157 | if {$listcnt == 1} { | |
158 | set clk_freq $element | |
159 | } | |
160 | if {$listcnt == 2} { | |
161 | set setup_skew $element | |
162 | } | |
163 | if {$listcnt == 3} { | |
164 | set hold_skew $element | |
165 | } | |
166 | if {$listcnt == 4} { | |
167 | set clock_transition $element | |
168 | } | |
169 | if {$listcnt == 5} { | |
170 | set clk_name $element | |
171 | set clk_is_port 0 | |
172 | } | |
173 | set listcnt [expr $listcnt + 1] | |
174 | } | |
175 | if {$clk_is_port == 1} { | |
176 | set clk_exists [sizeof_collection [find port $clk_port_pin]] | |
177 | } else { | |
178 | set clk_exists [sizeof_collection [find pin $clk_port_pin]] | |
179 | } | |
180 | if {$clk_exists != 0} { | |
181 | set clk_period [expr 1000.0 / $clk_freq / 1.0] | |
182 | set high_time [expr $clk_period / 2.0] | |
183 | create_clock $clk_port_pin -period $clk_period -waveform [list 0 $high_time] -name $clk_name | |
184 | set_clock_uncertainty -setup $setup_skew [find clock $clk_name] | |
185 | set_clock_uncertainty -hold $hold_skew [find clock $clk_name] | |
186 | set_clock_transition $clock_transition [find clock $clk_name] | |
187 | set_dont_touch_network $clk_name | |
188 | if {$clk_is_port == 1} { | |
189 | set_drive 0.0 $clk_name | |
190 | lappend ideal_inputs $clk_name | |
191 | } | |
192 | set clk_name_list [concat $clk_name_list $clk_name] | |
193 | } | |
194 | } | |
195 | if {$clk_name_list == {} } { | |
196 | echo "\[WARNING\] No clock is defined,create a virtual one -- $default_clk..." | |
197 | set clk_name $default_clk | |
198 | set clk_freq $default_clk_freq | |
199 | set clk_period [expr 1000.0 / $clk_freq / 1.0] | |
200 | set high_time [expr $clk_period / 2.0] | |
201 | set setup_skew $default_setup_skew | |
202 | set hold_skew $default_hold_skew | |
203 | set clock_transition $default_clk_transition | |
204 | create_clock -name $clk_name -period $clk_period -waveform [list 0 $high_time] | |
205 | set_clock_uncertainty -setup $setup_skew $clk_name | |
206 | set_clock_uncertainty -hold $hold_skew $clk_name | |
207 | } | |
208 | set non_ideal_inputs [list] | |
209 | foreach_in_collection input_object [all_inputs] { | |
210 | set input_name [get_object_name $input_object] | |
211 | set input_is_ideal [lsearch -exact $ideal_net_list $input_name] | |
212 | if {$input_is_ideal == -1} { | |
213 | lappend non_ideal_inputs $input_name | |
214 | } else { | |
215 | lappend ideal_inputs $input_name | |
216 | } | |
217 | } | |
218 | ||
219 | echo $ideal_inputs | |
220 | echo $non_ideal_inputs | |
221 | ||
222 | set_input_delay $default_input_delay -clock $clk_name $non_ideal_inputs | |
223 | set_output_delay $default_output_delay -clock $clk_name [all_outputs] | |
224 | ||
225 | if {$clk_name_list != {} } { | |
226 | group_path -name "reg2reg" -critical_range $critical_range -from [ all_registers -clock_pins ] -to [ all_registers -data_pins ] | |
227 | group_path -name "in2reg" -from $non_ideal_inputs -to [ all_registers -data_pins ] | |
228 | group_path -name "reg2out" -from [ all_registers -clock_pins ] -to [all_outputs] | |
229 | } | |
230 | group_path -name "in2out" -from $non_ideal_inputs -to [all_outputs] | |
231 | if {[info exists false_path_list] && ($false_path_list != {}) } { | |
232 | set_false_path -through $false_path_list | |
233 | } | |
234 | ||
235 | if {[info exists enforce_input_fanout_one] && ($enforce_input_fanout_one == 1)} { | |
236 | set_max_fanout 1 $non_ideal_inputs | |
237 | } | |
238 | ||
239 | # Load custom constraint file for the unit | |
240 | # This will overwrite the default constraints | |
241 | ||
242 | ||
243 | ########################################################################### | |
244 | # 4. More constraints and setup before compile | |
245 | ########################################################################### | |
246 | # This is to prevent assign statements from generated in the netlist | |
247 | # Certain rtl coding conventions need to be followed. For IO blocks only | |
248 | # write_name_nets_same_as_ports | |
249 | if {[info exists project_io_cfg] && ($project_io_cfg == 1) } { | |
250 | foreach_in_collection design [ get_designs "*" ] { | |
251 | current_design $design | |
252 | set_fix_multiple_port_nets -outputs -feedthroughs | |
253 | } | |
254 | current_design $top_module | |
255 | } | |
256 | ||
257 | # Check timing constraints | |
258 | ||
259 | ||
260 | ########################################################################### | |
261 | # 5. Compile | |
262 | ########################################################################### | |
263 | ||
264 | # Disable cells that we don't want to use in the library | |
265 | if {$dont_use_cells != 0} { | |
266 | if {[info exists my_dont_use_cell_list] && ($my_dont_use_cell_list != {}) } { | |
267 | set dont_use_cell_list [concat $dont_use_cell_list $my_dont_use_cell_list] | |
268 | } | |
269 | foreach dont_use_cell $dont_use_cell_list { | |
270 | set_dont_use [find lib_cell $dont_use_cell] | |
271 | } | |
272 | } | |
273 | ||
274 | sh date | |
275 | sh uptime | |
276 | ||
277 | # Don't remove sequential cells with constant outputs | |
278 | set compile_seqmap_propagate_constants false | |
279 | ||
280 | # Switch off the dont_touch attribute globally for set_size_only cells | |
281 | set dont_touch_nets_with_size_only_cells false | |
282 | ||
283 | ## Source user compile options | |
284 | ||
285 | #if set to 1, the whole design will be flattened. default 1 for cmp | |
286 | if {[info exists compile_flatten_all] && ($compile_flatten_all == 1)} { | |
287 | ungroup -flatten -all | |
288 | } | |
289 | ||
290 | # compile !! | |
291 | if {[info exists project_io_cfg] && ($project_io_cfg == 1) } { | |
292 | set dc_shell_status [ compile -boundary_optimization -exact_map -map_effort $compile_effort ] | |
293 | } | |
294 | ||
295 | if {[info exists project_sparc_cfg] && ($project_sparc_cfg == 1) } { | |
296 | if {[info exists use_physopt] && ($use_physopt == 1)} { | |
297 | set_fix_multiple_port_nets -all -buffer_constants | |
298 | } | |
299 | set dc_shell_status [ compile -boundary_optimization -exact_map -map_effort $compile_effort ] | |
300 | } | |
301 | ||
302 | if {$dc_shell_status == 0} { | |
303 | echo "*******************************************************" | |
304 | echo "* ERROR!!!! Failed to compile...exiting prematurely. *" | |
305 | echo "*******************************************************" | |
306 | quit | |
307 | } | |
308 | ||
309 | sh date | |
310 | ||
311 | ########################################################################### | |
312 | # 6. Insert Scan - Hook up the scan chain. | |
313 | ########################################################################### | |
314 | if {[info exists use_physopt] && ($use_physopt == 1)} { | |
315 | set skip_scan 1 | |
316 | } | |
317 | if {[info exists skip_scan] && ($skip_scan == 1)} { | |
318 | ###### skip section 5e. | |
319 | } else { | |
320 | ||
321 | current_design $top_module | |
322 | ||
323 | ## Tell DC the design is "scan ready" | |
324 | ## We do this because we already instantiate scan flops in the rtl | |
325 | set_attribute $top_module is_test_ready true -type boolean | |
326 | foreach_in_collection design_object [get_designs] { | |
327 | current_design $design_object | |
328 | # make sure the module has FFs in it to prevent warning messages | |
329 | if { [all_registers] != {} } { | |
330 | set_attribute [all_registers] scanned_by_test_compiler true -type boolean | |
331 | } | |
332 | } | |
333 | ||
334 | current_design $top_module | |
335 | ||
336 | ||
337 | # Tell DC not to optimize away spare FF's | |
338 | set compile_delete_unloaded_sequential_cells false | |
339 | ||
340 | # Disable cells that we don't want to use in the library | |
341 | if {$dont_use_cells != 0} { | |
342 | foreach dont_use_cell $dont_use_cell_list { | |
343 | set_dont_use [find lib_cell $dont_use_cell] | |
344 | } | |
345 | } | |
346 | ||
347 | # Insert scan chain with number of chains specified by user | |
348 | # Allow scan chain to hook up flops clocked by different clocks | |
349 | # Add lockup latches between clock domains | |
350 | set_scan_configuration -add_lockup $add_lockup_latch -chain_count $chain_count -clock_mixing mix_clocks | |
351 | ||
352 | # This should prevent assign statements from generated in the netlist | |
353 | # at the cost of extra compile time. For cmp only | |
354 | if {[info exists project_sparc_cfg] && ($project_sparc_cfg == 1) } { | |
355 | foreach_in_collection design [ get_designs "*" ] { | |
356 | current_design $design | |
357 | set_fix_multiple_port_nets -all -buffer_constants | |
358 | } | |
359 | ||
360 | current_design $top_module | |
361 | ||
362 | # allow_outport_drive_innodes is used by sparc units but not IO units | |
363 | # set this switch to 0 to make sure output port doesn't driving internal nodes | |
364 | if {[info exists allow_outport_drive_innodes] && ($allow_outport_drive_innodes == 0)} { | |
365 | set_isolate_ports -type inverter [all_outputs] | |
366 | } | |
367 | ||
368 | current_design $top_module | |
369 | compile -inc | |
370 | } | |
371 | ||
372 | ||
373 | ### section 5e. will be skipped if user want to use PC flow | |
374 | } | |
375 | ||
376 | ||
377 | ########################################################################### | |
378 | # 7. Write Out netlist | |
379 | ########################################################################### | |
380 | ||
381 | # Remove don't touch modules from the design | |
382 | # It caused unmatching hierarchy between rtl and netlist | |
383 | if { [get_designs -hier $dont_touch_modules] != {} } { | |
384 | remove_design $dont_touch_modules | |
385 | } | |
386 | ||
387 | # remove dont_touch attribute before flattening the design | |
388 | if { [get_designs -hier $dont_touch_modules] != {} } { | |
389 | set_dont_touch $dont_touch_modules false | |
390 | } | |
391 | ||
392 | current_design $top_module | |
393 | ungroup -all -flatten | |
394 | ||
395 | # Make sure flat netlist does not have "/" in signal names | |
396 | define_name_rules hier_change -restricted "/" -replacement_char "_" | |
397 | change_names -rule hier_change -hierarchy | |
398 | ||
399 | # Write out netlist. | |
400 | write -format verilog -output [format "%s%s%s" gate/ $top_module .vSyn] | |
401 | ||
402 | # Report flattened results | |
403 | redirect [format "%s%s%s" log/ $top_module _area.rep] { report_area } | |
404 | redirect -append [format "%s%s%s" log/ $top_module _area.rep] { report_reference } | |
405 | ||
406 | ||
407 | ########################################################################### | |
408 | # 8. Check design and Detect unmapped design | |
409 | ########################################################################### | |
410 | ||
411 | set unmapped_designs [get_designs -filter "is_unmapped == true" $top_module] | |
412 | ||
413 | if { [sizeof_collection $unmapped_designs] != 0 } { | |
414 | echo "****************************************************" | |
415 | echo "* ERROR!!!! Compile finished with unmapped logic. *" | |
416 | echo "****************************************************" | |
417 | quit | |
418 | } | |
419 | ||
420 | ||
421 | ########################################################################### | |
422 | # 9. Done | |
423 | ########################################################################### | |
424 | sh date | |
425 | ||
426 | echo "run.scr completed successfully" | |
427 | ||
428 | quit |