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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_core_pll_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | // ------------------------------------------------------------------ | |
36 | // Tuesday Sep 20,2005 at 06:09:15 PM PDT | |
37 | // | |
38 | // Directory: /import/n2-emir5/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_cust/netlists | |
39 | // /import/datools/release/tools/sno,1.2.10 \ | |
40 | // -CELL n2_core_pll_cust \ | |
41 | // -LIB n2_core_pll_cust_l \ | |
42 | // -NOSPECIALVDDOVSSO \ | |
43 | // -VERILOGLIBS \ | |
44 | // -AUDITFILE /import/n2-emir5/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_cust/verification/audit/n2_core_pll_cust.sno.audit | |
45 | // ------------------------------------------------------------------ | |
46 | ||
47 | ||
48 | // | |
49 | // some preprocessors imported from rtl for convenience - mh157021 | |
50 | // | |
51 | ||
52 | // define clock stretch amount | |
53 | `define PLL_BASE_STR_AMT 40 | |
54 | ||
55 | // enable for pll to track feedback | |
56 | // ***WARNING!!!!*** Make sure timescale is set to 1 xs / 1xs | |
57 | // ***WARNING!!!!*** The feedback tracking mechanism relies on quantization | |
58 | // ***WARNING!!!!*** to perform correction. Otherwise set FDBK_TRACKING to off | |
59 | // `define FDBK_TRACKING | |
60 | // `timescale 1 ps / 1 ps | |
61 | ||
62 | // pll phase debug option | |
63 | // `ifdef PLL_PH_DEBUG | |
64 | ||
65 | `define PLL_LOCK_CNT 3'b011 | |
66 | ||
67 | // needed to use normal cl_u1 library elements | |
68 | `define LIB | |
69 | ||
70 | ||
71 | // ================================================================== | |
72 | // mh157021: PLL TOP LEVEL MODULE DEFINITION | |
73 | // ================================================================== | |
74 | ||
75 | ||
76 | // | |
77 | // Last Modified: Thursday Sep 1,2005 at 10:28:18 AM PDT | |
78 | // | |
79 | ||
80 | // module n2_core_pll_cust(sel_l2clk_fbk ,dr_stretch_a ,pll_clk_out_l , | |
81 | // dr_clk_out_l ,pll_clamp_fltr ,dr_ext_clk ,ccu_serdes_dtm , | |
82 | // pll_char_out ,pll_sys_clk ,dr_sel_a ,pll_ext_clk ,vreg_selbg_l , | |
83 | // dr_sdel ,pll_clk_out ,l2clk ,pll_sdel ,dft_rst_a_l ,pll_char_in , | |
84 | // pll_arst_l ,vdd_hv15 ,dr_clk_out ,pll_stretch_a ,pll_sel_a , | |
85 | // pll_div4 ,pll_bypass ,pll_div3 ,pll_div1 ,pll_div2 , | |
86 | // ccu_rst_ref_buf2 ,ccu_rst_sys_clk ,pll_testmode ); | |
87 | // output [1:0] pll_char_out ; | |
88 | // input [1:0] pll_sys_clk ; | |
89 | // input [1:0] dr_sel_a ; | |
90 | // input [1:0] dr_sdel ; | |
91 | // input [1:0] pll_sdel ; | |
92 | // input [1:0] pll_sel_a ; | |
93 | // input [6:0] pll_div4 ; | |
94 | // input [5:0] pll_div3 ; | |
95 | // input [5:0] pll_div1 ; | |
96 | // input [5:0] pll_div2 ; | |
97 | // output pll_clk_out_l ; | |
98 | // output dr_clk_out_l ; | |
99 | // output pll_clk_out ; | |
100 | // output dr_clk_out ; | |
101 | // output ccu_rst_ref_buf2 ; | |
102 | // output ccu_rst_sys_clk ; | |
103 | // input sel_l2clk_fbk ; | |
104 | // input dr_stretch_a ; | |
105 | // input pll_clamp_fltr ; | |
106 | // input dr_ext_clk ; | |
107 | // input ccu_serdes_dtm ; | |
108 | // input pll_ext_clk ; | |
109 | // input vreg_selbg_l ; | |
110 | // input l2clk ; | |
111 | // input dft_rst_a_l ; | |
112 | // input pll_char_in ; | |
113 | // input pll_arst_l ; | |
114 | // input vdd_hv15 ; | |
115 | // input pll_stretch_a ; | |
116 | // input pll_bypass ; | |
117 | // input pll_testmode ; | |
118 | // supply1 vdd ; | |
119 | // wire vss = 1'b0; | |
120 | // | |
121 | // wire [9:0] net0210 ; | |
122 | // wire pll_jtag_lock_everlose ; | |
123 | // wire fast_l ; | |
124 | // wire ref_ck ; | |
125 | // wire l1clk_buf ; | |
126 | // wire net0189 ; | |
127 | // wire fast_buf ; | |
128 | // wire vco2_clk ; | |
129 | // wire slow_buf ; | |
130 | // wire vdd_reg ; | |
131 | // wire ref ; | |
132 | // wire pll_lock_pulse ; | |
133 | // wire pfd_reset ; | |
134 | // wire pll_lock_dyn ; | |
135 | // wire vco8_clk ; | |
136 | // wire net0131 ; | |
137 | // wire net0132 ; | |
138 | // wire bypass_clk ; | |
139 | // wire net0136 ; | |
140 | // wire slow ; | |
141 | // wire fb ; | |
142 | // wire net0144 ; | |
143 | // wire fast ; | |
144 | // wire net159 ; | |
145 | // wire fb_ck ; | |
146 | // wire net163 ; | |
147 | // wire div_ck3 ; | |
148 | // wire vco_clk ; | |
149 | // wire dr_clk ; | |
150 | // wire fltr ; | |
151 | // wire slow_l ; | |
152 | // wire vco_out ; | |
153 | // wire net0172 ; | |
154 | // | |
155 | // n2_core_pll_inv_32x_cust pll_clk_inv_inst ( // missing instance - mh157021 | |
156 | // .vdd_reg (vdd ), | |
157 | // .out (pll_clk_out_l ), | |
158 | // .in (net0144) ); | |
159 | // n2_core_pll_inv_32x_cust dr_clk_inv_inst ( // missing instance - mh157021 | |
160 | // .vdd_reg (vdd ), | |
161 | // .out (dr_clk_out_l ), | |
162 | // .in (dr_clk) ); | |
163 | // n2_core_pll_vco_sum_cust x2 ( | |
164 | // .cktree_drv (vco_out ), | |
165 | // .vco_clk (vco_clk ), | |
166 | // .vdd_reg (vdd_reg ), | |
167 | // .vco_out (vco_out ), | |
168 | // .slow (slow ), | |
169 | // .slow_l (slow_l ), | |
170 | // .fast (fast ), | |
171 | // .fltr (fltr ), | |
172 | // .fast_l (fast_l ) ); | |
173 | // n2_core_pll_vdd_xing_buf_4x_cust x3 ( | |
174 | // .vdd_reg (vdd_reg ), | |
175 | // .out (net0172 ), | |
176 | // .in (pll_clamp_fltr ) ); | |
177 | // n2_core_pll_m1_cust x4 ( | |
178 | // .vdd_reg (vdd_reg ) ); | |
179 | // n2_core_pll_inv_100x_cust x5 ( | |
180 | // .vdd_reg (vdd ), | |
181 | // .out (dr_clk_out ), | |
182 | // .in (net0131 ) ); | |
183 | // n2_core_pll_tpm3_all_cust x6 ( | |
184 | // .pll_div3 ({pll_div3 } ), | |
185 | // .pll_sdel ({pll_sdel } ), | |
186 | // .pll_sel_a ({pll_sel_a } ), | |
187 | // .dr_sdel ({dr_sdel } ), | |
188 | // .dr_sel_a ({dr_sel_a } ), | |
189 | // .pll_div4 ({pll_div4 } ), | |
190 | // .pll_stretch_a (pll_stretch_a ), | |
191 | // .ccu_serdes_dtm (ccu_serdes_dtm ), | |
192 | // .dr_ext_clk (dr_ext_clk ), | |
193 | // .volb (~vco_out ), | |
194 | // .pll_clk_out_l (net0132 ), | |
195 | // .pll_bypass_clk_en (pll_bypass ), | |
196 | // .pll_arst_l (timed_pll_arst_l), // worked around non-deterministic reset - mh157021 | |
197 | // .dr_clk_out (dr_clk ), | |
198 | // .pll_bypass_clk (bypass_clk ), | |
199 | // .pll_clk_out (net0144 ), | |
200 | // .dr_clk_out_l (net0131 ), | |
201 | // .dr_stretch_a (dr_stretch_a ), | |
202 | // .pll_testmode (pll_testmode ), | |
203 | // .dc_clk (dc_clk), // unused -same polarity as volb | |
204 | // .vco8_clk (vco8_clk ), | |
205 | // .vco2_clk (vco2_clk ), | |
206 | // .pll_ext_clk (pll_ext_clk ), | |
207 | // .dft_rst_a_l (dft_rst_a_l ) ); | |
208 | // n2_vreg_cust x7 ( | |
209 | // .i50n ({net0210[0] ,net0210[1] ,net0210[2] ,net0210[3] , | |
210 | // net0210[4] ,net0210[5] ,net0210[6] ,net0210[7] ,net0210[8] , | |
211 | // net0210[9] } ), | |
212 | // .v1p1reg_lowv (vdd_reg ), | |
213 | // .vdd_hv15 (vdd_hv15 ), | |
214 | // .vref (net0189 ), | |
215 | // .vrefb (net0136 ), | |
216 | // .selbg_l (vreg_selbg_l ) ); | |
217 | // n2_core_pll_inv_1x_cust x8 ( | |
218 | // .vdd_reg (vdd ), | |
219 | // .out (net163 ), | |
220 | // .in (pll_arst_l ) ); | |
221 | // n2_core_pll_vdd_xing_buf_4x_cust x9 ( | |
222 | // .vdd_reg (vdd_reg ), | |
223 | // .out (net159 ), | |
224 | // .in (net163 ) ); | |
225 | // n2_core_pll_charc_cust xcharc ( | |
226 | // .pll_charc_out ({pll_char_out } ), | |
227 | // .arst_l (pll_arst_l ), | |
228 | // .testmode (pll_testmode ), | |
229 | // .dr_clk_out (dr_clk ), | |
230 | // .ccu_rst_ref_buf2 (ccu_rst_ref_buf2 ), | |
231 | // .ccu_rst_sys_clk (ccu_rst_sys_clk ), | |
232 | // .lock (pll_lock_dyn ), | |
233 | // .fb_clk_l (fb_ck ), | |
234 | // .pll_charc_in (pll_char_in ), | |
235 | // .ref_clk_l (ref_ck ), | |
236 | // .fast (fast_buf ), | |
237 | // .slow (slow_buf ), | |
238 | // .ref (ref ), | |
239 | // .fb (fb ), | |
240 | // .vco_clk (vco8_clk ), | |
241 | // .l1clk (l1clk_buf ) ); | |
242 | // n2_core_pll_inv_100x_cust x10 ( | |
243 | // .vdd_reg (vdd ), | |
244 | // .out (pll_clk_out ), | |
245 | // .in (net0132 ) ); | |
246 | // n2_core_pll_pad_cluster_cust x11 ( | |
247 | // .pll_sys_clk ({pll_sys_clk } ), | |
248 | // .vdd_hv15 (vdd_hv15 ) ); | |
249 | // n2_core_pll_vrr_cust x0 ( | |
250 | // .vdd_reg (vdd_reg ), | |
251 | // .fltr_nw (fltr ), | |
252 | // .reset (net159 ), | |
253 | // .fb (fb ), | |
254 | // .div8 (vdd_reg ), | |
255 | // .div4 (vdd_reg ), | |
256 | // .div_ck (ref ), | |
257 | // .vrr_disbl (vss ), | |
258 | // .clamp_fltr (net0172 ), | |
259 | // .pfd_reset (pfd_reset ) ); | |
260 | // n2_core_pll_pecl_all_cust x1 ( | |
261 | // .pll_div1 ({pll_div1 } ), | |
262 | // .pll_div2 ({pll_div2 } ), | |
263 | // .pll_sys_clk ({pll_sys_clk } ), | |
264 | // .regdivcr (div_ck3 ), | |
265 | // .ref_ck (ref_ck ), | |
266 | // .slow_l (slow_l ), | |
267 | // .fast (fast ), | |
268 | // .fast_l (fast_l ), | |
269 | // .pll_clamp_fltr (net0172 ), | |
270 | // .pll_lock_pulse (pll_lock_pulse ), | |
271 | // .vdd_reg (vdd_reg ), | |
272 | // .fb_ck (fb_ck ), | |
273 | // .l2clk (l2clk ), | |
274 | // .slow (slow ), | |
275 | // .slow_buf (slow_buf ), | |
276 | // .pll_jtag_lock_everlose (pll_jtag_lock_everlose ), | |
277 | // .pll_lock_dyn (pll_lock_dyn ), | |
278 | // .raw_clk_byp (bypass_clk ), | |
279 | // .fast_buf (fast_buf ), | |
280 | // .l2clkc (vco2_clk ), | |
281 | // .testmode (sel_l2clk_fbk ), | |
282 | // .pll_arst_l (pll_arst_l ), | |
283 | // .pll_bypass_clk_en (pll_bypass), // missing connectivity - mh157021 | |
284 | // .ref (ref ), | |
285 | // .fb (fb ), | |
286 | // .l1clk_buf (l1clk_buf ), | |
287 | // .pfd_reset (pfd_reset ), | |
288 | // .fltr (fltr ) ); | |
289 | // imaginary_timed_rst imaginary_timed_rst ( // added timed reset to resolve d3 reset issue - mh157021 | |
290 | // .ref (ref), | |
291 | // .vco_clk (vco_clk), | |
292 | // .pll_arst_l (pll_arst_l), | |
293 | // .pll_div2 (pll_div2), | |
294 | // .timed_pll_arst_l (timed_pll_arst_l) | |
295 | // ); | |
296 | // endmodule | |
297 | ||
298 | ||
299 | ||
300 | module n2_core_pll_cust(sel_l2clk_fbk ,dr_stretch_a ,pll_clk_out_l , | |
301 | dr_clk_out_l ,pll_clamp_fltr ,dr_ext_clk ,ccu_serdes_dtm , | |
302 | pll_char_out ,pll_sys_clk ,dr_sel_a ,pll_ext_clk ,vreg_selbg_l , | |
303 | dr_sdel ,pll_clk_out ,l2clk ,pll_sdel ,dft_rst_a_l ,pll_char_in , | |
304 | pll_arst_l ,vdd_hv15 ,dr_clk_out ,pll_stretch_a ,pll_sel_a , | |
305 | pll_div4 ,pll_bypass ,pll_div3 ,pll_div1 ,pll_div2 , | |
306 | ccu_rst_ref_buf2 ,ccu_rst_sys_clk ,pll_testmode ); | |
307 | output [1:0] pll_char_out ; | |
308 | input [1:0] pll_sys_clk ; | |
309 | input [1:0] dr_sel_a ; | |
310 | input [1:0] dr_sdel ; | |
311 | input [1:0] pll_sdel ; | |
312 | input [1:0] pll_sel_a ; | |
313 | input [6:0] pll_div4 ; | |
314 | input [5:0] pll_div3 ; | |
315 | input [5:0] pll_div1 ; | |
316 | input [5:0] pll_div2 ; | |
317 | output pll_clk_out_l ; | |
318 | output dr_clk_out_l ; | |
319 | output pll_clk_out ; | |
320 | output dr_clk_out ; | |
321 | output ccu_rst_ref_buf2 ; | |
322 | output ccu_rst_sys_clk ; | |
323 | input sel_l2clk_fbk ; | |
324 | input dr_stretch_a ; | |
325 | input pll_clamp_fltr ; | |
326 | input dr_ext_clk ; | |
327 | input ccu_serdes_dtm ; | |
328 | input pll_ext_clk ; | |
329 | input vreg_selbg_l ; | |
330 | input l2clk ; | |
331 | input dft_rst_a_l ; | |
332 | input pll_char_in ; | |
333 | input pll_arst_l ; | |
334 | input vdd_hv15 ; | |
335 | input pll_stretch_a ; | |
336 | input pll_bypass ; | |
337 | input pll_testmode ; | |
338 | ||
339 | supply1 vdd ; | |
340 | supply0 vss ; | |
341 | ||
342 | wire [9:0] net0210 ; | |
343 | wire pll_jtag_lock_everlose ; | |
344 | wire fast_l ; | |
345 | wire ref_ck ; | |
346 | wire l1clk_buf ; | |
347 | wire net0189 ; | |
348 | wire fast_buf ; | |
349 | wire vco2_clk ; | |
350 | wire slow_buf ; | |
351 | wire vdd_reg = 1'b1; | |
352 | wire ref ; | |
353 | wire pll_lock_pulse ; | |
354 | wire dc_clk ; | |
355 | wire pfd_reset ; | |
356 | wire pll_lock_dyn ; | |
357 | wire vco8_clk ; | |
358 | wire net0131 ; | |
359 | wire net0132 ; | |
360 | wire bypass_clk ; | |
361 | wire net0135 ; | |
362 | wire net0136 ; | |
363 | wire net0139 ; | |
364 | wire slow ; | |
365 | wire fb ; | |
366 | wire net0144 ; | |
367 | wire fast ; | |
368 | wire net159 ; | |
369 | wire fb_ck ; | |
370 | wire net0114 ; | |
371 | wire net163 ; | |
372 | wire div_ck3 ; | |
373 | wire net0117 ; | |
374 | wire dr_clk ; | |
375 | wire fltr ; | |
376 | wire net080 ; | |
377 | wire slow_l ; | |
378 | wire vco_out ; | |
379 | wire net0172 ; | |
380 | ||
381 | ||
382 | n2_core_pll_vco_sum_cust x2 ( | |
383 | .dc_clk (dc_clk ), | |
384 | .vdd_reg (vdd_reg ), | |
385 | .volb (vco_out ), | |
386 | .slow (slow ), | |
387 | .slow_l (slow_l ), | |
388 | .fast (fast ), | |
389 | .fltr (fltr ), | |
390 | .fast_l (fast_l ) ); | |
391 | //n2_core_pll_vdd_xing_buf_4x_cust x3 ( | |
392 | // .vdd_reg (vdd_reg ), | |
393 | // .out (net0172 ), | |
394 | // .in (pll_clamp_fltr ) ); | |
395 | //n2_core_pll_m1_cust x4 ( | |
396 | // .vdd_reg (vdd_reg ) ); | |
397 | n2_core_pll_inv_100x_cust x5 ( | |
398 | .vdd_reg (vdd ), | |
399 | .out (dr_clk_out ), | |
400 | .in (net0131 ) ); | |
401 | n2_core_pll_tpm3_all_cust x6 ( | |
402 | .pll_div3 ({pll_div3 } ), | |
403 | .pll_sdel ({pll_sdel } ), | |
404 | .pll_sel_a ({pll_sel_a } ), | |
405 | .dr_sdel ({dr_sdel } ), | |
406 | .dr_sel_a ({dr_sel_a } ), | |
407 | .pll_div4 ({pll_div4 } ), | |
408 | .pll_stretch_a (pll_stretch_a ), | |
409 | .ccu_serdes_dtm (ccu_serdes_dtm ), | |
410 | .dr_ext_clk (dr_ext_clk ), | |
411 | .dc_clk (dc_clk ), | |
412 | .pll_clk_out_l (net0132 ), | |
413 | .pll_bypass_clk_en (pll_bypass ), | |
414 | // .pll_arst_l (pll_arst_l ), | |
415 | .pll_arst_l (timed_pll_arst_l), // worked around non-deterministic reset - mh157021 | |
416 | .dr_clk_out (dr_clk ), | |
417 | .pll_bypass_clk (bypass_clk ), | |
418 | .pll_clk_out (net0144 ), | |
419 | .dr_clk_out_l (net0131 ), | |
420 | .dr_stretch_a (dr_stretch_a ), | |
421 | .pll_testmode (pll_testmode ), | |
422 | .vco8_clk (vco8_clk ), | |
423 | .volb (~vco_out ), | |
424 | .vco2_clk (vco2_clk ), | |
425 | .pll_ext_clk (pll_ext_clk ), | |
426 | .dft_rst_a_l (dft_rst_a_l ) ); | |
427 | //n2_vreg_cust x7 ( | |
428 | // .i50n ({net0210[0] ,net0210[1] ,net0210[2] ,net0210[3] , | |
429 | // net0210[4] ,net0210[5] ,net0210[6] ,net0210[7] ,net0210[8] , | |
430 | // net0210[9] } ), | |
431 | // .v1p1reg_lowv (vdd_reg ), | |
432 | // .vdd_hv15 (vdd_hv15 ), | |
433 | // .vref (net0189 ), | |
434 | // .vrefb (net0136 ), | |
435 | // .selbg_l (vreg_selbg_l ) ); | |
436 | //terminator i58_3_ ( | |
437 | // .TERM (net0210[6] ) ); | |
438 | n2_core_pll_inv_1x_cust x8 ( | |
439 | .vdd_reg (vdd ), | |
440 | .out (net163 ), | |
441 | .in (pll_arst_l ) ); | |
442 | n2_core_pll_vdd_xing_buf_4x_cust x9 ( | |
443 | .vdd_reg (vdd_reg ), | |
444 | .out (net159 ), | |
445 | .in (net163 ) ); | |
446 | n2_core_pll_charc_cust xcharc ( | |
447 | .pll_charc_out ({pll_char_out } ), | |
448 | .arst_l (pll_arst_l ), | |
449 | .ccu_rst_ref_buf2_l (net0139 ), | |
450 | .testmode (pll_testmode ), | |
451 | .dr_clk_out (dr_clk ), | |
452 | .ccu_rst_sys_clk (ccu_rst_sys_clk ), | |
453 | .lock (pll_lock_dyn ), | |
454 | .fb_clk_l (fb_ck ), | |
455 | .pll_charc_in (pll_char_in ), | |
456 | .ref_clk_l (ref_ck ), | |
457 | .fast (fast_buf ), | |
458 | .slow (slow_buf ), | |
459 | .ref (ref ), | |
460 | .fb (fb ), | |
461 | .vco_clk (vco8_clk ), | |
462 | .l1clk (l1clk_buf ) ); | |
463 | //terminator i58_4_ ( | |
464 | // .TERM (net0210[5] ) ); | |
465 | n2_core_pll_inv_100x_cust x10 ( | |
466 | .vdd_reg (vdd ), | |
467 | .out (pll_clk_out ), | |
468 | .in (net0132 ) ); | |
469 | //n2_core_pll_pad_cluster_cust x11 ( | |
470 | // .pll_sys_clk ({pll_sys_clk } ), | |
471 | // .vdd_hv15 (vdd_hv15 ) ); | |
472 | //terminator i30 ( | |
473 | // .TERM (pll_lock_pulse ) ); | |
474 | //n2_core_pll_inv_1x_cust x12 ( | |
475 | // .vdd_reg (vdd_reg ), | |
476 | // .out (net0135 ), | |
477 | // .in (vss ) ); | |
478 | //n2_core_pll_inv_1x_cust x13 ( | |
479 | // .vdd_reg (vdd_reg ), | |
480 | // .out (net080 ), | |
481 | // .in (vss ) ); | |
482 | n2_core_pll_inv_32x_cust x14 ( | |
483 | .vdd_reg (vdd ), | |
484 | .out (pll_clk_out_l ), | |
485 | .in (net0144 ) ); | |
486 | n2_core_pll_inv_32x_cust x15 ( | |
487 | .vdd_reg (vdd ), | |
488 | .out (dr_clk_out_l ), | |
489 | .in (dr_clk ) ); | |
490 | n2_core_pll_inv_4x_cust x16 ( | |
491 | .vdd_reg (vdd_reg ), | |
492 | .out (net0117 ), | |
493 | .in (net0172 ) ); | |
494 | n2_core_pll_inv_8x_cust x17 ( | |
495 | .vdd_reg (vdd_reg ), | |
496 | .out (net0114 ), | |
497 | .in (net0117 ) ); | |
498 | n2_core_pll_inv_32x_cust x18 ( | |
499 | .vdd_reg (vdd ), | |
500 | .out (ccu_rst_ref_buf2 ), | |
501 | .in (net0139 ) ); | |
502 | //terminator i58_5_ ( | |
503 | // .TERM (net0210[4] ) ); | |
504 | //terminator i58_6_ ( | |
505 | // .TERM (net0210[3] ) ); | |
506 | //terminator i52 ( | |
507 | // .TERM (div_ck3 ) ); | |
508 | //terminator i53 ( | |
509 | // .TERM (net0189 ) ); | |
510 | //terminator i54 ( | |
511 | // .TERM (net0136 ) ); | |
512 | //terminator i55 ( | |
513 | // .TERM (pll_jtag_lock_everlose ) ); | |
514 | //terminator i58_7_ ( | |
515 | // .TERM (net0210[2] ) ); | |
516 | //pfet_thox m0 ( | |
517 | // .B (vdd ), | |
518 | // .G (vss ), | |
519 | // .D (vdd ), | |
520 | // .S (vdd ) ); | |
521 | //terminator i58_0_ ( | |
522 | // .TERM (net0210[9] ) ); | |
523 | //terminator i58_8_ ( | |
524 | // .TERM (net0210[1] ) ); | |
525 | //terminator i58_1_ ( | |
526 | // .TERM (net0210[8] ) ); | |
527 | //terminator i58_9_ ( | |
528 | // .TERM (net0210[0] ) ); | |
529 | //terminator i58_2_ ( | |
530 | // .TERM (net0210[7] ) ); | |
531 | //n2_core_pll_vrr_cust x0 ( | |
532 | // .vdd_reg (vdd_reg ), | |
533 | // .fltr_nw (fltr ), | |
534 | // .reset (net159 ), | |
535 | // .fb (fb ), | |
536 | // .div8 (net0135 ), | |
537 | // .div4 (net080 ), | |
538 | // .div_ck (ref ), | |
539 | // .vrr_disbl (vss ), | |
540 | // .clamp_fltr (net0114 ), | |
541 | // .pfd_reset (pfd_reset ) ); | |
542 | n2_core_pll_pecl_all_cust x1 ( | |
543 | .pll_div1 ({pll_div1 } ), | |
544 | .pll_div2 ({pll_div2 } ), | |
545 | .pll_sys_clk ({pll_sys_clk } ), | |
546 | .regdivcr (div_ck3 ), | |
547 | .ref_ck (ref_ck ), | |
548 | .slow_l (slow_l ), | |
549 | .fast (fast ), | |
550 | .fast_l (fast_l ), | |
551 | .pll_clamp_fltr (net0114 ), | |
552 | .pll_lock_pulse (pll_lock_pulse ), | |
553 | .vdd_reg (vdd_reg ), | |
554 | .fb_ck (fb_ck ), | |
555 | .pll_bypass_clk_en (pll_bypass ), | |
556 | .ccu_serdes_dtm (ccu_serdes_dtm ), | |
557 | .l2clk (l2clk ), | |
558 | .slow (slow ), | |
559 | .slow_buf (slow_buf ), | |
560 | .pll_jtag_lock_everlose (pll_jtag_lock_everlose ), | |
561 | .pll_lock_dyn (pll_lock_dyn ), | |
562 | .raw_clk_byp (bypass_clk ), | |
563 | .fast_buf (fast_buf ), | |
564 | .l2clkc (vco2_clk ), | |
565 | .testmode (sel_l2clk_fbk ), | |
566 | .pll_arst_l (pll_arst_l ), | |
567 | .ref (ref ), | |
568 | .fb (fb ), | |
569 | .l1clk_buf (l1clk_buf ), | |
570 | .pfd_reset (pfd_reset ), | |
571 | .fltr (fltr ) ); | |
572 | imaginary_timed_rst imaginary_timed_rst ( // added timed reset to resolve d3 reset issue - mh157021 | |
573 | .ref (ref), | |
574 | .vco_clk (vco_out), | |
575 | .pll_arst_l (pll_arst_l), | |
576 | .pll_div2 (pll_div2), | |
577 | .timed_pll_arst_l (timed_pll_arst_l) | |
578 | ); | |
579 | ||
580 | endmodule | |
581 | ||
582 | // ================================================================== | |
583 | // mh157021: PLL LOWER LEVEL MODULE DEFINITIONS | |
584 | // ================================================================== | |
585 | ||
586 | ||
587 | // mh157021: instance #0 (n2_core_pll_vco_sum_cust) | |
588 | // | |
589 | // Last Modified: Friday Aug 26,2005 at 03:22:07 PM PDT | |
590 | // | |
591 | ||
592 | // module n2_core_pll_vco_sum_cust(cktree_drv ,vco_clk ,vdd_reg ,vco_out , | |
593 | // slow ,slow_l ,fast ,fltr ,fast_l ); | |
594 | // | |
595 | // output vco_clk ; | |
596 | // output vco_out ; | |
597 | // input cktree_drv ; | |
598 | // input vdd_reg ; | |
599 | // input slow ; | |
600 | // input slow_l ; | |
601 | // input fast ; | |
602 | // input fltr ; | |
603 | // input fast_l ; | |
604 | ||
605 | module n2_core_pll_vco_sum_cust(dc_clk,volb,vdd_reg, | |
606 | slow ,slow_l ,fast ,fltr ,fast_l ); | |
607 | ||
608 | output volb ; | |
609 | input dc_clk ; | |
610 | input vdd_reg ; | |
611 | input slow ; | |
612 | input slow_l ; | |
613 | input fast ; | |
614 | input fltr ; | |
615 | input fast_l ; | |
616 | ||
617 | // mh157021: implemented as a dummy mod if needed | |
618 | assign volb = fast; | |
619 | ||
620 | endmodule | |
621 | ||
622 | ||
623 | // mh157021: instance #1, #7 (n2_core_pll_vdd_xing_buf_4x_cust) | |
624 | // | |
625 | // Last Modified: Friday Aug 26,2005 at 03:22:12 PM PDT | |
626 | // | |
627 | ||
628 | module n2_core_pll_vdd_xing_buf_4x_cust(vdd_reg ,out ,in ); | |
629 | output out ; | |
630 | input vdd_reg ; | |
631 | input in ; | |
632 | wire vss = 1'b0; | |
633 | ||
634 | assign out = in; | |
635 | ||
636 | endmodule | |
637 | ||
638 | ||
639 | // mh157021: instance #2 (n2_core_pll_m1_cust) | |
640 | // | |
641 | // Last Modified: Friday Aug 26,2005 at 03:20:48 PM PDT | |
642 | // | |
643 | ||
644 | module n2_core_pll_m1_cust(vdd_reg ); | |
645 | input vdd_reg ; | |
646 | wire vss = 1'b0; | |
647 | ||
648 | endmodule | |
649 | ||
650 | ||
651 | // mh157021: instance #3, #9 (n2_core_pll_inv_100x_cust) | |
652 | // | |
653 | // Last Modified: Friday Aug 26,2005 at 03:20:26 PM PDT | |
654 | // | |
655 | ||
656 | module n2_core_pll_inv_100x_cust(vdd_reg ,out ,in ); | |
657 | output out ; | |
658 | input vdd_reg ; | |
659 | input in ; | |
660 | wire vss = 1'b0; | |
661 | ||
662 | assign out = ~in; | |
663 | ||
664 | endmodule | |
665 | ||
666 | ||
667 | // mh157021: instance #5 (n2_vreg_cust) | |
668 | // | |
669 | // Last Modified: Friday Aug 26,2005 at 03:22:43 PM PDT | |
670 | // | |
671 | ||
672 | module n2_vreg_cust(v1p1reg_lowv ,vdd_hv15 ,vref ,vrefb ,i50n ,selbg_l | |
673 | ); | |
674 | output [9:0] i50n ; | |
675 | output v1p1reg_lowv ; | |
676 | output vref ; | |
677 | output vrefb ; | |
678 | input vdd_hv15 ; | |
679 | input selbg_l ; | |
680 | wire vss = 1'b0; | |
681 | ||
682 | wire [9:0] i50n ; | |
683 | wire [3:0] i25 ; | |
684 | wire vgate_lowv ; | |
685 | wire net70 ; | |
686 | wire i5m ; | |
687 | wire vmid ; | |
688 | wire vrefr ; | |
689 | ||
690 | assign v1p1reg_lowv = 1'b1; | |
691 | assign i50n = 10'b0; | |
692 | assign vref = 1'b1; | |
693 | assign vrefb = 1'b1; | |
694 | ||
695 | endmodule | |
696 | ||
697 | ||
698 | ||
699 | // mh157021: instance #8 (n2_core_pll_charc_cust) | |
700 | // | |
701 | // | |
702 | ||
703 | module n2_core_pll_charc_cust(arst_l ,ccu_rst_ref_buf2_l ,testmode , | |
704 | dr_clk_out ,ccu_rst_sys_clk ,lock ,pll_charc_out ,fb_clk_l , | |
705 | pll_charc_in ,ref_clk_l ,fast ,slow ,ref ,fb ,vco_clk ,l1clk ); | |
706 | output [1:0] pll_charc_out ; | |
707 | output ccu_rst_ref_buf2_l ; | |
708 | output ccu_rst_sys_clk ; | |
709 | input arst_l ; | |
710 | input testmode ; | |
711 | input dr_clk_out ; | |
712 | input lock ; | |
713 | input fb_clk_l ; | |
714 | input pll_charc_in ; | |
715 | input ref_clk_l ; | |
716 | input fast ; | |
717 | input slow ; | |
718 | input ref ; | |
719 | input fb ; | |
720 | input vco_clk ; | |
721 | input l1clk ; | |
722 | supply1 vdd ; | |
723 | ||
724 | wire [7:0] aoa1a2_ ; | |
725 | wire [9:0] mxin ; | |
726 | wire [3:0] a3a4_ ; | |
727 | wire [1:0] a5_ ; | |
728 | wire \mxbuf[1] ; | |
729 | wire \mxbuf[9] ; | |
730 | wire out_bot ; | |
731 | wire mux_out1 ; | |
732 | wire mux_out2 ; | |
733 | wire net76 ; | |
734 | wire net77 ; | |
735 | wire clk_fall1 ; | |
736 | wire clk_fall2 ; | |
737 | wire \mxbuf[2] ; | |
738 | wire clk_fall3 ; | |
739 | wire clk_fall4 ; | |
740 | wire net224 ; | |
741 | wire out_top ; | |
742 | wire net227 ; | |
743 | wire \mxbuf[4] ; | |
744 | wire net238 ; | |
745 | wire reset ; | |
746 | wire net0232 ; | |
747 | wire a0 ; | |
748 | wire l1clk_vcoclk ; | |
749 | wire a1 ; | |
750 | wire a2 ; | |
751 | wire a3 ; | |
752 | wire net251 ; | |
753 | wire a4 ; | |
754 | wire net252 ; | |
755 | wire \mxbuf[6] ; | |
756 | wire a5 ; | |
757 | wire a6_0 ; | |
758 | wire out_cnt1 ; | |
759 | wire a6 ; | |
760 | wire a6_1 ; | |
761 | wire a7 ; | |
762 | wire \mxbuf[7] ; | |
763 | wire l1clk_vcoclk_l ; | |
764 | wire net169 ; | |
765 | wire clk_rise1 ; | |
766 | wire clk_rise2 ; | |
767 | wire clk_rise3 ; | |
768 | wire clk_rise4 ; | |
769 | wire \mxbuf[0] ; | |
770 | wire net174 ; | |
771 | wire \mxbuf[8] ; | |
772 | wire l1clk_vco_clk ; | |
773 | wire l1clk_vcoclk_div4 ; | |
774 | ||
775 | ||
776 | n2_core_pll_div4_new_cust x2 ( | |
777 | .clk (l1clk_vcoclk ), | |
778 | .arst_l (testmode ), | |
779 | .clk_div_out (l1clk_vcoclk_div4 ) ); | |
780 | n2_core_pll_charc_decoder_cust x3 ( | |
781 | .a5_out ({a5_ } ), | |
782 | .a6_out ({a6_1 ,a6_0 } ), | |
783 | .a3a4 ({a3a4_ } ), | |
784 | .aoa1a2 ({aoa1a2_ } ), | |
785 | .a6 (a6 ), | |
786 | .a5 (a5 ), | |
787 | .a4 (a4 ), | |
788 | .a3 (a3 ), | |
789 | .a2 (a2 ), | |
790 | .a1 (a1 ), | |
791 | .a0 (a0 ) ); | |
792 | n2_core_pll_mux8_8x_cust x4 ( | |
793 | .sel0 (aoa1a2_[0] ), | |
794 | .in2 (mxin[2] ), | |
795 | .sel2 (aoa1a2_[2] ), | |
796 | .sel5 (aoa1a2_[5] ), | |
797 | .in4 (mxin[4] ), | |
798 | .sel7 (aoa1a2_[7] ), | |
799 | .sel4 (aoa1a2_[4] ), | |
800 | .in1 (mxin[9] ), | |
801 | .dout (out_bot ), | |
802 | .in0 (mxin[0] ), | |
803 | .sel6 (aoa1a2_[6] ), | |
804 | .in5 (mxin[5] ), | |
805 | .in7 (mxin[7] ), | |
806 | .sel3 (aoa1a2_[3] ), | |
807 | .sel1 (aoa1a2_[1] ), | |
808 | .in3 (mxin[3] ), | |
809 | .in6 (mxin[6] ) ); | |
810 | n2_core_pll_mux2_8x_cust x5 ( | |
811 | .in0 (mxin[8] ), | |
812 | .sel0 (a5_[0] ), | |
813 | .dout (l1clk_vcoclk ), | |
814 | .sel1 (a5_[1] ), | |
815 | .in1 (mxin[1] ) ); | |
816 | n2_core_pll_mux2_8x_cust x6 ( | |
817 | .in0 (out_bot ), | |
818 | .sel0 (a6_0 ), | |
819 | .dout (net169 ), | |
820 | .sel1 (a6_1 ), | |
821 | .in1 (mux_out2 ) ); | |
822 | n2_core_pll_mux2_8x_cust x7 ( | |
823 | .in0 (out_top ), | |
824 | .sel0 (a6_0 ), | |
825 | .dout (net174 ), | |
826 | .sel1 (a6_1 ), | |
827 | .in1 (mux_out1 ) ); | |
828 | //terminator ia_4_ ( | |
829 | // .TERM (\mxbuf[6] ) ); | |
830 | n2_core_pll_buf_16x_cust x42_7_ ( | |
831 | .vdd_reg (vdd ), | |
832 | .out (\mxbuf[9] ), | |
833 | .in (mxin[9] ) ); | |
834 | n2_core_pll_buf_16x_cust x44_3_ ( | |
835 | .vdd_reg (vdd ), | |
836 | .out (mxin[3] ), | |
837 | .in (ref_clk_l ) ); | |
838 | //terminator ia_5_ ( | |
839 | // .TERM (\mxbuf[7] ) ); | |
840 | n2_core_pll_buf_16x_cust x42_0_ ( | |
841 | .vdd_reg (vdd ), | |
842 | .out (\mxbuf[0] ), | |
843 | .in (mxin[0] ) ); | |
844 | n2_core_pll_buf_16x_cust x44_4_ ( | |
845 | .vdd_reg (vdd ), | |
846 | .out (mxin[4] ), | |
847 | .in (fb ) ); | |
848 | n2_core_pll_4bit_counter_charc_cust x12 ( | |
849 | .clk (out_cnt1 ), | |
850 | .reset (net77 ), | |
851 | .cnt3 (vdd ), | |
852 | .qout_0 (a4 ), | |
853 | .qout_1 (a5 ), | |
854 | .qout_2 (a6 ), | |
855 | .qout_3 (a7 ), | |
856 | .count_out (net252 ), | |
857 | .cnt1 (vdd ), | |
858 | .cnt2 (vdd ), | |
859 | .cnt0 (vdd ) ); | |
860 | n2_core_pll_4bit_counter_charc_cust x15 ( | |
861 | .clk (pll_charc_in ), | |
862 | .reset (net77 ), | |
863 | .cnt3 (vdd ), | |
864 | .qout_0 (a0 ), | |
865 | .qout_1 (a1 ), | |
866 | .qout_2 (a2 ), | |
867 | .qout_3 (a3 ), | |
868 | .count_out (out_cnt1 ), | |
869 | .cnt1 (vdd ), | |
870 | .cnt2 (vdd ), | |
871 | .cnt0 (vdd ) ); | |
872 | n2_core_pll_charc_flops_cust x16 ( | |
873 | .data_in (net238 ), | |
874 | .clk (l1clk_vco_clk ), | |
875 | .clk_l (l1clk_vcoclk_l ), | |
876 | .clk_rise1 (clk_rise1 ), | |
877 | .clk_fall1 (clk_fall1 ), | |
878 | .clk_rise2 (clk_rise2 ), | |
879 | .clk_fall2 (clk_fall2 ), | |
880 | .reset (net77 ), | |
881 | .clk_rise4 (clk_rise4 ), | |
882 | .clk_rise3 (clk_rise3 ), | |
883 | .clk_fall3 (clk_fall3 ), | |
884 | .clk_fall4 (clk_fall4 ) ); | |
885 | n2_core_pll_charc_mux_cust x17 ( | |
886 | .a3a4_ ({a3a4_ } ), | |
887 | .aoa1a2_ ({aoa1a2_ } ), | |
888 | .clk_fall2 (clk_fall2 ), | |
889 | .clk_fall3 (clk_fall3 ), | |
890 | .clk_fall4 (clk_fall4 ), | |
891 | .clk_fall1 (clk_fall1 ), | |
892 | .clk_rise3 (clk_rise3 ), | |
893 | .clk_rise2 (clk_rise2 ), | |
894 | .clk_rise4 (clk_rise4 ), | |
895 | .clk_rise1 (clk_rise1 ), | |
896 | .mux_out1 (mux_out1 ), | |
897 | .mux_out2 (mux_out2 ) ); | |
898 | //terminator ia_6_ ( | |
899 | // .TERM (\mxbuf[8] ) ); | |
900 | n2_core_pll_buf_16x_cust x42_1_ ( | |
901 | .vdd_reg (vdd ), | |
902 | .out (\mxbuf[1] ), | |
903 | .in (mxin[1] ) ); | |
904 | n2_core_pll_buf_16x_cust x44_5_ ( | |
905 | .vdd_reg (vdd ), | |
906 | .out (mxin[5] ), | |
907 | .in (ref ) ); | |
908 | //terminator ia_7_ ( | |
909 | // .TERM (\mxbuf[9] ) ); | |
910 | n2_core_pll_buf_16x_cust x42_2_ ( | |
911 | .vdd_reg (vdd ), | |
912 | .out (\mxbuf[2] ), | |
913 | .in (mxin[2] ) ); | |
914 | n2_core_pll_buf_16x_cust x44_6_ ( | |
915 | .vdd_reg (vdd ), | |
916 | .out (mxin[6] ), | |
917 | .in (slow ) ); | |
918 | n2_core_pll_inv_16x_cust x34 ( | |
919 | .vdd_reg (vdd ), | |
920 | .out (l1clk_vcoclk_l ), | |
921 | .in (l1clk_vcoclk ) ); | |
922 | n2_core_pll_buf_16x_cust x35 ( | |
923 | .vdd_reg (vdd ), | |
924 | .out (l1clk_vco_clk ), | |
925 | .in (l1clk_vcoclk ) ); | |
926 | n2_core_pll_buf_16x_cust x36 ( | |
927 | .vdd_reg (vdd ), | |
928 | .out (net238 ), | |
929 | .in (net76 ) ); | |
930 | n2_core_pll_inv_16x_cust x37 ( | |
931 | .vdd_reg (vdd ), | |
932 | .out (net224 ), | |
933 | .in (net174 ) ); | |
934 | n2_core_pll_inv_16x_cust x38 ( | |
935 | .vdd_reg (vdd ), | |
936 | .out (net227 ), | |
937 | .in (net169 ) ); | |
938 | n2_core_pll_inv_32x_cust x39 ( | |
939 | .vdd_reg (vdd ), | |
940 | .out (pll_charc_out[1] ), | |
941 | .in (net224 ) ); | |
942 | //terminator ia_0_ ( | |
943 | // .TERM (\mxbuf[0] ) ); | |
944 | n2_core_pll_buf_16x_cust x42_3_ ( | |
945 | .vdd_reg (vdd ), | |
946 | .out (\mxbuf[4] ), | |
947 | .in (mxin[4] ) ); | |
948 | n2_core_pll_buf_16x_cust x44_7_ ( | |
949 | .vdd_reg (vdd ), | |
950 | .out (mxin[7] ), | |
951 | .in (fast ) ); | |
952 | n2_core_pll_inv_32x_cust x40 ( | |
953 | .vdd_reg (vdd ), | |
954 | .out (pll_charc_out[0] ), | |
955 | .in (net227 ) ); | |
956 | n2_core_pll_inv_2x_cust x41 ( | |
957 | .vdd_reg (vdd ), | |
958 | .out (reset ), | |
959 | .in (arst_l ) ); | |
960 | n2_core_pll_buf_16x_cust x43 ( | |
961 | .vdd_reg (vdd ), | |
962 | .out (net77 ), | |
963 | .in (reset ) ); | |
964 | n2_core_pll_inv_32x_cust x46 ( | |
965 | .vdd_reg (vdd ), | |
966 | .out (ccu_rst_ref_buf2_l ), | |
967 | .in (mxin[5] ) ); | |
968 | n2_core_pll_inv_32x_cust x47 ( | |
969 | .vdd_reg (vdd ), | |
970 | .out (ccu_rst_sys_clk ), | |
971 | .in (net0232 ) ); | |
972 | n2_core_pll_inv_16x_cust x48 ( | |
973 | .vdd_reg (vdd ), | |
974 | .out (net0232 ), | |
975 | .in (mxin[3] ) ); | |
976 | //terminator ia_1_ ( | |
977 | // .TERM (\mxbuf[1] ) ); | |
978 | n2_core_pll_buf_16x_cust x42_4_ ( | |
979 | .vdd_reg (vdd ), | |
980 | .out (\mxbuf[6] ), | |
981 | .in (mxin[6] ) ); | |
982 | n2_core_pll_buf_16x_cust x44_0_ ( | |
983 | .vdd_reg (vdd ), | |
984 | .out (mxin[0] ), | |
985 | .in (lock ) ); | |
986 | n2_core_pll_buf_16x_cust x44_8_ ( | |
987 | .vdd_reg (vdd ), | |
988 | .out (mxin[8] ), | |
989 | .in (l1clk ) ); | |
990 | //terminator ix10 ( | |
991 | // .TERM (a7 ) ); | |
992 | //terminator ia_2_ ( | |
993 | // .TERM (\mxbuf[2] ) ); | |
994 | n2_core_pll_buf_16x_cust x42_5_ ( | |
995 | .vdd_reg (vdd ), | |
996 | .out (\mxbuf[7] ), | |
997 | .in (mxin[7] ) ); | |
998 | n2_core_pll_buf_16x_cust x44_1_ ( | |
999 | .vdd_reg (vdd ), | |
1000 | .out (mxin[1] ), | |
1001 | .in (vco_clk ) ); | |
1002 | n2_core_pll_buf_16x_cust x44_9_ ( | |
1003 | .vdd_reg (vdd ), | |
1004 | .out (mxin[9] ), | |
1005 | .in (dr_clk_out ) ); | |
1006 | //terminator ia_3_ ( | |
1007 | // .TERM (\mxbuf[4] ) ); | |
1008 | //terminator ix6 ( | |
1009 | // .TERM (net251 ) ); | |
1010 | //terminator ix7 ( | |
1011 | // .TERM (net252 ) ); | |
1012 | n2_core_pll_buf_16x_cust x42_6_ ( | |
1013 | .vdd_reg (vdd ), | |
1014 | .out (\mxbuf[8] ), | |
1015 | .in (mxin[8] ) ); | |
1016 | n2_core_pll_buf_16x_cust x44_2_ ( | |
1017 | .vdd_reg (vdd ), | |
1018 | .out (mxin[2] ), | |
1019 | .in (fb_clk_l ) ); | |
1020 | n2_core_pll_flop_reset_new_cust x0 ( | |
1021 | .vdd_reg (vdd ), | |
1022 | .reset_val_l (vdd ), | |
1023 | .d (l1clk_vcoclk_div4 ), | |
1024 | .reset (net77 ), | |
1025 | .clk (l1clk_vcoclk_l ), | |
1026 | .q_l (net251 ), | |
1027 | .q (net76 ) ); | |
1028 | n2_core_pll_mux8_8x_cust x1 ( | |
1029 | .sel0 (aoa1a2_[0] ), | |
1030 | .in2 (mxin[3] ), | |
1031 | .sel2 (aoa1a2_[2] ), | |
1032 | .sel5 (aoa1a2_[5] ), | |
1033 | .in4 (mxin[5] ), | |
1034 | .sel7 (aoa1a2_[7] ), | |
1035 | .sel4 (aoa1a2_[4] ), | |
1036 | .in1 (mxin[1] ), | |
1037 | .dout (out_top ), | |
1038 | .in0 (mxin[1] ), | |
1039 | .sel6 (aoa1a2_[6] ), | |
1040 | .in5 (mxin[4] ), | |
1041 | .in7 (mxin[6] ), | |
1042 | .sel3 (aoa1a2_[3] ), | |
1043 | .sel1 (aoa1a2_[1] ), | |
1044 | .in3 (mxin[2] ), | |
1045 | .in6 (mxin[7] ) ); | |
1046 | endmodule | |
1047 | ||
1048 | ||
1049 | ||
1050 | // mh157021: instance #10 (n2_core_pll_pad_cluster_cust) | |
1051 | // | |
1052 | // Last Modified: Friday Aug 26,2005 at 03:21:04 PM PDT | |
1053 | // | |
1054 | ||
1055 | module n2_core_pll_pad_cluster_cust(vdd_hv15 ,pll_sys_clk ); | |
1056 | input [1:0] pll_sys_clk ; | |
1057 | input vdd_hv15 ; | |
1058 | supply1 vdd ; | |
1059 | ||
1060 | endmodule | |
1061 | ||
1062 | ||
1063 | ||
1064 | // mh157021: instance #11 (n2_core_pll_vrr_cust) | |
1065 | // | |
1066 | // Last Modified: Friday Aug 26,2005 at 03:22:17 PM PDT | |
1067 | // | |
1068 | ||
1069 | module n2_core_pll_vrr_cust(vdd_reg ,fltr_nw ,reset ,fb ,div8 ,div4 , | |
1070 | div_ck ,vrr_disbl ,clamp_fltr ,pfd_reset ); | |
1071 | input vdd_reg ; | |
1072 | input reset ; | |
1073 | input fb ; | |
1074 | input div8 ; | |
1075 | input div4 ; | |
1076 | input div_ck ; | |
1077 | input vrr_disbl ; | |
1078 | input clamp_fltr ; | |
1079 | input pfd_reset ; | |
1080 | inout fltr_nw ; | |
1081 | wire vss = 1'b0; | |
1082 | ||
1083 | endmodule | |
1084 | ||
1085 | ||
1086 | ||
1087 | // mh157021: instance #12 (n2_core_pll_pecl_all_cust) | |
1088 | // | |
1089 | // | |
1090 | ||
1091 | module n2_core_pll_pecl_all_cust(regdivcr ,ref_ck ,slow_l ,fast ,fast_l | |
1092 | ,pll_clamp_fltr ,pll_lock_pulse ,vdd_reg ,fb_ck ,pll_bypass_clk_en | |
1093 | ,ccu_serdes_dtm ,l2clk ,slow ,slow_buf ,pll_jtag_lock_everlose , | |
1094 | pll_lock_dyn ,raw_clk_byp ,fast_buf ,l2clkc ,testmode ,pll_arst_l , | |
1095 | pll_div1 ,pll_div2 ,ref ,fb ,pll_sys_clk ,l1clk_buf ,pfd_reset , | |
1096 | fltr ); | |
1097 | input [5:0] pll_div1 ; | |
1098 | input [5:0] pll_div2 ; | |
1099 | input [1:0] pll_sys_clk ; | |
1100 | output regdivcr ; | |
1101 | output ref_ck ; | |
1102 | output slow_l ; | |
1103 | output fast ; | |
1104 | output fast_l ; | |
1105 | output pll_lock_pulse ; | |
1106 | output fb_ck ; | |
1107 | output slow ; | |
1108 | output slow_buf ; | |
1109 | output pll_jtag_lock_everlose ; | |
1110 | output pll_lock_dyn ; | |
1111 | output raw_clk_byp ; | |
1112 | output fast_buf ; | |
1113 | output ref ; | |
1114 | output fb ; | |
1115 | output l1clk_buf ; | |
1116 | output pfd_reset ; | |
1117 | output fltr ; | |
1118 | input pll_clamp_fltr ; | |
1119 | input vdd_reg ; | |
1120 | input pll_bypass_clk_en ; | |
1121 | input ccu_serdes_dtm ; | |
1122 | input l2clk ; | |
1123 | input l2clkc ; | |
1124 | input testmode ; | |
1125 | input pll_arst_l ; | |
1126 | supply1 vdd ; | |
1127 | ||
1128 | wire [5:0] net0142 ; | |
1129 | wire [5:0] net0111 ; | |
1130 | wire [1:0] arst ; | |
1131 | wire net0178 ; | |
1132 | wire l1clk_p ; | |
1133 | wire net0207 ; | |
1134 | wire regdiv ; | |
1135 | wire fb_ckn ; | |
1136 | wire ref_ck_lock ; | |
1137 | wire net0164 ; | |
1138 | wire bypass_clk ; | |
1139 | wire net0234 ; | |
1140 | wire net0139 ; | |
1141 | wire net153 ; | |
1142 | wire net155 ; | |
1143 | wire ref_ckn ; | |
1144 | wire net0110 ; | |
1145 | wire l1clk ; | |
1146 | wire l1clk_l ; | |
1147 | wire net0118 ; | |
1148 | wire fb_ck_lock ; | |
1149 | wire l1clk_n ; | |
1150 | wire net0120 ; | |
1151 | wire net0122 ; | |
1152 | wire net0124 ; | |
1153 | ||
1154 | ||
1155 | n2_core_pll_pecl_bypass_clk_cust x2 ( | |
1156 | .phase_ck (bypass_clk ), | |
1157 | .pecl_p (pll_sys_clk[0] ), | |
1158 | .pecl_n (pll_sys_clk[1] ) ); | |
1159 | //n2_core_pll_inv_8x_cust x3 ( | |
1160 | // .vdd_reg (vdd ), | |
1161 | // .out (fb_ck_lock ), | |
1162 | // .in (net0118 ) ); | |
1163 | //terminator ixop2_5_ ( | |
1164 | // .TERM (net0142[0] ) ); | |
1165 | //n2_core_pll_inv_16x_cust x4 ( | |
1166 | // .vdd_reg (vdd ), | |
1167 | // .out (pll_lock_dyn ), | |
1168 | // .in (net0122 ) ); | |
1169 | //n2_core_pll_inv_8x_cust x5 ( | |
1170 | // .vdd_reg (vdd ), | |
1171 | // .out (net0207 ), | |
1172 | // .in (pll_arst_l ) ); | |
1173 | //n2_core_pll_inv_8x_cust x6 ( | |
1174 | // .vdd_reg (vdd ), | |
1175 | // .out (net0178 ), | |
1176 | // .in (ref_ck ) ); | |
1177 | n2_core_pll_delay_cust xdel1 ( | |
1178 | .vdd_reg (vdd_reg ), | |
1179 | .out_delcr (regdivcr ), | |
1180 | .in (pll_arst_l ), | |
1181 | .out_del (regdiv ) ); | |
1182 | //n2_core_pll_inv_4x_cust x7 ( | |
1183 | // .vdd_reg (vdd ), | |
1184 | // .out (net0122 ), | |
1185 | // .in (net0124 ) ); | |
1186 | n2_core_pll_tpm_cust x8 ( | |
1187 | .ip ({pll_div2 } ), | |
1188 | .op ({net0142[0] ,net0142[1] ,net0142[2] ,net0142[3] , | |
1189 | net0142[4] ,net0142[5] } ), | |
1190 | .reset (arst[0] ), | |
1191 | .vdd_reg (vdd_reg ), | |
1192 | .sel (net0120 ), | |
1193 | .div_ck_i (regdiv ), | |
1194 | .pwr_rst (arst[1] ), | |
1195 | .div_ck (fb ), | |
1196 | .vco_ck (fb_ckn ) ); | |
1197 | n2_core_pll_inv_16x_cust x9 ( | |
1198 | .vdd_reg (vdd ), | |
1199 | .out (l1clk_buf ), | |
1200 | .in (net0139 ) ); | |
1201 | n2_core_pll_inv_8x_cust x1_1_ ( | |
1202 | .vdd_reg (vdd_reg ), | |
1203 | .out (arst[1] ), | |
1204 | .in (net0164 ) ); | |
1205 | //terminator ixop1_0_ ( | |
1206 | // .TERM (net0111[5] ) ); | |
1207 | //n2_core_pll_inv_4x_cust x10 ( | |
1208 | // .vdd_reg (vdd ), | |
1209 | // .out (net0118 ), | |
1210 | // .in (fb_ck ) ); | |
1211 | //n2_core_pll_inv_32x_cust x11 ( | |
1212 | // .vdd_reg (vdd ), | |
1213 | // .out (ref_ck_lock ), | |
1214 | // .in (net0178 ) ); | |
1215 | n2_core_pll_pecl_enb_cust x12 ( | |
1216 | .in (bypass_clk ), | |
1217 | .out (raw_clk_byp ), | |
1218 | .enb1 (ccu_serdes_dtm ), | |
1219 | .enb0 (pll_bypass_clk_en ) ); | |
1220 | n2_core_pll_inv_16x_cust x13 ( | |
1221 | .vdd_reg (vdd_reg ), | |
1222 | .out (l1clk_n ), | |
1223 | .in (l1clk ) ); | |
1224 | //n2_core_pll_buf_4x_cust x14 ( | |
1225 | // .vdd_reg (vdd ), | |
1226 | // .out (net0234 ), | |
1227 | // .in (l1clk ) ); | |
1228 | n2_core_pll_buf_4x_cust x15 ( | |
1229 | .vdd_reg (vdd ), | |
1230 | .out (net0139 ), | |
1231 | .in (l1clk_l ) ); | |
1232 | n2_core_pll_vdd_xing_buf_32x_cust x16 ( | |
1233 | .vdd_reg (vdd ), | |
1234 | .out (fb_ck ), | |
1235 | .in (fb_ckn ) ); | |
1236 | n2_core_pll_vdd_xing_buf_32x_cust x17 ( | |
1237 | .vdd_reg (vdd ), | |
1238 | .out (ref_ck ), | |
1239 | .in (ref_ckn ) ); | |
1240 | //terminator ixop1_1_ ( | |
1241 | // .TERM (net0111[4] ) ); | |
1242 | n2_core_pll_vdd_xing_buf_4x_cust x18 ( | |
1243 | .vdd_reg (vdd_reg ), | |
1244 | .out (net0164 ), | |
1245 | .in (pll_arst_l ) ); | |
1246 | n2_core_pll_inv_16x_cust x19 ( | |
1247 | .vdd_reg (vdd_reg ), | |
1248 | .out (l1clk_p ), | |
1249 | .in (l1clk_l ) ); | |
1250 | //terminator ixop2_0_ ( | |
1251 | // .TERM (net0142[5] ) ); | |
1252 | //terminator ixop1_2_ ( | |
1253 | // .TERM (net0111[3] ) ); | |
1254 | n2_core_pll_pecl_cust xpcl ( | |
1255 | .vdd_reg (vdd_reg ), | |
1256 | .fb_ck (fb_ckn ), | |
1257 | .pecl_p (pll_sys_clk[0] ), | |
1258 | .pecl_n (pll_sys_clk[1] ), | |
1259 | .hdr_p (l1clk_p ), | |
1260 | .ref_ck (ref_ckn ), | |
1261 | .hdr_n (l1clk_n ) ); | |
1262 | //terminator ixop2_1_ ( | |
1263 | // .TERM (net0142[4] ) ); | |
1264 | //terminator ixop1_3_ ( | |
1265 | // .TERM (net0111[2] ) ); | |
1266 | n2_core_pll_tpm_cust xd1 ( | |
1267 | .ip ({pll_div1 } ), | |
1268 | .op ({net0111[0] ,net0111[1] ,net0111[2] ,net0111[3] , | |
1269 | net0111[4] ,net0111[5] } ), | |
1270 | .reset (arst[1] ), | |
1271 | .vdd_reg (vdd_reg ), | |
1272 | .sel (net0110 ), | |
1273 | .div_ck_i (regdiv ), | |
1274 | .pwr_rst (arst[0] ), | |
1275 | .div_ck (ref ), | |
1276 | .vco_ck (ref_ckn ) ); | |
1277 | //terminator ixop2_2_ ( | |
1278 | // .TERM (net0142[3] ) ); | |
1279 | //terminator ixop1_4_ ( | |
1280 | // .TERM (net0111[1] ) ); | |
1281 | n2_core_pll_se2diff_mux_cust xil1clk_hdr ( | |
1282 | .vdd_reg (vdd ), | |
1283 | .in1 (l2clk ), | |
1284 | .sel (testmode ), | |
1285 | .out (l1clk ), | |
1286 | .in0 (l2clkc ), | |
1287 | .out_l (l1clk_l ) ); | |
1288 | //n2_core_pll_pfd_cust xpfd ( | |
1289 | // .vdd_reg (vdd_reg ), | |
1290 | // .f_buf (fast_buf ), | |
1291 | // .f_buf_l (net155 ), | |
1292 | // .fast_l (fast_l ), | |
1293 | // .clamp_fltr (pll_clamp_fltr ), | |
1294 | // .s_buf (slow_buf ), | |
1295 | // .s_buf_l (net153 ), | |
1296 | // .slow_l (slow_l ), | |
1297 | // .slow (slow ), | |
1298 | // .fast (fast ), | |
1299 | // .pfd_reset (pfd_reset ), | |
1300 | // .fb (fb ), | |
1301 | // .ref (ref ) ); | |
1302 | //terminator ixop2_3_ ( | |
1303 | // .TERM (net0142[2] ) ); | |
1304 | //terminator ixop1_5_ ( | |
1305 | // .TERM (net0111[0] ) ); | |
1306 | //terminator i207 ( | |
1307 | // .TERM (net0234 ) ); | |
1308 | //terminator ixop2_4_ ( | |
1309 | // .TERM (net0142[1] ) ); | |
1310 | //terminator ix25 ( | |
1311 | // .TERM (net0110 ) ); | |
1312 | //terminator ix27 ( | |
1313 | // .TERM (net153 ) ); | |
1314 | //terminator ix28 ( | |
1315 | // .TERM (net155 ) ); | |
1316 | n2_core_pll_inv_8x_cust x1_0_ ( | |
1317 | .vdd_reg (vdd_reg ), | |
1318 | .out (arst[0] ), | |
1319 | .in (net0164 ) ); | |
1320 | //terminator ix8 ( | |
1321 | // .TERM (net0120 ) ); | |
1322 | //n2_core_pll_cp_cust xcp ( | |
1323 | // .slow_l (slow_l ), | |
1324 | // .vdd_reg (vdd_reg ), | |
1325 | // .slow (slow ), | |
1326 | // .fast (fast ), | |
1327 | // .fast_l (fast_l ), | |
1328 | // .fltr (fltr ) ); | |
1329 | //n2_core_pll_lockdet_cust x0 ( | |
1330 | // .pll_jtag_lock_everlose (pll_jtag_lock_everlose ), | |
1331 | // .l1clk (fb_ck_lock ), | |
1332 | // .pll_lock_dyn (net0124 ), | |
1333 | // .reset_in (net0207 ), | |
1334 | // .slow (slow_buf ), | |
1335 | // .fast (fast_buf ), | |
1336 | // .pll_lock_pulse (pll_lock_pulse ), | |
1337 | // .ref_ck (ref_ck_lock ) ); | |
1338 | imaginary_vco_gen imaginary_vco_gen ( | |
1339 | .pll_arst_l (pll_arst_l), | |
1340 | .sysclk (ref), | |
1341 | .fdbkclk (fast), | |
1342 | .div ({pll_div2[4:0], 1'b1}), // x2 since D3 == 2 (eff) always | |
1343 | .vco_out (fast) | |
1344 | ); | |
1345 | endmodule | |
1346 | ||
1347 | ||
1348 | // mh157021: lower level module definition (n2_core_pll_inv_2x_cust) | |
1349 | // | |
1350 | // Last Modified: Friday Aug 26,2005 at 03:20:31 PM PDT | |
1351 | // | |
1352 | ||
1353 | module n2_core_pll_inv_2x_cust(vdd_reg ,out ,in ); | |
1354 | output out ; | |
1355 | input vdd_reg ; | |
1356 | input in ; | |
1357 | wire vss = 1'b0; | |
1358 | ||
1359 | assign out = ~in; | |
1360 | ||
1361 | endmodule | |
1362 | ||
1363 | ||
1364 | ||
1365 | ||
1366 | ||
1367 | ||
1368 | // mh157021: lower level module definition (n2_core_pll_mux2_8x_cust) | |
1369 | // | |
1370 | // Last Modified: Friday Aug 26,2005 at 03:20:51 PM PDT | |
1371 | // | |
1372 | ||
1373 | module n2_core_pll_mux2_8x_cust(in0 ,sel0 ,dout ,sel1 ,in1 ); | |
1374 | output dout ; | |
1375 | input in0 ; | |
1376 | input sel0 ; | |
1377 | input sel1 ; | |
1378 | input in1 ; | |
1379 | ||
1380 | mux2 x1 ( | |
1381 | .sel0 (sel0), | |
1382 | .sel1 (sel1), | |
1383 | .in0 (in0), | |
1384 | .in1 (in1), | |
1385 | .y (dout) ); | |
1386 | ||
1387 | endmodule | |
1388 | ||
1389 | ||
1390 | // mh157021: lower level module definition (mux2) | |
1391 | module mux2 (in0,in1,sel0,sel1,y); | |
1392 | ||
1393 | input sel0,sel1; | |
1394 | input in0,in1; | |
1395 | ||
1396 | output y; | |
1397 | ||
1398 | reg y; | |
1399 | ||
1400 | always @(sel0 or sel1 or in0 or in1) | |
1401 | begin | |
1402 | case ( {sel1, sel0} ) | |
1403 | 2'b01: y <= in0; | |
1404 | 2'b10: y <= in1; | |
1405 | endcase | |
1406 | end | |
1407 | ||
1408 | endmodule | |
1409 | ||
1410 | // mh157021: lower level module definition (n2_core_pll_mux8_8x_cust) | |
1411 | // | |
1412 | // Last Modified: Friday Aug 26,2005 at 03:20:53 PM PDT | |
1413 | // | |
1414 | ||
1415 | module n2_core_pll_mux8_8x_cust(sel0 ,in2 ,sel2 ,sel5 ,in4 ,sel7 ,sel4 , | |
1416 | in1 ,dout ,in0 ,sel6 ,in5 ,in7 ,sel3 ,sel1 ,in3 ,in6 ); | |
1417 | output dout ; | |
1418 | input sel0 ; | |
1419 | input in2 ; | |
1420 | input sel2 ; | |
1421 | input sel5 ; | |
1422 | input in4 ; | |
1423 | input sel7 ; | |
1424 | input sel4 ; | |
1425 | input in1 ; | |
1426 | input in0 ; | |
1427 | input sel6 ; | |
1428 | input in5 ; | |
1429 | input in7 ; | |
1430 | input sel3 ; | |
1431 | input sel1 ; | |
1432 | input in3 ; | |
1433 | input in6 ; | |
1434 | ||
1435 | mux8 x1 ( | |
1436 | .sel0 (sel0), | |
1437 | .sel1 (sel1), | |
1438 | .sel2 (sel2), | |
1439 | .sel3 (sel3), | |
1440 | .sel4 (sel4), | |
1441 | .sel5 (sel5), | |
1442 | .sel6 (sel6), | |
1443 | .sel7 (sel7), | |
1444 | .in0 (in0), | |
1445 | .in1 (in1), | |
1446 | .in2 (in2), | |
1447 | .in3 (in3), | |
1448 | .in4 (in4), | |
1449 | .in5 (in5), | |
1450 | .in6 (in6), | |
1451 | .in7 (in7), | |
1452 | .muxtst (1'b0), // compile warning - mh157021 | |
1453 | .dout (dout) ); // compile error ".y (dout)" - mh157021 | |
1454 | ||
1455 | endmodule | |
1456 | ||
1457 | ||
1458 | ||
1459 | // mh157021: lower level module definition (n2_core_pll_charc_decoder_cust) | |
1460 | // | |
1461 | // Last Modified: Friday Aug 26,2005 at 03:19:12 PM PDT | |
1462 | // | |
1463 | ||
1464 | module n2_core_pll_charc_decoder_cust(a5_out ,a6_out ,a6 ,a5 ,a3a4 ,a4 , | |
1465 | a3 ,aoa1a2 ,a2 ,a1 ,a0 ); | |
1466 | output [1:0] a5_out ; | |
1467 | output [1:0] a6_out ; | |
1468 | output [3:0] a3a4 ; | |
1469 | output [7:0] aoa1a2 ; | |
1470 | input a6 ; | |
1471 | input a5 ; | |
1472 | input a4 ; | |
1473 | input a3 ; | |
1474 | input a2 ; | |
1475 | input a1 ; | |
1476 | input a0 ; | |
1477 | supply1 vdd ; | |
1478 | ||
1479 | wire net188 ; | |
1480 | wire net191 ; | |
1481 | wire net194 ; | |
1482 | wire net197 ; | |
1483 | wire a0_buf ; | |
1484 | wire a1_buf ; | |
1485 | wire a2_buf ; | |
1486 | wire a3_buf ; | |
1487 | wire a4_buf ; | |
1488 | wire net144 ; | |
1489 | wire net153 ; | |
1490 | wire a0_inv ; | |
1491 | wire a1_inv ; | |
1492 | wire a2_inv ; | |
1493 | wire a3_inv ; | |
1494 | wire a4_inv ; | |
1495 | wire net179 ; | |
1496 | ||
1497 | ||
1498 | n2_core_pll_and3_16x_cust x2 ( | |
1499 | .out (aoa1a2[2] ), | |
1500 | .in2 (a0_inv ), | |
1501 | .in1 (a1_buf ), | |
1502 | .in0 (a2_inv ) ); | |
1503 | n2_core_pll_and3_16x_cust x3 ( | |
1504 | .out (aoa1a2[3] ), | |
1505 | .in2 (a0_buf ), | |
1506 | .in1 (a1_buf ), | |
1507 | .in0 (a2_inv ) ); | |
1508 | n2_core_pll_inv_4x_cust x4 ( | |
1509 | .vdd_reg (vdd ), | |
1510 | .out (net197 ), | |
1511 | .in (a0 ) ); | |
1512 | n2_core_pll_inv_4x_cust x5 ( | |
1513 | .vdd_reg (vdd ), | |
1514 | .out (net188 ), | |
1515 | .in (a3 ) ); | |
1516 | n2_core_pll_buf_16x_cust x6 ( | |
1517 | .vdd_reg (vdd ), | |
1518 | .out (a2_buf ), | |
1519 | .in (a2 ) ); | |
1520 | n2_core_pll_buf_16x_cust x7 ( | |
1521 | .vdd_reg (vdd ), | |
1522 | .out (a3_buf ), | |
1523 | .in (a3 ) ); | |
1524 | n2_core_pll_and3_16x_cust x8 ( | |
1525 | .out (aoa1a2[4] ), | |
1526 | .in2 (a0_inv ), | |
1527 | .in1 (a1_inv ), | |
1528 | .in0 (a2_buf ) ); | |
1529 | n2_core_pll_and3_16x_cust x9 ( | |
1530 | .out (aoa1a2[5] ), | |
1531 | .in2 (a0_buf ), | |
1532 | .in1 (a1_inv ), | |
1533 | .in0 (a2_buf ) ); | |
1534 | n2_core_pll_and3_16x_cust x10 ( | |
1535 | .out (aoa1a2[6] ), | |
1536 | .in2 (a0_inv ), | |
1537 | .in1 (a1_buf ), | |
1538 | .in0 (a2_buf ) ); | |
1539 | n2_core_pll_and3_16x_cust x11 ( | |
1540 | .out (aoa1a2[7] ), | |
1541 | .in2 (a0_buf ), | |
1542 | .in1 (a1_buf ), | |
1543 | .in0 (a2_buf ) ); | |
1544 | n2_core_pll_and2_16x_cust x12 ( | |
1545 | .out (a3a4[0] ), | |
1546 | .in1 (a3_inv ), | |
1547 | .in0 (a4_inv ) ); | |
1548 | n2_core_pll_and2_16x_cust x13 ( | |
1549 | .out (a3a4[1] ), | |
1550 | .in1 (a3_buf ), | |
1551 | .in0 (a4_inv ) ); | |
1552 | n2_core_pll_buf_16x_cust x14 ( | |
1553 | .vdd_reg (vdd ), | |
1554 | .out (a1_buf ), | |
1555 | .in (a1 ) ); | |
1556 | n2_core_pll_buf_16x_cust x15 ( | |
1557 | .vdd_reg (vdd ), | |
1558 | .out (a0_buf ), | |
1559 | .in (a0 ) ); | |
1560 | n2_core_pll_buf_16x_cust x16 ( | |
1561 | .vdd_reg (vdd ), | |
1562 | .out (a2_inv ), | |
1563 | .in (net191 ) ); | |
1564 | n2_core_pll_buf_16x_cust x17 ( | |
1565 | .vdd_reg (vdd ), | |
1566 | .out (a1_inv ), | |
1567 | .in (net194 ) ); | |
1568 | n2_core_pll_buf_16x_cust x18 ( | |
1569 | .vdd_reg (vdd ), | |
1570 | .out (a0_inv ), | |
1571 | .in (net197 ) ); | |
1572 | n2_core_pll_inv_4x_cust x19 ( | |
1573 | .vdd_reg (vdd ), | |
1574 | .out (net194 ), | |
1575 | .in (a1 ) ); | |
1576 | n2_core_pll_inv_4x_cust x20 ( | |
1577 | .vdd_reg (vdd ), | |
1578 | .out (net191 ), | |
1579 | .in (a2 ) ); | |
1580 | n2_core_pll_buf_16x_cust x21 ( | |
1581 | .vdd_reg (vdd ), | |
1582 | .out (a4_buf ), | |
1583 | .in (a4 ) ); | |
1584 | n2_core_pll_buf_16x_cust x22 ( | |
1585 | .vdd_reg (vdd ), | |
1586 | .out (a4_inv ), | |
1587 | .in (net153 ) ); | |
1588 | n2_core_pll_buf_16x_cust x23 ( | |
1589 | .vdd_reg (vdd ), | |
1590 | .out (a3_inv ), | |
1591 | .in (net188 ) ); | |
1592 | n2_core_pll_inv_4x_cust x24 ( | |
1593 | .vdd_reg (vdd ), | |
1594 | .out (net153 ), | |
1595 | .in (a4 ) ); | |
1596 | n2_core_pll_buf_16x_cust x25 ( | |
1597 | .vdd_reg (vdd ), | |
1598 | .out (a5_out[0] ), | |
1599 | .in (net179 ) ); | |
1600 | n2_core_pll_and2_16x_cust x26 ( | |
1601 | .out (a3a4[2] ), | |
1602 | .in1 (a3_inv ), | |
1603 | .in0 (a4_buf ) ); | |
1604 | n2_core_pll_and2_16x_cust x27 ( | |
1605 | .out (a3a4[3] ), | |
1606 | .in1 (a3_buf ), | |
1607 | .in0 (a4_buf ) ); | |
1608 | n2_core_pll_buf_16x_cust x28 ( | |
1609 | .vdd_reg (vdd ), | |
1610 | .out (a6_out[0] ), | |
1611 | .in (net144 ) ); | |
1612 | n2_core_pll_buf_16x_cust x39 ( | |
1613 | .vdd_reg (vdd ), | |
1614 | .out (a6_out[1] ), | |
1615 | .in (a6 ) ); | |
1616 | n2_core_pll_buf_16x_cust x40 ( | |
1617 | .vdd_reg (vdd ), | |
1618 | .out (a5_out[1] ), | |
1619 | .in (a5 ) ); | |
1620 | n2_core_pll_inv_4x_cust x41 ( | |
1621 | .vdd_reg (vdd ), | |
1622 | .out (net144 ), | |
1623 | .in (a6 ) ); | |
1624 | n2_core_pll_inv_4x_cust x42 ( | |
1625 | .vdd_reg (vdd ), | |
1626 | .out (net179 ), | |
1627 | .in (a5 ) ); | |
1628 | n2_core_pll_and3_16x_cust x0 ( | |
1629 | .out (aoa1a2[0] ), | |
1630 | .in2 (a0_inv ), | |
1631 | .in1 (a1_inv ), | |
1632 | .in0 (a2_inv ) ); | |
1633 | n2_core_pll_and3_16x_cust x1 ( | |
1634 | .out (aoa1a2[1] ), | |
1635 | .in2 (a0_buf ), | |
1636 | .in1 (a1_inv ), | |
1637 | .in0 (a2_inv ) ); | |
1638 | endmodule | |
1639 | ||
1640 | ||
1641 | // mh157021: lower level module definition (n2_core_pll_charc_flops_cust) | |
1642 | // | |
1643 | // Last Modified: Friday Aug 26,2005 at 03:19:13 PM PDT | |
1644 | // | |
1645 | ||
1646 | module n2_core_pll_charc_flops_cust(data_in ,clk ,clk_l ,clk_rise1 , | |
1647 | clk_fall1 ,clk_rise2 ,clk_fall2 ,reset ,clk_rise4 ,clk_rise3 , | |
1648 | clk_fall3 ,clk_fall4 ); | |
1649 | output clk_rise1 ; | |
1650 | output clk_fall1 ; | |
1651 | output clk_rise2 ; | |
1652 | output clk_fall2 ; | |
1653 | output clk_rise4 ; | |
1654 | output clk_rise3 ; | |
1655 | output clk_fall3 ; | |
1656 | output clk_fall4 ; | |
1657 | input data_in ; | |
1658 | input clk ; | |
1659 | input clk_l ; | |
1660 | input reset ; | |
1661 | supply1 vdd ; | |
1662 | ||
1663 | wire net200 ; | |
1664 | wire net107 ; | |
1665 | wire net205 ; | |
1666 | wire net092 ; | |
1667 | wire net191 ; | |
1668 | wire net094 ; | |
1669 | wire net193 ; | |
1670 | wire net0186 ; | |
1671 | wire net213 ; | |
1672 | wire net116 ; | |
1673 | wire net214 ; | |
1674 | wire net88 ; | |
1675 | wire net221 ; | |
1676 | wire net227 ; | |
1677 | wire net229 ; | |
1678 | wire net130 ; | |
1679 | wire net231 ; | |
1680 | wire net233 ; | |
1681 | wire net137 ; | |
1682 | wire net235 ; | |
1683 | wire net237 ; | |
1684 | wire net239 ; | |
1685 | wire net142 ; | |
1686 | wire net241 ; | |
1687 | wire net243 ; | |
1688 | wire net245 ; | |
1689 | wire net247 ; | |
1690 | wire net149 ; | |
1691 | wire net249 ; | |
1692 | wire net151 ; | |
1693 | wire net255 ; | |
1694 | wire net256 ; | |
1695 | wire net158 ; | |
1696 | wire net257 ; | |
1697 | wire net0193 ; | |
1698 | wire net165 ; | |
1699 | wire net265 ; | |
1700 | wire net267 ; | |
1701 | wire net268 ; | |
1702 | wire net170 ; | |
1703 | wire net172 ; | |
1704 | wire net270 ; | |
1705 | wire net177 ; | |
1706 | wire net179 ; | |
1707 | wire net100 ; | |
1708 | ||
1709 | ||
1710 | n2_core_pll_flop_reset_new_1x_cust x2 ( | |
1711 | .vdd_reg (vdd ), | |
1712 | .reset_val_l (vdd ), | |
1713 | .d (data_in ), | |
1714 | .reset (net213 ), | |
1715 | .clk (clk_l ), | |
1716 | .q_l (net172 ), | |
1717 | .q (net170 ) ); | |
1718 | n2_core_pll_flop_reset_new_1x_cust x3 ( | |
1719 | .vdd_reg (vdd ), | |
1720 | .reset_val_l (vdd ), | |
1721 | .d (net233 ), | |
1722 | .reset (net213 ), | |
1723 | .clk (clk_l ), | |
1724 | .q_l (net165 ), | |
1725 | .q (net0193 ) ); | |
1726 | n2_core_pll_flop_reset_new_1x_cust x4 ( | |
1727 | .vdd_reg (vdd ), | |
1728 | .reset_val_l (vdd ), | |
1729 | .d (net239 ), | |
1730 | .reset (net213 ), | |
1731 | .clk (clk_l ), | |
1732 | .q_l (net257 ), | |
1733 | .q (net142 ) ); | |
1734 | n2_core_pll_flop_reset_new_1x_cust x5 ( | |
1735 | .vdd_reg (vdd ), | |
1736 | .reset_val_l (vdd ), | |
1737 | .d (net249 ), | |
1738 | .reset (net213 ), | |
1739 | .clk (clk ), | |
1740 | .q_l (net151 ), | |
1741 | .q (net149 ) ); | |
1742 | n2_core_pll_flop_reset_new_1x_cust x6 ( | |
1743 | .vdd_reg (vdd ), | |
1744 | .reset_val_l (vdd ), | |
1745 | .d (net231 ), | |
1746 | .reset (net213 ), | |
1747 | .clk (clk ), | |
1748 | .q_l (net158 ), | |
1749 | .q (net0186 ) ); | |
1750 | n2_core_pll_flop_reset_new_1x_cust x7 ( | |
1751 | .vdd_reg (vdd ), | |
1752 | .reset_val_l (vdd ), | |
1753 | .d (data_in ), | |
1754 | .reset (net213 ), | |
1755 | .clk (clk ), | |
1756 | .q_l (net179 ), | |
1757 | .q (net177 ) ); | |
1758 | n2_core_pll_flop_reset_new_1x_cust x8 ( | |
1759 | .vdd_reg (vdd ), | |
1760 | .reset_val_l (vdd ), | |
1761 | .d (data_in ), | |
1762 | .reset (net213 ), | |
1763 | .clk (clk ), | |
1764 | .q_l (net267 ), | |
1765 | .q (net100 ) ); | |
1766 | n2_core_pll_flop_reset_new_1x_cust x9 ( | |
1767 | .vdd_reg (vdd ), | |
1768 | .reset_val_l (vdd ), | |
1769 | .d (data_in ), | |
1770 | .reset (net213 ), | |
1771 | .clk (clk_l ), | |
1772 | .q_l (net268 ), | |
1773 | .q (net107 ) ); | |
1774 | n2_core_pll_flop_reset_new_1x_cust x10 ( | |
1775 | .vdd_reg (vdd ), | |
1776 | .reset_val_l (vdd ), | |
1777 | .d (net241 ), | |
1778 | .reset (net213 ), | |
1779 | .clk (clk_l ), | |
1780 | .q_l (net116 ), | |
1781 | .q (net094 ) ); | |
1782 | n2_core_pll_flop_reset_new_1x_cust x11 ( | |
1783 | .vdd_reg (vdd ), | |
1784 | .reset_val_l (vdd ), | |
1785 | .d (net245 ), | |
1786 | .reset (net213 ), | |
1787 | .clk (clk ), | |
1788 | .q_l (net265 ), | |
1789 | .q (net092 ) ); | |
1790 | n2_core_pll_bufi_4x_cust x12 ( | |
1791 | .vdd_reg (vdd ), | |
1792 | .out (net245 ), | |
1793 | .in (net267 ) ); | |
1794 | n2_core_pll_bufi_4x_cust x13 ( | |
1795 | .vdd_reg (vdd ), | |
1796 | .out (net247 ), | |
1797 | .in (net265 ) ); | |
1798 | n2_core_pll_bufi_4x_cust x14 ( | |
1799 | .vdd_reg (vdd ), | |
1800 | .out (net243 ), | |
1801 | .in (net116 ) ); | |
1802 | n2_core_pll_bufi_4x_cust x15 ( | |
1803 | .vdd_reg (vdd ), | |
1804 | .out (net241 ), | |
1805 | .in (net268 ) ); | |
1806 | n2_core_pll_bufi_4x_cust x17 ( | |
1807 | .vdd_reg (vdd ), | |
1808 | .out (net229 ), | |
1809 | .in (net255 ) ); | |
1810 | n2_core_pll_bufi_4x_cust x18 ( | |
1811 | .vdd_reg (vdd ), | |
1812 | .out (net227 ), | |
1813 | .in (net193 ) ); | |
1814 | n2_core_pll_bufi_4x_cust x19 ( | |
1815 | .vdd_reg (vdd ), | |
1816 | .out (net233 ), | |
1817 | .in (net172 ) ); | |
1818 | n2_core_pll_bufi_4x_cust x20 ( | |
1819 | .vdd_reg (vdd ), | |
1820 | .out (net231 ), | |
1821 | .in (net179 ) ); | |
1822 | n2_core_pll_bufi_4x_cust x21 ( | |
1823 | .vdd_reg (vdd ), | |
1824 | .out (net249 ), | |
1825 | .in (net158 ) ); | |
1826 | n2_core_pll_bufi_4x_cust x22 ( | |
1827 | .vdd_reg (vdd ), | |
1828 | .out (net239 ), | |
1829 | .in (net165 ) ); | |
1830 | n2_core_pll_bufi_4x_cust x23 ( | |
1831 | .vdd_reg (vdd ), | |
1832 | .out (net237 ), | |
1833 | .in (net257 ) ); | |
1834 | n2_core_pll_bufi_4x_cust x24 ( | |
1835 | .vdd_reg (vdd ), | |
1836 | .out (net235 ), | |
1837 | .in (net151 ) ); | |
1838 | n2_core_pll_buf_16x_cust x33 ( | |
1839 | .vdd_reg (vdd ), | |
1840 | .out (net213 ), | |
1841 | .in (reset ) ); | |
1842 | n2_core_pll_flop_reset_new_cust x34 ( | |
1843 | .vdd_reg (vdd ), | |
1844 | .reset_val_l (vdd ), | |
1845 | .d (net227 ), | |
1846 | .reset (net213 ), | |
1847 | .clk (clk_l ), | |
1848 | .q_l (net256 ), | |
1849 | .q (clk_fall2 ) ); | |
1850 | n2_core_pll_flop_reset_new_cust x35 ( | |
1851 | .vdd_reg (vdd ), | |
1852 | .reset_val_l (vdd ), | |
1853 | .d (net229 ), | |
1854 | .reset (net213 ), | |
1855 | .clk (clk ), | |
1856 | .q_l (net200 ), | |
1857 | .q (clk_rise2 ) ); | |
1858 | n2_core_pll_flop_reset_new_cust x37 ( | |
1859 | .vdd_reg (vdd ), | |
1860 | .reset_val_l (vdd ), | |
1861 | .d (data_in ), | |
1862 | .reset (net213 ), | |
1863 | .clk (clk_l ), | |
1864 | .q_l (net214 ), | |
1865 | .q (clk_fall1 ) ); | |
1866 | n2_core_pll_flop_reset_new_cust x38 ( | |
1867 | .vdd_reg (vdd ), | |
1868 | .reset_val_l (vdd ), | |
1869 | .d (data_in ), | |
1870 | .reset (net213 ), | |
1871 | .clk (clk ), | |
1872 | .q_l (net221 ), | |
1873 | .q (clk_rise1 ) ); | |
1874 | n2_core_pll_flop_reset_new_cust x41 ( | |
1875 | .vdd_reg (vdd ), | |
1876 | .reset_val_l (vdd ), | |
1877 | .d (net247 ), | |
1878 | .reset (net213 ), | |
1879 | .clk (clk ), | |
1880 | .q_l (net88 ), | |
1881 | .q (clk_rise3 ) ); | |
1882 | n2_core_pll_flop_reset_new_cust x42 ( | |
1883 | .vdd_reg (vdd ), | |
1884 | .reset_val_l (vdd ), | |
1885 | .d (net243 ), | |
1886 | .reset (net213 ), | |
1887 | .clk (clk_l ), | |
1888 | .q_l (net270 ), | |
1889 | .q (clk_fall3 ) ); | |
1890 | n2_core_pll_flop_reset_new_cust x49 ( | |
1891 | .vdd_reg (vdd ), | |
1892 | .reset_val_l (vdd ), | |
1893 | .d (net237 ), | |
1894 | .reset (net213 ), | |
1895 | .clk (clk_l ), | |
1896 | .q_l (net130 ), | |
1897 | .q (clk_fall4 ) ); | |
1898 | n2_core_pll_flop_reset_new_cust x50 ( | |
1899 | .vdd_reg (vdd ), | |
1900 | .reset_val_l (vdd ), | |
1901 | .d (net235 ), | |
1902 | .reset (net213 ), | |
1903 | .clk (clk ), | |
1904 | .q_l (net137 ), | |
1905 | .q (clk_rise4 ) ); | |
1906 | n2_core_pll_flop_reset_new_1x_cust x0 ( | |
1907 | .vdd_reg (vdd ), | |
1908 | .reset_val_l (vdd ), | |
1909 | .d (data_in ), | |
1910 | .reset (net213 ), | |
1911 | .clk (clk ), | |
1912 | .q_l (net255 ), | |
1913 | .q (net205 ) ); | |
1914 | n2_core_pll_flop_reset_new_1x_cust x1 ( | |
1915 | .vdd_reg (vdd ), | |
1916 | .reset_val_l (vdd ), | |
1917 | .d (data_in ), | |
1918 | .reset (net213 ), | |
1919 | .clk (clk_l ), | |
1920 | .q_l (net193 ), | |
1921 | .q (net191 ) ); | |
1922 | endmodule | |
1923 | ||
1924 | // mh157021: lower level module definition (n2_core_pll_charc_mux_cust) | |
1925 | // | |
1926 | // Last Modified: Friday Aug 26,2005 at 03:19:16 PM PDT | |
1927 | // | |
1928 | ||
1929 | module n2_core_pll_charc_mux_cust(clk_fall2 ,clk_fall3 ,clk_fall4 , | |
1930 | clk_fall1 ,clk_rise3 ,clk_rise2 ,clk_rise4 ,clk_rise1 ,mux_out1 , | |
1931 | mux_out2 ,a3a4_ ,aoa1a2_ ); | |
1932 | input [3:0] a3a4_ ; | |
1933 | input [7:0] aoa1a2_ ; | |
1934 | output mux_out1 ; | |
1935 | output mux_out2 ; | |
1936 | input clk_fall2 ; | |
1937 | input clk_fall3 ; | |
1938 | input clk_fall4 ; | |
1939 | input clk_fall1 ; | |
1940 | input clk_rise3 ; | |
1941 | input clk_rise2 ; | |
1942 | input clk_rise4 ; | |
1943 | input clk_rise1 ; | |
1944 | ||
1945 | wire [7:0] mux_in ; | |
1946 | wire [7:0] mux_in1 ; | |
1947 | ||
1948 | ||
1949 | n2_core_pll_mux4_8x_cust x18 ( | |
1950 | .sel2 (a3a4_[2] ), | |
1951 | .sel3 (a3a4_[3] ), | |
1952 | .in2 (clk_fall1 ), | |
1953 | .in3 (clk_rise2 ), | |
1954 | .sel0 (a3a4_[0] ), | |
1955 | .sel1 (a3a4_[1] ), | |
1956 | .dout (mux_in[0] ), | |
1957 | .in0 (clk_rise1 ), | |
1958 | .in1 (clk_rise1 ) ); | |
1959 | n2_core_pll_mux4_8x_cust x19 ( | |
1960 | .sel2 (a3a4_[2] ), | |
1961 | .sel3 (a3a4_[3] ), | |
1962 | .in2 (clk_rise1 ), | |
1963 | .in3 (clk_rise1 ), | |
1964 | .sel0 (a3a4_[0] ), | |
1965 | .sel1 (a3a4_[1] ), | |
1966 | .dout (mux_in1[0] ), | |
1967 | .in0 (clk_fall1 ), | |
1968 | .in1 (clk_rise2 ) ); | |
1969 | n2_core_pll_mux8_8x_cust x20 ( | |
1970 | .sel0 (aoa1a2_[0] ), | |
1971 | .in2 (mux_in[2] ), | |
1972 | .sel2 (aoa1a2_[2] ), | |
1973 | .sel5 (aoa1a2_[5] ), | |
1974 | .in4 (mux_in[4] ), | |
1975 | .sel7 (aoa1a2_[7] ), | |
1976 | .sel4 (aoa1a2_[4] ), | |
1977 | .in1 (mux_in[1] ), | |
1978 | .dout (mux_out1 ), | |
1979 | .in0 (mux_in[0] ), | |
1980 | .sel6 (aoa1a2_[6] ), | |
1981 | .in5 (mux_in[5] ), | |
1982 | .in7 (mux_in[7] ), | |
1983 | .sel3 (aoa1a2_[3] ), | |
1984 | .sel1 (aoa1a2_[1] ), | |
1985 | .in3 (mux_in[3] ), | |
1986 | .in6 (mux_in[6] ) ); | |
1987 | n2_core_pll_mux8_8x_cust x21 ( | |
1988 | .sel0 (aoa1a2_[0] ), | |
1989 | .in2 (mux_in1[2] ), | |
1990 | .sel2 (aoa1a2_[2] ), | |
1991 | .sel5 (aoa1a2_[5] ), | |
1992 | .in4 (mux_in1[4] ), | |
1993 | .sel7 (aoa1a2_[7] ), | |
1994 | .sel4 (aoa1a2_[4] ), | |
1995 | .in1 (mux_in1[1] ), | |
1996 | .dout (mux_out2 ), | |
1997 | .in0 (mux_in1[0] ), | |
1998 | .sel6 (aoa1a2_[6] ), | |
1999 | .in5 (mux_in1[5] ), | |
2000 | .in7 (mux_in1[7] ), | |
2001 | .sel3 (aoa1a2_[3] ), | |
2002 | .sel1 (aoa1a2_[1] ), | |
2003 | .in3 (mux_in1[3] ), | |
2004 | .in6 (mux_in1[6] ) ); | |
2005 | n2_core_pll_mux4_8x_cust x22 ( | |
2006 | .sel2 (a3a4_[2] ), | |
2007 | .sel3 (a3a4_[3] ), | |
2008 | .in2 (clk_rise2 ), | |
2009 | .in3 (clk_fall2 ), | |
2010 | .sel0 (a3a4_[0] ), | |
2011 | .sel1 (a3a4_[1] ), | |
2012 | .dout (mux_in[1] ), | |
2013 | .in0 (clk_fall1 ), | |
2014 | .in1 (clk_fall1 ) ); | |
2015 | n2_core_pll_mux4_8x_cust x23 ( | |
2016 | .sel2 (a3a4_[2] ), | |
2017 | .sel3 (a3a4_[3] ), | |
2018 | .in2 (clk_fall2 ), | |
2019 | .in3 (clk_rise3 ), | |
2020 | .sel0 (a3a4_[0] ), | |
2021 | .sel1 (a3a4_[1] ), | |
2022 | .dout (mux_in[2] ), | |
2023 | .in0 (clk_rise2 ), | |
2024 | .in1 (clk_rise2 ) ); | |
2025 | n2_core_pll_mux4_8x_cust x24 ( | |
2026 | .sel2 (a3a4_[2] ), | |
2027 | .sel3 (a3a4_[3] ), | |
2028 | .in2 (clk_rise3 ), | |
2029 | .in3 (clk_fall3 ), | |
2030 | .sel0 (a3a4_[0] ), | |
2031 | .sel1 (a3a4_[1] ), | |
2032 | .dout (mux_in[3] ), | |
2033 | .in0 (clk_fall2 ), | |
2034 | .in1 (clk_fall2 ) ); | |
2035 | n2_core_pll_mux4_8x_cust x25 ( | |
2036 | .sel2 (a3a4_[2] ), | |
2037 | .sel3 (a3a4_[3] ), | |
2038 | .in2 (clk_fall3 ), | |
2039 | .in3 (clk_rise4 ), | |
2040 | .sel0 (a3a4_[0] ), | |
2041 | .sel1 (a3a4_[1] ), | |
2042 | .dout (mux_in[4] ), | |
2043 | .in0 (clk_rise3 ), | |
2044 | .in1 (clk_rise3 ) ); | |
2045 | n2_core_pll_mux4_8x_cust x26 ( | |
2046 | .sel2 (a3a4_[2] ), | |
2047 | .sel3 (a3a4_[3] ), | |
2048 | .in2 (clk_rise4 ), | |
2049 | .in3 (clk_fall4 ), | |
2050 | .sel0 (a3a4_[0] ), | |
2051 | .sel1 (a3a4_[1] ), | |
2052 | .dout (mux_in[5] ), | |
2053 | .in0 (clk_fall3 ), | |
2054 | .in1 (clk_fall3 ) ); | |
2055 | n2_core_pll_mux4_8x_cust x27 ( | |
2056 | .sel2 (a3a4_[2] ), | |
2057 | .sel3 (a3a4_[3] ), | |
2058 | .in2 (clk_fall4 ), | |
2059 | .in3 (clk_rise1 ), | |
2060 | .sel0 (a3a4_[0] ), | |
2061 | .sel1 (a3a4_[1] ), | |
2062 | .dout (mux_in[6] ), | |
2063 | .in0 (clk_rise4 ), | |
2064 | .in1 (clk_rise4 ) ); | |
2065 | n2_core_pll_mux4_8x_cust x28 ( | |
2066 | .sel2 (a3a4_[2] ), | |
2067 | .sel3 (a3a4_[3] ), | |
2068 | .in2 (clk_rise1 ), | |
2069 | .in3 (clk_fall1 ), | |
2070 | .sel0 (a3a4_[0] ), | |
2071 | .sel1 (a3a4_[1] ), | |
2072 | .dout (mux_in[7] ), | |
2073 | .in0 (clk_fall4 ), | |
2074 | .in1 (clk_fall4 ) ); | |
2075 | n2_core_pll_mux4_8x_cust x29 ( | |
2076 | .sel2 (a3a4_[2] ), | |
2077 | .sel3 (a3a4_[3] ), | |
2078 | .in2 (clk_fall1 ), | |
2079 | .in3 (clk_fall1 ), | |
2080 | .sel0 (a3a4_[0] ), | |
2081 | .sel1 (a3a4_[1] ), | |
2082 | .dout (mux_in1[1] ), | |
2083 | .in0 (clk_rise2 ), | |
2084 | .in1 (clk_fall2 ) ); | |
2085 | n2_core_pll_mux4_8x_cust x30 ( | |
2086 | .sel2 (a3a4_[2] ), | |
2087 | .sel3 (a3a4_[3] ), | |
2088 | .in2 (clk_rise2 ), | |
2089 | .in3 (clk_rise2 ), | |
2090 | .sel0 (a3a4_[0] ), | |
2091 | .sel1 (a3a4_[1] ), | |
2092 | .dout (mux_in1[2] ), | |
2093 | .in0 (clk_fall2 ), | |
2094 | .in1 (clk_rise3 ) ); | |
2095 | n2_core_pll_mux4_8x_cust x31 ( | |
2096 | .sel2 (a3a4_[2] ), | |
2097 | .sel3 (a3a4_[3] ), | |
2098 | .in2 (clk_fall2 ), | |
2099 | .in3 (clk_fall2 ), | |
2100 | .sel0 (a3a4_[0] ), | |
2101 | .sel1 (a3a4_[1] ), | |
2102 | .dout (mux_in1[3] ), | |
2103 | .in0 (clk_rise3 ), | |
2104 | .in1 (clk_fall3 ) ); | |
2105 | n2_core_pll_mux4_8x_cust x32 ( | |
2106 | .sel2 (a3a4_[2] ), | |
2107 | .sel3 (a3a4_[3] ), | |
2108 | .in2 (clk_rise3 ), | |
2109 | .in3 (clk_rise3 ), | |
2110 | .sel0 (a3a4_[0] ), | |
2111 | .sel1 (a3a4_[1] ), | |
2112 | .dout (mux_in1[4] ), | |
2113 | .in0 (clk_fall3 ), | |
2114 | .in1 (clk_rise4 ) ); | |
2115 | n2_core_pll_mux4_8x_cust x33 ( | |
2116 | .sel2 (a3a4_[2] ), | |
2117 | .sel3 (a3a4_[3] ), | |
2118 | .in2 (clk_fall3 ), | |
2119 | .in3 (clk_fall3 ), | |
2120 | .sel0 (a3a4_[0] ), | |
2121 | .sel1 (a3a4_[1] ), | |
2122 | .dout (mux_in1[5] ), | |
2123 | .in0 (clk_rise4 ), | |
2124 | .in1 (clk_fall4 ) ); | |
2125 | n2_core_pll_mux4_8x_cust x34 ( | |
2126 | .sel2 (a3a4_[2] ), | |
2127 | .sel3 (a3a4_[3] ), | |
2128 | .in2 (clk_rise4 ), | |
2129 | .in3 (clk_rise4 ), | |
2130 | .sel0 (a3a4_[0] ), | |
2131 | .sel1 (a3a4_[1] ), | |
2132 | .dout (mux_in1[6] ), | |
2133 | .in0 (clk_fall4 ), | |
2134 | .in1 (clk_rise1 ) ); | |
2135 | n2_core_pll_mux4_8x_cust x35 ( | |
2136 | .sel2 (a3a4_[2] ), | |
2137 | .sel3 (a3a4_[3] ), | |
2138 | .in2 (clk_fall4 ), | |
2139 | .in3 (clk_fall4 ), | |
2140 | .sel0 (a3a4_[0] ), | |
2141 | .sel1 (a3a4_[1] ), | |
2142 | .dout (mux_in1[7] ), | |
2143 | .in0 (clk_rise1 ), | |
2144 | .in1 (clk_fall1 ) ); | |
2145 | endmodule | |
2146 | ||
2147 | // mh157021: lower level module definition (n2_core_pll_mux4_8x_cust) | |
2148 | // | |
2149 | // Last Modified: Friday Aug 26,2005 at 03:20:52 PM PDT | |
2150 | // | |
2151 | ||
2152 | module n2_core_pll_mux4_8x_cust(sel2 ,sel3 ,in2 ,in3 ,sel0 ,sel1 ,dout , | |
2153 | in0 ,in1 ); | |
2154 | output dout ; | |
2155 | input sel2 ; | |
2156 | input sel3 ; | |
2157 | input in2 ; | |
2158 | input in3 ; | |
2159 | input sel0 ; | |
2160 | input sel1 ; | |
2161 | input in0 ; | |
2162 | input in1 ; | |
2163 | ||
2164 | mux4 x1 ( | |
2165 | .in0 (in0), | |
2166 | .in1 (in1), | |
2167 | .in2 (in2), | |
2168 | .in3 (in3), | |
2169 | .sel0 (sel0), | |
2170 | .sel1 (sel1), | |
2171 | .sel2 (sel2), | |
2172 | .sel3 (sel3), | |
2173 | .muxtst (1'b0), // compile warning - mh157021 | |
2174 | .dout (dout) ); // compile error ".y (dout)" - mh157021 | |
2175 | ||
2176 | endmodule | |
2177 | ||
2178 | ||
2179 | ||
2180 | // mh157021: lower level module definition (n2_core_pll_div4_new_cust) | |
2181 | // | |
2182 | // Last Modified: Friday Aug 26,2005 at 03:20:16 PM PDT | |
2183 | // | |
2184 | ||
2185 | module n2_core_pll_div4_new_cust(clk ,arst_l ,clk_div_out ); | |
2186 | output clk_div_out ; | |
2187 | input clk ; | |
2188 | input arst_l ; | |
2189 | supply1 vdd ; | |
2190 | ||
2191 | wire div4_l ; | |
2192 | wire clk_div ; | |
2193 | wire n1 ; | |
2194 | wire n2 ; | |
2195 | wire n3 ; | |
2196 | wire n4 ; | |
2197 | wire net19 ; | |
2198 | wire net038 ; | |
2199 | wire net26 ; | |
2200 | wire net33 ; | |
2201 | wire clk_div_l ; | |
2202 | wire div2_l ; | |
2203 | ||
2204 | ||
2205 | n2_core_pll_inv_8x_cust x2 ( | |
2206 | .vdd_reg (vdd ), | |
2207 | .out (clk_div_l ), | |
2208 | .in (clk_div ) ); | |
2209 | cl_u1_inv_4x x3 ( | |
2210 | .out (net038 ), | |
2211 | .in (arst_l ) ); | |
2212 | n2_core_pll_flop_reset_new_cust x4 ( | |
2213 | .vdd_reg (vdd ), | |
2214 | .reset_val_l (vdd ), | |
2215 | .d (n2 ), | |
2216 | .reset (net038 ), | |
2217 | .clk (clk ), | |
2218 | .q_l (div2_l ), | |
2219 | .q (net33 ) ); | |
2220 | n2_core_pll_flop_reset_new_cust x5 ( | |
2221 | .vdd_reg (vdd ), | |
2222 | .reset_val_l (vdd ), | |
2223 | .d (n4 ), | |
2224 | .reset (net038 ), | |
2225 | .clk (div2_l ), | |
2226 | .q_l (div4_l ), | |
2227 | .q (net26 ) ); | |
2228 | n2_core_pll_flop_reset_new_cust x6 ( | |
2229 | .vdd_reg (vdd ), | |
2230 | .reset_val_l (vdd ), | |
2231 | .d (div4_l ), | |
2232 | .reset (net038 ), | |
2233 | .clk (clk ), | |
2234 | .q_l (clk_div ), | |
2235 | .q (net19 ) ); | |
2236 | n2_core_pll_buf_2x_cust x9 ( | |
2237 | .vdd_reg (vdd ), | |
2238 | .out (n2 ), | |
2239 | .in (n1 ) ); | |
2240 | n2_core_pll_buf_2x_cust x10 ( | |
2241 | .vdd_reg (vdd ), | |
2242 | .out (n3 ), | |
2243 | .in (div4_l ) ); | |
2244 | n2_core_pll_buf_2x_cust x11 ( | |
2245 | .vdd_reg (vdd ), | |
2246 | .out (n4 ), | |
2247 | .in (n3 ) ); | |
2248 | n2_core_pll_buf_2x_cust x0 ( | |
2249 | .vdd_reg (vdd ), | |
2250 | .out (n1 ), | |
2251 | .in (div2_l ) ); | |
2252 | n2_core_pll_inv_32x_cust x1 ( | |
2253 | .vdd_reg (vdd ), | |
2254 | .out (clk_div_out ), | |
2255 | .in (clk_div_l ) ); | |
2256 | endmodule | |
2257 | ||
2258 | ||
2259 | // mh157021: lower level module definition (n2_core_pll_and2_16x_cust) | |
2260 | // | |
2261 | // Last Modified: Friday Aug 26,2005 at 03:18:55 PM PDT | |
2262 | // | |
2263 | ||
2264 | module n2_core_pll_and2_16x_cust(out ,in1 ,in0 ); | |
2265 | output out ; | |
2266 | input in1 ; | |
2267 | input in0 ; | |
2268 | supply1 vdd ; | |
2269 | wire vss = 1'b0; | |
2270 | ||
2271 | assign out = in0 & in1; | |
2272 | ||
2273 | endmodule | |
2274 | ||
2275 | // mh157021: lower level module definition (n2_core_pll_and3_16x_cust) | |
2276 | // | |
2277 | // Last Modified: Friday Aug 26,2005 at 03:18:56 PM PDT | |
2278 | // | |
2279 | ||
2280 | module n2_core_pll_and3_16x_cust(out ,in2 ,in1 ,in0 ); | |
2281 | output out ; | |
2282 | input in2 ; | |
2283 | input in1 ; | |
2284 | input in0 ; | |
2285 | supply1 vdd ; | |
2286 | wire vss = 1'b0; | |
2287 | ||
2288 | assign out = (in0 & in1 & in2); | |
2289 | ||
2290 | endmodule | |
2291 | ||
2292 | ||
2293 | // mh157021: lower level module definition (n2_core_pll_bufi_4x_cust) | |
2294 | // | |
2295 | // Last Modified: Friday Aug 26,2005 at 03:19:07 PM PDT | |
2296 | // | |
2297 | ||
2298 | module n2_core_pll_bufi_4x_cust(vdd_reg ,out ,in ); | |
2299 | output out ; | |
2300 | input vdd_reg ; | |
2301 | input in ; | |
2302 | wire vss = 1'b0; | |
2303 | ||
2304 | wire out; | |
2305 | ||
2306 | assign out = ~in; | |
2307 | ||
2308 | endmodule | |
2309 | ||
2310 | ||
2311 | ||
2312 | // | |
2313 | // Last Modified: Friday Aug 26,2005 at 03:18:51 PM PDT | |
2314 | // | |
2315 | ||
2316 | module n2_core_pll_4bit_counter_charc_cust(clk ,reset ,cnt3 ,qout_0 , | |
2317 | qout_1 ,qout_2 ,qout_3 ,count_out ,cnt1 ,cnt2 ,cnt0 ); | |
2318 | output qout_0 ; | |
2319 | output qout_1 ; | |
2320 | output qout_2 ; | |
2321 | output qout_3 ; | |
2322 | output count_out ; | |
2323 | input clk ; | |
2324 | input reset ; | |
2325 | input cnt3 ; | |
2326 | input cnt1 ; | |
2327 | input cnt2 ; | |
2328 | input cnt0 ; | |
2329 | supply1 vdd ; | |
2330 | wire vss = 1'b0; | |
2331 | ||
2332 | wire net115 ; | |
2333 | wire net88 ; | |
2334 | wire net121 ; | |
2335 | wire net127 ; | |
2336 | wire sel ; | |
2337 | wire net133 ; | |
2338 | wire nand_out ; | |
2339 | wire zero_0 ; | |
2340 | wire zero_1 ; | |
2341 | wire zero_2 ; | |
2342 | wire zero_3 ; | |
2343 | wire sel_b ; | |
2344 | wire din_0 ; | |
2345 | wire din_1 ; | |
2346 | wire din_2 ; | |
2347 | wire din_3 ; | |
2348 | wire next_0 ; | |
2349 | wire next_1 ; | |
2350 | wire next_2 ; | |
2351 | wire next_3 ; | |
2352 | ||
2353 | ||
2354 | n2_core_pll_flop_reset_new_cust x2 ( | |
2355 | .vdd_reg (vdd ), | |
2356 | .reset_val_l (vss ), | |
2357 | .d (din_1 ), | |
2358 | .reset (reset ), | |
2359 | .clk (clk ), | |
2360 | .q_l (qout_1 ), | |
2361 | .q (zero_1 ) ); | |
2362 | n2_core_pll_tpm_muxa_cust x3 ( | |
2363 | .opb (net127 ), | |
2364 | .op (din_0 ), | |
2365 | .d0 (next_0 ), | |
2366 | .d1 (cnt0 ), | |
2367 | .sel (sel ), | |
2368 | .sel_b (sel_b ) ); | |
2369 | n2_core_pll_flop_reset_new_cust x4 ( | |
2370 | .vdd_reg (vdd ), | |
2371 | .reset_val_l (vss ), | |
2372 | .d (din_2 ), | |
2373 | .reset (reset ), | |
2374 | .clk (clk ), | |
2375 | .q_l (qout_2 ), | |
2376 | .q (zero_2 ) ); | |
2377 | n2_core_pll_flop_reset_new_cust x5 ( | |
2378 | .vdd_reg (vdd ), | |
2379 | .reset_val_l (vss ), | |
2380 | .d (din_3 ), | |
2381 | .reset (reset ), | |
2382 | .clk (clk ), | |
2383 | .q_l (qout_3 ), | |
2384 | .q (zero_3 ) ); | |
2385 | n2_core_pll_tpm_muxa_cust x6 ( | |
2386 | .opb (net133 ), | |
2387 | .op (din_1 ), | |
2388 | .d0 (next_1 ), | |
2389 | .d1 (cnt1 ), | |
2390 | .sel (sel ), | |
2391 | .sel_b (sel_b ) ); | |
2392 | n2_core_pll_tpm_muxa_cust x7 ( | |
2393 | .opb (net121 ), | |
2394 | .op (din_2 ), | |
2395 | .d0 (next_2 ), | |
2396 | .d1 (cnt2 ), | |
2397 | .sel (sel ), | |
2398 | .sel_b (sel_b ) ); | |
2399 | n2_core_pll_tpm_muxa_cust x8 ( | |
2400 | .opb (net115 ), | |
2401 | .op (din_3 ), | |
2402 | .d0 (next_3 ), | |
2403 | .d1 (cnt3 ), | |
2404 | .sel (sel ), | |
2405 | .sel_b (sel_b ) ); | |
2406 | n2_core_pll_inv_8x_cust x13 ( | |
2407 | .vdd_reg (vdd ), | |
2408 | .out (sel ), | |
2409 | .in (nand_out ) ); | |
2410 | n2_core_pll_inv_8x_cust x14 ( | |
2411 | .vdd_reg (vdd ), | |
2412 | .out (sel_b ), | |
2413 | .in (net88 ) ); | |
2414 | n2_core_pll_buf_8x_cust x15 ( | |
2415 | .vdd_reg (vdd ), | |
2416 | .out (count_out ), | |
2417 | .in (nand_out ) ); | |
2418 | n2_core_pll_inv_4x_cust x16 ( | |
2419 | .vdd_reg (vdd ), | |
2420 | .out (net88 ), | |
2421 | .in (nand_out ) ); | |
2422 | n2_core_pll_nand4_4x_cust x18 ( | |
2423 | .in3 (qout_3 ), | |
2424 | .out (nand_out ), | |
2425 | .in2 (qout_2 ), | |
2426 | .in1 (qout_1 ), | |
2427 | .in0 (qout_0 ) ); | |
2428 | n2_core_pll_flop_reset_new_cust x0 ( | |
2429 | .vdd_reg (vdd ), | |
2430 | .reset_val_l (vss ), | |
2431 | .d (din_0 ), | |
2432 | .reset (reset ), | |
2433 | .clk (clk ), | |
2434 | .q_l (qout_0 ), | |
2435 | .q (zero_0 ) ); | |
2436 | n2_core_pll_4bit_counter_next_cust x1 ( | |
2437 | .q3 (zero_3 ), | |
2438 | .q0b (qout_0 ), | |
2439 | .q3b (qout_3 ), | |
2440 | .d3 (next_3 ), | |
2441 | .q1b (qout_1 ), | |
2442 | .q2b (qout_2 ), | |
2443 | .d2 (next_2 ), | |
2444 | .d0 (next_0 ), | |
2445 | .q2 (zero_2 ), | |
2446 | .q0 (zero_0 ), | |
2447 | .q1 (zero_1 ), | |
2448 | .d1 (next_1 ) ); | |
2449 | endmodule | |
2450 | ||
2451 | ||
2452 | ||
2453 | // | |
2454 | // Last Modified: Friday Aug 26,2005 at 03:20:59 PM PDT | |
2455 | // | |
2456 | ||
2457 | module n2_core_pll_nand4_4x_cust(in3 ,out ,in2 ,in1 ,in0 ); | |
2458 | output out ; | |
2459 | input in3 ; | |
2460 | input in2 ; | |
2461 | input in1 ; | |
2462 | input in0 ; | |
2463 | supply1 vdd ; | |
2464 | wire vss = 1'b0; | |
2465 | ||
2466 | assign out = ~(in0 & in1 & in2 & in3); | |
2467 | ||
2468 | endmodule | |
2469 | ||
2470 | // | |
2471 | // Last Modified: Friday Aug 26,2005 at 03:20:19 PM PDT | |
2472 | // | |
2473 | ||
2474 | module n2_core_pll_flop_reset_new_1x_cust(vdd_reg ,reset_val_l ,d ,reset | |
2475 | ,clk ,q_l ,q ); | |
2476 | output q_l ; | |
2477 | output q ; | |
2478 | input vdd_reg ; | |
2479 | input reset_val_l ; | |
2480 | input d ; | |
2481 | input reset ; | |
2482 | input clk ; | |
2483 | wire vss = 1'b0; | |
2484 | ||
2485 | reg q; | |
2486 | ||
2487 | always | |
2488 | @( posedge clk or posedge reset ) | |
2489 | if ( reset ) | |
2490 | q <= !reset_val_l; | |
2491 | else | |
2492 | q <= d; | |
2493 | ||
2494 | assign q_l = !q; | |
2495 | ||
2496 | endmodule | |
2497 | ||
2498 | // | |
2499 | // Last Modified: Tuesday Sep 6,2005 at 02:50:02 PM PDT | |
2500 | // | |
2501 | ||
2502 | module n2_core_pll_4bit_counter_next_cust(q3 ,q0b ,q3b ,d3 ,q1b ,q2b ,d2 | |
2503 | ,d0 ,q2 ,q0 ,q1 ,d1 ); | |
2504 | output d3 ; | |
2505 | output d2 ; | |
2506 | output d0 ; | |
2507 | output d1 ; | |
2508 | input q3 ; | |
2509 | input q0b ; | |
2510 | input q3b ; | |
2511 | input q1b ; | |
2512 | input q2b ; | |
2513 | input q2 ; | |
2514 | input q0 ; | |
2515 | input q1 ; | |
2516 | supply1 vdd ; | |
2517 | ||
2518 | wire net31 ; | |
2519 | wire net34 ; | |
2520 | wire net53 ; | |
2521 | ||
2522 | ||
2523 | cl_u1_xnor2_4x x2 ( | |
2524 | .out (d2 ), | |
2525 | .in0 (q2b ), | |
2526 | .in1 (net34 ) ); | |
2527 | cl_u1_xnor2_4x x3 ( | |
2528 | .out (d3 ), | |
2529 | .in0 (q3b ), | |
2530 | .in1 (net53 ) ); | |
2531 | cl_u1_nor2_2x x4 ( | |
2532 | .out (net31 ), | |
2533 | .in1 (vdd ), | |
2534 | .in0 (q3 ) ); | |
2535 | cl_u1_nor2_2x xi45 ( | |
2536 | .out (net34 ), | |
2537 | .in1 (q0 ), | |
2538 | .in0 (q1 ) ); | |
2539 | cl_u1_nor3_2x xi46 ( | |
2540 | .out (net53 ), | |
2541 | .in2 (q0 ), | |
2542 | .in1 (q1 ), | |
2543 | .in0 (q2 ) ); | |
2544 | cl_u1_xnor2_4x x0 ( | |
2545 | .out (d0 ), | |
2546 | .in0 (q0b ), | |
2547 | .in1 (vdd ) ); | |
2548 | cl_u1_xnor2_4x x1 ( | |
2549 | .out (d1 ), | |
2550 | .in0 (q1b ), | |
2551 | .in1 (q0b ) ); | |
2552 | endmodule | |
2553 | ||
2554 | ||
2555 | // | |
2556 | // Last Modified: Friday Aug 26,2005 at 03:21:53 PM PDT | |
2557 | // | |
2558 | ||
2559 | module n2_core_pll_tpm_muxa_cust(opb ,op ,d0 ,d1 ,sel ,sel_b ); | |
2560 | output opb ; | |
2561 | output op ; | |
2562 | input d0 ; | |
2563 | input d1 ; | |
2564 | input sel ; | |
2565 | input sel_b ; | |
2566 | supply1 vdd ; | |
2567 | wire vss = 1'b0; | |
2568 | ||
2569 | mux2 x1 ( | |
2570 | .sel0 (sel_b), | |
2571 | .sel1 (sel), | |
2572 | .in0 (d0), | |
2573 | .in1 (d1), | |
2574 | .y (op) ); | |
2575 | ||
2576 | assign opb = ~op; | |
2577 | ||
2578 | endmodule | |
2579 | ||
2580 | ||
2581 | ||
2582 | // | |
2583 | // Last Modified: Friday Aug 26,2005 at 03:21:16 PM PDT | |
2584 | // | |
2585 | ||
2586 | module n2_core_pll_pecl_cust(vdd_reg ,fb_ck ,pecl_p ,pecl_n ,hdr_p , | |
2587 | ref_ck ,hdr_n ); | |
2588 | output fb_ck ; | |
2589 | output ref_ck ; | |
2590 | input pecl_p ; | |
2591 | input pecl_n ; | |
2592 | input hdr_p ; | |
2593 | input hdr_n ; | |
2594 | inout vdd_reg ; | |
2595 | wire vss = 1'b0; | |
2596 | ||
2597 | assign ref_ck = pecl_p; | |
2598 | assign fb_ck = hdr_p; | |
2599 | ||
2600 | endmodule | |
2601 | ||
2602 | // | |
2603 | // Last Modified: Friday Aug 26,2005 at 03:21:12 PM PDT | |
2604 | // | |
2605 | ||
2606 | module n2_core_pll_pecl_bypass_clk_cust(phase_ck ,pecl_p ,pecl_n ); | |
2607 | output phase_ck ; | |
2608 | input pecl_p ; | |
2609 | input pecl_n ; | |
2610 | supply1 vdd ; | |
2611 | ||
2612 | assign phase_ck = pecl_p; // pecl buffer model - mh157021 | |
2613 | ||
2614 | endmodule | |
2615 | ||
2616 | ||
2617 | // | |
2618 | // Last Modified: Friday Aug 26,2005 at 03:21:24 PM PDT | |
2619 | // | |
2620 | ||
2621 | module n2_core_pll_pfd_cust(vdd_reg ,f_buf ,f_buf_l ,fast_l ,clamp_fltr | |
2622 | ,s_buf ,s_buf_l ,slow_l ,slow ,fast ,pfd_reset ,fb ,ref ); | |
2623 | output f_buf ; | |
2624 | output f_buf_l ; | |
2625 | output fast_l ; | |
2626 | output s_buf ; | |
2627 | output s_buf_l ; | |
2628 | output slow_l ; | |
2629 | output slow ; | |
2630 | output fast ; | |
2631 | output pfd_reset ; | |
2632 | input vdd_reg ; | |
2633 | input clamp_fltr ; | |
2634 | input fb ; | |
2635 | input ref ; | |
2636 | ||
2637 | endmodule | |
2638 | ||
2639 | ||
2640 | // | |
2641 | // Last Modified: Friday Aug 26,2005 at 03:21:38 PM PDT | |
2642 | // | |
2643 | ||
2644 | module n2_core_pll_se2diff_mux_cust(vdd_reg ,in1 ,sel ,out ,in0 ,out_l | |
2645 | ); | |
2646 | output out ; | |
2647 | output out_l ; | |
2648 | input vdd_reg ; | |
2649 | input in1 ; | |
2650 | input sel ; | |
2651 | input in0 ; | |
2652 | wire vss = 1'b0; | |
2653 | ||
2654 | assign out = sel ? in1 : in0; | |
2655 | assign out_l = ~out; | |
2656 | ||
2657 | endmodule | |
2658 | ||
2659 | ||
2660 | // | |
2661 | // Last Modified: Friday Aug 26,2005 at 03:22:10 PM PDT | |
2662 | // | |
2663 | ||
2664 | module n2_core_pll_vdd_xing_buf_32x_cust(vdd_reg ,out ,in ); | |
2665 | output out ; | |
2666 | input vdd_reg ; | |
2667 | input in ; | |
2668 | wire vss = 1'b0; | |
2669 | ||
2670 | assign out = in; | |
2671 | ||
2672 | endmodule | |
2673 | ||
2674 | ||
2675 | // | |
2676 | // Last Modified: Friday Aug 26,2005 at 03:21:47 PM PDT | |
2677 | // | |
2678 | ||
2679 | module n2_core_pll_tpm_cust(reset ,ip ,vdd_reg ,op ,sel ,div_ck_i , | |
2680 | pwr_rst ,div_ck ,vco_ck ); | |
2681 | output [5:0] op ; | |
2682 | input [5:0] ip ; | |
2683 | output sel ; | |
2684 | output div_ck ; | |
2685 | input reset ; | |
2686 | input vdd_reg ; | |
2687 | input div_ck_i ; | |
2688 | input pwr_rst ; | |
2689 | input vco_ck ; | |
2690 | wire vss = 1'b0; | |
2691 | ||
2692 | wire net183 ; | |
2693 | wire nz_2 ; | |
2694 | wire net201 ; | |
2695 | wire net282 ; | |
2696 | wire nz_3 ; | |
2697 | wire nz_4 ; | |
2698 | wire nz_5 ; | |
2699 | wire net186 ; | |
2700 | wire net205 ; | |
2701 | wire net189 ; | |
2702 | wire f4q ; | |
2703 | wire f5d ; | |
2704 | wire net195 ; | |
2705 | wire vco_ckb ; | |
2706 | wire vco_ckd ; | |
2707 | wire net198 ; | |
2708 | wire f5q ; | |
2709 | wire net219 ; | |
2710 | wire f_gate ; | |
2711 | wire r_gate ; | |
2712 | wire reset_d ; | |
2713 | wire net235 ; | |
2714 | wire zero_0 ; | |
2715 | wire net236 ; | |
2716 | wire zero_1 ; | |
2717 | wire zero_2 ; | |
2718 | wire f0d ; | |
2719 | wire zero_3 ; | |
2720 | wire zero_4 ; | |
2721 | wire zero_5 ; | |
2722 | wire sel_b ; | |
2723 | wire f0q ; | |
2724 | wire net147 ; | |
2725 | wire f1d ; | |
2726 | wire not_zero ; | |
2727 | wire net252 ; | |
2728 | wire net256 ; | |
2729 | wire net159 ; | |
2730 | wire f1q ; | |
2731 | wire f2d ; | |
2732 | wire nzero_0 ; | |
2733 | wire nzero_1 ; | |
2734 | wire net162 ; | |
2735 | wire nzero_2 ; | |
2736 | wire nzero_3 ; | |
2737 | wire nzero_4 ; | |
2738 | wire nzero_5 ; | |
2739 | wire f2q ; | |
2740 | wire next0 ; | |
2741 | wire next1 ; | |
2742 | wire next2 ; | |
2743 | wire next3 ; | |
2744 | wire f3d ; | |
2745 | wire next4 ; | |
2746 | wire next5 ; | |
2747 | wire net171 ; | |
2748 | wire nip0 ; | |
2749 | wire nip1 ; | |
2750 | wire nip2 ; | |
2751 | wire nip3 ; | |
2752 | wire nip4 ; | |
2753 | wire nip5 ; | |
2754 | wire net0501 ; | |
2755 | wire f3q ; | |
2756 | wire net0502 ; | |
2757 | wire net0503 ; | |
2758 | wire net0504 ; | |
2759 | wire f4d ; | |
2760 | wire net0505 ; | |
2761 | wire net0506 ; | |
2762 | wire nz_0 ; | |
2763 | wire nz_1 ; | |
2764 | ||
2765 | ||
2766 | n2_core_pll_buf_4x_cust x2 ( | |
2767 | .vdd_reg (vdd_reg ), | |
2768 | .out (net205 ), | |
2769 | .in (ip[0] ) ); | |
2770 | n2_core_pll_buf_16x_cust x4 ( | |
2771 | .vdd_reg (vdd_reg ), | |
2772 | .out (reset_d ), | |
2773 | .in (reset ) ); | |
2774 | n2_core_pll_tpm_mux_cust x5 ( | |
2775 | .opb (nzero_0 ), | |
2776 | .vdd_reg (vdd_reg ), | |
2777 | .op (nz_0 ), | |
2778 | .d0 (ip[0] ), | |
2779 | .d1 (nip0 ), | |
2780 | .sel (net256 ), | |
2781 | .sel_b (net282 ) ); | |
2782 | n2_core_pll_buf_8x_cust x6 ( | |
2783 | .vdd_reg (vdd_reg ), | |
2784 | .out (net282 ), | |
2785 | .in (pwr_rst ) ); | |
2786 | n2_core_pll_inv_8x_cust x7 ( | |
2787 | .vdd_reg (vdd_reg ), | |
2788 | .out (net256 ), | |
2789 | .in (pwr_rst ) ); | |
2790 | n2_core_pll_buf_4x_cust x8 ( | |
2791 | .vdd_reg (vdd_reg ), | |
2792 | .out (net183 ), | |
2793 | .in (ip[1] ) ); | |
2794 | n2_core_pll_buf_4x_cust x9 ( | |
2795 | .vdd_reg (vdd_reg ), | |
2796 | .out (net195 ), | |
2797 | .in (ip[2] ) ); | |
2798 | n2_core_pll_buf_4x_cust x10 ( | |
2799 | .vdd_reg (vdd_reg ), | |
2800 | .out (net159 ), | |
2801 | .in (ip[3] ) ); | |
2802 | n2_core_pll_buf_4x_cust x11 ( | |
2803 | .vdd_reg (vdd_reg ), | |
2804 | .out (net147 ), | |
2805 | .in (ip[4] ) ); | |
2806 | n2_core_pll_buf_4x_cust x12 ( | |
2807 | .vdd_reg (vdd_reg ), | |
2808 | .out (net171 ), | |
2809 | .in (ip[5] ) ); | |
2810 | n2_core_pll_buf_8x_cust x13 ( | |
2811 | .vdd_reg (vdd_reg ), | |
2812 | .out (op[0] ), | |
2813 | .in (nip0 ) ); | |
2814 | n2_core_pll_buf_8x_cust x14 ( | |
2815 | .vdd_reg (vdd_reg ), | |
2816 | .out (op[1] ), | |
2817 | .in (nip1 ) ); | |
2818 | n2_core_pll_buf_8x_cust x15 ( | |
2819 | .vdd_reg (vdd_reg ), | |
2820 | .out (op[2] ), | |
2821 | .in (nip2 ) ); | |
2822 | n2_core_pll_tpm_next_new_cust x16 ( | |
2823 | .vdd_reg (vdd_reg ), | |
2824 | .d5 (next5 ), | |
2825 | .q0b (zero_0 ), | |
2826 | .q3b (zero_3 ), | |
2827 | .d3 (next3 ), | |
2828 | .q5b (zero_5 ), | |
2829 | .q1b (zero_1 ), | |
2830 | .q2b (zero_2 ), | |
2831 | .d2 (next2 ), | |
2832 | .d0 (next0 ), | |
2833 | .d4 (next4 ), | |
2834 | .q2 (f2q ), | |
2835 | .q0 (f0q ), | |
2836 | .q1 (f1q ), | |
2837 | .d1 (next1 ), | |
2838 | .q4b (zero_4 ) ); | |
2839 | n2_core_pll_tpm_mux_cust x17 ( | |
2840 | .opb (nzero_1 ), | |
2841 | .vdd_reg (vdd_reg ), | |
2842 | .op (nz_1 ), | |
2843 | .d0 (ip[1] ), | |
2844 | .d1 (nip1 ), | |
2845 | .sel (net256 ), | |
2846 | .sel_b (net282 ) ); | |
2847 | n2_core_pll_buf_8x_cust x18 ( | |
2848 | .vdd_reg (vdd_reg ), | |
2849 | .out (op[3] ), | |
2850 | .in (nip3 ) ); | |
2851 | n2_core_pll_buf_8x_cust x19 ( | |
2852 | .vdd_reg (vdd_reg ), | |
2853 | .out (op[4] ), | |
2854 | .in (nip4 ) ); | |
2855 | n2_core_pll_buf_8x_cust x20 ( | |
2856 | .vdd_reg (vdd_reg ), | |
2857 | .out (op[5] ), | |
2858 | .in (nip5 ) ); | |
2859 | n2_core_pll_tpm_mux_cust x23 ( | |
2860 | .opb (nzero_2 ), | |
2861 | .vdd_reg (vdd_reg ), | |
2862 | .op (nz_2 ), | |
2863 | .d0 (ip[2] ), | |
2864 | .d1 (nip2 ), | |
2865 | .sel (net256 ), | |
2866 | .sel_b (net282 ) ); | |
2867 | n2_core_pll_flop_reset_new_cust x24 ( | |
2868 | .vdd_reg (vdd_reg ), | |
2869 | .reset_val_l (vdd_reg ), | |
2870 | .d (net205 ), | |
2871 | .reset (reset_d ), | |
2872 | .clk (div_ck_i ), | |
2873 | .q_l (net201 ), | |
2874 | .q (nip0 ) ); | |
2875 | n2_core_pll_flop_reset_new_cust x25 ( | |
2876 | .vdd_reg (vdd_reg ), | |
2877 | .reset_val_l (vdd_reg ), | |
2878 | .d (net183 ), | |
2879 | .reset (reset_d ), | |
2880 | .clk (div_ck_i ), | |
2881 | .q_l (net186 ), | |
2882 | .q (nip1 ) ); | |
2883 | n2_core_pll_tpm_mux_cust x27 ( | |
2884 | .opb (nzero_3 ), | |
2885 | .vdd_reg (vdd_reg ), | |
2886 | .op (nz_3 ), | |
2887 | .d0 (ip[3] ), | |
2888 | .d1 (nip3 ), | |
2889 | .sel (net256 ), | |
2890 | .sel_b (net282 ) ); | |
2891 | n2_core_pll_tpm_mux_cust x28 ( | |
2892 | .opb (nzero_4 ), | |
2893 | .vdd_reg (vdd_reg ), | |
2894 | .op (nz_4 ), | |
2895 | .d0 (ip[4] ), | |
2896 | .d1 (nip4 ), | |
2897 | .sel (net256 ), | |
2898 | .sel_b (net282 ) ); | |
2899 | n2_core_pll_tpm_mux_cust x29 ( | |
2900 | .opb (nzero_5 ), | |
2901 | .vdd_reg (vdd_reg ), | |
2902 | .op (nz_5 ), | |
2903 | .d0 (ip[5] ), | |
2904 | .d1 (nip5 ), | |
2905 | .sel (net256 ), | |
2906 | .sel_b (net282 ) ); | |
2907 | n2_core_pll_flop_reset_new_cust x30 ( | |
2908 | .vdd_reg (vdd_reg ), | |
2909 | .reset_val_l (vdd_reg ), | |
2910 | .d (net195 ), | |
2911 | .reset (reset_d ), | |
2912 | .clk (div_ck_i ), | |
2913 | .q_l (net198 ), | |
2914 | .q (nip2 ) ); | |
2915 | n2_core_pll_inv_32x_cust x31 ( | |
2916 | .vdd_reg (vdd_reg ), | |
2917 | .out (vco_ckd ), | |
2918 | .in (net252 ) ); | |
2919 | n2_core_pll_flop_reset_new_cust x32 ( | |
2920 | .vdd_reg (vdd_reg ), | |
2921 | .reset_val_l (vdd_reg ), | |
2922 | .d (net159 ), | |
2923 | .reset (reset_d ), | |
2924 | .clk (div_ck_i ), | |
2925 | .q_l (net162 ), | |
2926 | .q (nip3 ) ); | |
2927 | n2_core_pll_flop_reset_new_cust x33 ( | |
2928 | .vdd_reg (vdd_reg ), | |
2929 | .reset_val_l (vdd_reg ), | |
2930 | .d (net147 ), | |
2931 | .reset (reset_d ), | |
2932 | .clk (div_ck_i ), | |
2933 | .q_l (net235 ), | |
2934 | .q (nip4 ) ); | |
2935 | n2_core_pll_flop_reset_new_cust x34 ( | |
2936 | .vdd_reg (vdd_reg ), | |
2937 | .reset_val_l (vdd_reg ), | |
2938 | .d (net171 ), | |
2939 | .reset (reset_d ), | |
2940 | .clk (div_ck_i ), | |
2941 | .q_l (net236 ), | |
2942 | .q (nip5 ) ); | |
2943 | n2_core_pll_flop_reset_new_cust x35 ( | |
2944 | .vdd_reg (vdd_reg ), | |
2945 | .reset_val_l (vdd_reg ), | |
2946 | .d (f0d ), | |
2947 | .reset (reset_d ), | |
2948 | .clk (vco_ckd ), | |
2949 | .q_l (zero_0 ), | |
2950 | .q (f0q ) ); | |
2951 | n2_core_pll_flop_reset_new_cust x36 ( | |
2952 | .vdd_reg (vdd_reg ), | |
2953 | .reset_val_l (vdd_reg ), | |
2954 | .d (f1d ), | |
2955 | .reset (reset_d ), | |
2956 | .clk (vco_ckd ), | |
2957 | .q_l (zero_1 ), | |
2958 | .q (f1q ) ); | |
2959 | n2_core_pll_flop_reset_new_cust x37 ( | |
2960 | .vdd_reg (vdd_reg ), | |
2961 | .reset_val_l (vdd_reg ), | |
2962 | .d (f2d ), | |
2963 | .reset (reset_d ), | |
2964 | .clk (vco_ckd ), | |
2965 | .q_l (zero_2 ), | |
2966 | .q (f2q ) ); | |
2967 | n2_core_pll_flop_reset_new_cust x38 ( | |
2968 | .vdd_reg (vdd_reg ), | |
2969 | .reset_val_l (vdd_reg ), | |
2970 | .d (f3d ), | |
2971 | .reset (reset_d ), | |
2972 | .clk (vco_ckd ), | |
2973 | .q_l (zero_3 ), | |
2974 | .q (f3q ) ); | |
2975 | n2_core_pll_flop_reset_new_cust x39 ( | |
2976 | .vdd_reg (vdd_reg ), | |
2977 | .reset_val_l (vdd_reg ), | |
2978 | .d (f4d ), | |
2979 | .reset (reset_d ), | |
2980 | .clk (vco_ckd ), | |
2981 | .q_l (zero_4 ), | |
2982 | .q (f4q ) ); | |
2983 | n2_core_pll_tpm_zd1_cust x40 ( | |
2984 | .vdd_reg (vdd_reg ), | |
2985 | .zero1 (sel ), | |
2986 | .zero1_b (sel_b ), | |
2987 | .q4b (zero_4 ), | |
2988 | .q0b (zero_0 ), | |
2989 | .q1b (zero_1 ), | |
2990 | .q2b (zero_2 ), | |
2991 | .q3b (zero_3 ), | |
2992 | .q5b (zero_5 ) ); | |
2993 | n2_core_pll_inv_8x_cust x41 ( | |
2994 | .vdd_reg (vdd_reg ), | |
2995 | .out (net252 ), | |
2996 | .in (vco_ck ) ); | |
2997 | n2_core_pll_flop_reset_new_cust x42 ( | |
2998 | .vdd_reg (vdd_reg ), | |
2999 | .reset_val_l (vdd_reg ), | |
3000 | .d (f5d ), | |
3001 | .reset (reset_d ), | |
3002 | .clk (vco_ckd ), | |
3003 | .q_l (zero_5 ), | |
3004 | .q (f5q ) ); | |
3005 | n2_core_pll_flop_reset_new_cust x43 ( | |
3006 | .vdd_reg (vdd_reg ), | |
3007 | .reset_val_l (vss ), | |
3008 | .d (sel ), | |
3009 | .reset (reset_d ), | |
3010 | .clk (vco_ckb ), | |
3011 | .q_l (net219 ), | |
3012 | .q (r_gate ) ); | |
3013 | n2_core_pll_flop_reset_new_cust x44 ( | |
3014 | .vdd_reg (vdd_reg ), | |
3015 | .reset_val_l (vdd_reg ), | |
3016 | .d (not_zero ), | |
3017 | .reset (reset_d ), | |
3018 | .clk (vco_ckd ), | |
3019 | .q_l (net189 ), | |
3020 | .q (f_gate ) ); | |
3021 | n2_core_pll_tpm_mux_cust x47 ( | |
3022 | .opb (net0506 ), | |
3023 | .vdd_reg (vdd_reg ), | |
3024 | .op (f0d ), | |
3025 | .d0 (next0 ), | |
3026 | .d1 (nz_0 ), | |
3027 | .sel (sel ), | |
3028 | .sel_b (sel_b ) ); | |
3029 | n2_core_pll_tpm_mux_cust x48 ( | |
3030 | .opb (net0505 ), | |
3031 | .vdd_reg (vdd_reg ), | |
3032 | .op (f1d ), | |
3033 | .d0 (next1 ), | |
3034 | .d1 (nz_1 ), | |
3035 | .sel (sel ), | |
3036 | .sel_b (sel_b ) ); | |
3037 | n2_core_pll_tpm_nzd_cust x49 ( | |
3038 | .vdd_reg (vdd_reg ), | |
3039 | .q2b (nzero_2 ), | |
3040 | .q4b (nzero_4 ), | |
3041 | .q3b (nzero_3 ), | |
3042 | .zero (not_zero ), | |
3043 | .q1b (nzero_1 ), | |
3044 | .q0b (nzero_0 ), | |
3045 | .q5b (nzero_5 ) ); | |
3046 | n2_core_pll_tpm_mux_cust x50 ( | |
3047 | .opb (net0504 ), | |
3048 | .vdd_reg (vdd_reg ), | |
3049 | .op (f2d ), | |
3050 | .d0 (next2 ), | |
3051 | .d1 (nz_2 ), | |
3052 | .sel (sel ), | |
3053 | .sel_b (sel_b ) ); | |
3054 | n2_core_pll_tpm_mux_cust x51 ( | |
3055 | .opb (net0503 ), | |
3056 | .vdd_reg (vdd_reg ), | |
3057 | .op (f3d ), | |
3058 | .d0 (next3 ), | |
3059 | .d1 (nz_3 ), | |
3060 | .sel (sel ), | |
3061 | .sel_b (sel_b ) ); | |
3062 | n2_core_pll_tpm_mux_cust x52 ( | |
3063 | .opb (net0502 ), | |
3064 | .vdd_reg (vdd_reg ), | |
3065 | .op (f4d ), | |
3066 | .d0 (next4 ), | |
3067 | .d1 (nz_4 ), | |
3068 | .sel (sel ), | |
3069 | .sel_b (sel_b ) ); | |
3070 | n2_core_pll_tpm_mux_cust x53 ( | |
3071 | .opb (net0501 ), | |
3072 | .vdd_reg (vdd_reg ), | |
3073 | .op (f5d ), | |
3074 | .d0 (next5 ), | |
3075 | .d1 (nz_5 ), | |
3076 | .sel (sel ), | |
3077 | .sel_b (sel_b ) ); | |
3078 | n2_core_pll_tpm_gate_new_cust x0 ( | |
3079 | .r_b (net219 ), | |
3080 | .vdd_reg (vdd_reg ), | |
3081 | .div_ck (div_ck ), | |
3082 | .r (r_gate ), | |
3083 | .ck (vco_ck ), | |
3084 | .f (f_gate ) ); | |
3085 | n2_core_pll_inv_4x_cust x1 ( | |
3086 | .vdd_reg (vdd_reg ), | |
3087 | .out (vco_ckb ), | |
3088 | .in (vco_ckd ) ); | |
3089 | endmodule | |
3090 | ||
3091 | // | |
3092 | // Last Modified: Friday Aug 26,2005 at 03:19:30 PM PDT | |
3093 | // | |
3094 | ||
3095 | module n2_core_pll_cp_cust(slow_l ,vdd_reg ,slow ,fast ,fast_l ,fltr ); | |
3096 | output fltr ; | |
3097 | input slow_l ; | |
3098 | input vdd_reg ; | |
3099 | input slow ; | |
3100 | input fast ; | |
3101 | input fast_l ; | |
3102 | ||
3103 | endmodule | |
3104 | ||
3105 | ||
3106 | // | |
3107 | // Last Modified: Friday Aug 26,2005 at 03:20:12 PM PDT | |
3108 | // | |
3109 | ||
3110 | module n2_core_pll_delay_cust(vdd_reg ,out_delcr ,in ,out_del ); | |
3111 | output out_delcr ; | |
3112 | output out_del ; | |
3113 | input vdd_reg ; | |
3114 | input in ; | |
3115 | supply1 vdd ; | |
3116 | wire vss = 1'b0; | |
3117 | ||
3118 | assign #1 out_del = in; | |
3119 | assign #1 out_delcr = ~in; | |
3120 | ||
3121 | endmodule | |
3122 | ||
3123 | ||
3124 | // | |
3125 | // Last Modified: Friday Aug 26,2005 at 03:21:49 PM PDT | |
3126 | // | |
3127 | ||
3128 | module n2_core_pll_tpm_gate_new_cust(r_b ,vdd_reg ,div_ck ,r ,ck ,f ); | |
3129 | output div_ck ; | |
3130 | input r_b ; | |
3131 | input vdd_reg ; | |
3132 | input r ; | |
3133 | input ck ; | |
3134 | input f ; | |
3135 | wire vss = 1'b0; | |
3136 | ||
3137 | // | |
3138 | // special divider modeling - kc | |
3139 | // | |
3140 | ||
3141 | reg div_ck; | |
3142 | ||
3143 | always @(ck or r or f or div_ck) begin | |
3144 | if (ck && r) | |
3145 | div_ck <= 1'b1; | |
3146 | else if (~ck && ~f) | |
3147 | div_ck <= 1'b0; | |
3148 | else if (ck && ~r && div_ck) | |
3149 | div_ck <= 1'b0; | |
3150 | else | |
3151 | div_ck <= div_ck; | |
3152 | end | |
3153 | ||
3154 | endmodule | |
3155 | ||
3156 | ||
3157 | ||
3158 | // | |
3159 | // Last Modified: Friday Aug 26,2005 at 03:20:47 PM PDT | |
3160 | // | |
3161 | ||
3162 | module n2_core_pll_lockdet_cust(pll_jtag_lock_everlose ,l1clk , | |
3163 | pll_lock_dyn ,reset_in ,slow ,fast ,pll_lock_pulse ,ref_ck ); | |
3164 | output pll_jtag_lock_everlose ; | |
3165 | output pll_lock_dyn ; | |
3166 | output pll_lock_pulse ; | |
3167 | input l1clk ; | |
3168 | input reset_in ; | |
3169 | input slow ; | |
3170 | input fast ; | |
3171 | input ref_ck ; | |
3172 | supply1 vdd ; | |
3173 | ||
3174 | endmodule | |
3175 | ||
3176 | ||
3177 | // | |
3178 | // wrapper for pll_core - mh157021 | |
3179 | // | |
3180 | ||
3181 | module imaginary_vco_gen ( | |
3182 | pll_arst_l, | |
3183 | sysclk, | |
3184 | fdbkclk, | |
3185 | div, | |
3186 | vco_out | |
3187 | ); | |
3188 | ||
3189 | input pll_arst_l; | |
3190 | input sysclk; | |
3191 | input [5:0] div; | |
3192 | input fdbkclk; | |
3193 | output vco_out; | |
3194 | ||
3195 | wire [5:0] div; | |
3196 | reg [5:0] div_lat; | |
3197 | ||
3198 | reg rst_lat; | |
3199 | wire sysclk_gated; | |
3200 | ||
3201 | ||
3202 | // latch the divider value on falling edge of rst | |
3203 | always @(pll_arst_l or div) begin | |
3204 | if (!pll_arst_l) | |
3205 | div_lat <= div; | |
3206 | end | |
3207 | ||
3208 | // zero out sysclk until pll_arst_l is high | |
3209 | /* | |
3210 | always @(pll_arst_l or sysclk) begin | |
3211 | if (!sysclk) | |
3212 | rst_lat <= pll_arst_l; | |
3213 | end | |
3214 | ||
3215 | assign sysclk_gated = rst_lat & sysclk; | |
3216 | */ | |
3217 | assign sysclk_gated = sysclk; | |
3218 | ||
3219 | ||
3220 | pll_core pll_core ( | |
3221 | .pll_arst_l (pll_arst_l), | |
3222 | .sysclk (sysclk_gated), | |
3223 | .fdbkclk (fdbkclk), | |
3224 | .div (div_lat), | |
3225 | .vco_out (vco_out) | |
3226 | ); | |
3227 | ||
3228 | endmodule | |
3229 | ||
3230 | ||
3231 | // | |
3232 | // heart of frequency multiplication; imported from rtl model - mh157021 | |
3233 | // | |
3234 | module pll_core ( | |
3235 | pll_arst_l, | |
3236 | sysclk, | |
3237 | fdbkclk, | |
3238 | div, | |
3239 | vco_out | |
3240 | ); | |
3241 | ||
3242 | ||
3243 | // ************************* | |
3244 | // input/output declaration | |
3245 | // ************************* | |
3246 | input pll_arst_l; | |
3247 | input sysclk; | |
3248 | input fdbkclk; | |
3249 | input [5:0] div; | |
3250 | output vco_out; | |
3251 | ||
3252 | // synopsys translate_off | |
3253 | ||
3254 | // ************************* | |
3255 | // wire/reg declaration | |
3256 | // ************************* | |
3257 | wire pll_arst_l; | |
3258 | wire sysclk; | |
3259 | wire fdbkclk; | |
3260 | wire [5:0] div; | |
3261 | wire vco_out; | |
3262 | // reg vco_out; | |
3263 | ||
3264 | reg vco_tmp; | |
3265 | reg locked; | |
3266 | ||
3267 | time t0; | |
3268 | time t1; | |
3269 | time posedge_vco_tmp; | |
3270 | time posedge_fdbkclk; | |
3271 | time ref_per; | |
3272 | time vco_per; | |
3273 | time vco_hi_ph; | |
3274 | time vco_lo_ph; | |
3275 | ||
3276 | time insdelay; | |
3277 | integer pulse_cnt; | |
3278 | integer ph_offset; | |
3279 | integer ph_offset_past; | |
3280 | time adj_delay; | |
3281 | time neg_delay; | |
3282 | ||
3283 | integer j; | |
3284 | ||
3285 | wire vco_shift; | |
3286 | wire [6:0] mult = div + 1'b1; | |
3287 | wire [6:0] mult2x = {mult[5:0],1'b0}; | |
3288 | ||
3289 | // testing | |
3290 | reg tmp_clk1; | |
3291 | reg tmp_clk2; | |
3292 | reg tmp_clk3; | |
3293 | reg tmp_clk4; | |
3294 | ||
3295 | reg [2:0] lock_cnt; | |
3296 | ||
3297 | ||
3298 | initial begin | |
3299 | #0 t0 = 0; | |
3300 | #0 t1 = 0; | |
3301 | #0 locked = 0; | |
3302 | #0 posedge_vco_tmp = 0; | |
3303 | #0 posedge_fdbkclk = 0; | |
3304 | #0 insdelay = 0; | |
3305 | #0 adj_delay = 0; // initialization | |
3306 | #0 pulse_cnt = 2; // initialization | |
3307 | end | |
3308 | ||
3309 | // ************************************ | |
3310 | // STABLE | |
3311 | // ************************************ | |
3312 | time qnt_err; | |
3313 | ||
3314 | // extract period of ref clk, and vco clk | |
3315 | always @ ( posedge sysclk ) begin | |
3316 | t0 = $realtime; | |
3317 | @(posedge sysclk); | |
3318 | t1 = $realtime; | |
3319 | ref_per = t1 - t0; // get reference period [ps] | |
3320 | vco_per = ref_per / (div+1'b1); // vco period [ps] | |
3321 | vco_hi_ph = ref_per/(mult2x); | |
3322 | vco_lo_ph = vco_per - vco_hi_ph; | |
3323 | qnt_err = ref_per - (vco_hi_ph+vco_lo_ph)*mult; | |
3324 | end | |
3325 | ||
3326 | ||
3327 | // generate vco tmp clk - direct multiplication | |
3328 | always @ ( posedge sysclk ) begin | |
3329 | ||
3330 | // OLD CODE THAT HAD DUTY CYCLE PROBLEMS | |
3331 | /* | |
3332 | vco_tmp = 1'b1; | |
3333 | for ( j = 1; j < pulse_cnt; j = j+1 ) begin | |
3334 | #(vco_per/2) vco_tmp = 1'b0; | |
3335 | #(vco_per/2) vco_tmp = 1'b1; | |
3336 | end | |
3337 | #(vco_hi_ph) vco_tmp = 1'b0; // for remaining part of cycle | |
3338 | */ | |
3339 | ||
3340 | // DUTY CYCLE CORRECTOR (ONLY FOR EVEN DIVIDERS) | |
3341 | vco_tmp = 1'b1; | |
3342 | for ( j = 1; j < mult; j = j+1 ) begin | |
3343 | #(vco_hi_ph) vco_tmp = 1'b0; | |
3344 | if ((j == (mult >> 1)) && (qnt_err != 0)) // internal multiplier for N2 is always even | |
3345 | #(j/2); | |
3346 | #(vco_lo_ph) vco_tmp = 1'b1; | |
3347 | end | |
3348 | #(vco_hi_ph) vco_tmp = 1'b0; // for remaining part of cycle | |
3349 | end | |
3350 | ||
3351 | ||
3352 | ||
3353 | // ***************************************** | |
3354 | // PH MEASURMENT & TRACKING | |
3355 | // ***************************************** | |
3356 | // measure phase offset between fdbkclk & vco_tmp | |
3357 | ||
3358 | ||
3359 | always @ ( posedge vco_tmp or negedge pll_arst_l ) begin | |
3360 | ||
3361 | if (!pll_arst_l) begin | |
3362 | ||
3363 | // clean wash | |
3364 | ||
3365 | posedge_vco_tmp = 0; | |
3366 | posedge_fdbkclk = 0; | |
3367 | adj_delay = 0; | |
3368 | insdelay = 0; | |
3369 | ph_offset_past = 360; | |
3370 | ||
3371 | end else begin | |
3372 | ||
3373 | // begin searching | |
3374 | if (locked) | |
3375 | insdelay = insdelay; | |
3376 | else begin | |
3377 | posedge_vco_tmp = $realtime; | |
3378 | @(posedge fdbkclk ); | |
3379 | posedge_fdbkclk = $realtime; | |
3380 | insdelay = posedge_fdbkclk - posedge_vco_tmp; | |
3381 | end | |
3382 | `ifdef PLL_PH_DEBUG | |
3383 | // DEBUG BEGIN | |
3384 | ph_offset = (360 * insdelay)/vco_per; | |
3385 | if (ph_offset != ph_offset_past) | |
3386 | $display ("phase offset changed changed from %d to %d degrees", | |
3387 | ph_offset_past, ph_offset ); | |
3388 | ph_offset_past = ph_offset; | |
3389 | // DEBUG END | |
3390 | `endif | |
3391 | while (vco_per <= insdelay) | |
3392 | insdelay = insdelay - vco_per ; | |
3393 | adj_delay = vco_per - insdelay; | |
3394 | end | |
3395 | end | |
3396 | ||
3397 | ||
3398 | // switch over to phase locked version so that | |
3399 | // vco_out + global tree delay lines up with | |
3400 | // reference signal | |
3401 | ||
3402 | assign vco_out = locked? vco_shift : vco_tmp; | |
3403 | ||
3404 | always @ (negedge sysclk or negedge pll_arst_l ) begin | |
3405 | if (!pll_arst_l) begin | |
3406 | locked <= 1'b0; | |
3407 | lock_cnt <= 3'b0; | |
3408 | end else begin | |
3409 | if (lock_cnt == `PLL_LOCK_CNT ) begin | |
3410 | locked <= 1'b1; | |
3411 | lock_cnt <= `PLL_LOCK_CNT; | |
3412 | end else begin | |
3413 | locked <= 1'b0; | |
3414 | lock_cnt <= lock_cnt + 1'b1; | |
3415 | end | |
3416 | end | |
3417 | end | |
3418 | ||
3419 | // need cascaded delays to account for large delays | |
3420 | // with respect to half-cycle of vco | |
3421 | // the following is guaranteed to work for all delays | |
3422 | ||
3423 | `ifdef FDBK_TRACKING | |
3424 | always @ (vco_tmp) tmp_clk1 = #(adj_delay/4) vco_tmp; | |
3425 | always @ (tmp_clk1) tmp_clk2 = #(adj_delay/4) tmp_clk1; | |
3426 | always @ (tmp_clk2) tmp_clk3 = #(adj_delay/4) tmp_clk2; | |
3427 | always @ (tmp_clk3) tmp_clk4 = #(adj_delay/4) tmp_clk3; | |
3428 | `else | |
3429 | always @ (vco_tmp) tmp_clk1 = vco_tmp; | |
3430 | always @ (tmp_clk1) tmp_clk2 = tmp_clk1; | |
3431 | always @ (tmp_clk2) tmp_clk3 = tmp_clk2; | |
3432 | always @ (tmp_clk3) tmp_clk4 = tmp_clk3; | |
3433 | `endif | |
3434 | ||
3435 | assign vco_shift = tmp_clk4; | |
3436 | ||
3437 | // synopsys translate_on | |
3438 | ||
3439 | endmodule | |
3440 | ||
3441 | // | |
3442 | // generate timed reset to resolve d3 reset issue - mh157021 | |
3443 | // in real pll, d3 start state does not matter since vco lock | |
3444 | // process will force rising edge alignment automatically | |
3445 | // however, for digital logic that does not simulate true lock | |
3446 | // need alternate scheme to fake out the auto alignment | |
3447 | // | |
3448 | module imaginary_timed_rst ( | |
3449 | ref, | |
3450 | vco_clk, | |
3451 | pll_div2, | |
3452 | pll_arst_l, | |
3453 | timed_pll_arst_l | |
3454 | ); | |
3455 | ||
3456 | input ref; | |
3457 | input vco_clk; | |
3458 | input pll_arst_l; | |
3459 | input [5:0] pll_div2; | |
3460 | output timed_pll_arst_l; | |
3461 | ||
3462 | wire ref; | |
3463 | wire vco_clk; | |
3464 | wire pll_arst_l; | |
3465 | wire [5:0] pll_div2; | |
3466 | wire timed_pll_arst_l; | |
3467 | ||
3468 | reg t0_pll_arst_l; | |
3469 | reg t1_pll_arst_l; | |
3470 | reg ref_q; | |
3471 | reg ref_pulse; | |
3472 | reg [2:0] cnt; | |
3473 | ||
3474 | // count reference cycles | |
3475 | always @(posedge ref or negedge pll_arst_l) begin | |
3476 | if (!pll_arst_l) | |
3477 | cnt <= 3'b0; | |
3478 | else | |
3479 | if (cnt == 3'b101) | |
3480 | cnt <= 3'b101; | |
3481 | else | |
3482 | cnt <= cnt + 1'b1; | |
3483 | end | |
3484 | ||
3485 | // vco_clk is always even multiple of ref since d3=2, vco_clk = ref * d2 * d3 | |
3486 | always @(negedge vco_clk or negedge pll_arst_l) begin | |
3487 | if (!pll_arst_l) begin | |
3488 | ref_q <= 1'b0; | |
3489 | ref_pulse <= 1'b0; | |
3490 | end else begin | |
3491 | ref_q <= ref; | |
3492 | ref_pulse <= ~ref_q & ref; | |
3493 | end | |
3494 | end | |
3495 | ||
3496 | // pulse converted to sticky reset release | |
3497 | always @(posedge vco_clk or negedge pll_arst_l) begin | |
3498 | if (!pll_arst_l) | |
3499 | t0_pll_arst_l <= 1'b0; | |
3500 | else | |
3501 | if (cnt != 3'b101) | |
3502 | t0_pll_arst_l <= 1'b0; | |
3503 | else if (ref_pulse) | |
3504 | t0_pll_arst_l <= 1'b1; | |
3505 | else | |
3506 | t0_pll_arst_l <= t0_pll_arst_l; | |
3507 | end | |
3508 | ||
3509 | // flop the reset release on negedge | |
3510 | always @(negedge vco_clk or negedge pll_arst_l) begin | |
3511 | if (!pll_arst_l) | |
3512 | t1_pll_arst_l <= 1'b0; | |
3513 | else | |
3514 | t1_pll_arst_l <= t0_pll_arst_l; | |
3515 | end | |
3516 | ||
3517 | assign timed_pll_arst_l = (pll_div2[0]) ? t0_pll_arst_l : t1_pll_arst_l; | |
3518 | ||
3519 | endmodule | |
3520 | ||
3521 | ||
3522 | // ========================================================================== | |
3523 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_clkmux_sync_cust/rtl/n2_core_pll_clkmux_sync_cust.v | |
3524 | // ========================================================================== | |
3525 | // mh157021: lower level module definition (n2_core_pll_clkmux_sync_cust) | |
3526 | // | |
3527 | // Last Modified: Friday Aug 26,2005 at 03:19:25 PM PDT | |
3528 | // | |
3529 | ||
3530 | module n2_core_pll_clkmux_sync_cust(bypass_pll_clk, pll_clk ,arst ,d1 ,d2 ,d1_sync , | |
3531 | d2_sync ,d0_sync ,d0 ,d3_sync ,d3 ); | |
3532 | output d1_sync ; | |
3533 | output d2_sync ; | |
3534 | output d0_sync ; | |
3535 | output d3_sync ; | |
3536 | input bypass_pll_clk ; | |
3537 | input pll_clk ; | |
3538 | input arst ; | |
3539 | input d1 ; | |
3540 | input d2 ; | |
3541 | input d0 ; | |
3542 | input d3 ; | |
3543 | supply1 vdd ; | |
3544 | ||
3545 | wire net089 ; | |
3546 | wire net111 ; | |
3547 | wire net112 ; | |
3548 | wire net113 ; | |
3549 | wire net114 ; | |
3550 | wire net0185 ; | |
3551 | wire net0186 ; | |
3552 | wire net0187 ; | |
3553 | wire net0207 ; | |
3554 | wire net0189 ; | |
3555 | wire d0_1 ; | |
3556 | wire d0_2 ; | |
3557 | wire d1_1 ; | |
3558 | wire d0_3 ; | |
3559 | wire d1_2 ; | |
3560 | wire d0_4 ; | |
3561 | wire d1_3 ; | |
3562 | wire d2_1 ; | |
3563 | wire d1_4 ; | |
3564 | wire d2_2 ; | |
3565 | wire d3_1 ; | |
3566 | wire d2_3 ; | |
3567 | wire d3_2 ; | |
3568 | wire d2_4 ; | |
3569 | wire d3_3 ; | |
3570 | wire d3_4 ; | |
3571 | wire clk_dly1 ; | |
3572 | wire clk_dly2 ; | |
3573 | wire clk_dly3 ; | |
3574 | wire clk_dly4 ; | |
3575 | wire clk_dly5 ; | |
3576 | wire net054 ; | |
3577 | wire net057 ; | |
3578 | wire net0110 ; | |
3579 | wire net0191 ; | |
3580 | wire net0192 ; | |
3581 | wire net56 ; | |
3582 | wire net0125 ; | |
3583 | wire net0126 ; | |
3584 | wire net078 ; | |
3585 | wire net63 ; | |
3586 | ||
3587 | wire bypass_pll_clk_l= ~bypass_pll_clk; // compile error fixed - mh157021 | |
3588 | ||
3589 | n2_core_pll_flop_reset_new_cust x2 ( | |
3590 | .vdd_reg (vdd ), | |
3591 | .reset_val_l (bypass_pll_clk_l), | |
3592 | .d (d2_4 ), | |
3593 | .reset (arst ), | |
3594 | .clk (clk_dly1 ), | |
3595 | .q_l (net0125 ), | |
3596 | .q (d2_sync ) ); | |
3597 | n2_core_pll_flop_reset_new_cust x3 ( | |
3598 | .vdd_reg (vdd ), | |
3599 | .reset_val_l (vdd ), | |
3600 | .d (d3_4 ), | |
3601 | .reset (arst ), | |
3602 | .clk (clk_dly1 ), | |
3603 | .q_l (net057 ), | |
3604 | .q (d3_sync ) ); | |
3605 | n2_core_pll_flop_reset_new_cust x4 ( | |
3606 | .vdd_reg (vdd ), | |
3607 | .reset_val_l (vdd ), | |
3608 | .d (d1_4 ), | |
3609 | .reset (arst ), | |
3610 | .clk (clk_dly1 ), | |
3611 | .q_l (net0110 ), | |
3612 | .q (d1_sync ) ); | |
3613 | n2_core_pll_flop_reset_new_cust x5 ( | |
3614 | .vdd_reg (vdd ), | |
3615 | .reset_val_l (vdd ), | |
3616 | .d (d0_4 ), | |
3617 | .reset (arst ), | |
3618 | .clk (clk_dly1 ), | |
3619 | .q_l (net0192 ), | |
3620 | .q (d0_sync ) ); | |
3621 | n2_core_pll_flop_reset_new_cust x6 ( | |
3622 | .vdd_reg (vdd ), | |
3623 | .reset_val_l (vdd ), | |
3624 | .d (d0_3 ), | |
3625 | .reset (arst ), | |
3626 | .clk (clk_dly2 ), | |
3627 | .q_l (net0191 ), | |
3628 | .q (d0_4 ) ); | |
3629 | n2_core_pll_flop_reset_new_cust x7 ( | |
3630 | .vdd_reg (vdd ), | |
3631 | .reset_val_l (vdd ), | |
3632 | .d (d1_3 ), | |
3633 | .reset (arst ), | |
3634 | .clk (clk_dly2 ), | |
3635 | .q_l (net089 ), | |
3636 | .q (d1_4 ) ); | |
3637 | n2_core_pll_flop_reset_new_cust x8 ( | |
3638 | .vdd_reg (vdd ), | |
3639 | .reset_val_l (vdd ), | |
3640 | .d (d0_1 ), | |
3641 | .reset (arst ), | |
3642 | .clk (clk_dly4 ), | |
3643 | .q_l (net0186 ), | |
3644 | .q (d0_2 ) ); | |
3645 | n2_core_pll_flop_reset_new_cust x9 ( | |
3646 | .vdd_reg (vdd ), | |
3647 | .reset_val_l (vdd ), | |
3648 | .d (d1_1 ), | |
3649 | .reset (arst ), | |
3650 | .clk (clk_dly4 ), | |
3651 | .q_l (net0187 ), | |
3652 | .q (d1_2 ) ); | |
3653 | n2_core_pll_flop_reset_new_cust x10 ( | |
3654 | .vdd_reg (vdd ), | |
3655 | .reset_val_l (vdd ), | |
3656 | .d (d1_2 ), | |
3657 | .reset (arst ), | |
3658 | .clk (clk_dly3 ), | |
3659 | .q_l (net0189 ), | |
3660 | .q (d1_3 ) ); | |
3661 | n2_core_pll_flop_reset_new_cust x12 ( | |
3662 | .vdd_reg (vdd ), | |
3663 | .reset_val_l (vdd ), | |
3664 | .d (d1 ), | |
3665 | .reset (arst ), | |
3666 | .clk (clk_dly5 ), | |
3667 | .q_l (net054 ), | |
3668 | .q (d1_1 ) ); | |
3669 | n2_core_pll_flop_reset_new_cust x13 ( | |
3670 | .vdd_reg (vdd ), | |
3671 | .reset_val_l (vdd ), | |
3672 | .d (d0_2 ), | |
3673 | .reset (arst ), | |
3674 | .clk (clk_dly3 ), | |
3675 | .q_l (net0185 ), | |
3676 | .q (d0_3 ) ); | |
3677 | n2_core_pll_flop_reset_new_cust x14 ( | |
3678 | .vdd_reg (vdd ), | |
3679 | .reset_val_l (vdd ), | |
3680 | .d (d0 ), | |
3681 | .reset (arst ), | |
3682 | .clk (clk_dly5 ), | |
3683 | .q_l (net0207 ), | |
3684 | .q (d0_1 ) ); | |
3685 | n2_core_pll_flop_reset_new_cust x18 ( | |
3686 | .vdd_reg (vdd ), | |
3687 | .reset_val_l (bypass_pll_clk_l), | |
3688 | .d (d2_2 ), | |
3689 | .reset (arst ), | |
3690 | .clk (clk_dly3 ), | |
3691 | .q_l (net114 ), | |
3692 | .q (d2_3 ) ); | |
3693 | n2_core_pll_flop_reset_new_cust x19 ( | |
3694 | .vdd_reg (vdd ), | |
3695 | .reset_val_l (vdd ), | |
3696 | .d (d3_2 ), | |
3697 | .reset (arst ), | |
3698 | .clk (clk_dly3 ), | |
3699 | .q_l (net56 ), | |
3700 | .q (d3_3 ) ); | |
3701 | n2_core_pll_flop_reset_new_cust x20 ( | |
3702 | .vdd_reg (vdd ), | |
3703 | .reset_val_l (vdd ), | |
3704 | .d (d3_1 ), | |
3705 | .reset (arst ), | |
3706 | .clk (clk_dly4 ), | |
3707 | .q_l (net112 ), | |
3708 | .q (d3_2 ) ); | |
3709 | n2_core_pll_flop_reset_new_cust x21 ( | |
3710 | .vdd_reg (vdd ), | |
3711 | .reset_val_l (bypass_pll_clk_l), | |
3712 | .d (d2_1 ), | |
3713 | .reset (arst ), | |
3714 | .clk (clk_dly4 ), | |
3715 | .q_l (net113 ), | |
3716 | .q (d2_2 ) ); | |
3717 | n2_core_pll_flop_reset_new_cust x22 ( | |
3718 | .vdd_reg (vdd ), | |
3719 | .reset_val_l (bypass_pll_clk_l), | |
3720 | .d (d2 ), | |
3721 | .reset (arst ), | |
3722 | .clk (clk_dly5 ), | |
3723 | .q_l (net63 ), | |
3724 | .q (d2_1 ) ); | |
3725 | n2_core_pll_flop_reset_new_cust x23 ( | |
3726 | .vdd_reg (vdd ), | |
3727 | .reset_val_l (vdd ), | |
3728 | .d (d3 ), | |
3729 | .reset (arst ), | |
3730 | .clk (clk_dly5 ), | |
3731 | .q_l (net111 ), | |
3732 | .q (d3_1 ) ); | |
3733 | n2_core_pll_clkrep_cust x24 ( | |
3734 | .pll_clk (pll_clk ), | |
3735 | .clk_dly3 (clk_dly3 ), | |
3736 | .clk_dly5 (clk_dly5 ), | |
3737 | .clk_dly4 (clk_dly4 ), | |
3738 | .clk_dly2 (clk_dly2 ), | |
3739 | .clk_dly1 (clk_dly1 ) ); | |
3740 | n2_core_pll_flop_reset_new_cust x0 ( | |
3741 | .vdd_reg (vdd ), | |
3742 | .reset_val_l (vdd ), | |
3743 | .d (d3_3 ), | |
3744 | .reset (arst ), | |
3745 | .clk (clk_dly2 ), | |
3746 | .q_l (net078 ), | |
3747 | .q (d3_4 ) ); | |
3748 | n2_core_pll_flop_reset_new_cust x1 ( | |
3749 | .vdd_reg (vdd ), | |
3750 | .reset_val_l (bypass_pll_clk_l), | |
3751 | .d (d2_3 ), | |
3752 | .reset (arst ), | |
3753 | .clk (clk_dly2 ), | |
3754 | .q_l (net0126 ), | |
3755 | .q (d2_4 ) ); | |
3756 | endmodule | |
3757 | ||
3758 | // ========================================================================== | |
3759 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_flop_reset_new_cust/rtl/n2_core_pll_flop_reset_new_cust.v | |
3760 | // ========================================================================== | |
3761 | // mh157021: lower level module definition (n2_core_pll_flop_reset_new_cust) | |
3762 | // | |
3763 | // Last Modified: Friday Aug 26,2005 at 03:20:20 PM PDT | |
3764 | // | |
3765 | ||
3766 | module n2_core_pll_flop_reset_new_cust(vdd_reg ,reset_val_l ,d ,reset , | |
3767 | clk ,q_l ,q ); | |
3768 | output q_l ; | |
3769 | output q ; | |
3770 | input vdd_reg ; | |
3771 | input reset_val_l ; | |
3772 | input d ; | |
3773 | input reset ; | |
3774 | input clk ; | |
3775 | ||
3776 | reg q; | |
3777 | reg qb; | |
3778 | ||
3779 | ||
3780 | /* | |
3781 | always | |
3782 | @( clk or d or reset ) | |
3783 | if ( reset ) | |
3784 | qb <= !reset_val_l; | |
3785 | else if ( !clk ) | |
3786 | qb <= d; | |
3787 | else | |
3788 | qb <= qb; | |
3789 | ||
3790 | ||
3791 | always | |
3792 | @( clk or reset ) | |
3793 | if ( reset ) | |
3794 | q <= !reset_val_l; | |
3795 | else if ( clk ) | |
3796 | q <= qb; | |
3797 | else | |
3798 | q <= q; | |
3799 | ||
3800 | assign q_l = !q; | |
3801 | */ | |
3802 | ||
3803 | ||
3804 | always @(posedge clk or posedge reset) begin | |
3805 | if (reset) | |
3806 | q <= ~reset_val_l; | |
3807 | else | |
3808 | q <= d; | |
3809 | end | |
3810 | ||
3811 | assign q_l = ~q; | |
3812 | ||
3813 | endmodule | |
3814 | ||
3815 | // ========================================================================== | |
3816 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_clkrep_cust/rtl/n2_core_pll_clkrep_cust.v | |
3817 | // ========================================================================== | |
3818 | // | |
3819 | // Last Modified: Friday Aug 26,2005 at 03:19:28 PM PDT | |
3820 | // | |
3821 | ||
3822 | module n2_core_pll_clkrep_cust(pll_clk ,clk_dly3 ,clk_dly5 ,clk_dly4 , | |
3823 | clk_dly2 ,clk_dly1 ); | |
3824 | output clk_dly3 ; | |
3825 | output clk_dly5 ; | |
3826 | output clk_dly4 ; | |
3827 | output clk_dly2 ; | |
3828 | output clk_dly1 ; | |
3829 | input pll_clk ; | |
3830 | supply1 vdd ; | |
3831 | wire vss = 1'b0; | |
3832 | ||
3833 | assign clk_dly1=pll_clk; | |
3834 | assign clk_dly2=clk_dly1; | |
3835 | assign clk_dly3=clk_dly2; | |
3836 | assign clk_dly4=clk_dly3; | |
3837 | assign clk_dly5=clk_dly4; | |
3838 | ||
3839 | endmodule | |
3840 | ||
3841 | // ========================================================================== | |
3842 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_flopderst_16x_cust/rtl/n2_core_pll_flopderst_16x_cust.v | |
3843 | // ========================================================================== | |
3844 | // mh157021: lower level module definition (n2_core_pll_flopderst_16x_cust) | |
3845 | // | |
3846 | // Last Modified: Friday Aug 26,2005 at 03:20:22 PM PDT | |
3847 | // | |
3848 | ||
3849 | module n2_core_pll_flopderst_16x_cust(q_l ,reset_val ,d ,q ,reset ,clk ,ena ); | |
3850 | output q_l ; | |
3851 | output q ; | |
3852 | input reset_val ; | |
3853 | input d ; | |
3854 | input reset ; | |
3855 | input clk ; | |
3856 | input ena ; | |
3857 | ||
3858 | reg qb_p; | |
3859 | reg qb_n; | |
3860 | reg q; | |
3861 | ||
3862 | always | |
3863 | @( clk or d or reset or reset_val ) | |
3864 | if ( reset ) | |
3865 | qb_p <= reset_val; | |
3866 | else if ( clk ) | |
3867 | qb_p <= d; | |
3868 | ||
3869 | always | |
3870 | @( clk or d or reset or reset_val ) | |
3871 | if ( reset ) | |
3872 | qb_n <= reset_val; | |
3873 | else if ( !clk ) | |
3874 | qb_n <= d; | |
3875 | ||
3876 | always | |
3877 | @( clk or reset or ena or reset_val ) | |
3878 | if ( reset ) | |
3879 | q <= reset_val; | |
3880 | else if ( clk && ena ) | |
3881 | q <= qb_n; | |
3882 | else if ( !clk && !ena ) | |
3883 | q <= qb_p; | |
3884 | ||
3885 | assign q_l = !q; | |
3886 | ||
3887 | endmodule | |
3888 | ||
3889 | // ========================================================================== | |
3890 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_ckmux_mxdel_diffout_cust/rtl/n2_core_pll_ckmux_mxdel_diffout_cust.v | |
3891 | // ========================================================================== | |
3892 | // mh157021: lower level module definition (n2_core_pll_ckmux_mxdel_diffout_cust) | |
3893 | // | |
3894 | // Last Modified: Tuesday Sep 20,2005 at 06:05:05 PM PDT | |
3895 | // | |
3896 | ||
3897 | module n2_core_pll_ckmux_mxdel_diffout_cust(ckt_drv_int ,cktree_drv , | |
3898 | cktree_drv_l ,pll1_clk ,sel1 ,pll2_clk ,bypass_clk ,sel3 ,d1_clk , | |
3899 | pll_sdel ,sel0 ,sel2 ); | |
3900 | input [1:0] pll_sdel ; | |
3901 | output ckt_drv_int ; | |
3902 | output cktree_drv ; | |
3903 | output cktree_drv_l ; | |
3904 | output d1_clk ; | |
3905 | input pll1_clk ; | |
3906 | input sel1 ; | |
3907 | input pll2_clk ; | |
3908 | input bypass_clk ; | |
3909 | input sel3 ; | |
3910 | input sel0 ; | |
3911 | input sel2 ; | |
3912 | supply1 vdd ; | |
3913 | wire vss = 1'b0; | |
3914 | ||
3915 | ||
3916 | mux4k x1 ( | |
3917 | .muxtst (1'b0), | |
3918 | .in0 (pll1_clk), | |
3919 | .in1 (d1_clk), | |
3920 | .in2 (pll2_clk), | |
3921 | .in3 (bypass_clk), | |
3922 | .sel0 (sel0), | |
3923 | .sel1 (sel1), | |
3924 | .sel2 (sel2), | |
3925 | .sel3 (sel3), | |
3926 | .dout (cktree_drv) ); | |
3927 | ||
3928 | ||
3929 | n2_core_pll_clkmux_delay x0 ( | |
3930 | .pll_sdel ({pll_sdel } ), | |
3931 | .mux_out (d1_clk ), | |
3932 | .d (pll1_clk ) ); | |
3933 | ||
3934 | assign cktree_drv_l = ~cktree_drv; // missing connectivity - mh157021 | |
3935 | assign ckt_drv_int=cktree_drv; // missing connectivity - kcyen | |
3936 | ||
3937 | endmodule | |
3938 | ||
3939 | ||
3940 | // ========================================================================== | |
3941 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_clkmux_delay/rtl/decode.v | |
3942 | // ========================================================================== | |
3943 | // mh157021: lower level module definition (decode) | |
3944 | module decode ( a, d ); | |
3945 | ||
3946 | input [1:0] a; | |
3947 | output [3:0] d; | |
3948 | ||
3949 | reg [3:0] d; | |
3950 | ||
3951 | always @(a) | |
3952 | begin | |
3953 | case (a) | |
3954 | 2'b00: d <= 4'b0001; | |
3955 | 2'b01: d <= 4'b0010; | |
3956 | 2'b10: d <= 4'b0100; | |
3957 | 2'b11: d <= 4'b1000; | |
3958 | endcase | |
3959 | end | |
3960 | ||
3961 | endmodule | |
3962 | ||
3963 | // ========================================================================== | |
3964 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_buf_4x_cust/rtl/n2_core_pll_buf_4x_cust.v | |
3965 | // ========================================================================== | |
3966 | // | |
3967 | // Last Modified: Friday Aug 26,2005 at 03:19:05 PM PDT | |
3968 | // | |
3969 | ||
3970 | module n2_core_pll_buf_4x_cust(vdd_reg ,out ,in ); | |
3971 | output out ; | |
3972 | input vdd_reg ; | |
3973 | input in ; | |
3974 | wire vss = 1'b0; | |
3975 | ||
3976 | assign out = in; | |
3977 | ||
3978 | endmodule | |
3979 | ||
3980 | // ========================================================================== | |
3981 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_buf_16x_cust/rtl/n2_core_pll_buf_16x_cust.v | |
3982 | // ========================================================================== | |
3983 | // mh157021: lower level module definition (n2_core_pll_buf_16x_cust) | |
3984 | // | |
3985 | // Last Modified: Friday Aug 26,2005 at 03:19:03 PM PDT | |
3986 | // | |
3987 | ||
3988 | module n2_core_pll_buf_16x_cust(vdd_reg ,out ,in ); | |
3989 | output out ; | |
3990 | input vdd_reg ; | |
3991 | input in ; | |
3992 | wire vss = 1'b0; | |
3993 | ||
3994 | assign out = in; | |
3995 | ||
3996 | endmodule | |
3997 | ||
3998 | // ========================================================================== | |
3999 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_mux_cust/rtl/n2_core_pll_tpm_mux_cust.v | |
4000 | // ========================================================================== | |
4001 | // | |
4002 | // Last Modified: Friday Aug 26,2005 at 03:21:51 PM PDT | |
4003 | // | |
4004 | ||
4005 | module n2_core_pll_tpm_mux_cust(opb ,vdd_reg ,op ,d0 ,d1 ,sel ,sel_b ); | |
4006 | output opb ; | |
4007 | output op ; | |
4008 | input vdd_reg ; | |
4009 | input d0 ; | |
4010 | input d1 ; | |
4011 | input sel ; | |
4012 | input sel_b ; | |
4013 | wire vss = 1'b0; | |
4014 | ||
4015 | assign opb = (~(sel & d1)) & (~(sel_b & d0)); | |
4016 | assign op = ~opb; | |
4017 | ||
4018 | endmodule | |
4019 | ||
4020 | // ========================================================================== | |
4021 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_buf_8x_cust/rtl/n2_core_pll_buf_8x_cust.v | |
4022 | // ========================================================================== | |
4023 | // | |
4024 | // Last Modified: Friday Aug 26,2005 at 03:19:06 PM PDT | |
4025 | // | |
4026 | ||
4027 | module n2_core_pll_buf_8x_cust(vdd_reg ,out ,in ); | |
4028 | output out ; | |
4029 | input vdd_reg ; | |
4030 | input in ; | |
4031 | wire vss = 1'b0; | |
4032 | ||
4033 | assign out = in; | |
4034 | ||
4035 | endmodule | |
4036 | ||
4037 | // ========================================================================== | |
4038 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_8x_cust/rtl/n2_core_pll_inv_8x_cust.v | |
4039 | // ========================================================================== | |
4040 | // mh157021: lower level module definition (n2_core_pll_inv_8x_cust) | |
4041 | // | |
4042 | // Last Modified: Friday Aug 26,2005 at 03:20:35 PM PDT | |
4043 | // | |
4044 | ||
4045 | module n2_core_pll_inv_8x_cust(vdd_reg ,out ,in ); | |
4046 | output out ; | |
4047 | input vdd_reg ; | |
4048 | input in ; | |
4049 | wire vss = 1'b0; | |
4050 | ||
4051 | assign out = ~in; | |
4052 | ||
4053 | endmodule | |
4054 | ||
4055 | // ========================================================================== | |
4056 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_next_new_cust/rtl/n2_core_pll_tpm_next_new_cust.v | |
4057 | // ========================================================================== | |
4058 | /* | |
4059 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_next_new_cust/schematic/sch.cdb | |
4060 | Last Modified: Monday Sep 19,2005 at 12:16:27 PM PDT | |
4061 | By: ky82615 | |
4062 | */ | |
4063 | module n2_core_pll_tpm_next_new_cust(vdd_reg ,d5 ,q0b ,q3b ,d3 ,q5b ,q1b | |
4064 | ,q2b ,d2 ,d0 ,d4 ,q2 ,q0 ,q1 ,d1 ,q4b ); | |
4065 | output d5 ; | |
4066 | output d3 ; | |
4067 | output d2 ; | |
4068 | output d0 ; | |
4069 | output d4 ; | |
4070 | output d1 ; | |
4071 | input vdd_reg ; | |
4072 | input q0b ; | |
4073 | input q3b ; | |
4074 | input q5b ; | |
4075 | input q1b ; | |
4076 | input q2b ; | |
4077 | input q2 ; | |
4078 | input q0 ; | |
4079 | input q1 ; | |
4080 | input q4b ; | |
4081 | ||
4082 | wire net73 ; | |
4083 | wire net76 ; | |
4084 | wire net091 ; | |
4085 | wire net0115 ; | |
4086 | wire net53 ; | |
4087 | wire net55 ; | |
4088 | wire net64 ; | |
4089 | wire net69 ; | |
4090 | ||
4091 | ||
4092 | n2_core_pll_xnor2_4x_new_cust x2 ( | |
4093 | .vdd_reg (vdd_reg ), | |
4094 | .out (d1 ), | |
4095 | .in0 (q1b ), | |
4096 | .in1 (q0b ) ); | |
4097 | n2_core_pll_xnor2_4x_new_cust x3 ( | |
4098 | .vdd_reg (vdd_reg ), | |
4099 | .out (d2 ), | |
4100 | .in0 (q2b ), | |
4101 | .in1 (net76 ) ); | |
4102 | n2_core_pll_xnor2_4x_new_cust x4 ( | |
4103 | .vdd_reg (vdd_reg ), | |
4104 | .out (d3 ), | |
4105 | .in0 (q3b ), | |
4106 | .in1 (net73 ) ); | |
4107 | n2_core_pll_nand2_2x_cust x5 ( | |
4108 | .vdd_reg (vdd_reg ), | |
4109 | .out (net53 ), | |
4110 | .in1 (q1b ), | |
4111 | .in0 (q0b ) ); | |
4112 | n2_core_pll_nor2_2x_cust x6 ( | |
4113 | .vdd_reg (vdd_reg ), | |
4114 | .out (net76 ), | |
4115 | .in1 (q1 ), | |
4116 | .in0 (q0 ) ); | |
4117 | n2_core_pll_nor2_2x_cust x7 ( | |
4118 | .vdd_reg (vdd_reg ), | |
4119 | .out (net55 ), | |
4120 | .in1 (net64 ), | |
4121 | .in0 (net53 ) ); | |
4122 | n2_core_pll_xnor2_4x_new_cust x8 ( | |
4123 | .vdd_reg (vdd_reg ), | |
4124 | .out (d4 ), | |
4125 | .in0 (q4b ), | |
4126 | .in1 (net69 ) ); | |
4127 | n2_core_pll_xnor2_4x_new_cust x9 ( | |
4128 | .vdd_reg (vdd_reg ), | |
4129 | .out (d5 ), | |
4130 | .in0 (q5b ), | |
4131 | .in1 (net55 ) ); | |
4132 | n2_core_pll_nand3_2x_cust x13 ( | |
4133 | .vdd_reg (vdd_reg ), | |
4134 | .out (net64 ), | |
4135 | .in2 (q4b ), | |
4136 | .in1 (q3b ), | |
4137 | .in0 (q2b ) ); | |
4138 | n2_core_pll_nand2_2x_cust x14 ( | |
4139 | .vdd_reg (vdd_reg ), | |
4140 | .out (net0115 ), | |
4141 | .in1 (q1b ), | |
4142 | .in0 (q0b ) ); | |
4143 | n2_core_pll_nand2_2x_cust x15 ( | |
4144 | .vdd_reg (vdd_reg ), | |
4145 | .out (net091 ), | |
4146 | .in1 (q3b ), | |
4147 | .in0 (q2b ) ); | |
4148 | n2_core_pll_nor2_2x_cust x16 ( | |
4149 | .vdd_reg (vdd_reg ), | |
4150 | .out (net69 ), | |
4151 | .in1 (net091 ), | |
4152 | .in0 (net0115 ) ); | |
4153 | n2_core_pll_nor3_2x_cust x0 ( | |
4154 | .vdd_reg (vdd_reg ), | |
4155 | .out (net73 ), | |
4156 | .in2 (q2 ), | |
4157 | .in1 (q1 ), | |
4158 | .in0 (q0 ) ); | |
4159 | n2_core_pll_xnor2_4x_new_cust x1 ( | |
4160 | .vdd_reg (vdd_reg ), | |
4161 | .out (d0 ), | |
4162 | .in0 (q0b ), | |
4163 | .in1 (vdd_reg ) ); | |
4164 | endmodule | |
4165 | ||
4166 | ||
4167 | // ========================================================================== | |
4168 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_gate2_cust/rtl/n2_core_pll_tpm_gate2_cust.v | |
4169 | // ========================================================================== | |
4170 | // | |
4171 | // Last Modified: Friday Aug 26,2005 at 03:21:48 PM PDT | |
4172 | // | |
4173 | ||
4174 | module n2_core_pll_tpm_gate2_cust(vdd_reg ,div_ck ,r ,ck ); | |
4175 | output div_ck ; | |
4176 | input vdd_reg ; | |
4177 | input r ; | |
4178 | input ck ; | |
4179 | wire vss = 1'b0; | |
4180 | ||
4181 | reg div_ck; | |
4182 | ||
4183 | always @ ( ck or r) begin // better latch modeling - mh157021 | |
4184 | if ( ck ) | |
4185 | div_ck <= ~r; | |
4186 | end | |
4187 | ||
4188 | endmodule | |
4189 | ||
4190 | // ========================================================================== | |
4191 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_32x_cust/rtl/n2_core_pll_inv_32x_cust.v | |
4192 | // ========================================================================== | |
4193 | // mh157021: lower level module definition (n2_core_pll_inv_32x_cust) | |
4194 | // | |
4195 | // Last Modified: Friday Aug 26,2005 at 03:20:33 PM PDT | |
4196 | // | |
4197 | ||
4198 | module n2_core_pll_inv_32x_cust(vdd_reg ,out ,in ); | |
4199 | output out ; | |
4200 | input vdd_reg ; | |
4201 | input in ; | |
4202 | wire vss = 1'b0; | |
4203 | ||
4204 | assign out = ~in; | |
4205 | ||
4206 | endmodule | |
4207 | ||
4208 | // ========================================================================== | |
4209 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_zd1_cust/rtl/n2_core_pll_tpm_zd1_cust.v | |
4210 | // ========================================================================== | |
4211 | /* | |
4212 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_zd1_cust/schematic/sch.cdb | |
4213 | Last Modified: Monday Sep 19,2005 at 12:15:28 PM PDT | |
4214 | By: ky82615 | |
4215 | */ | |
4216 | module n2_core_pll_tpm_zd1_cust(vdd_reg ,zero1 ,zero1_b ,q4b ,q0b ,q1b , | |
4217 | q2b ,q3b ,q5b ); | |
4218 | output zero1 ; | |
4219 | output zero1_b ; | |
4220 | input vdd_reg ; | |
4221 | input q4b ; | |
4222 | input q0b ; | |
4223 | input q1b ; | |
4224 | input q2b ; | |
4225 | input q3b ; | |
4226 | input q5b ; | |
4227 | ||
4228 | wire net28 ; | |
4229 | wire net33 ; | |
4230 | wire net38 ; | |
4231 | ||
4232 | ||
4233 | n2_core_pll_nand2_2x_cust x2 ( | |
4234 | .vdd_reg (vdd_reg ), | |
4235 | .out (net33 ), | |
4236 | .in1 (q1b ), | |
4237 | .in0 (q2b ) ); | |
4238 | n2_core_pll_nor2_4x_cust x3 ( | |
4239 | .vdd_reg (vdd_reg ), | |
4240 | .out (net28 ), | |
4241 | .in1 (net33 ), | |
4242 | .in0 (net38 ) ); | |
4243 | n2_core_plllvt_nand2_16x_cust x4 ( | |
4244 | .vdd_reg (vdd_reg ), | |
4245 | .out (zero1_b ), | |
4246 | .in1 (q0b ), | |
4247 | .in0 (net28 ) ); | |
4248 | n2_core_pll_nand3_2x_cust x0 ( | |
4249 | .vdd_reg (vdd_reg ), | |
4250 | .out (net38 ), | |
4251 | .in2 (q3b ), | |
4252 | .in1 (q4b ), | |
4253 | .in0 (q5b ) ); | |
4254 | n2_core_pll_inv_16x_a_cust x1 ( | |
4255 | .vdd_reg (vdd_reg ), | |
4256 | .out (zero1 ), | |
4257 | .in (zero1_b ) ); | |
4258 | endmodule | |
4259 | ||
4260 | ||
4261 | // ========================================================================== | |
4262 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_4x_cust/rtl/n2_core_pll_inv_4x_cust.v | |
4263 | // ========================================================================== | |
4264 | // mh157021: lower level module definition (n2_core_pll_inv_4x_cust) | |
4265 | // | |
4266 | // Last Modified: Friday Aug 26,2005 at 03:20:34 PM PDT | |
4267 | // | |
4268 | ||
4269 | module n2_core_pll_inv_4x_cust(vdd_reg ,out ,in ); | |
4270 | output out ; | |
4271 | input vdd_reg ; | |
4272 | input in ; | |
4273 | wire vss = 1'b0; | |
4274 | ||
4275 | assign out = ~in; | |
4276 | ||
4277 | endmodule | |
4278 | ||
4279 | // ========================================================================== | |
4280 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nand2_2x_cust/rtl/n2_core_pll_nand2_2x_cust.v | |
4281 | // ========================================================================== | |
4282 | // | |
4283 | // Last Modified: Friday Aug 26,2005 at 03:20:55 PM PDT | |
4284 | // | |
4285 | ||
4286 | module n2_core_pll_nand2_2x_cust(vdd_reg ,out ,in1 ,in0 ); | |
4287 | output out ; | |
4288 | input vdd_reg ; | |
4289 | input in1 ; | |
4290 | input in0 ; | |
4291 | wire vss = 1'b0; | |
4292 | ||
4293 | assign out = ~(in0 & in1); | |
4294 | ||
4295 | endmodule | |
4296 | ||
4297 | // ========================================================================== | |
4298 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nor2_4x_cust/rtl/n2_core_pll_nor2_4x_cust.v | |
4299 | // ========================================================================== | |
4300 | // | |
4301 | // Last Modified: Friday Aug 26,2005 at 03:21:02 PM PDT | |
4302 | // | |
4303 | ||
4304 | module n2_core_pll_nor2_4x_cust(vdd_reg ,out ,in1 ,in0 ); | |
4305 | output out ; | |
4306 | input vdd_reg ; | |
4307 | input in1 ; | |
4308 | input in0 ; | |
4309 | wire vss = 1'b0; | |
4310 | ||
4311 | assign out = ~(in0 | in1); | |
4312 | ||
4313 | endmodule | |
4314 | ||
4315 | // ========================================================================== | |
4316 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_plllvt_nand2_16x_cust/rtl/n2_core_plllvt_nand2_16x_cust.v | |
4317 | // ========================================================================== | |
4318 | // | |
4319 | // Last Modified: Friday Aug 26,2005 at 03:22:28 PM PDT | |
4320 | // | |
4321 | ||
4322 | module n2_core_plllvt_nand2_16x_cust(vdd_reg ,out ,in1 ,in0 ); | |
4323 | output out ; | |
4324 | input vdd_reg ; | |
4325 | input in1 ; | |
4326 | input in0 ; | |
4327 | wire vss = 1'b0; | |
4328 | ||
4329 | assign out = ~(in0 & in1); | |
4330 | ||
4331 | endmodule | |
4332 | ||
4333 | // ========================================================================== | |
4334 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nand3_2x_cust/rtl/n2_core_pll_nand3_2x_cust.v | |
4335 | // ========================================================================== | |
4336 | // | |
4337 | // Last Modified: Friday Aug 26,2005 at 03:20:58 PM PDT | |
4338 | // | |
4339 | ||
4340 | module n2_core_pll_nand3_2x_cust(vdd_reg ,out ,in2 ,in1 ,in0 ); | |
4341 | output out ; | |
4342 | input vdd_reg ; | |
4343 | input in2 ; | |
4344 | input in1 ; | |
4345 | input in0 ; | |
4346 | wire vss = 1'b0; | |
4347 | ||
4348 | assign out = ~(in0 & in1 & in2); | |
4349 | ||
4350 | endmodule | |
4351 | ||
4352 | // ========================================================================== | |
4353 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_16x_a_cust/rtl/n2_core_pll_inv_16x_a_cust.v | |
4354 | // ========================================================================== | |
4355 | // | |
4356 | // Last Modified: Friday Aug 26,2005 at 03:20:27 PM PDT | |
4357 | // | |
4358 | ||
4359 | module n2_core_pll_inv_16x_a_cust(vdd_reg ,out ,in ); | |
4360 | output out ; | |
4361 | input vdd_reg ; | |
4362 | input in ; | |
4363 | wire vss = 1'b0; | |
4364 | ||
4365 | assign out = ~in; | |
4366 | ||
4367 | endmodule | |
4368 | ||
4369 | // ========================================================================== | |
4370 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nor2_2x_cust/rtl/n2_core_pll_nor2_2x_cust.v | |
4371 | // ========================================================================== | |
4372 | // | |
4373 | // Last Modified: Friday Aug 26,2005 at 03:21:01 PM PDT | |
4374 | // | |
4375 | ||
4376 | module n2_core_pll_nor2_2x_cust(vdd_reg ,out ,in1 ,in0 ); | |
4377 | output out ; | |
4378 | input vdd_reg ; | |
4379 | input in1 ; | |
4380 | input in0 ; | |
4381 | wire vss = 1'b0; | |
4382 | ||
4383 | assign out = ~(in0 | in1); | |
4384 | ||
4385 | endmodule | |
4386 | ||
4387 | // ========================================================================== | |
4388 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nor3_2x_cust/rtl/n2_core_pll_nor3_2x_cust.v | |
4389 | // ========================================================================== | |
4390 | // | |
4391 | // Last Modified: Friday Aug 26,2005 at 03:21:03 PM PDT | |
4392 | // | |
4393 | ||
4394 | module n2_core_pll_nor3_2x_cust(vdd_reg ,out ,in2 ,in1 ,in0 ); | |
4395 | output out ; | |
4396 | input vdd_reg ; | |
4397 | input in2 ; | |
4398 | input in1 ; | |
4399 | input in0 ; | |
4400 | wire vss = 1'b0; | |
4401 | ||
4402 | assign out = ~(in0 | in1 | in2); | |
4403 | ||
4404 | endmodule | |
4405 | ||
4406 | // ========================================================================== | |
4407 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_nzd_cust/rtl/n2_core_pll_tpm_nzd_cust.v | |
4408 | // ========================================================================== | |
4409 | /* | |
4410 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_nzd_cust/schematic/sch.cdb | |
4411 | Last Modified: Monday Sep 19,2005 at 12:10:20 PM PDT | |
4412 | By: ky82615 | |
4413 | */ | |
4414 | module n2_core_pll_tpm_nzd_cust(vdd_reg ,q2b ,q4b ,q3b ,zero ,q1b ,q0b , | |
4415 | q5b ); | |
4416 | output zero ; | |
4417 | input vdd_reg ; | |
4418 | input q2b ; | |
4419 | input q4b ; | |
4420 | input q3b ; | |
4421 | input q1b ; | |
4422 | input q0b ; | |
4423 | input q5b ; | |
4424 | ||
4425 | wire net22 ; | |
4426 | wire net28 ; | |
4427 | wire net33 ; | |
4428 | ||
4429 | ||
4430 | n2_core_pll_nand3_2x_cust x2 ( | |
4431 | .vdd_reg (vdd_reg ), | |
4432 | .out (net28 ), | |
4433 | .in2 (q2b ), | |
4434 | .in1 (q1b ), | |
4435 | .in0 (q0b ) ); | |
4436 | n2_core_pll_nand3_2x_cust x3 ( | |
4437 | .vdd_reg (vdd_reg ), | |
4438 | .out (net33 ), | |
4439 | .in2 (q5b ), | |
4440 | .in1 (q4b ), | |
4441 | .in0 (q3b ) ); | |
4442 | n2_core_pll_inv_4x_cust x0 ( | |
4443 | .vdd_reg (vdd_reg ), | |
4444 | .out (zero ), | |
4445 | .in (net22 ) ); | |
4446 | n2_core_pll_nor2_2x_cust x1 ( | |
4447 | .vdd_reg (vdd_reg ), | |
4448 | .out (net22 ), | |
4449 | .in1 (net33 ), | |
4450 | .in0 (net28 ) ); | |
4451 | endmodule | |
4452 | ||
4453 | ||
4454 | // ========================================================================== | |
4455 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_xnor2_4x_new_cust/rtl/n2_core_pll_xnor2_4x_new_cust.v | |
4456 | // ========================================================================== | |
4457 | // | |
4458 | // Last Modified: Friday Aug 26,2005 at 03:22:27 PM PDT | |
4459 | // | |
4460 | ||
4461 | module n2_core_pll_xnor2_4x_new_cust(vdd_reg ,out ,in0 ,in1 ); | |
4462 | output out ; | |
4463 | input vdd_reg ; | |
4464 | input in0 ; | |
4465 | input in1 ; | |
4466 | wire vss = 1'b0; | |
4467 | ||
4468 | assign out = ~(in0 ^ in1); | |
4469 | ||
4470 | endmodule | |
4471 | ||
4472 | // ========================================================================== | |
4473 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_sync_cust/rtl/n2_core_pll_d4_sync_cust.v | |
4474 | // ========================================================================== | |
4475 | // | |
4476 | // Last Modified: Friday Aug 26,2005 at 03:19:55 PM PDT | |
4477 | // | |
4478 | ||
4479 | module n2_core_pll_d4_sync_cust(dft_rst_l ,bs_rstps_4 ,bs_rstps_0 , | |
4480 | bs_pclk_4 ,bs_pclk_0 ); | |
4481 | output bs_rstps_4 ; | |
4482 | output bs_rstps_0 ; | |
4483 | input dft_rst_l ; | |
4484 | input bs_pclk_4 ; | |
4485 | input bs_pclk_0 ; | |
4486 | supply1 vdd ; | |
4487 | ||
4488 | wire [4:4] rstp ; | |
4489 | wire net014 ; | |
4490 | wire net031 ; | |
4491 | wire net46 ; | |
4492 | ||
4493 | ||
4494 | n2_core_pll_flop_reset2_cust x2 ( | |
4495 | .d (rstp_4 ), | |
4496 | .clk (bs_pclk_4 ), | |
4497 | .q_l (net46 ), | |
4498 | .q (net031 ) ); | |
4499 | n2_core_pll_inv1_16x_cust x7 ( | |
4500 | .vdd_reg (vdd ), | |
4501 | .out (bs_rstps_0 ), | |
4502 | .in (net014 ) ); | |
4503 | n2_core_pll_flop_reset2_cust x0 ( | |
4504 | .d (dft_rst_l ), | |
4505 | .clk (bs_pclk_0 ), | |
4506 | .q_l (rstp_4 ), | |
4507 | .q (net014 ) ); | |
4508 | n2_core_pll_inv1_16x_cust x1 ( | |
4509 | .vdd_reg (vdd ), | |
4510 | .out (bs_rstps_4 ), | |
4511 | .in (net46 ) ); | |
4512 | endmodule | |
4513 | ||
4514 | // ========================================================================== | |
4515 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_fse2diff_out_cust/rtl/n2_core_pll_fse2diff_out_cust.v | |
4516 | // ========================================================================== | |
4517 | // | |
4518 | // Last Modified: Friday Aug 26,2005 at 03:20:23 PM PDT | |
4519 | // | |
4520 | ||
4521 | module n2_core_pll_fse2diff_out_cust(vdd_reg ,in ,out_l ,out ); | |
4522 | output out_l ; | |
4523 | output out ; | |
4524 | input vdd_reg ; | |
4525 | input in ; | |
4526 | wire vss = 1'b0; | |
4527 | ||
4528 | assign out = in; | |
4529 | assign out_l = ~in; | |
4530 | ||
4531 | endmodule | |
4532 | ||
4533 | // ========================================================================== | |
4534 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_ctl_cust/rtl/n2_core_pll_d4_ctl_cust.v | |
4535 | // ========================================================================== | |
4536 | /* | |
4537 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_ctl_cust/schematic/sch.cdb | |
4538 | Last Modified: Monday Sep 19,2005 at 12:13:09 PM PDT | |
4539 | By: ky82615 | |
4540 | */ | |
4541 | module n2_core_pll_d4_ctl_cust(cac_l ,csel_l ,pclk ,out_clk ,eq ,in_clk | |
4542 | ,csel ,rstps ,a ); | |
4543 | output [1:1] csel_l ; | |
4544 | output [1:1] csel ; | |
4545 | input [4:0] a ; | |
4546 | output cac_l ; | |
4547 | output pclk ; | |
4548 | output out_clk ; | |
4549 | input eq ; | |
4550 | input in_clk ; | |
4551 | input rstps ; | |
4552 | supply1 vdd ; | |
4553 | wire vss = 1'b0; | |
4554 | ||
4555 | wire [3:1] carry ; | |
4556 | wire [1:0] csel_a1 ; | |
4557 | wire [2:0] sum ; | |
4558 | wire [1:0] csel_a1_l ; | |
4559 | wire net089 ; | |
4560 | wire mux_clk_l ; | |
4561 | wire ca2_a1_l ; | |
4562 | wire net94 ; | |
4563 | wire net034 ; | |
4564 | wire net043 ; | |
4565 | wire net045 ; | |
4566 | wire rst1 ; | |
4567 | wire ca2_a1 ; | |
4568 | wire mux_clk ; | |
4569 | wire nreset ; | |
4570 | ||
4571 | ||
4572 | n2_core_pll_tpm1_cust x2 ( | |
4573 | .ip ({a[4:2] } ), | |
4574 | .nreset (nreset ), | |
4575 | .ca2_a1 (ca2_a1 ), | |
4576 | .cac_l (cac_l ), | |
4577 | .reset (rst1 ), | |
4578 | .sel_l (mux_clk ), | |
4579 | .sel (mux_clk_l ), | |
4580 | .vco_ck (in_clk ) ); | |
4581 | cl_u1_inv_8x x5 ( | |
4582 | .out (net034 ), | |
4583 | .in (rstps ) ); | |
4584 | n2_core_pll_flop_reset1_cust xa_0_ ( | |
4585 | .reset_val_l (vdd ), | |
4586 | .d (sum[0] ), | |
4587 | .reset (rst1 ), | |
4588 | .clk (mux_clk ), | |
4589 | .q_l (csel_a1_l[0] ), | |
4590 | .q (csel_a1[0] ) ); | |
4591 | n2_core_pll_inv1_32x_cust x6 ( | |
4592 | .out (rst1 ), | |
4593 | .in (net043 ) ); | |
4594 | cl_u1_nand2_8x x7 ( | |
4595 | .out (nreset ), | |
4596 | .in1 (a[4] ), | |
4597 | .in0 (net043 ) ); | |
4598 | //terminator i22 ( | |
4599 | // .TERM (ca2_a1_l ) ); | |
4600 | //terminator i3 ( | |
4601 | // .TERM (carry[3] ) ); | |
4602 | //terminator i24 ( | |
4603 | // .TERM (net045 ) ); | |
4604 | n2_core_pll_flop_reset1_cust xa_1_ ( | |
4605 | .reset_val_l (vdd ), | |
4606 | .d (sum[1] ), | |
4607 | .reset (rst1 ), | |
4608 | .clk (mux_clk ), | |
4609 | .q_l (csel_a1_l[1] ), | |
4610 | .q (csel_a1[1] ) ); | |
4611 | cl_u1_nand2_8x x11 ( | |
4612 | .out (out_clk ), | |
4613 | .in1 (eq ), | |
4614 | .in0 (mux_clk_l ) ); | |
4615 | n2_core_pll_flop_reset2_cust x13 ( | |
4616 | .d (net034 ), | |
4617 | .clk (in_clk ), | |
4618 | .q_l (net045 ), | |
4619 | .q (net043 ) ); | |
4620 | n2_core_pll_flop_reset1_cust xa_2_ ( | |
4621 | .reset_val_l (vdd ), | |
4622 | .d (sum[2] ), | |
4623 | .reset (rst1 ), | |
4624 | .clk (mux_clk ), | |
4625 | .q_l (ca2_a1_l ), | |
4626 | .q (ca2_a1 ) ); | |
4627 | n2_core_pll_csa32_cust xb_0_ ( | |
4628 | .in0 (csel_a1[0] ), | |
4629 | .sum (sum[0] ), | |
4630 | .in0_l (csel_a1_l[0] ), | |
4631 | .carry (carry[1] ), | |
4632 | .in2 (vss ), | |
4633 | .in1 (a[0] ) ); | |
4634 | n2_core_pll_inv1_16x_cust x22 ( | |
4635 | .vdd_reg (vdd ), | |
4636 | .out (pclk ), | |
4637 | .in (net94 ) ); | |
4638 | n2_core_pll_csa32_cust xb_1_ ( | |
4639 | .in0 (csel_a1[1] ), | |
4640 | .sum (sum[1] ), | |
4641 | .in0_l (csel_a1_l[1] ), | |
4642 | .carry (carry[2] ), | |
4643 | .in2 (carry[1] ), | |
4644 | .in1 (a[1] ) ); | |
4645 | cl_u1_buf_1x x3_1_ ( | |
4646 | .out (net089 ), | |
4647 | .in (csel_a1[1] ) ); | |
4648 | n2_core_pll_csa32_cust xb_2_ ( | |
4649 | .in0 (vss ), | |
4650 | .sum (sum[2] ), | |
4651 | .in0_l (vdd ), | |
4652 | .carry (carry[3] ), | |
4653 | .in2 (carry[2] ), | |
4654 | .in1 (vss ) ); | |
4655 | n2_core_pll_flop_reset1_cust x0_1_ ( | |
4656 | .reset_val_l (vdd ), | |
4657 | .d (net089 ), | |
4658 | .reset (rst1 ), | |
4659 | .clk (mux_clk ), | |
4660 | .q_l (csel_l[1] ), | |
4661 | .q (csel[1] ) ); | |
4662 | cl_u1_inv_4x x1 ( | |
4663 | .out (net94 ), | |
4664 | .in (in_clk ) ); | |
4665 | endmodule | |
4666 | ||
4667 | // ========================================================================== | |
4668 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_mux_cust/rtl/n2_core_pll_d4_mux_cust.v | |
4669 | // ========================================================================== | |
4670 | // | |
4671 | // Last Modified: Friday Aug 26,2005 at 03:19:54 PM PDT | |
4672 | // | |
4673 | ||
4674 | module n2_core_pll_d4_mux_cust(out_clk ,rstps ,bs_pi_clk_4 ,bs_pi_clk_0 ); | |
4675 | input [0:0] rstps ; | |
4676 | output out_clk ; | |
4677 | input bs_pi_clk_4 ; | |
4678 | input bs_pi_clk_0 ; | |
4679 | supply1 vdd ; | |
4680 | wire vss = 1'b0; | |
4681 | ||
4682 | wire in8_clk_l ; | |
4683 | wire net032 ; | |
4684 | wire mux_clk ; | |
4685 | wire in8_clk ; | |
4686 | wire net61 ; | |
4687 | ||
4688 | ||
4689 | //cl_u1_nand2_4x x7 ( | |
4690 | // .out (mux_clk ), | |
4691 | // .in1 (bs_pi_clk_4 ), | |
4692 | // .in0 (bs_pi_clk_0 ) ); | |
4693 | cl_u1_nand2_4x x8 ( | |
4694 | .out (mux_clk ), | |
4695 | .in1 (bs_pi_clk_0 ), | |
4696 | .in0 (bs_pi_clk_4 ) ); | |
4697 | cl_u1_buf_1x x9 ( | |
4698 | .out (net61 ), | |
4699 | .in (in8_clk_l ) ); | |
4700 | n2_core_pll_flop_reset1_cust x17 ( | |
4701 | .reset_val_l (vss ), | |
4702 | .d (net61 ), | |
4703 | .reset (rstps[0] ), | |
4704 | .clk (mux_clk ), | |
4705 | .q_l (in8_clk_l ), | |
4706 | .q (in8_clk ) ); | |
4707 | n2_core_pll_inv_32x_cust x0 ( | |
4708 | .vdd_reg (vdd ), | |
4709 | .out (out_clk ), | |
4710 | .in (net032 ) ); | |
4711 | n2_core_pll_inv_8x_cust x1 ( | |
4712 | .vdd_reg (vdd ), | |
4713 | .out (net032 ), | |
4714 | .in (in8_clk ) ); | |
4715 | endmodule | |
4716 | ||
4717 | // ========================================================================== | |
4718 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_flop_reset1_cust/rtl/n2_core_pll_flop_reset1_cust.v | |
4719 | // ========================================================================== | |
4720 | // | |
4721 | // Last Modified: Friday Aug 26,2005 at 03:20:17 PM PDT | |
4722 | // | |
4723 | ||
4724 | module n2_core_pll_flop_reset1_cust(reset_val_l ,d ,reset ,clk ,q_l ,q | |
4725 | ); | |
4726 | output q_l ; | |
4727 | output q ; | |
4728 | input reset_val_l ; | |
4729 | input d ; | |
4730 | input reset ; | |
4731 | input clk ; | |
4732 | supply1 vdd ; | |
4733 | ||
4734 | reg q; | |
4735 | reg qb; | |
4736 | ||
4737 | /* | |
4738 | always | |
4739 | @( clk or d or reset ) | |
4740 | if ( reset ) | |
4741 | qb <= !reset_val_l; | |
4742 | else if ( !clk ) | |
4743 | qb <= d; | |
4744 | ||
4745 | always | |
4746 | @( clk or reset ) | |
4747 | if ( reset ) | |
4748 | q <= !reset_val_l; | |
4749 | else if ( clk ) | |
4750 | q <= qb; | |
4751 | */ | |
4752 | ||
4753 | always @( posedge clk or posedge reset ) begin | |
4754 | if (reset) | |
4755 | q <= ~reset_val_l; | |
4756 | else | |
4757 | q <= d; | |
4758 | end | |
4759 | ||
4760 | assign q_l = !q; | |
4761 | ||
4762 | endmodule | |
4763 | ||
4764 | // ========================================================================== | |
4765 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm1_cust/rtl/n2_core_pll_tpm1_cust.v | |
4766 | // ========================================================================== | |
4767 | /* | |
4768 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm1_cust/schematic/sch.cdb | |
4769 | Last Modified: Monday Sep 19,2005 at 12:09:54 PM PDT | |
4770 | By: ky82615 | |
4771 | */ | |
4772 | module n2_core_pll_tpm1_cust(nreset ,ca2_a1 ,cac_l ,reset ,sel_l ,sel , | |
4773 | ip ,vco_ck ); | |
4774 | input [2:0] ip ; | |
4775 | output cac_l ; | |
4776 | output sel_l ; | |
4777 | output sel ; | |
4778 | input nreset ; | |
4779 | input ca2_a1 ; | |
4780 | input reset ; | |
4781 | input vco_ck ; | |
4782 | supply1 vdd ; | |
4783 | wire vss = 1'b0; | |
4784 | ||
4785 | wire d3 ; | |
4786 | wire q0_l ; | |
4787 | wire q1_l ; | |
4788 | wire q2_l ; | |
4789 | wire net75 ; | |
4790 | wire q3_l ; | |
4791 | wire vco_ck_l ; | |
4792 | wire ca3 ; | |
4793 | wire net121 ; | |
4794 | wire d22 ; | |
4795 | wire net128 ; | |
4796 | wire d22_l ; | |
4797 | wire net130 ; | |
4798 | wire net132 ; | |
4799 | wire net0165 ; | |
4800 | wire net137 ; | |
4801 | wire net143 ; | |
4802 | wire sel1 ; | |
4803 | wire qa2_l ; | |
4804 | wire q0 ; | |
4805 | wire q1 ; | |
4806 | wire q2 ; | |
4807 | wire q3 ; | |
4808 | wire l1clk ; | |
4809 | wire net173 ; | |
4810 | wire net174 ; | |
4811 | wire sel1_q ; | |
4812 | wire d0 ; | |
4813 | wire d1 ; | |
4814 | wire d2 ; | |
4815 | ||
4816 | ||
4817 | //terminator i15 ( | |
4818 | // .TERM (q3 ) ); | |
4819 | n2_core_pll_flop_reset2_cust x2 ( | |
4820 | .d (ca2_a1 ), | |
4821 | .clk (vco_ck ), | |
4822 | .q_l (net174 ), | |
4823 | .q (qa2_l ) ); | |
4824 | //terminator i16 ( | |
4825 | // .TERM (q2 ) ); | |
4826 | cl_u1_inv_8x x3 ( | |
4827 | .out (vco_ck_l ), | |
4828 | .in (vco_ck ) ); | |
4829 | //terminator i17 ( | |
4830 | // .TERM (q1 ) ); | |
4831 | n2_core_pll_inv1_16x_cust x4 ( | |
4832 | .vdd_reg (vdd ), | |
4833 | .out (d22 ), | |
4834 | .in (q0 ) ); | |
4835 | n2_core_pll_tpm_mux1_cust x5 ( | |
4836 | .sel_l (d22_l ), | |
4837 | .vdd_reg (vdd ), | |
4838 | .out_l (d1 ), | |
4839 | .d0 (net132 ), | |
4840 | .d1 (q2_l ), | |
4841 | .sel (d22 ) ); | |
4842 | n2_core_pll_flop_reset2_cust x6 ( | |
4843 | .d (sel1 ), | |
4844 | .clk (vco_ck_l ), | |
4845 | .q_l (net121 ), | |
4846 | .q (sel1_q ) ); | |
4847 | n2_core_pll_inv_32x_cust x7 ( | |
4848 | .vdd_reg (vdd ), | |
4849 | .out (l1clk ), | |
4850 | .in (net137 ) ); | |
4851 | n2_core_pll_flop_reset1_cust x8 ( | |
4852 | .reset_val_l (vss ), | |
4853 | .d (d1 ), | |
4854 | .reset (reset ), | |
4855 | .clk (l1clk ), | |
4856 | .q_l (q1_l ), | |
4857 | .q (q1 ) ); | |
4858 | n2_core_pll_flop_reset2_cust x9 ( | |
4859 | .d (ca3 ), | |
4860 | .clk (vco_ck_l ), | |
4861 | .q_l (net173 ), | |
4862 | .q (cac_l ) ); | |
4863 | //terminator i6 ( | |
4864 | // .TERM (net121 ) ); | |
4865 | //terminator i9 ( | |
4866 | // .TERM (ip[0] ) ); | |
4867 | cl_u1_nand2_8x x10 ( | |
4868 | .out (ca3 ), | |
4869 | .in1 (qa2_l ), | |
4870 | .in0 (sel1 ) ); | |
4871 | n2_core_pll_tpm_mux1_cust x11 ( | |
4872 | .sel_l (d22_l ), | |
4873 | .vdd_reg (vdd ), | |
4874 | .out_l (d2 ), | |
4875 | .d0 (vdd ), | |
4876 | .d1 (q3_l ), | |
4877 | .sel (d22 ) ); | |
4878 | n2_core_pll_flop_reset1_cust x12 ( | |
4879 | .reset_val_l (vss ), | |
4880 | .d (d3 ), | |
4881 | .reset (nreset ), | |
4882 | .clk (l1clk ), | |
4883 | .q_l (q3_l ), | |
4884 | .q (q3 ) ); | |
4885 | n2_core_pll_inv1_32x_cust x13 ( | |
4886 | .out (sel_l ), | |
4887 | .in (net143 ) ); | |
4888 | cl_u1_nand2_8x x14 ( | |
4889 | .out (net143 ), | |
4890 | .in1 (sel1_q ), | |
4891 | .in0 (vco_ck ) ); | |
4892 | cl_u1_inv_1x x15 ( | |
4893 | .out (net130 ), | |
4894 | .in (ip[2] ) ); | |
4895 | n2_core_pll_tpm_mux1_cust x16 ( | |
4896 | .sel_l (d22_l ), | |
4897 | .vdd_reg (vdd ), | |
4898 | .out_l (d3 ), | |
4899 | .d0 (ip[0] ), | |
4900 | .d1 (vss ), | |
4901 | .sel (d22 ) ); | |
4902 | n2_core_pll_inv1_16x_cust x17 ( | |
4903 | .vdd_reg (vdd ), | |
4904 | .out (d22_l ), | |
4905 | .in (q0_l ) ); | |
4906 | cl_u1_nand2_2x x18 ( | |
4907 | .out (net132 ), | |
4908 | .in1 (net130 ), | |
4909 | .in0 (net128 ) ); | |
4910 | cl_u1_inv_1x x19 ( | |
4911 | .out (net128 ), | |
4912 | .in (ip[0] ) ); | |
4913 | cl_u1_inv_1x x20 ( | |
4914 | .out (net0165 ), | |
4915 | .in (ip[1] ) ); | |
4916 | n2_core_pll_flop_reset1_cust x22 ( | |
4917 | .reset_val_l (vss ), | |
4918 | .d (d22 ), | |
4919 | .reset (reset ), | |
4920 | .clk (vco_ck ), | |
4921 | .q_l (sel1 ), | |
4922 | .q (net75 ) ); | |
4923 | n2_core_pll_tpm_mux1_cust x36 ( | |
4924 | .sel_l (d22_l ), | |
4925 | .vdd_reg (vdd ), | |
4926 | .out_l (d0 ), | |
4927 | .d0 (vdd ), | |
4928 | .d1 (q1_l ), | |
4929 | .sel (d22 ) ); | |
4930 | n2_core_pll_flop_reset1_cust x45 ( | |
4931 | .reset_val_l (vss ), | |
4932 | .d (d0 ), | |
4933 | .reset (reset ), | |
4934 | .clk (l1clk ), | |
4935 | .q_l (q0_l ), | |
4936 | .q (q0 ) ); | |
4937 | n2_core_pll_flop_reset1_cust x46 ( | |
4938 | .reset_val_l (vss ), | |
4939 | .d (d2 ), | |
4940 | .reset (nreset ), | |
4941 | .clk (l1clk ), | |
4942 | .q_l (q2_l ), | |
4943 | .q (q2 ) ); | |
4944 | //terminator ix3 ( | |
4945 | // .TERM (net174 ) ); | |
4946 | //terminator ix8 ( | |
4947 | // .TERM (net173 ) ); | |
4948 | //terminator i10 ( | |
4949 | // .TERM (net0165 ) ); | |
4950 | //terminator i11 ( | |
4951 | // .TERM (ip[2] ) ); | |
4952 | n2_core_pll_nand2_8x_cust x0 ( | |
4953 | .vsup (vdd ), | |
4954 | .out (net137 ), | |
4955 | .in1 (cac_l ), | |
4956 | .in0 (vco_ck ) ); | |
4957 | n2_core_pll_inv1_16x_cust x1 ( | |
4958 | .vdd_reg (vdd ), | |
4959 | .out (sel ), | |
4960 | .in (net75 ) ); | |
4961 | endmodule | |
4962 | ||
4963 | ||
4964 | // ========================================================================== | |
4965 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv1_32x_cust/rtl/n2_core_pll_inv1_32x_cust.v | |
4966 | // ========================================================================== | |
4967 | // | |
4968 | // Last Modified: Friday Aug 26,2005 at 03:20:25 PM PDT | |
4969 | // | |
4970 | ||
4971 | module n2_core_pll_inv1_32x_cust(out ,in ); | |
4972 | output out ; | |
4973 | input in ; | |
4974 | supply1 vdd ; | |
4975 | wire vss = 1'b0; | |
4976 | ||
4977 | assign out = ~in; | |
4978 | ||
4979 | endmodule | |
4980 | ||
4981 | // ========================================================================== | |
4982 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_flop_reset2_cust/rtl/n2_core_pll_flop_reset2_cust.v | |
4983 | // ========================================================================== | |
4984 | // mh157021: lower level module definition (n2_core_pll_flop_reset2_cust) | |
4985 | // | |
4986 | // Last Modified: Tuesday Sep 6,2005 at 02:49:34 PM PDT | |
4987 | // | |
4988 | ||
4989 | module n2_core_pll_flop_reset2_cust(d ,clk ,q_l ,q ); | |
4990 | output q_l ; | |
4991 | output q ; | |
4992 | input d ; | |
4993 | input clk ; | |
4994 | supply1 vdd ; | |
4995 | ||
4996 | reg q; | |
4997 | reg q_b; | |
4998 | ||
4999 | /* | |
5000 | always | |
5001 | @( clk or d ) | |
5002 | if ( !clk ) | |
5003 | q_b <= d; | |
5004 | else | |
5005 | q_b <= q_b; | |
5006 | ||
5007 | always | |
5008 | @( clk ) | |
5009 | if ( clk ) | |
5010 | q <= q_b; | |
5011 | else | |
5012 | q <= q; | |
5013 | */ | |
5014 | assign q_l = !q; | |
5015 | ||
5016 | always @(posedge clk) begin | |
5017 | q <= d; | |
5018 | end | |
5019 | ||
5020 | endmodule | |
5021 | ||
5022 | // ========================================================================== | |
5023 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_csa32_cust/rtl/n2_core_pll_csa32_cust.v | |
5024 | // ========================================================================== | |
5025 | // | |
5026 | // Last Modified: Friday Aug 26,2005 at 03:19:32 PM PDT | |
5027 | // | |
5028 | ||
5029 | module n2_core_pll_csa32_cust(in0 ,sum ,in0_l ,carry ,in2 ,in1 ); | |
5030 | output sum ; | |
5031 | output carry ; | |
5032 | input in0 ; | |
5033 | input in0_l ; | |
5034 | input in2 ; | |
5035 | input in1 ; | |
5036 | ||
5037 | fadd x1 ( | |
5038 | .cin (in0), | |
5039 | .a (in1), | |
5040 | .b (in2), | |
5041 | .s (sum), | |
5042 | .cout (carry) ); | |
5043 | ||
5044 | endmodule | |
5045 | ||
5046 | // ========================================================================== | |
5047 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_csa32_cust/rtl/fadd.v | |
5048 | // ========================================================================== | |
5049 | module fadd ( cin,a,b,s,cout ); | |
5050 | ||
5051 | input cin, a, b; | |
5052 | output s, cout; | |
5053 | ||
5054 | assign s = cin^a^b; | |
5055 | assign cout = cin&a|cin&b|a&b; | |
5056 | ||
5057 | endmodule | |
5058 | ||
5059 | // ========================================================================== | |
5060 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv1_16x_cust/rtl/n2_core_pll_inv1_16x_cust.v | |
5061 | // ========================================================================== | |
5062 | // mh157021: lower level module definition (n2_core_pll_inv1_16x_cust) | |
5063 | // | |
5064 | // Last Modified: Friday Aug 26,2005 at 03:20:24 PM PDT | |
5065 | // | |
5066 | ||
5067 | module n2_core_pll_inv1_16x_cust(vdd_reg ,out ,in ); | |
5068 | output out ; | |
5069 | input vdd_reg ; | |
5070 | input in ; | |
5071 | wire vss = 1'b0; | |
5072 | ||
5073 | assign out = ~in; | |
5074 | ||
5075 | endmodule | |
5076 | ||
5077 | // ========================================================================== | |
5078 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm_mux1_cust/rtl/n2_core_pll_tpm_mux1_cust.v | |
5079 | // ========================================================================== | |
5080 | // | |
5081 | // Last Modified: Friday Aug 26,2005 at 03:21:51 PM PDT | |
5082 | // | |
5083 | ||
5084 | module n2_core_pll_tpm_mux1_cust(sel_l ,vdd_reg ,out_l ,d0 ,d1 ,sel ); | |
5085 | output out_l ; | |
5086 | input sel_l ; | |
5087 | input vdd_reg ; | |
5088 | input d0 ; | |
5089 | input d1 ; | |
5090 | input sel ; | |
5091 | wire vss = 1'b0; | |
5092 | ||
5093 | mux2s x1 ( | |
5094 | .sel0 (sel_l), | |
5095 | .sel1 (sel), | |
5096 | .in0 (d0), | |
5097 | .in1 (d1), | |
5098 | .dout (out) ); | |
5099 | ||
5100 | assign out_l = ~out; | |
5101 | ||
5102 | endmodule | |
5103 | ||
5104 | // ========================================================================== | |
5105 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_nand2_8x_cust/rtl/n2_core_pll_nand2_8x_cust.v | |
5106 | // ========================================================================== | |
5107 | // | |
5108 | // Last Modified: Friday Aug 26,2005 at 03:20:57 PM PDT | |
5109 | // | |
5110 | ||
5111 | module n2_core_pll_nand2_8x_cust(vsup ,out ,in1 ,in0 ); | |
5112 | output out ; | |
5113 | input vsup ; | |
5114 | input in1 ; | |
5115 | input in0 ; | |
5116 | wire vss = 1'b0; | |
5117 | ||
5118 | assign out = ~(in0 & in1); | |
5119 | ||
5120 | endmodule | |
5121 | ||
5122 | // ========================================================================== | |
5123 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_div4_cust/rtl/n2_core_pll_div4_cust.v | |
5124 | // ========================================================================== | |
5125 | /* | |
5126 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_div4_cust/schematic/sch.cdb | |
5127 | Last Modified: Monday Sep 19,2005 at 12:12:32 PM PDT | |
5128 | By: ky82615 | |
5129 | */ | |
5130 | module n2_core_pll_div4_cust(clk ,arst_l ,clk_div_out ); | |
5131 | output clk_div_out ; | |
5132 | input clk ; | |
5133 | input arst_l ; | |
5134 | supply1 vdd ; | |
5135 | ||
5136 | wire div4_l ; | |
5137 | wire clk_div ; | |
5138 | wire n1 ; | |
5139 | wire n2 ; | |
5140 | wire n3 ; | |
5141 | wire n4 ; | |
5142 | wire net19 ; | |
5143 | wire net038 ; | |
5144 | wire net26 ; | |
5145 | wire net33 ; | |
5146 | wire clk_div_l ; | |
5147 | wire div2_l ; | |
5148 | ||
5149 | ||
5150 | n2_core_pll_inv_8x_cust x2 ( | |
5151 | .vdd_reg (vdd ), | |
5152 | .out (clk_div_l ), | |
5153 | .in (clk_div ) ); | |
5154 | cl_u1_inv_4x x3 ( | |
5155 | .out (net038 ), | |
5156 | .in (arst_l ) ); | |
5157 | n2_core_pll_flop_reset_new_cust x4 ( | |
5158 | .vdd_reg (vdd ), | |
5159 | .reset_val_l (vdd ), | |
5160 | .d (n2 ), | |
5161 | .reset (net038 ), | |
5162 | .clk (clk ), | |
5163 | .q_l (div2_l ), | |
5164 | .q (net33 ) ); | |
5165 | n2_core_pll_flop_reset_new_cust x5 ( | |
5166 | .vdd_reg (vdd ), | |
5167 | .reset_val_l (vdd ), | |
5168 | .d (n4 ), | |
5169 | .reset (net038 ), | |
5170 | .clk (div2_l ), | |
5171 | .q_l (div4_l ), | |
5172 | .q (net26 ) ); | |
5173 | n2_core_pll_flop_reset_new_cust x6 ( | |
5174 | .vdd_reg (vdd ), | |
5175 | .reset_val_l (vdd ), | |
5176 | .d (div4_l ), | |
5177 | .reset (net038 ), | |
5178 | .clk (clk ), | |
5179 | .q_l (clk_div ), | |
5180 | .q (net19 ) ); | |
5181 | n2_core_pll_buf_2x_cust x9 ( | |
5182 | .vdd_reg (vdd ), | |
5183 | .out (n2 ), | |
5184 | .in (n1 ) ); | |
5185 | n2_core_pll_buf_2x_cust x10 ( | |
5186 | .vdd_reg (vdd ), | |
5187 | .out (n3 ), | |
5188 | .in (div4_l ) ); | |
5189 | n2_core_pll_buf_2x_cust x11 ( | |
5190 | .vdd_reg (vdd ), | |
5191 | .out (n4 ), | |
5192 | .in (n3 ) ); | |
5193 | //terminator ix3 ( | |
5194 | // .TERM (net33 ) ); | |
5195 | //terminator ix4 ( | |
5196 | // .TERM (net26 ) ); | |
5197 | //terminator ix5 ( | |
5198 | // .TERM (net19 ) ); | |
5199 | n2_core_pll_buf_2x_cust x0 ( | |
5200 | .vdd_reg (vdd ), | |
5201 | .out (n1 ), | |
5202 | .in (div2_l ) ); | |
5203 | n2_core_pll_inv_32x_cust x1 ( | |
5204 | .vdd_reg (vdd ), | |
5205 | .out (clk_div_out ), | |
5206 | .in (clk_div_l ) ); | |
5207 | endmodule | |
5208 | ||
5209 | ||
5210 | // ========================================================================== | |
5211 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_16x_cust/rtl/n2_core_pll_inv_16x_cust.v | |
5212 | // ========================================================================== | |
5213 | // mh157021: lower level module definition (n2_core_pll_inv_16x_cust) | |
5214 | // | |
5215 | // Last Modified: Friday Aug 26,2005 at 03:20:28 PM PDT | |
5216 | // | |
5217 | ||
5218 | module n2_core_pll_inv_16x_cust(vdd_reg ,out ,in ); | |
5219 | output out ; | |
5220 | input vdd_reg ; | |
5221 | input in ; | |
5222 | wire vss = 1'b0; | |
5223 | ||
5224 | assign out = ~in; | |
5225 | ||
5226 | endmodule | |
5227 | ||
5228 | // ========================================================================== | |
5229 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm3_cust/rtl/n2_core_pll_tpm3_cust.v | |
5230 | // ========================================================================== | |
5231 | /* | |
5232 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm3_cust/schematic/sch.cdb | |
5233 | Last Modified: Wednesday Oct 12,2005 at 04:19:44 PM PDT | |
5234 | By: ky82615 | |
5235 | */ | |
5236 | module n2_core_pll_tpm3_cust(reset ,ip ,vdd_reg ,op ,sel ,div_ck_i , | |
5237 | pwr_rst ,div_ck ,vco_ck ); | |
5238 | output [5:0] op ; | |
5239 | input [5:0] ip ; | |
5240 | output sel ; | |
5241 | output div_ck ; | |
5242 | input reset ; | |
5243 | input vdd_reg ; | |
5244 | input div_ck_i ; | |
5245 | input pwr_rst ; | |
5246 | input vco_ck ; | |
5247 | wire vss = 1'b0; | |
5248 | ||
5249 | wire net183 ; | |
5250 | wire nz_2 ; | |
5251 | wire net201 ; | |
5252 | wire net282 ; | |
5253 | wire nz_3 ; | |
5254 | wire nz_4 ; | |
5255 | wire nz_5 ; | |
5256 | wire net186 ; | |
5257 | wire net205 ; | |
5258 | wire f4q ; | |
5259 | wire f5d ; | |
5260 | wire net195 ; | |
5261 | wire vco_ckb ; | |
5262 | wire vco_ckd ; | |
5263 | wire net198 ; | |
5264 | wire f5q ; | |
5265 | wire r_gate ; | |
5266 | wire reset_d ; | |
5267 | wire net0362 ; | |
5268 | wire net235 ; | |
5269 | wire zero_0 ; | |
5270 | wire net236 ; | |
5271 | wire zero_1 ; | |
5272 | wire zero_2 ; | |
5273 | wire f0d ; | |
5274 | wire zero_3 ; | |
5275 | wire zero_4 ; | |
5276 | wire zero_5 ; | |
5277 | wire sel_b ; | |
5278 | wire f0q ; | |
5279 | wire net147 ; | |
5280 | wire f1d ; | |
5281 | wire net252 ; | |
5282 | wire net256 ; | |
5283 | wire net0248 ; | |
5284 | wire net159 ; | |
5285 | wire f1q ; | |
5286 | wire f2d ; | |
5287 | wire nzero_0 ; | |
5288 | wire nzero_1 ; | |
5289 | wire net162 ; | |
5290 | wire nzero_2 ; | |
5291 | wire nzero_3 ; | |
5292 | wire nzero_4 ; | |
5293 | wire nzero_5 ; | |
5294 | wire f2q ; | |
5295 | wire next0 ; | |
5296 | wire next1 ; | |
5297 | wire next2 ; | |
5298 | wire next3 ; | |
5299 | wire f3d ; | |
5300 | wire next4 ; | |
5301 | wire next5 ; | |
5302 | wire net171 ; | |
5303 | wire nip0 ; | |
5304 | wire nip1 ; | |
5305 | wire nip2 ; | |
5306 | wire nip3 ; | |
5307 | wire nip4 ; | |
5308 | wire nip5 ; | |
5309 | wire net0501 ; | |
5310 | wire f3q ; | |
5311 | wire net0502 ; | |
5312 | wire net0503 ; | |
5313 | wire net0504 ; | |
5314 | wire f4d ; | |
5315 | wire net0505 ; | |
5316 | wire net0506 ; | |
5317 | wire nz_0 ; | |
5318 | wire nz_1 ; | |
5319 | ||
5320 | ||
5321 | n2_core_pll_buf_4x_cust x2 ( | |
5322 | .vdd_reg (vdd_reg ), | |
5323 | .out (net205 ), | |
5324 | .in (ip[0] ) ); | |
5325 | n2_core_pll_buf_16x_cust x4 ( | |
5326 | .vdd_reg (vdd_reg ), | |
5327 | .out (reset_d ), | |
5328 | .in (reset ) ); | |
5329 | n2_core_pll_tpm_mux_cust x5 ( | |
5330 | .opb (nzero_0 ), | |
5331 | .vdd_reg (vdd_reg ), | |
5332 | .op (nz_0 ), | |
5333 | .d0 (ip[0] ), | |
5334 | .d1 (nip0 ), | |
5335 | .sel (net256 ), | |
5336 | .sel_b (net282 ) ); | |
5337 | n2_core_pll_buf_8x_cust x6 ( | |
5338 | .vdd_reg (vdd_reg ), | |
5339 | .out (net282 ), | |
5340 | .in (pwr_rst ) ); | |
5341 | n2_core_pll_inv_8x_cust x7 ( | |
5342 | .vdd_reg (vdd_reg ), | |
5343 | .out (net256 ), | |
5344 | .in (pwr_rst ) ); | |
5345 | n2_core_pll_buf_4x_cust x8 ( | |
5346 | .vdd_reg (vdd_reg ), | |
5347 | .out (net183 ), | |
5348 | .in (ip[1] ) ); | |
5349 | n2_core_pll_buf_4x_cust x9 ( | |
5350 | .vdd_reg (vdd_reg ), | |
5351 | .out (net195 ), | |
5352 | .in (ip[2] ) ); | |
5353 | n2_core_pll_buf_4x_cust x10 ( | |
5354 | .vdd_reg (vdd_reg ), | |
5355 | .out (net159 ), | |
5356 | .in (ip[3] ) ); | |
5357 | n2_core_pll_buf_4x_cust x11 ( | |
5358 | .vdd_reg (vdd_reg ), | |
5359 | .out (net147 ), | |
5360 | .in (ip[4] ) ); | |
5361 | n2_core_pll_buf_4x_cust x12 ( | |
5362 | .vdd_reg (vdd_reg ), | |
5363 | .out (net171 ), | |
5364 | .in (ip[5] ) ); | |
5365 | n2_core_pll_buf_8x_cust x13 ( | |
5366 | .vdd_reg (vdd_reg ), | |
5367 | .out (op[0] ), | |
5368 | .in (nip0 ) ); | |
5369 | n2_core_pll_buf_8x_cust x14 ( | |
5370 | .vdd_reg (vdd_reg ), | |
5371 | .out (op[1] ), | |
5372 | .in (nip1 ) ); | |
5373 | n2_core_pll_buf_8x_cust x15 ( | |
5374 | .vdd_reg (vdd_reg ), | |
5375 | .out (op[2] ), | |
5376 | .in (nip2 ) ); | |
5377 | n2_core_pll_tpm_next_new_cust x16 ( | |
5378 | .vdd_reg (vdd_reg ), | |
5379 | .d5 (next5 ), | |
5380 | .q0b (zero_0 ), | |
5381 | .q3b (zero_3 ), | |
5382 | .d3 (next3 ), | |
5383 | .q5b (zero_5 ), | |
5384 | .q1b (zero_1 ), | |
5385 | .q2b (zero_2 ), | |
5386 | .d2 (next2 ), | |
5387 | .d0 (next0 ), | |
5388 | .d4 (next4 ), | |
5389 | .q2 (f2q ), | |
5390 | .q0 (f0q ), | |
5391 | .q1 (f1q ), | |
5392 | .d1 (next1 ), | |
5393 | .q4b (zero_4 ) ); | |
5394 | n2_core_pll_tpm_mux_cust x17 ( | |
5395 | .opb (nzero_1 ), | |
5396 | .vdd_reg (vdd_reg ), | |
5397 | .op (nz_1 ), | |
5398 | .d0 (ip[1] ), | |
5399 | .d1 (nip1 ), | |
5400 | .sel (net256 ), | |
5401 | .sel_b (net282 ) ); | |
5402 | n2_core_pll_buf_8x_cust x18 ( | |
5403 | .vdd_reg (vdd_reg ), | |
5404 | .out (op[3] ), | |
5405 | .in (nip3 ) ); | |
5406 | n2_core_pll_buf_8x_cust x19 ( | |
5407 | .vdd_reg (vdd_reg ), | |
5408 | .out (op[4] ), | |
5409 | .in (nip4 ) ); | |
5410 | n2_core_pll_buf_8x_cust x20 ( | |
5411 | .vdd_reg (vdd_reg ), | |
5412 | .out (op[5] ), | |
5413 | .in (nip5 ) ); | |
5414 | n2_core_pll_tpm_mux_cust x23 ( | |
5415 | .opb (nzero_2 ), | |
5416 | .vdd_reg (vdd_reg ), | |
5417 | .op (nz_2 ), | |
5418 | .d0 (ip[2] ), | |
5419 | .d1 (nip2 ), | |
5420 | .sel (net256 ), | |
5421 | .sel_b (net282 ) ); | |
5422 | n2_core_pll_tpm_gate2_cust x24 ( | |
5423 | .vdd_reg (vdd_reg ), | |
5424 | .div_ck (div_ck ), | |
5425 | .r (r_gate ), | |
5426 | .ck (vco_ck ) ); | |
5427 | n2_core_pll_flop_reset_new_cust x25 ( | |
5428 | .vdd_reg (vdd_reg ), | |
5429 | .reset_val_l (vdd_reg ), | |
5430 | .d (net205 ), | |
5431 | .reset (reset_d ), | |
5432 | .clk (div_ck_i ), | |
5433 | .q_l (net201 ), | |
5434 | .q (nip0 ) ); | |
5435 | n2_core_pll_flop_reset_new_cust x26 ( | |
5436 | .vdd_reg (vdd_reg ), | |
5437 | .reset_val_l (vdd_reg ), | |
5438 | .d (net183 ), | |
5439 | .reset (reset_d ), | |
5440 | .clk (div_ck_i ), | |
5441 | .q_l (net186 ), | |
5442 | .q (nip1 ) ); | |
5443 | n2_core_pll_tpm_mux_cust x27 ( | |
5444 | .opb (nzero_3 ), | |
5445 | .vdd_reg (vdd_reg ), | |
5446 | .op (nz_3 ), | |
5447 | .d0 (ip[3] ), | |
5448 | .d1 (nip3 ), | |
5449 | .sel (net256 ), | |
5450 | .sel_b (net282 ) ); | |
5451 | n2_core_pll_tpm_mux_cust x28 ( | |
5452 | .opb (nzero_4 ), | |
5453 | .vdd_reg (vdd_reg ), | |
5454 | .op (nz_4 ), | |
5455 | .d0 (ip[4] ), | |
5456 | .d1 (nip4 ), | |
5457 | .sel (net256 ), | |
5458 | .sel_b (net282 ) ); | |
5459 | n2_core_pll_tpm_mux_cust x29 ( | |
5460 | .opb (nzero_5 ), | |
5461 | .vdd_reg (vdd_reg ), | |
5462 | .op (nz_5 ), | |
5463 | .d0 (ip[5] ), | |
5464 | .d1 (nip5 ), | |
5465 | .sel (net256 ), | |
5466 | .sel_b (net282 ) ); | |
5467 | //terminator i50 ( | |
5468 | // .TERM (f4q ) ); | |
5469 | n2_core_pll_flop_reset_new_cust x30 ( | |
5470 | .vdd_reg (vdd_reg ), | |
5471 | .reset_val_l (vdd_reg ), | |
5472 | .d (net195 ), | |
5473 | .reset (reset_d ), | |
5474 | .clk (div_ck_i ), | |
5475 | .q_l (net198 ), | |
5476 | .q (nip2 ) ); | |
5477 | //terminator i51 ( | |
5478 | // .TERM (f5q ) ); | |
5479 | n2_core_pll_inv_32x_cust x31 ( | |
5480 | .vdd_reg (vdd_reg ), | |
5481 | .out (vco_ckd ), | |
5482 | .in (net252 ) ); | |
5483 | //terminator i52 ( | |
5484 | // .TERM (net0248 ) ); | |
5485 | n2_core_pll_flop_reset_new_cust x32 ( | |
5486 | .vdd_reg (vdd_reg ), | |
5487 | .reset_val_l (vdd_reg ), | |
5488 | .d (net159 ), | |
5489 | .reset (reset_d ), | |
5490 | .clk (div_ck_i ), | |
5491 | .q_l (net162 ), | |
5492 | .q (nip3 ) ); | |
5493 | n2_core_pll_flop_reset_new_cust x33 ( | |
5494 | .vdd_reg (vdd_reg ), | |
5495 | .reset_val_l (vdd_reg ), | |
5496 | .d (net147 ), | |
5497 | .reset (reset_d ), | |
5498 | .clk (div_ck_i ), | |
5499 | .q_l (net235 ), | |
5500 | .q (nip4 ) ); | |
5501 | //terminator i54 ( | |
5502 | // .TERM (net236 ) ); | |
5503 | n2_core_pll_flop_reset_new_cust x34 ( | |
5504 | .vdd_reg (vdd_reg ), | |
5505 | .reset_val_l (vdd_reg ), | |
5506 | .d (net171 ), | |
5507 | .reset (reset_d ), | |
5508 | .clk (div_ck_i ), | |
5509 | .q_l (net236 ), | |
5510 | .q (nip5 ) ); | |
5511 | //terminator i55 ( | |
5512 | // .TERM (net235 ) ); | |
5513 | //terminator i56 ( | |
5514 | // .TERM (net162 ) ); | |
5515 | n2_core_pll_flop_reset_new_cust x36 ( | |
5516 | .vdd_reg (vdd_reg ), | |
5517 | .reset_val_l (vdd_reg ), | |
5518 | .d (f1d ), | |
5519 | .reset (reset_d ), | |
5520 | .clk (vco_ckd ), | |
5521 | .q_l (zero_1 ), | |
5522 | .q (f1q ) ); | |
5523 | //terminator i57 ( | |
5524 | // .TERM (net198 ) ); | |
5525 | n2_core_pll_flop_reset_new_cust x37 ( | |
5526 | .vdd_reg (vdd_reg ), | |
5527 | .reset_val_l (vdd_reg ), | |
5528 | .d (f2d ), | |
5529 | .reset (reset_d ), | |
5530 | .clk (vco_ckd ), | |
5531 | .q_l (zero_2 ), | |
5532 | .q (f2q ) ); | |
5533 | //terminator i58 ( | |
5534 | // .TERM (net186 ) ); | |
5535 | n2_core_pll_flop_reset_new_cust x38 ( | |
5536 | .vdd_reg (vdd_reg ), | |
5537 | .reset_val_l (vdd_reg ), | |
5538 | .d (f3d ), | |
5539 | .reset (reset_d ), | |
5540 | .clk (vco_ckd ), | |
5541 | .q_l (zero_3 ), | |
5542 | .q (f3q ) ); | |
5543 | //terminator i59 ( | |
5544 | // .TERM (net201 ) ); | |
5545 | n2_core_pll_flop_reset_new_cust x39 ( | |
5546 | .vdd_reg (vdd_reg ), | |
5547 | .reset_val_l (vdd_reg ), | |
5548 | .d (f4d ), | |
5549 | .reset (reset_d ), | |
5550 | .clk (vco_ckd ), | |
5551 | .q_l (zero_4 ), | |
5552 | .q (f4q ) ); | |
5553 | //terminator i60 ( | |
5554 | // .TERM (f3q ) ); | |
5555 | n2_core_pll_tpm_zd1_cust x40 ( | |
5556 | .vdd_reg (vdd_reg ), | |
5557 | .zero1 (sel ), | |
5558 | .zero1_b (sel_b ), | |
5559 | .q4b (zero_4 ), | |
5560 | .q0b (zero_0 ), | |
5561 | .q1b (zero_1 ), | |
5562 | .q2b (zero_2 ), | |
5563 | .q3b (zero_3 ), | |
5564 | .q5b (zero_5 ) ); | |
5565 | //terminator i61 ( | |
5566 | // .TERM (net0506 ) ); | |
5567 | n2_core_pll_inv_8x_cust x41 ( | |
5568 | .vdd_reg (vdd_reg ), | |
5569 | .out (net252 ), | |
5570 | .in (vco_ck ) ); | |
5571 | //terminator i62 ( | |
5572 | // .TERM (net0505 ) ); | |
5573 | n2_core_pll_flop_reset_new_cust x42 ( | |
5574 | .vdd_reg (vdd_reg ), | |
5575 | .reset_val_l (vdd_reg ), | |
5576 | .d (f5d ), | |
5577 | .reset (reset_d ), | |
5578 | .clk (vco_ckd ), | |
5579 | .q_l (zero_5 ), | |
5580 | .q (f5q ) ); | |
5581 | //terminator i63 ( | |
5582 | // .TERM (net0504 ) ); | |
5583 | n2_core_pll_flop_reset_new_cust x43 ( | |
5584 | .vdd_reg (vdd_reg ), | |
5585 | .reset_val_l (vss ), | |
5586 | .d (sel ), | |
5587 | .reset (reset_d ), | |
5588 | .clk (vco_ckb ), | |
5589 | .q_l (r_gate ), | |
5590 | .q (net0248 ) ); | |
5591 | //terminator i64 ( | |
5592 | // .TERM (net0503 ) ); | |
5593 | n2_core_pll_flop_reset_new_cust x44 ( | |
5594 | .vdd_reg (vdd_reg ), | |
5595 | .reset_val_l (vdd_reg ), | |
5596 | .d (f0d ), | |
5597 | .reset (reset_d ), | |
5598 | .clk (vco_ckd ), | |
5599 | .q_l (zero_0 ), | |
5600 | .q (f0q ) ); | |
5601 | //terminator i65 ( | |
5602 | // .TERM (net0502 ) ); | |
5603 | //terminator i66 ( | |
5604 | // .TERM (net0501 ) ); | |
5605 | n2_core_pll_tpm_mux_cust x47 ( | |
5606 | .opb (net0506 ), | |
5607 | .vdd_reg (vdd_reg ), | |
5608 | .op (f0d ), | |
5609 | .d0 (next0 ), | |
5610 | .d1 (nz_0 ), | |
5611 | .sel (sel ), | |
5612 | .sel_b (sel_b ) ); | |
5613 | //terminator i68 ( | |
5614 | // .TERM (net0362 ) ); | |
5615 | n2_core_pll_tpm_mux_cust x48 ( | |
5616 | .opb (net0505 ), | |
5617 | .vdd_reg (vdd_reg ), | |
5618 | .op (f1d ), | |
5619 | .d0 (next1 ), | |
5620 | .d1 (nz_1 ), | |
5621 | .sel (sel ), | |
5622 | .sel_b (sel_b ) ); | |
5623 | n2_core_pll_tpm_nzd_cust x49 ( | |
5624 | .vdd_reg (vdd_reg ), | |
5625 | .q2b (nzero_2 ), | |
5626 | .q4b (nzero_4 ), | |
5627 | .q3b (nzero_3 ), | |
5628 | .zero (net0362 ), | |
5629 | .q1b (nzero_1 ), | |
5630 | .q0b (nzero_0 ), | |
5631 | .q5b (nzero_5 ) ); | |
5632 | n2_core_pll_tpm_mux_cust x50 ( | |
5633 | .opb (net0504 ), | |
5634 | .vdd_reg (vdd_reg ), | |
5635 | .op (f2d ), | |
5636 | .d0 (next2 ), | |
5637 | .d1 (nz_2 ), | |
5638 | .sel (sel ), | |
5639 | .sel_b (sel_b ) ); | |
5640 | n2_core_pll_tpm_mux_cust x51 ( | |
5641 | .opb (net0503 ), | |
5642 | .vdd_reg (vdd_reg ), | |
5643 | .op (f3d ), | |
5644 | .d0 (next3 ), | |
5645 | .d1 (nz_3 ), | |
5646 | .sel (sel ), | |
5647 | .sel_b (sel_b ) ); | |
5648 | n2_core_pll_tpm_mux_cust x52 ( | |
5649 | .opb (net0502 ), | |
5650 | .vdd_reg (vdd_reg ), | |
5651 | .op (f4d ), | |
5652 | .d0 (next4 ), | |
5653 | .d1 (nz_4 ), | |
5654 | .sel (sel ), | |
5655 | .sel_b (sel_b ) ); | |
5656 | n2_core_pll_tpm_mux_cust x53 ( | |
5657 | .opb (net0501 ), | |
5658 | .vdd_reg (vdd_reg ), | |
5659 | .op (f5d ), | |
5660 | .d0 (next5 ), | |
5661 | .d1 (nz_5 ), | |
5662 | .sel (sel ), | |
5663 | .sel_b (sel_b ) ); | |
5664 | n2_core_pll_inv_4x_cust x1 ( | |
5665 | .vdd_reg (vdd_reg ), | |
5666 | .out (vco_ckb ), | |
5667 | .in (vco_ckd ) ); | |
5668 | endmodule | |
5669 | ||
5670 | ||
5671 | // ========================================================================== | |
5672 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_inv_1x_cust/rtl/n2_core_pll_inv_1x_cust.v | |
5673 | // ========================================================================== | |
5674 | // mh157021: instance #6 (n2_core_pll_inv_1x_cust) | |
5675 | // | |
5676 | // Last Modified: Friday Aug 26,2005 at 03:20:30 PM PDT | |
5677 | // | |
5678 | ||
5679 | module n2_core_pll_inv_1x_cust(vdd_reg ,out ,in ); | |
5680 | output out ; | |
5681 | input vdd_reg ; | |
5682 | input in ; | |
5683 | wire vss = 1'b0; | |
5684 | ||
5685 | assign out = ~in; | |
5686 | ||
5687 | endmodule | |
5688 | ||
5689 | // ========================================================================== | |
5690 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm3_sync_cust/rtl/n2_core_pll_tpm3_sync_cust.v | |
5691 | // ========================================================================== | |
5692 | /* | |
5693 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_tpm3_sync_cust/schematic/sch.cdb | |
5694 | Last Modified: Saturday Dec 10,2005 at 07:49:42 PM PST | |
5695 | By: ky82615 | |
5696 | */ | |
5697 | module n2_core_pll_tpm3_sync_cust(dri1_clk ,dft_rst_l ,dc_clk ,d4int_out | |
5698 | ,ccu_serdes_dtm ,arst_l ,arst ,vco_clk ,pll1_clk ,arst_d_l ,a , | |
5699 | rst_l ,rst ,volb ); | |
5700 | output [0:0] rst_l ; | |
5701 | output [1:1] rst ; | |
5702 | input [2:2] a ; | |
5703 | output dc_clk ; | |
5704 | output d4int_out ; | |
5705 | output arst ; | |
5706 | output vco_clk ; | |
5707 | output arst_d_l ; | |
5708 | input dri1_clk ; | |
5709 | input dft_rst_l ; | |
5710 | input ccu_serdes_dtm ; | |
5711 | input arst_l ; | |
5712 | input pll1_clk ; | |
5713 | input volb ; | |
5714 | supply1 vdd ; | |
5715 | supply0 vss ; | |
5716 | ||
5717 | wire [1:1] rstpa ; | |
5718 | wire [1:0] rstp_l ; | |
5719 | wire [1:1] rstpb ; | |
5720 | wire [1:0] rstp ; | |
5721 | wire [1:0] rstp1 ; | |
5722 | wire [1:0] net127 ; | |
5723 | wire net77 ; | |
5724 | wire net110 ; | |
5725 | wire net79 ; | |
5726 | wire net112 ; | |
5727 | wire net115 ; | |
5728 | wire net116 ; | |
5729 | wire net81 ; | |
5730 | wire net120 ; | |
5731 | wire vco_clk_d ; | |
5732 | wire net63 ; | |
5733 | wire vco_out ; | |
5734 | wire net69 ; | |
5735 | ||
5736 | ||
5737 | assign vco_out = ~volb; | |
5738 | assign dc_clk = ~vco_out; | |
5739 | assign vco_clk = ~dc_clk; | |
5740 | ||
5741 | n2_core_pll_inv1_16x_cust x2 ( | |
5742 | .vdd_reg (vdd ), | |
5743 | .out (rstpa[1] ), | |
5744 | .in (rstp_l[1] ) ); | |
5745 | //terminator ix1_0_ ( | |
5746 | // .TERM (rstp[0] ) ); | |
5747 | n2_core_pll_flop_reset2_cust x5_1_ ( | |
5748 | .d (rstp1[0] ), | |
5749 | .clk (vco_clk_d ), | |
5750 | .q_l (net127[0] ), | |
5751 | .q (rstp1[1] ) ); | |
5752 | n2_core_pll_inv1_16x_cust x8 ( | |
5753 | .vdd_reg (vdd ), | |
5754 | .out (arst ), | |
5755 | .in (arst_l ) ); | |
5756 | cl_u1_nand2_8x x9 ( | |
5757 | .out (rst[1] ), | |
5758 | .in1 (ccu_serdes_dtm ), | |
5759 | .in0 (net63 ) ); | |
5760 | //nmos_lvt mnout ( | |
5761 | // .S (vss ), | |
5762 | // .G (volb ), | |
5763 | // .D (vco_out ) ); | |
5764 | //nmos mi3 (vco_clk ,vss ,dc_clk ); | |
5765 | //terminator ixa_0_ ( | |
5766 | // .TERM (net127[1] ) ); | |
5767 | //terminator i3 ( | |
5768 | // .TERM (net81 ) ); | |
5769 | //terminator i4 ( | |
5770 | // .TERM (net112 ) ); | |
5771 | n2_core_pll_fse2diff_out_cust x10 ( | |
5772 | .vdd_reg (vdd ), | |
5773 | .in (vco_clk ), | |
5774 | .out_l (net81 ), | |
5775 | .out (vco_clk_d ) ); | |
5776 | cl_u1_inv_4x x11 ( | |
5777 | .out (net77 ), | |
5778 | .in (net69 ) ); | |
5779 | n2_core_pll_fse2diff_out_cust x12 ( | |
5780 | .vdd_reg (vdd ), | |
5781 | .in (rstpa[1] ), | |
5782 | .out_l (net112 ), | |
5783 | .out (rstpb[1] ) ); | |
5784 | n2_core_pll_inv1_16x_cust x14 ( | |
5785 | .vdd_reg (vdd ), | |
5786 | .out (arst_d_l ), | |
5787 | .in (arst ) ); | |
5788 | //terminator ixa_1_ ( | |
5789 | // .TERM (net127[0] ) ); | |
5790 | cl_u1_inv_4x x15 ( | |
5791 | .out (net79 ), | |
5792 | .in (a[2] ) ); | |
5793 | cl_u1_inv_2x x16 ( | |
5794 | .out (net63 ), | |
5795 | .in (rstp[1] ) ); | |
5796 | n2_core_pll_flop_reset1_cust x17 ( | |
5797 | .reset_val_l (vdd ), | |
5798 | .d (net116 ), | |
5799 | .reset (rst[1] ), | |
5800 | .clk (dri1_clk ), | |
5801 | .q_l (net120 ), | |
5802 | .q (net110 ) ); | |
5803 | n2_core_pll_flop_reset2_cust xb_0_ ( | |
5804 | .d (dft_rst_l ), | |
5805 | .clk (pll1_clk ), | |
5806 | .q_l (rstp[0] ), | |
5807 | .q (rstp_l[0] ) ); | |
5808 | n2_core_pll_inv1_16x_cust x22 ( | |
5809 | .vdd_reg (vdd ), | |
5810 | .out (rst_l[0] ), | |
5811 | .in (net77 ) ); | |
5812 | n2_core_pll_flop_reset2_cust xb_1_ ( | |
5813 | .d (rstp_l[0] ), | |
5814 | .clk (vco_clk ), | |
5815 | .q_l (rstp[1] ), | |
5816 | .q (rstp_l[1] ) ); | |
5817 | n2_core_pll_tpm_mux_cust x37 ( | |
5818 | .opb (net69 ), | |
5819 | .vdd_reg (vdd ), | |
5820 | .op (net115 ), | |
5821 | .d0 (rstp1[1] ), | |
5822 | .d1 (rstp1[0] ), | |
5823 | .sel (a[2] ), | |
5824 | .sel_b (net79 ) ); | |
5825 | //pfet_lvt mpout ( | |
5826 | // .G (volb ), | |
5827 | // .S (vco_out ), | |
5828 | // .B (vdd ), | |
5829 | // .D (vdd ) ); | |
5830 | //pfet m0 ( | |
5831 | // .G (dc_clk ), | |
5832 | // .S (vdd ), | |
5833 | // .B (vdd ), | |
5834 | // .D (vco_clk ) ); | |
5835 | //nmos m1 (dc_clk ,vss ,vco_out ); | |
5836 | //pfet m2 ( | |
5837 | // .G (vco_out ), | |
5838 | // .S (vdd ), | |
5839 | // .B (vdd ), | |
5840 | // .D (dc_clk ) ); | |
5841 | n2_core_pll_flop_reset2_cust x5_0_ ( | |
5842 | .d (rstpb[1] ), | |
5843 | .clk (vco_clk_d ), | |
5844 | .q_l (net127[1] ), | |
5845 | .q (rstp1[0] ) ); | |
5846 | //terminator i10 ( | |
5847 | // .TERM (net115 ) ); | |
5848 | cl_u1_inv_8x x0 ( | |
5849 | .out (d4int_out ), | |
5850 | .in (net110 ) ); | |
5851 | cl_u1_buf_1x x1 ( | |
5852 | .out (net116 ), | |
5853 | .in (net120 ) ); | |
5854 | endmodule | |
5855 | ||
5856 | // ========================================================================== | |
5857 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_frac_cust/rtl/n2_core_pll_d4_frac_cust.v | |
5858 | // ========================================================================== | |
5859 | /* | |
5860 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_d4_frac_cust/schematic/sch.cdb | |
5861 | Last Modified: Saturday Dec 10,2005 at 04:26:42 PM PST | |
5862 | By: ky82615 | |
5863 | */ | |
5864 | module n2_core_pll_d4_frac_cust(dft_rst_l ,vco_clk ,a ,out_clk ); | |
5865 | input [4:0] a ; | |
5866 | output out_clk ; | |
5867 | input dft_rst_l ; | |
5868 | input vco_clk ; | |
5869 | supply1 vdd ; | |
5870 | ||
5871 | wire bs_pclk_0 ; | |
5872 | wire bs_rstps_0 ; | |
5873 | wire bs_pi_clk_4 ; | |
5874 | wire bs_cac_l_0 ; | |
5875 | wire bs_csel_l_1 ; | |
5876 | wire bs_ph_clk_4 ; | |
5877 | wire bs_csel_1 ; | |
5878 | wire bs_csel_l_3 ; | |
5879 | wire bs_pclk_4 ; | |
5880 | wire bs_rstps_4 ; | |
5881 | wire bs_csel_3 ; | |
5882 | wire bs_pi_clk_0 ; | |
5883 | wire bs_cac_l_4 ; | |
5884 | wire bs_ph_clk_0 ; | |
5885 | ||
5886 | ||
5887 | n2_core_pll_d4_sync_cust x3 ( | |
5888 | .dft_rst_l (dft_rst_l ), | |
5889 | .bs_rstps_4 (bs_rstps_4 ), | |
5890 | .bs_rstps_0 (bs_rstps_0 ), | |
5891 | .bs_pclk_4 (bs_pclk_4 ), | |
5892 | .bs_pclk_0 (bs_pclk_0 ) ); | |
5893 | //n2_core_pll_fse2diff_out_cust x1_1_ ( | |
5894 | // .vdd_reg (vdd ), | |
5895 | // .in (vco_clk ), | |
5896 | // .out_l (bs_ph_clk_4 ), | |
5897 | // .out (bs_ph_clk_0 ) ); | |
5898 | n2_core_pll_d4_ctl_cust x2_0_ ( | |
5899 | .csel_l ({bs_csel_l_1 } ), | |
5900 | .csel ({bs_csel_1 } ), | |
5901 | .a ({a } ), | |
5902 | .cac_l (bs_cac_l_0 ), | |
5903 | .pclk (bs_pclk_0 ), | |
5904 | .out_clk (bs_pi_clk_0 ), | |
5905 | .eq (bs_csel_l_1 ), | |
5906 | .in_clk (bs_ph_clk_0 ), | |
5907 | .rstps (bs_rstps_0 ) ); | |
5908 | //terminator ix6_0_ ( | |
5909 | // .TERM (\csel[1] ) ); | |
5910 | n2_core_pll_d4_ctl_cust x2_1_ ( | |
5911 | .csel_l ({bs_csel_l_3 } ), | |
5912 | .csel ({bs_csel_3 } ), | |
5913 | .a ({a } ), | |
5914 | .cac_l (bs_cac_l_4 ), | |
5915 | .pclk (bs_pclk_4 ), | |
5916 | .out_clk (bs_pi_clk_4 ), | |
5917 | .eq (bs_csel_3 ), | |
5918 | .in_clk (bs_ph_clk_4 ), | |
5919 | .rstps (bs_rstps_4 ) ); | |
5920 | //terminator ix7_0_ ( | |
5921 | // .TERM (\csel_l[3] ) ); | |
5922 | //terminator ix8_0_ ( | |
5923 | // .TERM (\cac_l[0] ) ); | |
5924 | //terminator ix8_1_ ( | |
5925 | // .TERM (\cac_l[4] ) ); | |
5926 | n2_core_pll_fse2diff_out_cust x1_0_ ( | |
5927 | .vdd_reg (vdd ), | |
5928 | .in (vco_clk ), | |
5929 | .out_l (bs_ph_clk_4 ), | |
5930 | .out (bs_ph_clk_0 ) ); | |
5931 | n2_core_pll_d4_mux_cust x0 ( | |
5932 | .rstps ({bs_rstps_0 } ), | |
5933 | .out_clk (out_clk ), | |
5934 | .bs_pi_clk_4 (bs_pi_clk_4 ), | |
5935 | .bs_pi_clk_0 (bs_pi_clk_0 ) ); | |
5936 | endmodule | |
5937 | ||
5938 | ||
5939 | // ========================================================================== | |
5940 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_ckmux_cust/rtl/n2_core_pll_ckmux_cust.v | |
5941 | // ========================================================================== | |
5942 | /* | |
5943 | File: /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_ckmux_cust/schematic/sch.cdb | |
5944 | Last Modified: Friday Dec 9,2005 at 04:20:36 PM PST | |
5945 | By: ky82615 | |
5946 | */ | |
5947 | ||
5948 | `timescale 1 ps/ 1 ps | |
5949 | ||
5950 | module n2_core_pll_ckmux_cust(pll_sdel ,ckt_drv_int ,cktree_drv_l , | |
5951 | ext_clk ,dft_rst_a_l ,dft_rst_l ,bypass_pll_clk ,psel1 ,psel0 , | |
5952 | stretch_a ,async_reset ,cktree_drv ,pll1_clk ,pll_sel ,bypass_clk | |
5953 | ); | |
5954 | input [1:0] pll_sdel ; | |
5955 | input [1:0] pll_sel ; | |
5956 | output ckt_drv_int ; | |
5957 | output cktree_drv_l ; | |
5958 | output dft_rst_l ; | |
5959 | output psel1 ; | |
5960 | output psel0 ; | |
5961 | output cktree_drv ; | |
5962 | input ext_clk ; | |
5963 | input dft_rst_a_l ; | |
5964 | input bypass_pll_clk ; | |
5965 | input stretch_a ; | |
5966 | input async_reset ; | |
5967 | input pll1_clk ; | |
5968 | input bypass_clk ; | |
5969 | supply0 vss ; | |
5970 | ||
5971 | wire sel_n0 ; | |
5972 | wire byp_pll_clk_l ; | |
5973 | wire sel_n1 ; | |
5974 | wire net93 ; | |
5975 | wire pll_sel0_l ; | |
5976 | wire byp_pll_clk ; | |
5977 | wire s0_l ; | |
5978 | wire sel0 ; | |
5979 | wire sel1 ; | |
5980 | wire s1_l ; | |
5981 | wire sel2 ; | |
5982 | wire sel3 ; | |
5983 | wire net069 ; | |
5984 | wire psel0_l ; | |
5985 | wire psel1_l ; | |
5986 | wire d1_clk ; | |
5987 | wire net070 ; | |
5988 | wire net071 ; | |
5989 | wire sel_n1_l ; | |
5990 | wire s0 ; | |
5991 | wire s1 ; | |
5992 | wire sel_n0_l ; | |
5993 | wire sel2_l ; | |
5994 | wire sel3_l ; | |
5995 | wire net64 ; | |
5996 | ||
5997 | wire net069_orig; | |
5998 | wire net070_orig; | |
5999 | ||
6000 | assign #200 net069 = net069_orig; | |
6001 | assign #200 net070 = net070_orig; | |
6002 | ||
6003 | cl_u1_nand2_4x x2 ( | |
6004 | .out (s1_l ), | |
6005 | .in1 (sel_n1_l ), | |
6006 | .in0 (sel_n0 ) ); | |
6007 | cl_u1_inv_16x x4 ( | |
6008 | .out (sel3 ), | |
6009 | .in (sel3_l ) ); | |
6010 | cl_u1_inv_4x x5 ( | |
6011 | .out (s1 ), | |
6012 | .in (s1_l ) ); | |
6013 | cl_u1_inv_8x x6 ( | |
6014 | .out (byp_pll_clk_l ), | |
6015 | .in (bypass_pll_clk ) ); | |
6016 | cl_u1_inv_1x x7 ( | |
6017 | .out (pll_sel0_l ), | |
6018 | .in (pll_sel[0] ) ); | |
6019 | cl_u1_nand2_4x x8 ( | |
6020 | .out (sel2_l ), | |
6021 | .in1 (pll_sel[1] ), | |
6022 | .in0 (pll_sel0_l ) ); | |
6023 | n2_core_pll_flopderst_16x_cust xi72 ( | |
6024 | .q_l (net64 ), | |
6025 | .reset_val (byp_pll_clk_l ), | |
6026 | .d (s0 ), | |
6027 | .q (sel0 ), | |
6028 | .reset (async_reset ), | |
6029 | .clk (d1_clk ), | |
6030 | .ena (net071 ) ); | |
6031 | n2_core_pll_flopderst_16x_cust xi74 ( | |
6032 | .q_l (net93 ), | |
6033 | .reset_val (vss ), | |
6034 | .d (s1 ), | |
6035 | .q (sel1 ), | |
6036 | .reset (async_reset ), | |
6037 | .clk (d1_clk ), | |
6038 | .ena (net071 ) ); | |
6039 | n2_core_pll_flopderst_16x_cust xi75 ( | |
6040 | .q_l (sel_n1_l ), | |
6041 | .reset_val (byp_pll_clk ), | |
6042 | .d (net069 ), | |
6043 | .q (sel_n1 ), | |
6044 | .reset (async_reset ), | |
6045 | .clk (d1_clk ), | |
6046 | .ena (net071 ) ); | |
6047 | n2_core_pll_flopderst_16x_cust xi76 ( | |
6048 | .q_l (sel_n0_l ), | |
6049 | .reset_val (byp_pll_clk ), | |
6050 | .d (net070 ), | |
6051 | .q (sel_n0 ), | |
6052 | .reset (async_reset ), | |
6053 | .clk (d1_clk ), | |
6054 | .ena (net071 ) ); | |
6055 | cl_u1_nand2_4x x10 ( | |
6056 | .out (sel3_l ), | |
6057 | .in1 (pll_sel[1] ), | |
6058 | .in0 (pll_sel[0] ) ); | |
6059 | cl_u1_inv_16x x11 ( | |
6060 | .out (sel2 ), | |
6061 | .in (sel2_l ) ); | |
6062 | cl_u1_inv_8x x16 ( | |
6063 | .out (psel1 ), | |
6064 | .in (psel1_l ) ); | |
6065 | cl_u1_inv_2x x22 ( | |
6066 | .out (psel1_l ), | |
6067 | .in (sel1 ) ); | |
6068 | cl_u1_inv_2x x23 ( | |
6069 | .out (psel0_l ), | |
6070 | .in (sel0 ) ); | |
6071 | cl_u1_inv_8x x24 ( | |
6072 | .out (psel0 ), | |
6073 | .in (psel0_l ) ); | |
6074 | cl_u1_inv_8x x26 ( | |
6075 | .out (byp_pll_clk ), | |
6076 | .in (byp_pll_clk_l ) ); | |
6077 | cl_u1_inv_4x x27 ( | |
6078 | .out (s0 ), | |
6079 | .in (s0_l ) ); | |
6080 | n2_core_pll_ckmux_mxdel_diffout_cust xmxdel ( | |
6081 | .pll_sdel ({pll_sdel } ), | |
6082 | .ckt_drv_int (ckt_drv_int ), | |
6083 | .cktree_drv (cktree_drv ), | |
6084 | .cktree_drv_l (cktree_drv_l ), | |
6085 | .pll1_clk (pll1_clk ), | |
6086 | .sel1 (sel1 ), | |
6087 | .pll2_clk (ext_clk ), | |
6088 | .bypass_clk (bypass_clk ), | |
6089 | .sel3 (sel3 ), | |
6090 | .d1_clk (d1_clk ), | |
6091 | .sel0 (sel0 ), | |
6092 | .sel2 (sel2 ) ); | |
6093 | //terminator ix21 ( | |
6094 | // .TERM (net93 ) ); | |
6095 | //terminator ix25 ( | |
6096 | // .TERM (net64 ) ); | |
6097 | //terminator ix28 ( | |
6098 | // .TERM (sel_n1 ) ); | |
6099 | n2_core_pll_clkmux_sync_cust x0 ( | |
6100 | .bypass_pll_clk (bypass_pll_clk ), | |
6101 | .pll_clk (pll1_clk ), | |
6102 | .arst (async_reset ), | |
6103 | .d1 (pll_sel[0] ), | |
6104 | .d2 (pll_sel[1] ), | |
6105 | .d1_sync (net070_orig ), | |
6106 | .d2_sync (net069_orig ), | |
6107 | .d0_sync (net071), | |
6108 | .d0 (stretch_a ), | |
6109 | .d3_sync (dft_rst_l ), | |
6110 | .d3 (dft_rst_a_l ) ); | |
6111 | cl_u1_nand2_1x x1 ( | |
6112 | .out (s0_l ), | |
6113 | .in1 (sel_n1_l ), | |
6114 | .in0 (sel_n0_l ) ); | |
6115 | ||
6116 | ||
6117 | endmodule | |
6118 | ||
6119 | ||
6120 | // ========================================================================== | |
6121 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_buf_2x_cust/rtl/n2_core_pll_buf_2x_cust.v | |
6122 | // ========================================================================== | |
6123 | // mh157021: lower level module definition (n2_core_pll_buf_2x_cust) | |
6124 | // | |
6125 | // Last Modified: Friday Aug 26,2005 at 03:19:04 PM PDT | |
6126 | // | |
6127 | ||
6128 | module n2_core_pll_buf_2x_cust(vdd_reg ,out ,in ); | |
6129 | output out ; | |
6130 | input vdd_reg ; | |
6131 | input in ; | |
6132 | wire vss = 1'b0; | |
6133 | ||
6134 | assign out = in; | |
6135 | ||
6136 | endmodule | |
6137 | ||
6138 | // ========================================================================== | |
6139 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_ckmux_mxdel_diffout_cust/rtl/mux4k.v | |
6140 | // ========================================================================== | |
6141 | module mux4k ( dout, in0, in1, in2, in3, | |
6142 | sel0, sel1, sel2, sel3, muxtst ); | |
6143 | ||
6144 | parameter SIZE = 1; | |
6145 | ||
6146 | output [SIZE-1:0] dout; | |
6147 | input [SIZE-1:0] in0; | |
6148 | input [SIZE-1:0] in1; | |
6149 | input [SIZE-1:0] in2; | |
6150 | input [SIZE-1:0] in3; | |
6151 | input sel0; | |
6152 | input sel1; | |
6153 | input sel2; | |
6154 | input sel3; | |
6155 | input muxtst; | |
6156 | ||
6157 | wire [4:0] sel = { muxtst, sel3, sel2, sel1, sel0 }; | |
6158 | ||
6159 | reg [SIZE-1:0] dout; | |
6160 | always @ ( sel or in0 or in1 or in2 or in3 ) | |
6161 | casex ( sel ) | |
6162 | 5'bx0001: dout = in0; | |
6163 | 5'bx0010: dout = in1; | |
6164 | 5'bx0100: dout = in2; | |
6165 | 5'bx1000: dout = in3; | |
6166 | 5'b00000: dout = { SIZE { 1'bx } }; | |
6167 | ||
6168 | default: | |
6169 | dout = { SIZE { 1'bx } }; | |
6170 | endcase // case( sel ) | |
6171 | ||
6172 | ||
6173 | endmodule // mux4k | |
6174 | ||
6175 | ||
6176 | ||
6177 | module n2_core_pll_byp_enb_cust(sel1 ,in1 ,out1 ,out0 ,in0 ,sel0 ); | |
6178 | output out1 ; | |
6179 | output out0 ; | |
6180 | input sel1 ; | |
6181 | input in1 ; | |
6182 | input in0 ; | |
6183 | input sel0 ; | |
6184 | supply1 vdd ; | |
6185 | ||
6186 | wire net11 ; | |
6187 | wire net8 ; | |
6188 | ||
6189 | ||
6190 | n2_core_pll_inv_8x_cust x4 ( | |
6191 | .vdd_reg (vdd ), | |
6192 | .out (out1 ), | |
6193 | .in (net8 ) ); | |
6194 | n2_core_pll_nand2_2x_cust x8 ( | |
6195 | .vdd_reg (vdd ), | |
6196 | .out (net11 ), | |
6197 | .in1 (sel0 ), | |
6198 | .in0 (in0 ) ); | |
6199 | n2_core_pll_nand2_2x_cust x10 ( | |
6200 | .vdd_reg (vdd ), | |
6201 | .out (net8 ), | |
6202 | .in1 (sel1 ), | |
6203 | .in0 (in1 ) ); | |
6204 | n2_core_pll_inv_8x_cust x11 ( | |
6205 | .vdd_reg (vdd ), | |
6206 | .out (out0 ), | |
6207 | .in (net11 ) ); | |
6208 | endmodule | |
6209 | ||
6210 | ||
6211 | ||
6212 | module n2_core_pll_pecl_enb_cust(in ,out ,enb1 ,enb0 ); | |
6213 | output out ; | |
6214 | input in ; | |
6215 | input enb1 ; | |
6216 | input enb0 ; | |
6217 | supply1 vdd ; | |
6218 | ||
6219 | wire net10 ; | |
6220 | wire net12 ; | |
6221 | wire net8 ; | |
6222 | ||
6223 | ||
6224 | n2_core_pll_nand2_4x_cust x12 ( | |
6225 | .vdd_reg (vdd ), | |
6226 | .out (net8 ), | |
6227 | .in1 (net10 ), | |
6228 | .in0 (in ) ); | |
6229 | n2_core_pll_inv_16x_cust x22 ( | |
6230 | .vdd_reg (vdd ), | |
6231 | .out (out ), | |
6232 | .in (net8 ) ); | |
6233 | cl_u1_nor2_2x x0 ( | |
6234 | .out (net12 ), | |
6235 | .in1 (enb0 ), | |
6236 | .in0 (enb1 ) ); | |
6237 | cl_u1_inv_2x x1 ( | |
6238 | .out (net10 ), | |
6239 | .in (net12 ) ); | |
6240 | endmodule | |
6241 | ||
6242 | ||
6243 | module n2_core_pll_nand2_4x_cust(vdd_reg ,out ,in1 ,in0 ); | |
6244 | output out ; | |
6245 | input vdd_reg ; | |
6246 | input in1 ; | |
6247 | input in0 ; | |
6248 | wire vss = 1'b0; | |
6249 | ||
6250 | assign out = ~(in0 & in1); | |
6251 | ||
6252 | endmodule | |
6253 | ||
6254 | module n2_core_pll_tpm3_all_cust(pll_stretch_a ,ccu_serdes_dtm , | |
6255 | dr_ext_clk ,dc_clk ,pll_clk_out_l ,pll_div3 ,pll_sdel ,pll_sel_a , | |
6256 | pll_bypass_clk_en ,pll_arst_l ,dr_clk_out ,pll_bypass_clk , | |
6257 | pll_clk_out ,dr_clk_out_l ,dr_stretch_a ,pll_testmode ,dr_sdel , | |
6258 | vco8_clk ,dr_sel_a ,volb ,vco2_clk ,pll_ext_clk ,pll_div4 , | |
6259 | dft_rst_a_l ); | |
6260 | input [5:0] pll_div3 ; | |
6261 | input [1:0] pll_sdel ; | |
6262 | input [1:0] pll_sel_a ; | |
6263 | input [1:0] dr_sdel ; | |
6264 | input [1:0] dr_sel_a ; | |
6265 | input [6:0] pll_div4 ; | |
6266 | output dc_clk ; | |
6267 | output pll_clk_out_l ; | |
6268 | output dr_clk_out ; | |
6269 | output pll_clk_out ; | |
6270 | output dr_clk_out_l ; | |
6271 | output vco8_clk ; | |
6272 | output vco2_clk ; | |
6273 | input pll_stretch_a ; | |
6274 | input ccu_serdes_dtm ; | |
6275 | input dr_ext_clk ; | |
6276 | input pll_bypass_clk_en ; | |
6277 | input pll_arst_l ; | |
6278 | input pll_bypass_clk ; | |
6279 | input dr_stretch_a ; | |
6280 | input pll_testmode ; | |
6281 | input volb ; | |
6282 | input pll_ext_clk ; | |
6283 | input dft_rst_a_l ; | |
6284 | supply1 vdd ; | |
6285 | supply0 vss ; | |
6286 | ||
6287 | wire [1:0] net077 ; | |
6288 | wire [5:0] net080 ; | |
6289 | wire [1:1] rst ; | |
6290 | wire [0:0] rst_l ; | |
6291 | wire net088 ; | |
6292 | wire net0100 ; | |
6293 | wire net0103 ; | |
6294 | wire net0104 ; | |
6295 | wire net095 ; | |
6296 | wire arst_d_l ; | |
6297 | wire net096 ; | |
6298 | wire net097 ; | |
6299 | wire net098 ; | |
6300 | wire pll1_clk ; | |
6301 | wire dr_byp_clk ; | |
6302 | wire net0153 ; | |
6303 | wire net042 ; | |
6304 | wire dr1_clk ; | |
6305 | wire d4int_out ; | |
6306 | wire net069 ; | |
6307 | wire vco_clk ; | |
6308 | wire pll_byp_clk ; | |
6309 | ||
6310 | ||
6311 | n2_core_pll_ckmux_cust x2 ( | |
6312 | .pll_sdel ({pll_sdel } ), | |
6313 | .pll_sel ({pll_sel_a } ), | |
6314 | .ckt_drv_int (net0104 ), | |
6315 | .cktree_drv_l (pll_clk_out_l ), | |
6316 | .ext_clk (pll_ext_clk ), | |
6317 | .dft_rst_a_l (vdd ), | |
6318 | .dft_rst_l (net0153 ), | |
6319 | .bypass_pll_clk (pll_bypass_clk_en ), | |
6320 | .psel1 (net0103 ), | |
6321 | .psel0 (net096 ), | |
6322 | .stretch_a (pll_stretch_a ), | |
6323 | .async_reset (net095 ), | |
6324 | .cktree_drv (pll_clk_out ), | |
6325 | .pll1_clk (pll1_clk ), | |
6326 | .bypass_clk (pll_byp_clk ) ); | |
6327 | n2_core_pll_byp_enb_cust x3 ( | |
6328 | .sel1 (ccu_serdes_dtm ), | |
6329 | .in1 (pll_bypass_clk ), | |
6330 | .out1 (dr_byp_clk ), | |
6331 | .out0 (pll_byp_clk ), | |
6332 | .in0 (pll_bypass_clk ), | |
6333 | .sel0 (pll_bypass_clk_en ) ); | |
6334 | n2_core_pll_ckmux_cust x4 ( | |
6335 | .pll_sdel ({dr_sdel } ), | |
6336 | .pll_sel ({dr_sel_a } ), | |
6337 | .ckt_drv_int (net098 ), | |
6338 | .cktree_drv_l (dr_clk_out_l ), | |
6339 | .ext_clk (dr_ext_clk ), | |
6340 | .dft_rst_a_l (vdd ), | |
6341 | .dft_rst_l (net097 ), | |
6342 | .bypass_pll_clk (ccu_serdes_dtm ), | |
6343 | .psel1 (net0100 ), | |
6344 | .psel0 (net042 ), | |
6345 | .stretch_a (dr_stretch_a ), | |
6346 | .async_reset (net095 ), | |
6347 | .cktree_drv (dr_clk_out ), | |
6348 | .pll1_clk (dr1_clk ), | |
6349 | .bypass_clk (dr_byp_clk ) ); | |
6350 | n2_core_pll_div4_cust x5 ( | |
6351 | .clk (pll1_clk ), | |
6352 | .arst_l (pll_testmode ), | |
6353 | .clk_div_out (vco8_clk ) ); | |
6354 | n2_core_pll_inv_32x_cust x6 ( | |
6355 | .vdd_reg (vdd ), | |
6356 | .out (vco2_clk ), | |
6357 | .in (net069 ) ); | |
6358 | n2_core_pll_inv_16x_cust x7 ( | |
6359 | .vdd_reg (vdd ), | |
6360 | .out (net069 ), | |
6361 | .in (pll1_clk ) ); | |
6362 | n2_core_pll_tpm3_cust xd3 ( | |
6363 | .ip ({pll_div3 } ), | |
6364 | .op ({net080[0] ,net080[1] ,net080[2] ,net080[3] , | |
6365 | net080[4] ,net080[5] } ), | |
6366 | .reset (net095 ), | |
6367 | .vdd_reg (vdd ), | |
6368 | .sel (net088 ), | |
6369 | .div_ck_i (vdd ), | |
6370 | .pwr_rst (vdd ), | |
6371 | .div_ck (pll1_clk ), | |
6372 | .vco_ck (vco_clk ) ); | |
6373 | n2_core_pll_inv_1x_cust x11_0_ ( | |
6374 | .vdd_reg (vdd ), | |
6375 | .out (net077[1] ), | |
6376 | .in (pll_div4[5] ) ); | |
6377 | n2_core_pll_inv_1x_cust x11_1_ ( | |
6378 | .vdd_reg (vdd ), | |
6379 | .out (net077[0] ), | |
6380 | .in (pll_div4[6] ) ); | |
6381 | n2_core_pll_tpm3_sync_cust x0 ( | |
6382 | .a ({pll_div4[2] } ), | |
6383 | .rst_l ({rst_l[0] } ), | |
6384 | .rst ({rst[1] } ), | |
6385 | .dri1_clk (vss ), | |
6386 | .dft_rst_l (dft_rst_a_l ), | |
6387 | .dc_clk (dc_clk ), | |
6388 | .d4int_out (d4int_out ), | |
6389 | .ccu_serdes_dtm (vss ), | |
6390 | .arst_l (pll_arst_l ), | |
6391 | .arst (net095 ), | |
6392 | .vco_clk (vco_clk ), | |
6393 | .pll1_clk (pll1_clk ), | |
6394 | .arst_d_l (arst_d_l ), | |
6395 | .volb (volb ) ); | |
6396 | n2_core_pll_d4_frac_cust x1 ( | |
6397 | .a ({pll_div4[4:0] } ), | |
6398 | .dft_rst_l (rst_l[0] ), | |
6399 | .vco_clk (vco_clk ), | |
6400 | .out_clk (dr1_clk ) ); | |
6401 | endmodule | |
6402 | ||
6403 | ||
6404 | // ========================================================================== | |
6405 | // /import/n2-analog3/ky82615/n2cdmspp/libs/analog/n2_core_pll_cust_l/n2_core_pll_clkmux_delay/rtl/n2_core_pll_clkmux_delay.v | |
6406 | // ========================================================================== | |
6407 | // mh157021: lower level module definition (n2_core_pll_clkmux_delay) | |
6408 | // | |
6409 | // Last Modified: Friday Aug 26,2005 at 03:19:23 PM PDT | |
6410 | // | |
6411 | ||
6412 | `timescale 1 ps / 1 ps | |
6413 | ||
6414 | module n2_core_pll_clkmux_delay(pll_sdel ,mux_out ,d ); | |
6415 | input [1:0] pll_sdel ; | |
6416 | output mux_out ; | |
6417 | input d ; | |
6418 | supply1 vdd ; | |
6419 | wire vss = 1'b0; | |
6420 | ||
6421 | wire [3:0] sel; | |
6422 | ||
6423 | wire d0, d1, d2, d3; | |
6424 | ||
6425 | assign #40 d0 = d; | |
6426 | assign #40 d1 = d0; | |
6427 | assign #40 d2 = d1; | |
6428 | assign #40 d3 = d2; | |
6429 | ||
6430 | decode x0 ( | |
6431 | .a (pll_sdel[1:0]), | |
6432 | .d (sel[3:0]) ); | |
6433 | ||
6434 | ||
6435 | mux4 x1 ( | |
6436 | .muxtst (1'b0), | |
6437 | .sel0 (sel[0]), | |
6438 | .sel1 (sel[1]), | |
6439 | .sel2 (sel[2]), | |
6440 | .sel3 (sel[3]), | |
6441 | .in0 (d0), | |
6442 | .in1 (d1), | |
6443 | .in2 (d2), | |
6444 | .in3 (d3), | |
6445 | .dout (mux_out) ); | |
6446 | ||
6447 | ||
6448 | endmodule |