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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_a1.behV | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
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29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_a1_msffmin_fp_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
36 | // RFM 05-14-2004 | |
37 | // Level sensitive in SCAN_MODE | |
38 | // Edge triggered when not in SCAN_MODE | |
39 | ||
40 | ||
41 | parameter SIZE = 1; | |
42 | ||
43 | output q; | |
44 | output so; | |
45 | ||
46 | input d; | |
47 | input l1clk; | |
48 | input si; | |
49 | input siclk; | |
50 | input soclk; | |
51 | ||
52 | reg q; | |
53 | wire so; | |
54 | wire l1clk, siclk, soclk; | |
55 | ||
56 | `ifdef SCAN_MODE | |
57 | ||
58 | reg l1; | |
59 | `ifdef FAST_FLUSH | |
60 | always @(posedge l1clk or posedge siclk ) begin | |
61 | if (siclk) begin | |
62 | q <= 1'b0; //pseudo flush reset | |
63 | end else begin | |
64 | q <= d; | |
65 | end | |
66 | end | |
67 | `else | |
68 | always @(l1clk or siclk or soclk or d or si) | |
69 | begin | |
70 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
71 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
72 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
73 | ||
74 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
75 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
76 | end | |
77 | `endif | |
78 | `else | |
79 | wire si_unused; | |
80 | wire siclk_unused; | |
81 | wire soclk_unused; | |
82 | assign si_unused = si; | |
83 | assign siclk_unused = siclk; | |
84 | assign soclk_unused = soclk; | |
85 | ||
86 | ||
87 | `ifdef INITLATZERO | |
88 | initial q = 1'b0; | |
89 | `endif | |
90 | ||
91 | always @(posedge l1clk) | |
92 | begin | |
93 | if (!siclk && !soclk) q <= d; | |
94 | else q <= 1'bx; | |
95 | end | |
96 | `endif | |
97 | ||
98 | assign so = q; | |
99 | ||
100 | endmodule // dff | |
101 | ||
102 | ||
103 | ||
104 | ||
105 | module cl_a1_msffmin_fp_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
106 | // RFM 05-14-2004 | |
107 | // Level sensitive in SCAN_MODE | |
108 | // Edge triggered when not in SCAN_MODE | |
109 | ||
110 | ||
111 | parameter SIZE = 1; | |
112 | ||
113 | output q; | |
114 | output so; | |
115 | ||
116 | input d; | |
117 | input l1clk; | |
118 | input si; | |
119 | input siclk; | |
120 | input soclk; | |
121 | ||
122 | reg q; | |
123 | wire so; | |
124 | wire l1clk, siclk, soclk; | |
125 | ||
126 | `ifdef SCAN_MODE | |
127 | `ifdef FAST_FLUSH | |
128 | always @(posedge l1clk or posedge siclk ) begin | |
129 | if (siclk) begin | |
130 | q <= 1'b0; //pseudo flush reset | |
131 | end else begin | |
132 | q <= d; | |
133 | end | |
134 | end | |
135 | `else | |
136 | reg l1; | |
137 | ||
138 | always @(l1clk or siclk or soclk or d or si) | |
139 | begin | |
140 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
141 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
142 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
143 | ||
144 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
145 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
146 | end | |
147 | `endif | |
148 | `else | |
149 | wire si_unused; | |
150 | wire siclk_unused; | |
151 | wire soclk_unused; | |
152 | assign si_unused = si; | |
153 | assign siclk_unused = siclk; | |
154 | assign soclk_unused = soclk; | |
155 | ||
156 | ||
157 | `ifdef INITLATZERO | |
158 | initial q = 1'b0; | |
159 | `endif | |
160 | ||
161 | always @(posedge l1clk) | |
162 | begin | |
163 | if (!siclk && !soclk) q <= d; | |
164 | else q <= 1'bx; | |
165 | end | |
166 | `endif | |
167 | ||
168 | assign so = q; | |
169 | ||
170 | endmodule // dff | |
171 | module cl_a1_msffmin_fp_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
172 | // RFM 05-14-2004 | |
173 | // Level sensitive in SCAN_MODE | |
174 | // Edge triggered when not in SCAN_MODE | |
175 | ||
176 | ||
177 | parameter SIZE = 1; | |
178 | ||
179 | output q; | |
180 | output so; | |
181 | ||
182 | input d; | |
183 | input l1clk; | |
184 | input si; | |
185 | input siclk; | |
186 | input soclk; | |
187 | ||
188 | reg q; | |
189 | wire so; | |
190 | wire l1clk, siclk, soclk; | |
191 | ||
192 | `ifdef SCAN_MODE | |
193 | ||
194 | reg l1; | |
195 | `ifdef FAST_FLUSH | |
196 | always @(posedge l1clk or posedge siclk ) begin | |
197 | if (siclk) begin | |
198 | q <= 1'b0; //pseudo flush reset | |
199 | end else begin | |
200 | q <= d; | |
201 | end | |
202 | end | |
203 | `else | |
204 | always @(l1clk or siclk or soclk or d or si) | |
205 | begin | |
206 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
207 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
208 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
209 | ||
210 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
211 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
212 | end | |
213 | `endif | |
214 | `else | |
215 | wire si_unused; | |
216 | wire siclk_unused; | |
217 | wire soclk_unused; | |
218 | assign si_unused = si; | |
219 | assign siclk_unused = siclk; | |
220 | assign soclk_unused = soclk; | |
221 | ||
222 | ||
223 | `ifdef INITLATZERO | |
224 | initial q = 1'b0; | |
225 | `endif | |
226 | ||
227 | always @(posedge l1clk) | |
228 | begin | |
229 | if (!siclk && !soclk) q <= d; | |
230 | else q <= 1'bx; | |
231 | end | |
232 | `endif | |
233 | ||
234 | assign so = q; | |
235 | ||
236 | endmodule // dff | |
237 | module cl_a1_msffmin_fp_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
238 | // RFM 05-14-2004 | |
239 | // Level sensitive in SCAN_MODE | |
240 | // Edge triggered when not in SCAN_MODE | |
241 | ||
242 | ||
243 | parameter SIZE = 1; | |
244 | ||
245 | output q; | |
246 | output so; | |
247 | ||
248 | input d; | |
249 | input l1clk; | |
250 | input si; | |
251 | input siclk; | |
252 | input soclk; | |
253 | ||
254 | reg q; | |
255 | wire so; | |
256 | wire l1clk, siclk, soclk; | |
257 | ||
258 | `ifdef SCAN_MODE | |
259 | ||
260 | reg l1; | |
261 | `ifdef FAST_FLUSH | |
262 | always @(posedge l1clk or posedge siclk ) begin | |
263 | if (siclk) begin | |
264 | q <= 1'b0; //pseudo flush reset | |
265 | end else begin | |
266 | q <= d; | |
267 | end | |
268 | end | |
269 | `else | |
270 | always @(l1clk or siclk or soclk or d or si) | |
271 | begin | |
272 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
273 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
274 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
275 | ||
276 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
277 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
278 | end | |
279 | `endif | |
280 | `else | |
281 | wire si_unused; | |
282 | wire siclk_unused; | |
283 | wire soclk_unused; | |
284 | assign si_unused = si; | |
285 | assign siclk_unused = siclk; | |
286 | assign soclk_unused = soclk; | |
287 | ||
288 | ||
289 | `ifdef INITLATZERO | |
290 | initial q = 1'b0; | |
291 | `endif | |
292 | ||
293 | always @(posedge l1clk) | |
294 | begin | |
295 | if (!siclk && !soclk) q <= d; | |
296 | else q <= 1'bx; | |
297 | end | |
298 | `endif | |
299 | ||
300 | assign so = q; | |
301 | ||
302 | endmodule // dff | |
303 | module cl_a1_msffmin_fp_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
304 | // RFM 05-14-2004 | |
305 | // Level sensitive in SCAN_MODE | |
306 | // Edge triggered when not in SCAN_MODE | |
307 | ||
308 | ||
309 | parameter SIZE = 1; | |
310 | ||
311 | output q; | |
312 | output so; | |
313 | ||
314 | input d; | |
315 | input l1clk; | |
316 | input si; | |
317 | input siclk; | |
318 | input soclk; | |
319 | ||
320 | reg q; | |
321 | wire so; | |
322 | wire l1clk, siclk, soclk; | |
323 | ||
324 | `ifdef SCAN_MODE | |
325 | ||
326 | reg l1; | |
327 | `ifdef FAST_FLUSH | |
328 | always @(posedge l1clk or posedge siclk ) begin | |
329 | if (siclk) begin | |
330 | q <= 1'b0; //pseudo flush reset | |
331 | end else begin | |
332 | q <= d; | |
333 | end | |
334 | end | |
335 | `else | |
336 | always @(l1clk or siclk or soclk or d or si) | |
337 | begin | |
338 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
339 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
340 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
341 | ||
342 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
343 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
344 | end | |
345 | `endif | |
346 | `else | |
347 | wire si_unused; | |
348 | wire siclk_unused; | |
349 | wire soclk_unused; | |
350 | assign si_unused = si; | |
351 | assign siclk_unused = siclk; | |
352 | assign soclk_unused = soclk; | |
353 | ||
354 | ||
355 | `ifdef INITLATZERO | |
356 | initial q = 1'b0; | |
357 | `endif | |
358 | ||
359 | always @(posedge l1clk) | |
360 | begin | |
361 | if (!siclk && !soclk) q <= d; | |
362 | else q <= 1'bx; | |
363 | end | |
364 | `endif | |
365 | ||
366 | assign so = q; | |
367 | ||
368 | endmodule // dff | |
369 | module cl_a1_msffmin_fp_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
370 | // RFM 05-14-2004 | |
371 | // Level sensitive in SCAN_MODE | |
372 | // Edge triggered when not in SCAN_MODE | |
373 | ||
374 | ||
375 | parameter SIZE = 1; | |
376 | ||
377 | output q; | |
378 | output so; | |
379 | ||
380 | input d; | |
381 | input l1clk; | |
382 | input si; | |
383 | input siclk; | |
384 | input soclk; | |
385 | ||
386 | reg q; | |
387 | wire so; | |
388 | wire l1clk, siclk, soclk; | |
389 | ||
390 | `ifdef SCAN_MODE | |
391 | ||
392 | reg l1; | |
393 | `ifdef FAST_FLUSH | |
394 | always @(posedge l1clk or posedge siclk ) begin | |
395 | if (siclk) begin | |
396 | q <= 1'b0; //pseudo flush reset | |
397 | end else begin | |
398 | q <= d; | |
399 | end | |
400 | end | |
401 | `else | |
402 | ||
403 | always @(l1clk or siclk or soclk or d or si) | |
404 | begin | |
405 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
406 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
407 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
408 | ||
409 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
410 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
411 | end | |
412 | `endif | |
413 | `else | |
414 | wire si_unused; | |
415 | wire siclk_unused; | |
416 | wire soclk_unused; | |
417 | assign si_unused = si; | |
418 | assign siclk_unused = siclk; | |
419 | assign soclk_unused = soclk; | |
420 | ||
421 | ||
422 | `ifdef INITLATZERO | |
423 | initial q = 1'b0; | |
424 | `endif | |
425 | ||
426 | always @(posedge l1clk) | |
427 | begin | |
428 | if (!siclk && !soclk) q <= d; | |
429 | else q <= 1'bx; | |
430 | end | |
431 | `endif | |
432 | ||
433 | assign so = q; | |
434 | ||
435 | endmodule // dff | |
436 | ||
437 | ||
438 | ||
439 | ||
440 | module cl_a1_msffmin_fp_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
441 | // RFM 05-14-2004 | |
442 | // Level sensitive in SCAN_MODE | |
443 | // Edge triggered when not in SCAN_MODE | |
444 | ||
445 | ||
446 | parameter SIZE = 1; | |
447 | ||
448 | output q; | |
449 | output so; | |
450 | ||
451 | input d; | |
452 | input l1clk; | |
453 | input si; | |
454 | input siclk; | |
455 | input soclk; | |
456 | ||
457 | reg q; | |
458 | wire so; | |
459 | wire l1clk, siclk, soclk; | |
460 | ||
461 | `ifdef SCAN_MODE | |
462 | ||
463 | reg l1; | |
464 | `ifdef FAST_FLUSH | |
465 | always @(posedge l1clk or posedge siclk ) begin | |
466 | if (siclk) begin | |
467 | q <= 1'b0; //pseudo flush reset | |
468 | end else begin | |
469 | q <= d; | |
470 | end | |
471 | end | |
472 | `else | |
473 | always @(l1clk or siclk or soclk or d or si) | |
474 | begin | |
475 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
476 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
477 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
478 | ||
479 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
480 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
481 | end | |
482 | `endif | |
483 | `else | |
484 | wire si_unused; | |
485 | wire siclk_unused; | |
486 | wire soclk_unused; | |
487 | assign si_unused = si; | |
488 | assign siclk_unused = siclk; | |
489 | assign soclk_unused = soclk; | |
490 | ||
491 | ||
492 | `ifdef INITLATZERO | |
493 | initial q = 1'b0; | |
494 | `endif | |
495 | ||
496 | always @(posedge l1clk) | |
497 | begin | |
498 | if (!siclk && !soclk) q <= d; | |
499 | else q <= 1'bx; | |
500 | end | |
501 | `endif | |
502 | ||
503 | assign so = q; | |
504 | ||
505 | endmodule // dff | |
506 | module cl_a1_msffmin_fp_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
507 | // RFM 05-14-2004 | |
508 | // Level sensitive in SCAN_MODE | |
509 | // Edge triggered when not in SCAN_MODE | |
510 | ||
511 | ||
512 | parameter SIZE = 1; | |
513 | ||
514 | output q; | |
515 | output so; | |
516 | ||
517 | input d; | |
518 | input l1clk; | |
519 | input si; | |
520 | input siclk; | |
521 | input soclk; | |
522 | ||
523 | reg q; | |
524 | wire so; | |
525 | wire l1clk, siclk, soclk; | |
526 | ||
527 | `ifdef SCAN_MODE | |
528 | ||
529 | reg l1; | |
530 | `ifdef FAST_FLUSH | |
531 | always @(posedge l1clk or posedge siclk ) begin | |
532 | if (siclk) begin | |
533 | q <= 1'b0; //pseudo flush reset | |
534 | end else begin | |
535 | q <= d; | |
536 | end | |
537 | end | |
538 | `else | |
539 | always @(l1clk or siclk or soclk or d or si) | |
540 | begin | |
541 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
542 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
543 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
544 | ||
545 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
546 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
547 | end | |
548 | `endif | |
549 | `else | |
550 | wire si_unused; | |
551 | wire siclk_unused; | |
552 | wire soclk_unused; | |
553 | assign si_unused = si; | |
554 | assign siclk_unused = siclk; | |
555 | assign soclk_unused = soclk; | |
556 | ||
557 | ||
558 | `ifdef INITLATZERO | |
559 | initial q = 1'b0; | |
560 | `endif | |
561 | ||
562 | always @(posedge l1clk) | |
563 | begin | |
564 | if (!siclk && !soclk) q <= d; | |
565 | else q <= 1'bx; | |
566 | end | |
567 | `endif | |
568 | ||
569 | assign so = q; | |
570 | ||
571 | endmodule // dff | |
572 | module cl_a1_msffmin_fp_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
573 | // RFM 05-14-2004 | |
574 | // Level sensitive in SCAN_MODE | |
575 | // Edge triggered when not in SCAN_MODE | |
576 | ||
577 | ||
578 | parameter SIZE = 1; | |
579 | ||
580 | output q; | |
581 | output so; | |
582 | ||
583 | input d; | |
584 | input l1clk; | |
585 | input si; | |
586 | input siclk; | |
587 | input soclk; | |
588 | ||
589 | reg q; | |
590 | wire so; | |
591 | wire l1clk, siclk, soclk; | |
592 | ||
593 | `ifdef SCAN_MODE | |
594 | ||
595 | reg l1; | |
596 | `ifdef FAST_FLUSH | |
597 | always @(posedge l1clk or posedge siclk ) begin | |
598 | if (siclk) begin | |
599 | q <= 1'b0; //pseudo flush reset | |
600 | end else begin | |
601 | q <= d; | |
602 | end | |
603 | end | |
604 | `else | |
605 | always @(l1clk or siclk or soclk or d or si) | |
606 | begin | |
607 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
608 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
609 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
610 | ||
611 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
612 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
613 | end | |
614 | `endif | |
615 | `else | |
616 | wire si_unused; | |
617 | wire siclk_unused; | |
618 | wire soclk_unused; | |
619 | assign si_unused = si; | |
620 | assign siclk_unused = siclk; | |
621 | assign soclk_unused = soclk; | |
622 | ||
623 | ||
624 | `ifdef INITLATZERO | |
625 | initial q = 1'b0; | |
626 | `endif | |
627 | ||
628 | always @(posedge l1clk) | |
629 | begin | |
630 | if (!siclk && !soclk) q <= d; | |
631 | else q <= 1'bx; | |
632 | end | |
633 | `endif | |
634 | ||
635 | assign so = q; | |
636 | ||
637 | endmodule // dff | |
638 | module cl_a1_msffmin_fp_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
639 | // RFM 05-14-2004 | |
640 | // Level sensitive in SCAN_MODE | |
641 | // Edge triggered when not in SCAN_MODE | |
642 | ||
643 | ||
644 | parameter SIZE = 1; | |
645 | ||
646 | output q; | |
647 | output so; | |
648 | ||
649 | input d; | |
650 | input l1clk; | |
651 | input si; | |
652 | input siclk; | |
653 | input soclk; | |
654 | ||
655 | reg q; | |
656 | wire so; | |
657 | wire l1clk, siclk, soclk; | |
658 | ||
659 | `ifdef SCAN_MODE | |
660 | ||
661 | reg l1; | |
662 | `ifdef FAST_FLUSH | |
663 | always @(posedge l1clk or posedge siclk ) begin | |
664 | if (siclk) begin | |
665 | q <= 1'b0; //pseudo flush reset | |
666 | end else begin | |
667 | q <= d; | |
668 | end | |
669 | end | |
670 | `else | |
671 | always @(l1clk or siclk or soclk or d or si) | |
672 | begin | |
673 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
674 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
675 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
676 | ||
677 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
678 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
679 | end | |
680 | `endif | |
681 | `else | |
682 | wire si_unused; | |
683 | wire siclk_unused; | |
684 | wire soclk_unused; | |
685 | assign si_unused = si; | |
686 | assign siclk_unused = siclk; | |
687 | assign soclk_unused = soclk; | |
688 | ||
689 | ||
690 | `ifdef INITLATZERO | |
691 | initial q = 1'b0; | |
692 | `endif | |
693 | ||
694 | always @(posedge l1clk) | |
695 | begin | |
696 | if (!siclk && !soclk) q <= d; | |
697 | else q <= 1'bx; | |
698 | end | |
699 | `endif | |
700 | ||
701 | assign so = q; | |
702 | ||
703 | endmodule // dff | |
704 | ||
705 | module cl_a1_msffmin_fp_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
706 | // RFM 05-14-2004 | |
707 | // Level sensitive in SCAN_MODE | |
708 | // Edge triggered when not in SCAN_MODE | |
709 | ||
710 | ||
711 | parameter SIZE = 1; | |
712 | ||
713 | output q; | |
714 | output so; | |
715 | ||
716 | input d; | |
717 | input l1clk; | |
718 | input si; | |
719 | input siclk; | |
720 | input soclk; | |
721 | input reset; | |
722 | reg q; | |
723 | wire so; | |
724 | wire l1clk, siclk, soclk; | |
725 | ||
726 | `ifdef SCAN_MODE | |
727 | ||
728 | reg l1; | |
729 | `ifdef FAST_FLUSH | |
730 | always @(l1clk or siclk or d ) // vcs optimized code | |
731 | begin | |
732 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
733 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
734 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
735 | l1 <= 1'b0; | |
736 | q <= 1'b0; | |
737 | end | |
738 | end | |
739 | `else | |
740 | always @(l1clk or siclk or soclk or d or si) | |
741 | begin | |
742 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
743 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
744 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
745 | ||
746 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
747 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
748 | end | |
749 | `endif | |
750 | `else | |
751 | wire si_unused; | |
752 | wire siclk_unused; | |
753 | wire soclk_unused; | |
754 | assign si_unused = si; | |
755 | assign siclk_unused = siclk; | |
756 | assign soclk_unused = soclk; | |
757 | ||
758 | ||
759 | `ifdef INITLATZERO | |
760 | initial q = 1'b0; | |
761 | `endif | |
762 | ||
763 | always @(posedge l1clk) | |
764 | begin | |
765 | if (!siclk && !soclk) q <= (d&reset); | |
766 | else q <= 1'bx; | |
767 | end | |
768 | `endif | |
769 | ||
770 | assign so = q; | |
771 | ||
772 | endmodule // dff | |
773 | module cl_a1_msffmin_fp_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
774 | // RFM 05-14-2004 | |
775 | // Level sensitive in SCAN_MODE | |
776 | // Edge triggered when not in SCAN_MODE | |
777 | ||
778 | ||
779 | parameter SIZE = 1; | |
780 | ||
781 | output q; | |
782 | output so; | |
783 | ||
784 | input d; | |
785 | input l1clk; | |
786 | input si; | |
787 | input siclk; | |
788 | input soclk; | |
789 | input reset; | |
790 | reg q; | |
791 | wire so; | |
792 | wire l1clk, siclk, soclk; | |
793 | ||
794 | `ifdef SCAN_MODE | |
795 | ||
796 | reg l1; | |
797 | `ifdef FAST_FLUSH | |
798 | always @(l1clk or siclk or d ) // vcs optimized code | |
799 | begin | |
800 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
801 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
802 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
803 | l1 <= 1'b0; | |
804 | q <= 1'b0; | |
805 | end | |
806 | end | |
807 | `else | |
808 | always @(l1clk or siclk or soclk or d or si) | |
809 | begin | |
810 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
811 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
812 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
813 | ||
814 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
815 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
816 | end | |
817 | `endif | |
818 | `else | |
819 | wire si_unused; | |
820 | wire siclk_unused; | |
821 | wire soclk_unused; | |
822 | assign si_unused = si; | |
823 | assign siclk_unused = siclk; | |
824 | assign soclk_unused = soclk; | |
825 | ||
826 | ||
827 | `ifdef INITLATZERO | |
828 | initial q = 1'b0; | |
829 | `endif | |
830 | ||
831 | always @(posedge l1clk) | |
832 | begin | |
833 | if (!siclk && !soclk) q <= (d&reset); | |
834 | else q <= 1'bx; | |
835 | end | |
836 | `endif | |
837 | ||
838 | assign so = q; | |
839 | ||
840 | endmodule // dff | |
841 | module cl_a1_msffmin_fp_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
842 | // RFM 05-14-2004 | |
843 | // Level sensitive in SCAN_MODE | |
844 | // Edge triggered when not in SCAN_MODE | |
845 | ||
846 | ||
847 | parameter SIZE = 1; | |
848 | ||
849 | output q; | |
850 | output so; | |
851 | ||
852 | input d; | |
853 | input l1clk; | |
854 | input si; | |
855 | input siclk; | |
856 | input soclk; | |
857 | input reset; | |
858 | reg q; | |
859 | wire so; | |
860 | wire l1clk, siclk, soclk; | |
861 | ||
862 | `ifdef SCAN_MODE | |
863 | ||
864 | reg l1; | |
865 | `ifdef FAST_FLUSH | |
866 | always @(l1clk or siclk or d ) // vcs optimized code | |
867 | begin | |
868 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
869 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
870 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
871 | l1 <= 1'b0; | |
872 | q <= 1'b0; | |
873 | end | |
874 | end | |
875 | `else | |
876 | always @(l1clk or siclk or soclk or d or si) | |
877 | begin | |
878 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
879 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
880 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
881 | ||
882 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
883 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
884 | end | |
885 | `endif | |
886 | `else | |
887 | wire si_unused; | |
888 | wire siclk_unused; | |
889 | wire soclk_unused; | |
890 | assign si_unused = si; | |
891 | assign siclk_unused = siclk; | |
892 | assign soclk_unused = soclk; | |
893 | ||
894 | ||
895 | `ifdef INITLATZERO | |
896 | initial q = 1'b0; | |
897 | `endif | |
898 | ||
899 | always @(posedge l1clk) | |
900 | begin | |
901 | if (!siclk && !soclk) q <= (d&reset); | |
902 | else q <= 1'bx; | |
903 | end | |
904 | `endif | |
905 | ||
906 | assign so = q; | |
907 | ||
908 | endmodule // dff | |
909 | module cl_a1_msffmin_fp_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
910 | // RFM 05-14-2004 | |
911 | // Level sensitive in SCAN_MODE | |
912 | // Edge triggered when not in SCAN_MODE | |
913 | ||
914 | ||
915 | parameter SIZE = 1; | |
916 | ||
917 | output q; | |
918 | output so; | |
919 | ||
920 | input d; | |
921 | input l1clk; | |
922 | input si; | |
923 | input siclk; | |
924 | input soclk; | |
925 | input reset; | |
926 | reg q; | |
927 | wire so; | |
928 | wire l1clk, siclk, soclk; | |
929 | ||
930 | `ifdef SCAN_MODE | |
931 | ||
932 | reg l1; | |
933 | `ifdef FAST_FLUSH | |
934 | always @(l1clk or siclk or d ) // vcs optimized code | |
935 | begin | |
936 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
937 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
938 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
939 | l1 <= 1'b0; | |
940 | q <= 1'b0; | |
941 | end | |
942 | end | |
943 | `else | |
944 | always @(l1clk or siclk or soclk or d or si) | |
945 | begin | |
946 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
947 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
948 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
949 | ||
950 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
951 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
952 | end | |
953 | `endif | |
954 | `else | |
955 | wire si_unused; | |
956 | wire siclk_unused; | |
957 | wire soclk_unused; | |
958 | assign si_unused = si; | |
959 | assign siclk_unused = siclk; | |
960 | assign soclk_unused = soclk; | |
961 | ||
962 | ||
963 | `ifdef INITLATZERO | |
964 | initial q = 1'b0; | |
965 | `endif | |
966 | ||
967 | always @(posedge l1clk) | |
968 | begin | |
969 | if (!siclk && !soclk) q <= (d&reset); | |
970 | else q <= 1'bx; | |
971 | end | |
972 | `endif | |
973 | ||
974 | assign so = q; | |
975 | ||
976 | endmodule // dff | |
977 | module cl_a1_msffmin_fp_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
978 | // RFM 05-14-2004 | |
979 | // Level sensitive in SCAN_MODE | |
980 | // Edge triggered when not in SCAN_MODE | |
981 | ||
982 | ||
983 | parameter SIZE = 1; | |
984 | ||
985 | output q; | |
986 | output so; | |
987 | ||
988 | input d; | |
989 | input l1clk; | |
990 | input si; | |
991 | input siclk; | |
992 | input soclk; | |
993 | input reset; | |
994 | reg q; | |
995 | wire so; | |
996 | wire l1clk, siclk, soclk; | |
997 | ||
998 | `ifdef SCAN_MODE | |
999 | ||
1000 | reg l1; | |
1001 | `ifdef FAST_FLUSH | |
1002 | always @(l1clk or siclk or d ) // vcs optimized code | |
1003 | begin | |
1004 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1005 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1006 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1007 | l1 <= 1'b0; | |
1008 | q <= 1'b0; | |
1009 | end | |
1010 | end | |
1011 | `else | |
1012 | always @(l1clk or siclk or soclk or d or si) | |
1013 | begin | |
1014 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1015 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1016 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1017 | ||
1018 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1019 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1020 | end | |
1021 | `endif | |
1022 | `else | |
1023 | wire si_unused; | |
1024 | wire siclk_unused; | |
1025 | wire soclk_unused; | |
1026 | assign si_unused = si; | |
1027 | assign siclk_unused = siclk; | |
1028 | assign soclk_unused = soclk; | |
1029 | ||
1030 | ||
1031 | `ifdef INITLATZERO | |
1032 | initial q = 1'b0; | |
1033 | `endif | |
1034 | ||
1035 | always @(posedge l1clk) | |
1036 | begin | |
1037 | if (!siclk && !soclk) q <= (d&reset); | |
1038 | else q <= 1'bx; | |
1039 | end | |
1040 | `endif | |
1041 | ||
1042 | assign so = q; | |
1043 | ||
1044 | endmodule // dff | |
1045 | module cl_a1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
1046 | // RFM 05-14-2004 | |
1047 | // Level sensitive in SCAN_MODE | |
1048 | // Edge triggered when not in SCAN_MODE | |
1049 | ||
1050 | ||
1051 | parameter SIZE = 1; | |
1052 | ||
1053 | output q; | |
1054 | output so; | |
1055 | ||
1056 | input d; | |
1057 | input l1clk; | |
1058 | input si; | |
1059 | input siclk; | |
1060 | input soclk; | |
1061 | ||
1062 | reg q; | |
1063 | wire so; | |
1064 | wire l1clk, siclk, soclk; | |
1065 | ||
1066 | `ifdef SCAN_MODE | |
1067 | ||
1068 | reg l1; | |
1069 | `ifdef FAST_FLUSH | |
1070 | always @(posedge l1clk or posedge siclk ) begin | |
1071 | if (siclk) begin | |
1072 | q <= 1'b0; //pseudo flush reset | |
1073 | end else begin | |
1074 | q <= d; | |
1075 | end | |
1076 | end | |
1077 | `else | |
1078 | ||
1079 | always @(l1clk or siclk or soclk or d or si) | |
1080 | begin | |
1081 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1082 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1083 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1084 | ||
1085 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1086 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1087 | end | |
1088 | `endif | |
1089 | `else | |
1090 | wire si_unused; | |
1091 | wire siclk_unused; | |
1092 | wire soclk_unused; | |
1093 | assign si_unused = si; | |
1094 | assign siclk_unused = siclk; | |
1095 | assign soclk_unused = soclk; | |
1096 | ||
1097 | ||
1098 | `ifdef INITLATZERO | |
1099 | initial q = 1'b0; | |
1100 | `endif | |
1101 | ||
1102 | always @(posedge l1clk) | |
1103 | begin | |
1104 | if (!siclk && !soclk) q <= d; | |
1105 | else q <= 1'bx; | |
1106 | end | |
1107 | `endif | |
1108 | ||
1109 | assign so = q; | |
1110 | ||
1111 | endmodule // dff | |
1112 | ||
1113 | ||
1114 | ||
1115 | ||
1116 | module cl_a1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
1117 | // RFM 05-14-2004 | |
1118 | // Level sensitive in SCAN_MODE | |
1119 | // Edge triggered when not in SCAN_MODE | |
1120 | ||
1121 | ||
1122 | parameter SIZE = 1; | |
1123 | ||
1124 | output q; | |
1125 | output so; | |
1126 | ||
1127 | input d; | |
1128 | input l1clk; | |
1129 | input si; | |
1130 | input siclk; | |
1131 | input soclk; | |
1132 | ||
1133 | reg q; | |
1134 | wire so; | |
1135 | wire l1clk, siclk, soclk; | |
1136 | ||
1137 | `ifdef SCAN_MODE | |
1138 | ||
1139 | reg l1; | |
1140 | `ifdef FAST_FLUSH | |
1141 | always @(posedge l1clk or posedge siclk ) begin | |
1142 | if (siclk) begin | |
1143 | q <= 1'b0; //pseudo flush reset | |
1144 | end else begin | |
1145 | q <= d; | |
1146 | end | |
1147 | end | |
1148 | `else | |
1149 | always @(l1clk or siclk or soclk or d or si) | |
1150 | begin | |
1151 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1152 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1153 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1154 | ||
1155 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1156 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1157 | end | |
1158 | `endif | |
1159 | `else | |
1160 | wire si_unused; | |
1161 | wire siclk_unused; | |
1162 | wire soclk_unused; | |
1163 | assign si_unused = si; | |
1164 | assign siclk_unused = siclk; | |
1165 | assign soclk_unused = soclk; | |
1166 | ||
1167 | ||
1168 | `ifdef INITLATZERO | |
1169 | initial q = 1'b0; | |
1170 | `endif | |
1171 | ||
1172 | always @(posedge l1clk) | |
1173 | begin | |
1174 | if (!siclk && !soclk) q <= d; | |
1175 | else q <= 1'bx; | |
1176 | end | |
1177 | `endif | |
1178 | ||
1179 | assign so = q; | |
1180 | ||
1181 | endmodule // dff | |
1182 | module cl_a1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
1183 | // RFM 05-14-2004 | |
1184 | // Level sensitive in SCAN_MODE | |
1185 | // Edge triggered when not in SCAN_MODE | |
1186 | ||
1187 | ||
1188 | parameter SIZE = 1; | |
1189 | ||
1190 | output q; | |
1191 | output so; | |
1192 | ||
1193 | input d; | |
1194 | input l1clk; | |
1195 | input si; | |
1196 | input siclk; | |
1197 | input soclk; | |
1198 | ||
1199 | reg q; | |
1200 | wire so; | |
1201 | wire l1clk, siclk, soclk; | |
1202 | ||
1203 | `ifdef SCAN_MODE | |
1204 | ||
1205 | reg l1; | |
1206 | `ifdef FAST_FLUSH | |
1207 | always @(posedge l1clk or posedge siclk ) begin | |
1208 | if (siclk) begin | |
1209 | q <= 1'b0; //pseudo flush reset | |
1210 | end else begin | |
1211 | q <= d; | |
1212 | end | |
1213 | end | |
1214 | `else | |
1215 | always @(l1clk or siclk or soclk or d or si) | |
1216 | begin | |
1217 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1218 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1219 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1220 | ||
1221 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1222 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1223 | end | |
1224 | `endif | |
1225 | `else | |
1226 | wire si_unused; | |
1227 | wire siclk_unused; | |
1228 | wire soclk_unused; | |
1229 | assign si_unused = si; | |
1230 | assign siclk_unused = siclk; | |
1231 | assign soclk_unused = soclk; | |
1232 | ||
1233 | ||
1234 | `ifdef INITLATZERO | |
1235 | initial q = 1'b0; | |
1236 | `endif | |
1237 | ||
1238 | always @(posedge l1clk) | |
1239 | begin | |
1240 | if (!siclk && !soclk) q <= d; | |
1241 | else q <= 1'bx; | |
1242 | end | |
1243 | `endif | |
1244 | ||
1245 | assign so = q; | |
1246 | ||
1247 | endmodule // dff | |
1248 | module cl_a1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
1249 | // RFM 05-14-2004 | |
1250 | // Level sensitive in SCAN_MODE | |
1251 | // Edge triggered when not in SCAN_MODE | |
1252 | ||
1253 | ||
1254 | parameter SIZE = 1; | |
1255 | ||
1256 | output q; | |
1257 | output so; | |
1258 | ||
1259 | input d; | |
1260 | input l1clk; | |
1261 | input si; | |
1262 | input siclk; | |
1263 | input soclk; | |
1264 | ||
1265 | reg q; | |
1266 | wire so; | |
1267 | wire l1clk, siclk, soclk; | |
1268 | ||
1269 | `ifdef SCAN_MODE | |
1270 | ||
1271 | reg l1; | |
1272 | `ifdef FAST_FLUSH | |
1273 | always @(posedge l1clk or posedge siclk ) begin | |
1274 | if (siclk) begin | |
1275 | q <= 1'b0; //pseudo flush reset | |
1276 | end else begin | |
1277 | q <= d; | |
1278 | end | |
1279 | end | |
1280 | `else | |
1281 | always @(l1clk or siclk or soclk or d or si) | |
1282 | begin | |
1283 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1284 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1285 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1286 | ||
1287 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1288 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1289 | end | |
1290 | `endif | |
1291 | `else | |
1292 | wire si_unused; | |
1293 | wire siclk_unused; | |
1294 | wire soclk_unused; | |
1295 | assign si_unused = si; | |
1296 | assign siclk_unused = siclk; | |
1297 | assign soclk_unused = soclk; | |
1298 | ||
1299 | ||
1300 | `ifdef INITLATZERO | |
1301 | initial q = 1'b0; | |
1302 | `endif | |
1303 | ||
1304 | always @(posedge l1clk) | |
1305 | begin | |
1306 | if (!siclk && !soclk) q <= d; | |
1307 | else q <= 1'bx; | |
1308 | end | |
1309 | `endif | |
1310 | ||
1311 | assign so = q; | |
1312 | ||
1313 | endmodule // dff | |
1314 | module cl_a1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
1315 | // RFM 05-14-2004 | |
1316 | // Level sensitive in SCAN_MODE | |
1317 | // Edge triggered when not in SCAN_MODE | |
1318 | ||
1319 | ||
1320 | parameter SIZE = 1; | |
1321 | ||
1322 | output q; | |
1323 | output so; | |
1324 | ||
1325 | input d; | |
1326 | input l1clk; | |
1327 | input si; | |
1328 | input siclk; | |
1329 | input soclk; | |
1330 | ||
1331 | reg q; | |
1332 | wire so; | |
1333 | wire l1clk, siclk, soclk; | |
1334 | ||
1335 | `ifdef SCAN_MODE | |
1336 | ||
1337 | reg l1; | |
1338 | `ifdef FAST_FLUSH | |
1339 | always @(posedge l1clk or posedge siclk ) begin | |
1340 | if (siclk) begin | |
1341 | q <= 1'b0; //pseudo flush reset | |
1342 | end else begin | |
1343 | q <= d; | |
1344 | end | |
1345 | end | |
1346 | `else | |
1347 | always @(l1clk or siclk or soclk or d or si) | |
1348 | begin | |
1349 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1350 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1351 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1352 | ||
1353 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1354 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1355 | end | |
1356 | `endif | |
1357 | `else | |
1358 | wire si_unused; | |
1359 | wire siclk_unused; | |
1360 | wire soclk_unused; | |
1361 | assign si_unused = si; | |
1362 | assign siclk_unused = siclk; | |
1363 | assign soclk_unused = soclk; | |
1364 | ||
1365 | ||
1366 | `ifdef INITLATZERO | |
1367 | initial q = 1'b0; | |
1368 | `endif | |
1369 | ||
1370 | always @(posedge l1clk) | |
1371 | begin | |
1372 | if (!siclk && !soclk) q <= d; | |
1373 | else q <= 1'bx; | |
1374 | end | |
1375 | `endif | |
1376 | ||
1377 | assign so = q; | |
1378 | ||
1379 | endmodule // dff | |
1380 | module cl_a1_clken_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk, clken); | |
1381 | // Level sensitive in SCAN_MODE | |
1382 | // Edge triggered when not in SCAN_MODE | |
1383 | // created by xl on 3/18 | |
1384 | ||
1385 | ||
1386 | ||
1387 | output q; | |
1388 | output so; | |
1389 | ||
1390 | input d; | |
1391 | input l1clk; | |
1392 | input si; | |
1393 | input siclk; | |
1394 | input soclk; | |
1395 | input clken; | |
1396 | reg q; | |
1397 | wire so; | |
1398 | wire l1clk, siclk, soclk; | |
1399 | ||
1400 | `ifdef SCAN_MODE | |
1401 | ||
1402 | reg l1; | |
1403 | ||
1404 | always @(l1clk or siclk or soclk or d or si) | |
1405 | begin | |
1406 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data | |
1407 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1408 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1409 | ||
1410 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1411 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1412 | end | |
1413 | ||
1414 | ||
1415 | `else | |
1416 | wire si_unused; | |
1417 | wire siclk_unused; | |
1418 | wire soclk_unused; | |
1419 | assign si_unused = si; | |
1420 | assign siclk_unused = siclk; | |
1421 | assign soclk_unused = soclk; | |
1422 | ||
1423 | ||
1424 | `ifdef INITLATZERO | |
1425 | ||
1426 | initial q = 1'b0; | |
1427 | `endif | |
1428 | ||
1429 | always @(posedge l1clk) | |
1430 | begin | |
1431 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); | |
1432 | else q <= 1'bx; | |
1433 | end | |
1434 | `endif | |
1435 | ||
1436 | assign so = q; | |
1437 | ||
1438 | endmodule | |
1439 | module cl_a1_msffmin_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1440 | // RFM 05-14-2004 | |
1441 | // Level sensitive in SCAN_MODE | |
1442 | // Edge triggered when not in SCAN_MODE | |
1443 | ||
1444 | ||
1445 | parameter SIZE = 1; | |
1446 | ||
1447 | output q; | |
1448 | output so; | |
1449 | ||
1450 | input d; | |
1451 | input l1clk; | |
1452 | input si; | |
1453 | input siclk; | |
1454 | input soclk; | |
1455 | input reset; | |
1456 | reg q; | |
1457 | wire so; | |
1458 | wire l1clk, siclk, soclk; | |
1459 | ||
1460 | `ifdef SCAN_MODE | |
1461 | ||
1462 | reg l1; | |
1463 | `ifdef FAST_FLUSH | |
1464 | always @(l1clk or siclk or d ) // vcs optimized code | |
1465 | begin | |
1466 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1467 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1468 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1469 | l1 <= 1'b0; | |
1470 | q <= 1'b0; | |
1471 | end | |
1472 | end | |
1473 | `else | |
1474 | always @(l1clk or siclk or soclk or d or si) | |
1475 | begin | |
1476 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1477 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1478 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1479 | ||
1480 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1481 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1482 | end | |
1483 | `endif | |
1484 | `else | |
1485 | wire si_unused; | |
1486 | wire siclk_unused; | |
1487 | wire soclk_unused; | |
1488 | assign si_unused = si; | |
1489 | assign siclk_unused = siclk; | |
1490 | assign soclk_unused = soclk; | |
1491 | ||
1492 | ||
1493 | `ifdef INITLATZERO | |
1494 | initial q = 1'b0; | |
1495 | `endif | |
1496 | ||
1497 | always @(posedge l1clk) | |
1498 | begin | |
1499 | if (!siclk && !soclk) q <= (d&reset); | |
1500 | else q <= 1'bx; | |
1501 | end | |
1502 | `endif | |
1503 | ||
1504 | assign so = q; | |
1505 | ||
1506 | endmodule // dff | |
1507 | module cl_a1_msffmin_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1508 | // RFM 05-14-2004 | |
1509 | // Level sensitive in SCAN_MODE | |
1510 | // Edge triggered when not in SCAN_MODE | |
1511 | ||
1512 | ||
1513 | parameter SIZE = 1; | |
1514 | ||
1515 | output q; | |
1516 | output so; | |
1517 | ||
1518 | input d; | |
1519 | input l1clk; | |
1520 | input si; | |
1521 | input siclk; | |
1522 | input soclk; | |
1523 | input reset; | |
1524 | reg q; | |
1525 | wire so; | |
1526 | wire l1clk, siclk, soclk; | |
1527 | ||
1528 | `ifdef SCAN_MODE | |
1529 | ||
1530 | reg l1; | |
1531 | `ifdef FAST_FLUSH | |
1532 | always @(l1clk or siclk or d ) // vcs optimized code | |
1533 | begin | |
1534 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1535 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1536 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1537 | l1 <= 1'b0; | |
1538 | q <= 1'b0; | |
1539 | end | |
1540 | end | |
1541 | `else | |
1542 | always @(l1clk or siclk or soclk or d or si) | |
1543 | begin | |
1544 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1545 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1546 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1547 | ||
1548 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1549 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1550 | end | |
1551 | `endif | |
1552 | `else | |
1553 | wire si_unused; | |
1554 | wire siclk_unused; | |
1555 | wire soclk_unused; | |
1556 | assign si_unused = si; | |
1557 | assign siclk_unused = siclk; | |
1558 | assign soclk_unused = soclk; | |
1559 | ||
1560 | ||
1561 | `ifdef INITLATZERO | |
1562 | initial q = 1'b0; | |
1563 | `endif | |
1564 | ||
1565 | always @(posedge l1clk) | |
1566 | begin | |
1567 | if (!siclk && !soclk) q <= (d&reset); | |
1568 | else q <= 1'bx; | |
1569 | end | |
1570 | `endif | |
1571 | ||
1572 | assign so = q; | |
1573 | ||
1574 | endmodule // dff | |
1575 | module cl_a1_msffmin_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1576 | // RFM 05-14-2004 | |
1577 | // Level sensitive in SCAN_MODE | |
1578 | // Edge triggered when not in SCAN_MODE | |
1579 | ||
1580 | ||
1581 | parameter SIZE = 1; | |
1582 | ||
1583 | output q; | |
1584 | output so; | |
1585 | ||
1586 | input d; | |
1587 | input l1clk; | |
1588 | input si; | |
1589 | input siclk; | |
1590 | input soclk; | |
1591 | input reset; | |
1592 | reg q; | |
1593 | wire so; | |
1594 | wire l1clk, siclk, soclk; | |
1595 | ||
1596 | `ifdef SCAN_MODE | |
1597 | ||
1598 | reg l1; | |
1599 | `ifdef FAST_FLUSH | |
1600 | always @(l1clk or siclk or d ) // vcs optimized code | |
1601 | begin | |
1602 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1603 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1604 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1605 | l1 <= 1'b0; | |
1606 | q <= 1'b0; | |
1607 | end | |
1608 | end | |
1609 | `else | |
1610 | always @(l1clk or siclk or soclk or d or si) | |
1611 | begin | |
1612 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1613 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1614 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1615 | ||
1616 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1617 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1618 | end | |
1619 | `endif | |
1620 | `else | |
1621 | wire si_unused; | |
1622 | wire siclk_unused; | |
1623 | wire soclk_unused; | |
1624 | assign si_unused = si; | |
1625 | assign siclk_unused = siclk; | |
1626 | assign soclk_unused = soclk; | |
1627 | ||
1628 | ||
1629 | `ifdef INITLATZERO | |
1630 | initial q = 1'b0; | |
1631 | `endif | |
1632 | ||
1633 | always @(posedge l1clk) | |
1634 | begin | |
1635 | if (!siclk && !soclk) q <= (d&reset); | |
1636 | else q <= 1'bx; | |
1637 | end | |
1638 | `endif | |
1639 | ||
1640 | assign so = q; | |
1641 | ||
1642 | endmodule // dff | |
1643 | module cl_a1_msffmin_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1644 | // RFM 05-14-2004 | |
1645 | // Level sensitive in SCAN_MODE | |
1646 | // Edge triggered when not in SCAN_MODE | |
1647 | ||
1648 | ||
1649 | parameter SIZE = 1; | |
1650 | ||
1651 | output q; | |
1652 | output so; | |
1653 | ||
1654 | input d; | |
1655 | input l1clk; | |
1656 | input si; | |
1657 | input siclk; | |
1658 | input soclk; | |
1659 | input reset; | |
1660 | reg q; | |
1661 | wire so; | |
1662 | wire l1clk, siclk, soclk; | |
1663 | ||
1664 | `ifdef SCAN_MODE | |
1665 | ||
1666 | reg l1; | |
1667 | `ifdef FAST_FLUSH | |
1668 | always @(l1clk or siclk or d ) // vcs optimized code | |
1669 | begin | |
1670 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1671 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1672 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1673 | l1 <= 1'b0; | |
1674 | q <= 1'b0; | |
1675 | end | |
1676 | end | |
1677 | `else | |
1678 | always @(l1clk or siclk or soclk or d or si) | |
1679 | begin | |
1680 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1681 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1682 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1683 | ||
1684 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1685 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1686 | end | |
1687 | `endif | |
1688 | `else | |
1689 | wire si_unused; | |
1690 | wire siclk_unused; | |
1691 | wire soclk_unused; | |
1692 | assign si_unused = si; | |
1693 | assign siclk_unused = siclk; | |
1694 | assign soclk_unused = soclk; | |
1695 | ||
1696 | ||
1697 | `ifdef INITLATZERO | |
1698 | initial q = 1'b0; | |
1699 | `endif | |
1700 | ||
1701 | always @(posedge l1clk) | |
1702 | begin | |
1703 | if (!siclk && !soclk) q <= (d&reset); | |
1704 | else q <= 1'bx; | |
1705 | end | |
1706 | `endif | |
1707 | ||
1708 | assign so = q; | |
1709 | ||
1710 | endmodule // dff | |
1711 | module cl_a1_msffmin_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
1712 | // RFM 05-14-2004 | |
1713 | // Level sensitive in SCAN_MODE | |
1714 | // Edge triggered when not in SCAN_MODE | |
1715 | ||
1716 | ||
1717 | parameter SIZE = 1; | |
1718 | ||
1719 | output q; | |
1720 | output so; | |
1721 | ||
1722 | input d; | |
1723 | input l1clk; | |
1724 | input si; | |
1725 | input siclk; | |
1726 | input soclk; | |
1727 | input reset; | |
1728 | reg q; | |
1729 | wire so; | |
1730 | wire l1clk, siclk, soclk; | |
1731 | ||
1732 | `ifdef SCAN_MODE | |
1733 | ||
1734 | reg l1; | |
1735 | `ifdef FAST_FLUSH | |
1736 | always @(l1clk or siclk or d ) // vcs optimized code | |
1737 | begin | |
1738 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1739 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
1740 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
1741 | l1 <= 1'b0; | |
1742 | q <= 1'b0; | |
1743 | end | |
1744 | end | |
1745 | `else | |
1746 | always @(l1clk or siclk or soclk or d or si) | |
1747 | begin | |
1748 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
1749 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1750 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1751 | ||
1752 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1753 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1754 | end | |
1755 | `endif | |
1756 | `else | |
1757 | wire si_unused; | |
1758 | wire siclk_unused; | |
1759 | wire soclk_unused; | |
1760 | assign si_unused = si; | |
1761 | assign siclk_unused = siclk; | |
1762 | assign soclk_unused = soclk; | |
1763 | ||
1764 | ||
1765 | `ifdef INITLATZERO | |
1766 | initial q = 1'b0; | |
1767 | `endif | |
1768 | ||
1769 | always @(posedge l1clk) | |
1770 | begin | |
1771 | if (!siclk && !soclk) q <= (d&reset); | |
1772 | else q <= 1'bx; | |
1773 | end | |
1774 | `endif | |
1775 | ||
1776 | assign so = q; | |
1777 | ||
1778 | endmodule // dff | |
1779 | module cl_a1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, | |
1780 | ac_mode, ac_test_signal); | |
1781 | output q; | |
1782 | output so; | |
1783 | ||
1784 | input d, ac_test_signal; | |
1785 | input l1clk; | |
1786 | input si; | |
1787 | input siclk; | |
1788 | input soclk; | |
1789 | input updateclk, ac_mode; | |
1790 | ||
1791 | reg q; | |
1792 | reg so; | |
1793 | wire l1clk, siclk, soclk, updateclk; | |
1794 | ||
1795 | ||
1796 | reg l1, qm; | |
1797 | ||
1798 | always @(l1clk or siclk or soclk or d or si) | |
1799 | begin | |
1800 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
1801 | if ( l1clk && siclk) l1 <= si; // Load master with | |
1802 | // scan or flush | |
1803 | if (!l1clk && siclk) l1 <= 1'bx; // Conflict between | |
1804 | // data and scan | |
1805 | if ( l1clk && !soclk) so <= l1; // Load slave with | |
1806 | // master data | |
1807 | if ( l1clk && siclk && !soclk) so <= si; // Flush | |
1808 | end | |
1809 | ||
1810 | initial qm = 1'b0; | |
1811 | ||
1812 | always@(updateclk or l1) | |
1813 | begin | |
1814 | if(updateclk) qm <=l1; | |
1815 | end | |
1816 | always@(ac_mode or qm or ac_test_signal) | |
1817 | begin | |
1818 | if(ac_mode==0) q=qm; | |
1819 | else q=qm ^ ac_test_signal; | |
1820 | end | |
1821 | endmodule | |
1822 | module cl_a1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk); | |
1823 | ||
1824 | output latout; | |
1825 | output so; | |
1826 | input d; | |
1827 | input l1clk; | |
1828 | input si; | |
1829 | input siclk; | |
1830 | input soclk; | |
1831 | ||
1832 | ||
1833 | wire so; | |
1834 | reg s, m; | |
1835 | ||
1836 | `ifdef SCAN_MODE | |
1837 | `ifdef FAST_FLUSH | |
1838 | always @(posedge l1clk or posedge siclk ) begin | |
1839 | if (siclk) begin | |
1840 | m <= 1'b0; //pseudo flush reset | |
1841 | s <= 1'b0; //pseudo flush reset | |
1842 | end else begin | |
1843 | m <= d; | |
1844 | s <= d; | |
1845 | end | |
1846 | end | |
1847 | ||
1848 | `else | |
1849 | always @(l1clk or siclk or soclk or d or si) begin | |
1850 | ||
1851 | if (!l1clk && !siclk) m <= d; // Load master with data | |
1852 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush | |
1853 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan | |
1854 | ||
1855 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data | |
1856 | else if (l1clk && siclk && !soclk) s <= si; // Flush | |
1857 | end | |
1858 | `endif // FAST_FLUSH | |
1859 | `else | |
1860 | wire si_unused = si; | |
1861 | `ifdef INITLATZERO | |
1862 | ||
1863 | ||
1864 | initial m = 1'b0; | |
1865 | `endif | |
1866 | ||
1867 | ||
1868 | always @(l1clk or d or si or siclk) begin | |
1869 | if(siclk==0 && l1clk==0) m = d; | |
1870 | else if(siclk && !l1clk) m = 1'bx; | |
1871 | if(siclk && l1clk) m = si; | |
1872 | if(l1clk && !soclk) s = m; | |
1873 | end | |
1874 | ||
1875 | `endif | |
1876 | ||
1877 | assign latout = m; | |
1878 | assign so = s; | |
1879 | ||
1880 | ||
1881 | endmodule | |
1882 | ||
1883 | ||
1884 | ||
1885 | ||
1886 | ||
1887 | module cl_a1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se ); | |
1888 | ||
1889 | ||
1890 | ||
1891 | ||
1892 | ||
1893 | output q; | |
1894 | output so; | |
1895 | ||
1896 | input d; | |
1897 | input l1clk; | |
1898 | input si; | |
1899 | input siclk; | |
1900 | input soclk; | |
1901 | input se; | |
1902 | ||
1903 | reg q; | |
1904 | wire so; | |
1905 | wire l1clk, siclk, soclk; | |
1906 | ||
1907 | ||
1908 | ||
1909 | reg l1; | |
1910 | ||
1911 | always @(l1clk or siclk or soclk or d or si or se) | |
1912 | begin | |
1913 | ||
1914 | if (siclk) l1 <= si; // Load master with scan or flush | |
1915 | ||
1916 | if(se && !soclk && l1clk && siclk) q <= si; | |
1917 | else if ( se && !soclk && l1clk) q <= l1; | |
1918 | else if ( !soclk && l1clk) q <= d; | |
1919 | end | |
1920 | ||
1921 | ||
1922 | ||
1923 | ||
1924 | `ifdef INITLATZERO | |
1925 | initial q = 1'b0; | |
1926 | `endif | |
1927 | ||
1928 | ||
1929 | ||
1930 | assign so = q; | |
1931 | ||
1932 | endmodule // dff | |
1933 | module cl_a1_clken_msff_4x ( q, so, d, l1clk, si, siclk, soclk, clken); | |
1934 | // Level sensitive in SCAN_MODE | |
1935 | // Edge triggered when not in SCAN_MODE | |
1936 | // created by xl on 3/18 | |
1937 | ||
1938 | ||
1939 | ||
1940 | output q; | |
1941 | output so; | |
1942 | ||
1943 | input d; | |
1944 | input l1clk; | |
1945 | input si; | |
1946 | input siclk; | |
1947 | input soclk; | |
1948 | input clken; | |
1949 | reg q; | |
1950 | wire so; | |
1951 | wire l1clk, siclk, soclk; | |
1952 | ||
1953 | `ifdef SCAN_MODE | |
1954 | ||
1955 | reg l1; | |
1956 | `ifdef FAST_FLUSH | |
1957 | always @(posedge l1clk or posedge siclk ) begin | |
1958 | if (siclk) begin | |
1959 | q <= 1'b0; //pseudo flush reset | |
1960 | end else begin | |
1961 | q <= (d & clken ) | (q & !clken); | |
1962 | end | |
1963 | end | |
1964 | `else | |
1965 | always @(l1clk or siclk or soclk or d or si) | |
1966 | begin | |
1967 | if (!l1clk && !siclk) l1 <= (d & clken ) | (q & !clken); // Load master with data | |
1968 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
1969 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
1970 | ||
1971 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
1972 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
1973 | end | |
1974 | ||
1975 | `endif | |
1976 | `else | |
1977 | wire si_unused; | |
1978 | wire siclk_unused; | |
1979 | wire soclk_unused; | |
1980 | assign si_unused = si; | |
1981 | assign siclk_unused = siclk; | |
1982 | assign soclk_unused = soclk; | |
1983 | ||
1984 | ||
1985 | `ifdef INITLATZERO | |
1986 | ||
1987 | initial q = 1'b0; | |
1988 | `endif | |
1989 | ||
1990 | always @(posedge l1clk) | |
1991 | begin | |
1992 | if (!siclk && !soclk) q <= (d & clken ) | (q & !clken); | |
1993 | else q <= 1'bx; | |
1994 | end | |
1995 | `endif | |
1996 | ||
1997 | assign so = q; | |
1998 | ||
1999 | endmodule | |
2000 | ||
2001 | module cl_a1_msff_arst_4x ( q, so, d, l1clk, si, siclk, soclk, reset ); | |
2002 | // RFM 05-14-2004 | |
2003 | // Level sensitive in SCAN_MODE | |
2004 | // Edge triggered when not in SCAN_MODE | |
2005 | ||
2006 | ||
2007 | parameter SIZE = 1; | |
2008 | ||
2009 | output q; | |
2010 | output so; | |
2011 | ||
2012 | input d; | |
2013 | input l1clk; | |
2014 | input si; | |
2015 | input siclk; | |
2016 | input soclk; | |
2017 | input reset; | |
2018 | ||
2019 | reg q; | |
2020 | wire so; | |
2021 | wire l1clk, siclk, soclk; | |
2022 | ||
2023 | `ifdef SCAN_MODE | |
2024 | ||
2025 | reg l1; | |
2026 | ||
2027 | always @(l1clk or siclk or soclk or d or si or reset) | |
2028 | begin | |
2029 | if (reset ) l1 <= 1'b0; | |
2030 | else if (!l1clk && !siclk) l1 <= d; | |
2031 | else if ( l1clk && siclk) l1 <= si; | |
2032 | else if (!l1clk && siclk) l1 <= 1'bx; | |
2033 | ||
2034 | if (reset) q <= 1'b0; | |
2035 | else if ( l1clk && !siclk && !soclk) q <= l1; | |
2036 | else if ( l1clk && siclk && !soclk) q <= si; | |
2037 | ||
2038 | end | |
2039 | ||
2040 | ||
2041 | `else | |
2042 | wire si_unused; | |
2043 | wire siclk_unused; | |
2044 | wire soclk_unused; | |
2045 | assign si_unused = si; | |
2046 | assign siclk_unused = siclk; | |
2047 | assign soclk_unused = soclk; | |
2048 | ||
2049 | ||
2050 | `ifdef INITLATZERO | |
2051 | initial q = 1'b0; | |
2052 | `endif | |
2053 | ||
2054 | always @(posedge l1clk or posedge reset) | |
2055 | begin | |
2056 | ||
2057 | if ( reset) q <= 1'b0; | |
2058 | else if (!siclk && !soclk ) q <= d; | |
2059 | else q <= 1'bx; | |
2060 | end | |
2061 | `endif | |
2062 | ||
2063 | assign so = q; | |
2064 | ||
2065 | endmodule // dff | |
2066 | ||
2067 | ||
2068 | ||
2069 | module cl_a1_aomux2_12x ( | |
2070 | in0, | |
2071 | in1, | |
2072 | sel0, | |
2073 | sel1, | |
2074 | out | |
2075 | ); | |
2076 | input in0; | |
2077 | input in1; | |
2078 | input sel0; | |
2079 | input sel1; | |
2080 | output out; | |
2081 | ||
2082 | `ifdef LIB | |
2083 | assign out = ((sel0 & in0) | | |
2084 | (sel1 & in1)); | |
2085 | `endif | |
2086 | ||
2087 | ||
2088 | endmodule | |
2089 | module cl_a1_aomux2_16x ( | |
2090 | in0, | |
2091 | in1, | |
2092 | sel0, | |
2093 | sel1, | |
2094 | out | |
2095 | ); | |
2096 | input in0; | |
2097 | input in1; | |
2098 | input sel0; | |
2099 | input sel1; | |
2100 | output out; | |
2101 | ||
2102 | `ifdef LIB | |
2103 | assign out = ((sel0 & in0) | | |
2104 | (sel1 & in1)); | |
2105 | `endif | |
2106 | ||
2107 | ||
2108 | endmodule | |
2109 | module cl_a1_aomux2_1x ( | |
2110 | in0, | |
2111 | in1, | |
2112 | sel0, | |
2113 | sel1, | |
2114 | out | |
2115 | ); | |
2116 | input in0; | |
2117 | input in1; | |
2118 | input sel0; | |
2119 | input sel1; | |
2120 | output out; | |
2121 | ||
2122 | `ifdef LIB | |
2123 | assign out = ((sel0 & in0) | | |
2124 | (sel1 & in1)); | |
2125 | `endif | |
2126 | ||
2127 | ||
2128 | endmodule | |
2129 | module cl_a1_aomux2_2x ( | |
2130 | in0, | |
2131 | in1, | |
2132 | sel0, | |
2133 | sel1, | |
2134 | out | |
2135 | ); | |
2136 | input in0; | |
2137 | input in1; | |
2138 | input sel0; | |
2139 | input sel1; | |
2140 | output out; | |
2141 | ||
2142 | `ifdef LIB | |
2143 | assign out = ((sel0 & in0) | | |
2144 | (sel1 & in1)); | |
2145 | `endif | |
2146 | ||
2147 | ||
2148 | endmodule | |
2149 | module cl_a1_aomux2_4x ( | |
2150 | in0, | |
2151 | in1, | |
2152 | sel0, | |
2153 | sel1, | |
2154 | out | |
2155 | ); | |
2156 | input in0; | |
2157 | input in1; | |
2158 | input sel0; | |
2159 | input sel1; | |
2160 | output out; | |
2161 | ||
2162 | `ifdef LIB | |
2163 | assign out = ((sel0 & in0) | | |
2164 | (sel1 & in1)); | |
2165 | `endif | |
2166 | ||
2167 | ||
2168 | endmodule | |
2169 | module cl_a1_aomux2_6x ( | |
2170 | in0, | |
2171 | in1, | |
2172 | sel0, | |
2173 | sel1, | |
2174 | out | |
2175 | ); | |
2176 | input in0; | |
2177 | input in1; | |
2178 | input sel0; | |
2179 | input sel1; | |
2180 | output out; | |
2181 | ||
2182 | `ifdef LIB | |
2183 | assign out = ((sel0 & in0) | | |
2184 | (sel1 & in1)); | |
2185 | `endif | |
2186 | ||
2187 | ||
2188 | endmodule | |
2189 | module cl_a1_aomux2_8x ( | |
2190 | in0, | |
2191 | in1, | |
2192 | sel0, | |
2193 | sel1, | |
2194 | out | |
2195 | ); | |
2196 | input in0; | |
2197 | input in1; | |
2198 | input sel0; | |
2199 | input sel1; | |
2200 | output out; | |
2201 | ||
2202 | `ifdef LIB | |
2203 | assign out = ((sel0 & in0) | | |
2204 | (sel1 & in1)); | |
2205 | `endif | |
2206 | ||
2207 | ||
2208 | endmodule | |
2209 | module cl_a1_aomux3_12x ( | |
2210 | in0, | |
2211 | in1, | |
2212 | in2, | |
2213 | sel0, | |
2214 | sel1, | |
2215 | sel2, | |
2216 | out | |
2217 | ); | |
2218 | input in0; | |
2219 | input in1; | |
2220 | input in2; | |
2221 | input sel0; | |
2222 | input sel1; | |
2223 | input sel2; | |
2224 | output out; | |
2225 | ||
2226 | `ifdef LIB | |
2227 | assign out = ((sel0 & in0) | | |
2228 | (sel1 & in1) | | |
2229 | (sel2 & in2)); | |
2230 | `endif | |
2231 | ||
2232 | endmodule | |
2233 | module cl_a1_aomux3_16x ( | |
2234 | in0, | |
2235 | in1, | |
2236 | in2, | |
2237 | sel0, | |
2238 | sel1, | |
2239 | sel2, | |
2240 | out | |
2241 | ); | |
2242 | input in0; | |
2243 | input in1; | |
2244 | input in2; | |
2245 | input sel0; | |
2246 | input sel1; | |
2247 | input sel2; | |
2248 | output out; | |
2249 | ||
2250 | `ifdef LIB | |
2251 | assign out = ((sel0 & in0) | | |
2252 | (sel1 & in1) | | |
2253 | (sel2 & in2)); | |
2254 | `endif | |
2255 | ||
2256 | endmodule | |
2257 | module cl_a1_aomux3_1x ( | |
2258 | in0, | |
2259 | in1, | |
2260 | in2, | |
2261 | sel0, | |
2262 | sel1, | |
2263 | sel2, | |
2264 | out | |
2265 | ); | |
2266 | input in0; | |
2267 | input in1; | |
2268 | input in2; | |
2269 | input sel0; | |
2270 | input sel1; | |
2271 | input sel2; | |
2272 | output out; | |
2273 | ||
2274 | `ifdef LIB | |
2275 | assign out = ((sel0 & in0) | | |
2276 | (sel1 & in1) | | |
2277 | (sel2 & in2)); | |
2278 | `endif | |
2279 | ||
2280 | endmodule | |
2281 | module cl_a1_aomux3_2x ( | |
2282 | in0, | |
2283 | in1, | |
2284 | in2, | |
2285 | sel0, | |
2286 | sel1, | |
2287 | sel2, | |
2288 | out | |
2289 | ); | |
2290 | input in0; | |
2291 | input in1; | |
2292 | input in2; | |
2293 | input sel0; | |
2294 | input sel1; | |
2295 | input sel2; | |
2296 | output out; | |
2297 | ||
2298 | `ifdef LIB | |
2299 | assign out = ((sel0 & in0) | | |
2300 | (sel1 & in1) | | |
2301 | (sel2 & in2)); | |
2302 | `endif | |
2303 | ||
2304 | endmodule | |
2305 | module cl_a1_aomux3_4x ( | |
2306 | in0, | |
2307 | in1, | |
2308 | in2, | |
2309 | sel0, | |
2310 | sel1, | |
2311 | sel2, | |
2312 | out | |
2313 | ); | |
2314 | input in0; | |
2315 | input in1; | |
2316 | input in2; | |
2317 | input sel0; | |
2318 | input sel1; | |
2319 | input sel2; | |
2320 | output out; | |
2321 | ||
2322 | `ifdef LIB | |
2323 | assign out = ((sel0 & in0) | | |
2324 | (sel1 & in1) | | |
2325 | (sel2 & in2)); | |
2326 | `endif | |
2327 | ||
2328 | endmodule | |
2329 | module cl_a1_aomux3_6x ( | |
2330 | in0, | |
2331 | in1, | |
2332 | in2, | |
2333 | sel0, | |
2334 | sel1, | |
2335 | sel2, | |
2336 | out | |
2337 | ); | |
2338 | input in0; | |
2339 | input in1; | |
2340 | input in2; | |
2341 | input sel0; | |
2342 | input sel1; | |
2343 | input sel2; | |
2344 | output out; | |
2345 | ||
2346 | `ifdef LIB | |
2347 | assign out = ((sel0 & in0) | | |
2348 | (sel1 & in1) | | |
2349 | (sel2 & in2)); | |
2350 | `endif | |
2351 | ||
2352 | endmodule | |
2353 | module cl_a1_aomux3_8x ( | |
2354 | in0, | |
2355 | in1, | |
2356 | in2, | |
2357 | sel0, | |
2358 | sel1, | |
2359 | sel2, | |
2360 | out | |
2361 | ); | |
2362 | input in0; | |
2363 | input in1; | |
2364 | input in2; | |
2365 | input sel0; | |
2366 | input sel1; | |
2367 | input sel2; | |
2368 | output out; | |
2369 | ||
2370 | `ifdef LIB | |
2371 | assign out = ((sel0 & in0) | | |
2372 | (sel1 & in1) | | |
2373 | (sel2 & in2)); | |
2374 | `endif | |
2375 | ||
2376 | endmodule | |
2377 | module cl_a1_aomux4_12x ( | |
2378 | in0, | |
2379 | in1, | |
2380 | in2, | |
2381 | in3, | |
2382 | sel0, | |
2383 | sel1, | |
2384 | sel2, | |
2385 | sel3, | |
2386 | out | |
2387 | ); | |
2388 | input in0; | |
2389 | input in1; | |
2390 | input in2; | |
2391 | input in3; | |
2392 | input sel0; | |
2393 | input sel1; | |
2394 | input sel2; | |
2395 | input sel3; | |
2396 | output out; | |
2397 | ||
2398 | `ifdef LIB | |
2399 | assign out = ((sel0 & in0) | | |
2400 | (sel1 & in1) | | |
2401 | (sel2 & in2) | | |
2402 | (sel3 & in3)); | |
2403 | `endif | |
2404 | ||
2405 | endmodule | |
2406 | module cl_a1_aomux4_16x ( | |
2407 | in0, | |
2408 | in1, | |
2409 | in2, | |
2410 | in3, | |
2411 | sel0, | |
2412 | sel1, | |
2413 | sel2, | |
2414 | sel3, | |
2415 | out | |
2416 | ); | |
2417 | input in0; | |
2418 | input in1; | |
2419 | input in2; | |
2420 | input in3; | |
2421 | input sel0; | |
2422 | input sel1; | |
2423 | input sel2; | |
2424 | input sel3; | |
2425 | output out; | |
2426 | ||
2427 | `ifdef LIB | |
2428 | assign out = ((sel0 & in0) | | |
2429 | (sel1 & in1) | | |
2430 | (sel2 & in2) | | |
2431 | (sel3 & in3)); | |
2432 | `endif | |
2433 | ||
2434 | endmodule | |
2435 | module cl_a1_aomux4_1x ( | |
2436 | in0, | |
2437 | in1, | |
2438 | in2, | |
2439 | in3, | |
2440 | sel0, | |
2441 | sel1, | |
2442 | sel2, | |
2443 | sel3, | |
2444 | out | |
2445 | ); | |
2446 | input in0; | |
2447 | input in1; | |
2448 | input in2; | |
2449 | input in3; | |
2450 | input sel0; | |
2451 | input sel1; | |
2452 | input sel2; | |
2453 | input sel3; | |
2454 | output out; | |
2455 | ||
2456 | `ifdef LIB | |
2457 | assign out = ((sel0 & in0) | | |
2458 | (sel1 & in1) | | |
2459 | (sel2 & in2) | | |
2460 | (sel3 & in3)); | |
2461 | `endif | |
2462 | ||
2463 | endmodule | |
2464 | module cl_a1_aomux4_2x ( | |
2465 | in0, | |
2466 | in1, | |
2467 | in2, | |
2468 | in3, | |
2469 | sel0, | |
2470 | sel1, | |
2471 | sel2, | |
2472 | sel3, | |
2473 | out | |
2474 | ); | |
2475 | input in0; | |
2476 | input in1; | |
2477 | input in2; | |
2478 | input in3; | |
2479 | input sel0; | |
2480 | input sel1; | |
2481 | input sel2; | |
2482 | input sel3; | |
2483 | output out; | |
2484 | ||
2485 | `ifdef LIB | |
2486 | assign out = ((sel0 & in0) | | |
2487 | (sel1 & in1) | | |
2488 | (sel2 & in2) | | |
2489 | (sel3 & in3)); | |
2490 | `endif | |
2491 | ||
2492 | endmodule | |
2493 | module cl_a1_aomux4_4x ( | |
2494 | in0, | |
2495 | in1, | |
2496 | in2, | |
2497 | in3, | |
2498 | sel0, | |
2499 | sel1, | |
2500 | sel2, | |
2501 | sel3, | |
2502 | out | |
2503 | ); | |
2504 | input in0; | |
2505 | input in1; | |
2506 | input in2; | |
2507 | input in3; | |
2508 | input sel0; | |
2509 | input sel1; | |
2510 | input sel2; | |
2511 | input sel3; | |
2512 | output out; | |
2513 | ||
2514 | `ifdef LIB | |
2515 | assign out = ((sel0 & in0) | | |
2516 | (sel1 & in1) | | |
2517 | (sel2 & in2) | | |
2518 | (sel3 & in3)); | |
2519 | `endif | |
2520 | ||
2521 | endmodule | |
2522 | module cl_a1_aomux4_6x ( | |
2523 | in0, | |
2524 | in1, | |
2525 | in2, | |
2526 | in3, | |
2527 | sel0, | |
2528 | sel1, | |
2529 | sel2, | |
2530 | sel3, | |
2531 | out | |
2532 | ); | |
2533 | input in0; | |
2534 | input in1; | |
2535 | input in2; | |
2536 | input in3; | |
2537 | input sel0; | |
2538 | input sel1; | |
2539 | input sel2; | |
2540 | input sel3; | |
2541 | output out; | |
2542 | ||
2543 | `ifdef LIB | |
2544 | assign out = ((sel0 & in0) | | |
2545 | (sel1 & in1) | | |
2546 | (sel2 & in2) | | |
2547 | (sel3 & in3)); | |
2548 | `endif | |
2549 | ||
2550 | endmodule | |
2551 | module cl_a1_aomux4_8x ( | |
2552 | in0, | |
2553 | in1, | |
2554 | in2, | |
2555 | in3, | |
2556 | sel0, | |
2557 | sel1, | |
2558 | sel2, | |
2559 | sel3, | |
2560 | out | |
2561 | ); | |
2562 | input in0; | |
2563 | input in1; | |
2564 | input in2; | |
2565 | input in3; | |
2566 | input sel0; | |
2567 | input sel1; | |
2568 | input sel2; | |
2569 | input sel3; | |
2570 | output out; | |
2571 | ||
2572 | `ifdef LIB | |
2573 | assign out = ((sel0 & in0) | | |
2574 | (sel1 & in1) | | |
2575 | (sel2 & in2) | | |
2576 | (sel3 & in3)); | |
2577 | `endif | |
2578 | ||
2579 | endmodule | |
2580 | module cl_a1_aomux4_niu_8x ( | |
2581 | in0, | |
2582 | in1, | |
2583 | in2, | |
2584 | in3, | |
2585 | sel0, | |
2586 | sel1, | |
2587 | sel2, | |
2588 | sel3, | |
2589 | out | |
2590 | ); | |
2591 | input in0; | |
2592 | input in1; | |
2593 | input in2; | |
2594 | input in3; | |
2595 | input sel0; | |
2596 | input sel1; | |
2597 | input sel2; | |
2598 | input sel3; | |
2599 | output out; | |
2600 | ||
2601 | `ifdef LIB | |
2602 | assign out = ((sel0 & in0) | | |
2603 | (sel1 & in1) | | |
2604 | (sel2 & in2) | | |
2605 | (sel3 & in3)); | |
2606 | `endif | |
2607 | ||
2608 | endmodule | |
2609 | module cl_a1_aomux5_12x ( | |
2610 | in0, | |
2611 | in1, | |
2612 | in2, | |
2613 | in3, | |
2614 | in4, | |
2615 | sel0, | |
2616 | sel1, | |
2617 | sel2, | |
2618 | sel3, | |
2619 | sel4, | |
2620 | out | |
2621 | ); | |
2622 | input in0; | |
2623 | input in1; | |
2624 | input in2; | |
2625 | input in3; | |
2626 | input in4; | |
2627 | input sel0; | |
2628 | input sel1; | |
2629 | input sel2; | |
2630 | input sel3; | |
2631 | input sel4; | |
2632 | output out; | |
2633 | ||
2634 | `ifdef LIB | |
2635 | assign out = ((sel0 & in0) | | |
2636 | (sel1 & in1) | | |
2637 | (sel2 & in2) | | |
2638 | (sel3 & in3) | | |
2639 | (sel4 & in4)); | |
2640 | `endif | |
2641 | ||
2642 | endmodule | |
2643 | module cl_a1_aomux5_16x ( | |
2644 | in0, | |
2645 | in1, | |
2646 | in2, | |
2647 | in3, | |
2648 | in4, | |
2649 | sel0, | |
2650 | sel1, | |
2651 | sel2, | |
2652 | sel3, | |
2653 | sel4, | |
2654 | out | |
2655 | ); | |
2656 | input in0; | |
2657 | input in1; | |
2658 | input in2; | |
2659 | input in3; | |
2660 | input in4; | |
2661 | input sel0; | |
2662 | input sel1; | |
2663 | input sel2; | |
2664 | input sel3; | |
2665 | input sel4; | |
2666 | output out; | |
2667 | ||
2668 | `ifdef LIB | |
2669 | assign out = ((sel0 & in0) | | |
2670 | (sel1 & in1) | | |
2671 | (sel2 & in2) | | |
2672 | (sel3 & in3) | | |
2673 | (sel4 & in4)); | |
2674 | `endif | |
2675 | ||
2676 | endmodule | |
2677 | module cl_a1_aomux5_1x ( | |
2678 | in0, | |
2679 | in1, | |
2680 | in2, | |
2681 | in3, | |
2682 | in4, | |
2683 | sel0, | |
2684 | sel1, | |
2685 | sel2, | |
2686 | sel3, | |
2687 | sel4, | |
2688 | out | |
2689 | ); | |
2690 | input in0; | |
2691 | input in1; | |
2692 | input in2; | |
2693 | input in3; | |
2694 | input in4; | |
2695 | input sel0; | |
2696 | input sel1; | |
2697 | input sel2; | |
2698 | input sel3; | |
2699 | input sel4; | |
2700 | output out; | |
2701 | ||
2702 | `ifdef LIB | |
2703 | assign out = ((sel0 & in0) | | |
2704 | (sel1 & in1) | | |
2705 | (sel2 & in2) | | |
2706 | (sel3 & in3) | | |
2707 | (sel4 & in4)); | |
2708 | `endif | |
2709 | ||
2710 | endmodule | |
2711 | module cl_a1_aomux5_2x ( | |
2712 | in0, | |
2713 | in1, | |
2714 | in2, | |
2715 | in3, | |
2716 | in4, | |
2717 | sel0, | |
2718 | sel1, | |
2719 | sel2, | |
2720 | sel3, | |
2721 | sel4, | |
2722 | out | |
2723 | ); | |
2724 | input in0; | |
2725 | input in1; | |
2726 | input in2; | |
2727 | input in3; | |
2728 | input in4; | |
2729 | input sel0; | |
2730 | input sel1; | |
2731 | input sel2; | |
2732 | input sel3; | |
2733 | input sel4; | |
2734 | output out; | |
2735 | ||
2736 | `ifdef LIB | |
2737 | assign out = ((sel0 & in0) | | |
2738 | (sel1 & in1) | | |
2739 | (sel2 & in2) | | |
2740 | (sel3 & in3) | | |
2741 | (sel4 & in4)); | |
2742 | `endif | |
2743 | ||
2744 | endmodule | |
2745 | module cl_a1_aomux5_4x ( | |
2746 | in0, | |
2747 | in1, | |
2748 | in2, | |
2749 | in3, | |
2750 | in4, | |
2751 | sel0, | |
2752 | sel1, | |
2753 | sel2, | |
2754 | sel3, | |
2755 | sel4, | |
2756 | out | |
2757 | ); | |
2758 | input in0; | |
2759 | input in1; | |
2760 | input in2; | |
2761 | input in3; | |
2762 | input in4; | |
2763 | input sel0; | |
2764 | input sel1; | |
2765 | input sel2; | |
2766 | input sel3; | |
2767 | input sel4; | |
2768 | output out; | |
2769 | ||
2770 | `ifdef LIB | |
2771 | assign out = ((sel0 & in0) | | |
2772 | (sel1 & in1) | | |
2773 | (sel2 & in2) | | |
2774 | (sel3 & in3) | | |
2775 | (sel4 & in4)); | |
2776 | `endif | |
2777 | ||
2778 | endmodule | |
2779 | module cl_a1_aomux5_6x ( | |
2780 | in0, | |
2781 | in1, | |
2782 | in2, | |
2783 | in3, | |
2784 | in4, | |
2785 | sel0, | |
2786 | sel1, | |
2787 | sel2, | |
2788 | sel3, | |
2789 | sel4, | |
2790 | out | |
2791 | ); | |
2792 | input in0; | |
2793 | input in1; | |
2794 | input in2; | |
2795 | input in3; | |
2796 | input in4; | |
2797 | input sel0; | |
2798 | input sel1; | |
2799 | input sel2; | |
2800 | input sel3; | |
2801 | input sel4; | |
2802 | output out; | |
2803 | ||
2804 | `ifdef LIB | |
2805 | assign out = ((sel0 & in0) | | |
2806 | (sel1 & in1) | | |
2807 | (sel2 & in2) | | |
2808 | (sel3 & in3) | | |
2809 | (sel4 & in4)); | |
2810 | `endif | |
2811 | ||
2812 | endmodule | |
2813 | module cl_a1_aomux5_8x ( | |
2814 | in0, | |
2815 | in1, | |
2816 | in2, | |
2817 | in3, | |
2818 | in4, | |
2819 | sel0, | |
2820 | sel1, | |
2821 | sel2, | |
2822 | sel3, | |
2823 | sel4, | |
2824 | out | |
2825 | ); | |
2826 | input in0; | |
2827 | input in1; | |
2828 | input in2; | |
2829 | input in3; | |
2830 | input in4; | |
2831 | input sel0; | |
2832 | input sel1; | |
2833 | input sel2; | |
2834 | input sel3; | |
2835 | input sel4; | |
2836 | output out; | |
2837 | ||
2838 | `ifdef LIB | |
2839 | assign out = ((sel0 & in0) | | |
2840 | (sel1 & in1) | | |
2841 | (sel2 & in2) | | |
2842 | (sel3 & in3) | | |
2843 | (sel4 & in4)); | |
2844 | `endif | |
2845 | ||
2846 | endmodule | |
2847 | module cl_a1_aomux6_12x ( | |
2848 | in0, | |
2849 | in1, | |
2850 | in2, | |
2851 | in3, | |
2852 | in4, | |
2853 | in5, | |
2854 | sel0, | |
2855 | sel1, | |
2856 | sel2, | |
2857 | sel3, | |
2858 | sel4, | |
2859 | sel5, | |
2860 | out | |
2861 | ); | |
2862 | input in0; | |
2863 | input in1; | |
2864 | input in2; | |
2865 | input in3; | |
2866 | input in4; | |
2867 | input in5; | |
2868 | input sel0; | |
2869 | input sel1; | |
2870 | input sel2; | |
2871 | input sel3; | |
2872 | input sel4; | |
2873 | input sel5; | |
2874 | output out; | |
2875 | ||
2876 | `ifdef LIB | |
2877 | assign out = ((sel0 & in0) | | |
2878 | (sel1 & in1) | | |
2879 | (sel2 & in2) | | |
2880 | (sel3 & in3) | | |
2881 | (sel4 & in4) | | |
2882 | (sel5 & in5)); | |
2883 | `endif | |
2884 | ||
2885 | endmodule | |
2886 | module cl_a1_aomux6_16x ( | |
2887 | in0, | |
2888 | in1, | |
2889 | in2, | |
2890 | in3, | |
2891 | in4, | |
2892 | in5, | |
2893 | sel0, | |
2894 | sel1, | |
2895 | sel2, | |
2896 | sel3, | |
2897 | sel4, | |
2898 | sel5, | |
2899 | out | |
2900 | ); | |
2901 | input in0; | |
2902 | input in1; | |
2903 | input in2; | |
2904 | input in3; | |
2905 | input in4; | |
2906 | input in5; | |
2907 | input sel0; | |
2908 | input sel1; | |
2909 | input sel2; | |
2910 | input sel3; | |
2911 | input sel4; | |
2912 | input sel5; | |
2913 | output out; | |
2914 | ||
2915 | `ifdef LIB | |
2916 | assign out = ((sel0 & in0) | | |
2917 | (sel1 & in1) | | |
2918 | (sel2 & in2) | | |
2919 | (sel3 & in3) | | |
2920 | (sel4 & in4) | | |
2921 | (sel5 & in5)); | |
2922 | `endif | |
2923 | ||
2924 | endmodule | |
2925 | module cl_a1_aomux6_1x ( | |
2926 | in0, | |
2927 | in1, | |
2928 | in2, | |
2929 | in3, | |
2930 | in4, | |
2931 | in5, | |
2932 | sel0, | |
2933 | sel1, | |
2934 | sel2, | |
2935 | sel3, | |
2936 | sel4, | |
2937 | sel5, | |
2938 | out | |
2939 | ); | |
2940 | input in0; | |
2941 | input in1; | |
2942 | input in2; | |
2943 | input in3; | |
2944 | input in4; | |
2945 | input in5; | |
2946 | input sel0; | |
2947 | input sel1; | |
2948 | input sel2; | |
2949 | input sel3; | |
2950 | input sel4; | |
2951 | input sel5; | |
2952 | output out; | |
2953 | ||
2954 | `ifdef LIB | |
2955 | assign out = ((sel0 & in0) | | |
2956 | (sel1 & in1) | | |
2957 | (sel2 & in2) | | |
2958 | (sel3 & in3) | | |
2959 | (sel4 & in4) | | |
2960 | (sel5 & in5)); | |
2961 | `endif | |
2962 | ||
2963 | endmodule | |
2964 | module cl_a1_aomux6_2x ( | |
2965 | in0, | |
2966 | in1, | |
2967 | in2, | |
2968 | in3, | |
2969 | in4, | |
2970 | in5, | |
2971 | sel0, | |
2972 | sel1, | |
2973 | sel2, | |
2974 | sel3, | |
2975 | sel4, | |
2976 | sel5, | |
2977 | out | |
2978 | ); | |
2979 | input in0; | |
2980 | input in1; | |
2981 | input in2; | |
2982 | input in3; | |
2983 | input in4; | |
2984 | input in5; | |
2985 | input sel0; | |
2986 | input sel1; | |
2987 | input sel2; | |
2988 | input sel3; | |
2989 | input sel4; | |
2990 | input sel5; | |
2991 | output out; | |
2992 | ||
2993 | `ifdef LIB | |
2994 | assign out = ((sel0 & in0) | | |
2995 | (sel1 & in1) | | |
2996 | (sel2 & in2) | | |
2997 | (sel3 & in3) | | |
2998 | (sel4 & in4) | | |
2999 | (sel5 & in5)); | |
3000 | `endif | |
3001 | ||
3002 | endmodule | |
3003 | module cl_a1_aomux6_4x ( | |
3004 | in0, | |
3005 | in1, | |
3006 | in2, | |
3007 | in3, | |
3008 | in4, | |
3009 | in5, | |
3010 | sel0, | |
3011 | sel1, | |
3012 | sel2, | |
3013 | sel3, | |
3014 | sel4, | |
3015 | sel5, | |
3016 | out | |
3017 | ); | |
3018 | input in0; | |
3019 | input in1; | |
3020 | input in2; | |
3021 | input in3; | |
3022 | input in4; | |
3023 | input in5; | |
3024 | input sel0; | |
3025 | input sel1; | |
3026 | input sel2; | |
3027 | input sel3; | |
3028 | input sel4; | |
3029 | input sel5; | |
3030 | output out; | |
3031 | ||
3032 | `ifdef LIB | |
3033 | assign out = ((sel0 & in0) | | |
3034 | (sel1 & in1) | | |
3035 | (sel2 & in2) | | |
3036 | (sel3 & in3) | | |
3037 | (sel4 & in4) | | |
3038 | (sel5 & in5)); | |
3039 | `endif | |
3040 | ||
3041 | endmodule | |
3042 | module cl_a1_aomux6_6x ( | |
3043 | in0, | |
3044 | in1, | |
3045 | in2, | |
3046 | in3, | |
3047 | in4, | |
3048 | in5, | |
3049 | sel0, | |
3050 | sel1, | |
3051 | sel2, | |
3052 | sel3, | |
3053 | sel4, | |
3054 | sel5, | |
3055 | out | |
3056 | ); | |
3057 | input in0; | |
3058 | input in1; | |
3059 | input in2; | |
3060 | input in3; | |
3061 | input in4; | |
3062 | input in5; | |
3063 | input sel0; | |
3064 | input sel1; | |
3065 | input sel2; | |
3066 | input sel3; | |
3067 | input sel4; | |
3068 | input sel5; | |
3069 | output out; | |
3070 | ||
3071 | `ifdef LIB | |
3072 | assign out = ((sel0 & in0) | | |
3073 | (sel1 & in1) | | |
3074 | (sel2 & in2) | | |
3075 | (sel3 & in3) | | |
3076 | (sel4 & in4) | | |
3077 | (sel5 & in5)); | |
3078 | `endif | |
3079 | ||
3080 | endmodule | |
3081 | module cl_a1_aomux6_8x ( | |
3082 | in0, | |
3083 | in1, | |
3084 | in2, | |
3085 | in3, | |
3086 | in4, | |
3087 | in5, | |
3088 | sel0, | |
3089 | sel1, | |
3090 | sel2, | |
3091 | sel3, | |
3092 | sel4, | |
3093 | sel5, | |
3094 | out | |
3095 | ); | |
3096 | input in0; | |
3097 | input in1; | |
3098 | input in2; | |
3099 | input in3; | |
3100 | input in4; | |
3101 | input in5; | |
3102 | input sel0; | |
3103 | input sel1; | |
3104 | input sel2; | |
3105 | input sel3; | |
3106 | input sel4; | |
3107 | input sel5; | |
3108 | output out; | |
3109 | ||
3110 | `ifdef LIB | |
3111 | assign out = ((sel0 & in0) | | |
3112 | (sel1 & in1) | | |
3113 | (sel2 & in2) | | |
3114 | (sel3 & in3) | | |
3115 | (sel4 & in4) | | |
3116 | (sel5 & in5)); | |
3117 | `endif | |
3118 | ||
3119 | endmodule | |
3120 | module cl_a1_aomux6_by2_1x ( | |
3121 | in0, | |
3122 | in1, | |
3123 | in2, | |
3124 | in3, | |
3125 | in4, | |
3126 | in5, | |
3127 | sel0, | |
3128 | sel1, | |
3129 | sel2, | |
3130 | sel3, | |
3131 | sel4, | |
3132 | sel5, | |
3133 | out | |
3134 | ); | |
3135 | input in0; | |
3136 | input in1; | |
3137 | input in2; | |
3138 | input in3; | |
3139 | input in4; | |
3140 | input in5; | |
3141 | input sel0; | |
3142 | input sel1; | |
3143 | input sel2; | |
3144 | input sel3; | |
3145 | input sel4; | |
3146 | input sel5; | |
3147 | output out; | |
3148 | ||
3149 | `ifdef LIB | |
3150 | assign out = ((sel0 & in0) | | |
3151 | (sel1 & in1) | | |
3152 | (sel2 & in2) | | |
3153 | (sel3 & in3) | | |
3154 | (sel4 & in4) | | |
3155 | (sel5 & in5)); | |
3156 | `endif | |
3157 | ||
3158 | endmodule | |
3159 | module cl_a1_aomux6_by2_2x ( | |
3160 | in0, | |
3161 | in1, | |
3162 | in2, | |
3163 | in3, | |
3164 | in4, | |
3165 | in5, | |
3166 | sel0, | |
3167 | sel1, | |
3168 | sel2, | |
3169 | sel3, | |
3170 | sel4, | |
3171 | sel5, | |
3172 | out | |
3173 | ); | |
3174 | input in0; | |
3175 | input in1; | |
3176 | input in2; | |
3177 | input in3; | |
3178 | input in4; | |
3179 | input in5; | |
3180 | input sel0; | |
3181 | input sel1; | |
3182 | input sel2; | |
3183 | input sel3; | |
3184 | input sel4; | |
3185 | input sel5; | |
3186 | output out; | |
3187 | ||
3188 | `ifdef LIB | |
3189 | assign out = ((sel0 & in0) | | |
3190 | (sel1 & in1) | | |
3191 | (sel2 & in2) | | |
3192 | (sel3 & in3) | | |
3193 | (sel4 & in4) | | |
3194 | (sel5 & in5)); | |
3195 | `endif | |
3196 | ||
3197 | endmodule | |
3198 | module cl_a1_aomux7_12x ( | |
3199 | in0, | |
3200 | in1, | |
3201 | in2, | |
3202 | in3, | |
3203 | in4, | |
3204 | in5, | |
3205 | in6, | |
3206 | sel0, | |
3207 | sel1, | |
3208 | sel2, | |
3209 | sel3, | |
3210 | sel4, | |
3211 | sel5, | |
3212 | sel6, | |
3213 | out | |
3214 | ); | |
3215 | input in0; | |
3216 | input in1; | |
3217 | input in2; | |
3218 | input in3; | |
3219 | input in4; | |
3220 | input in5; | |
3221 | input in6; | |
3222 | input sel0; | |
3223 | input sel1; | |
3224 | input sel2; | |
3225 | input sel3; | |
3226 | input sel4; | |
3227 | input sel5; | |
3228 | input sel6; | |
3229 | output out; | |
3230 | ||
3231 | `ifdef LIB | |
3232 | assign out = ((sel0 & in0) | | |
3233 | (sel1 & in1) | | |
3234 | (sel2 & in2) | | |
3235 | (sel3 & in3) | | |
3236 | (sel4 & in4) | | |
3237 | (sel5 & in5) | | |
3238 | (sel6 & in6)); | |
3239 | `endif | |
3240 | ||
3241 | endmodule | |
3242 | module cl_a1_aomux7_16x ( | |
3243 | in0, | |
3244 | in1, | |
3245 | in2, | |
3246 | in3, | |
3247 | in4, | |
3248 | in5, | |
3249 | in6, | |
3250 | sel0, | |
3251 | sel1, | |
3252 | sel2, | |
3253 | sel3, | |
3254 | sel4, | |
3255 | sel5, | |
3256 | sel6, | |
3257 | out | |
3258 | ); | |
3259 | input in0; | |
3260 | input in1; | |
3261 | input in2; | |
3262 | input in3; | |
3263 | input in4; | |
3264 | input in5; | |
3265 | input in6; | |
3266 | input sel0; | |
3267 | input sel1; | |
3268 | input sel2; | |
3269 | input sel3; | |
3270 | input sel4; | |
3271 | input sel5; | |
3272 | input sel6; | |
3273 | output out; | |
3274 | ||
3275 | `ifdef LIB | |
3276 | assign out = ((sel0 & in0) | | |
3277 | (sel1 & in1) | | |
3278 | (sel2 & in2) | | |
3279 | (sel3 & in3) | | |
3280 | (sel4 & in4) | | |
3281 | (sel5 & in5) | | |
3282 | (sel6 & in6)); | |
3283 | `endif | |
3284 | ||
3285 | endmodule | |
3286 | module cl_a1_aomux7_1x ( | |
3287 | in0, | |
3288 | in1, | |
3289 | in2, | |
3290 | in3, | |
3291 | in4, | |
3292 | in5, | |
3293 | in6, | |
3294 | sel0, | |
3295 | sel1, | |
3296 | sel2, | |
3297 | sel3, | |
3298 | sel4, | |
3299 | sel5, | |
3300 | sel6, | |
3301 | out | |
3302 | ); | |
3303 | input in0; | |
3304 | input in1; | |
3305 | input in2; | |
3306 | input in3; | |
3307 | input in4; | |
3308 | input in5; | |
3309 | input in6; | |
3310 | input sel0; | |
3311 | input sel1; | |
3312 | input sel2; | |
3313 | input sel3; | |
3314 | input sel4; | |
3315 | input sel5; | |
3316 | input sel6; | |
3317 | output out; | |
3318 | ||
3319 | `ifdef LIB | |
3320 | assign out = ((sel0 & in0) | | |
3321 | (sel1 & in1) | | |
3322 | (sel2 & in2) | | |
3323 | (sel3 & in3) | | |
3324 | (sel4 & in4) | | |
3325 | (sel5 & in5) | | |
3326 | (sel6 & in6)); | |
3327 | `endif | |
3328 | ||
3329 | endmodule | |
3330 | module cl_a1_aomux7_2x ( | |
3331 | in0, | |
3332 | in1, | |
3333 | in2, | |
3334 | in3, | |
3335 | in4, | |
3336 | in5, | |
3337 | in6, | |
3338 | sel0, | |
3339 | sel1, | |
3340 | sel2, | |
3341 | sel3, | |
3342 | sel4, | |
3343 | sel5, | |
3344 | sel6, | |
3345 | out | |
3346 | ); | |
3347 | input in0; | |
3348 | input in1; | |
3349 | input in2; | |
3350 | input in3; | |
3351 | input in4; | |
3352 | input in5; | |
3353 | input in6; | |
3354 | input sel0; | |
3355 | input sel1; | |
3356 | input sel2; | |
3357 | input sel3; | |
3358 | input sel4; | |
3359 | input sel5; | |
3360 | input sel6; | |
3361 | output out; | |
3362 | ||
3363 | `ifdef LIB | |
3364 | assign out = ((sel0 & in0) | | |
3365 | (sel1 & in1) | | |
3366 | (sel2 & in2) | | |
3367 | (sel3 & in3) | | |
3368 | (sel4 & in4) | | |
3369 | (sel5 & in5) | | |
3370 | (sel6 & in6)); | |
3371 | `endif | |
3372 | ||
3373 | endmodule | |
3374 | module cl_a1_aomux7_4x ( | |
3375 | in0, | |
3376 | in1, | |
3377 | in2, | |
3378 | in3, | |
3379 | in4, | |
3380 | in5, | |
3381 | in6, | |
3382 | sel0, | |
3383 | sel1, | |
3384 | sel2, | |
3385 | sel3, | |
3386 | sel4, | |
3387 | sel5, | |
3388 | sel6, | |
3389 | out | |
3390 | ); | |
3391 | input in0; | |
3392 | input in1; | |
3393 | input in2; | |
3394 | input in3; | |
3395 | input in4; | |
3396 | input in5; | |
3397 | input in6; | |
3398 | input sel0; | |
3399 | input sel1; | |
3400 | input sel2; | |
3401 | input sel3; | |
3402 | input sel4; | |
3403 | input sel5; | |
3404 | input sel6; | |
3405 | output out; | |
3406 | ||
3407 | `ifdef LIB | |
3408 | assign out = ((sel0 & in0) | | |
3409 | (sel1 & in1) | | |
3410 | (sel2 & in2) | | |
3411 | (sel3 & in3) | | |
3412 | (sel4 & in4) | | |
3413 | (sel5 & in5) | | |
3414 | (sel6 & in6)); | |
3415 | `endif | |
3416 | ||
3417 | endmodule | |
3418 | module cl_a1_aomux7_6x ( | |
3419 | in0, | |
3420 | in1, | |
3421 | in2, | |
3422 | in3, | |
3423 | in4, | |
3424 | in5, | |
3425 | in6, | |
3426 | sel0, | |
3427 | sel1, | |
3428 | sel2, | |
3429 | sel3, | |
3430 | sel4, | |
3431 | sel5, | |
3432 | sel6, | |
3433 | out | |
3434 | ); | |
3435 | input in0; | |
3436 | input in1; | |
3437 | input in2; | |
3438 | input in3; | |
3439 | input in4; | |
3440 | input in5; | |
3441 | input in6; | |
3442 | input sel0; | |
3443 | input sel1; | |
3444 | input sel2; | |
3445 | input sel3; | |
3446 | input sel4; | |
3447 | input sel5; | |
3448 | input sel6; | |
3449 | output out; | |
3450 | ||
3451 | `ifdef LIB | |
3452 | assign out = ((sel0 & in0) | | |
3453 | (sel1 & in1) | | |
3454 | (sel2 & in2) | | |
3455 | (sel3 & in3) | | |
3456 | (sel4 & in4) | | |
3457 | (sel5 & in5) | | |
3458 | (sel6 & in6)); | |
3459 | `endif | |
3460 | ||
3461 | endmodule | |
3462 | module cl_a1_aomux7_8x ( | |
3463 | in0, | |
3464 | in1, | |
3465 | in2, | |
3466 | in3, | |
3467 | in4, | |
3468 | in5, | |
3469 | in6, | |
3470 | sel0, | |
3471 | sel1, | |
3472 | sel2, | |
3473 | sel3, | |
3474 | sel4, | |
3475 | sel5, | |
3476 | sel6, | |
3477 | out | |
3478 | ); | |
3479 | input in0; | |
3480 | input in1; | |
3481 | input in2; | |
3482 | input in3; | |
3483 | input in4; | |
3484 | input in5; | |
3485 | input in6; | |
3486 | input sel0; | |
3487 | input sel1; | |
3488 | input sel2; | |
3489 | input sel3; | |
3490 | input sel4; | |
3491 | input sel5; | |
3492 | input sel6; | |
3493 | output out; | |
3494 | ||
3495 | `ifdef LIB | |
3496 | assign out = ((sel0 & in0) | | |
3497 | (sel1 & in1) | | |
3498 | (sel2 & in2) | | |
3499 | (sel3 & in3) | | |
3500 | (sel4 & in4) | | |
3501 | (sel5 & in5) | | |
3502 | (sel6 & in6)); | |
3503 | `endif | |
3504 | ||
3505 | endmodule | |
3506 | module cl_a1_aomux7_by2_1x ( | |
3507 | in0, | |
3508 | in1, | |
3509 | in2, | |
3510 | in3, | |
3511 | in4, | |
3512 | in5, | |
3513 | in6, | |
3514 | sel0, | |
3515 | sel1, | |
3516 | sel2, | |
3517 | sel3, | |
3518 | sel4, | |
3519 | sel5, | |
3520 | sel6, | |
3521 | out | |
3522 | ); | |
3523 | input in0; | |
3524 | input in1; | |
3525 | input in2; | |
3526 | input in3; | |
3527 | input in4; | |
3528 | input in5; | |
3529 | input in6; | |
3530 | input sel0; | |
3531 | input sel1; | |
3532 | input sel2; | |
3533 | input sel3; | |
3534 | input sel4; | |
3535 | input sel5; | |
3536 | input sel6; | |
3537 | output out; | |
3538 | ||
3539 | `ifdef LIB | |
3540 | assign out = ((sel0 & in0) | | |
3541 | (sel1 & in1) | | |
3542 | (sel2 & in2) | | |
3543 | (sel3 & in3) | | |
3544 | (sel4 & in4) | | |
3545 | (sel5 & in5) | | |
3546 | (sel6 & in6)); | |
3547 | `endif | |
3548 | ||
3549 | endmodule | |
3550 | module cl_a1_aomux7_by2_2x ( | |
3551 | in0, | |
3552 | in1, | |
3553 | in2, | |
3554 | in3, | |
3555 | in4, | |
3556 | in5, | |
3557 | in6, | |
3558 | sel0, | |
3559 | sel1, | |
3560 | sel2, | |
3561 | sel3, | |
3562 | sel4, | |
3563 | sel5, | |
3564 | sel6, | |
3565 | out | |
3566 | ); | |
3567 | input in0; | |
3568 | input in1; | |
3569 | input in2; | |
3570 | input in3; | |
3571 | input in4; | |
3572 | input in5; | |
3573 | input in6; | |
3574 | input sel0; | |
3575 | input sel1; | |
3576 | input sel2; | |
3577 | input sel3; | |
3578 | input sel4; | |
3579 | input sel5; | |
3580 | input sel6; | |
3581 | output out; | |
3582 | ||
3583 | `ifdef LIB | |
3584 | assign out = ((sel0 & in0) | | |
3585 | (sel1 & in1) | | |
3586 | (sel2 & in2) | | |
3587 | (sel3 & in3) | | |
3588 | (sel4 & in4) | | |
3589 | (sel5 & in5) | | |
3590 | (sel6 & in6)); | |
3591 | `endif | |
3592 | ||
3593 | endmodule | |
3594 | module cl_a1_aomux8_12x ( | |
3595 | in0, | |
3596 | in1, | |
3597 | in2, | |
3598 | in3, | |
3599 | in4, | |
3600 | in5, | |
3601 | in6, | |
3602 | in7, | |
3603 | sel0, | |
3604 | sel1, | |
3605 | sel2, | |
3606 | sel3, | |
3607 | sel4, | |
3608 | sel5, | |
3609 | sel6, | |
3610 | sel7, | |
3611 | out | |
3612 | ); | |
3613 | input in0; | |
3614 | input in1; | |
3615 | input in2; | |
3616 | input in3; | |
3617 | input in4; | |
3618 | input in5; | |
3619 | input in6; | |
3620 | input in7; | |
3621 | input sel0; | |
3622 | input sel1; | |
3623 | input sel2; | |
3624 | input sel3; | |
3625 | input sel4; | |
3626 | input sel5; | |
3627 | input sel6; | |
3628 | input sel7; | |
3629 | output out; | |
3630 | ||
3631 | `ifdef LIB | |
3632 | assign out = ((sel0 & in0) | | |
3633 | (sel1 & in1) | | |
3634 | (sel2 & in2) | | |
3635 | (sel3 & in3) | | |
3636 | (sel4 & in4) | | |
3637 | (sel5 & in5) | | |
3638 | (sel6 & in6) | | |
3639 | (sel7 & in7)); | |
3640 | `endif | |
3641 | ||
3642 | ||
3643 | endmodule | |
3644 | module cl_a1_aomux8_16x ( | |
3645 | in0, | |
3646 | in1, | |
3647 | in2, | |
3648 | in3, | |
3649 | in4, | |
3650 | in5, | |
3651 | in6, | |
3652 | in7, | |
3653 | sel0, | |
3654 | sel1, | |
3655 | sel2, | |
3656 | sel3, | |
3657 | sel4, | |
3658 | sel5, | |
3659 | sel6, | |
3660 | sel7, | |
3661 | out | |
3662 | ); | |
3663 | input in0; | |
3664 | input in1; | |
3665 | input in2; | |
3666 | input in3; | |
3667 | input in4; | |
3668 | input in5; | |
3669 | input in6; | |
3670 | input in7; | |
3671 | input sel0; | |
3672 | input sel1; | |
3673 | input sel2; | |
3674 | input sel3; | |
3675 | input sel4; | |
3676 | input sel5; | |
3677 | input sel6; | |
3678 | input sel7; | |
3679 | output out; | |
3680 | ||
3681 | `ifdef LIB | |
3682 | assign out = ((sel0 & in0) | | |
3683 | (sel1 & in1) | | |
3684 | (sel2 & in2) | | |
3685 | (sel3 & in3) | | |
3686 | (sel4 & in4) | | |
3687 | (sel5 & in5) | | |
3688 | (sel6 & in6) | | |
3689 | (sel7 & in7)); | |
3690 | `endif | |
3691 | ||
3692 | ||
3693 | endmodule | |
3694 | module cl_a1_aomux8_1x ( | |
3695 | in0, | |
3696 | in1, | |
3697 | in2, | |
3698 | in3, | |
3699 | in4, | |
3700 | in5, | |
3701 | in6, | |
3702 | in7, | |
3703 | sel0, | |
3704 | sel1, | |
3705 | sel2, | |
3706 | sel3, | |
3707 | sel4, | |
3708 | sel5, | |
3709 | sel6, | |
3710 | sel7, | |
3711 | out | |
3712 | ); | |
3713 | input in0; | |
3714 | input in1; | |
3715 | input in2; | |
3716 | input in3; | |
3717 | input in4; | |
3718 | input in5; | |
3719 | input in6; | |
3720 | input in7; | |
3721 | input sel0; | |
3722 | input sel1; | |
3723 | input sel2; | |
3724 | input sel3; | |
3725 | input sel4; | |
3726 | input sel5; | |
3727 | input sel6; | |
3728 | input sel7; | |
3729 | output out; | |
3730 | ||
3731 | `ifdef LIB | |
3732 | assign out = ((sel0 & in0) | | |
3733 | (sel1 & in1) | | |
3734 | (sel2 & in2) | | |
3735 | (sel3 & in3) | | |
3736 | (sel4 & in4) | | |
3737 | (sel5 & in5) | | |
3738 | (sel6 & in6) | | |
3739 | (sel7 & in7)); | |
3740 | `endif | |
3741 | ||
3742 | ||
3743 | endmodule | |
3744 | module cl_a1_aomux8_2x ( | |
3745 | in0, | |
3746 | in1, | |
3747 | in2, | |
3748 | in3, | |
3749 | in4, | |
3750 | in5, | |
3751 | in6, | |
3752 | in7, | |
3753 | sel0, | |
3754 | sel1, | |
3755 | sel2, | |
3756 | sel3, | |
3757 | sel4, | |
3758 | sel5, | |
3759 | sel6, | |
3760 | sel7, | |
3761 | out | |
3762 | ); | |
3763 | input in0; | |
3764 | input in1; | |
3765 | input in2; | |
3766 | input in3; | |
3767 | input in4; | |
3768 | input in5; | |
3769 | input in6; | |
3770 | input in7; | |
3771 | input sel0; | |
3772 | input sel1; | |
3773 | input sel2; | |
3774 | input sel3; | |
3775 | input sel4; | |
3776 | input sel5; | |
3777 | input sel6; | |
3778 | input sel7; | |
3779 | output out; | |
3780 | ||
3781 | `ifdef LIB | |
3782 | assign out = ((sel0 & in0) | | |
3783 | (sel1 & in1) | | |
3784 | (sel2 & in2) | | |
3785 | (sel3 & in3) | | |
3786 | (sel4 & in4) | | |
3787 | (sel5 & in5) | | |
3788 | (sel6 & in6) | | |
3789 | (sel7 & in7)); | |
3790 | `endif | |
3791 | ||
3792 | ||
3793 | endmodule | |
3794 | module cl_a1_aomux8_4x ( | |
3795 | in0, | |
3796 | in1, | |
3797 | in2, | |
3798 | in3, | |
3799 | in4, | |
3800 | in5, | |
3801 | in6, | |
3802 | in7, | |
3803 | sel0, | |
3804 | sel1, | |
3805 | sel2, | |
3806 | sel3, | |
3807 | sel4, | |
3808 | sel5, | |
3809 | sel6, | |
3810 | sel7, | |
3811 | out | |
3812 | ); | |
3813 | input in0; | |
3814 | input in1; | |
3815 | input in2; | |
3816 | input in3; | |
3817 | input in4; | |
3818 | input in5; | |
3819 | input in6; | |
3820 | input in7; | |
3821 | input sel0; | |
3822 | input sel1; | |
3823 | input sel2; | |
3824 | input sel3; | |
3825 | input sel4; | |
3826 | input sel5; | |
3827 | input sel6; | |
3828 | input sel7; | |
3829 | output out; | |
3830 | ||
3831 | `ifdef LIB | |
3832 | assign out = ((sel0 & in0) | | |
3833 | (sel1 & in1) | | |
3834 | (sel2 & in2) | | |
3835 | (sel3 & in3) | | |
3836 | (sel4 & in4) | | |
3837 | (sel5 & in5) | | |
3838 | (sel6 & in6) | | |
3839 | (sel7 & in7)); | |
3840 | `endif | |
3841 | ||
3842 | ||
3843 | endmodule | |
3844 | module cl_a1_aomux8_6x ( | |
3845 | in0, | |
3846 | in1, | |
3847 | in2, | |
3848 | in3, | |
3849 | in4, | |
3850 | in5, | |
3851 | in6, | |
3852 | in7, | |
3853 | sel0, | |
3854 | sel1, | |
3855 | sel2, | |
3856 | sel3, | |
3857 | sel4, | |
3858 | sel5, | |
3859 | sel6, | |
3860 | sel7, | |
3861 | out | |
3862 | ); | |
3863 | input in0; | |
3864 | input in1; | |
3865 | input in2; | |
3866 | input in3; | |
3867 | input in4; | |
3868 | input in5; | |
3869 | input in6; | |
3870 | input in7; | |
3871 | input sel0; | |
3872 | input sel1; | |
3873 | input sel2; | |
3874 | input sel3; | |
3875 | input sel4; | |
3876 | input sel5; | |
3877 | input sel6; | |
3878 | input sel7; | |
3879 | output out; | |
3880 | ||
3881 | `ifdef LIB | |
3882 | assign out = ((sel0 & in0) | | |
3883 | (sel1 & in1) | | |
3884 | (sel2 & in2) | | |
3885 | (sel3 & in3) | | |
3886 | (sel4 & in4) | | |
3887 | (sel5 & in5) | | |
3888 | (sel6 & in6) | | |
3889 | (sel7 & in7)); | |
3890 | `endif | |
3891 | ||
3892 | ||
3893 | endmodule | |
3894 | module cl_a1_aomux8_8x ( | |
3895 | in0, | |
3896 | in1, | |
3897 | in2, | |
3898 | in3, | |
3899 | in4, | |
3900 | in5, | |
3901 | in6, | |
3902 | in7, | |
3903 | sel0, | |
3904 | sel1, | |
3905 | sel2, | |
3906 | sel3, | |
3907 | sel4, | |
3908 | sel5, | |
3909 | sel6, | |
3910 | sel7, | |
3911 | out | |
3912 | ); | |
3913 | input in0; | |
3914 | input in1; | |
3915 | input in2; | |
3916 | input in3; | |
3917 | input in4; | |
3918 | input in5; | |
3919 | input in6; | |
3920 | input in7; | |
3921 | input sel0; | |
3922 | input sel1; | |
3923 | input sel2; | |
3924 | input sel3; | |
3925 | input sel4; | |
3926 | input sel5; | |
3927 | input sel6; | |
3928 | input sel7; | |
3929 | output out; | |
3930 | ||
3931 | `ifdef LIB | |
3932 | assign out = ((sel0 & in0) | | |
3933 | (sel1 & in1) | | |
3934 | (sel2 & in2) | | |
3935 | (sel3 & in3) | | |
3936 | (sel4 & in4) | | |
3937 | (sel5 & in5) | | |
3938 | (sel6 & in6) | | |
3939 | (sel7 & in7)); | |
3940 | `endif | |
3941 | ||
3942 | ||
3943 | endmodule | |
3944 | module cl_a1_aomux8_by2_1x ( | |
3945 | in0, | |
3946 | in1, | |
3947 | in2, | |
3948 | in3, | |
3949 | in4, | |
3950 | in5, | |
3951 | in6, | |
3952 | in7, | |
3953 | sel0, | |
3954 | sel1, | |
3955 | sel2, | |
3956 | sel3, | |
3957 | sel4, | |
3958 | sel5, | |
3959 | sel6, | |
3960 | sel7, | |
3961 | out | |
3962 | ); | |
3963 | input in0; | |
3964 | input in1; | |
3965 | input in2; | |
3966 | input in3; | |
3967 | input in4; | |
3968 | input in5; | |
3969 | input in6; | |
3970 | input in7; | |
3971 | input sel0; | |
3972 | input sel1; | |
3973 | input sel2; | |
3974 | input sel3; | |
3975 | input sel4; | |
3976 | input sel5; | |
3977 | input sel6; | |
3978 | input sel7; | |
3979 | output out; | |
3980 | ||
3981 | `ifdef LIB | |
3982 | assign out = ((sel0 & in0) | | |
3983 | (sel1 & in1) | | |
3984 | (sel2 & in2) | | |
3985 | (sel3 & in3) | | |
3986 | (sel4 & in4) | | |
3987 | (sel5 & in5) | | |
3988 | (sel6 & in6) | | |
3989 | (sel7 & in7)); | |
3990 | `endif | |
3991 | ||
3992 | ||
3993 | endmodule | |
3994 | module cl_a1_aomux8_by2_2x ( | |
3995 | in0, | |
3996 | in1, | |
3997 | in2, | |
3998 | in3, | |
3999 | in4, | |
4000 | in5, | |
4001 | in6, | |
4002 | in7, | |
4003 | sel0, | |
4004 | sel1, | |
4005 | sel2, | |
4006 | sel3, | |
4007 | sel4, | |
4008 | sel5, | |
4009 | sel6, | |
4010 | sel7, | |
4011 | out | |
4012 | ); | |
4013 | input in0; | |
4014 | input in1; | |
4015 | input in2; | |
4016 | input in3; | |
4017 | input in4; | |
4018 | input in5; | |
4019 | input in6; | |
4020 | input in7; | |
4021 | input sel0; | |
4022 | input sel1; | |
4023 | input sel2; | |
4024 | input sel3; | |
4025 | input sel4; | |
4026 | input sel5; | |
4027 | input sel6; | |
4028 | input sel7; | |
4029 | output out; | |
4030 | ||
4031 | `ifdef LIB | |
4032 | assign out = ((sel0 & in0) | | |
4033 | (sel1 & in1) | | |
4034 | (sel2 & in2) | | |
4035 | (sel3 & in3) | | |
4036 | (sel4 & in4) | | |
4037 | (sel5 & in5) | | |
4038 | (sel6 & in6) | | |
4039 | (sel7 & in7)); | |
4040 | `endif | |
4041 | ||
4042 | ||
4043 | endmodule | |
4044 | module cl_a1_l1hdr_12x ( | |
4045 | l2clk, | |
4046 | se, | |
4047 | pce, | |
4048 | pce_ov, | |
4049 | stop, | |
4050 | l1clk | |
4051 | ||
4052 | ); | |
4053 | ||
4054 | ||
4055 | ||
4056 | ||
4057 | input l2clk; // level 2 clock, from clock grid | |
4058 | input se; // Scan Enable | |
4059 | input pce; // Clock enable for local power savings | |
4060 | input pce_ov; // TCU sourced clock enable override for testing | |
4061 | input stop; // TCU/CCU sourced clock stop for debug | |
4062 | output l1clk; | |
4063 | `ifdef FORMAL_TOOL | |
4064 | wire l1en = (~stop & ( pce | pce_ov )); | |
4065 | assign l1clk = (l2clk & l1en) | se; | |
4066 | `else | |
4067 | `ifdef LIB | |
4068 | reg l1en; | |
4069 | ||
4070 | ||
4071 | `ifdef SCAN_MODE | |
4072 | always @ (l2clk or stop or pce or pce_ov) | |
4073 | begin | |
4074 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4075 | end | |
4076 | `else | |
4077 | always @ (negedge l2clk ) | |
4078 | begin | |
4079 | l1en <= (~stop & ( pce | pce_ov )); | |
4080 | end | |
4081 | `endif | |
4082 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4083 | ||
4084 | ||
4085 | ||
4086 | `endif | |
4087 | `endif | |
4088 | ||
4089 | endmodule | |
4090 | ||
4091 | module cl_a1_l1hdr_16x ( | |
4092 | l2clk, | |
4093 | se, | |
4094 | pce, | |
4095 | pce_ov, | |
4096 | stop, | |
4097 | l1clk | |
4098 | ); | |
4099 | // RFM 05/21/2004 | |
4100 | ||
4101 | ||
4102 | ||
4103 | input l2clk; // level 2 clock, from clock grid | |
4104 | input se; // Scan Enable | |
4105 | input pce; // Clock enable for local power savings | |
4106 | input pce_ov; // TCU sourced clock enable override for testing | |
4107 | input stop; // TCU/CCU sourced clock stop for debug | |
4108 | output l1clk; | |
4109 | `ifdef FORMAL_TOOL | |
4110 | wire l1en = (~stop & ( pce | pce_ov )); | |
4111 | assign l1clk = (l2clk & l1en) | se; | |
4112 | `else | |
4113 | `ifdef LIB | |
4114 | reg l1en; | |
4115 | ||
4116 | ||
4117 | ||
4118 | `ifdef SCAN_MODE | |
4119 | always @ (l2clk or stop or pce or pce_ov) | |
4120 | begin | |
4121 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4122 | end | |
4123 | `else | |
4124 | always @ (negedge l2clk ) | |
4125 | begin | |
4126 | l1en <= (~stop & ( pce | pce_ov )); | |
4127 | end | |
4128 | `endif | |
4129 | ||
4130 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4131 | ||
4132 | ||
4133 | ||
4134 | `endif | |
4135 | `endif | |
4136 | ||
4137 | endmodule | |
4138 | module cl_a1_l1hdr_24x ( | |
4139 | l2clk, | |
4140 | se, | |
4141 | pce, | |
4142 | pce_ov, | |
4143 | stop, | |
4144 | l1clk | |
4145 | ); | |
4146 | // RFM 05/21/2004 | |
4147 | ||
4148 | ||
4149 | ||
4150 | input l2clk; // level 2 clock, from clock grid | |
4151 | input se; // Scan Enable | |
4152 | input pce; // Clock enable for local power savings | |
4153 | input pce_ov; // TCU sourced clock enable override for testing | |
4154 | input stop; // TCU/CCU sourced clock stop for debug | |
4155 | output l1clk; | |
4156 | `ifdef FORMAL_TOOL | |
4157 | wire l1en = (~stop & ( pce | pce_ov )); | |
4158 | assign l1clk = (l2clk & l1en) | se; | |
4159 | `else | |
4160 | `ifdef LIB | |
4161 | reg l1en; | |
4162 | ||
4163 | ||
4164 | ||
4165 | `ifdef SCAN_MODE | |
4166 | always @ (l2clk or stop or pce or pce_ov) | |
4167 | begin | |
4168 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4169 | end | |
4170 | `else | |
4171 | always @ (negedge l2clk ) | |
4172 | begin | |
4173 | l1en <= (~stop & ( pce | pce_ov )); | |
4174 | end | |
4175 | `endif | |
4176 | ||
4177 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4178 | ||
4179 | ||
4180 | `endif | |
4181 | `endif | |
4182 | ||
4183 | endmodule | |
4184 | module cl_a1_l1hdr_32x ( | |
4185 | l2clk, | |
4186 | se, | |
4187 | pce, | |
4188 | pce_ov, | |
4189 | stop, | |
4190 | l1clk | |
4191 | ); | |
4192 | // RFM 05/21/2004 | |
4193 | ||
4194 | ||
4195 | ||
4196 | input l2clk; // level 2 clock, from clock grid | |
4197 | input se; // Scan Enable | |
4198 | input pce; // Clock enable for local power savings | |
4199 | input pce_ov; // TCU sourced clock enable override for testing | |
4200 | input stop; // TCU/CCU sourced clock stop for debug | |
4201 | output l1clk; | |
4202 | `ifdef FORMAL_TOOL | |
4203 | wire l1en = (~stop & ( pce | pce_ov )); | |
4204 | assign l1clk = (l2clk & l1en) | se; | |
4205 | `else | |
4206 | `ifdef LIB | |
4207 | reg l1en; | |
4208 | ||
4209 | ||
4210 | ||
4211 | `ifdef SCAN_MODE | |
4212 | always @ (l2clk or stop or pce or pce_ov) | |
4213 | begin | |
4214 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4215 | end | |
4216 | `else | |
4217 | always @ (negedge l2clk ) | |
4218 | begin | |
4219 | l1en <= (~stop & ( pce | pce_ov )); | |
4220 | end | |
4221 | `endif | |
4222 | ||
4223 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4224 | ||
4225 | ||
4226 | ||
4227 | `endif | |
4228 | `endif | |
4229 | ||
4230 | endmodule | |
4231 | ||
4232 | module cl_a1_l1hdr_4x ( | |
4233 | l2clk, | |
4234 | se, | |
4235 | pce, | |
4236 | pce_ov, | |
4237 | stop, | |
4238 | l1clk | |
4239 | ); | |
4240 | // RFM 05/21/2004 | |
4241 | ||
4242 | ||
4243 | ||
4244 | input l2clk; // level 2 clock, from clock grid | |
4245 | input se; // Scan Enable | |
4246 | input pce; // Clock enable for local power savings | |
4247 | input pce_ov; // TCU sourced clock enable override for testing | |
4248 | input stop; // TCU/CCU sourced clock stop for debug | |
4249 | output l1clk; | |
4250 | `ifdef FORMAL_TOOL | |
4251 | wire l1en = (~stop & ( pce | pce_ov )); | |
4252 | assign l1clk = (l2clk & l1en) | se; | |
4253 | `else | |
4254 | `ifdef LIB | |
4255 | reg l1en; | |
4256 | ||
4257 | ||
4258 | ||
4259 | `ifdef SCAN_MODE | |
4260 | always @ (l2clk or stop or pce or pce_ov) | |
4261 | begin | |
4262 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4263 | end | |
4264 | `else | |
4265 | always @ (negedge l2clk ) | |
4266 | begin | |
4267 | l1en <= (~stop & ( pce | pce_ov )); | |
4268 | end | |
4269 | `endif | |
4270 | ||
4271 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4272 | ||
4273 | ||
4274 | ||
4275 | `endif | |
4276 | `endif | |
4277 | ||
4278 | endmodule | |
4279 | module cl_a1_l1hdr_48x ( | |
4280 | l2clk, | |
4281 | se, | |
4282 | pce, | |
4283 | pce_ov, | |
4284 | stop, | |
4285 | l1clk | |
4286 | ||
4287 | ); | |
4288 | ||
4289 | ||
4290 | ||
4291 | ||
4292 | input l2clk; // level 2 clock, from clock grid | |
4293 | input se; // Scan Enable | |
4294 | input pce; // Clock enable for local power savings | |
4295 | input pce_ov; // TCU sourced clock enable override for testing | |
4296 | input stop; // TCU/CCU sourced clock stop for debug | |
4297 | output l1clk; | |
4298 | `ifdef FORMAL_TOOL | |
4299 | wire l1en = (~stop & ( pce | pce_ov )); | |
4300 | assign l1clk = (l2clk & l1en) | se; | |
4301 | `else | |
4302 | `ifdef LIB | |
4303 | reg l1en; | |
4304 | ||
4305 | ||
4306 | ||
4307 | `ifdef SCAN_MODE | |
4308 | always @ (l2clk or stop or pce or pce_ov) | |
4309 | begin | |
4310 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4311 | end | |
4312 | `else | |
4313 | always @ (negedge l2clk ) | |
4314 | begin | |
4315 | l1en <= (~stop & ( pce | pce_ov )); | |
4316 | end | |
4317 | `endif | |
4318 | ||
4319 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4320 | ||
4321 | ||
4322 | ||
4323 | `endif | |
4324 | `endif | |
4325 | ||
4326 | endmodule | |
4327 | module cl_a1_l1hdr_64x ( | |
4328 | l2clk, | |
4329 | se, | |
4330 | pce, | |
4331 | pce_ov, | |
4332 | stop, | |
4333 | l1clk | |
4334 | ||
4335 | ); | |
4336 | ||
4337 | ||
4338 | ||
4339 | ||
4340 | input l2clk; // level 2 clock, from clock grid | |
4341 | input se; // Scan Enable | |
4342 | input pce; // Clock enable for local power savings | |
4343 | input pce_ov; // TCU sourced clock enable override for testing | |
4344 | input stop; // TCU/CCU sourced clock stop for debug | |
4345 | output l1clk; | |
4346 | `ifdef FORMAL_TOOL | |
4347 | wire l1en = (~stop & ( pce | pce_ov )); | |
4348 | assign l1clk = (l2clk & l1en) | se; | |
4349 | `else | |
4350 | `ifdef LIB | |
4351 | reg l1en; | |
4352 | ||
4353 | ||
4354 | ||
4355 | `ifdef SCAN_MODE | |
4356 | always @ (l2clk or stop or pce or pce_ov) | |
4357 | begin | |
4358 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4359 | end | |
4360 | `else | |
4361 | always @ (negedge l2clk ) | |
4362 | begin | |
4363 | l1en <= (~stop & ( pce | pce_ov )); | |
4364 | end | |
4365 | `endif | |
4366 | ||
4367 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4368 | ||
4369 | ||
4370 | ||
4371 | `endif | |
4372 | `endif | |
4373 | ||
4374 | endmodule | |
4375 | module cl_a1_l1hdr_8x ( | |
4376 | l2clk, | |
4377 | se, | |
4378 | pce, | |
4379 | pce_ov, | |
4380 | stop, | |
4381 | l1clk | |
4382 | ); | |
4383 | // RFM 05/21/2004 | |
4384 | ||
4385 | ||
4386 | ||
4387 | input l2clk; // level 2 clock, from clock grid | |
4388 | input se; // Scan Enable | |
4389 | input pce; // Clock enable for local power savings | |
4390 | input pce_ov; // TCU sourced clock enable override for testing | |
4391 | input stop; // TCU/CCU sourced clock stop for debug | |
4392 | output l1clk; | |
4393 | `ifdef FORMAL_TOOL | |
4394 | wire l1en = (~stop & ( pce | pce_ov )); | |
4395 | assign l1clk = (l2clk & l1en) | se; | |
4396 | `else | |
4397 | `ifdef LIB | |
4398 | reg l1en; | |
4399 | ||
4400 | ||
4401 | `ifdef SCAN_MODE | |
4402 | always @ (l2clk or stop or pce or pce_ov) | |
4403 | begin | |
4404 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
4405 | end | |
4406 | `else | |
4407 | always @ (negedge l2clk ) | |
4408 | begin | |
4409 | l1en <= (~stop & ( pce | pce_ov )); | |
4410 | end | |
4411 | `endif | |
4412 | ||
4413 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
4414 | ||
4415 | ||
4416 | ||
4417 | `endif | |
4418 | `endif | |
4419 | ||
4420 | endmodule | |
4421 | ||
4422 | module cl_a1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
4423 | // RFM 05-14-2004 | |
4424 | // Level sensitive in SCAN_MODE | |
4425 | // Edge triggered when not in SCAN_MODE | |
4426 | ||
4427 | ||
4428 | parameter SIZE = 1; | |
4429 | ||
4430 | output q; | |
4431 | output so; | |
4432 | ||
4433 | input d; | |
4434 | input l1clk; | |
4435 | input si; | |
4436 | input siclk; | |
4437 | input soclk; | |
4438 | ||
4439 | reg q; | |
4440 | wire so; | |
4441 | wire l1clk, siclk, soclk; | |
4442 | ||
4443 | `ifdef SCAN_MODE | |
4444 | ||
4445 | reg l1; | |
4446 | `ifdef FAST_FLUSH | |
4447 | always @(posedge l1clk or posedge siclk ) begin | |
4448 | if (siclk) begin | |
4449 | q <= 1'b0; //pseudo flush reset | |
4450 | end else begin | |
4451 | q <= d; | |
4452 | end | |
4453 | end | |
4454 | `else | |
4455 | always @(l1clk or siclk or soclk or d or si) | |
4456 | begin | |
4457 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4458 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4459 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4460 | ||
4461 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4462 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4463 | end | |
4464 | `endif | |
4465 | `else | |
4466 | wire si_unused; | |
4467 | wire siclk_unused; | |
4468 | wire soclk_unused; | |
4469 | assign si_unused = si; | |
4470 | assign siclk_unused = siclk; | |
4471 | assign soclk_unused = soclk; | |
4472 | ||
4473 | ||
4474 | `ifdef INITLATZERO | |
4475 | initial q = 1'b0; | |
4476 | `endif | |
4477 | ||
4478 | always @(posedge l1clk) | |
4479 | begin | |
4480 | if (!siclk && !soclk) q <= d; | |
4481 | else q <= 1'bx; | |
4482 | end | |
4483 | `endif | |
4484 | ||
4485 | assign so = q; | |
4486 | ||
4487 | endmodule // dff | |
4488 | ||
4489 | ||
4490 | ||
4491 | ||
4492 | module cl_a1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
4493 | // RFM 05-14-2004 | |
4494 | // Level sensitive in SCAN_MODE | |
4495 | // Edge triggered when not in SCAN_MODE | |
4496 | ||
4497 | ||
4498 | parameter SIZE = 1; | |
4499 | ||
4500 | output q; | |
4501 | output so; | |
4502 | ||
4503 | input d; | |
4504 | input l1clk; | |
4505 | input si; | |
4506 | input siclk; | |
4507 | input soclk; | |
4508 | ||
4509 | reg q; | |
4510 | wire so; | |
4511 | wire l1clk, siclk, soclk; | |
4512 | ||
4513 | `ifdef SCAN_MODE | |
4514 | `ifdef FAST_FLUSH | |
4515 | always @(posedge l1clk or posedge siclk ) begin | |
4516 | if (siclk) begin | |
4517 | q <= 1'b0; //pseudo flush reset | |
4518 | end else begin | |
4519 | q <= d; | |
4520 | end | |
4521 | end | |
4522 | `else | |
4523 | reg l1; | |
4524 | ||
4525 | always @(l1clk or siclk or soclk or d or si) | |
4526 | begin | |
4527 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4528 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4529 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4530 | ||
4531 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4532 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4533 | end | |
4534 | `endif | |
4535 | `else | |
4536 | wire si_unused; | |
4537 | wire siclk_unused; | |
4538 | wire soclk_unused; | |
4539 | assign si_unused = si; | |
4540 | assign siclk_unused = siclk; | |
4541 | assign soclk_unused = soclk; | |
4542 | ||
4543 | ||
4544 | `ifdef INITLATZERO | |
4545 | initial q = 1'b0; | |
4546 | `endif | |
4547 | ||
4548 | always @(posedge l1clk) | |
4549 | begin | |
4550 | if (!siclk && !soclk) q <= d; | |
4551 | else q <= 1'bx; | |
4552 | end | |
4553 | `endif | |
4554 | ||
4555 | assign so = q; | |
4556 | ||
4557 | endmodule // dff | |
4558 | module cl_a1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
4559 | // RFM 05-14-2004 | |
4560 | // Level sensitive in SCAN_MODE | |
4561 | // Edge triggered when not in SCAN_MODE | |
4562 | ||
4563 | ||
4564 | parameter SIZE = 1; | |
4565 | ||
4566 | output q; | |
4567 | output so; | |
4568 | ||
4569 | input d; | |
4570 | input l1clk; | |
4571 | input si; | |
4572 | input siclk; | |
4573 | input soclk; | |
4574 | ||
4575 | reg q; | |
4576 | wire so; | |
4577 | wire l1clk, siclk, soclk; | |
4578 | ||
4579 | `ifdef SCAN_MODE | |
4580 | ||
4581 | reg l1; | |
4582 | `ifdef FAST_FLUSH | |
4583 | always @(posedge l1clk or posedge siclk ) begin | |
4584 | if (siclk) begin | |
4585 | q <= 1'b0; //pseudo flush reset | |
4586 | end else begin | |
4587 | q <= d; | |
4588 | end | |
4589 | end | |
4590 | `else | |
4591 | always @(l1clk or siclk or soclk or d or si) | |
4592 | begin | |
4593 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4594 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4595 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4596 | ||
4597 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4598 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4599 | end | |
4600 | `endif | |
4601 | `else | |
4602 | wire si_unused; | |
4603 | wire siclk_unused; | |
4604 | wire soclk_unused; | |
4605 | assign si_unused = si; | |
4606 | assign siclk_unused = siclk; | |
4607 | assign soclk_unused = soclk; | |
4608 | ||
4609 | ||
4610 | `ifdef INITLATZERO | |
4611 | initial q = 1'b0; | |
4612 | `endif | |
4613 | ||
4614 | always @(posedge l1clk) | |
4615 | begin | |
4616 | if (!siclk && !soclk) q <= d; | |
4617 | else q <= 1'bx; | |
4618 | end | |
4619 | `endif | |
4620 | ||
4621 | assign so = q; | |
4622 | ||
4623 | endmodule // dff | |
4624 | module cl_a1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
4625 | // RFM 05-14-2004 | |
4626 | // Level sensitive in SCAN_MODE | |
4627 | // Edge triggered when not in SCAN_MODE | |
4628 | ||
4629 | ||
4630 | parameter SIZE = 1; | |
4631 | ||
4632 | output q; | |
4633 | output so; | |
4634 | ||
4635 | input d; | |
4636 | input l1clk; | |
4637 | input si; | |
4638 | input siclk; | |
4639 | input soclk; | |
4640 | ||
4641 | reg q; | |
4642 | wire so; | |
4643 | wire l1clk, siclk, soclk; | |
4644 | ||
4645 | `ifdef SCAN_MODE | |
4646 | ||
4647 | reg l1; | |
4648 | `ifdef FAST_FLUSH | |
4649 | always @(posedge l1clk or posedge siclk ) begin | |
4650 | if (siclk) begin | |
4651 | q <= 1'b0; //pseudo flush reset | |
4652 | end else begin | |
4653 | q <= d; | |
4654 | end | |
4655 | end | |
4656 | `else | |
4657 | always @(l1clk or siclk or soclk or d or si) | |
4658 | begin | |
4659 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4660 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4661 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4662 | ||
4663 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4664 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4665 | end | |
4666 | `endif | |
4667 | `else | |
4668 | wire si_unused; | |
4669 | wire siclk_unused; | |
4670 | wire soclk_unused; | |
4671 | assign si_unused = si; | |
4672 | assign siclk_unused = siclk; | |
4673 | assign soclk_unused = soclk; | |
4674 | ||
4675 | ||
4676 | `ifdef INITLATZERO | |
4677 | initial q = 1'b0; | |
4678 | `endif | |
4679 | ||
4680 | always @(posedge l1clk) | |
4681 | begin | |
4682 | if (!siclk && !soclk) q <= d; | |
4683 | else q <= 1'bx; | |
4684 | end | |
4685 | `endif | |
4686 | ||
4687 | assign so = q; | |
4688 | ||
4689 | endmodule // dff | |
4690 | module cl_a1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
4691 | // RFM 05-14-2004 | |
4692 | // Level sensitive in SCAN_MODE | |
4693 | // Edge triggered when not in SCAN_MODE | |
4694 | ||
4695 | ||
4696 | parameter SIZE = 1; | |
4697 | ||
4698 | output q; | |
4699 | output so; | |
4700 | ||
4701 | input d; | |
4702 | input l1clk; | |
4703 | input si; | |
4704 | input siclk; | |
4705 | input soclk; | |
4706 | ||
4707 | reg q; | |
4708 | wire so; | |
4709 | wire l1clk, siclk, soclk; | |
4710 | ||
4711 | `ifdef SCAN_MODE | |
4712 | ||
4713 | reg l1; | |
4714 | `ifdef FAST_FLUSH | |
4715 | always @(posedge l1clk or posedge siclk ) begin | |
4716 | if (siclk) begin | |
4717 | q <= 1'b0; //pseudo flush reset | |
4718 | end else begin | |
4719 | q <= d; | |
4720 | end | |
4721 | end | |
4722 | `else | |
4723 | always @(l1clk or siclk or soclk or d or si) | |
4724 | begin | |
4725 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4726 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4727 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4728 | ||
4729 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4730 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4731 | end | |
4732 | `endif | |
4733 | `else | |
4734 | wire si_unused; | |
4735 | wire siclk_unused; | |
4736 | wire soclk_unused; | |
4737 | assign si_unused = si; | |
4738 | assign siclk_unused = siclk; | |
4739 | assign soclk_unused = soclk; | |
4740 | ||
4741 | ||
4742 | `ifdef INITLATZERO | |
4743 | initial q = 1'b0; | |
4744 | `endif | |
4745 | ||
4746 | always @(posedge l1clk) | |
4747 | begin | |
4748 | if (!siclk && !soclk) q <= d; | |
4749 | else q <= 1'bx; | |
4750 | end | |
4751 | `endif | |
4752 | ||
4753 | assign so = q; | |
4754 | ||
4755 | endmodule // dff | |
4756 | module cl_a1_msff_lp_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
4757 | // RFM 05-14-2004 | |
4758 | // Level sensitive in SCAN_MODE | |
4759 | // Edge triggered when not in SCAN_MODE | |
4760 | ||
4761 | ||
4762 | parameter SIZE = 1; | |
4763 | ||
4764 | output q; | |
4765 | output so; | |
4766 | ||
4767 | input d; | |
4768 | input l1clk; | |
4769 | input si; | |
4770 | input siclk; | |
4771 | input soclk; | |
4772 | ||
4773 | reg q; | |
4774 | wire so; | |
4775 | wire l1clk, siclk, soclk; | |
4776 | ||
4777 | `ifdef SCAN_MODE | |
4778 | ||
4779 | reg l1; | |
4780 | `ifdef FAST_FLUSH | |
4781 | always @(posedge l1clk or posedge siclk ) begin | |
4782 | if (siclk) begin | |
4783 | q <= 1'b0; //pseudo flush reset | |
4784 | end else begin | |
4785 | q <= d; | |
4786 | end | |
4787 | end | |
4788 | `else | |
4789 | always @(l1clk or siclk or soclk or d or si) | |
4790 | begin | |
4791 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4792 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4793 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4794 | ||
4795 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4796 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4797 | end | |
4798 | `endif | |
4799 | `else | |
4800 | wire si_unused; | |
4801 | wire siclk_unused; | |
4802 | wire soclk_unused; | |
4803 | assign si_unused = si; | |
4804 | assign siclk_unused = siclk; | |
4805 | assign soclk_unused = soclk; | |
4806 | ||
4807 | ||
4808 | `ifdef INITLATZERO | |
4809 | initial q = 1'b0; | |
4810 | `endif | |
4811 | ||
4812 | always @(posedge l1clk) | |
4813 | begin | |
4814 | if (!siclk && !soclk) q <= d; | |
4815 | else q <= 1'bx; | |
4816 | end | |
4817 | `endif | |
4818 | ||
4819 | assign so = q; | |
4820 | ||
4821 | endmodule // dff | |
4822 | ||
4823 | ||
4824 | module cl_a1_msff_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
4825 | // RFM 05-14-2004 | |
4826 | // Level sensitive in SCAN_MODE | |
4827 | // Edge triggered when not in SCAN_MODE | |
4828 | ||
4829 | ||
4830 | parameter SIZE = 1; | |
4831 | ||
4832 | output q; | |
4833 | output so; | |
4834 | ||
4835 | input d; | |
4836 | input l1clk; | |
4837 | input si; | |
4838 | input siclk; | |
4839 | input soclk; | |
4840 | ||
4841 | reg q; | |
4842 | wire so; | |
4843 | wire l1clk, siclk, soclk; | |
4844 | ||
4845 | `ifdef SCAN_MODE | |
4846 | ||
4847 | reg l1; | |
4848 | `ifdef FAST_FLUSH | |
4849 | always @(posedge l1clk or posedge siclk ) begin | |
4850 | if (siclk) begin | |
4851 | q <= 1'b0; //pseudo flush reset | |
4852 | end else begin | |
4853 | q <= d; | |
4854 | end | |
4855 | end | |
4856 | `else | |
4857 | always @(l1clk or siclk or soclk or d or si) | |
4858 | begin | |
4859 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4860 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4861 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4862 | ||
4863 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4864 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4865 | end | |
4866 | `endif | |
4867 | `else | |
4868 | wire si_unused; | |
4869 | wire siclk_unused; | |
4870 | wire soclk_unused; | |
4871 | assign si_unused = si; | |
4872 | assign siclk_unused = siclk; | |
4873 | assign soclk_unused = soclk; | |
4874 | ||
4875 | ||
4876 | `ifdef INITLATZERO | |
4877 | initial q = 1'b0; | |
4878 | `endif | |
4879 | ||
4880 | always @(posedge l1clk) | |
4881 | begin | |
4882 | if (!siclk && !soclk) q <= d; | |
4883 | else q <= 1'bx; | |
4884 | end | |
4885 | `endif | |
4886 | ||
4887 | assign so = q; | |
4888 | ||
4889 | endmodule // dff | |
4890 | module cl_a1_msff_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
4891 | // RFM 05-14-2004 | |
4892 | // Level sensitive in SCAN_MODE | |
4893 | // Edge triggered when not in SCAN_MODE | |
4894 | ||
4895 | ||
4896 | parameter SIZE = 1; | |
4897 | ||
4898 | output q; | |
4899 | output so; | |
4900 | ||
4901 | input d; | |
4902 | input l1clk; | |
4903 | input si; | |
4904 | input siclk; | |
4905 | input soclk; | |
4906 | ||
4907 | reg q; | |
4908 | wire so; | |
4909 | wire l1clk, siclk, soclk; | |
4910 | ||
4911 | `ifdef SCAN_MODE | |
4912 | reg l1; | |
4913 | `ifdef FAST_FLUSH | |
4914 | always @(posedge l1clk or posedge siclk ) begin | |
4915 | if (siclk) begin | |
4916 | q <= 1'b0; //pseudo flush reset | |
4917 | end else begin | |
4918 | q <= d; | |
4919 | end | |
4920 | end | |
4921 | `else | |
4922 | always @(l1clk or siclk or soclk or d or si) | |
4923 | begin | |
4924 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4925 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4926 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4927 | ||
4928 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4929 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4930 | end | |
4931 | `endif | |
4932 | `else | |
4933 | wire si_unused; | |
4934 | wire siclk_unused; | |
4935 | wire soclk_unused; | |
4936 | assign si_unused = si; | |
4937 | assign siclk_unused = siclk; | |
4938 | assign soclk_unused = soclk; | |
4939 | ||
4940 | ||
4941 | `ifdef INITLATZERO | |
4942 | initial q = 1'b0; | |
4943 | `endif | |
4944 | ||
4945 | always @(posedge l1clk) | |
4946 | begin | |
4947 | if (!siclk && !soclk) q <= d; | |
4948 | else q <= 1'bx; | |
4949 | end | |
4950 | `endif | |
4951 | ||
4952 | assign so = q; | |
4953 | ||
4954 | endmodule // dff | |
4955 | ||
4956 | ||
4957 | module cl_a1_msff_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
4958 | // RFM 05-14-2004 | |
4959 | // Level sensitive in SCAN_MODE | |
4960 | // Edge triggered when not in SCAN_MODE | |
4961 | ||
4962 | ||
4963 | parameter SIZE = 1; | |
4964 | ||
4965 | output q; | |
4966 | output so; | |
4967 | ||
4968 | input d; | |
4969 | input l1clk; | |
4970 | input si; | |
4971 | input siclk; | |
4972 | input soclk; | |
4973 | ||
4974 | reg q; | |
4975 | wire so; | |
4976 | wire l1clk, siclk, soclk; | |
4977 | ||
4978 | `ifdef SCAN_MODE | |
4979 | reg l1; | |
4980 | `ifdef FAST_FLUSH | |
4981 | always @(posedge l1clk or posedge siclk ) begin | |
4982 | if (siclk) begin | |
4983 | q <= 1'b0; //pseudo flush reset | |
4984 | end else begin | |
4985 | q <= d; | |
4986 | end | |
4987 | end | |
4988 | `else | |
4989 | ||
4990 | always @(l1clk or siclk or soclk or d or si) | |
4991 | begin | |
4992 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
4993 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
4994 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
4995 | ||
4996 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
4997 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
4998 | end | |
4999 | `endif | |
5000 | `else | |
5001 | wire si_unused; | |
5002 | wire siclk_unused; | |
5003 | wire soclk_unused; | |
5004 | assign si_unused = si; | |
5005 | assign siclk_unused = siclk; | |
5006 | assign soclk_unused = soclk; | |
5007 | ||
5008 | ||
5009 | `ifdef INITLATZERO | |
5010 | initial q = 1'b0; | |
5011 | `endif | |
5012 | ||
5013 | always @(posedge l1clk) | |
5014 | begin | |
5015 | if (!siclk && !soclk) q <= d; | |
5016 | else q <= 1'bx; | |
5017 | end | |
5018 | `endif | |
5019 | ||
5020 | assign so = q; | |
5021 | ||
5022 | endmodule // dff | |
5023 | module cl_a1_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
5024 | // RFM 05-14-2004 | |
5025 | // Level sensitive in SCAN_MODE | |
5026 | // Edge triggered when not in SCAN_MODE | |
5027 | ||
5028 | ||
5029 | parameter SIZE = 1; | |
5030 | ||
5031 | output q; | |
5032 | output so; | |
5033 | ||
5034 | input d; | |
5035 | input l1clk; | |
5036 | input si; | |
5037 | input siclk; | |
5038 | input soclk; | |
5039 | ||
5040 | reg q; | |
5041 | wire so; | |
5042 | wire l1clk, siclk, soclk; | |
5043 | ||
5044 | `ifdef SCAN_MODE | |
5045 | ||
5046 | reg l1; | |
5047 | `ifdef FAST_FLUSH | |
5048 | always @(posedge l1clk or posedge siclk ) begin | |
5049 | if (siclk) begin | |
5050 | q <= 1'b0; //pseudo flush reset | |
5051 | end else begin | |
5052 | q <= d; | |
5053 | end | |
5054 | end | |
5055 | `else | |
5056 | always @(l1clk or siclk or soclk or d or si) | |
5057 | begin | |
5058 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5059 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5060 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5061 | ||
5062 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5063 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5064 | end | |
5065 | `endif | |
5066 | `else | |
5067 | wire si_unused; | |
5068 | wire siclk_unused; | |
5069 | wire soclk_unused; | |
5070 | assign si_unused = si; | |
5071 | assign siclk_unused = siclk; | |
5072 | assign soclk_unused = soclk; | |
5073 | ||
5074 | ||
5075 | `ifdef INITLATZERO | |
5076 | initial q = 1'b0; | |
5077 | `endif | |
5078 | ||
5079 | always @(posedge l1clk) | |
5080 | begin | |
5081 | if (!siclk && !soclk) q <= d; | |
5082 | else q <= 1'bx; | |
5083 | end | |
5084 | `endif | |
5085 | ||
5086 | assign so = q; | |
5087 | ||
5088 | endmodule // dff | |
5089 | module cl_a1_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
5090 | // RFM 05-14-2004 | |
5091 | // Level sensitive in SCAN_MODE | |
5092 | // Edge triggered when not in SCAN_MODE | |
5093 | ||
5094 | ||
5095 | parameter SIZE = 1; | |
5096 | ||
5097 | output q; | |
5098 | output so; | |
5099 | ||
5100 | input d; | |
5101 | input l1clk; | |
5102 | input si; | |
5103 | input siclk; | |
5104 | input soclk; | |
5105 | ||
5106 | reg q; | |
5107 | wire so; | |
5108 | wire l1clk, siclk, soclk; | |
5109 | ||
5110 | `ifdef SCAN_MODE | |
5111 | reg l1; | |
5112 | `ifdef FAST_FLUSH | |
5113 | always @(posedge l1clk or posedge siclk ) begin | |
5114 | if (siclk) begin | |
5115 | q <= 1'b0; //pseudo flush reset | |
5116 | end else begin | |
5117 | q <= d; | |
5118 | end | |
5119 | end | |
5120 | `else | |
5121 | ||
5122 | always @(l1clk or siclk or soclk or d or si) | |
5123 | begin | |
5124 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5125 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5126 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5127 | ||
5128 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5129 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5130 | end | |
5131 | `endif | |
5132 | `else | |
5133 | wire si_unused; | |
5134 | wire siclk_unused; | |
5135 | wire soclk_unused; | |
5136 | assign si_unused = si; | |
5137 | assign siclk_unused = siclk; | |
5138 | assign soclk_unused = soclk; | |
5139 | ||
5140 | ||
5141 | `ifdef INITLATZERO | |
5142 | initial q = 1'b0; | |
5143 | `endif | |
5144 | ||
5145 | always @(posedge l1clk) | |
5146 | begin | |
5147 | if (!siclk && !soclk) q <= d; | |
5148 | else q <= 1'bx; | |
5149 | end | |
5150 | `endif | |
5151 | ||
5152 | assign so = q; | |
5153 | ||
5154 | endmodule // dff | |
5155 | ||
5156 | module cl_a1_msff_syrst_1x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5157 | // RFM 05-14-2004 | |
5158 | // Level sensitive in SCAN_MODE | |
5159 | // Edge triggered when not in SCAN_MODE | |
5160 | ||
5161 | ||
5162 | parameter SIZE = 1; | |
5163 | ||
5164 | output q; | |
5165 | output so; | |
5166 | ||
5167 | input d; | |
5168 | input l1clk; | |
5169 | input si; | |
5170 | input siclk; | |
5171 | input soclk; | |
5172 | input reset; | |
5173 | reg q; | |
5174 | wire so; | |
5175 | wire l1clk, siclk, soclk; | |
5176 | ||
5177 | `ifdef SCAN_MODE | |
5178 | reg l1; | |
5179 | `ifdef FAST_FLUSH | |
5180 | always @(l1clk or siclk or d ) // vcs optimized code | |
5181 | begin | |
5182 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5183 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5184 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5185 | l1 <= 1'b0; | |
5186 | q <= 1'b0; | |
5187 | end | |
5188 | end | |
5189 | `else | |
5190 | always @(l1clk or siclk or soclk or d or si) | |
5191 | begin | |
5192 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5193 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5194 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5195 | ||
5196 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5197 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5198 | end | |
5199 | `endif | |
5200 | `else | |
5201 | wire si_unused; | |
5202 | wire siclk_unused; | |
5203 | wire soclk_unused; | |
5204 | assign si_unused = si; | |
5205 | assign siclk_unused = siclk; | |
5206 | assign soclk_unused = soclk; | |
5207 | ||
5208 | ||
5209 | `ifdef INITLATZERO | |
5210 | initial q = 1'b0; | |
5211 | `endif | |
5212 | ||
5213 | always @(posedge l1clk) | |
5214 | begin | |
5215 | if (!siclk && !soclk) q <= (d&reset); | |
5216 | else q <= 1'bx; | |
5217 | end | |
5218 | `endif | |
5219 | ||
5220 | assign so = q; | |
5221 | ||
5222 | endmodule // dff | |
5223 | module cl_a1_msff_syrst_4x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5224 | // RFM 05-14-2004 | |
5225 | // Level sensitive in SCAN_MODE | |
5226 | // Edge triggered when not in SCAN_MODE | |
5227 | ||
5228 | ||
5229 | parameter SIZE = 1; | |
5230 | ||
5231 | output q; | |
5232 | output so; | |
5233 | ||
5234 | input d; | |
5235 | input l1clk; | |
5236 | input si; | |
5237 | input siclk; | |
5238 | input soclk; | |
5239 | input reset; | |
5240 | reg q; | |
5241 | wire so; | |
5242 | wire l1clk, siclk, soclk; | |
5243 | ||
5244 | `ifdef SCAN_MODE | |
5245 | ||
5246 | reg l1; | |
5247 | `ifdef FAST_FLUSH | |
5248 | always @(l1clk or siclk or d ) // vcs optimized code | |
5249 | begin | |
5250 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5251 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5252 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5253 | l1 <= 1'b0; | |
5254 | q <= 1'b0; | |
5255 | end | |
5256 | end | |
5257 | `else | |
5258 | always @(l1clk or siclk or soclk or d or si) | |
5259 | begin | |
5260 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5261 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5262 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5263 | ||
5264 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5265 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5266 | end | |
5267 | `endif | |
5268 | `else | |
5269 | wire si_unused; | |
5270 | wire siclk_unused; | |
5271 | wire soclk_unused; | |
5272 | assign si_unused = si; | |
5273 | assign siclk_unused = siclk; | |
5274 | assign soclk_unused = soclk; | |
5275 | ||
5276 | ||
5277 | `ifdef INITLATZERO | |
5278 | initial q = 1'b0; | |
5279 | `endif | |
5280 | ||
5281 | always @(posedge l1clk) | |
5282 | begin | |
5283 | if (!siclk && !soclk) q <= (d&reset); | |
5284 | else q <= 1'bx; | |
5285 | end | |
5286 | `endif | |
5287 | ||
5288 | assign so = q; | |
5289 | ||
5290 | endmodule // dff | |
5291 | module cl_a1_msff_syrst_8x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5292 | // RFM 05-14-2004 | |
5293 | // Level sensitive in SCAN_MODE | |
5294 | // Edge triggered when not in SCAN_MODE | |
5295 | ||
5296 | ||
5297 | parameter SIZE = 1; | |
5298 | ||
5299 | output q; | |
5300 | output so; | |
5301 | ||
5302 | input d; | |
5303 | input l1clk; | |
5304 | input si; | |
5305 | input siclk; | |
5306 | input soclk; | |
5307 | input reset; | |
5308 | reg q; | |
5309 | wire so; | |
5310 | wire l1clk, siclk, soclk; | |
5311 | ||
5312 | `ifdef SCAN_MODE | |
5313 | ||
5314 | reg l1; | |
5315 | `ifdef FAST_FLUSH | |
5316 | always @(l1clk or siclk or d ) // vcs optimized code | |
5317 | begin | |
5318 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5319 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5320 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5321 | l1 <= 1'b0; | |
5322 | q <= 1'b0; | |
5323 | end | |
5324 | end | |
5325 | `else | |
5326 | always @(l1clk or siclk or soclk or d or si) | |
5327 | begin | |
5328 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5329 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5330 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5331 | ||
5332 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5333 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5334 | end | |
5335 | `endif | |
5336 | `else | |
5337 | wire si_unused; | |
5338 | wire siclk_unused; | |
5339 | wire soclk_unused; | |
5340 | assign si_unused = si; | |
5341 | assign siclk_unused = siclk; | |
5342 | assign soclk_unused = soclk; | |
5343 | ||
5344 | ||
5345 | `ifdef INITLATZERO | |
5346 | initial q = 1'b0; | |
5347 | `endif | |
5348 | ||
5349 | always @(posedge l1clk) | |
5350 | begin | |
5351 | if (!siclk && !soclk) q <= (d&reset); | |
5352 | else q <= 1'bx; | |
5353 | end | |
5354 | `endif | |
5355 | ||
5356 | assign so = q; | |
5357 | ||
5358 | endmodule // dff | |
5359 | module cl_a1_msff_syrst_16x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5360 | // RFM 05-14-2004 | |
5361 | // Level sensitive in SCAN_MODE | |
5362 | // Edge triggered when not in SCAN_MODE | |
5363 | ||
5364 | ||
5365 | parameter SIZE = 1; | |
5366 | ||
5367 | output q; | |
5368 | output so; | |
5369 | ||
5370 | input d; | |
5371 | input l1clk; | |
5372 | input si; | |
5373 | input siclk; | |
5374 | input soclk; | |
5375 | input reset; | |
5376 | reg q; | |
5377 | wire so; | |
5378 | wire l1clk, siclk, soclk; | |
5379 | ||
5380 | `ifdef SCAN_MODE | |
5381 | ||
5382 | reg l1; | |
5383 | `ifdef FAST_FLUSH | |
5384 | always @(l1clk or siclk or d ) // vcs optimized code | |
5385 | begin | |
5386 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5387 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5388 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5389 | l1 <= 1'b0; | |
5390 | q <= 1'b0; | |
5391 | end | |
5392 | end | |
5393 | `else | |
5394 | always @(l1clk or siclk or soclk or d or si) | |
5395 | begin | |
5396 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5397 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5398 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5399 | ||
5400 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5401 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5402 | end | |
5403 | `endif | |
5404 | `else | |
5405 | wire si_unused; | |
5406 | wire siclk_unused; | |
5407 | wire soclk_unused; | |
5408 | assign si_unused = si; | |
5409 | assign siclk_unused = siclk; | |
5410 | assign soclk_unused = soclk; | |
5411 | ||
5412 | ||
5413 | `ifdef INITLATZERO | |
5414 | initial q = 1'b0; | |
5415 | `endif | |
5416 | ||
5417 | always @(posedge l1clk) | |
5418 | begin | |
5419 | if (!siclk && !soclk) q <= (d&reset); | |
5420 | else q <= 1'bx; | |
5421 | end | |
5422 | `endif | |
5423 | ||
5424 | assign so = q; | |
5425 | ||
5426 | endmodule // dff | |
5427 | module cl_a1_msff_syrst_32x ( q, so, d, l1clk, si, siclk, soclk,reset ); | |
5428 | // RFM 05-14-2004 | |
5429 | // Level sensitive in SCAN_MODE | |
5430 | // Edge triggered when not in SCAN_MODE | |
5431 | ||
5432 | ||
5433 | parameter SIZE = 1; | |
5434 | ||
5435 | output q; | |
5436 | output so; | |
5437 | ||
5438 | input d; | |
5439 | input l1clk; | |
5440 | input si; | |
5441 | input siclk; | |
5442 | input soclk; | |
5443 | input reset; | |
5444 | reg q; | |
5445 | wire so; | |
5446 | wire l1clk, siclk, soclk; | |
5447 | ||
5448 | `ifdef SCAN_MODE | |
5449 | ||
5450 | reg l1; | |
5451 | `ifdef FAST_FLUSH | |
5452 | always @(l1clk or siclk or d ) // vcs optimized code | |
5453 | begin | |
5454 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5455 | else if ( l1clk && !siclk) q <= l1; // Load slave with master data | |
5456 | else if ( l1clk && siclk) begin // Conflict between data and scan | |
5457 | l1 <= 1'b0; | |
5458 | q <= 1'b0; | |
5459 | end | |
5460 | end | |
5461 | `else | |
5462 | always @(l1clk or siclk or soclk or d or si) | |
5463 | begin | |
5464 | if (!l1clk && !siclk) l1 <= (d&reset); // Load master with data | |
5465 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5466 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5467 | ||
5468 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5469 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5470 | end | |
5471 | `endif | |
5472 | `else | |
5473 | wire si_unused; | |
5474 | wire siclk_unused; | |
5475 | wire soclk_unused; | |
5476 | assign si_unused = si; | |
5477 | assign siclk_unused = siclk; | |
5478 | assign soclk_unused = soclk; | |
5479 | ||
5480 | ||
5481 | `ifdef INITLATZERO | |
5482 | initial q = 1'b0; | |
5483 | `endif | |
5484 | ||
5485 | always @(posedge l1clk) | |
5486 | begin | |
5487 | if (!siclk && !soclk) q <= (d&reset); | |
5488 | else q <= 1'bx; | |
5489 | end | |
5490 | `endif | |
5491 | ||
5492 | assign so = q; | |
5493 | ||
5494 | endmodule // dff | |
5495 | ||
5496 | ||
5497 | module cl_a1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5498 | // RFM 05-14-2004 | |
5499 | // Level sensitive in SCAN_MODE | |
5500 | // Edge triggered when not in SCAN_MODE | |
5501 | ||
5502 | ||
5503 | parameter SIZE = 1; | |
5504 | ||
5505 | output q_l; | |
5506 | output so; | |
5507 | ||
5508 | input d; | |
5509 | input l1clk; | |
5510 | input si; | |
5511 | input siclk; | |
5512 | input soclk; | |
5513 | ||
5514 | reg q_l; | |
5515 | reg q; | |
5516 | wire so; | |
5517 | wire l1clk, siclk, soclk; | |
5518 | ||
5519 | `ifdef SCAN_MODE | |
5520 | reg l1; | |
5521 | `ifdef FAST_FLUSH | |
5522 | always @(posedge l1clk or posedge siclk ) begin | |
5523 | if (siclk) begin | |
5524 | q <= 1'b0; //pseudo flush reset | |
5525 | end else begin | |
5526 | q <= d; | |
5527 | end | |
5528 | end | |
5529 | `else | |
5530 | ||
5531 | always @(l1clk or siclk or soclk or d or si) | |
5532 | begin | |
5533 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5534 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5535 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5536 | ||
5537 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5538 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5539 | end | |
5540 | `endif | |
5541 | `else | |
5542 | wire si_unused; | |
5543 | wire siclk_unused; | |
5544 | wire soclk_unused; | |
5545 | assign si_unused = si; | |
5546 | assign siclk_unused = siclk; | |
5547 | assign soclk_unused = soclk; | |
5548 | ||
5549 | ||
5550 | `ifdef INITLATZERO | |
5551 | initial q_l = 1'b1; | |
5552 | initial q = 1'b0; | |
5553 | `endif | |
5554 | ||
5555 | always @(posedge l1clk) | |
5556 | begin | |
5557 | if (!siclk && !soclk) q <= d; | |
5558 | else q <= 1'bx; | |
5559 | end | |
5560 | `endif | |
5561 | ||
5562 | ||
5563 | always @ (q) | |
5564 | begin | |
5565 | q_l=~q; | |
5566 | end | |
5567 | ||
5568 | ||
5569 | ||
5570 | assign so = q; | |
5571 | ||
5572 | endmodule // dff | |
5573 | ||
5574 | module cl_a1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5575 | // RFM 05-14-2004 | |
5576 | // Level sensitive in SCAN_MODE | |
5577 | // Edge triggered when not in SCAN_MODE | |
5578 | ||
5579 | ||
5580 | parameter SIZE = 1; | |
5581 | ||
5582 | output q_l; | |
5583 | output so; | |
5584 | ||
5585 | input d; | |
5586 | input l1clk; | |
5587 | input si; | |
5588 | input siclk; | |
5589 | input soclk; | |
5590 | ||
5591 | reg q_l; | |
5592 | reg q; | |
5593 | wire so; | |
5594 | wire l1clk, siclk, soclk; | |
5595 | ||
5596 | `ifdef SCAN_MODE | |
5597 | ||
5598 | reg l1; | |
5599 | `ifdef FAST_FLUSH | |
5600 | always @(posedge l1clk or posedge siclk ) begin | |
5601 | if (siclk) begin | |
5602 | q <= 1'b0; //pseudo flush reset | |
5603 | end else begin | |
5604 | q <= d; | |
5605 | end | |
5606 | end | |
5607 | `else | |
5608 | always @(l1clk or siclk or soclk or d or si) | |
5609 | begin | |
5610 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5611 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5612 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5613 | ||
5614 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5615 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5616 | end | |
5617 | `endif | |
5618 | `else | |
5619 | wire si_unused; | |
5620 | wire siclk_unused; | |
5621 | wire soclk_unused; | |
5622 | assign si_unused = si; | |
5623 | assign siclk_unused = siclk; | |
5624 | assign soclk_unused = soclk; | |
5625 | ||
5626 | ||
5627 | `ifdef INITLATZERO | |
5628 | initial q_l = 1'b1; | |
5629 | initial q = 1'b0; | |
5630 | `endif | |
5631 | ||
5632 | always @(posedge l1clk) | |
5633 | begin | |
5634 | if (!siclk && !soclk) q <= d; | |
5635 | else q <= 1'bx; | |
5636 | end | |
5637 | `endif | |
5638 | ||
5639 | ||
5640 | always @ (q) | |
5641 | begin | |
5642 | q_l=~q; | |
5643 | end | |
5644 | ||
5645 | ||
5646 | ||
5647 | assign so = q; | |
5648 | ||
5649 | endmodule // dff | |
5650 | ||
5651 | ||
5652 | module cl_a1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5653 | // RFM 05-14-2004 | |
5654 | // Level sensitive in SCAN_MODE | |
5655 | // Edge triggered when not in SCAN_MODE | |
5656 | ||
5657 | ||
5658 | parameter SIZE = 1; | |
5659 | ||
5660 | output q_l; | |
5661 | output so; | |
5662 | ||
5663 | input d; | |
5664 | input l1clk; | |
5665 | input si; | |
5666 | input siclk; | |
5667 | input soclk; | |
5668 | ||
5669 | reg q_l; | |
5670 | reg q; | |
5671 | wire so; | |
5672 | wire l1clk, siclk, soclk; | |
5673 | ||
5674 | `ifdef SCAN_MODE | |
5675 | reg l1; | |
5676 | `ifdef FAST_FLUSH | |
5677 | always @(posedge l1clk or posedge siclk ) begin | |
5678 | if (siclk) begin | |
5679 | q <= 1'b0; //pseudo flush reset | |
5680 | end else begin | |
5681 | q <= d; | |
5682 | end | |
5683 | end | |
5684 | `else | |
5685 | ||
5686 | always @(l1clk or siclk or soclk or d or si) | |
5687 | begin | |
5688 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5689 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5690 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5691 | ||
5692 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5693 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5694 | end | |
5695 | `endif | |
5696 | `else | |
5697 | wire si_unused; | |
5698 | wire siclk_unused; | |
5699 | wire soclk_unused; | |
5700 | assign si_unused = si; | |
5701 | assign siclk_unused = siclk; | |
5702 | assign soclk_unused = soclk; | |
5703 | ||
5704 | ||
5705 | `ifdef INITLATZERO | |
5706 | initial q_l = 1'b1; | |
5707 | initial q = 1'b0; | |
5708 | `endif | |
5709 | ||
5710 | always @(posedge l1clk) | |
5711 | begin | |
5712 | if (!siclk && !soclk) q <= d; | |
5713 | else q <= 1'bx; | |
5714 | end | |
5715 | `endif | |
5716 | ||
5717 | ||
5718 | always @ (q) | |
5719 | begin | |
5720 | q_l=~q; | |
5721 | end | |
5722 | ||
5723 | ||
5724 | ||
5725 | assign so = q; | |
5726 | ||
5727 | endmodule // dff | |
5728 | ||
5729 | ||
5730 | module cl_a1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5731 | // RFM 05-14-2004 | |
5732 | // Level sensitive in SCAN_MODE | |
5733 | // Edge triggered when not in SCAN_MODE | |
5734 | ||
5735 | ||
5736 | parameter SIZE = 1; | |
5737 | ||
5738 | output q_l; | |
5739 | output so; | |
5740 | ||
5741 | input d; | |
5742 | input l1clk; | |
5743 | input si; | |
5744 | input siclk; | |
5745 | input soclk; | |
5746 | ||
5747 | reg q_l; | |
5748 | reg q; | |
5749 | wire so; | |
5750 | wire l1clk, siclk, soclk; | |
5751 | ||
5752 | `ifdef SCAN_MODE | |
5753 | reg l1; | |
5754 | `ifdef FAST_FLUSH | |
5755 | always @(posedge l1clk or posedge siclk ) begin | |
5756 | if (siclk) begin | |
5757 | q <= 1'b0; //pseudo flush reset | |
5758 | end else begin | |
5759 | q <= d; | |
5760 | end | |
5761 | end | |
5762 | `else | |
5763 | ||
5764 | always @(l1clk or siclk or soclk or d or si) | |
5765 | begin | |
5766 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5767 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5768 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5769 | ||
5770 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5771 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5772 | end | |
5773 | `endif | |
5774 | `else | |
5775 | wire si_unused; | |
5776 | wire siclk_unused; | |
5777 | wire soclk_unused; | |
5778 | assign si_unused = si; | |
5779 | assign siclk_unused = siclk; | |
5780 | assign soclk_unused = soclk; | |
5781 | ||
5782 | ||
5783 | `ifdef INITLATZERO | |
5784 | initial q_l = 1'b1; | |
5785 | initial q = 1'b0; | |
5786 | `endif | |
5787 | ||
5788 | always @(posedge l1clk) | |
5789 | begin | |
5790 | if (!siclk && !soclk) q <= d; | |
5791 | else q <= 1'bx; | |
5792 | end | |
5793 | `endif | |
5794 | ||
5795 | ||
5796 | always @ (q) | |
5797 | begin | |
5798 | q_l=~q; | |
5799 | end | |
5800 | ||
5801 | ||
5802 | ||
5803 | assign so = q; | |
5804 | ||
5805 | endmodule // dff | |
5806 | ||
5807 | module cl_a1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
5808 | // RFM 05-14-2004 | |
5809 | // Level sensitive in SCAN_MODE | |
5810 | // Edge triggered when not in SCAN_MODE | |
5811 | ||
5812 | ||
5813 | parameter SIZE = 1; | |
5814 | ||
5815 | output q_l; | |
5816 | output so; | |
5817 | ||
5818 | input d; | |
5819 | input l1clk; | |
5820 | input si; | |
5821 | input siclk; | |
5822 | input soclk; | |
5823 | ||
5824 | reg q_l; | |
5825 | reg q; | |
5826 | wire so; | |
5827 | wire l1clk, siclk, soclk; | |
5828 | ||
5829 | `ifdef SCAN_MODE | |
5830 | reg l1; | |
5831 | `ifdef FAST_FLUSH | |
5832 | always @(posedge l1clk or posedge siclk ) begin | |
5833 | if (siclk) begin | |
5834 | q <= 1'b0; //pseudo flush reset | |
5835 | end else begin | |
5836 | q <= d; | |
5837 | end | |
5838 | end | |
5839 | `else | |
5840 | ||
5841 | always @(l1clk or siclk or soclk or d or si) | |
5842 | begin | |
5843 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5844 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5845 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5846 | ||
5847 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
5848 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
5849 | end | |
5850 | `endif | |
5851 | `else | |
5852 | wire si_unused; | |
5853 | wire siclk_unused; | |
5854 | wire soclk_unused; | |
5855 | assign si_unused = si; | |
5856 | assign siclk_unused = siclk; | |
5857 | assign soclk_unused = soclk; | |
5858 | ||
5859 | ||
5860 | `ifdef INITLATZERO | |
5861 | initial q_l = 1'b1; | |
5862 | initial q = 1'b0; | |
5863 | `endif | |
5864 | ||
5865 | always @(posedge l1clk) | |
5866 | begin | |
5867 | if (!siclk && !soclk) q <= d; | |
5868 | else q <= 1'bx; | |
5869 | end | |
5870 | `endif | |
5871 | ||
5872 | ||
5873 | always @ (q) | |
5874 | begin | |
5875 | q_l=~q; | |
5876 | end | |
5877 | ||
5878 | ||
5879 | ||
5880 | assign so = q; | |
5881 | ||
5882 | endmodule // dff | |
5883 | ||
5884 | ||
5885 | ||
5886 | ||
5887 | ||
5888 | ||
5889 | module cl_a1_msffjtag_4x ( q, so, d, l1clk, si, siclk, soclk, reset, updateclk ); | |
5890 | ||
5891 | output q; | |
5892 | output so; | |
5893 | ||
5894 | input d; | |
5895 | input l1clk; | |
5896 | input si; | |
5897 | input siclk; | |
5898 | input soclk; | |
5899 | input reset; | |
5900 | input updateclk; | |
5901 | `ifdef LIB | |
5902 | reg q; | |
5903 | reg so; | |
5904 | wire l1clk, siclk, soclk, updateclk; | |
5905 | ||
5906 | reg l1; | |
5907 | ||
5908 | always @(l1clk or siclk or soclk or d or si or reset) | |
5909 | begin | |
5910 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
5911 | if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
5912 | if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
5913 | if ( l1clk && !reset && !soclk) so <= l1; // Load slave with master data | |
5914 | if ( l1clk && siclk && !soclk && !reset) so <= si; // Flush | |
5915 | end | |
5916 | ||
5917 | `ifdef INITLATZERO | |
5918 | initial q = 1'b0; | |
5919 | `endif | |
5920 | ||
5921 | ||
5922 | ||
5923 | always@(updateclk or reset or l1) | |
5924 | begin | |
5925 | if(!reset && updateclk) q <=l1; | |
5926 | if(reset) | |
5927 | begin | |
5928 | q <=1'b0; | |
5929 | so <=1'b0; | |
5930 | end | |
5931 | end | |
5932 | `endif | |
5933 | endmodule | |
5934 | ||
5935 | ||
5936 | ||
5937 | ||
5938 | module cl_a1_clksyncff_4x(l1clk, d, si, siclk, soclk, q, so); | |
5939 | input l1clk, d, si, siclk, soclk; | |
5940 | output q, so; | |
5941 | wire q1o, slo; | |
5942 | ||
5943 | cl_a1_msff_4x xx0 ( .l1clk(l1clk), .d(d), .si(si), .siclk(siclk), .soclk(soclk), .q(q1o), .so(slo)); | |
5944 | cl_a1_msff_4x xx1 ( .l1clk(l1clk), .d(q1o), .si(slo), .siclk(siclk), .soclk(soclk), .q(q), .so(so)); | |
5945 | endmodule | |
5946 | module cl_a1_bs_cell2_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, mode, | |
5947 | muxd, highz_n); | |
5948 | ||
5949 | output q; | |
5950 | output so; | |
5951 | ||
5952 | input d, highz_n; | |
5953 | input l1clk; | |
5954 | input si; | |
5955 | input siclk; | |
5956 | input soclk; | |
5957 | ||
5958 | input updateclk, mode, muxd; | |
5959 | ||
5960 | reg q; | |
5961 | reg so; | |
5962 | wire l1clk, siclk, soclk, updateclk; | |
5963 | ||
5964 | ||
5965 | reg l1, qm; | |
5966 | ||
5967 | always @(l1clk or siclk or soclk or d or si) | |
5968 | begin | |
5969 | if (!l1clk && !siclk) l1 <= d; | |
5970 | if ( l1clk && siclk) l1 <= si; | |
5971 | if (!l1clk && siclk) l1 <= 1'bx; | |
5972 | if ( l1clk && !soclk) so <= l1; | |
5973 | if ( l1clk && siclk && !soclk) so <= si; // Flush | |
5974 | end | |
5975 | `ifdef INITLATZERO | |
5976 | initial qm = 1'b0; | |
5977 | `endif | |
5978 | always@(updateclk or l1) | |
5979 | begin | |
5980 | if(updateclk) qm <=l1; | |
5981 | end | |
5982 | always@(mode or muxd or qm or highz_n) | |
5983 | begin | |
5984 | if(mode==0) q=(qm && highz_n); | |
5985 | else q=muxd; | |
5986 | end | |
5987 | endmodule | |
5988 | ||
5989 | module cl_a1_clk_buf_16x ( | |
5990 | in, | |
5991 | out | |
5992 | ); | |
5993 | input in; | |
5994 | output out; | |
5995 | ||
5996 | `ifdef LIB | |
5997 | assign out = in; | |
5998 | `endif | |
5999 | ||
6000 | endmodule | |
6001 | module cl_a1_clk_buf_20x ( | |
6002 | in, | |
6003 | out | |
6004 | ); | |
6005 | input in; | |
6006 | output out; | |
6007 | ||
6008 | `ifdef LIB | |
6009 | assign out = in; | |
6010 | `endif | |
6011 | ||
6012 | endmodule | |
6013 | module cl_a1_clk_buf_24x ( | |
6014 | in, | |
6015 | out | |
6016 | ); | |
6017 | input in; | |
6018 | output out; | |
6019 | ||
6020 | `ifdef LIB | |
6021 | assign out = in; | |
6022 | `endif | |
6023 | ||
6024 | endmodule | |
6025 | module cl_a1_clk_buf_32x ( | |
6026 | in, | |
6027 | out | |
6028 | ); | |
6029 | input in; | |
6030 | output out; | |
6031 | ||
6032 | `ifdef LIB | |
6033 | assign out = in; | |
6034 | `endif | |
6035 | ||
6036 | endmodule | |
6037 | module cl_a1_clk_buf_48x ( | |
6038 | in, | |
6039 | out | |
6040 | ); | |
6041 | input in; | |
6042 | output out; | |
6043 | ||
6044 | `ifdef LIB | |
6045 | assign out = in; | |
6046 | `endif | |
6047 | ||
6048 | endmodule | |
6049 | module cl_a1_clk_buf_64x ( | |
6050 | in, | |
6051 | out | |
6052 | ); | |
6053 | input in; | |
6054 | output out; | |
6055 | ||
6056 | `ifdef LIB | |
6057 | assign out = in; | |
6058 | `endif | |
6059 | ||
6060 | endmodule | |
6061 | module cl_a1_clk_buf_8x ( | |
6062 | in, | |
6063 | out | |
6064 | ); | |
6065 | input in; | |
6066 | output out; | |
6067 | ||
6068 | `ifdef LIB | |
6069 | assign out = in; | |
6070 | `endif | |
6071 | ||
6072 | endmodule | |
6073 | module cl_a1_clk_inv_16x ( | |
6074 | in, | |
6075 | out | |
6076 | ); | |
6077 | input in; | |
6078 | output out; | |
6079 | ||
6080 | `ifdef LIB | |
6081 | assign out = ~in; | |
6082 | `endif | |
6083 | ||
6084 | endmodule | |
6085 | module cl_a1_clk_inv_20x ( | |
6086 | clkin, | |
6087 | clkout | |
6088 | ); | |
6089 | input clkin; | |
6090 | output clkout; | |
6091 | ||
6092 | `ifdef LIB | |
6093 | assign clkout = ~clkin; | |
6094 | `endif | |
6095 | ||
6096 | endmodule | |
6097 | module cl_a1_clk_inv_24x ( | |
6098 | in, | |
6099 | out | |
6100 | ); | |
6101 | input in; | |
6102 | output out; | |
6103 | ||
6104 | `ifdef LIB | |
6105 | assign out = ~in; | |
6106 | `endif | |
6107 | ||
6108 | endmodule | |
6109 | module cl_a1_clk_inv_32x ( | |
6110 | in, | |
6111 | out | |
6112 | ); | |
6113 | input in; | |
6114 | output out; | |
6115 | ||
6116 | `ifdef LIB | |
6117 | assign out = ~in; | |
6118 | `endif | |
6119 | ||
6120 | endmodule | |
6121 | module cl_a1_clk_inv_48x ( | |
6122 | in, | |
6123 | out | |
6124 | ); | |
6125 | input in; | |
6126 | output out; | |
6127 | ||
6128 | `ifdef LIB | |
6129 | assign out = ~in; | |
6130 | `endif | |
6131 | ||
6132 | endmodule | |
6133 | module cl_a1_clk_inv_64x ( | |
6134 | in, | |
6135 | out | |
6136 | ); | |
6137 | input in; | |
6138 | output out; | |
6139 | ||
6140 | `ifdef LIB | |
6141 | assign out = ~in; | |
6142 | `endif | |
6143 | ||
6144 | endmodule | |
6145 | module cl_a1_clk_inv_8x ( | |
6146 | clkin, | |
6147 | clkout | |
6148 | ); | |
6149 | input clkin; | |
6150 | output clkout; | |
6151 | ||
6152 | `ifdef LIB | |
6153 | assign clkout = ~clkin; | |
6154 | `endif | |
6155 | ||
6156 | endmodule | |
6157 | module cl_a1_clk_mux2_16x ( | |
6158 | in0, | |
6159 | in1, | |
6160 | sel0, | |
6161 | out | |
6162 | ); | |
6163 | input in0; | |
6164 | input in1; | |
6165 | input sel0; | |
6166 | output out; | |
6167 | ||
6168 | `ifdef LIB | |
6169 | reg out; | |
6170 | always @ ( sel0 or in0 or in1) | |
6171 | case ( sel0 ) | |
6172 | 1'b1: out = in0; | |
6173 | 1'b0: out = in1; | |
6174 | ||
6175 | default: out = 1'bx; | |
6176 | ||
6177 | endcase | |
6178 | `endif | |
6179 | ||
6180 | endmodule | |
6181 | ||
6182 | module cl_a1_clk_mux2_24x ( | |
6183 | in0, | |
6184 | in1, | |
6185 | sel0, | |
6186 | out | |
6187 | ); | |
6188 | input in0; | |
6189 | input in1; | |
6190 | input sel0; | |
6191 | output out; | |
6192 | ||
6193 | `ifdef LIB | |
6194 | reg out; | |
6195 | always @ ( sel0 or in0 or in1) | |
6196 | case ( sel0 ) | |
6197 | 1'b1: out = in0; | |
6198 | 1'b0: out = in1; | |
6199 | ||
6200 | default: out = 1'bx; | |
6201 | ||
6202 | endcase | |
6203 | `endif | |
6204 | ||
6205 | endmodule | |
6206 | ||
6207 | module cl_a1_clk_mux2_32x ( | |
6208 | in0, | |
6209 | in1, | |
6210 | sel0, | |
6211 | out | |
6212 | ); | |
6213 | input in0; | |
6214 | input in1; | |
6215 | input sel0; | |
6216 | output out; | |
6217 | ||
6218 | `ifdef LIB | |
6219 | reg out; | |
6220 | always @ ( sel0 or in0 or in1) | |
6221 | case ( sel0 ) | |
6222 | 1'b1: out = in0; | |
6223 | 1'b0: out = in1; | |
6224 | ||
6225 | default: out = 1'bx; | |
6226 | ||
6227 | endcase | |
6228 | `endif | |
6229 | ||
6230 | endmodule | |
6231 | ||
6232 | module cl_a1_clk_mux2_8x ( | |
6233 | in0, | |
6234 | in1, | |
6235 | sel0, | |
6236 | out | |
6237 | ); | |
6238 | input in0; | |
6239 | input in1; | |
6240 | input sel0; | |
6241 | output out; | |
6242 | ||
6243 | `ifdef LIB | |
6244 | reg out; | |
6245 | always @ ( sel0 or in0 or in1) | |
6246 | case ( sel0 ) | |
6247 | 1'b1: out = in0; | |
6248 | 1'b0: out = in1; | |
6249 | ||
6250 | default: out = 1'bx; | |
6251 | ||
6252 | endcase | |
6253 | `endif | |
6254 | ||
6255 | endmodule | |
6256 | ||
6257 | // -------------------------------------------------- | |
6258 | // File: cl_a1_aoi12_12x.behV | |
6259 | // Auto generated verilog module by HnBCellAuto | |
6260 | // | |
6261 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
6262 | // By: balmiki | |
6263 | // -------------------------------------------------- | |
6264 | // | |
6265 | module cl_a1_aoi12_12x ( | |
6266 | out, | |
6267 | in10, | |
6268 | in00, | |
6269 | in01 ); | |
6270 | ||
6271 | output out; | |
6272 | input in10; | |
6273 | input in00; | |
6274 | input in01; | |
6275 | ||
6276 | `ifdef LIB | |
6277 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6278 | `endif | |
6279 | ||
6280 | endmodule | |
6281 | // -------------------------------------------------- | |
6282 | // File: cl_a1_aoi12_16x.behV | |
6283 | // Auto generated verilog module by HnBCellAuto | |
6284 | // | |
6285 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
6286 | // By: balmiki | |
6287 | // -------------------------------------------------- | |
6288 | // | |
6289 | module cl_a1_aoi12_16x ( | |
6290 | out, | |
6291 | in10, | |
6292 | in00, | |
6293 | in01 ); | |
6294 | ||
6295 | output out; | |
6296 | input in10; | |
6297 | input in00; | |
6298 | input in01; | |
6299 | ||
6300 | `ifdef LIB | |
6301 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6302 | `endif | |
6303 | ||
6304 | endmodule | |
6305 | // -------------------------------------------------- | |
6306 | // File: cl_a1_aoi12_1x.behV | |
6307 | // Auto generated verilog module by HnBCellAuto | |
6308 | // | |
6309 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST | |
6310 | // By: balmiki | |
6311 | // -------------------------------------------------- | |
6312 | // | |
6313 | module cl_a1_aoi12_1x ( | |
6314 | out, | |
6315 | in10, | |
6316 | in00, | |
6317 | in01 ); | |
6318 | ||
6319 | output out; | |
6320 | input in10; | |
6321 | input in00; | |
6322 | input in01; | |
6323 | ||
6324 | `ifdef LIB | |
6325 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6326 | `endif | |
6327 | ||
6328 | endmodule | |
6329 | // -------------------------------------------------- | |
6330 | // File: cl_a1_aoi12_2x.behV | |
6331 | // Auto generated verilog module by HnBCellAuto | |
6332 | // | |
6333 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
6334 | // By: balmiki | |
6335 | // -------------------------------------------------- | |
6336 | // | |
6337 | module cl_a1_aoi12_2x ( | |
6338 | out, | |
6339 | in10, | |
6340 | in00, | |
6341 | in01 ); | |
6342 | ||
6343 | output out; | |
6344 | input in10; | |
6345 | input in00; | |
6346 | input in01; | |
6347 | ||
6348 | `ifdef LIB | |
6349 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6350 | `endif | |
6351 | ||
6352 | endmodule | |
6353 | // -------------------------------------------------- | |
6354 | // File: cl_a1_aoi12_4x.behV | |
6355 | // Auto generated verilog module by HnBCellAuto | |
6356 | // | |
6357 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
6358 | // By: balmiki | |
6359 | // -------------------------------------------------- | |
6360 | // | |
6361 | module cl_a1_aoi12_4x ( | |
6362 | out, | |
6363 | in10, | |
6364 | in00, | |
6365 | in01 ); | |
6366 | ||
6367 | output out; | |
6368 | input in10; | |
6369 | input in00; | |
6370 | input in01; | |
6371 | ||
6372 | `ifdef LIB | |
6373 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6374 | `endif | |
6375 | ||
6376 | endmodule | |
6377 | // -------------------------------------------------- | |
6378 | // File: cl_a1_aoi12_8x.behV | |
6379 | // Auto generated verilog module by HnBCellAuto | |
6380 | // | |
6381 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
6382 | // By: balmiki | |
6383 | // -------------------------------------------------- | |
6384 | // | |
6385 | module cl_a1_aoi12_8x ( | |
6386 | out, | |
6387 | in10, | |
6388 | in00, | |
6389 | in01 ); | |
6390 | ||
6391 | output out; | |
6392 | input in10; | |
6393 | input in00; | |
6394 | input in01; | |
6395 | ||
6396 | `ifdef LIB | |
6397 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
6398 | `endif | |
6399 | ||
6400 | endmodule | |
6401 | // -------------------------------------------------- | |
6402 | // File: cl_a1_aoi21_12x.behV | |
6403 | // Auto generated verilog module by HnBCellAuto | |
6404 | // | |
6405 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6406 | // By: balmiki | |
6407 | // -------------------------------------------------- | |
6408 | // | |
6409 | module cl_a1_aoi21_12x ( | |
6410 | out, | |
6411 | in10, | |
6412 | in11, | |
6413 | in00 ); | |
6414 | ||
6415 | output out; | |
6416 | input in10; | |
6417 | input in11; | |
6418 | input in00; | |
6419 | ||
6420 | `ifdef LIB | |
6421 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6422 | `endif | |
6423 | ||
6424 | endmodule | |
6425 | // -------------------------------------------------- | |
6426 | // File: cl_a1_aoi21_16x.behV | |
6427 | // Auto generated verilog module by HnBCellAuto | |
6428 | // | |
6429 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6430 | // By: balmiki | |
6431 | // -------------------------------------------------- | |
6432 | // | |
6433 | module cl_a1_aoi21_16x ( | |
6434 | out, | |
6435 | in10, | |
6436 | in11, | |
6437 | in00 ); | |
6438 | ||
6439 | output out; | |
6440 | input in10; | |
6441 | input in11; | |
6442 | input in00; | |
6443 | ||
6444 | `ifdef LIB | |
6445 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6446 | `endif | |
6447 | ||
6448 | endmodule | |
6449 | // -------------------------------------------------- | |
6450 | // File: cl_a1_aoi21_1x.behV | |
6451 | // Auto generated verilog module by HnBCellAuto | |
6452 | // | |
6453 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6454 | // By: balmiki | |
6455 | // -------------------------------------------------- | |
6456 | // | |
6457 | module cl_a1_aoi21_1x ( | |
6458 | out, | |
6459 | in10, | |
6460 | in11, | |
6461 | in00 ); | |
6462 | ||
6463 | output out; | |
6464 | input in10; | |
6465 | input in11; | |
6466 | input in00; | |
6467 | ||
6468 | `ifdef LIB | |
6469 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6470 | `endif | |
6471 | ||
6472 | endmodule | |
6473 | // -------------------------------------------------- | |
6474 | // File: cl_a1_aoi21_2x.behV | |
6475 | // Auto generated verilog module by HnBCellAuto | |
6476 | // | |
6477 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6478 | // By: balmiki | |
6479 | // -------------------------------------------------- | |
6480 | // | |
6481 | module cl_a1_aoi21_2x ( | |
6482 | out, | |
6483 | in10, | |
6484 | in11, | |
6485 | in00 ); | |
6486 | ||
6487 | output out; | |
6488 | input in10; | |
6489 | input in11; | |
6490 | input in00; | |
6491 | ||
6492 | `ifdef LIB | |
6493 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6494 | `endif | |
6495 | ||
6496 | endmodule | |
6497 | // -------------------------------------------------- | |
6498 | // File: cl_a1_aoi21_4x.behV | |
6499 | // Auto generated verilog module by HnBCellAuto | |
6500 | // | |
6501 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6502 | // By: balmiki | |
6503 | // -------------------------------------------------- | |
6504 | // | |
6505 | module cl_a1_aoi21_4x ( | |
6506 | out, | |
6507 | in10, | |
6508 | in11, | |
6509 | in00 ); | |
6510 | ||
6511 | output out; | |
6512 | input in10; | |
6513 | input in11; | |
6514 | input in00; | |
6515 | ||
6516 | `ifdef LIB | |
6517 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6518 | `endif | |
6519 | ||
6520 | endmodule | |
6521 | // -------------------------------------------------- | |
6522 | // File: cl_a1_aoi21_8x.behV | |
6523 | // Auto generated verilog module by HnBCellAuto | |
6524 | // | |
6525 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
6526 | // By: balmiki | |
6527 | // -------------------------------------------------- | |
6528 | // | |
6529 | module cl_a1_aoi21_8x ( | |
6530 | out, | |
6531 | in10, | |
6532 | in11, | |
6533 | in00 ); | |
6534 | ||
6535 | output out; | |
6536 | input in10; | |
6537 | input in11; | |
6538 | input in00; | |
6539 | ||
6540 | `ifdef LIB | |
6541 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
6542 | `endif | |
6543 | ||
6544 | endmodule | |
6545 | // -------------------------------------------------- | |
6546 | // File: cl_a1_aoi22_12x.behV | |
6547 | // Auto generated verilog module by HnBCellAuto | |
6548 | // | |
6549 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
6550 | // By: balmiki | |
6551 | // -------------------------------------------------- | |
6552 | // | |
6553 | module cl_a1_aoi22_12x ( | |
6554 | out, | |
6555 | in10, | |
6556 | in11, | |
6557 | in00, | |
6558 | in01 ); | |
6559 | ||
6560 | output out; | |
6561 | input in10; | |
6562 | input in11; | |
6563 | input in00; | |
6564 | input in01; | |
6565 | ||
6566 | `ifdef LIB | |
6567 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
6568 | `endif | |
6569 | ||
6570 | endmodule | |
6571 | ||
6572 | // -------------------------------------------------- | |
6573 | // File: cl_a1_aoi22_1x.behV | |
6574 | // Auto generated verilog module by HnBCellAuto | |
6575 | // | |
6576 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT | |
6577 | // By: balmiki | |
6578 | // -------------------------------------------------- | |
6579 | // | |
6580 | module cl_a1_aoi22_1x ( | |
6581 | out, | |
6582 | in10, | |
6583 | in11, | |
6584 | in00, | |
6585 | in01 ); | |
6586 | ||
6587 | output out; | |
6588 | input in10; | |
6589 | input in11; | |
6590 | input in00; | |
6591 | input in01; | |
6592 | ||
6593 | `ifdef LIB | |
6594 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
6595 | `endif | |
6596 | ||
6597 | endmodule | |
6598 | // -------------------------------------------------- | |
6599 | // File: cl_a1_aoi22_2x.behV | |
6600 | // Auto generated verilog module by HnBCellAuto | |
6601 | // | |
6602 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
6603 | // By: balmiki | |
6604 | // -------------------------------------------------- | |
6605 | // | |
6606 | module cl_a1_aoi22_2x ( | |
6607 | out, | |
6608 | in10, | |
6609 | in11, | |
6610 | in00, | |
6611 | in01 ); | |
6612 | ||
6613 | output out; | |
6614 | input in10; | |
6615 | input in11; | |
6616 | input in00; | |
6617 | input in01; | |
6618 | ||
6619 | `ifdef LIB | |
6620 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
6621 | `endif | |
6622 | ||
6623 | endmodule | |
6624 | // -------------------------------------------------- | |
6625 | // File: cl_a1_aoi22_4x.behV | |
6626 | // Auto generated verilog module by HnBCellAuto | |
6627 | // | |
6628 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
6629 | // By: balmiki | |
6630 | // -------------------------------------------------- | |
6631 | // | |
6632 | module cl_a1_aoi22_4x ( | |
6633 | out, | |
6634 | in10, | |
6635 | in11, | |
6636 | in00, | |
6637 | in01 ); | |
6638 | ||
6639 | output out; | |
6640 | input in10; | |
6641 | input in11; | |
6642 | input in00; | |
6643 | input in01; | |
6644 | ||
6645 | `ifdef LIB | |
6646 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
6647 | `endif | |
6648 | ||
6649 | endmodule | |
6650 | // -------------------------------------------------- | |
6651 | // File: cl_a1_aoi22_8x.behV | |
6652 | // Auto generated verilog module by HnBCellAuto | |
6653 | // | |
6654 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
6655 | // By: balmiki | |
6656 | // -------------------------------------------------- | |
6657 | // | |
6658 | module cl_a1_aoi22_8x ( | |
6659 | out, | |
6660 | in10, | |
6661 | in11, | |
6662 | in00, | |
6663 | in01 ); | |
6664 | ||
6665 | output out; | |
6666 | input in10; | |
6667 | input in11; | |
6668 | input in00; | |
6669 | input in01; | |
6670 | ||
6671 | `ifdef LIB | |
6672 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
6673 | `endif | |
6674 | ||
6675 | endmodule | |
6676 | ||
6677 | ||
6678 | // -------------------------------------------------- | |
6679 | // File: cl_a1_aoi33_1x.behV | |
6680 | // Auto generated verilog module by HnBCellAuto | |
6681 | // | |
6682 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST | |
6683 | // By: balmiki | |
6684 | // -------------------------------------------------- | |
6685 | // | |
6686 | module cl_a1_aoi33_1x ( | |
6687 | out, | |
6688 | in10, | |
6689 | in11, | |
6690 | in12, | |
6691 | in00, | |
6692 | in01, | |
6693 | in02 ); | |
6694 | ||
6695 | output out; | |
6696 | input in10; | |
6697 | input in11; | |
6698 | input in12; | |
6699 | input in00; | |
6700 | input in01; | |
6701 | input in02; | |
6702 | ||
6703 | `ifdef LIB | |
6704 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
6705 | `endif | |
6706 | ||
6707 | endmodule | |
6708 | // -------------------------------------------------- | |
6709 | // File: cl_a1_aoi33_2x.behV | |
6710 | // Auto generated verilog module by HnBCellAuto | |
6711 | // | |
6712 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
6713 | // By: balmiki | |
6714 | // -------------------------------------------------- | |
6715 | // | |
6716 | module cl_a1_aoi33_2x ( | |
6717 | out, | |
6718 | in10, | |
6719 | in11, | |
6720 | in12, | |
6721 | in00, | |
6722 | in01, | |
6723 | in02 ); | |
6724 | ||
6725 | output out; | |
6726 | input in10; | |
6727 | input in11; | |
6728 | input in12; | |
6729 | input in00; | |
6730 | input in01; | |
6731 | input in02; | |
6732 | ||
6733 | `ifdef LIB | |
6734 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
6735 | `endif | |
6736 | ||
6737 | endmodule | |
6738 | // -------------------------------------------------- | |
6739 | // File: cl_a1_aoi33_4x.behV | |
6740 | // Auto generated verilog module by HnBCellAuto | |
6741 | // | |
6742 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
6743 | // By: balmiki | |
6744 | // -------------------------------------------------- | |
6745 | // | |
6746 | module cl_a1_aoi33_4x ( | |
6747 | out, | |
6748 | in10, | |
6749 | in11, | |
6750 | in12, | |
6751 | in00, | |
6752 | in01, | |
6753 | in02 ); | |
6754 | ||
6755 | output out; | |
6756 | input in10; | |
6757 | input in11; | |
6758 | input in12; | |
6759 | input in00; | |
6760 | input in01; | |
6761 | input in02; | |
6762 | ||
6763 | `ifdef LIB | |
6764 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
6765 | `endif | |
6766 | ||
6767 | endmodule | |
6768 | // -------------------------------------------------- | |
6769 | // File: cl_a1_aoi33_8x.behV | |
6770 | // Auto generated verilog module by HnBCellAuto | |
6771 | // | |
6772 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
6773 | // By: balmiki | |
6774 | // -------------------------------------------------- | |
6775 | // | |
6776 | module cl_a1_aoi33_8x ( | |
6777 | out, | |
6778 | in10, | |
6779 | in11, | |
6780 | in12, | |
6781 | in00, | |
6782 | in01, | |
6783 | in02 ); | |
6784 | ||
6785 | output out; | |
6786 | input in10; | |
6787 | input in11; | |
6788 | input in12; | |
6789 | input in00; | |
6790 | input in01; | |
6791 | input in02; | |
6792 | ||
6793 | `ifdef LIB | |
6794 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
6795 | `endif | |
6796 | ||
6797 | endmodule | |
6798 | module cl_a1_rep_32x ( | |
6799 | in, | |
6800 | out | |
6801 | ); | |
6802 | input in; | |
6803 | output out; | |
6804 | ||
6805 | `ifdef LIB | |
6806 | assign out = in; | |
6807 | `endif | |
6808 | ||
6809 | endmodule | |
6810 | module cl_a1_rep_40x ( | |
6811 | in, | |
6812 | out | |
6813 | ); | |
6814 | input in; | |
6815 | output out; | |
6816 | ||
6817 | `ifdef LIB | |
6818 | assign out = in; | |
6819 | `endif | |
6820 | ||
6821 | endmodule | |
6822 | module cl_a1_rep_24x ( | |
6823 | in, | |
6824 | out | |
6825 | ); | |
6826 | input in; | |
6827 | output out; | |
6828 | ||
6829 | `ifdef LIB | |
6830 | assign out = in; | |
6831 | `endif | |
6832 | ||
6833 | endmodule | |
6834 | module cl_a1_rep_16x ( | |
6835 | in, | |
6836 | out | |
6837 | ); | |
6838 | input in; | |
6839 | output out; | |
6840 | ||
6841 | `ifdef LIB | |
6842 | assign out = in; | |
6843 | `endif | |
6844 | ||
6845 | endmodule | |
6846 | module cl_a1_rep_8x ( | |
6847 | in, | |
6848 | out | |
6849 | ); | |
6850 | input in; | |
6851 | output out; | |
6852 | ||
6853 | `ifdef LIB | |
6854 | assign out = in; | |
6855 | `endif | |
6856 | ||
6857 | endmodule | |
6858 | module cl_a1_rep_48x ( | |
6859 | in, | |
6860 | out | |
6861 | ); | |
6862 | input in; | |
6863 | output out; | |
6864 | ||
6865 | `ifdef LIB | |
6866 | assign out = in; | |
6867 | `endif | |
6868 | ||
6869 | endmodule | |
6870 | module cl_a1_rep_dcp2x_32x ( | |
6871 | in, | |
6872 | out | |
6873 | ); | |
6874 | input in; | |
6875 | output out; | |
6876 | ||
6877 | `ifdef LIB | |
6878 | assign out = in; | |
6879 | `endif | |
6880 | ||
6881 | endmodule | |
6882 | ||
6883 | module cl_a1_rep_dcp2x_16x ( | |
6884 | in, | |
6885 | out | |
6886 | ); | |
6887 | input in; | |
6888 | output out; | |
6889 | ||
6890 | `ifdef LIB | |
6891 | assign out = in; | |
6892 | `endif | |
6893 | ||
6894 | endmodule | |
6895 | module cl_a1_rep_dcp2x_24x ( | |
6896 | in, | |
6897 | out | |
6898 | ); | |
6899 | input in; | |
6900 | output out; | |
6901 | ||
6902 | `ifdef LIB | |
6903 | assign out = in; | |
6904 | `endif | |
6905 | ||
6906 | endmodule | |
6907 | module cl_a1_rep_dcp2x_40x ( | |
6908 | in, | |
6909 | out | |
6910 | ); | |
6911 | input in; | |
6912 | output out; | |
6913 | ||
6914 | `ifdef LIB | |
6915 | assign out = in; | |
6916 | `endif | |
6917 | ||
6918 | endmodule | |
6919 | module cl_a1_rep_dcp2x_48x ( | |
6920 | in, | |
6921 | out | |
6922 | ); | |
6923 | input in; | |
6924 | output out; | |
6925 | ||
6926 | `ifdef LIB | |
6927 | assign out = in; | |
6928 | `endif | |
6929 | ||
6930 | endmodule | |
6931 | module cl_a1_rep_dcp_32x ( | |
6932 | in, | |
6933 | out | |
6934 | ); | |
6935 | input in; | |
6936 | output out; | |
6937 | ||
6938 | `ifdef LIB | |
6939 | assign out = in; | |
6940 | `endif | |
6941 | ||
6942 | endmodule | |
6943 | ||
6944 | module cl_a1_rep_dcp_16x ( | |
6945 | in, | |
6946 | out | |
6947 | ); | |
6948 | input in; | |
6949 | output out; | |
6950 | ||
6951 | `ifdef LIB | |
6952 | assign out = in; | |
6953 | `endif | |
6954 | ||
6955 | endmodule | |
6956 | module cl_a1_rep_dcp_24x ( | |
6957 | in, | |
6958 | out | |
6959 | ); | |
6960 | input in; | |
6961 | output out; | |
6962 | ||
6963 | `ifdef LIB | |
6964 | assign out = in; | |
6965 | `endif | |
6966 | ||
6967 | endmodule | |
6968 | module cl_a1_rep_dcp_40x ( | |
6969 | in, | |
6970 | out | |
6971 | ); | |
6972 | input in; | |
6973 | output out; | |
6974 | ||
6975 | `ifdef LIB | |
6976 | assign out = in; | |
6977 | `endif | |
6978 | ||
6979 | endmodule | |
6980 | module cl_a1_rep_dcp_48x ( | |
6981 | in, | |
6982 | out | |
6983 | ); | |
6984 | input in; | |
6985 | output out; | |
6986 | ||
6987 | `ifdef LIB | |
6988 | assign out = in; | |
6989 | `endif | |
6990 | ||
6991 | endmodule | |
6992 | module cl_a1_rep_dcp50k_48x ( | |
6993 | in, | |
6994 | out | |
6995 | ); | |
6996 | input in; | |
6997 | output out; | |
6998 | ||
6999 | `ifdef LIB | |
7000 | assign out = in; | |
7001 | `endif | |
7002 | ||
7003 | endmodule | |
7004 | module cl_a1_rep_dcp50k_32x ( | |
7005 | in, | |
7006 | out | |
7007 | ); | |
7008 | input in; | |
7009 | output out; | |
7010 | ||
7011 | `ifdef LIB | |
7012 | assign out = in; | |
7013 | `endif | |
7014 | ||
7015 | endmodule | |
7016 | module cl_a1_rep_dcp50k_40x ( | |
7017 | in, | |
7018 | out | |
7019 | ); | |
7020 | input in; | |
7021 | output out; | |
7022 | ||
7023 | `ifdef LIB | |
7024 | assign out = in; | |
7025 | `endif | |
7026 | ||
7027 | endmodule | |
7028 | ||
7029 | module cl_a1_buf_12x ( | |
7030 | in, | |
7031 | out | |
7032 | ); | |
7033 | input in; | |
7034 | output out; | |
7035 | ||
7036 | `ifdef LIB | |
7037 | assign out = in; | |
7038 | `endif | |
7039 | ||
7040 | endmodule | |
7041 | module cl_a1_buf_16x ( | |
7042 | in, | |
7043 | out | |
7044 | ); | |
7045 | input in; | |
7046 | output out; | |
7047 | ||
7048 | `ifdef LIB | |
7049 | assign out = in; | |
7050 | `endif | |
7051 | ||
7052 | endmodule | |
7053 | module cl_a1_buf_1x ( | |
7054 | in, | |
7055 | out | |
7056 | ); | |
7057 | input in; | |
7058 | output out; | |
7059 | ||
7060 | `ifdef LIB | |
7061 | assign out = in; | |
7062 | `endif | |
7063 | ||
7064 | endmodule | |
7065 | module cl_a1_buf_20x ( | |
7066 | in, | |
7067 | out | |
7068 | ); | |
7069 | input in; | |
7070 | output out; | |
7071 | ||
7072 | `ifdef LIB | |
7073 | assign out = in; | |
7074 | `endif | |
7075 | ||
7076 | endmodule | |
7077 | module cl_a1_buf_24x ( | |
7078 | in, | |
7079 | out | |
7080 | ); | |
7081 | input in; | |
7082 | output out; | |
7083 | ||
7084 | `ifdef LIB | |
7085 | assign out = in; | |
7086 | `endif | |
7087 | ||
7088 | endmodule | |
7089 | module cl_a1_buf_28x ( | |
7090 | in, | |
7091 | out | |
7092 | ); | |
7093 | input in; | |
7094 | output out; | |
7095 | ||
7096 | `ifdef LIB | |
7097 | assign out = in; | |
7098 | `endif | |
7099 | ||
7100 | endmodule | |
7101 | module cl_a1_buf_2x ( | |
7102 | in, | |
7103 | out | |
7104 | ); | |
7105 | input in; | |
7106 | output out; | |
7107 | ||
7108 | `ifdef LIB | |
7109 | assign out = in; | |
7110 | `endif | |
7111 | ||
7112 | endmodule | |
7113 | module cl_a1_buf_32x ( | |
7114 | in, | |
7115 | out | |
7116 | ); | |
7117 | input in; | |
7118 | output out; | |
7119 | ||
7120 | `ifdef LIB | |
7121 | assign out = in; | |
7122 | `endif | |
7123 | ||
7124 | endmodule | |
7125 | module cl_a1_buf_36x ( | |
7126 | in, | |
7127 | out | |
7128 | ); | |
7129 | input in; | |
7130 | output out; | |
7131 | ||
7132 | `ifdef LIB | |
7133 | assign out = in; | |
7134 | `endif | |
7135 | ||
7136 | endmodule | |
7137 | module cl_a1_buf_40x ( | |
7138 | in, | |
7139 | out | |
7140 | ); | |
7141 | input in; | |
7142 | output out; | |
7143 | ||
7144 | `ifdef LIB | |
7145 | assign out = in; | |
7146 | `endif | |
7147 | ||
7148 | endmodule | |
7149 | module cl_a1_buf_44x ( | |
7150 | in, | |
7151 | out | |
7152 | ); | |
7153 | input in; | |
7154 | output out; | |
7155 | ||
7156 | `ifdef LIB | |
7157 | assign out = in; | |
7158 | `endif | |
7159 | ||
7160 | endmodule | |
7161 | module cl_a1_buf_48x ( | |
7162 | in, | |
7163 | out | |
7164 | ); | |
7165 | input in; | |
7166 | output out; | |
7167 | ||
7168 | `ifdef LIB | |
7169 | assign out = in; | |
7170 | `endif | |
7171 | ||
7172 | endmodule | |
7173 | module cl_a1_buf_4x ( | |
7174 | in, | |
7175 | out | |
7176 | ); | |
7177 | input in; | |
7178 | output out; | |
7179 | ||
7180 | `ifdef LIB | |
7181 | assign out = in; | |
7182 | `endif | |
7183 | ||
7184 | endmodule | |
7185 | module cl_a1_buf_56x ( | |
7186 | in, | |
7187 | out | |
7188 | ); | |
7189 | input in; | |
7190 | output out; | |
7191 | ||
7192 | `ifdef LIB | |
7193 | assign out = in; | |
7194 | `endif | |
7195 | ||
7196 | endmodule | |
7197 | module cl_a1_buf_64x ( | |
7198 | in, | |
7199 | out | |
7200 | ); | |
7201 | input in; | |
7202 | output out; | |
7203 | ||
7204 | `ifdef LIB | |
7205 | assign out = in; | |
7206 | `endif | |
7207 | ||
7208 | endmodule | |
7209 | module cl_a1_buf_6x ( | |
7210 | in, | |
7211 | out | |
7212 | ); | |
7213 | input in; | |
7214 | output out; | |
7215 | ||
7216 | `ifdef LIB | |
7217 | assign out = in; | |
7218 | `endif | |
7219 | ||
7220 | endmodule | |
7221 | module cl_a1_buf_8x ( | |
7222 | in, | |
7223 | out | |
7224 | ); | |
7225 | input in; | |
7226 | output out; | |
7227 | ||
7228 | `ifdef LIB | |
7229 | assign out = in; | |
7230 | `endif | |
7231 | ||
7232 | endmodule | |
7233 | module cl_a1_bufmin_1x ( | |
7234 | in, | |
7235 | out | |
7236 | ); | |
7237 | input in; | |
7238 | output out; | |
7239 | ||
7240 | `ifdef LIB | |
7241 | assign out = in; | |
7242 | `endif | |
7243 | ||
7244 | endmodule | |
7245 | module cl_a1_bufmin_4x ( | |
7246 | in, | |
7247 | out | |
7248 | ); | |
7249 | input in; | |
7250 | output out; | |
7251 | ||
7252 | `ifdef LIB | |
7253 | assign out = in; | |
7254 | `endif | |
7255 | ||
7256 | endmodule | |
7257 | module cl_a1_bufmin_8x ( | |
7258 | in, | |
7259 | out | |
7260 | ); | |
7261 | input in; | |
7262 | output out; | |
7263 | ||
7264 | `ifdef LIB | |
7265 | assign out = in; | |
7266 | `endif | |
7267 | ||
7268 | endmodule | |
7269 | module cl_a1_bufmin_16x ( | |
7270 | in, | |
7271 | out | |
7272 | ); | |
7273 | input in; | |
7274 | output out; | |
7275 | ||
7276 | `ifdef LIB | |
7277 | assign out = in; | |
7278 | `endif | |
7279 | ||
7280 | endmodule | |
7281 | module cl_a1_bufmin_32x ( | |
7282 | in, | |
7283 | out | |
7284 | ); | |
7285 | input in; | |
7286 | output out; | |
7287 | ||
7288 | `ifdef LIB | |
7289 | assign out = in; | |
7290 | `endif | |
7291 | ||
7292 | endmodule | |
7293 | module cl_a1_csa32_16x ( | |
7294 | in0, | |
7295 | in1, | |
7296 | in2, | |
7297 | carry, | |
7298 | sum | |
7299 | ); | |
7300 | input in0; | |
7301 | input in1; | |
7302 | input in2; | |
7303 | output carry; | |
7304 | output sum; | |
7305 | ||
7306 | `ifdef LIB | |
7307 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); | |
7308 | assign sum = (in0 ^ in1 ^ in2); | |
7309 | `endif | |
7310 | ||
7311 | endmodule | |
7312 | module cl_a1_csa32_4x ( | |
7313 | in0, | |
7314 | in1, | |
7315 | in2, | |
7316 | carry, | |
7317 | sum | |
7318 | ); | |
7319 | input in0; | |
7320 | input in1; | |
7321 | input in2; | |
7322 | output carry; | |
7323 | output sum; | |
7324 | ||
7325 | `ifdef LIB | |
7326 | assign carry = (in0 & in1) | (in0 & in2) | (in1 & in2); | |
7327 | assign sum = (in0 ^ in1 ^ in2); | |
7328 | `endif | |
7329 | ||
7330 | endmodule | |
7331 | ||
7332 | module cl_a1_inv_12x ( | |
7333 | in, | |
7334 | out | |
7335 | ); | |
7336 | input in; | |
7337 | output out; | |
7338 | ||
7339 | `ifdef LIB | |
7340 | assign out = ~in; | |
7341 | `endif | |
7342 | ||
7343 | endmodule | |
7344 | module cl_a1_inv_16x ( | |
7345 | in, | |
7346 | out | |
7347 | ); | |
7348 | input in; | |
7349 | output out; | |
7350 | ||
7351 | `ifdef LIB | |
7352 | assign out = ~in; | |
7353 | `endif | |
7354 | ||
7355 | endmodule | |
7356 | module cl_a1_inv_1x ( | |
7357 | in, | |
7358 | out | |
7359 | ); | |
7360 | input in; | |
7361 | output out; | |
7362 | ||
7363 | `ifdef LIB | |
7364 | assign out = ~in; | |
7365 | `endif | |
7366 | ||
7367 | endmodule | |
7368 | module cl_a1_inv_20x ( | |
7369 | in, | |
7370 | out | |
7371 | ); | |
7372 | input in; | |
7373 | output out; | |
7374 | ||
7375 | `ifdef LIB | |
7376 | assign out = ~in; | |
7377 | `endif | |
7378 | ||
7379 | endmodule | |
7380 | module cl_a1_inv_24x ( | |
7381 | in, | |
7382 | out | |
7383 | ); | |
7384 | input in; | |
7385 | output out; | |
7386 | ||
7387 | `ifdef LIB | |
7388 | assign out = ~in; | |
7389 | `endif | |
7390 | ||
7391 | endmodule | |
7392 | module cl_a1_inv_28x ( | |
7393 | in, | |
7394 | out | |
7395 | ); | |
7396 | input in; | |
7397 | output out; | |
7398 | ||
7399 | `ifdef LIB | |
7400 | assign out = ~in; | |
7401 | `endif | |
7402 | ||
7403 | endmodule | |
7404 | module cl_a1_inv_2x ( | |
7405 | in, | |
7406 | out | |
7407 | ); | |
7408 | input in; | |
7409 | output out; | |
7410 | ||
7411 | `ifdef LIB | |
7412 | assign out = ~in; | |
7413 | `endif | |
7414 | ||
7415 | endmodule | |
7416 | module cl_a1_inv_32x ( | |
7417 | in, | |
7418 | out | |
7419 | ); | |
7420 | input in; | |
7421 | output out; | |
7422 | ||
7423 | `ifdef LIB | |
7424 | assign out = ~in; | |
7425 | `endif | |
7426 | ||
7427 | endmodule | |
7428 | module cl_a1_inv_36x ( | |
7429 | in, | |
7430 | out | |
7431 | ); | |
7432 | input in; | |
7433 | output out; | |
7434 | ||
7435 | `ifdef LIB | |
7436 | assign out = ~in; | |
7437 | `endif | |
7438 | ||
7439 | endmodule | |
7440 | module cl_a1_inv_40x ( | |
7441 | in, | |
7442 | out | |
7443 | ); | |
7444 | input in; | |
7445 | output out; | |
7446 | ||
7447 | `ifdef LIB | |
7448 | assign out = ~in; | |
7449 | `endif | |
7450 | ||
7451 | endmodule | |
7452 | module cl_a1_inv_44x ( | |
7453 | in, | |
7454 | out | |
7455 | ); | |
7456 | input in; | |
7457 | output out; | |
7458 | ||
7459 | `ifdef LIB | |
7460 | assign out = ~in; | |
7461 | `endif | |
7462 | ||
7463 | endmodule | |
7464 | module cl_a1_inv_48x ( | |
7465 | in, | |
7466 | out | |
7467 | ); | |
7468 | input in; | |
7469 | output out; | |
7470 | ||
7471 | `ifdef LIB | |
7472 | assign out = ~in; | |
7473 | `endif | |
7474 | ||
7475 | endmodule | |
7476 | module cl_a1_inv_4x ( | |
7477 | in, | |
7478 | out | |
7479 | ); | |
7480 | input in; | |
7481 | output out; | |
7482 | ||
7483 | `ifdef LIB | |
7484 | assign out = ~in; | |
7485 | `endif | |
7486 | ||
7487 | endmodule | |
7488 | module cl_a1_inv_56x ( | |
7489 | in, | |
7490 | out | |
7491 | ); | |
7492 | input in; | |
7493 | output out; | |
7494 | ||
7495 | `ifdef LIB | |
7496 | assign out = ~in; | |
7497 | `endif | |
7498 | ||
7499 | endmodule | |
7500 | module cl_a1_inv_64x ( | |
7501 | in, | |
7502 | out | |
7503 | ); | |
7504 | input in; | |
7505 | output out; | |
7506 | ||
7507 | `ifdef LIB | |
7508 | assign out = ~in; | |
7509 | `endif | |
7510 | ||
7511 | endmodule | |
7512 | module cl_a1_inv_6x ( | |
7513 | in, | |
7514 | out | |
7515 | ); | |
7516 | input in; | |
7517 | output out; | |
7518 | ||
7519 | `ifdef LIB | |
7520 | assign out = ~in; | |
7521 | `endif | |
7522 | ||
7523 | endmodule | |
7524 | module cl_a1_inv_8x ( | |
7525 | in, | |
7526 | out | |
7527 | ); | |
7528 | input in; | |
7529 | output out; | |
7530 | ||
7531 | `ifdef LIB | |
7532 | assign out = ~in; | |
7533 | `endif | |
7534 | ||
7535 | endmodule | |
7536 | module cl_a1_nand2_12x ( | |
7537 | in0, | |
7538 | in1, | |
7539 | out | |
7540 | ); | |
7541 | input in0; | |
7542 | input in1; | |
7543 | output out; | |
7544 | ||
7545 | `ifdef LIB | |
7546 | assign out = ~(in0 & in1); | |
7547 | `endif | |
7548 | ||
7549 | endmodule | |
7550 | module cl_a1_nand2_16x ( | |
7551 | in0, | |
7552 | in1, | |
7553 | out | |
7554 | ); | |
7555 | input in0; | |
7556 | input in1; | |
7557 | output out; | |
7558 | ||
7559 | `ifdef LIB | |
7560 | assign out = ~(in0 & in1); | |
7561 | `endif | |
7562 | ||
7563 | endmodule | |
7564 | module cl_a1_nand2_1x ( | |
7565 | in0, | |
7566 | in1, | |
7567 | out | |
7568 | ); | |
7569 | input in0; | |
7570 | input in1; | |
7571 | output out; | |
7572 | ||
7573 | `ifdef LIB | |
7574 | assign out = ~(in0 & in1); | |
7575 | `endif | |
7576 | ||
7577 | endmodule | |
7578 | module cl_a1_nand2_20x ( | |
7579 | in0, | |
7580 | in1, | |
7581 | out | |
7582 | ); | |
7583 | input in0; | |
7584 | input in1; | |
7585 | output out; | |
7586 | ||
7587 | `ifdef LIB | |
7588 | assign out = ~(in0 & in1); | |
7589 | `endif | |
7590 | ||
7591 | endmodule | |
7592 | module cl_a1_nand2_24x ( | |
7593 | in0, | |
7594 | in1, | |
7595 | out | |
7596 | ); | |
7597 | input in0; | |
7598 | input in1; | |
7599 | output out; | |
7600 | ||
7601 | `ifdef LIB | |
7602 | assign out = ~(in0 & in1); | |
7603 | `endif | |
7604 | ||
7605 | endmodule | |
7606 | module cl_a1_nand2_28x ( | |
7607 | in0, | |
7608 | in1, | |
7609 | out | |
7610 | ); | |
7611 | input in0; | |
7612 | input in1; | |
7613 | output out; | |
7614 | ||
7615 | `ifdef LIB | |
7616 | assign out = ~(in0 & in1); | |
7617 | `endif | |
7618 | ||
7619 | endmodule | |
7620 | module cl_a1_nand2_2x ( | |
7621 | in0, | |
7622 | in1, | |
7623 | out | |
7624 | ); | |
7625 | input in0; | |
7626 | input in1; | |
7627 | output out; | |
7628 | ||
7629 | `ifdef LIB | |
7630 | assign out = ~(in0 & in1); | |
7631 | `endif | |
7632 | ||
7633 | endmodule | |
7634 | module cl_a1_nand2_32x ( | |
7635 | in0, | |
7636 | in1, | |
7637 | out | |
7638 | ); | |
7639 | input in0; | |
7640 | input in1; | |
7641 | output out; | |
7642 | ||
7643 | `ifdef LIB | |
7644 | assign out = ~(in0 & in1); | |
7645 | `endif | |
7646 | ||
7647 | endmodule | |
7648 | module cl_a1_nand2_4x ( | |
7649 | in0, | |
7650 | in1, | |
7651 | out | |
7652 | ); | |
7653 | input in0; | |
7654 | input in1; | |
7655 | output out; | |
7656 | ||
7657 | `ifdef LIB | |
7658 | assign out = ~(in0 & in1); | |
7659 | `endif | |
7660 | ||
7661 | endmodule | |
7662 | module cl_a1_nand2_6x ( | |
7663 | in0, | |
7664 | in1, | |
7665 | out | |
7666 | ); | |
7667 | input in0; | |
7668 | input in1; | |
7669 | output out; | |
7670 | ||
7671 | `ifdef LIB | |
7672 | assign out = ~(in0 & in1); | |
7673 | `endif | |
7674 | ||
7675 | endmodule | |
7676 | module cl_a1_nand2_8x ( | |
7677 | in0, | |
7678 | in1, | |
7679 | out | |
7680 | ); | |
7681 | input in0; | |
7682 | input in1; | |
7683 | output out; | |
7684 | ||
7685 | `ifdef LIB | |
7686 | assign out = ~(in0 & in1); | |
7687 | `endif | |
7688 | ||
7689 | endmodule | |
7690 | module cl_a1_nand3_12x ( | |
7691 | in0, | |
7692 | in1, | |
7693 | in2, | |
7694 | out | |
7695 | ); | |
7696 | input in0; | |
7697 | input in1; | |
7698 | input in2; | |
7699 | output out; | |
7700 | ||
7701 | `ifdef LIB | |
7702 | assign out = ~(in0 & in1 & in2); | |
7703 | `endif | |
7704 | ||
7705 | endmodule | |
7706 | module cl_a1_nand3_16x ( | |
7707 | in0, | |
7708 | in1, | |
7709 | in2, | |
7710 | out | |
7711 | ); | |
7712 | input in0; | |
7713 | input in1; | |
7714 | input in2; | |
7715 | output out; | |
7716 | ||
7717 | `ifdef LIB | |
7718 | assign out = ~(in0 & in1 & in2); | |
7719 | `endif | |
7720 | ||
7721 | endmodule | |
7722 | module cl_a1_nand3_1x ( | |
7723 | in0, | |
7724 | in1, | |
7725 | in2, | |
7726 | out | |
7727 | ); | |
7728 | input in0; | |
7729 | input in1; | |
7730 | input in2; | |
7731 | output out; | |
7732 | ||
7733 | `ifdef LIB | |
7734 | assign out = ~(in0 & in1 & in2); | |
7735 | `endif | |
7736 | ||
7737 | endmodule | |
7738 | module cl_a1_nand3_20x ( | |
7739 | in0, | |
7740 | in1, | |
7741 | in2, | |
7742 | out | |
7743 | ); | |
7744 | input in0; | |
7745 | input in1; | |
7746 | input in2; | |
7747 | output out; | |
7748 | ||
7749 | `ifdef LIB | |
7750 | assign out = ~(in0 & in1 & in2); | |
7751 | `endif | |
7752 | ||
7753 | endmodule | |
7754 | module cl_a1_nand3_24x ( | |
7755 | in0, | |
7756 | in1, | |
7757 | in2, | |
7758 | out | |
7759 | ); | |
7760 | input in0; | |
7761 | input in1; | |
7762 | input in2; | |
7763 | output out; | |
7764 | ||
7765 | `ifdef LIB | |
7766 | assign out = ~(in0 & in1 & in2); | |
7767 | `endif | |
7768 | ||
7769 | endmodule | |
7770 | ||
7771 | module cl_a1_nand3_2x ( | |
7772 | in0, | |
7773 | in1, | |
7774 | in2, | |
7775 | out | |
7776 | ); | |
7777 | input in0; | |
7778 | input in1; | |
7779 | input in2; | |
7780 | output out; | |
7781 | ||
7782 | `ifdef LIB | |
7783 | assign out = ~(in0 & in1 & in2); | |
7784 | `endif | |
7785 | ||
7786 | endmodule | |
7787 | ||
7788 | module cl_a1_nand3_4x ( | |
7789 | in0, | |
7790 | in1, | |
7791 | in2, | |
7792 | out | |
7793 | ); | |
7794 | input in0; | |
7795 | input in1; | |
7796 | input in2; | |
7797 | output out; | |
7798 | ||
7799 | `ifdef LIB | |
7800 | assign out = ~(in0 & in1 & in2); | |
7801 | `endif | |
7802 | ||
7803 | endmodule | |
7804 | module cl_a1_nand3_6x ( | |
7805 | in0, | |
7806 | in1, | |
7807 | in2, | |
7808 | out | |
7809 | ); | |
7810 | input in0; | |
7811 | input in1; | |
7812 | input in2; | |
7813 | output out; | |
7814 | ||
7815 | `ifdef LIB | |
7816 | assign out = ~(in0 & in1 & in2); | |
7817 | `endif | |
7818 | ||
7819 | endmodule | |
7820 | module cl_a1_nand3_8x ( | |
7821 | in0, | |
7822 | in1, | |
7823 | in2, | |
7824 | out | |
7825 | ); | |
7826 | input in0; | |
7827 | input in1; | |
7828 | input in2; | |
7829 | output out; | |
7830 | ||
7831 | `ifdef LIB | |
7832 | assign out = ~(in0 & in1 & in2); | |
7833 | `endif | |
7834 | ||
7835 | endmodule | |
7836 | module cl_a1_nand4_12x ( | |
7837 | in0, | |
7838 | in1, | |
7839 | in2, | |
7840 | in3, | |
7841 | out | |
7842 | ); | |
7843 | input in0; | |
7844 | input in1; | |
7845 | input in2; | |
7846 | input in3; | |
7847 | output out; | |
7848 | ||
7849 | `ifdef LIB | |
7850 | assign out = ~(in0 & in1 & in2 & in3); | |
7851 | `endif | |
7852 | ||
7853 | endmodule | |
7854 | module cl_a1_nand4_16x ( | |
7855 | in0, | |
7856 | in1, | |
7857 | in2, | |
7858 | in3, | |
7859 | out | |
7860 | ); | |
7861 | input in0; | |
7862 | input in1; | |
7863 | input in2; | |
7864 | input in3; | |
7865 | output out; | |
7866 | ||
7867 | `ifdef LIB | |
7868 | assign out = ~(in0 & in1 & in2 & in3); | |
7869 | `endif | |
7870 | ||
7871 | endmodule | |
7872 | module cl_a1_nand4_1x ( | |
7873 | in0, | |
7874 | in1, | |
7875 | in2, | |
7876 | in3, | |
7877 | out | |
7878 | ); | |
7879 | input in0; | |
7880 | input in1; | |
7881 | input in2; | |
7882 | input in3; | |
7883 | output out; | |
7884 | ||
7885 | `ifdef LIB | |
7886 | assign out = ~(in0 & in1 & in2 & in3); | |
7887 | `endif | |
7888 | ||
7889 | endmodule | |
7890 | ||
7891 | ||
7892 | module cl_a1_nand4_2x ( | |
7893 | in0, | |
7894 | in1, | |
7895 | in2, | |
7896 | in3, | |
7897 | out | |
7898 | ); | |
7899 | input in0; | |
7900 | input in1; | |
7901 | input in2; | |
7902 | input in3; | |
7903 | output out; | |
7904 | ||
7905 | `ifdef LIB | |
7906 | assign out = ~(in0 & in1 & in2 & in3); | |
7907 | `endif | |
7908 | ||
7909 | endmodule | |
7910 | ||
7911 | module cl_a1_nand4_4x ( | |
7912 | in0, | |
7913 | in1, | |
7914 | in2, | |
7915 | in3, | |
7916 | out | |
7917 | ); | |
7918 | input in0; | |
7919 | input in1; | |
7920 | input in2; | |
7921 | input in3; | |
7922 | output out; | |
7923 | ||
7924 | `ifdef LIB | |
7925 | assign out = ~(in0 & in1 & in2 & in3); | |
7926 | `endif | |
7927 | ||
7928 | endmodule | |
7929 | module cl_a1_nand4_6x ( | |
7930 | in0, | |
7931 | in1, | |
7932 | in2, | |
7933 | in3, | |
7934 | out | |
7935 | ); | |
7936 | input in0; | |
7937 | input in1; | |
7938 | input in2; | |
7939 | input in3; | |
7940 | output out; | |
7941 | ||
7942 | `ifdef LIB | |
7943 | assign out = ~(in0 & in1 & in2 & in3); | |
7944 | `endif | |
7945 | ||
7946 | endmodule | |
7947 | module cl_a1_nand4_8x ( | |
7948 | in0, | |
7949 | in1, | |
7950 | in2, | |
7951 | in3, | |
7952 | out | |
7953 | ); | |
7954 | input in0; | |
7955 | input in1; | |
7956 | input in2; | |
7957 | input in3; | |
7958 | output out; | |
7959 | ||
7960 | `ifdef LIB | |
7961 | assign out = ~(in0 & in1 & in2 & in3); | |
7962 | `endif | |
7963 | ||
7964 | endmodule | |
7965 | module cl_a1_nor2_12x ( | |
7966 | in0, | |
7967 | in1, | |
7968 | out | |
7969 | ); | |
7970 | input in0; | |
7971 | input in1; | |
7972 | output out; | |
7973 | ||
7974 | `ifdef LIB | |
7975 | assign out = ~(in0 | in1); | |
7976 | `endif | |
7977 | ||
7978 | endmodule | |
7979 | module cl_a1_nor2_16x ( | |
7980 | in0, | |
7981 | in1, | |
7982 | out | |
7983 | ); | |
7984 | input in0; | |
7985 | input in1; | |
7986 | output out; | |
7987 | ||
7988 | `ifdef LIB | |
7989 | assign out = ~(in0 | in1); | |
7990 | `endif | |
7991 | ||
7992 | endmodule | |
7993 | module cl_a1_nor2_1x ( | |
7994 | in0, | |
7995 | in1, | |
7996 | out | |
7997 | ); | |
7998 | input in0; | |
7999 | input in1; | |
8000 | output out; | |
8001 | ||
8002 | `ifdef LIB | |
8003 | assign out = ~(in0 | in1); | |
8004 | `endif | |
8005 | ||
8006 | endmodule | |
8007 | module cl_a1_nor2_2x ( | |
8008 | in0, | |
8009 | in1, | |
8010 | out | |
8011 | ); | |
8012 | input in0; | |
8013 | input in1; | |
8014 | output out; | |
8015 | ||
8016 | `ifdef LIB | |
8017 | assign out = ~(in0 | in1); | |
8018 | `endif | |
8019 | ||
8020 | endmodule | |
8021 | module cl_a1_nor2_4x ( | |
8022 | in0, | |
8023 | in1, | |
8024 | out | |
8025 | ); | |
8026 | input in0; | |
8027 | input in1; | |
8028 | output out; | |
8029 | ||
8030 | `ifdef LIB | |
8031 | assign out = ~(in0 | in1); | |
8032 | `endif | |
8033 | ||
8034 | endmodule | |
8035 | module cl_a1_nor2_6x ( | |
8036 | in0, | |
8037 | in1, | |
8038 | out | |
8039 | ); | |
8040 | input in0; | |
8041 | input in1; | |
8042 | output out; | |
8043 | ||
8044 | `ifdef LIB | |
8045 | assign out = ~(in0 | in1); | |
8046 | `endif | |
8047 | ||
8048 | endmodule | |
8049 | module cl_a1_nor2_8x ( | |
8050 | in0, | |
8051 | in1, | |
8052 | out | |
8053 | ); | |
8054 | input in0; | |
8055 | input in1; | |
8056 | output out; | |
8057 | ||
8058 | `ifdef LIB | |
8059 | assign out = ~(in0 | in1); | |
8060 | `endif | |
8061 | ||
8062 | endmodule | |
8063 | module cl_a1_nor3_1x ( | |
8064 | in0, | |
8065 | in1, | |
8066 | in2, | |
8067 | out | |
8068 | ); | |
8069 | input in0; | |
8070 | input in1; | |
8071 | input in2; | |
8072 | output out; | |
8073 | ||
8074 | `ifdef LIB | |
8075 | assign out = ~(in0 | in1 | in2); | |
8076 | `endif | |
8077 | ||
8078 | endmodule | |
8079 | module cl_a1_nor3_2x ( | |
8080 | in0, | |
8081 | in1, | |
8082 | in2, | |
8083 | out | |
8084 | ); | |
8085 | input in0; | |
8086 | input in1; | |
8087 | input in2; | |
8088 | output out; | |
8089 | ||
8090 | `ifdef LIB | |
8091 | assign out = ~(in0 | in1 | in2); | |
8092 | `endif | |
8093 | ||
8094 | endmodule | |
8095 | module cl_a1_nor3_4x ( | |
8096 | in0, | |
8097 | in1, | |
8098 | in2, | |
8099 | out | |
8100 | ); | |
8101 | input in0; | |
8102 | input in1; | |
8103 | input in2; | |
8104 | output out; | |
8105 | ||
8106 | `ifdef LIB | |
8107 | assign out = ~(in0 | in1 | in2); | |
8108 | `endif | |
8109 | ||
8110 | endmodule | |
8111 | // -------------------------------------------------- | |
8112 | // File: cl_a1_oai12_12x.behV | |
8113 | // Auto generated verilog module by HnBCellAuto | |
8114 | // | |
8115 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8116 | // By: balmiki | |
8117 | // -------------------------------------------------- | |
8118 | // | |
8119 | module cl_a1_oai12_12x ( | |
8120 | out, | |
8121 | in10, | |
8122 | in00, | |
8123 | in01 ); | |
8124 | ||
8125 | output out; | |
8126 | input in10; | |
8127 | input in00; | |
8128 | input in01; | |
8129 | ||
8130 | `ifdef LIB | |
8131 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8132 | `endif | |
8133 | ||
8134 | endmodule | |
8135 | // -------------------------------------------------- | |
8136 | // File: cl_a1_oai12_16x.behV | |
8137 | // Auto generated verilog module by HnBCellAuto | |
8138 | // | |
8139 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8140 | // By: balmiki | |
8141 | // -------------------------------------------------- | |
8142 | // | |
8143 | module cl_a1_oai12_16x ( | |
8144 | out, | |
8145 | in10, | |
8146 | in00, | |
8147 | in01 ); | |
8148 | ||
8149 | output out; | |
8150 | input in10; | |
8151 | input in00; | |
8152 | input in01; | |
8153 | ||
8154 | `ifdef LIB | |
8155 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8156 | `endif | |
8157 | ||
8158 | endmodule | |
8159 | // -------------------------------------------------- | |
8160 | // File: cl_a1_oai12_1x.behV | |
8161 | // Auto generated verilog module by HnBCellAuto | |
8162 | // | |
8163 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8164 | // By: balmiki | |
8165 | // -------------------------------------------------- | |
8166 | // | |
8167 | module cl_a1_oai12_1x ( | |
8168 | out, | |
8169 | in10, | |
8170 | in00, | |
8171 | in01 ); | |
8172 | ||
8173 | output out; | |
8174 | input in10; | |
8175 | input in00; | |
8176 | input in01; | |
8177 | ||
8178 | `ifdef LIB | |
8179 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8180 | `endif | |
8181 | ||
8182 | endmodule | |
8183 | // -------------------------------------------------- | |
8184 | // File: cl_a1_oai12_2x.behV | |
8185 | // Auto generated verilog module by HnBCellAuto | |
8186 | // | |
8187 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8188 | // By: balmiki | |
8189 | // -------------------------------------------------- | |
8190 | // | |
8191 | module cl_a1_oai12_2x ( | |
8192 | out, | |
8193 | in10, | |
8194 | in00, | |
8195 | in01 ); | |
8196 | ||
8197 | output out; | |
8198 | input in10; | |
8199 | input in00; | |
8200 | input in01; | |
8201 | ||
8202 | `ifdef LIB | |
8203 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8204 | `endif | |
8205 | ||
8206 | endmodule | |
8207 | // -------------------------------------------------- | |
8208 | // File: cl_a1_oai12_4x.behV | |
8209 | // Auto generated verilog module by HnBCellAuto | |
8210 | // | |
8211 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8212 | // By: balmiki | |
8213 | // -------------------------------------------------- | |
8214 | // | |
8215 | module cl_a1_oai12_4x ( | |
8216 | out, | |
8217 | in10, | |
8218 | in00, | |
8219 | in01 ); | |
8220 | ||
8221 | output out; | |
8222 | input in10; | |
8223 | input in00; | |
8224 | input in01; | |
8225 | ||
8226 | `ifdef LIB | |
8227 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8228 | `endif | |
8229 | ||
8230 | endmodule | |
8231 | // -------------------------------------------------- | |
8232 | // File: cl_a1_oai12_8x.behV | |
8233 | // Auto generated verilog module by HnBCellAuto | |
8234 | // | |
8235 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
8236 | // By: balmiki | |
8237 | // -------------------------------------------------- | |
8238 | // | |
8239 | module cl_a1_oai12_8x ( | |
8240 | out, | |
8241 | in10, | |
8242 | in00, | |
8243 | in01 ); | |
8244 | ||
8245 | output out; | |
8246 | input in10; | |
8247 | input in00; | |
8248 | input in01; | |
8249 | ||
8250 | `ifdef LIB | |
8251 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
8252 | `endif | |
8253 | ||
8254 | endmodule | |
8255 | // -------------------------------------------------- | |
8256 | // File: cl_a1_oai21_12x.behV | |
8257 | // Auto generated verilog module by HnBCellAuto | |
8258 | // | |
8259 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
8260 | // By: balmiki | |
8261 | // -------------------------------------------------- | |
8262 | // | |
8263 | module cl_a1_oai21_12x ( | |
8264 | out, | |
8265 | in10, | |
8266 | in11, | |
8267 | in00 ); | |
8268 | ||
8269 | output out; | |
8270 | input in10; | |
8271 | input in11; | |
8272 | input in00; | |
8273 | ||
8274 | `ifdef LIB | |
8275 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8276 | `endif | |
8277 | ||
8278 | endmodule | |
8279 | // -------------------------------------------------- | |
8280 | // File: cl_a1_oai21_16x.behV | |
8281 | // Auto generated verilog module by HnBCellAuto | |
8282 | // | |
8283 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
8284 | // By: balmiki | |
8285 | // -------------------------------------------------- | |
8286 | // | |
8287 | module cl_a1_oai21_16x ( | |
8288 | out, | |
8289 | in10, | |
8290 | in11, | |
8291 | in00 ); | |
8292 | ||
8293 | output out; | |
8294 | input in10; | |
8295 | input in11; | |
8296 | input in00; | |
8297 | ||
8298 | `ifdef LIB | |
8299 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8300 | `endif | |
8301 | ||
8302 | endmodule | |
8303 | // -------------------------------------------------- | |
8304 | // File: cl_a1_oai21_1x.behV | |
8305 | // Auto generated verilog module by HnBCellAuto | |
8306 | // | |
8307 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST | |
8308 | // By: balmiki | |
8309 | // -------------------------------------------------- | |
8310 | // | |
8311 | module cl_a1_oai21_1x ( | |
8312 | out, | |
8313 | in10, | |
8314 | in11, | |
8315 | in00 ); | |
8316 | ||
8317 | output out; | |
8318 | input in10; | |
8319 | input in11; | |
8320 | input in00; | |
8321 | ||
8322 | `ifdef LIB | |
8323 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8324 | `endif | |
8325 | ||
8326 | endmodule | |
8327 | // -------------------------------------------------- | |
8328 | // File: cl_a1_oai21_2x.behV | |
8329 | // Auto generated verilog module by HnBCellAuto | |
8330 | // | |
8331 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
8332 | // By: balmiki | |
8333 | // -------------------------------------------------- | |
8334 | // | |
8335 | module cl_a1_oai21_2x ( | |
8336 | out, | |
8337 | in10, | |
8338 | in11, | |
8339 | in00 ); | |
8340 | ||
8341 | output out; | |
8342 | input in10; | |
8343 | input in11; | |
8344 | input in00; | |
8345 | ||
8346 | `ifdef LIB | |
8347 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8348 | `endif | |
8349 | ||
8350 | endmodule | |
8351 | // -------------------------------------------------- | |
8352 | // File: cl_a1_oai21_4x.behV | |
8353 | // Auto generated verilog module by HnBCellAuto | |
8354 | // | |
8355 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
8356 | // By: balmiki | |
8357 | // -------------------------------------------------- | |
8358 | // | |
8359 | module cl_a1_oai21_4x ( | |
8360 | out, | |
8361 | in10, | |
8362 | in11, | |
8363 | in00 ); | |
8364 | ||
8365 | output out; | |
8366 | input in10; | |
8367 | input in11; | |
8368 | input in00; | |
8369 | ||
8370 | `ifdef LIB | |
8371 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8372 | `endif | |
8373 | ||
8374 | endmodule | |
8375 | // -------------------------------------------------- | |
8376 | // File: cl_a1_oai21_8x.behV | |
8377 | // Auto generated verilog module by HnBCellAuto | |
8378 | // | |
8379 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
8380 | // By: balmiki | |
8381 | // -------------------------------------------------- | |
8382 | // | |
8383 | module cl_a1_oai21_8x ( | |
8384 | out, | |
8385 | in10, | |
8386 | in11, | |
8387 | in00 ); | |
8388 | ||
8389 | output out; | |
8390 | input in10; | |
8391 | input in11; | |
8392 | input in00; | |
8393 | ||
8394 | `ifdef LIB | |
8395 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
8396 | `endif | |
8397 | ||
8398 | endmodule | |
8399 | // -------------------------------------------------- | |
8400 | // File: cl_a1_oai22_12x.behV | |
8401 | // Auto generated verilog module by HnBCellAuto | |
8402 | // | |
8403 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
8404 | // By: balmiki | |
8405 | // -------------------------------------------------- | |
8406 | // | |
8407 | module cl_a1_oai22_12x ( | |
8408 | out, | |
8409 | in10, | |
8410 | in11, | |
8411 | in00, | |
8412 | in01 ); | |
8413 | ||
8414 | output out; | |
8415 | input in10; | |
8416 | input in11; | |
8417 | input in00; | |
8418 | input in01; | |
8419 | ||
8420 | `ifdef LIB | |
8421 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8422 | `endif | |
8423 | ||
8424 | endmodule | |
8425 | // -------------------------------------------------- | |
8426 | // File: cl_a1_oai22_16x.behV | |
8427 | // Auto generated verilog module by HnBCellAuto | |
8428 | // | |
8429 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
8430 | // By: balmiki | |
8431 | // -------------------------------------------------- | |
8432 | // | |
8433 | module cl_a1_oai22_16x ( | |
8434 | out, | |
8435 | in10, | |
8436 | in11, | |
8437 | in00, | |
8438 | in01 ); | |
8439 | ||
8440 | output out; | |
8441 | input in10; | |
8442 | input in11; | |
8443 | input in00; | |
8444 | input in01; | |
8445 | ||
8446 | `ifdef LIB | |
8447 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8448 | `endif | |
8449 | ||
8450 | endmodule | |
8451 | // -------------------------------------------------- | |
8452 | // File: cl_a1_oai22_1x.behV | |
8453 | // Auto generated verilog module by HnBCellAuto | |
8454 | // | |
8455 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
8456 | // By: balmiki | |
8457 | // -------------------------------------------------- | |
8458 | // | |
8459 | module cl_a1_oai22_1x ( | |
8460 | out, | |
8461 | in10, | |
8462 | in11, | |
8463 | in00, | |
8464 | in01 ); | |
8465 | ||
8466 | output out; | |
8467 | input in10; | |
8468 | input in11; | |
8469 | input in00; | |
8470 | input in01; | |
8471 | ||
8472 | `ifdef LIB | |
8473 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8474 | `endif | |
8475 | ||
8476 | endmodule | |
8477 | // -------------------------------------------------- | |
8478 | // File: cl_a1_oai22_2x.behV | |
8479 | // Auto generated verilog module by HnBCellAuto | |
8480 | // | |
8481 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
8482 | // By: balmiki | |
8483 | // -------------------------------------------------- | |
8484 | // | |
8485 | module cl_a1_oai22_2x ( | |
8486 | out, | |
8487 | in10, | |
8488 | in11, | |
8489 | in00, | |
8490 | in01 ); | |
8491 | ||
8492 | output out; | |
8493 | input in10; | |
8494 | input in11; | |
8495 | input in00; | |
8496 | input in01; | |
8497 | ||
8498 | `ifdef LIB | |
8499 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8500 | `endif | |
8501 | ||
8502 | endmodule | |
8503 | // -------------------------------------------------- | |
8504 | // File: cl_a1_oai22_4x.behV | |
8505 | // Auto generated verilog module by HnBCellAuto | |
8506 | // | |
8507 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
8508 | // By: balmiki | |
8509 | // -------------------------------------------------- | |
8510 | // | |
8511 | module cl_a1_oai22_4x ( | |
8512 | out, | |
8513 | in10, | |
8514 | in11, | |
8515 | in00, | |
8516 | in01 ); | |
8517 | ||
8518 | output out; | |
8519 | input in10; | |
8520 | input in11; | |
8521 | input in00; | |
8522 | input in01; | |
8523 | ||
8524 | `ifdef LIB | |
8525 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8526 | `endif | |
8527 | ||
8528 | endmodule | |
8529 | // -------------------------------------------------- | |
8530 | // File: cl_a1_oai22_8x.behV | |
8531 | // Auto generated verilog module by HnBCellAuto | |
8532 | // | |
8533 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
8534 | // By: balmiki | |
8535 | // -------------------------------------------------- | |
8536 | // | |
8537 | module cl_a1_oai22_8x ( | |
8538 | out, | |
8539 | in10, | |
8540 | in11, | |
8541 | in00, | |
8542 | in01 ); | |
8543 | ||
8544 | output out; | |
8545 | input in10; | |
8546 | input in11; | |
8547 | input in00; | |
8548 | input in01; | |
8549 | ||
8550 | `ifdef LIB | |
8551 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
8552 | `endif | |
8553 | ||
8554 | endmodule | |
8555 | module cl_a1_xnor2_16x ( | |
8556 | in0, | |
8557 | in1, | |
8558 | out | |
8559 | ); | |
8560 | input in0; | |
8561 | input in1; | |
8562 | output out; | |
8563 | ||
8564 | `ifdef LIB | |
8565 | assign out = ~(in0 ^ in1); | |
8566 | `endif | |
8567 | ||
8568 | endmodule | |
8569 | ||
8570 | module cl_a1_xnor2_1x ( | |
8571 | in0, | |
8572 | in1, | |
8573 | out | |
8574 | ); | |
8575 | input in0; | |
8576 | input in1; | |
8577 | output out; | |
8578 | ||
8579 | `ifdef LIB | |
8580 | assign out = ~(in0 ^ in1); | |
8581 | `endif | |
8582 | ||
8583 | endmodule | |
8584 | module cl_a1_xnor2_2x ( | |
8585 | in0, | |
8586 | in1, | |
8587 | out | |
8588 | ); | |
8589 | input in0; | |
8590 | input in1; | |
8591 | output out; | |
8592 | ||
8593 | `ifdef LIB | |
8594 | assign out = ~(in0 ^ in1); | |
8595 | `endif | |
8596 | ||
8597 | endmodule | |
8598 | module cl_a1_xnor2_4x ( | |
8599 | in0, | |
8600 | in1, | |
8601 | out | |
8602 | ); | |
8603 | input in0; | |
8604 | input in1; | |
8605 | output out; | |
8606 | ||
8607 | `ifdef LIB | |
8608 | assign out = ~(in0 ^ in1); | |
8609 | `endif | |
8610 | ||
8611 | endmodule | |
8612 | module cl_a1_xnor2_6x ( | |
8613 | in0, | |
8614 | in1, | |
8615 | out | |
8616 | ); | |
8617 | input in0; | |
8618 | input in1; | |
8619 | output out; | |
8620 | ||
8621 | `ifdef LIB | |
8622 | assign out = ~(in0 ^ in1); | |
8623 | `endif | |
8624 | ||
8625 | endmodule | |
8626 | module cl_a1_xnor2_8x ( | |
8627 | in0, | |
8628 | in1, | |
8629 | out | |
8630 | ); | |
8631 | input in0; | |
8632 | input in1; | |
8633 | output out; | |
8634 | ||
8635 | `ifdef LIB | |
8636 | assign out = ~(in0 ^ in1); | |
8637 | `endif | |
8638 | ||
8639 | endmodule | |
8640 | ||
8641 | module cl_a1_xnor3_16x ( | |
8642 | in0, | |
8643 | in1, | |
8644 | in2, | |
8645 | out | |
8646 | ); | |
8647 | input in0; | |
8648 | input in1; | |
8649 | input in2; | |
8650 | output out; | |
8651 | ||
8652 | `ifdef LIB | |
8653 | assign out = ~(in0 ^ in1 ^ in2); | |
8654 | `endif | |
8655 | ||
8656 | ||
8657 | ||
8658 | endmodule | |
8659 | module cl_a1_xnor3_1x ( | |
8660 | in0, | |
8661 | in1, | |
8662 | in2, | |
8663 | out | |
8664 | ); | |
8665 | input in0; | |
8666 | input in1; | |
8667 | input in2; | |
8668 | output out; | |
8669 | ||
8670 | `ifdef LIB | |
8671 | assign out = ~(in0 ^ in1 ^ in2); | |
8672 | `endif | |
8673 | ||
8674 | ||
8675 | ||
8676 | endmodule | |
8677 | module cl_a1_xnor3_2x ( | |
8678 | in0, | |
8679 | in1, | |
8680 | in2, | |
8681 | out | |
8682 | ); | |
8683 | input in0; | |
8684 | input in1; | |
8685 | input in2; | |
8686 | output out; | |
8687 | ||
8688 | `ifdef LIB | |
8689 | assign out = ~(in0 ^ in1 ^ in2); | |
8690 | `endif | |
8691 | ||
8692 | ||
8693 | ||
8694 | endmodule | |
8695 | module cl_a1_xnor3_4x ( | |
8696 | in0, | |
8697 | in1, | |
8698 | in2, | |
8699 | out | |
8700 | ); | |
8701 | input in0; | |
8702 | input in1; | |
8703 | input in2; | |
8704 | output out; | |
8705 | ||
8706 | `ifdef LIB | |
8707 | assign out = ~(in0 ^ in1 ^ in2); | |
8708 | `endif | |
8709 | ||
8710 | ||
8711 | ||
8712 | endmodule | |
8713 | module cl_a1_xnor3_6x ( | |
8714 | in0, | |
8715 | in1, | |
8716 | in2, | |
8717 | out | |
8718 | ); | |
8719 | input in0; | |
8720 | input in1; | |
8721 | input in2; | |
8722 | output out; | |
8723 | ||
8724 | `ifdef LIB | |
8725 | assign out = ~(in0 ^ in1 ^ in2); | |
8726 | `endif | |
8727 | ||
8728 | ||
8729 | ||
8730 | endmodule | |
8731 | module cl_a1_xnor3_8x ( | |
8732 | in0, | |
8733 | in1, | |
8734 | in2, | |
8735 | out | |
8736 | ); | |
8737 | input in0; | |
8738 | input in1; | |
8739 | input in2; | |
8740 | output out; | |
8741 | ||
8742 | `ifdef LIB | |
8743 | assign out = ~(in0 ^ in1 ^ in2); | |
8744 | `endif | |
8745 | ||
8746 | ||
8747 | ||
8748 | endmodule | |
8749 | module cl_a1_xor2_16x ( | |
8750 | in0, | |
8751 | in1, | |
8752 | out | |
8753 | ); | |
8754 | input in0; | |
8755 | input in1; | |
8756 | output out; | |
8757 | ||
8758 | `ifdef LIB | |
8759 | assign out = in0 ^ in1; | |
8760 | `endif | |
8761 | ||
8762 | endmodule | |
8763 | ||
8764 | module cl_a1_xor2_1x ( | |
8765 | in0, | |
8766 | in1, | |
8767 | out | |
8768 | ); | |
8769 | input in0; | |
8770 | input in1; | |
8771 | output out; | |
8772 | ||
8773 | `ifdef LIB | |
8774 | assign out = in0 ^ in1; | |
8775 | `endif | |
8776 | ||
8777 | endmodule | |
8778 | module cl_a1_xor2_2x ( | |
8779 | in0, | |
8780 | in1, | |
8781 | out | |
8782 | ); | |
8783 | input in0; | |
8784 | input in1; | |
8785 | output out; | |
8786 | ||
8787 | `ifdef LIB | |
8788 | assign out = in0 ^ in1; | |
8789 | `endif | |
8790 | ||
8791 | endmodule | |
8792 | module cl_a1_xor2_4x ( | |
8793 | in0, | |
8794 | in1, | |
8795 | out | |
8796 | ); | |
8797 | input in0; | |
8798 | input in1; | |
8799 | output out; | |
8800 | ||
8801 | `ifdef LIB | |
8802 | assign out = in0 ^ in1; | |
8803 | `endif | |
8804 | ||
8805 | endmodule | |
8806 | module cl_a1_xor2_6x ( | |
8807 | in0, | |
8808 | in1, | |
8809 | out | |
8810 | ); | |
8811 | input in0; | |
8812 | input in1; | |
8813 | output out; | |
8814 | ||
8815 | `ifdef LIB | |
8816 | assign out = in0 ^ in1; | |
8817 | `endif | |
8818 | ||
8819 | endmodule | |
8820 | module cl_a1_xor2_8x ( | |
8821 | in0, | |
8822 | in1, | |
8823 | out | |
8824 | ); | |
8825 | input in0; | |
8826 | input in1; | |
8827 | output out; | |
8828 | ||
8829 | `ifdef LIB | |
8830 | assign out = in0 ^ in1; | |
8831 | `endif | |
8832 | ||
8833 | endmodule | |
8834 | module cl_a1_xor3_16x ( | |
8835 | in0, | |
8836 | in1, | |
8837 | in2, | |
8838 | out | |
8839 | ); | |
8840 | input in0; | |
8841 | input in1; | |
8842 | input in2; | |
8843 | output out; | |
8844 | ||
8845 | `ifdef LIB | |
8846 | assign out = in0 ^ in1 ^ in2; | |
8847 | `endif | |
8848 | ||
8849 | ||
8850 | endmodule | |
8851 | ||
8852 | module cl_a1_xor3_1x ( | |
8853 | in0, | |
8854 | in1, | |
8855 | in2, | |
8856 | out | |
8857 | ); | |
8858 | input in0; | |
8859 | input in1; | |
8860 | input in2; | |
8861 | output out; | |
8862 | ||
8863 | `ifdef LIB | |
8864 | assign out = in0 ^ in1 ^ in2; | |
8865 | `endif | |
8866 | ||
8867 | ||
8868 | endmodule | |
8869 | module cl_a1_xor3_2x ( | |
8870 | in0, | |
8871 | in1, | |
8872 | in2, | |
8873 | out | |
8874 | ); | |
8875 | input in0; | |
8876 | input in1; | |
8877 | input in2; | |
8878 | output out; | |
8879 | ||
8880 | `ifdef LIB | |
8881 | assign out = in0 ^ in1 ^ in2; | |
8882 | `endif | |
8883 | ||
8884 | ||
8885 | endmodule | |
8886 | module cl_a1_xor3_4x ( | |
8887 | in0, | |
8888 | in1, | |
8889 | in2, | |
8890 | out | |
8891 | ); | |
8892 | input in0; | |
8893 | input in1; | |
8894 | input in2; | |
8895 | output out; | |
8896 | ||
8897 | `ifdef LIB | |
8898 | assign out = in0 ^ in1 ^ in2; | |
8899 | `endif | |
8900 | ||
8901 | ||
8902 | endmodule | |
8903 | module cl_a1_xor3_6x ( | |
8904 | in0, | |
8905 | in1, | |
8906 | in2, | |
8907 | out | |
8908 | ); | |
8909 | input in0; | |
8910 | input in1; | |
8911 | input in2; | |
8912 | output out; | |
8913 | ||
8914 | `ifdef LIB | |
8915 | assign out = in0 ^ in1 ^ in2; | |
8916 | `endif | |
8917 | ||
8918 | ||
8919 | endmodule | |
8920 | module cl_a1_xor3_8x ( | |
8921 | in0, | |
8922 | in1, | |
8923 | in2, | |
8924 | out | |
8925 | ); | |
8926 | input in0; | |
8927 | input in1; | |
8928 | input in2; | |
8929 | output out; | |
8930 | ||
8931 | `ifdef LIB | |
8932 | assign out = in0 ^ in1 ^ in2; | |
8933 | `endif | |
8934 | ||
8935 | ||
8936 | endmodule | |
8937 | ||
8938 | ||
8939 | ||
8940 | module cl_a1_muxprotect_2x ( | |
8941 | d0, | |
8942 | d1, | |
8943 | d2, | |
8944 | d3, | |
8945 | scan_en, | |
8946 | e0, | |
8947 | e1, | |
8948 | e2, | |
8949 | e3 | |
8950 | ); | |
8951 | input d0; | |
8952 | input d1; | |
8953 | input d2; | |
8954 | input d3; | |
8955 | input scan_en; | |
8956 | output e0; | |
8957 | output e1; | |
8958 | output e2; | |
8959 | output e3; | |
8960 | ||
8961 | `ifdef LIB | |
8962 | assign e0 = scan_en | d0; | |
8963 | assign e1= ~scan_en & d1; | |
8964 | assign e2= ~scan_en & d2; | |
8965 | assign e3= ~scan_en & d3; | |
8966 | `endif | |
8967 | ||
8968 | endmodule | |
8969 | ||
8970 | module cl_a1_add64_8x ( | |
8971 | cin, | |
8972 | in0, | |
8973 | in1, | |
8974 | out, | |
8975 | cout | |
8976 | ); | |
8977 | input cin; | |
8978 | input [63:0] in0; | |
8979 | input [63:0] in1; | |
8980 | output [63:0] out; | |
8981 | output cout; | |
8982 | ||
8983 | `ifdef LIB | |
8984 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
8985 | `endif | |
8986 | ||
8987 | endmodule | |
8988 | ||
8989 | ||
8990 | ||
8991 | ||
8992 | ||
8993 | ||
8994 |