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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_dp1.behV | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
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31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_dp1_msffmin_30ps_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
36 | // RFM 05-14-2004 | |
37 | // Level sensitive in SCAN_MODE | |
38 | // Edge triggered when not in SCAN_MODE | |
39 | ||
40 | ||
41 | parameter SIZE = 1; | |
42 | ||
43 | output q; | |
44 | output so; | |
45 | ||
46 | input d; | |
47 | input l1clk; | |
48 | input si; | |
49 | input siclk; | |
50 | input soclk; | |
51 | ||
52 | reg q; | |
53 | wire so; | |
54 | wire l1clk, siclk, soclk; | |
55 | ||
56 | `ifdef SCAN_MODE | |
57 | ||
58 | reg l1; | |
59 | `ifdef FAST_FLUSH | |
60 | always @(posedge l1clk or posedge siclk ) begin | |
61 | if (siclk) begin | |
62 | q <= 1'b0; //pseudo flush reset | |
63 | end else begin | |
64 | q <= d; | |
65 | end | |
66 | end | |
67 | `else | |
68 | always @(l1clk or siclk or soclk or d or si) | |
69 | begin | |
70 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
71 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
72 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
73 | ||
74 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
75 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
76 | end | |
77 | `endif | |
78 | `else | |
79 | wire si_unused; | |
80 | wire siclk_unused; | |
81 | wire soclk_unused; | |
82 | assign si_unused = si; | |
83 | assign siclk_unused = siclk; | |
84 | assign soclk_unused = soclk; | |
85 | ||
86 | ||
87 | `ifdef INITLATZERO | |
88 | initial q = 1'b0; | |
89 | `endif | |
90 | ||
91 | always @(posedge l1clk) | |
92 | begin | |
93 | if (!siclk && !soclk) q <= d; | |
94 | else q <= 1'bx; | |
95 | end | |
96 | `endif | |
97 | ||
98 | assign so = q; | |
99 | ||
100 | endmodule // dff | |
101 | ||
102 | ||
103 | ||
104 | ||
105 | module cl_dp1_msffmin_30ps_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
106 | // RFM 05-14-2004 | |
107 | // Level sensitive in SCAN_MODE | |
108 | // Edge triggered when not in SCAN_MODE | |
109 | ||
110 | ||
111 | parameter SIZE = 1; | |
112 | ||
113 | output q; | |
114 | output so; | |
115 | ||
116 | input d; | |
117 | input l1clk; | |
118 | input si; | |
119 | input siclk; | |
120 | input soclk; | |
121 | ||
122 | reg q; | |
123 | wire so; | |
124 | wire l1clk, siclk, soclk; | |
125 | ||
126 | `ifdef SCAN_MODE | |
127 | ||
128 | reg l1; | |
129 | `ifdef FAST_FLUSH | |
130 | always @(posedge l1clk or posedge siclk ) begin | |
131 | if (siclk) begin | |
132 | q <= 1'b0; //pseudo flush reset | |
133 | end else begin | |
134 | q <= d; | |
135 | end | |
136 | end | |
137 | `else | |
138 | always @(l1clk or siclk or soclk or d or si) | |
139 | begin | |
140 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
141 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
142 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
143 | ||
144 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
145 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
146 | end | |
147 | `endif | |
148 | `else | |
149 | wire si_unused; | |
150 | wire siclk_unused; | |
151 | wire soclk_unused; | |
152 | assign si_unused = si; | |
153 | assign siclk_unused = siclk; | |
154 | assign soclk_unused = soclk; | |
155 | ||
156 | ||
157 | `ifdef INITLATZERO | |
158 | initial q = 1'b0; | |
159 | `endif | |
160 | ||
161 | always @(posedge l1clk) | |
162 | begin | |
163 | if (!siclk && !soclk) q <= d; | |
164 | else q <= 1'bx; | |
165 | end | |
166 | `endif | |
167 | ||
168 | assign so = q; | |
169 | ||
170 | endmodule // dff | |
171 | module cl_dp1_msffmin_30ps_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
172 | // RFM 05-14-2004 | |
173 | // Level sensitive in SCAN_MODE | |
174 | // Edge triggered when not in SCAN_MODE | |
175 | ||
176 | ||
177 | parameter SIZE = 1; | |
178 | ||
179 | output q; | |
180 | output so; | |
181 | ||
182 | input d; | |
183 | input l1clk; | |
184 | input si; | |
185 | input siclk; | |
186 | input soclk; | |
187 | ||
188 | reg q; | |
189 | wire so; | |
190 | wire l1clk, siclk, soclk; | |
191 | ||
192 | `ifdef SCAN_MODE | |
193 | ||
194 | reg l1; | |
195 | `ifdef FAST_FLUSH | |
196 | always @(posedge l1clk or posedge siclk ) begin | |
197 | if (siclk) begin | |
198 | q <= 1'b0; //pseudo flush reset | |
199 | end else begin | |
200 | q <= d; | |
201 | end | |
202 | end | |
203 | `else | |
204 | always @(l1clk or siclk or soclk or d or si) | |
205 | begin | |
206 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
207 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
208 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
209 | ||
210 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
211 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
212 | end | |
213 | `endif | |
214 | `else | |
215 | wire si_unused; | |
216 | wire siclk_unused; | |
217 | wire soclk_unused; | |
218 | assign si_unused = si; | |
219 | assign siclk_unused = siclk; | |
220 | assign soclk_unused = soclk; | |
221 | ||
222 | ||
223 | `ifdef INITLATZERO | |
224 | initial q = 1'b0; | |
225 | `endif | |
226 | ||
227 | always @(posedge l1clk) | |
228 | begin | |
229 | if (!siclk && !soclk) q <= d; | |
230 | else q <= 1'bx; | |
231 | end | |
232 | `endif | |
233 | ||
234 | assign so = q; | |
235 | ||
236 | endmodule // dff | |
237 | module cl_dp1_msffmin_30ps_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
238 | // RFM 05-14-2004 | |
239 | // Level sensitive in SCAN_MODE | |
240 | // Edge triggered when not in SCAN_MODE | |
241 | ||
242 | ||
243 | parameter SIZE = 1; | |
244 | ||
245 | output q; | |
246 | output so; | |
247 | ||
248 | input d; | |
249 | input l1clk; | |
250 | input si; | |
251 | input siclk; | |
252 | input soclk; | |
253 | ||
254 | reg q; | |
255 | wire so; | |
256 | wire l1clk, siclk, soclk; | |
257 | ||
258 | `ifdef SCAN_MODE | |
259 | ||
260 | reg l1; | |
261 | `ifdef FAST_FLUSH | |
262 | always @(posedge l1clk or posedge siclk ) begin | |
263 | if (siclk) begin | |
264 | q <= 1'b0; //pseudo flush reset | |
265 | end else begin | |
266 | q <= d; | |
267 | end | |
268 | end | |
269 | `else | |
270 | always @(l1clk or siclk or soclk or d or si) | |
271 | begin | |
272 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
273 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
274 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
275 | ||
276 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
277 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
278 | end | |
279 | `endif | |
280 | `else | |
281 | wire si_unused; | |
282 | wire siclk_unused; | |
283 | wire soclk_unused; | |
284 | assign si_unused = si; | |
285 | assign siclk_unused = siclk; | |
286 | assign soclk_unused = soclk; | |
287 | ||
288 | ||
289 | `ifdef INITLATZERO | |
290 | initial q = 1'b0; | |
291 | `endif | |
292 | ||
293 | always @(posedge l1clk) | |
294 | begin | |
295 | if (!siclk && !soclk) q <= d; | |
296 | else q <= 1'bx; | |
297 | end | |
298 | `endif | |
299 | ||
300 | assign so = q; | |
301 | ||
302 | endmodule // dff | |
303 | module cl_dp1_msffmin_30ps_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
304 | // RFM 05-14-2004 | |
305 | // Level sensitive in SCAN_MODE | |
306 | // Edge triggered when not in SCAN_MODE | |
307 | ||
308 | ||
309 | parameter SIZE = 1; | |
310 | ||
311 | output q; | |
312 | output so; | |
313 | ||
314 | input d; | |
315 | input l1clk; | |
316 | input si; | |
317 | input siclk; | |
318 | input soclk; | |
319 | ||
320 | reg q; | |
321 | wire so; | |
322 | wire l1clk, siclk, soclk; | |
323 | ||
324 | `ifdef SCAN_MODE | |
325 | ||
326 | reg l1; | |
327 | `ifdef FAST_FLUSH | |
328 | always @(posedge l1clk or posedge siclk ) begin | |
329 | if (siclk) begin | |
330 | q <= 1'b0; //pseudo flush reset | |
331 | end else begin | |
332 | q <= d; | |
333 | end | |
334 | end | |
335 | `else | |
336 | always @(l1clk or siclk or soclk or d or si) | |
337 | begin | |
338 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
339 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
340 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
341 | ||
342 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
343 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
344 | end | |
345 | `endif | |
346 | `else | |
347 | wire si_unused; | |
348 | wire siclk_unused; | |
349 | wire soclk_unused; | |
350 | assign si_unused = si; | |
351 | assign siclk_unused = siclk; | |
352 | assign soclk_unused = soclk; | |
353 | ||
354 | ||
355 | `ifdef INITLATZERO | |
356 | initial q = 1'b0; | |
357 | `endif | |
358 | ||
359 | always @(posedge l1clk) | |
360 | begin | |
361 | if (!siclk && !soclk) q <= d; | |
362 | else q <= 1'bx; | |
363 | end | |
364 | `endif | |
365 | ||
366 | assign so = q; | |
367 | ||
368 | endmodule // dff | |
369 | module cl_dp1_bsac_cell_4x(q, so, d, l1clk, si, siclk, soclk, updateclk, | |
370 | ac_mode, ac_test_signal); | |
371 | output q; | |
372 | output so; | |
373 | ||
374 | input d, ac_test_signal; | |
375 | input l1clk; | |
376 | input si; | |
377 | input siclk; | |
378 | input soclk; | |
379 | input updateclk, ac_mode; | |
380 | ||
381 | reg q; | |
382 | reg so; | |
383 | wire l1clk, siclk, soclk, updateclk; | |
384 | ||
385 | ||
386 | reg l1, qm; | |
387 | ||
388 | always @(l1clk or siclk or soclk or d or si) | |
389 | begin | |
390 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
391 | if ( l1clk && siclk) l1 <= si; // Load master with | |
392 | // scan or flush | |
393 | if (!l1clk && siclk) l1 <= 1'bx; // Conflict between | |
394 | // data and scan | |
395 | if ( l1clk && !soclk) so <= l1; // Load slave with | |
396 | // master data | |
397 | if ( l1clk && siclk && !soclk) so <= si; // Flush | |
398 | end | |
399 | ||
400 | initial qm = 1'b0; | |
401 | ||
402 | always@(updateclk or l1) | |
403 | begin | |
404 | if(updateclk) qm <=l1; | |
405 | end | |
406 | always@(ac_mode or qm or ac_test_signal) | |
407 | begin | |
408 | if(ac_mode==0) q=qm; | |
409 | else q=qm ^ ac_test_signal; | |
410 | end | |
411 | endmodule | |
412 | module cl_dp1_blatch_4x ( latout, so, d, l1clk, si, siclk, soclk); | |
413 | ||
414 | output latout; | |
415 | output so; | |
416 | input d; | |
417 | input l1clk; | |
418 | input si; | |
419 | input siclk; | |
420 | input soclk; | |
421 | ||
422 | ||
423 | wire so; | |
424 | reg s, m; | |
425 | /* | |
426 | `ifdef SCAN_MODE | |
427 | */ | |
428 | always @(l1clk or siclk or soclk or d or si) begin | |
429 | ||
430 | if (!l1clk && !siclk) m <= d; // Load master with data | |
431 | else if ( l1clk && siclk) m <= si; // Load master with scan or flush | |
432 | else if (!l1clk && siclk) m <= 1'bx; // Conflict between data and scan | |
433 | ||
434 | if ( l1clk && !soclk && !siclk) s <= m; // Load slave with master data | |
435 | else if (l1clk && siclk && !soclk) s <= si; // Flush | |
436 | end | |
437 | /* | |
438 | `else | |
439 | wire si_unused = si; | |
440 | `ifdef INITLATZERO | |
441 | ||
442 | */ | |
443 | initial m = 1'b0; | |
444 | // `endif | |
445 | ||
446 | ||
447 | always @(l1clk or d or si or siclk) begin | |
448 | if(siclk==0 && l1clk==0) m = d; | |
449 | else if(siclk && !l1clk) m = 1'bx; | |
450 | if(siclk && l1clk) m = si; | |
451 | if(l1clk && !soclk) s = m; | |
452 | end | |
453 | ||
454 | // `endif | |
455 | ||
456 | assign latout = m; | |
457 | assign so = s; | |
458 | ||
459 | ||
460 | endmodule | |
461 | module cl_dp1_alatch_4x ( q, so, d, l1clk, si, siclk, soclk, se ); | |
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | output q; | |
468 | output so; | |
469 | ||
470 | input d; | |
471 | input l1clk; | |
472 | input si; | |
473 | input siclk; | |
474 | input soclk; | |
475 | input se; | |
476 | ||
477 | reg q; | |
478 | wire so; | |
479 | wire l1clk, siclk, soclk; | |
480 | ||
481 | ||
482 | ||
483 | reg l1; | |
484 | ||
485 | always @(l1clk or siclk or soclk or d or si or se) | |
486 | begin | |
487 | ||
488 | if (siclk) l1 <= si; // Load master with scan or flush | |
489 | ||
490 | if(se && !soclk && l1clk && siclk) q <= si; | |
491 | else if ( se && !soclk && l1clk) q <= l1; | |
492 | else if ( !soclk && l1clk) q <= d; | |
493 | end | |
494 | ||
495 | ||
496 | ||
497 | ||
498 | `ifdef INITLATZERO | |
499 | initial q = 1'b0; | |
500 | `endif | |
501 | ||
502 | ||
503 | ||
504 | assign so = q; | |
505 | ||
506 | endmodule // dff | |
507 | module cl_dp1_msffmin_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
508 | // RFM 05-14-2004 | |
509 | // Level sensitive in SCAN_MODE | |
510 | // Edge triggered when not in SCAN_MODE | |
511 | ||
512 | ||
513 | parameter SIZE = 1; | |
514 | ||
515 | output q; | |
516 | output so; | |
517 | ||
518 | input d; | |
519 | input l1clk; | |
520 | input si; | |
521 | input siclk; | |
522 | input soclk; | |
523 | ||
524 | reg q; | |
525 | wire so; | |
526 | wire l1clk, siclk, soclk; | |
527 | ||
528 | `ifdef SCAN_MODE | |
529 | ||
530 | reg l1; | |
531 | `ifdef FAST_FLUSH | |
532 | always @(posedge l1clk or posedge siclk ) begin | |
533 | if (siclk) begin | |
534 | q <= 1'b0; //pseudo flush reset | |
535 | end else begin | |
536 | q <= d; | |
537 | end | |
538 | end | |
539 | `else | |
540 | always @(l1clk or siclk or soclk or d or si) | |
541 | begin | |
542 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
543 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
544 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
545 | ||
546 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
547 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
548 | end | |
549 | `endif | |
550 | `else | |
551 | wire si_unused; | |
552 | wire siclk_unused; | |
553 | wire soclk_unused; | |
554 | assign si_unused = si; | |
555 | assign siclk_unused = siclk; | |
556 | assign soclk_unused = soclk; | |
557 | ||
558 | ||
559 | `ifdef INITLATZERO | |
560 | initial q = 1'b0; | |
561 | `endif | |
562 | ||
563 | always @(posedge l1clk) | |
564 | begin | |
565 | if (!siclk && !soclk) q <= d; | |
566 | else q <= 1'bx; | |
567 | end | |
568 | `endif | |
569 | ||
570 | assign so = q; | |
571 | ||
572 | endmodule // dff | |
573 | ||
574 | ||
575 | ||
576 | ||
577 | module cl_dp1_msffmin_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
578 | // RFM 05-14-2004 | |
579 | // Level sensitive in SCAN_MODE | |
580 | // Edge triggered when not in SCAN_MODE | |
581 | ||
582 | ||
583 | parameter SIZE = 1; | |
584 | ||
585 | output q; | |
586 | output so; | |
587 | ||
588 | input d; | |
589 | input l1clk; | |
590 | input si; | |
591 | input siclk; | |
592 | input soclk; | |
593 | ||
594 | reg q; | |
595 | wire so; | |
596 | wire l1clk, siclk, soclk; | |
597 | ||
598 | `ifdef SCAN_MODE | |
599 | ||
600 | reg l1; | |
601 | `ifdef FAST_FLUSH | |
602 | always @(posedge l1clk or posedge siclk ) begin | |
603 | if (siclk) begin | |
604 | q <= 1'b0; //pseudo flush reset | |
605 | end else begin | |
606 | q <= d; | |
607 | end | |
608 | end | |
609 | `else | |
610 | always @(l1clk or siclk or soclk or d or si) | |
611 | begin | |
612 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
613 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
614 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
615 | ||
616 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
617 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
618 | end | |
619 | `endif | |
620 | `else | |
621 | wire si_unused; | |
622 | wire siclk_unused; | |
623 | wire soclk_unused; | |
624 | assign si_unused = si; | |
625 | assign siclk_unused = siclk; | |
626 | assign soclk_unused = soclk; | |
627 | ||
628 | ||
629 | `ifdef INITLATZERO | |
630 | initial q = 1'b0; | |
631 | `endif | |
632 | ||
633 | always @(posedge l1clk) | |
634 | begin | |
635 | if (!siclk && !soclk) q <= d; | |
636 | else q <= 1'bx; | |
637 | end | |
638 | `endif | |
639 | ||
640 | assign so = q; | |
641 | ||
642 | endmodule // dff | |
643 | module cl_dp1_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
644 | // RFM 05-14-2004 | |
645 | // Level sensitive in SCAN_MODE | |
646 | // Edge triggered when not in SCAN_MODE | |
647 | ||
648 | ||
649 | parameter SIZE = 1; | |
650 | ||
651 | output q; | |
652 | output so; | |
653 | ||
654 | input d; | |
655 | input l1clk; | |
656 | input si; | |
657 | input siclk; | |
658 | input soclk; | |
659 | ||
660 | reg q; | |
661 | wire so; | |
662 | wire l1clk, siclk, soclk; | |
663 | ||
664 | `ifdef SCAN_MODE | |
665 | ||
666 | reg l1; | |
667 | `ifdef FAST_FLUSH | |
668 | always @(posedge l1clk or posedge siclk ) begin | |
669 | if (siclk) begin | |
670 | q <= 1'b0; //pseudo flush reset | |
671 | end else begin | |
672 | q <= d; | |
673 | end | |
674 | end | |
675 | `else | |
676 | always @(l1clk or siclk or soclk or d or si) | |
677 | begin | |
678 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
679 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
680 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
681 | ||
682 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
683 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
684 | end | |
685 | `endif | |
686 | `else | |
687 | wire si_unused; | |
688 | wire siclk_unused; | |
689 | wire soclk_unused; | |
690 | assign si_unused = si; | |
691 | assign siclk_unused = siclk; | |
692 | assign soclk_unused = soclk; | |
693 | ||
694 | ||
695 | `ifdef INITLATZERO | |
696 | initial q = 1'b0; | |
697 | `endif | |
698 | ||
699 | always @(posedge l1clk) | |
700 | begin | |
701 | if (!siclk && !soclk) q <= d; | |
702 | else q <= 1'bx; | |
703 | end | |
704 | `endif | |
705 | ||
706 | assign so = q; | |
707 | ||
708 | endmodule // dff | |
709 | module cl_dp1_msffmin_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
710 | // RFM 05-14-2004 | |
711 | // Level sensitive in SCAN_MODE | |
712 | // Edge triggered when not in SCAN_MODE | |
713 | ||
714 | ||
715 | parameter SIZE = 1; | |
716 | ||
717 | output q; | |
718 | output so; | |
719 | ||
720 | input d; | |
721 | input l1clk; | |
722 | input si; | |
723 | input siclk; | |
724 | input soclk; | |
725 | ||
726 | reg q; | |
727 | wire so; | |
728 | wire l1clk, siclk, soclk; | |
729 | ||
730 | `ifdef SCAN_MODE | |
731 | ||
732 | reg l1; | |
733 | `ifdef FAST_FLUSH | |
734 | always @(posedge l1clk or posedge siclk ) begin | |
735 | if (siclk) begin | |
736 | q <= 1'b0; //pseudo flush reset | |
737 | end else begin | |
738 | q <= d; | |
739 | end | |
740 | end | |
741 | `else | |
742 | always @(l1clk or siclk or soclk or d or si) | |
743 | begin | |
744 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
745 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
746 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
747 | ||
748 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
749 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
750 | end | |
751 | `endif | |
752 | `else | |
753 | wire si_unused; | |
754 | wire siclk_unused; | |
755 | wire soclk_unused; | |
756 | assign si_unused = si; | |
757 | assign siclk_unused = siclk; | |
758 | assign soclk_unused = soclk; | |
759 | ||
760 | ||
761 | `ifdef INITLATZERO | |
762 | initial q = 1'b0; | |
763 | `endif | |
764 | ||
765 | always @(posedge l1clk) | |
766 | begin | |
767 | if (!siclk && !soclk) q <= d; | |
768 | else q <= 1'bx; | |
769 | end | |
770 | `endif | |
771 | ||
772 | assign so = q; | |
773 | ||
774 | endmodule // dff | |
775 | module cl_dp1_msffmin_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
776 | // RFM 05-14-2004 | |
777 | // Level sensitive in SCAN_MODE | |
778 | // Edge triggered when not in SCAN_MODE | |
779 | ||
780 | ||
781 | parameter SIZE = 1; | |
782 | ||
783 | output q; | |
784 | output so; | |
785 | ||
786 | input d; | |
787 | input l1clk; | |
788 | input si; | |
789 | input siclk; | |
790 | input soclk; | |
791 | ||
792 | reg q; | |
793 | wire so; | |
794 | wire l1clk, siclk, soclk; | |
795 | ||
796 | `ifdef SCAN_MODE | |
797 | ||
798 | reg l1; | |
799 | `ifdef FAST_FLUSH | |
800 | always @(posedge l1clk or posedge siclk ) begin | |
801 | if (siclk) begin | |
802 | q <= 1'b0; //pseudo flush reset | |
803 | end else begin | |
804 | q <= d; | |
805 | end | |
806 | end | |
807 | `else | |
808 | always @(l1clk or siclk or soclk or d or si) | |
809 | begin | |
810 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
811 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
812 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
813 | ||
814 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
815 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
816 | end | |
817 | `endif | |
818 | `else | |
819 | wire si_unused; | |
820 | wire siclk_unused; | |
821 | wire soclk_unused; | |
822 | assign si_unused = si; | |
823 | assign siclk_unused = siclk; | |
824 | assign soclk_unused = soclk; | |
825 | ||
826 | ||
827 | `ifdef INITLATZERO | |
828 | initial q = 1'b0; | |
829 | `endif | |
830 | ||
831 | always @(posedge l1clk) | |
832 | begin | |
833 | if (!siclk && !soclk) q <= d; | |
834 | else q <= 1'bx; | |
835 | end | |
836 | `endif | |
837 | ||
838 | assign so = q; | |
839 | ||
840 | endmodule // dff | |
841 | module cl_dp1_rep_32x ( | |
842 | in, | |
843 | out | |
844 | ); | |
845 | input in; | |
846 | output out; | |
847 | ||
848 | `ifdef LIB | |
849 | assign out = in; | |
850 | `endif | |
851 | ||
852 | endmodule | |
853 | ||
854 | module cl_dp1_rep_m6_32x ( | |
855 | in, | |
856 | out | |
857 | ); | |
858 | input in; | |
859 | output out; | |
860 | ||
861 | `ifdef LIB | |
862 | assign out = in; | |
863 | `endif | |
864 | ||
865 | endmodule | |
866 | ||
867 | module cl_dp1_add12_8x ( | |
868 | cin, | |
869 | in0, | |
870 | in1, | |
871 | out, | |
872 | cout | |
873 | ); | |
874 | input cin; | |
875 | input [11:0] in0; | |
876 | input [11:0] in1; | |
877 | output [11:0] out; | |
878 | output cout; | |
879 | ||
880 | `ifdef LIB | |
881 | assign {cout, out[11:0]} = ({1'b0, in0[11:0]} + {1'b0, in1[11:0]} + {{12{1'b0}}, cin}); | |
882 | `endif | |
883 | ||
884 | endmodule | |
885 | module cl_dp1_add136_8x ( | |
886 | din0, | |
887 | din1, | |
888 | din2, | |
889 | sel_din2, | |
890 | sum, | |
891 | fya_sticky_dp, | |
892 | fya_sticky_sp, | |
893 | fya_xicc_z); | |
894 | wire [101:0] p; | |
895 | wire [100:0] k; | |
896 | wire [101:0] z; | |
897 | ||
898 | ||
899 | input [135:0] din0; | |
900 | input [132:0] din1; | |
901 | input [135:0] din2; | |
902 | input [3:0] sel_din2; | |
903 | ||
904 | output [135:0] sum; | |
905 | output fya_sticky_dp; | |
906 | output fya_sticky_sp; | |
907 | output [1:0] fya_xicc_z; | |
908 | ||
909 | `ifdef LIB | |
910 | ||
911 | assign sum[135:0] = { din0[135:0]} + | |
912 | {3'b000,din1[132:0]} + | |
913 | ({{{40{sel_din2[3]}} & din2[135:96]}, | |
914 | {{32{sel_din2[2]}} & din2[95:64] }, | |
915 | {{32{sel_din2[1]}} & din2[63:32] }, | |
916 | {{32{sel_din2[0]}} & din2[31:0] }}); | |
917 | ||
918 | ||
919 | // 127 126 125 ... 74 73 72 0 | |
920 | // --- --- --------------- --- ------------ | |
921 | // Float DP x x . 52 fraction G -> Sticky -> | |
922 | ||
923 | // 127 126 125 ... 103 102 101 0 | |
924 | // --- --- --------------- --- ------------ | |
925 | // Float SP x x . 23 fraction G -> Sticky -> | |
926 | ||
927 | ||
928 | assign p[101:0] = din0[101:0] ^ {din1[101:4],{4{1'b0}}}; | |
929 | assign k[100:0] = ~din0[100:0] & ~{din1[100:4],{4{1'b0}}}; | |
930 | ||
931 | assign z[101:1] = p[101:1] ^ k[100:0]; | |
932 | assign z[0] = ~p[0]; | |
933 | ||
934 | assign fya_sticky_sp = ~(& z[101:0]); | |
935 | assign fya_sticky_dp = ~(& z[72:0]); | |
936 | ||
937 | assign fya_xicc_z[1] = & z[63:0]; | |
938 | assign fya_xicc_z[0] = & z[31:0]; | |
939 | ||
940 | `endif | |
941 | ||
942 | endmodule | |
943 | module cl_dp1_add16_8x ( | |
944 | cin, | |
945 | in0, | |
946 | in1, | |
947 | out, | |
948 | cout | |
949 | ); | |
950 | input cin; | |
951 | input [15:0] in0; | |
952 | input [15:0] in1; | |
953 | output [15:0] out; | |
954 | output cout; | |
955 | ||
956 | `ifdef LIB | |
957 | assign {cout, out[15:0]} = ({1'b0, in0[15:0]} + {1'b0, in1[15:0]} + {{16{1'b0}}, cin}); | |
958 | `endif | |
959 | ||
960 | endmodule | |
961 | module cl_dp1_add32_8x ( | |
962 | cin, | |
963 | in0, | |
964 | in1, | |
965 | out, | |
966 | cout | |
967 | ); | |
968 | input cin; | |
969 | input [31:0] in0; | |
970 | input [31:0] in1; | |
971 | output [31:0] out; | |
972 | output cout; | |
973 | ||
974 | `ifdef LIB | |
975 | assign {cout, out[31:0]} = ({1'b0, in0[31:0]} + {1'b0, in1[31:0]} + {{32{1'b0}}, cin}); | |
976 | `endif | |
977 | ||
978 | endmodule | |
979 | module cl_dp1_add4_8x ( | |
980 | cin, | |
981 | in0, | |
982 | in1, | |
983 | out, | |
984 | cout | |
985 | ); | |
986 | input cin; | |
987 | input [3:0] in0; | |
988 | input [3:0] in1; | |
989 | output [3:0] out; | |
990 | output cout; | |
991 | ||
992 | `ifdef LIB | |
993 | assign {cout, out[3:0]} = ({1'b0, in0[3:0]} + {1'b0, in1[3:0]} + {{4{1'b0}}, cin}); | |
994 | `endif | |
995 | ||
996 | endmodule | |
997 | module cl_dp1_add64_8x ( | |
998 | cin, | |
999 | in0, | |
1000 | in1, | |
1001 | out, | |
1002 | cout | |
1003 | ); | |
1004 | input cin; | |
1005 | input [63:0] in0; | |
1006 | input [63:0] in1; | |
1007 | output [63:0] out; | |
1008 | output cout; | |
1009 | ||
1010 | `ifdef LIB | |
1011 | assign {cout, out[63:0]} = ({1'b0, in0[63:0]} + {1'b0, in1[63:0]} + {{64{1'b0}}, cin}); | |
1012 | `endif | |
1013 | ||
1014 | endmodule | |
1015 | module cl_dp1_add8_8x ( | |
1016 | cin, | |
1017 | in0, | |
1018 | in1, | |
1019 | out, | |
1020 | cout | |
1021 | ); | |
1022 | input cin; | |
1023 | input [7:0] in0; | |
1024 | input [7:0] in1; | |
1025 | output [7:0] out; | |
1026 | output cout; | |
1027 | ||
1028 | `ifdef LIB | |
1029 | assign {cout, out[7:0]} = ({1'b0, in0[7:0]} + {1'b0, in1[7:0]} + {{8{1'b0}}, cin}); | |
1030 | `endif | |
1031 | ||
1032 | endmodule | |
1033 | ||
1034 | module cl_dp1_aomux2_1x ( | |
1035 | in0, | |
1036 | in1, | |
1037 | sel0, | |
1038 | sel1, | |
1039 | out | |
1040 | ); | |
1041 | input in0; | |
1042 | input in1; | |
1043 | input sel0; | |
1044 | input sel1; | |
1045 | output out; | |
1046 | ||
1047 | `ifdef LIB | |
1048 | assign out = ((sel0 & in0) | | |
1049 | (sel1 & in1)); | |
1050 | `endif | |
1051 | ||
1052 | ||
1053 | endmodule | |
1054 | module cl_dp1_aomux2_2x ( | |
1055 | in0, | |
1056 | in1, | |
1057 | sel0, | |
1058 | sel1, | |
1059 | out | |
1060 | ); | |
1061 | input in0; | |
1062 | input in1; | |
1063 | input sel0; | |
1064 | input sel1; | |
1065 | output out; | |
1066 | ||
1067 | `ifdef LIB | |
1068 | assign out = ((sel0 & in0) | | |
1069 | (sel1 & in1)); | |
1070 | `endif | |
1071 | ||
1072 | ||
1073 | endmodule | |
1074 | module cl_dp1_aomux2_4x ( | |
1075 | in0, | |
1076 | in1, | |
1077 | sel0, | |
1078 | sel1, | |
1079 | out | |
1080 | ); | |
1081 | input in0; | |
1082 | input in1; | |
1083 | input sel0; | |
1084 | input sel1; | |
1085 | output out; | |
1086 | ||
1087 | `ifdef LIB | |
1088 | assign out = ((sel0 & in0) | | |
1089 | (sel1 & in1)); | |
1090 | `endif | |
1091 | ||
1092 | ||
1093 | endmodule | |
1094 | module cl_dp1_aomux2_6x ( | |
1095 | in0, | |
1096 | in1, | |
1097 | sel0, | |
1098 | sel1, | |
1099 | out | |
1100 | ); | |
1101 | input in0; | |
1102 | input in1; | |
1103 | input sel0; | |
1104 | input sel1; | |
1105 | output out; | |
1106 | ||
1107 | `ifdef LIB | |
1108 | assign out = ((sel0 & in0) | | |
1109 | (sel1 & in1)); | |
1110 | `endif | |
1111 | ||
1112 | ||
1113 | endmodule | |
1114 | module cl_dp1_aomux2_8x ( | |
1115 | in0, | |
1116 | in1, | |
1117 | sel0, | |
1118 | sel1, | |
1119 | out | |
1120 | ); | |
1121 | input in0; | |
1122 | input in1; | |
1123 | input sel0; | |
1124 | input sel1; | |
1125 | output out; | |
1126 | ||
1127 | `ifdef LIB | |
1128 | assign out = ((sel0 & in0) | | |
1129 | (sel1 & in1)); | |
1130 | `endif | |
1131 | ||
1132 | ||
1133 | endmodule | |
1134 | ||
1135 | module cl_dp1_aomux3_1x ( | |
1136 | in0, | |
1137 | in1, | |
1138 | in2, | |
1139 | sel0, | |
1140 | sel1, | |
1141 | sel2, | |
1142 | out | |
1143 | ); | |
1144 | input in0; | |
1145 | input in1; | |
1146 | input in2; | |
1147 | input sel0; | |
1148 | input sel1; | |
1149 | input sel2; | |
1150 | output out; | |
1151 | ||
1152 | `ifdef LIB | |
1153 | assign out = ((sel0 & in0) | | |
1154 | (sel1 & in1) | | |
1155 | (sel2 & in2)); | |
1156 | `endif | |
1157 | ||
1158 | endmodule | |
1159 | module cl_dp1_aomux3_2x ( | |
1160 | in0, | |
1161 | in1, | |
1162 | in2, | |
1163 | sel0, | |
1164 | sel1, | |
1165 | sel2, | |
1166 | out | |
1167 | ); | |
1168 | input in0; | |
1169 | input in1; | |
1170 | input in2; | |
1171 | input sel0; | |
1172 | input sel1; | |
1173 | input sel2; | |
1174 | output out; | |
1175 | ||
1176 | `ifdef LIB | |
1177 | assign out = ((sel0 & in0) | | |
1178 | (sel1 & in1) | | |
1179 | (sel2 & in2)); | |
1180 | `endif | |
1181 | ||
1182 | endmodule | |
1183 | module cl_dp1_aomux3_4x ( | |
1184 | in0, | |
1185 | in1, | |
1186 | in2, | |
1187 | sel0, | |
1188 | sel1, | |
1189 | sel2, | |
1190 | out | |
1191 | ); | |
1192 | input in0; | |
1193 | input in1; | |
1194 | input in2; | |
1195 | input sel0; | |
1196 | input sel1; | |
1197 | input sel2; | |
1198 | output out; | |
1199 | ||
1200 | `ifdef LIB | |
1201 | assign out = ((sel0 & in0) | | |
1202 | (sel1 & in1) | | |
1203 | (sel2 & in2)); | |
1204 | `endif | |
1205 | ||
1206 | endmodule | |
1207 | module cl_dp1_aomux3_6x ( | |
1208 | in0, | |
1209 | in1, | |
1210 | in2, | |
1211 | sel0, | |
1212 | sel1, | |
1213 | sel2, | |
1214 | out | |
1215 | ); | |
1216 | input in0; | |
1217 | input in1; | |
1218 | input in2; | |
1219 | input sel0; | |
1220 | input sel1; | |
1221 | input sel2; | |
1222 | output out; | |
1223 | ||
1224 | `ifdef LIB | |
1225 | assign out = ((sel0 & in0) | | |
1226 | (sel1 & in1) | | |
1227 | (sel2 & in2)); | |
1228 | `endif | |
1229 | ||
1230 | endmodule | |
1231 | module cl_dp1_aomux3_8x ( | |
1232 | in0, | |
1233 | in1, | |
1234 | in2, | |
1235 | sel0, | |
1236 | sel1, | |
1237 | sel2, | |
1238 | out | |
1239 | ); | |
1240 | input in0; | |
1241 | input in1; | |
1242 | input in2; | |
1243 | input sel0; | |
1244 | input sel1; | |
1245 | input sel2; | |
1246 | output out; | |
1247 | ||
1248 | `ifdef LIB | |
1249 | assign out = ((sel0 & in0) | | |
1250 | (sel1 & in1) | | |
1251 | (sel2 & in2)); | |
1252 | `endif | |
1253 | ||
1254 | endmodule | |
1255 | ||
1256 | module cl_dp1_aomux4_1x ( | |
1257 | in0, | |
1258 | in1, | |
1259 | in2, | |
1260 | in3, | |
1261 | sel0, | |
1262 | sel1, | |
1263 | sel2, | |
1264 | sel3, | |
1265 | out | |
1266 | ); | |
1267 | input in0; | |
1268 | input in1; | |
1269 | input in2; | |
1270 | input in3; | |
1271 | input sel0; | |
1272 | input sel1; | |
1273 | input sel2; | |
1274 | input sel3; | |
1275 | output out; | |
1276 | ||
1277 | `ifdef LIB | |
1278 | assign out = ((sel0 & in0) | | |
1279 | (sel1 & in1) | | |
1280 | (sel2 & in2) | | |
1281 | (sel3 & in3)); | |
1282 | `endif | |
1283 | ||
1284 | endmodule | |
1285 | module cl_dp1_aomux4_2x ( | |
1286 | in0, | |
1287 | in1, | |
1288 | in2, | |
1289 | in3, | |
1290 | sel0, | |
1291 | sel1, | |
1292 | sel2, | |
1293 | sel3, | |
1294 | out | |
1295 | ); | |
1296 | input in0; | |
1297 | input in1; | |
1298 | input in2; | |
1299 | input in3; | |
1300 | input sel0; | |
1301 | input sel1; | |
1302 | input sel2; | |
1303 | input sel3; | |
1304 | output out; | |
1305 | ||
1306 | `ifdef LIB | |
1307 | assign out = ((sel0 & in0) | | |
1308 | (sel1 & in1) | | |
1309 | (sel2 & in2) | | |
1310 | (sel3 & in3)); | |
1311 | `endif | |
1312 | ||
1313 | endmodule | |
1314 | module cl_dp1_aomux4_4x ( | |
1315 | in0, | |
1316 | in1, | |
1317 | in2, | |
1318 | in3, | |
1319 | sel0, | |
1320 | sel1, | |
1321 | sel2, | |
1322 | sel3, | |
1323 | out | |
1324 | ); | |
1325 | input in0; | |
1326 | input in1; | |
1327 | input in2; | |
1328 | input in3; | |
1329 | input sel0; | |
1330 | input sel1; | |
1331 | input sel2; | |
1332 | input sel3; | |
1333 | output out; | |
1334 | ||
1335 | `ifdef LIB | |
1336 | assign out = ((sel0 & in0) | | |
1337 | (sel1 & in1) | | |
1338 | (sel2 & in2) | | |
1339 | (sel3 & in3)); | |
1340 | `endif | |
1341 | ||
1342 | endmodule | |
1343 | module cl_dp1_aomux4_6x ( | |
1344 | in0, | |
1345 | in1, | |
1346 | in2, | |
1347 | in3, | |
1348 | sel0, | |
1349 | sel1, | |
1350 | sel2, | |
1351 | sel3, | |
1352 | out | |
1353 | ); | |
1354 | input in0; | |
1355 | input in1; | |
1356 | input in2; | |
1357 | input in3; | |
1358 | input sel0; | |
1359 | input sel1; | |
1360 | input sel2; | |
1361 | input sel3; | |
1362 | output out; | |
1363 | ||
1364 | `ifdef LIB | |
1365 | assign out = ((sel0 & in0) | | |
1366 | (sel1 & in1) | | |
1367 | (sel2 & in2) | | |
1368 | (sel3 & in3)); | |
1369 | `endif | |
1370 | ||
1371 | endmodule | |
1372 | module cl_dp1_aomux4_8x ( | |
1373 | in0, | |
1374 | in1, | |
1375 | in2, | |
1376 | in3, | |
1377 | sel0, | |
1378 | sel1, | |
1379 | sel2, | |
1380 | sel3, | |
1381 | out | |
1382 | ); | |
1383 | input in0; | |
1384 | input in1; | |
1385 | input in2; | |
1386 | input in3; | |
1387 | input sel0; | |
1388 | input sel1; | |
1389 | input sel2; | |
1390 | input sel3; | |
1391 | output out; | |
1392 | ||
1393 | `ifdef LIB | |
1394 | assign out = ((sel0 & in0) | | |
1395 | (sel1 & in1) | | |
1396 | (sel2 & in2) | | |
1397 | (sel3 & in3)); | |
1398 | `endif | |
1399 | ||
1400 | endmodule | |
1401 | ||
1402 | module cl_dp1_aomux5_1x ( | |
1403 | in0, | |
1404 | in1, | |
1405 | in2, | |
1406 | in3, | |
1407 | in4, | |
1408 | sel0, | |
1409 | sel1, | |
1410 | sel2, | |
1411 | sel3, | |
1412 | sel4, | |
1413 | out | |
1414 | ); | |
1415 | input in0; | |
1416 | input in1; | |
1417 | input in2; | |
1418 | input in3; | |
1419 | input in4; | |
1420 | input sel0; | |
1421 | input sel1; | |
1422 | input sel2; | |
1423 | input sel3; | |
1424 | input sel4; | |
1425 | output out; | |
1426 | ||
1427 | `ifdef LIB | |
1428 | assign out = ((sel0 & in0) | | |
1429 | (sel1 & in1) | | |
1430 | (sel2 & in2) | | |
1431 | (sel3 & in3) | | |
1432 | (sel4 & in4)); | |
1433 | `endif | |
1434 | ||
1435 | endmodule | |
1436 | module cl_dp1_aomux5_2x ( | |
1437 | in0, | |
1438 | in1, | |
1439 | in2, | |
1440 | in3, | |
1441 | in4, | |
1442 | sel0, | |
1443 | sel1, | |
1444 | sel2, | |
1445 | sel3, | |
1446 | sel4, | |
1447 | out | |
1448 | ); | |
1449 | input in0; | |
1450 | input in1; | |
1451 | input in2; | |
1452 | input in3; | |
1453 | input in4; | |
1454 | input sel0; | |
1455 | input sel1; | |
1456 | input sel2; | |
1457 | input sel3; | |
1458 | input sel4; | |
1459 | output out; | |
1460 | ||
1461 | `ifdef LIB | |
1462 | assign out = ((sel0 & in0) | | |
1463 | (sel1 & in1) | | |
1464 | (sel2 & in2) | | |
1465 | (sel3 & in3) | | |
1466 | (sel4 & in4)); | |
1467 | `endif | |
1468 | ||
1469 | endmodule | |
1470 | module cl_dp1_aomux5_4x ( | |
1471 | in0, | |
1472 | in1, | |
1473 | in2, | |
1474 | in3, | |
1475 | in4, | |
1476 | sel0, | |
1477 | sel1, | |
1478 | sel2, | |
1479 | sel3, | |
1480 | sel4, | |
1481 | out | |
1482 | ); | |
1483 | input in0; | |
1484 | input in1; | |
1485 | input in2; | |
1486 | input in3; | |
1487 | input in4; | |
1488 | input sel0; | |
1489 | input sel1; | |
1490 | input sel2; | |
1491 | input sel3; | |
1492 | input sel4; | |
1493 | output out; | |
1494 | ||
1495 | `ifdef LIB | |
1496 | assign out = ((sel0 & in0) | | |
1497 | (sel1 & in1) | | |
1498 | (sel2 & in2) | | |
1499 | (sel3 & in3) | | |
1500 | (sel4 & in4)); | |
1501 | `endif | |
1502 | ||
1503 | endmodule | |
1504 | module cl_dp1_aomux5_6x ( | |
1505 | in0, | |
1506 | in1, | |
1507 | in2, | |
1508 | in3, | |
1509 | in4, | |
1510 | sel0, | |
1511 | sel1, | |
1512 | sel2, | |
1513 | sel3, | |
1514 | sel4, | |
1515 | out | |
1516 | ); | |
1517 | input in0; | |
1518 | input in1; | |
1519 | input in2; | |
1520 | input in3; | |
1521 | input in4; | |
1522 | input sel0; | |
1523 | input sel1; | |
1524 | input sel2; | |
1525 | input sel3; | |
1526 | input sel4; | |
1527 | output out; | |
1528 | ||
1529 | `ifdef LIB | |
1530 | assign out = ((sel0 & in0) | | |
1531 | (sel1 & in1) | | |
1532 | (sel2 & in2) | | |
1533 | (sel3 & in3) | | |
1534 | (sel4 & in4)); | |
1535 | `endif | |
1536 | ||
1537 | endmodule | |
1538 | module cl_dp1_aomux5_8x ( | |
1539 | in0, | |
1540 | in1, | |
1541 | in2, | |
1542 | in3, | |
1543 | in4, | |
1544 | sel0, | |
1545 | sel1, | |
1546 | sel2, | |
1547 | sel3, | |
1548 | sel4, | |
1549 | out | |
1550 | ); | |
1551 | input in0; | |
1552 | input in1; | |
1553 | input in2; | |
1554 | input in3; | |
1555 | input in4; | |
1556 | input sel0; | |
1557 | input sel1; | |
1558 | input sel2; | |
1559 | input sel3; | |
1560 | input sel4; | |
1561 | output out; | |
1562 | ||
1563 | `ifdef LIB | |
1564 | assign out = ((sel0 & in0) | | |
1565 | (sel1 & in1) | | |
1566 | (sel2 & in2) | | |
1567 | (sel3 & in3) | | |
1568 | (sel4 & in4)); | |
1569 | `endif | |
1570 | ||
1571 | endmodule | |
1572 | ||
1573 | module cl_dp1_aomux6_1x ( | |
1574 | in0, | |
1575 | in1, | |
1576 | in2, | |
1577 | in3, | |
1578 | in4, | |
1579 | in5, | |
1580 | sel0, | |
1581 | sel1, | |
1582 | sel2, | |
1583 | sel3, | |
1584 | sel4, | |
1585 | sel5, | |
1586 | out | |
1587 | ); | |
1588 | input in0; | |
1589 | input in1; | |
1590 | input in2; | |
1591 | input in3; | |
1592 | input in4; | |
1593 | input in5; | |
1594 | input sel0; | |
1595 | input sel1; | |
1596 | input sel2; | |
1597 | input sel3; | |
1598 | input sel4; | |
1599 | input sel5; | |
1600 | output out; | |
1601 | ||
1602 | `ifdef LIB | |
1603 | assign out = ((sel0 & in0) | | |
1604 | (sel1 & in1) | | |
1605 | (sel2 & in2) | | |
1606 | (sel3 & in3) | | |
1607 | (sel4 & in4) | | |
1608 | (sel5 & in5)); | |
1609 | `endif | |
1610 | ||
1611 | endmodule | |
1612 | module cl_dp1_aomux6_2x ( | |
1613 | in0, | |
1614 | in1, | |
1615 | in2, | |
1616 | in3, | |
1617 | in4, | |
1618 | in5, | |
1619 | sel0, | |
1620 | sel1, | |
1621 | sel2, | |
1622 | sel3, | |
1623 | sel4, | |
1624 | sel5, | |
1625 | out | |
1626 | ); | |
1627 | input in0; | |
1628 | input in1; | |
1629 | input in2; | |
1630 | input in3; | |
1631 | input in4; | |
1632 | input in5; | |
1633 | input sel0; | |
1634 | input sel1; | |
1635 | input sel2; | |
1636 | input sel3; | |
1637 | input sel4; | |
1638 | input sel5; | |
1639 | output out; | |
1640 | ||
1641 | `ifdef LIB | |
1642 | assign out = ((sel0 & in0) | | |
1643 | (sel1 & in1) | | |
1644 | (sel2 & in2) | | |
1645 | (sel3 & in3) | | |
1646 | (sel4 & in4) | | |
1647 | (sel5 & in5)); | |
1648 | `endif | |
1649 | ||
1650 | endmodule | |
1651 | module cl_dp1_aomux6_4x ( | |
1652 | in0, | |
1653 | in1, | |
1654 | in2, | |
1655 | in3, | |
1656 | in4, | |
1657 | in5, | |
1658 | sel0, | |
1659 | sel1, | |
1660 | sel2, | |
1661 | sel3, | |
1662 | sel4, | |
1663 | sel5, | |
1664 | out | |
1665 | ); | |
1666 | input in0; | |
1667 | input in1; | |
1668 | input in2; | |
1669 | input in3; | |
1670 | input in4; | |
1671 | input in5; | |
1672 | input sel0; | |
1673 | input sel1; | |
1674 | input sel2; | |
1675 | input sel3; | |
1676 | input sel4; | |
1677 | input sel5; | |
1678 | output out; | |
1679 | ||
1680 | `ifdef LIB | |
1681 | assign out = ((sel0 & in0) | | |
1682 | (sel1 & in1) | | |
1683 | (sel2 & in2) | | |
1684 | (sel3 & in3) | | |
1685 | (sel4 & in4) | | |
1686 | (sel5 & in5)); | |
1687 | `endif | |
1688 | ||
1689 | endmodule | |
1690 | module cl_dp1_aomux6_6x ( | |
1691 | in0, | |
1692 | in1, | |
1693 | in2, | |
1694 | in3, | |
1695 | in4, | |
1696 | in5, | |
1697 | sel0, | |
1698 | sel1, | |
1699 | sel2, | |
1700 | sel3, | |
1701 | sel4, | |
1702 | sel5, | |
1703 | out | |
1704 | ); | |
1705 | input in0; | |
1706 | input in1; | |
1707 | input in2; | |
1708 | input in3; | |
1709 | input in4; | |
1710 | input in5; | |
1711 | input sel0; | |
1712 | input sel1; | |
1713 | input sel2; | |
1714 | input sel3; | |
1715 | input sel4; | |
1716 | input sel5; | |
1717 | output out; | |
1718 | ||
1719 | `ifdef LIB | |
1720 | assign out = ((sel0 & in0) | | |
1721 | (sel1 & in1) | | |
1722 | (sel2 & in2) | | |
1723 | (sel3 & in3) | | |
1724 | (sel4 & in4) | | |
1725 | (sel5 & in5)); | |
1726 | `endif | |
1727 | ||
1728 | endmodule | |
1729 | module cl_dp1_aomux6_8x ( | |
1730 | in0, | |
1731 | in1, | |
1732 | in2, | |
1733 | in3, | |
1734 | in4, | |
1735 | in5, | |
1736 | sel0, | |
1737 | sel1, | |
1738 | sel2, | |
1739 | sel3, | |
1740 | sel4, | |
1741 | sel5, | |
1742 | out | |
1743 | ); | |
1744 | input in0; | |
1745 | input in1; | |
1746 | input in2; | |
1747 | input in3; | |
1748 | input in4; | |
1749 | input in5; | |
1750 | input sel0; | |
1751 | input sel1; | |
1752 | input sel2; | |
1753 | input sel3; | |
1754 | input sel4; | |
1755 | input sel5; | |
1756 | output out; | |
1757 | ||
1758 | `ifdef LIB | |
1759 | assign out = ((sel0 & in0) | | |
1760 | (sel1 & in1) | | |
1761 | (sel2 & in2) | | |
1762 | (sel3 & in3) | | |
1763 | (sel4 & in4) | | |
1764 | (sel5 & in5)); | |
1765 | `endif | |
1766 | ||
1767 | endmodule | |
1768 | ||
1769 | module cl_dp1_aomux7_1x ( | |
1770 | in0, | |
1771 | in1, | |
1772 | in2, | |
1773 | in3, | |
1774 | in4, | |
1775 | in5, | |
1776 | in6, | |
1777 | sel0, | |
1778 | sel1, | |
1779 | sel2, | |
1780 | sel3, | |
1781 | sel4, | |
1782 | sel5, | |
1783 | sel6, | |
1784 | out | |
1785 | ); | |
1786 | input in0; | |
1787 | input in1; | |
1788 | input in2; | |
1789 | input in3; | |
1790 | input in4; | |
1791 | input in5; | |
1792 | input in6; | |
1793 | input sel0; | |
1794 | input sel1; | |
1795 | input sel2; | |
1796 | input sel3; | |
1797 | input sel4; | |
1798 | input sel5; | |
1799 | input sel6; | |
1800 | output out; | |
1801 | ||
1802 | `ifdef LIB | |
1803 | assign out = ((sel0 & in0) | | |
1804 | (sel1 & in1) | | |
1805 | (sel2 & in2) | | |
1806 | (sel3 & in3) | | |
1807 | (sel4 & in4) | | |
1808 | (sel5 & in5) | | |
1809 | (sel6 & in6)); | |
1810 | `endif | |
1811 | ||
1812 | endmodule | |
1813 | module cl_dp1_aomux7_2x ( | |
1814 | in0, | |
1815 | in1, | |
1816 | in2, | |
1817 | in3, | |
1818 | in4, | |
1819 | in5, | |
1820 | in6, | |
1821 | sel0, | |
1822 | sel1, | |
1823 | sel2, | |
1824 | sel3, | |
1825 | sel4, | |
1826 | sel5, | |
1827 | sel6, | |
1828 | out | |
1829 | ); | |
1830 | input in0; | |
1831 | input in1; | |
1832 | input in2; | |
1833 | input in3; | |
1834 | input in4; | |
1835 | input in5; | |
1836 | input in6; | |
1837 | input sel0; | |
1838 | input sel1; | |
1839 | input sel2; | |
1840 | input sel3; | |
1841 | input sel4; | |
1842 | input sel5; | |
1843 | input sel6; | |
1844 | output out; | |
1845 | ||
1846 | `ifdef LIB | |
1847 | assign out = ((sel0 & in0) | | |
1848 | (sel1 & in1) | | |
1849 | (sel2 & in2) | | |
1850 | (sel3 & in3) | | |
1851 | (sel4 & in4) | | |
1852 | (sel5 & in5) | | |
1853 | (sel6 & in6)); | |
1854 | `endif | |
1855 | ||
1856 | endmodule | |
1857 | module cl_dp1_aomux7_4x ( | |
1858 | in0, | |
1859 | in1, | |
1860 | in2, | |
1861 | in3, | |
1862 | in4, | |
1863 | in5, | |
1864 | in6, | |
1865 | sel0, | |
1866 | sel1, | |
1867 | sel2, | |
1868 | sel3, | |
1869 | sel4, | |
1870 | sel5, | |
1871 | sel6, | |
1872 | out | |
1873 | ); | |
1874 | input in0; | |
1875 | input in1; | |
1876 | input in2; | |
1877 | input in3; | |
1878 | input in4; | |
1879 | input in5; | |
1880 | input in6; | |
1881 | input sel0; | |
1882 | input sel1; | |
1883 | input sel2; | |
1884 | input sel3; | |
1885 | input sel4; | |
1886 | input sel5; | |
1887 | input sel6; | |
1888 | output out; | |
1889 | ||
1890 | `ifdef LIB | |
1891 | assign out = ((sel0 & in0) | | |
1892 | (sel1 & in1) | | |
1893 | (sel2 & in2) | | |
1894 | (sel3 & in3) | | |
1895 | (sel4 & in4) | | |
1896 | (sel5 & in5) | | |
1897 | (sel6 & in6)); | |
1898 | `endif | |
1899 | ||
1900 | endmodule | |
1901 | module cl_dp1_aomux7_6x ( | |
1902 | in0, | |
1903 | in1, | |
1904 | in2, | |
1905 | in3, | |
1906 | in4, | |
1907 | in5, | |
1908 | in6, | |
1909 | sel0, | |
1910 | sel1, | |
1911 | sel2, | |
1912 | sel3, | |
1913 | sel4, | |
1914 | sel5, | |
1915 | sel6, | |
1916 | out | |
1917 | ); | |
1918 | input in0; | |
1919 | input in1; | |
1920 | input in2; | |
1921 | input in3; | |
1922 | input in4; | |
1923 | input in5; | |
1924 | input in6; | |
1925 | input sel0; | |
1926 | input sel1; | |
1927 | input sel2; | |
1928 | input sel3; | |
1929 | input sel4; | |
1930 | input sel5; | |
1931 | input sel6; | |
1932 | output out; | |
1933 | ||
1934 | `ifdef LIB | |
1935 | assign out = ((sel0 & in0) | | |
1936 | (sel1 & in1) | | |
1937 | (sel2 & in2) | | |
1938 | (sel3 & in3) | | |
1939 | (sel4 & in4) | | |
1940 | (sel5 & in5) | | |
1941 | (sel6 & in6)); | |
1942 | `endif | |
1943 | ||
1944 | endmodule | |
1945 | module cl_dp1_aomux7_8x ( | |
1946 | in0, | |
1947 | in1, | |
1948 | in2, | |
1949 | in3, | |
1950 | in4, | |
1951 | in5, | |
1952 | in6, | |
1953 | sel0, | |
1954 | sel1, | |
1955 | sel2, | |
1956 | sel3, | |
1957 | sel4, | |
1958 | sel5, | |
1959 | sel6, | |
1960 | out | |
1961 | ); | |
1962 | input in0; | |
1963 | input in1; | |
1964 | input in2; | |
1965 | input in3; | |
1966 | input in4; | |
1967 | input in5; | |
1968 | input in6; | |
1969 | input sel0; | |
1970 | input sel1; | |
1971 | input sel2; | |
1972 | input sel3; | |
1973 | input sel4; | |
1974 | input sel5; | |
1975 | input sel6; | |
1976 | output out; | |
1977 | ||
1978 | `ifdef LIB | |
1979 | assign out = ((sel0 & in0) | | |
1980 | (sel1 & in1) | | |
1981 | (sel2 & in2) | | |
1982 | (sel3 & in3) | | |
1983 | (sel4 & in4) | | |
1984 | (sel5 & in5) | | |
1985 | (sel6 & in6)); | |
1986 | `endif | |
1987 | ||
1988 | endmodule | |
1989 | ||
1990 | module cl_dp1_aomux8_1x ( | |
1991 | in0, | |
1992 | in1, | |
1993 | in2, | |
1994 | in3, | |
1995 | in4, | |
1996 | in5, | |
1997 | in6, | |
1998 | in7, | |
1999 | sel0, | |
2000 | sel1, | |
2001 | sel2, | |
2002 | sel3, | |
2003 | sel4, | |
2004 | sel5, | |
2005 | sel6, | |
2006 | sel7, | |
2007 | out | |
2008 | ); | |
2009 | input in0; | |
2010 | input in1; | |
2011 | input in2; | |
2012 | input in3; | |
2013 | input in4; | |
2014 | input in5; | |
2015 | input in6; | |
2016 | input in7; | |
2017 | input sel0; | |
2018 | input sel1; | |
2019 | input sel2; | |
2020 | input sel3; | |
2021 | input sel4; | |
2022 | input sel5; | |
2023 | input sel6; | |
2024 | input sel7; | |
2025 | output out; | |
2026 | ||
2027 | `ifdef LIB | |
2028 | assign out = ((sel0 & in0) | | |
2029 | (sel1 & in1) | | |
2030 | (sel2 & in2) | | |
2031 | (sel3 & in3) | | |
2032 | (sel4 & in4) | | |
2033 | (sel5 & in5) | | |
2034 | (sel6 & in6) | | |
2035 | (sel7 & in7)); | |
2036 | `endif | |
2037 | ||
2038 | ||
2039 | endmodule | |
2040 | module cl_dp1_aomux8_2x ( | |
2041 | in0, | |
2042 | in1, | |
2043 | in2, | |
2044 | in3, | |
2045 | in4, | |
2046 | in5, | |
2047 | in6, | |
2048 | in7, | |
2049 | sel0, | |
2050 | sel1, | |
2051 | sel2, | |
2052 | sel3, | |
2053 | sel4, | |
2054 | sel5, | |
2055 | sel6, | |
2056 | sel7, | |
2057 | out | |
2058 | ); | |
2059 | input in0; | |
2060 | input in1; | |
2061 | input in2; | |
2062 | input in3; | |
2063 | input in4; | |
2064 | input in5; | |
2065 | input in6; | |
2066 | input in7; | |
2067 | input sel0; | |
2068 | input sel1; | |
2069 | input sel2; | |
2070 | input sel3; | |
2071 | input sel4; | |
2072 | input sel5; | |
2073 | input sel6; | |
2074 | input sel7; | |
2075 | output out; | |
2076 | ||
2077 | `ifdef LIB | |
2078 | assign out = ((sel0 & in0) | | |
2079 | (sel1 & in1) | | |
2080 | (sel2 & in2) | | |
2081 | (sel3 & in3) | | |
2082 | (sel4 & in4) | | |
2083 | (sel5 & in5) | | |
2084 | (sel6 & in6) | | |
2085 | (sel7 & in7)); | |
2086 | `endif | |
2087 | ||
2088 | ||
2089 | endmodule | |
2090 | module cl_dp1_aomux8_4x ( | |
2091 | in0, | |
2092 | in1, | |
2093 | in2, | |
2094 | in3, | |
2095 | in4, | |
2096 | in5, | |
2097 | in6, | |
2098 | in7, | |
2099 | sel0, | |
2100 | sel1, | |
2101 | sel2, | |
2102 | sel3, | |
2103 | sel4, | |
2104 | sel5, | |
2105 | sel6, | |
2106 | sel7, | |
2107 | out | |
2108 | ); | |
2109 | input in0; | |
2110 | input in1; | |
2111 | input in2; | |
2112 | input in3; | |
2113 | input in4; | |
2114 | input in5; | |
2115 | input in6; | |
2116 | input in7; | |
2117 | input sel0; | |
2118 | input sel1; | |
2119 | input sel2; | |
2120 | input sel3; | |
2121 | input sel4; | |
2122 | input sel5; | |
2123 | input sel6; | |
2124 | input sel7; | |
2125 | output out; | |
2126 | ||
2127 | `ifdef LIB | |
2128 | assign out = ((sel0 & in0) | | |
2129 | (sel1 & in1) | | |
2130 | (sel2 & in2) | | |
2131 | (sel3 & in3) | | |
2132 | (sel4 & in4) | | |
2133 | (sel5 & in5) | | |
2134 | (sel6 & in6) | | |
2135 | (sel7 & in7)); | |
2136 | `endif | |
2137 | ||
2138 | ||
2139 | endmodule | |
2140 | module cl_dp1_aomux8_6x ( | |
2141 | in0, | |
2142 | in1, | |
2143 | in2, | |
2144 | in3, | |
2145 | in4, | |
2146 | in5, | |
2147 | in6, | |
2148 | in7, | |
2149 | sel0, | |
2150 | sel1, | |
2151 | sel2, | |
2152 | sel3, | |
2153 | sel4, | |
2154 | sel5, | |
2155 | sel6, | |
2156 | sel7, | |
2157 | out | |
2158 | ); | |
2159 | input in0; | |
2160 | input in1; | |
2161 | input in2; | |
2162 | input in3; | |
2163 | input in4; | |
2164 | input in5; | |
2165 | input in6; | |
2166 | input in7; | |
2167 | input sel0; | |
2168 | input sel1; | |
2169 | input sel2; | |
2170 | input sel3; | |
2171 | input sel4; | |
2172 | input sel5; | |
2173 | input sel6; | |
2174 | input sel7; | |
2175 | output out; | |
2176 | ||
2177 | `ifdef LIB | |
2178 | assign out = ((sel0 & in0) | | |
2179 | (sel1 & in1) | | |
2180 | (sel2 & in2) | | |
2181 | (sel3 & in3) | | |
2182 | (sel4 & in4) | | |
2183 | (sel5 & in5) | | |
2184 | (sel6 & in6) | | |
2185 | (sel7 & in7)); | |
2186 | `endif | |
2187 | ||
2188 | ||
2189 | endmodule | |
2190 | module cl_dp1_aomux8_8x ( | |
2191 | in0, | |
2192 | in1, | |
2193 | in2, | |
2194 | in3, | |
2195 | in4, | |
2196 | in5, | |
2197 | in6, | |
2198 | in7, | |
2199 | sel0, | |
2200 | sel1, | |
2201 | sel2, | |
2202 | sel3, | |
2203 | sel4, | |
2204 | sel5, | |
2205 | sel6, | |
2206 | sel7, | |
2207 | out | |
2208 | ); | |
2209 | input in0; | |
2210 | input in1; | |
2211 | input in2; | |
2212 | input in3; | |
2213 | input in4; | |
2214 | input in5; | |
2215 | input in6; | |
2216 | input in7; | |
2217 | input sel0; | |
2218 | input sel1; | |
2219 | input sel2; | |
2220 | input sel3; | |
2221 | input sel4; | |
2222 | input sel5; | |
2223 | input sel6; | |
2224 | input sel7; | |
2225 | output out; | |
2226 | ||
2227 | `ifdef LIB | |
2228 | assign out = ((sel0 & in0) | | |
2229 | (sel1 & in1) | | |
2230 | (sel2 & in2) | | |
2231 | (sel3 & in3) | | |
2232 | (sel4 & in4) | | |
2233 | (sel5 & in5) | | |
2234 | (sel6 & in6) | | |
2235 | (sel7 & in7)); | |
2236 | `endif | |
2237 | ||
2238 | ||
2239 | endmodule | |
2240 | module cl_dp1_boothenc_4x ( | |
2241 | din, | |
2242 | xr_mode, | |
2243 | dout, | |
2244 | pout, | |
2245 | hout | |
2246 | ); | |
2247 | ||
2248 | input [2:0] din; | |
2249 | ||
2250 | input xr_mode; | |
2251 | ||
2252 | output [4:0] dout; | |
2253 | ||
2254 | output pout; | |
2255 | ||
2256 | output hout; | |
2257 | `ifdef LIB | |
2258 | assign dout[0] = (~xr_mode & ~din[2] & ~din[1] & din[0]) | // +1 | |
2259 | (~xr_mode & ~din[2] & din[1] & ~din[0]) | | |
2260 | ( xr_mode & ~din[2] & din[1] ); | |
2261 | ||
2262 | assign dout[1] = (~xr_mode & ~din[2] & din[1] & din[0]) | // +2 | |
2263 | ( xr_mode & din[2] & ~din[1] ); | |
2264 | ||
2265 | assign dout[2] = (~xr_mode & din[2] & ~din[1] & ~din[0]); // -2 | |
2266 | ||
2267 | assign dout[3] = (~xr_mode & din[2] & ~din[1] & din[0]) | // -1 | |
2268 | (~xr_mode & din[2] & din[1] & ~din[0]); | |
2269 | ||
2270 | assign dout[4] = ( xr_mode & din[2] & din[1] ); // +3 | |
2271 | ||
2272 | ||
2273 | assign pout = (~xr_mode & ~din[2] ) | // P | |
2274 | (~xr_mode & din[1] & din[0]); | |
2275 | ||
2276 | assign hout = (~xr_mode & din[2] & ~din[1] ) | // H | |
2277 | (~xr_mode & din[2] & ~din[0]); | |
2278 | ||
2279 | `endif | |
2280 | ||
2281 | ||
2282 | ||
2283 | endmodule | |
2284 | ||
2285 | module cl_dp1_boothenc_8x ( | |
2286 | din, | |
2287 | xr_mode, | |
2288 | dout, | |
2289 | pout, | |
2290 | hout | |
2291 | ); | |
2292 | ||
2293 | input [2:0] din; | |
2294 | ||
2295 | input xr_mode; | |
2296 | ||
2297 | output [4:0] dout; | |
2298 | ||
2299 | output pout; | |
2300 | ||
2301 | output hout; | |
2302 | `ifdef LIB | |
2303 | assign dout[0] = (~xr_mode & ~din[2] & ~din[1] & din[0]) | // +1 | |
2304 | (~xr_mode & ~din[2] & din[1] & ~din[0]) | | |
2305 | ( xr_mode & ~din[2] & din[1] ); | |
2306 | ||
2307 | assign dout[1] = (~xr_mode & ~din[2] & din[1] & din[0]) | // +2 | |
2308 | ( xr_mode & din[2] & ~din[1] ); | |
2309 | ||
2310 | assign dout[2] = (~xr_mode & din[2] & ~din[1] & ~din[0]); // -2 | |
2311 | ||
2312 | assign dout[3] = (~xr_mode & din[2] & ~din[1] & din[0]) | // -1 | |
2313 | (~xr_mode & din[2] & din[1] & ~din[0]); | |
2314 | ||
2315 | assign dout[4] = ( xr_mode & din[2] & din[1] ); // +3 | |
2316 | ||
2317 | ||
2318 | assign pout = (~xr_mode & ~din[2] ) | // P | |
2319 | (~xr_mode & din[1] & din[0]); | |
2320 | ||
2321 | assign hout = (~xr_mode & din[2] & ~din[1] ) | // H | |
2322 | (~xr_mode & din[2] & ~din[0]); | |
2323 | ||
2324 | `endif | |
2325 | ||
2326 | ||
2327 | ||
2328 | endmodule | |
2329 | ||
2330 | module cl_dp1_cmpr12_8x ( | |
2331 | in0, | |
2332 | in1, | |
2333 | out | |
2334 | ); | |
2335 | input [11:0] in0; | |
2336 | input [11:0] in1; | |
2337 | output out; | |
2338 | ||
2339 | `ifdef LIB | |
2340 | assign out = (in0[11:0] == in1[11:0]); | |
2341 | `endif | |
2342 | ||
2343 | endmodule | |
2344 | module cl_dp1_cmpr16_8x ( | |
2345 | in0, | |
2346 | in1, | |
2347 | out | |
2348 | ); | |
2349 | input [15:0] in0; | |
2350 | input [15:0] in1; | |
2351 | output out; | |
2352 | ||
2353 | `ifdef LIB | |
2354 | assign out = (in0[15:0] == in1[15:0]); | |
2355 | `endif | |
2356 | ||
2357 | endmodule | |
2358 | module cl_dp1_cmpr32_8x ( | |
2359 | in0, | |
2360 | in1, | |
2361 | out | |
2362 | ); | |
2363 | input [31:0] in0; | |
2364 | input [31:0] in1; | |
2365 | output out; | |
2366 | ||
2367 | `ifdef LIB | |
2368 | assign out = (in0[31:0] == in1[31:0]); | |
2369 | `endif | |
2370 | ||
2371 | endmodule | |
2372 | module cl_dp1_cmpr4_8x ( | |
2373 | in0, | |
2374 | in1, | |
2375 | out | |
2376 | ); | |
2377 | input [3:0] in0; | |
2378 | input [3:0] in1; | |
2379 | output out; | |
2380 | ||
2381 | `ifdef LIB | |
2382 | assign out = (in0[3:0] == in1[3:0]); | |
2383 | `endif | |
2384 | ||
2385 | endmodule | |
2386 | module cl_dp1_cmpr64_8x ( | |
2387 | in0, | |
2388 | in1, | |
2389 | out | |
2390 | ); | |
2391 | input [63:0] in0; | |
2392 | input [63:0] in1; | |
2393 | output out; | |
2394 | ||
2395 | `ifdef LIB | |
2396 | assign out = (in0[63:0] == in1[63:0]); | |
2397 | `endif | |
2398 | ||
2399 | endmodule | |
2400 | module cl_dp1_cmpr8_8x ( | |
2401 | in0, | |
2402 | in1, | |
2403 | out | |
2404 | ); | |
2405 | input [7:0] in0; | |
2406 | input [7:0] in1; | |
2407 | output out; | |
2408 | ||
2409 | `ifdef LIB | |
2410 | assign out = (in0[7:0] == in1[7:0]); | |
2411 | `endif | |
2412 | ||
2413 | endmodule | |
2414 | module cl_dp1_incr12_8x ( | |
2415 | cin, | |
2416 | in0, | |
2417 | out, | |
2418 | cout | |
2419 | ); | |
2420 | input cin; | |
2421 | input [11:0] in0; | |
2422 | output [11:0] out; | |
2423 | output cout; | |
2424 | ||
2425 | `ifdef LIB | |
2426 | assign {cout, out[11:0]} = {1'b0, in0[11:0]} + {12'b0, cin}; | |
2427 | `endif | |
2428 | ||
2429 | endmodule | |
2430 | module cl_dp1_incr16_8x ( | |
2431 | cin, | |
2432 | in0, | |
2433 | out, | |
2434 | cout | |
2435 | ); | |
2436 | input cin; | |
2437 | input [15:0] in0; | |
2438 | output [15:0] out; | |
2439 | output cout; | |
2440 | ||
2441 | `ifdef LIB | |
2442 | assign {cout, out[15:0]} = {1'b0, in0[15:0]} + {16'b0, cin}; | |
2443 | `endif | |
2444 | ||
2445 | endmodule | |
2446 | module cl_dp1_incr32_8x ( | |
2447 | cin, | |
2448 | in0, | |
2449 | out, | |
2450 | cout | |
2451 | ); | |
2452 | input cin; | |
2453 | input [31:0] in0; | |
2454 | output [31:0] out; | |
2455 | output cout; | |
2456 | ||
2457 | `ifdef LIB | |
2458 | assign {cout, out[31:0]} = {1'b0, in0[31:0]} + {32'b0, cin}; | |
2459 | `endif | |
2460 | ||
2461 | endmodule | |
2462 | module cl_dp1_incr4_8x ( | |
2463 | cin, | |
2464 | in0, | |
2465 | out, | |
2466 | cout | |
2467 | ); | |
2468 | input cin; | |
2469 | input [3:0] in0; | |
2470 | output [3:0] out; | |
2471 | output cout; | |
2472 | ||
2473 | `ifdef LIB | |
2474 | assign {cout, out[3:0]} = {1'b0, in0[3:0]} + {4'b0, cin}; | |
2475 | `endif | |
2476 | ||
2477 | endmodule | |
2478 | module cl_dp1_incr48_8x ( | |
2479 | cin, | |
2480 | in0, | |
2481 | out, | |
2482 | cout | |
2483 | ); | |
2484 | input cin; | |
2485 | input [47:0] in0; | |
2486 | output [47:0] out; | |
2487 | output cout; | |
2488 | ||
2489 | `ifdef LIB | |
2490 | assign {cout, out[47:0]} = {1'b0, in0[47:0]} + {48'b0, cin}; | |
2491 | `endif | |
2492 | ||
2493 | endmodule | |
2494 | module cl_dp1_incr64_8x ( | |
2495 | cin, | |
2496 | in0, | |
2497 | out, | |
2498 | cout | |
2499 | ); | |
2500 | input cin; | |
2501 | input [63:0] in0; | |
2502 | output [63:0] out; | |
2503 | output cout; | |
2504 | ||
2505 | `ifdef LIB | |
2506 | assign {cout, out[63:0]} = {1'b0, in0[63:0]} + {64'b0, cin}; | |
2507 | `endif | |
2508 | ||
2509 | endmodule | |
2510 | module cl_dp1_incr8_8x ( | |
2511 | cin, | |
2512 | in0, | |
2513 | out, | |
2514 | cout | |
2515 | ); | |
2516 | input cin; | |
2517 | input [7:0] in0; | |
2518 | output [7:0] out; | |
2519 | output cout; | |
2520 | ||
2521 | `ifdef LIB | |
2522 | assign {cout, out[7:0]} = {1'b0, in0[7:0]} + {8'b0, cin}; | |
2523 | `endif | |
2524 | ||
2525 | endmodule // cl_dp1_incr8_8x | |
2526 | module cl_dp1_l1hdr_12x (l1clk, | |
2527 | l2clk, | |
2528 | se, | |
2529 | pce, | |
2530 | pce_ov, | |
2531 | stop, | |
2532 | aclk, | |
2533 | bclk, | |
2534 | siclk_out, | |
2535 | soclk_out | |
2536 | ); | |
2537 | // RFM 05/21/2004 | |
2538 | ||
2539 | ||
2540 | output l1clk; | |
2541 | input l2clk; // level 2 clock, from clock grid | |
2542 | input se; // Scan Enable | |
2543 | input pce; // Clock enable for local power savings | |
2544 | input pce_ov; // TCU sourced clock enable override for testing | |
2545 | input stop; // TCU/CCU sourced clock stop for debug | |
2546 | input aclk; | |
2547 | input bclk; | |
2548 | output siclk_out; | |
2549 | output soclk_out; | |
2550 | `ifdef FORMAL_TOOL | |
2551 | wire l1en = (~stop & ( pce | pce_ov )); | |
2552 | assign l1clk = (l2clk & l1en) | se; | |
2553 | assign siclk_out = aclk; | |
2554 | assign soclk_out = bclk; | |
2555 | `else | |
2556 | `ifdef LIB | |
2557 | reg l1en; | |
2558 | `ifdef SCAN_MODE | |
2559 | always @ (l2clk or stop or pce or pce_ov) | |
2560 | begin | |
2561 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2562 | end | |
2563 | `else | |
2564 | always @ (negedge l2clk ) | |
2565 | begin | |
2566 | l1en <= (~stop & ( pce | pce_ov )); | |
2567 | end | |
2568 | `endif | |
2569 | ||
2570 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2571 | ||
2572 | assign siclk_out = aclk; | |
2573 | assign soclk_out = bclk; | |
2574 | ||
2575 | `endif // `ifdef LIB | |
2576 | `endif // !`ifdef FORMAL_TOOL | |
2577 | ||
2578 | ||
2579 | endmodule | |
2580 | ||
2581 | module cl_dp1_l1hdr_16x (l1clk, | |
2582 | l2clk, | |
2583 | se, | |
2584 | pce, | |
2585 | pce_ov, | |
2586 | stop, | |
2587 | aclk, | |
2588 | bclk, | |
2589 | siclk_out, | |
2590 | soclk_out | |
2591 | ); | |
2592 | // RFM 05/21/2004 | |
2593 | ||
2594 | ||
2595 | output l1clk; | |
2596 | input l2clk; // level 2 clock, from clock grid | |
2597 | input se; // Scan Enable | |
2598 | input pce; // Clock enable for local power savings | |
2599 | input pce_ov; // TCU sourced clock enable override for testing | |
2600 | input stop; // TCU/CCU sourced clock stop for debug | |
2601 | input aclk; | |
2602 | input bclk; | |
2603 | output siclk_out; | |
2604 | output soclk_out; | |
2605 | `ifdef FORMAL_TOOL | |
2606 | wire l1en = (~stop & ( pce | pce_ov )); | |
2607 | assign l1clk = (l2clk & l1en) | se; | |
2608 | assign siclk_out = aclk; | |
2609 | assign soclk_out = bclk; | |
2610 | `else | |
2611 | `ifdef LIB | |
2612 | reg l1en; | |
2613 | `ifdef SCAN_MODE | |
2614 | always @ (l2clk or stop or pce or pce_ov) | |
2615 | begin | |
2616 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2617 | end | |
2618 | `else | |
2619 | always @ (negedge l2clk ) | |
2620 | begin | |
2621 | l1en <= (~stop & ( pce | pce_ov )); | |
2622 | end | |
2623 | `endif | |
2624 | ||
2625 | ||
2626 | ||
2627 | ||
2628 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2629 | ||
2630 | assign siclk_out = aclk; | |
2631 | assign soclk_out = bclk; | |
2632 | ||
2633 | `endif | |
2634 | `endif | |
2635 | ||
2636 | endmodule | |
2637 | module cl_dp1_l1hdr_24x (l1clk, | |
2638 | l2clk, | |
2639 | se, | |
2640 | pce, | |
2641 | pce_ov, | |
2642 | stop, | |
2643 | aclk, | |
2644 | bclk, | |
2645 | siclk_out, | |
2646 | soclk_out | |
2647 | ); | |
2648 | // RFM 05/21/2004 | |
2649 | ||
2650 | ||
2651 | output l1clk; | |
2652 | input l2clk; // level 2 clock, from clock grid | |
2653 | input se; // Scan Enable | |
2654 | input pce; // Clock enable for local power savings | |
2655 | input pce_ov; // TCU sourced clock enable override for testing | |
2656 | input stop; // TCU/CCU sourced clock stop for debug | |
2657 | input aclk; | |
2658 | input bclk; | |
2659 | output siclk_out; | |
2660 | output soclk_out; | |
2661 | `ifdef FORMAL_TOOL | |
2662 | wire l1en = (~stop & ( pce | pce_ov )); | |
2663 | assign l1clk = (l2clk & l1en) | se; | |
2664 | assign siclk_out = aclk; | |
2665 | assign soclk_out = bclk; | |
2666 | `else | |
2667 | `ifdef LIB | |
2668 | reg l1en; | |
2669 | ||
2670 | `ifdef SCAN_MODE | |
2671 | always @ (l2clk or stop or pce or pce_ov) | |
2672 | begin | |
2673 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2674 | end | |
2675 | `else | |
2676 | always @ (negedge l2clk ) | |
2677 | begin | |
2678 | l1en <= (~stop & ( pce | pce_ov )); | |
2679 | end | |
2680 | `endif | |
2681 | ||
2682 | ||
2683 | ||
2684 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2685 | ||
2686 | assign siclk_out = aclk; | |
2687 | assign soclk_out = bclk; | |
2688 | ||
2689 | `endif | |
2690 | `endif | |
2691 | ||
2692 | endmodule | |
2693 | module cl_dp1_l1hdr_32x (l1clk, | |
2694 | l2clk, | |
2695 | se, | |
2696 | pce, | |
2697 | pce_ov, | |
2698 | stop, | |
2699 | aclk, | |
2700 | bclk, | |
2701 | siclk_out, | |
2702 | soclk_out | |
2703 | ); | |
2704 | // RFM 05/21/2004 | |
2705 | ||
2706 | ||
2707 | output l1clk; | |
2708 | input l2clk; // level 2 clock, from clock grid | |
2709 | input se; // Scan Enable | |
2710 | input pce; // Clock enable for local power savings | |
2711 | input pce_ov; // TCU sourced clock enable override for testing | |
2712 | input stop; // TCU/CCU sourced clock stop for debug | |
2713 | input aclk; | |
2714 | input bclk; | |
2715 | output siclk_out; | |
2716 | output soclk_out; | |
2717 | `ifdef FORMAL_TOOL | |
2718 | wire l1en = (~stop & ( pce | pce_ov )); | |
2719 | assign l1clk = (l2clk & l1en) | se; | |
2720 | assign siclk_out = aclk; | |
2721 | assign soclk_out = bclk; | |
2722 | `else | |
2723 | `ifdef LIB | |
2724 | reg l1en; | |
2725 | ||
2726 | ||
2727 | ||
2728 | `ifdef SCAN_MODE | |
2729 | always @ (l2clk or stop or pce or pce_ov) | |
2730 | begin | |
2731 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2732 | end | |
2733 | `else | |
2734 | always @ (negedge l2clk ) | |
2735 | begin | |
2736 | l1en <= (~stop & ( pce | pce_ov )); | |
2737 | end | |
2738 | `endif | |
2739 | ||
2740 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2741 | ||
2742 | assign siclk_out = aclk; | |
2743 | assign soclk_out = bclk; | |
2744 | ||
2745 | `endif | |
2746 | `endif | |
2747 | ||
2748 | endmodule | |
2749 | module cl_dp1_l1hdr_4x (l1clk, | |
2750 | l2clk, | |
2751 | se, | |
2752 | pce, | |
2753 | pce_ov, | |
2754 | stop, | |
2755 | aclk, | |
2756 | bclk, | |
2757 | siclk_out, | |
2758 | soclk_out | |
2759 | ); | |
2760 | // RFM 05/21/2004 | |
2761 | ||
2762 | ||
2763 | output l1clk; | |
2764 | input l2clk; // level 2 clock, from clock grid | |
2765 | input se; // Scan Enable | |
2766 | input pce; // Clock enable for local power savings | |
2767 | input pce_ov; // TCU sourced clock enable override for testing | |
2768 | input stop; // TCU/CCU sourced clock stop for debug | |
2769 | input aclk; | |
2770 | input bclk; | |
2771 | output siclk_out; | |
2772 | output soclk_out; | |
2773 | `ifdef FORMAL_TOOL | |
2774 | wire l1en = (~stop & ( pce | pce_ov )); | |
2775 | assign l1clk = (l2clk & l1en) | se; | |
2776 | assign siclk_out = aclk; | |
2777 | assign soclk_out = bclk; | |
2778 | `else | |
2779 | `ifdef LIB | |
2780 | reg l1en; | |
2781 | ||
2782 | ||
2783 | ||
2784 | `ifdef SCAN_MODE | |
2785 | always @ (l2clk or stop or pce or pce_ov) | |
2786 | begin | |
2787 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2788 | end | |
2789 | `else | |
2790 | always @ (negedge l2clk ) | |
2791 | begin | |
2792 | l1en <= (~stop & ( pce | pce_ov )); | |
2793 | end | |
2794 | `endif | |
2795 | ||
2796 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2797 | ||
2798 | assign siclk_out = aclk; | |
2799 | assign soclk_out = bclk; | |
2800 | ||
2801 | `endif | |
2802 | `endif | |
2803 | ||
2804 | endmodule | |
2805 | module cl_dp1_l1hdr_8x (l1clk, | |
2806 | l2clk, | |
2807 | se, | |
2808 | pce, | |
2809 | pce_ov, | |
2810 | stop, | |
2811 | aclk, | |
2812 | bclk, | |
2813 | siclk_out, | |
2814 | soclk_out | |
2815 | ); | |
2816 | // RFM 05/21/2004 | |
2817 | ||
2818 | ||
2819 | output l1clk; | |
2820 | input l2clk; // level 2 clock, from clock grid | |
2821 | input se; // Scan Enable | |
2822 | input pce; // Clock enable for local power savings | |
2823 | input pce_ov; // TCU sourced clock enable override for testing | |
2824 | input stop; // TCU/CCU sourced clock stop for debug | |
2825 | input aclk; | |
2826 | input bclk; | |
2827 | output siclk_out; | |
2828 | output soclk_out; | |
2829 | `ifdef FORMAL_TOOL | |
2830 | wire l1en = (~stop & ( pce | pce_ov )); | |
2831 | assign l1clk = (l2clk & l1en) | se; | |
2832 | assign siclk_out = aclk; | |
2833 | assign soclk_out = bclk; | |
2834 | `else | |
2835 | `ifdef LIB | |
2836 | reg l1en; | |
2837 | ||
2838 | ||
2839 | ||
2840 | `ifdef SCAN_MODE | |
2841 | always @ (l2clk or stop or pce or pce_ov) | |
2842 | begin | |
2843 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2844 | end | |
2845 | `else | |
2846 | always @ (negedge l2clk ) | |
2847 | begin | |
2848 | l1en <= (~stop & ( pce | pce_ov )); | |
2849 | end | |
2850 | `endif | |
2851 | ||
2852 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2853 | ||
2854 | assign siclk_out = aclk; | |
2855 | assign soclk_out = bclk; | |
2856 | ||
2857 | `endif | |
2858 | `endif | |
2859 | ||
2860 | endmodule | |
2861 | module cl_dp1_l1hdr_48x (l1clk, | |
2862 | l2clk, | |
2863 | se, | |
2864 | pce, | |
2865 | pce_ov, | |
2866 | stop, | |
2867 | aclk, | |
2868 | bclk, | |
2869 | siclk_out, | |
2870 | soclk_out | |
2871 | ); | |
2872 | // RFM 05/21/2004 | |
2873 | ||
2874 | ||
2875 | output l1clk; | |
2876 | input l2clk; // level 2 clock, from clock grid | |
2877 | input se; // Scan Enable | |
2878 | input pce; // Clock enable for local power savings | |
2879 | input pce_ov; // TCU sourced clock enable override for testing | |
2880 | input stop; // TCU/CCU sourced clock stop for debug | |
2881 | input aclk; | |
2882 | input bclk; | |
2883 | output siclk_out; | |
2884 | output soclk_out; | |
2885 | `ifdef FORMAL_TOOL | |
2886 | wire l1en = (~stop & ( pce | pce_ov )); | |
2887 | assign l1clk = (l2clk & l1en) | se; | |
2888 | assign siclk_out = aclk; | |
2889 | assign soclk_out = bclk; | |
2890 | `else | |
2891 | `ifdef LIB | |
2892 | reg l1en; | |
2893 | ||
2894 | ||
2895 | ||
2896 | `ifdef SCAN_MODE | |
2897 | always @ (l2clk or stop or pce or pce_ov) | |
2898 | begin | |
2899 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2900 | end | |
2901 | `else | |
2902 | always @ (negedge l2clk ) | |
2903 | begin | |
2904 | l1en <= (~stop & ( pce | pce_ov )); | |
2905 | end | |
2906 | `endif | |
2907 | ||
2908 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2909 | ||
2910 | assign siclk_out = aclk; | |
2911 | assign soclk_out = bclk; | |
2912 | ||
2913 | `endif | |
2914 | `endif | |
2915 | ||
2916 | endmodule | |
2917 | module cl_dp1_l1hdr_64x (l1clk, | |
2918 | l2clk, | |
2919 | se, | |
2920 | pce, | |
2921 | pce_ov, | |
2922 | stop, | |
2923 | aclk, | |
2924 | bclk, | |
2925 | siclk_out, | |
2926 | soclk_out | |
2927 | ); | |
2928 | // RFM 05/21/2004 | |
2929 | ||
2930 | ||
2931 | output l1clk; | |
2932 | input l2clk; // level 2 clock, from clock grid | |
2933 | input se; // Scan Enable | |
2934 | input pce; // Clock enable for local power savings | |
2935 | input pce_ov; // TCU sourced clock enable override for testing | |
2936 | input stop; // TCU/CCU sourced clock stop for debug | |
2937 | input aclk; | |
2938 | input bclk; | |
2939 | output siclk_out; | |
2940 | output soclk_out; | |
2941 | `ifdef FORMAL_TOOL | |
2942 | wire l1en = (~stop & ( pce | pce_ov )); | |
2943 | assign l1clk = (l2clk & l1en) | se; | |
2944 | assign siclk_out = aclk; | |
2945 | assign soclk_out = bclk; | |
2946 | `else | |
2947 | `ifdef LIB | |
2948 | reg l1en; | |
2949 | ||
2950 | ||
2951 | ||
2952 | `ifdef SCAN_MODE | |
2953 | always @ (l2clk or stop or pce or pce_ov) | |
2954 | begin | |
2955 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
2956 | end | |
2957 | `else | |
2958 | always @ (negedge l2clk ) | |
2959 | begin | |
2960 | l1en <= (~stop & ( pce | pce_ov )); | |
2961 | end | |
2962 | `endif | |
2963 | ||
2964 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
2965 | ||
2966 | assign siclk_out = aclk; | |
2967 | assign soclk_out = bclk; | |
2968 | ||
2969 | `endif | |
2970 | `endif | |
2971 | ||
2972 | endmodule | |
2973 | module cl_dp1_l1hdr_nostop_48x (l1clk, | |
2974 | l2clk, | |
2975 | se, | |
2976 | pce, | |
2977 | pce_ov, | |
2978 | stop, | |
2979 | aclk, | |
2980 | bclk, | |
2981 | siclk_out, | |
2982 | soclk_out | |
2983 | ); | |
2984 | // RFM 05/21/2004 | |
2985 | ||
2986 | ||
2987 | output l1clk; | |
2988 | input l2clk; // level 2 clock, from clock grid | |
2989 | input se; // Scan Enable | |
2990 | input pce; // Clock enable for local power savings | |
2991 | input pce_ov; // TCU sourced clock enable override for testing | |
2992 | input stop; // TCU/CCU sourced clock stop for debug | |
2993 | input aclk; | |
2994 | input bclk; | |
2995 | output siclk_out; | |
2996 | output soclk_out; | |
2997 | `ifdef FORMAL_TOOL | |
2998 | wire l1en = pce | pce_ov ; | |
2999 | assign l1clk = (l2clk & l1en) | se; | |
3000 | assign siclk_out = aclk; | |
3001 | assign soclk_out = bclk; | |
3002 | `else | |
3003 | `ifdef LIB | |
3004 | reg l1en; | |
3005 | `ifdef SCAN_MODE | |
3006 | always @ (l2clk or stop or pce or pce_ov) | |
3007 | begin | |
3008 | if (~l2clk) l1en <= ((pce | pce_ov)); | |
3009 | end | |
3010 | `else | |
3011 | ||
3012 | ||
3013 | always @ (negedge l2clk ) | |
3014 | begin | |
3015 | l1en <= (( pce | pce_ov )); | |
3016 | end | |
3017 | `endif | |
3018 | ||
3019 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
3020 | ||
3021 | assign siclk_out = aclk; | |
3022 | assign soclk_out = bclk; | |
3023 | ||
3024 | `endif | |
3025 | `endif | |
3026 | ||
3027 | endmodule | |
3028 | module cl_dp1_inv_diode_16x ( | |
3029 | in, | |
3030 | out | |
3031 | ); | |
3032 | input in; | |
3033 | output out; | |
3034 | ||
3035 | `ifdef LIB | |
3036 | assign out = ~in; | |
3037 | `endif | |
3038 | ||
3039 | endmodule | |
3040 | module cl_dp1_l1hdr_nostop_72x (l1clk, | |
3041 | l2clk, | |
3042 | se, | |
3043 | pce, | |
3044 | pce_ov, | |
3045 | stop, | |
3046 | aclk, | |
3047 | bclk, | |
3048 | siclk_out, | |
3049 | soclk_out | |
3050 | ); | |
3051 | // RFM 05/21/2004 | |
3052 | ||
3053 | ||
3054 | output l1clk; | |
3055 | input l2clk; // level 2 clock, from clock grid | |
3056 | input se; // Scan Enable | |
3057 | input pce; // Clock enable for local power savings | |
3058 | input pce_ov; // TCU sourced clock enable override for testing | |
3059 | input stop; // TCU/CCU sourced clock stop for debug | |
3060 | input aclk; | |
3061 | input bclk; | |
3062 | output siclk_out; | |
3063 | output soclk_out; | |
3064 | `ifdef FORMAL_TOOL | |
3065 | wire l1en = pce | pce_ov ; | |
3066 | assign l1clk = (l2clk & l1en) | se; | |
3067 | assign siclk_out = aclk; | |
3068 | assign soclk_out = bclk; | |
3069 | `else | |
3070 | `ifdef LIB | |
3071 | reg l1en; | |
3072 | `ifdef SCAN_MODE | |
3073 | always @ (l2clk or stop or pce or pce_ov) | |
3074 | begin | |
3075 | if (~l2clk) l1en <= ((pce | pce_ov)); | |
3076 | end | |
3077 | `else | |
3078 | ||
3079 | ||
3080 | always @ (negedge l2clk ) | |
3081 | begin | |
3082 | l1en <= (( pce | pce_ov )); | |
3083 | end | |
3084 | `endif | |
3085 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
3086 | ||
3087 | assign siclk_out = aclk; | |
3088 | assign soclk_out = bclk; | |
3089 | ||
3090 | `endif | |
3091 | `endif | |
3092 | ||
3093 | endmodule | |
3094 | module cl_dp1_l1hdr_nostop_64x (l1clk, | |
3095 | l2clk, | |
3096 | se, | |
3097 | pce, | |
3098 | pce_ov, | |
3099 | stop, | |
3100 | aclk, | |
3101 | bclk, | |
3102 | siclk_out, | |
3103 | soclk_out | |
3104 | ); | |
3105 | // RFM 05/21/2004 | |
3106 | ||
3107 | ||
3108 | output l1clk; | |
3109 | input l2clk; // level 2 clock, from clock grid | |
3110 | input se; // Scan Enable | |
3111 | input pce; // Clock enable for local power savings | |
3112 | input pce_ov; // TCU sourced clock enable override for testing | |
3113 | input stop; // TCU/CCU sourced clock stop for debug | |
3114 | input aclk; | |
3115 | input bclk; | |
3116 | output siclk_out; | |
3117 | output soclk_out; | |
3118 | `ifdef FORMAL_TOOL | |
3119 | wire l1en = pce | pce_ov ; | |
3120 | assign l1clk = (l2clk & l1en) | se; | |
3121 | assign siclk_out = aclk; | |
3122 | assign soclk_out = bclk; | |
3123 | `else | |
3124 | `ifdef LIB | |
3125 | reg l1en; | |
3126 | ||
3127 | `ifdef SCAN_MODE | |
3128 | always @ (l2clk or stop or pce or pce_ov) | |
3129 | begin | |
3130 | if (~l2clk) l1en <= ((pce | pce_ov)); | |
3131 | end | |
3132 | `else | |
3133 | ||
3134 | always @ (negedge l2clk ) | |
3135 | begin | |
3136 | l1en <= (( pce | pce_ov )); | |
3137 | end | |
3138 | `endif | |
3139 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
3140 | ||
3141 | assign siclk_out = aclk; | |
3142 | assign soclk_out = bclk; | |
3143 | ||
3144 | `endif | |
3145 | `endif | |
3146 | ||
3147 | endmodule | |
3148 | module cl_dp1_msff_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
3149 | // RFM 05-14-2004 | |
3150 | // Level sensitive in SCAN_MODE | |
3151 | // Edge triggered when not in SCAN_MODE | |
3152 | ||
3153 | ||
3154 | parameter SIZE = 1; | |
3155 | ||
3156 | output q; | |
3157 | output so; | |
3158 | ||
3159 | input d; | |
3160 | input l1clk; | |
3161 | input si; | |
3162 | input siclk; | |
3163 | input soclk; | |
3164 | ||
3165 | reg q; | |
3166 | wire so; | |
3167 | wire l1clk, siclk, soclk; | |
3168 | ||
3169 | `ifdef SCAN_MODE | |
3170 | ||
3171 | reg l1; | |
3172 | `ifdef FAST_FLUSH | |
3173 | always @(posedge l1clk or posedge siclk ) begin | |
3174 | if (siclk) begin | |
3175 | q <= 1'b0; //pseudo flush reset | |
3176 | end else begin | |
3177 | q <= d; | |
3178 | end | |
3179 | end | |
3180 | `else | |
3181 | always @(l1clk or siclk or soclk or d or si) | |
3182 | begin | |
3183 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3184 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3185 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3186 | ||
3187 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3188 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3189 | end | |
3190 | `endif | |
3191 | `else | |
3192 | wire si_unused; | |
3193 | wire siclk_unused; | |
3194 | wire soclk_unused; | |
3195 | assign si_unused = si; | |
3196 | assign siclk_unused = siclk; | |
3197 | assign soclk_unused = soclk; | |
3198 | ||
3199 | ||
3200 | `ifdef INITLATZERO | |
3201 | initial q = 1'b0; | |
3202 | `endif | |
3203 | ||
3204 | always @(posedge l1clk) | |
3205 | begin | |
3206 | if (!siclk && !soclk) q <= d; | |
3207 | else q <= 1'bx; | |
3208 | end | |
3209 | `endif | |
3210 | ||
3211 | assign so = q; | |
3212 | ||
3213 | endmodule // dff | |
3214 | ||
3215 | module cl_dp1_msff_1x ( q, so, d, l1clk, si, siclk, soclk ); | |
3216 | // RFM 05-14-2004 | |
3217 | // Level sensitive in SCAN_MODE | |
3218 | // Edge triggered when not in SCAN_MODE | |
3219 | ||
3220 | ||
3221 | parameter SIZE = 1; | |
3222 | ||
3223 | output q; | |
3224 | output so; | |
3225 | ||
3226 | input d; | |
3227 | input l1clk; | |
3228 | input si; | |
3229 | input siclk; | |
3230 | input soclk; | |
3231 | ||
3232 | reg q; | |
3233 | wire so; | |
3234 | wire l1clk, siclk, soclk; | |
3235 | ||
3236 | `ifdef SCAN_MODE | |
3237 | ||
3238 | reg l1; | |
3239 | `ifdef FAST_FLUSH | |
3240 | always @(posedge l1clk or posedge siclk ) begin | |
3241 | if (siclk) begin | |
3242 | q <= 1'b0; //pseudo flush reset | |
3243 | end else begin | |
3244 | q <= d; | |
3245 | end | |
3246 | end | |
3247 | `else | |
3248 | always @(l1clk or siclk or soclk or d or si) | |
3249 | begin | |
3250 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3251 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3252 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3253 | ||
3254 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3255 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3256 | end | |
3257 | `endif | |
3258 | `else | |
3259 | wire si_unused; | |
3260 | wire siclk_unused; | |
3261 | wire soclk_unused; | |
3262 | assign si_unused = si; | |
3263 | assign siclk_unused = siclk; | |
3264 | assign soclk_unused = soclk; | |
3265 | ||
3266 | ||
3267 | `ifdef INITLATZERO | |
3268 | initial q = 1'b0; | |
3269 | `endif | |
3270 | ||
3271 | always @(posedge l1clk) | |
3272 | begin | |
3273 | if (!siclk && !soclk) q <= d; | |
3274 | else q <= 1'bx; | |
3275 | end | |
3276 | `endif | |
3277 | ||
3278 | assign so = q; | |
3279 | ||
3280 | endmodule // dff | |
3281 | ||
3282 | module cl_dp1_msff_32x ( q, so, d, l1clk, si, siclk, soclk ); | |
3283 | // RFM 05-14-2004 | |
3284 | // Level sensitive in SCAN_MODE | |
3285 | // Edge triggered when not in SCAN_MODE | |
3286 | ||
3287 | ||
3288 | parameter SIZE = 1; | |
3289 | ||
3290 | output q; | |
3291 | output so; | |
3292 | ||
3293 | input d; | |
3294 | input l1clk; | |
3295 | input si; | |
3296 | input siclk; | |
3297 | input soclk; | |
3298 | ||
3299 | reg q; | |
3300 | wire so; | |
3301 | wire l1clk, siclk, soclk; | |
3302 | ||
3303 | `ifdef SCAN_MODE | |
3304 | ||
3305 | reg l1; | |
3306 | `ifdef FAST_FLUSH | |
3307 | always @(posedge l1clk or posedge siclk ) begin | |
3308 | if (siclk) begin | |
3309 | q <= 1'b0; //pseudo flush reset | |
3310 | end else begin | |
3311 | q <= d; | |
3312 | end | |
3313 | end | |
3314 | `else | |
3315 | always @(l1clk or siclk or soclk or d or si) | |
3316 | begin | |
3317 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3318 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3319 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3320 | ||
3321 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3322 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3323 | end | |
3324 | `endif | |
3325 | `else | |
3326 | wire si_unused; | |
3327 | wire siclk_unused; | |
3328 | wire soclk_unused; | |
3329 | assign si_unused = si; | |
3330 | assign siclk_unused = siclk; | |
3331 | assign soclk_unused = soclk; | |
3332 | ||
3333 | ||
3334 | `ifdef INITLATZERO | |
3335 | initial q = 1'b0; | |
3336 | `endif | |
3337 | ||
3338 | always @(posedge l1clk) | |
3339 | begin | |
3340 | if (!siclk && !soclk) q <= d; | |
3341 | else q <= 1'bx; | |
3342 | end | |
3343 | `endif | |
3344 | ||
3345 | assign so = q; | |
3346 | ||
3347 | endmodule // dff | |
3348 | ||
3349 | module cl_dp1_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
3350 | // RFM 05-14-2004 | |
3351 | // Level sensitive in SCAN_MODE | |
3352 | // Edge triggered when not in SCAN_MODE | |
3353 | ||
3354 | ||
3355 | parameter SIZE = 1; | |
3356 | ||
3357 | output q; | |
3358 | output so; | |
3359 | ||
3360 | input d; | |
3361 | input l1clk; | |
3362 | input si; | |
3363 | input siclk; | |
3364 | input soclk; | |
3365 | ||
3366 | reg q; | |
3367 | wire so; | |
3368 | wire l1clk, siclk, soclk; | |
3369 | ||
3370 | `ifdef SCAN_MODE | |
3371 | ||
3372 | reg l1; | |
3373 | `ifdef FAST_FLUSH | |
3374 | always @(posedge l1clk or posedge siclk ) begin | |
3375 | if (siclk) begin | |
3376 | q <= 1'b0; //pseudo flush reset | |
3377 | end else begin | |
3378 | q <= d; | |
3379 | end | |
3380 | end | |
3381 | `else | |
3382 | always @(l1clk or siclk or soclk or d or si) | |
3383 | begin | |
3384 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3385 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3386 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3387 | ||
3388 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3389 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3390 | end | |
3391 | `endif | |
3392 | `else | |
3393 | wire si_unused; | |
3394 | wire siclk_unused; | |
3395 | wire soclk_unused; | |
3396 | assign si_unused = si; | |
3397 | assign siclk_unused = siclk; | |
3398 | assign soclk_unused = soclk; | |
3399 | ||
3400 | ||
3401 | `ifdef INITLATZERO | |
3402 | initial q = 1'b0; | |
3403 | `endif | |
3404 | ||
3405 | always @(posedge l1clk) | |
3406 | begin | |
3407 | if (!siclk && !soclk) q <= d; | |
3408 | else q <= 1'bx; | |
3409 | end | |
3410 | `endif | |
3411 | ||
3412 | assign so = q; | |
3413 | ||
3414 | endmodule // dff | |
3415 | ||
3416 | module cl_dp1_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
3417 | // RFM 05-14-2004 | |
3418 | // Level sensitive in SCAN_MODE | |
3419 | // Edge triggered when not in SCAN_MODE | |
3420 | ||
3421 | ||
3422 | parameter SIZE = 1; | |
3423 | ||
3424 | output q; | |
3425 | output so; | |
3426 | ||
3427 | input d; | |
3428 | input l1clk; | |
3429 | input si; | |
3430 | input siclk; | |
3431 | input soclk; | |
3432 | ||
3433 | reg q; | |
3434 | wire so; | |
3435 | wire l1clk, siclk, soclk; | |
3436 | ||
3437 | `ifdef SCAN_MODE | |
3438 | ||
3439 | reg l1; | |
3440 | `ifdef FAST_FLUSH | |
3441 | always @(posedge l1clk or posedge siclk ) begin | |
3442 | if (siclk) begin | |
3443 | q <= 1'b0; //pseudo flush reset | |
3444 | end else begin | |
3445 | q <= d; | |
3446 | end | |
3447 | end | |
3448 | `else | |
3449 | always @(l1clk or siclk or soclk or d or si) | |
3450 | begin | |
3451 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3452 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3453 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3454 | ||
3455 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3456 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3457 | end | |
3458 | `endif | |
3459 | `else | |
3460 | wire si_unused; | |
3461 | wire siclk_unused; | |
3462 | wire soclk_unused; | |
3463 | assign si_unused = si; | |
3464 | assign siclk_unused = siclk; | |
3465 | assign soclk_unused = soclk; | |
3466 | ||
3467 | ||
3468 | `ifdef INITLATZERO | |
3469 | initial q = 1'b0; | |
3470 | `endif | |
3471 | ||
3472 | always @(posedge l1clk) | |
3473 | begin | |
3474 | if (!siclk && !soclk) q <= d; | |
3475 | else q <= 1'bx; | |
3476 | end | |
3477 | `endif | |
3478 | ||
3479 | assign so = q; | |
3480 | ||
3481 | endmodule // dff | |
3482 | ||
3483 | module cl_dp1_msffi_16x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3484 | // RFM 05-14-2004 | |
3485 | // Level sensitive in SCAN_MODE | |
3486 | // Edge triggered when not in SCAN_MODE | |
3487 | ||
3488 | ||
3489 | parameter SIZE = 1; | |
3490 | ||
3491 | output q_l; | |
3492 | output so; | |
3493 | ||
3494 | input d; | |
3495 | input l1clk; | |
3496 | input si; | |
3497 | input siclk; | |
3498 | input soclk; | |
3499 | ||
3500 | reg q_l; | |
3501 | reg q; | |
3502 | wire so; | |
3503 | wire l1clk, siclk, soclk; | |
3504 | ||
3505 | `ifdef SCAN_MODE | |
3506 | reg l1; | |
3507 | `ifdef FAST_FLUSH | |
3508 | always @(posedge l1clk or posedge siclk ) begin | |
3509 | if (siclk) begin | |
3510 | q <= 1'b0; //pseudo flush reset | |
3511 | end else begin | |
3512 | q <= d; | |
3513 | end | |
3514 | end | |
3515 | `else | |
3516 | ||
3517 | always @(l1clk or siclk or soclk or d or si) | |
3518 | begin | |
3519 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3520 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3521 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3522 | ||
3523 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3524 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3525 | end | |
3526 | `endif | |
3527 | `else | |
3528 | wire si_unused; | |
3529 | wire siclk_unused; | |
3530 | wire soclk_unused; | |
3531 | assign si_unused = si; | |
3532 | assign siclk_unused = siclk; | |
3533 | assign soclk_unused = soclk; | |
3534 | ||
3535 | ||
3536 | `ifdef INITLATZERO | |
3537 | initial q_l = 1'b1; | |
3538 | initial q = 1'b0; | |
3539 | `endif | |
3540 | ||
3541 | always @(posedge l1clk) | |
3542 | begin | |
3543 | if (!siclk && !soclk) q <= d; | |
3544 | else q <= 1'bx; | |
3545 | end | |
3546 | `endif | |
3547 | ||
3548 | ||
3549 | always @ (q) | |
3550 | begin | |
3551 | q_l=~q; | |
3552 | end | |
3553 | ||
3554 | ||
3555 | ||
3556 | assign so = q; | |
3557 | ||
3558 | endmodule // dff | |
3559 | module cl_dp1_msffi_1x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3560 | // RFM 05-14-2004 | |
3561 | // Level sensitive in SCAN_MODE | |
3562 | // Edge triggered when not in SCAN_MODE | |
3563 | ||
3564 | ||
3565 | parameter SIZE = 1; | |
3566 | ||
3567 | output q_l; | |
3568 | output so; | |
3569 | ||
3570 | input d; | |
3571 | input l1clk; | |
3572 | input si; | |
3573 | input siclk; | |
3574 | input soclk; | |
3575 | ||
3576 | reg q_l; | |
3577 | reg q; | |
3578 | wire so; | |
3579 | wire l1clk, siclk, soclk; | |
3580 | ||
3581 | `ifdef SCAN_MODE | |
3582 | reg l1; | |
3583 | `ifdef FAST_FLUSH | |
3584 | always @(posedge l1clk or posedge siclk ) begin | |
3585 | if (siclk) begin | |
3586 | q <= 1'b0; //pseudo flush reset | |
3587 | end else begin | |
3588 | q <= d; | |
3589 | end | |
3590 | end | |
3591 | `else | |
3592 | ||
3593 | always @(l1clk or siclk or soclk or d or si) | |
3594 | begin | |
3595 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3596 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3597 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3598 | ||
3599 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3600 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3601 | end | |
3602 | `endif | |
3603 | `else | |
3604 | wire si_unused; | |
3605 | wire siclk_unused; | |
3606 | wire soclk_unused; | |
3607 | assign si_unused = si; | |
3608 | assign siclk_unused = siclk; | |
3609 | assign soclk_unused = soclk; | |
3610 | ||
3611 | ||
3612 | `ifdef INITLATZERO | |
3613 | initial q_l = 1'b1; | |
3614 | initial q = 1'b0; | |
3615 | `endif | |
3616 | ||
3617 | always @(posedge l1clk) | |
3618 | begin | |
3619 | if (!siclk && !soclk) q <= d; | |
3620 | else q <= 1'bx; | |
3621 | end | |
3622 | `endif | |
3623 | ||
3624 | ||
3625 | always @ (q) | |
3626 | begin | |
3627 | q_l=~q; | |
3628 | end | |
3629 | ||
3630 | ||
3631 | ||
3632 | assign so = q; | |
3633 | ||
3634 | endmodule // dff | |
3635 | module cl_dp1_msffi_32x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3636 | // RFM 05-14-2004 | |
3637 | // Level sensitive in SCAN_MODE | |
3638 | // Edge triggered when not in SCAN_MODE | |
3639 | ||
3640 | ||
3641 | parameter SIZE = 1; | |
3642 | ||
3643 | output q_l; | |
3644 | output so; | |
3645 | ||
3646 | input d; | |
3647 | input l1clk; | |
3648 | input si; | |
3649 | input siclk; | |
3650 | input soclk; | |
3651 | ||
3652 | reg q_l; | |
3653 | reg q; | |
3654 | wire so; | |
3655 | wire l1clk, siclk, soclk; | |
3656 | ||
3657 | `ifdef SCAN_MODE | |
3658 | reg l1; | |
3659 | `ifdef FAST_FLUSH | |
3660 | always @(posedge l1clk or posedge siclk ) begin | |
3661 | if (siclk) begin | |
3662 | q <= 1'b0; //pseudo flush reset | |
3663 | end else begin | |
3664 | q <= d; | |
3665 | end | |
3666 | end | |
3667 | `else | |
3668 | ||
3669 | always @(l1clk or siclk or soclk or d or si) | |
3670 | begin | |
3671 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3672 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3673 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3674 | ||
3675 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3676 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3677 | end | |
3678 | `endif | |
3679 | `else | |
3680 | wire si_unused; | |
3681 | wire siclk_unused; | |
3682 | wire soclk_unused; | |
3683 | assign si_unused = si; | |
3684 | assign siclk_unused = siclk; | |
3685 | assign soclk_unused = soclk; | |
3686 | ||
3687 | ||
3688 | `ifdef INITLATZERO | |
3689 | initial q_l = 1'b1; | |
3690 | initial q = 1'b0; | |
3691 | `endif | |
3692 | ||
3693 | always @(posedge l1clk) | |
3694 | begin | |
3695 | if (!siclk && !soclk) q <= d; | |
3696 | else q <= 1'bx; | |
3697 | end | |
3698 | `endif | |
3699 | ||
3700 | ||
3701 | always @ (q) | |
3702 | begin | |
3703 | q_l=~q; | |
3704 | end | |
3705 | ||
3706 | ||
3707 | ||
3708 | assign so = q; | |
3709 | ||
3710 | endmodule // dff | |
3711 | module cl_dp1_msffi_4x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3712 | // RFM 05-14-2004 | |
3713 | // Level sensitive in SCAN_MODE | |
3714 | // Edge triggered when not in SCAN_MODE | |
3715 | ||
3716 | ||
3717 | parameter SIZE = 1; | |
3718 | ||
3719 | output q_l; | |
3720 | output so; | |
3721 | ||
3722 | input d; | |
3723 | input l1clk; | |
3724 | input si; | |
3725 | input siclk; | |
3726 | input soclk; | |
3727 | ||
3728 | reg q_l; | |
3729 | reg q; | |
3730 | wire so; | |
3731 | wire l1clk, siclk, soclk; | |
3732 | ||
3733 | `ifdef SCAN_MODE | |
3734 | reg l1; | |
3735 | `ifdef FAST_FLUSH | |
3736 | always @(posedge l1clk or posedge siclk ) begin | |
3737 | if (siclk) begin | |
3738 | q <= 1'b0; //pseudo flush reset | |
3739 | end else begin | |
3740 | q <= d; | |
3741 | end | |
3742 | end | |
3743 | `else | |
3744 | ||
3745 | always @(l1clk or siclk or soclk or d or si) | |
3746 | begin | |
3747 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3748 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3749 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3750 | ||
3751 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3752 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3753 | end | |
3754 | `endif | |
3755 | `else | |
3756 | wire si_unused; | |
3757 | wire siclk_unused; | |
3758 | wire soclk_unused; | |
3759 | assign si_unused = si; | |
3760 | assign siclk_unused = siclk; | |
3761 | assign soclk_unused = soclk; | |
3762 | ||
3763 | ||
3764 | `ifdef INITLATZERO | |
3765 | initial q_l = 1'b1; | |
3766 | initial q = 1'b0; | |
3767 | `endif | |
3768 | ||
3769 | always @(posedge l1clk) | |
3770 | begin | |
3771 | if (!siclk && !soclk) q <= d; | |
3772 | else q <= 1'bx; | |
3773 | end | |
3774 | `endif | |
3775 | ||
3776 | ||
3777 | always @ (q) | |
3778 | begin | |
3779 | q_l=~q; | |
3780 | end | |
3781 | ||
3782 | ||
3783 | ||
3784 | assign so = q; | |
3785 | ||
3786 | endmodule // dff | |
3787 | module cl_dp1_msffi_8x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3788 | // RFM 05-14-2004 | |
3789 | // Level sensitive in SCAN_MODE | |
3790 | // Edge triggered when not in SCAN_MODE | |
3791 | ||
3792 | ||
3793 | parameter SIZE = 1; | |
3794 | ||
3795 | output q_l; | |
3796 | output so; | |
3797 | ||
3798 | input d; | |
3799 | input l1clk; | |
3800 | input si; | |
3801 | input siclk; | |
3802 | input soclk; | |
3803 | ||
3804 | reg q_l; | |
3805 | reg q; | |
3806 | wire so; | |
3807 | wire l1clk, siclk, soclk; | |
3808 | ||
3809 | `ifdef SCAN_MODE | |
3810 | reg l1; | |
3811 | `ifdef FAST_FLUSH | |
3812 | always @(posedge l1clk or posedge siclk ) begin | |
3813 | if (siclk) begin | |
3814 | q <= 1'b0; //pseudo flush reset | |
3815 | end else begin | |
3816 | q <= d; | |
3817 | end | |
3818 | end | |
3819 | `else | |
3820 | ||
3821 | always @(l1clk or siclk or soclk or d or si) | |
3822 | begin | |
3823 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
3824 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3825 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3826 | ||
3827 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
3828 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
3829 | end | |
3830 | `endif | |
3831 | `else | |
3832 | wire si_unused; | |
3833 | wire siclk_unused; | |
3834 | wire soclk_unused; | |
3835 | assign si_unused = si; | |
3836 | assign siclk_unused = siclk; | |
3837 | assign soclk_unused = soclk; | |
3838 | ||
3839 | ||
3840 | `ifdef INITLATZERO | |
3841 | initial q_l = 1'b1; | |
3842 | initial q = 1'b0; | |
3843 | `endif | |
3844 | ||
3845 | always @(posedge l1clk) | |
3846 | begin | |
3847 | if (!siclk && !soclk) q <= d; | |
3848 | else q <= 1'bx; | |
3849 | end | |
3850 | `endif | |
3851 | ||
3852 | ||
3853 | always @ (q) | |
3854 | begin | |
3855 | q_l=~q; | |
3856 | end | |
3857 | ||
3858 | ||
3859 | ||
3860 | assign so = q; | |
3861 | ||
3862 | endmodule // dff | |
3863 | module cl_dp1_msffiz_32x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3864 | // RFM 05-14-2004 | |
3865 | // Level sensitive in SCAN_MODE | |
3866 | // Edge triggered when not in SCAN_MODE | |
3867 | ||
3868 | ||
3869 | parameter SIZE = 1; | |
3870 | ||
3871 | output q_l; | |
3872 | output so; | |
3873 | ||
3874 | input d; | |
3875 | input l1clk; | |
3876 | input si; | |
3877 | input siclk; | |
3878 | input soclk; | |
3879 | ||
3880 | reg q_l; | |
3881 | ||
3882 | wire so; | |
3883 | wire l1clk, siclk, soclk; | |
3884 | ||
3885 | `ifdef SCAN_MODE | |
3886 | ||
3887 | reg l1; | |
3888 | `ifdef FAST_FLUSH | |
3889 | always @(posedge l1clk or posedge siclk ) begin | |
3890 | if (siclk) begin | |
3891 | q_l <= 1'b0; //pseudo flush reset | |
3892 | end else begin | |
3893 | q_l <= ~d; | |
3894 | end | |
3895 | end | |
3896 | `else | |
3897 | always @(l1clk or siclk or soclk or d or si) | |
3898 | begin | |
3899 | if (!l1clk && !siclk) l1 <= ~d; // Load master with data | |
3900 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3901 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3902 | ||
3903 | else if ( l1clk && !siclk && !soclk) q_l <= l1; // Load slave with master data | |
3904 | if ( l1clk && siclk && !soclk) q_l <= si; // Flush | |
3905 | end | |
3906 | `endif | |
3907 | `else | |
3908 | wire si_unused; | |
3909 | wire siclk_unused; | |
3910 | wire soclk_unused; | |
3911 | assign si_unused = si; | |
3912 | assign siclk_unused = siclk; | |
3913 | assign soclk_unused = soclk; | |
3914 | ||
3915 | ||
3916 | `ifdef INITLATZERO | |
3917 | initial q_l = 1'b0; | |
3918 | `endif | |
3919 | ||
3920 | always @(posedge l1clk) | |
3921 | begin | |
3922 | if (!siclk && !soclk) q_l <= ~d; | |
3923 | else q_l <= 1'bx; | |
3924 | end | |
3925 | `endif | |
3926 | ||
3927 | assign so = q_l; | |
3928 | ||
3929 | endmodule // dff | |
3930 | module cl_dp1_msffiz_16x ( q_l, so, d, l1clk, si, siclk, soclk ); | |
3931 | // RFM 05-14-2004 | |
3932 | // Level sensitive in SCAN_MODE | |
3933 | // Edge triggered when not in SCAN_MODE | |
3934 | ||
3935 | ||
3936 | parameter SIZE = 1; | |
3937 | ||
3938 | output q_l; | |
3939 | output so; | |
3940 | ||
3941 | input d; | |
3942 | input l1clk; | |
3943 | input si; | |
3944 | input siclk; | |
3945 | input soclk; | |
3946 | ||
3947 | reg q_l; | |
3948 | ||
3949 | wire so; | |
3950 | wire l1clk, siclk, soclk; | |
3951 | ||
3952 | `ifdef SCAN_MODE | |
3953 | ||
3954 | reg l1; | |
3955 | `ifdef FAST_FLUSH | |
3956 | always @(posedge l1clk or posedge siclk ) begin | |
3957 | if (siclk) begin | |
3958 | q_l <= 1'b0; //pseudo flush reset | |
3959 | end else begin | |
3960 | q_l <= ~d; | |
3961 | end | |
3962 | end | |
3963 | `else | |
3964 | always @(l1clk or siclk or soclk or d or si) | |
3965 | begin | |
3966 | if (!l1clk && !siclk) l1 <= ~d; // Load master with data | |
3967 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
3968 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
3969 | ||
3970 | else if ( l1clk && !siclk && !soclk) q_l <= l1; // Load slave with master data | |
3971 | if ( l1clk && siclk && !soclk) q_l <= si; // Flush | |
3972 | end | |
3973 | `endif | |
3974 | `else | |
3975 | wire si_unused; | |
3976 | wire siclk_unused; | |
3977 | wire soclk_unused; | |
3978 | assign si_unused = si; | |
3979 | assign siclk_unused = siclk; | |
3980 | assign soclk_unused = soclk; | |
3981 | ||
3982 | ||
3983 | `ifdef INITLATZERO | |
3984 | initial q_l = 1'b0; | |
3985 | `endif | |
3986 | ||
3987 | always @(posedge l1clk) | |
3988 | begin | |
3989 | if (!siclk && !soclk) q_l <= ~d; | |
3990 | else q_l <= 1'bx; | |
3991 | end | |
3992 | `endif | |
3993 | ||
3994 | assign so = q_l; | |
3995 | ||
3996 | endmodule // dff | |
3997 | module cl_dp1_mux2_12x ( | |
3998 | in0, | |
3999 | in1, | |
4000 | sel0, | |
4001 | out | |
4002 | ); | |
4003 | input in0; | |
4004 | input in1; | |
4005 | input sel0; | |
4006 | output out; | |
4007 | ||
4008 | `ifdef LIB | |
4009 | reg out; | |
4010 | always @ ( sel0 or in0 or in1) | |
4011 | case ( sel0 ) | |
4012 | 1'b1: out = in0; | |
4013 | 1'b0: out = in1; | |
4014 | ||
4015 | default: out = 1'bx; | |
4016 | ||
4017 | endcase | |
4018 | `endif | |
4019 | ||
4020 | endmodule | |
4021 | ||
4022 | module cl_dp1_mux2_16x ( | |
4023 | in0, | |
4024 | in1, | |
4025 | sel0, | |
4026 | out | |
4027 | ); | |
4028 | input in0; | |
4029 | input in1; | |
4030 | input sel0; | |
4031 | output out; | |
4032 | ||
4033 | `ifdef LIB | |
4034 | reg out; | |
4035 | always @ ( sel0 or in0 or in1) | |
4036 | case ( sel0 ) | |
4037 | 1'b1: out = in0; | |
4038 | 1'b0: out = in1; | |
4039 | ||
4040 | default: out = 1'bx; | |
4041 | ||
4042 | endcase | |
4043 | `endif | |
4044 | ||
4045 | endmodule | |
4046 | ||
4047 | module cl_dp1_mux2_24x ( | |
4048 | in0, | |
4049 | in1, | |
4050 | sel0, | |
4051 | out | |
4052 | ); | |
4053 | input in0; | |
4054 | input in1; | |
4055 | input sel0; | |
4056 | output out; | |
4057 | ||
4058 | `ifdef LIB | |
4059 | reg out; | |
4060 | always @ ( sel0 or in0 or in1) | |
4061 | case ( sel0 ) | |
4062 | 1'b1: out = in0; | |
4063 | 1'b0: out = in1; | |
4064 | ||
4065 | default: out = 1'bx; | |
4066 | ||
4067 | endcase | |
4068 | `endif | |
4069 | ||
4070 | endmodule | |
4071 | ||
4072 | module cl_dp1_mux2_2x ( | |
4073 | in0, | |
4074 | in1, | |
4075 | sel0, | |
4076 | out | |
4077 | ); | |
4078 | input in0; | |
4079 | input in1; | |
4080 | input sel0; | |
4081 | output out; | |
4082 | ||
4083 | `ifdef LIB | |
4084 | reg out; | |
4085 | always @ ( sel0 or in0 or in1) | |
4086 | case ( sel0 ) | |
4087 | 1'b1: out = in0; | |
4088 | 1'b0: out = in1; | |
4089 | ||
4090 | default: out = 1'bx; | |
4091 | ||
4092 | endcase | |
4093 | `endif | |
4094 | ||
4095 | endmodule | |
4096 | ||
4097 | module cl_dp1_mux2_32x ( | |
4098 | in0, | |
4099 | in1, | |
4100 | sel0, | |
4101 | out | |
4102 | ); | |
4103 | input in0; | |
4104 | input in1; | |
4105 | input sel0; | |
4106 | output out; | |
4107 | ||
4108 | `ifdef LIB | |
4109 | reg out; | |
4110 | always @ ( sel0 or in0 or in1) | |
4111 | case ( sel0 ) | |
4112 | 1'b1: out = in0; | |
4113 | 1'b0: out = in1; | |
4114 | ||
4115 | default: out = 1'bx; | |
4116 | ||
4117 | endcase | |
4118 | `endif | |
4119 | ||
4120 | endmodule | |
4121 | ||
4122 | module cl_dp1_mux2_4x ( | |
4123 | in0, | |
4124 | in1, | |
4125 | sel0, | |
4126 | out | |
4127 | ); | |
4128 | input in0; | |
4129 | input in1; | |
4130 | input sel0; | |
4131 | output out; | |
4132 | ||
4133 | `ifdef LIB | |
4134 | reg out; | |
4135 | always @ ( sel0 or in0 or in1) | |
4136 | case ( sel0 ) | |
4137 | 1'b1: out = in0; | |
4138 | 1'b0: out = in1; | |
4139 | ||
4140 | default: out = 1'bx; | |
4141 | ||
4142 | endcase | |
4143 | `endif | |
4144 | ||
4145 | endmodule | |
4146 | ||
4147 | module cl_dp1_mux2_6x ( | |
4148 | in0, | |
4149 | in1, | |
4150 | sel0, | |
4151 | out | |
4152 | ); | |
4153 | input in0; | |
4154 | input in1; | |
4155 | input sel0; | |
4156 | output out; | |
4157 | ||
4158 | `ifdef LIB | |
4159 | reg out; | |
4160 | always @ ( sel0 or in0 or in1) | |
4161 | case ( sel0 ) | |
4162 | 1'b1: out = in0; | |
4163 | 1'b0: out = in1; | |
4164 | ||
4165 | default: out = 1'bx; | |
4166 | ||
4167 | endcase | |
4168 | `endif | |
4169 | ||
4170 | endmodule | |
4171 | ||
4172 | module cl_dp1_mux2_8x ( | |
4173 | in0, | |
4174 | in1, | |
4175 | sel0, | |
4176 | out | |
4177 | ); | |
4178 | input in0; | |
4179 | input in1; | |
4180 | input sel0; | |
4181 | output out; | |
4182 | ||
4183 | `ifdef LIB | |
4184 | reg out; | |
4185 | always @ ( sel0 or in0 or in1) | |
4186 | case ( sel0 ) | |
4187 | 1'b1: out = in0; | |
4188 | 1'b0: out = in1; | |
4189 | ||
4190 | default: out = 1'bx; | |
4191 | ||
4192 | endcase | |
4193 | `endif | |
4194 | ||
4195 | endmodule | |
4196 | ||
4197 | ||
4198 | ||
4199 | ||
4200 | module cl_dp1_mux3_12x( | |
4201 | in0, | |
4202 | in1, | |
4203 | in2, | |
4204 | sel0, | |
4205 | sel1, | |
4206 | sel2, | |
4207 | muxtst, | |
4208 | out | |
4209 | ); | |
4210 | ||
4211 | ||
4212 | ||
4213 | input in0; | |
4214 | input in1; | |
4215 | input in2; | |
4216 | input sel0; | |
4217 | input sel1; | |
4218 | input sel2; | |
4219 | input muxtst; | |
4220 | output out; | |
4221 | ||
4222 | `ifdef LIB | |
4223 | `ifdef muxohtest | |
4224 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4225 | `endif | |
4226 | ||
4227 | wire [3:0] sel= {muxtst,sel2,sel1,sel0}; | |
4228 | ||
4229 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4230 | (sel[2:0] == 3'b010) ? in1: | |
4231 | (sel[2:0] == 3'b100) ? in2: | |
4232 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4233 | 1'bx; | |
4234 | `endif | |
4235 | endmodule | |
4236 | ||
4237 | module cl_dp1_mux3_16x( | |
4238 | in0, | |
4239 | in1, | |
4240 | in2, | |
4241 | sel0, | |
4242 | sel1, | |
4243 | sel2, | |
4244 | muxtst, | |
4245 | out | |
4246 | ); | |
4247 | ||
4248 | ||
4249 | ||
4250 | input in0; | |
4251 | input in1; | |
4252 | input in2; | |
4253 | input sel0; | |
4254 | input sel1; | |
4255 | input sel2; | |
4256 | input muxtst; | |
4257 | output out; | |
4258 | ||
4259 | `ifdef LIB | |
4260 | ||
4261 | `ifdef muxohtest | |
4262 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4263 | `endif | |
4264 | ||
4265 | wire [3:0] sel = {muxtst,sel2,sel1,sel0}; | |
4266 | ||
4267 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4268 | (sel[2:0] == 3'b010) ? in1: | |
4269 | (sel[2:0] == 3'b100) ? in2: | |
4270 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4271 | 1'bx; | |
4272 | `endif | |
4273 | endmodule | |
4274 | ||
4275 | module cl_dp1_mux3_24x( | |
4276 | in0, | |
4277 | in1, | |
4278 | in2, | |
4279 | sel0, | |
4280 | sel1, | |
4281 | sel2, | |
4282 | muxtst, | |
4283 | out | |
4284 | ); | |
4285 | ||
4286 | ||
4287 | ||
4288 | input in0; | |
4289 | input in1; | |
4290 | input in2; | |
4291 | input sel0; | |
4292 | input sel1; | |
4293 | input sel2; | |
4294 | input muxtst; | |
4295 | output out; | |
4296 | ||
4297 | `ifdef LIB | |
4298 | `ifdef muxohtest | |
4299 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4300 | `endif | |
4301 | ||
4302 | wire [3:0] sel = {muxtst,sel2,sel1,sel0}; | |
4303 | ||
4304 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4305 | (sel[2:0] == 3'b010) ? in1: | |
4306 | (sel[2:0] == 3'b100) ? in2: | |
4307 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4308 | 1'bx; | |
4309 | `endif | |
4310 | endmodule | |
4311 | ||
4312 | module cl_dp1_mux3_2x( | |
4313 | in0, | |
4314 | in1, | |
4315 | in2, | |
4316 | sel0, | |
4317 | sel1, | |
4318 | sel2, | |
4319 | muxtst, | |
4320 | out | |
4321 | ); | |
4322 | ||
4323 | ||
4324 | ||
4325 | input in0; | |
4326 | input in1; | |
4327 | input in2; | |
4328 | input sel0; | |
4329 | input sel1; | |
4330 | input sel2; | |
4331 | input muxtst; | |
4332 | output out; | |
4333 | ||
4334 | `ifdef LIB | |
4335 | `ifdef muxohtest | |
4336 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4337 | `endif | |
4338 | ||
4339 | wire [3:0] sel= {muxtst,sel2,sel1,sel0}; | |
4340 | ||
4341 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4342 | (sel[2:0] == 3'b010) ? in1: | |
4343 | (sel[2:0] == 3'b100) ? in2: | |
4344 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4345 | 1'bx; | |
4346 | `endif | |
4347 | endmodule | |
4348 | ||
4349 | module cl_dp1_mux3_32x( | |
4350 | in0, | |
4351 | in1, | |
4352 | in2, | |
4353 | sel0, | |
4354 | sel1, | |
4355 | sel2, | |
4356 | muxtst, | |
4357 | out | |
4358 | ); | |
4359 | ||
4360 | ||
4361 | ||
4362 | input in0; | |
4363 | input in1; | |
4364 | input in2; | |
4365 | input sel0; | |
4366 | input sel1; | |
4367 | input sel2; | |
4368 | input muxtst; | |
4369 | output out; | |
4370 | ||
4371 | `ifdef LIB | |
4372 | ||
4373 | ||
4374 | wire [3:0] sel= {muxtst,sel2,sel1,sel0}; | |
4375 | ||
4376 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4377 | (sel[2:0] == 3'b010) ? in1: | |
4378 | (sel[2:0] == 3'b100) ? in2: | |
4379 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4380 | 1'bx; | |
4381 | `endif | |
4382 | endmodule | |
4383 | ||
4384 | module cl_dp1_mux3_4x( | |
4385 | in0, | |
4386 | in1, | |
4387 | in2, | |
4388 | sel0, | |
4389 | sel1, | |
4390 | sel2, | |
4391 | muxtst, | |
4392 | out | |
4393 | ); | |
4394 | ||
4395 | ||
4396 | ||
4397 | input in0; | |
4398 | input in1; | |
4399 | input in2; | |
4400 | input sel0; | |
4401 | input sel1; | |
4402 | input sel2; | |
4403 | input muxtst; | |
4404 | output out; | |
4405 | ||
4406 | `ifdef LIB | |
4407 | `ifdef muxohtest | |
4408 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4409 | `endif | |
4410 | ||
4411 | wire [3:0] sel= {muxtst,sel2,sel1,sel0}; | |
4412 | ||
4413 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4414 | (sel[2:0] == 3'b010) ? in1: | |
4415 | (sel[2:0] == 3'b100) ? in2: | |
4416 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4417 | 1'bx; | |
4418 | `endif | |
4419 | endmodule | |
4420 | ||
4421 | module cl_dp1_mux3_6x( | |
4422 | in0, | |
4423 | in1, | |
4424 | in2, | |
4425 | sel0, | |
4426 | sel1, | |
4427 | sel2, | |
4428 | muxtst, | |
4429 | out | |
4430 | ); | |
4431 | ||
4432 | ||
4433 | ||
4434 | input in0; | |
4435 | input in1; | |
4436 | input in2; | |
4437 | input sel0; | |
4438 | input sel1; | |
4439 | input sel2; | |
4440 | input muxtst; | |
4441 | output out; | |
4442 | ||
4443 | `ifdef LIB | |
4444 | ||
4445 | `ifdef muxohtest | |
4446 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4447 | `endif | |
4448 | ||
4449 | wire [3:0] sel= {muxtst,sel2,sel1,sel0}; | |
4450 | ||
4451 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4452 | (sel[2:0] == 3'b010) ? in1: | |
4453 | (sel[2:0] == 3'b100) ? in2: | |
4454 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4455 | 1'bx; | |
4456 | `endif | |
4457 | endmodule | |
4458 | ||
4459 | module cl_dp1_mux3_8x( | |
4460 | in0, | |
4461 | in1, | |
4462 | in2, | |
4463 | sel0, | |
4464 | sel1, | |
4465 | sel2, | |
4466 | muxtst, | |
4467 | out | |
4468 | ); | |
4469 | ||
4470 | ||
4471 | ||
4472 | input in0; | |
4473 | input in1; | |
4474 | input in2; | |
4475 | input sel0; | |
4476 | input sel1; | |
4477 | input sel2; | |
4478 | input muxtst; | |
4479 | output out; | |
4480 | ||
4481 | `ifdef LIB | |
4482 | ||
4483 | `ifdef muxohtest | |
4484 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4485 | `endif | |
4486 | ||
4487 | wire [3:0] sel = {muxtst,sel2,sel1,sel0}; | |
4488 | ||
4489 | assign out = (sel[2:0] == 3'b001) ? in0: | |
4490 | (sel[2:0] == 3'b010) ? in1: | |
4491 | (sel[2:0] == 3'b100) ? in2: | |
4492 | (sel[3:0] == 4'b0000) ? 1'b1: | |
4493 | 1'bx; | |
4494 | `endif | |
4495 | endmodule | |
4496 | ||
4497 | ||
4498 | module cl_dp1_mux4_12x( | |
4499 | in0, | |
4500 | in1, | |
4501 | in2, | |
4502 | in3, | |
4503 | sel0, | |
4504 | sel1, | |
4505 | sel2, | |
4506 | sel3, | |
4507 | muxtst, | |
4508 | out | |
4509 | ); | |
4510 | ||
4511 | ||
4512 | ||
4513 | input in0; | |
4514 | input in1; | |
4515 | input in2; | |
4516 | input in3; | |
4517 | input sel0; | |
4518 | input sel1; | |
4519 | input sel2; | |
4520 | input sel3; | |
4521 | input muxtst; | |
4522 | output out; | |
4523 | ||
4524 | ||
4525 | `ifdef LIB | |
4526 | ||
4527 | `ifdef muxohtest | |
4528 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2} | |
4529 | `endif | |
4530 | ||
4531 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4532 | ||
4533 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4534 | (sel[3:0] == 4'b0010) ? in1: | |
4535 | (sel[3:0] == 4'b0100) ? in2: | |
4536 | (sel[3:0] == 4'b1000) ? in3: | |
4537 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4538 | 1'bx; | |
4539 | `endif | |
4540 | endmodule | |
4541 | ||
4542 | module cl_dp1_mux4_16x( | |
4543 | in0, | |
4544 | in1, | |
4545 | in2, | |
4546 | in3, | |
4547 | sel0, | |
4548 | sel1, | |
4549 | sel2, | |
4550 | sel3, | |
4551 | muxtst, | |
4552 | out | |
4553 | ); | |
4554 | ||
4555 | ||
4556 | ||
4557 | input in0; | |
4558 | input in1; | |
4559 | input in2; | |
4560 | input in3; | |
4561 | input sel0; | |
4562 | input sel1; | |
4563 | input sel2; | |
4564 | input sel3; | |
4565 | input muxtst; | |
4566 | output out; | |
4567 | ||
4568 | ||
4569 | `ifdef LIB | |
4570 | `ifdef MUXOHTEST | |
4571 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4572 | `endif | |
4573 | ||
4574 | ||
4575 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4576 | ||
4577 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4578 | (sel[3:0] == 4'b0010) ? in1: | |
4579 | (sel[3:0] == 4'b0100) ? in2: | |
4580 | (sel[3:0] == 4'b1000) ? in3: | |
4581 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4582 | 1'bx; | |
4583 | `endif | |
4584 | endmodule | |
4585 | ||
4586 | module cl_dp1_mux4_24x( | |
4587 | in0, | |
4588 | in1, | |
4589 | in2, | |
4590 | in3, | |
4591 | sel0, | |
4592 | sel1, | |
4593 | sel2, | |
4594 | sel3, | |
4595 | muxtst, | |
4596 | out | |
4597 | ); | |
4598 | ||
4599 | ||
4600 | ||
4601 | input in0; | |
4602 | input in1; | |
4603 | input in2; | |
4604 | input in3; | |
4605 | input sel0; | |
4606 | input sel1; | |
4607 | input sel2; | |
4608 | input sel3; | |
4609 | input muxtst; | |
4610 | output out; | |
4611 | ||
4612 | ||
4613 | `ifdef LIB | |
4614 | `ifdef MUXOHTEST | |
4615 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4616 | `endif | |
4617 | ||
4618 | ||
4619 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4620 | ||
4621 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4622 | (sel[3:0] == 4'b0010) ? in1: | |
4623 | (sel[3:0] == 4'b0100) ? in2: | |
4624 | (sel[3:0] == 4'b1000) ? in3: | |
4625 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4626 | 1'bx; | |
4627 | `endif | |
4628 | endmodule | |
4629 | ||
4630 | module cl_dp1_mux4_2x( | |
4631 | in0, | |
4632 | in1, | |
4633 | in2, | |
4634 | in3, | |
4635 | sel0, | |
4636 | sel1, | |
4637 | sel2, | |
4638 | sel3, | |
4639 | muxtst, | |
4640 | out | |
4641 | ); | |
4642 | ||
4643 | ||
4644 | ||
4645 | input in0; | |
4646 | input in1; | |
4647 | input in2; | |
4648 | input in3; | |
4649 | input sel0; | |
4650 | input sel1; | |
4651 | input sel2; | |
4652 | input sel3; | |
4653 | input muxtst; | |
4654 | output out; | |
4655 | ||
4656 | ||
4657 | `ifdef LIB | |
4658 | `ifdef MUXOHTEST | |
4659 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4660 | `endif | |
4661 | ||
4662 | ||
4663 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4664 | ||
4665 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4666 | (sel[3:0] == 4'b0010) ? in1: | |
4667 | (sel[3:0] == 4'b0100) ? in2: | |
4668 | (sel[3:0] == 4'b1000) ? in3: | |
4669 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4670 | 1'bx; | |
4671 | `endif | |
4672 | endmodule | |
4673 | ||
4674 | module cl_dp1_mux4_32x( | |
4675 | in0, | |
4676 | in1, | |
4677 | in2, | |
4678 | in3, | |
4679 | sel0, | |
4680 | sel1, | |
4681 | sel2, | |
4682 | sel3, | |
4683 | muxtst, | |
4684 | out | |
4685 | ); | |
4686 | ||
4687 | ||
4688 | ||
4689 | input in0; | |
4690 | input in1; | |
4691 | input in2; | |
4692 | input in3; | |
4693 | input sel0; | |
4694 | input sel1; | |
4695 | input sel2; | |
4696 | input sel3; | |
4697 | input muxtst; | |
4698 | output out; | |
4699 | ||
4700 | ||
4701 | `ifdef LIB | |
4702 | `ifdef MUXOHTEST | |
4703 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4704 | `endif | |
4705 | ||
4706 | ||
4707 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4708 | ||
4709 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4710 | (sel[3:0] == 4'b0010) ? in1: | |
4711 | (sel[3:0] == 4'b0100) ? in2: | |
4712 | (sel[3:0] == 4'b1000) ? in3: | |
4713 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4714 | 1'bx; | |
4715 | `endif | |
4716 | endmodule | |
4717 | ||
4718 | module cl_dp1_mux4_4x( | |
4719 | in0, | |
4720 | in1, | |
4721 | in2, | |
4722 | in3, | |
4723 | sel0, | |
4724 | sel1, | |
4725 | sel2, | |
4726 | sel3, | |
4727 | muxtst, | |
4728 | out | |
4729 | ); | |
4730 | ||
4731 | ||
4732 | ||
4733 | input in0; | |
4734 | input in1; | |
4735 | input in2; | |
4736 | input in3; | |
4737 | input sel0; | |
4738 | input sel1; | |
4739 | input sel2; | |
4740 | input sel3; | |
4741 | input muxtst; | |
4742 | output out; | |
4743 | ||
4744 | ||
4745 | `ifdef LIB | |
4746 | `ifdef MUXOHTEST | |
4747 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4748 | `endif | |
4749 | ||
4750 | ||
4751 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4752 | ||
4753 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4754 | (sel[3:0] == 4'b0010) ? in1: | |
4755 | (sel[3:0] == 4'b0100) ? in2: | |
4756 | (sel[3:0] == 4'b1000) ? in3: | |
4757 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4758 | 1'bx; | |
4759 | `endif | |
4760 | endmodule | |
4761 | ||
4762 | module cl_dp1_mux4_6x( | |
4763 | in0, | |
4764 | in1, | |
4765 | in2, | |
4766 | in3, | |
4767 | sel0, | |
4768 | sel1, | |
4769 | sel2, | |
4770 | sel3, | |
4771 | muxtst, | |
4772 | out | |
4773 | ); | |
4774 | ||
4775 | ||
4776 | ||
4777 | input in0; | |
4778 | input in1; | |
4779 | input in2; | |
4780 | input in3; | |
4781 | input sel0; | |
4782 | input sel1; | |
4783 | input sel2; | |
4784 | input sel3; | |
4785 | input muxtst; | |
4786 | output out; | |
4787 | ||
4788 | ||
4789 | `ifdef LIB | |
4790 | `ifdef MUXOHTEST | |
4791 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4792 | `endif | |
4793 | ||
4794 | ||
4795 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4796 | ||
4797 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4798 | (sel[3:0] == 4'b0010) ? in1: | |
4799 | (sel[3:0] == 4'b0100) ? in2: | |
4800 | (sel[3:0] == 4'b1000) ? in3: | |
4801 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4802 | 1'bx; | |
4803 | `endif | |
4804 | endmodule | |
4805 | ||
4806 | module cl_dp1_mux4_8x( | |
4807 | in0, | |
4808 | in1, | |
4809 | in2, | |
4810 | in3, | |
4811 | sel0, | |
4812 | sel1, | |
4813 | sel2, | |
4814 | sel3, | |
4815 | muxtst, | |
4816 | out | |
4817 | ); | |
4818 | ||
4819 | ||
4820 | ||
4821 | input in0; | |
4822 | input in1; | |
4823 | input in2; | |
4824 | input in3; | |
4825 | input sel0; | |
4826 | input sel1; | |
4827 | input sel2; | |
4828 | input sel3; | |
4829 | input muxtst; | |
4830 | output out; | |
4831 | ||
4832 | ||
4833 | `ifdef LIB | |
4834 | ||
4835 | `ifdef MUXOHTEST | |
4836 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3} | |
4837 | `endif | |
4838 | ||
4839 | wire [4:0] sel = {muxtst,sel3,sel2,sel1,sel0}; | |
4840 | ||
4841 | assign out = (sel[3:0] == 4'b0001) ? in0: | |
4842 | (sel[3:0] == 4'b0010) ? in1: | |
4843 | (sel[3:0] == 4'b0100) ? in2: | |
4844 | (sel[3:0] == 4'b1000) ? in3: | |
4845 | (sel[4:0] == 5'b00000) ? 1'b1: | |
4846 | 1'bx; | |
4847 | `endif | |
4848 | endmodule | |
4849 | ||
4850 | ||
4851 | ||
4852 | module cl_dp1_mux5_12x( | |
4853 | in0, | |
4854 | in1, | |
4855 | in2, | |
4856 | in3, | |
4857 | in4, | |
4858 | sel0, | |
4859 | sel1, | |
4860 | sel2, | |
4861 | sel3, | |
4862 | sel4, | |
4863 | muxtst, | |
4864 | out | |
4865 | ); | |
4866 | ||
4867 | ||
4868 | ||
4869 | input in0; | |
4870 | input in1; | |
4871 | input in2; | |
4872 | input in3; | |
4873 | input in4; | |
4874 | input sel0; | |
4875 | input sel1; | |
4876 | input sel2; | |
4877 | input sel3; | |
4878 | input sel4; | |
4879 | input muxtst; | |
4880 | output out; | |
4881 | `ifdef LIB | |
4882 | `ifdef MUXOHTEST | |
4883 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
4884 | `endif | |
4885 | ||
4886 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
4887 | ||
4888 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
4889 | (sel[4:0] == 5'b00010) ? in1: | |
4890 | (sel[4:0] == 5'b00100) ? in2: | |
4891 | (sel[4:0] == 5'b01000) ? in3: | |
4892 | (sel[4:0] == 5'b10000) ? in4: | |
4893 | (sel[5:0] == 6'b000000) ? 1'b1: | |
4894 | 1'bx; | |
4895 | `endif | |
4896 | endmodule | |
4897 | ||
4898 | module cl_dp1_mux5_16x( | |
4899 | in0, | |
4900 | in1, | |
4901 | in2, | |
4902 | in3, | |
4903 | in4, | |
4904 | sel0, | |
4905 | sel1, | |
4906 | sel2, | |
4907 | sel3, | |
4908 | sel4, | |
4909 | muxtst, | |
4910 | out | |
4911 | ); | |
4912 | ||
4913 | ||
4914 | ||
4915 | input in0; | |
4916 | input in1; | |
4917 | input in2; | |
4918 | input in3; | |
4919 | input in4; | |
4920 | input sel0; | |
4921 | input sel1; | |
4922 | input sel2; | |
4923 | input sel3; | |
4924 | input sel4; | |
4925 | input muxtst; | |
4926 | output out; | |
4927 | `ifdef LIB | |
4928 | `ifdef MUXOHTEST | |
4929 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
4930 | `endif | |
4931 | ||
4932 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
4933 | ||
4934 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
4935 | (sel[4:0] == 5'b00010) ? in1: | |
4936 | (sel[4:0] == 5'b00100) ? in2: | |
4937 | (sel[4:0] == 5'b01000) ? in3: | |
4938 | (sel[4:0] == 5'b10000) ? in4: | |
4939 | (sel[5:0] == 6'b000000) ? 1'b1: | |
4940 | 1'bx; | |
4941 | `endif | |
4942 | endmodule | |
4943 | ||
4944 | module cl_dp1_mux5_24x( | |
4945 | in0, | |
4946 | in1, | |
4947 | in2, | |
4948 | in3, | |
4949 | in4, | |
4950 | sel0, | |
4951 | sel1, | |
4952 | sel2, | |
4953 | sel3, | |
4954 | sel4, | |
4955 | muxtst, | |
4956 | out | |
4957 | ); | |
4958 | ||
4959 | ||
4960 | ||
4961 | input in0; | |
4962 | input in1; | |
4963 | input in2; | |
4964 | input in3; | |
4965 | input in4; | |
4966 | input sel0; | |
4967 | input sel1; | |
4968 | input sel2; | |
4969 | input sel3; | |
4970 | input sel4; | |
4971 | input muxtst; | |
4972 | output out; | |
4973 | `ifdef LIB | |
4974 | `ifdef MUXOHTEST | |
4975 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
4976 | `endif | |
4977 | ||
4978 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
4979 | ||
4980 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
4981 | (sel[4:0] == 5'b00010) ? in1: | |
4982 | (sel[4:0] == 5'b00100) ? in2: | |
4983 | (sel[4:0] == 5'b01000) ? in3: | |
4984 | (sel[4:0] == 5'b10000) ? in4: | |
4985 | (sel[5:0] == 6'b000000) ? 1'b1: | |
4986 | 1'bx; | |
4987 | `endif | |
4988 | endmodule | |
4989 | ||
4990 | module cl_dp1_mux5_2x( | |
4991 | in0, | |
4992 | in1, | |
4993 | in2, | |
4994 | in3, | |
4995 | in4, | |
4996 | sel0, | |
4997 | sel1, | |
4998 | sel2, | |
4999 | sel3, | |
5000 | sel4, | |
5001 | muxtst, | |
5002 | out | |
5003 | ); | |
5004 | ||
5005 | ||
5006 | ||
5007 | input in0; | |
5008 | input in1; | |
5009 | input in2; | |
5010 | input in3; | |
5011 | input in4; | |
5012 | input sel0; | |
5013 | input sel1; | |
5014 | input sel2; | |
5015 | input sel3; | |
5016 | input sel4; | |
5017 | input muxtst; | |
5018 | output out; | |
5019 | `ifdef LIB | |
5020 | `ifdef MUXOHTEST | |
5021 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
5022 | `endif | |
5023 | ||
5024 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
5025 | ||
5026 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
5027 | (sel[4:0] == 5'b00010) ? in1: | |
5028 | (sel[4:0] == 5'b00100) ? in2: | |
5029 | (sel[4:0] == 5'b01000) ? in3: | |
5030 | (sel[4:0] == 5'b10000) ? in4: | |
5031 | (sel[5:0] == 6'b000000) ? 1'b1: | |
5032 | 1'bx; | |
5033 | `endif | |
5034 | endmodule | |
5035 | ||
5036 | module cl_dp1_mux5_32x( | |
5037 | in0, | |
5038 | in1, | |
5039 | in2, | |
5040 | in3, | |
5041 | in4, | |
5042 | sel0, | |
5043 | sel1, | |
5044 | sel2, | |
5045 | sel3, | |
5046 | sel4, | |
5047 | muxtst, | |
5048 | out | |
5049 | ); | |
5050 | ||
5051 | ||
5052 | ||
5053 | input in0; | |
5054 | input in1; | |
5055 | input in2; | |
5056 | input in3; | |
5057 | input in4; | |
5058 | input sel0; | |
5059 | input sel1; | |
5060 | input sel2; | |
5061 | input sel3; | |
5062 | input sel4; | |
5063 | input muxtst; | |
5064 | output out; | |
5065 | `ifdef LIB | |
5066 | `ifdef MUXOHTEST | |
5067 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
5068 | `endif | |
5069 | ||
5070 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
5071 | ||
5072 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
5073 | (sel[4:0] == 5'b00010) ? in1: | |
5074 | (sel[4:0] == 5'b00100) ? in2: | |
5075 | (sel[4:0] == 5'b01000) ? in3: | |
5076 | (sel[4:0] == 5'b10000) ? in4: | |
5077 | (sel[5:0] == 6'b000000) ? 1'b1: | |
5078 | 1'bx; | |
5079 | `endif | |
5080 | endmodule | |
5081 | ||
5082 | module cl_dp1_mux5_4x( | |
5083 | in0, | |
5084 | in1, | |
5085 | in2, | |
5086 | in3, | |
5087 | in4, | |
5088 | sel0, | |
5089 | sel1, | |
5090 | sel2, | |
5091 | sel3, | |
5092 | sel4, | |
5093 | muxtst, | |
5094 | out | |
5095 | ); | |
5096 | ||
5097 | ||
5098 | ||
5099 | input in0; | |
5100 | input in1; | |
5101 | input in2; | |
5102 | input in3; | |
5103 | input in4; | |
5104 | input sel0; | |
5105 | input sel1; | |
5106 | input sel2; | |
5107 | input sel3; | |
5108 | input sel4; | |
5109 | input muxtst; | |
5110 | output out; | |
5111 | `ifdef LIB | |
5112 | `ifdef MUXOHTEST | |
5113 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
5114 | `endif | |
5115 | ||
5116 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
5117 | ||
5118 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
5119 | (sel[4:0] == 5'b00010) ? in1: | |
5120 | (sel[4:0] == 5'b00100) ? in2: | |
5121 | (sel[4:0] == 5'b01000) ? in3: | |
5122 | (sel[4:0] == 5'b10000) ? in4: | |
5123 | (sel[5:0] == 6'b000000) ? 1'b1: | |
5124 | 1'bx; | |
5125 | `endif | |
5126 | endmodule | |
5127 | ||
5128 | module cl_dp1_mux5_6x( | |
5129 | in0, | |
5130 | in1, | |
5131 | in2, | |
5132 | in3, | |
5133 | in4, | |
5134 | sel0, | |
5135 | sel1, | |
5136 | sel2, | |
5137 | sel3, | |
5138 | sel4, | |
5139 | muxtst, | |
5140 | out | |
5141 | ); | |
5142 | ||
5143 | ||
5144 | ||
5145 | input in0; | |
5146 | input in1; | |
5147 | input in2; | |
5148 | input in3; | |
5149 | input in4; | |
5150 | input sel0; | |
5151 | input sel1; | |
5152 | input sel2; | |
5153 | input sel3; | |
5154 | input sel4; | |
5155 | input muxtst; | |
5156 | output out; | |
5157 | `ifdef LIB | |
5158 | `ifdef MUXOHTEST | |
5159 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
5160 | `endif | |
5161 | ||
5162 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
5163 | ||
5164 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
5165 | (sel[4:0] == 5'b00010) ? in1: | |
5166 | (sel[4:0] == 5'b00100) ? in2: | |
5167 | (sel[4:0] == 5'b01000) ? in3: | |
5168 | (sel[4:0] == 5'b10000) ? in4: | |
5169 | (sel[5:0] == 6'b000000) ? 1'b1: | |
5170 | 1'bx; | |
5171 | `endif | |
5172 | endmodule | |
5173 | ||
5174 | module cl_dp1_mux5_8x( | |
5175 | in0, | |
5176 | in1, | |
5177 | in2, | |
5178 | in3, | |
5179 | in4, | |
5180 | sel0, | |
5181 | sel1, | |
5182 | sel2, | |
5183 | sel3, | |
5184 | sel4, | |
5185 | muxtst, | |
5186 | out | |
5187 | ); | |
5188 | ||
5189 | ||
5190 | ||
5191 | input in0; | |
5192 | input in1; | |
5193 | input in2; | |
5194 | input in3; | |
5195 | input in4; | |
5196 | input sel0; | |
5197 | input sel1; | |
5198 | input sel2; | |
5199 | input sel3; | |
5200 | input sel4; | |
5201 | input muxtst; | |
5202 | output out; | |
5203 | `ifdef LIB | |
5204 | `ifdef MUXOHTEST | |
5205 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4} | |
5206 | `endif | |
5207 | ||
5208 | wire [5:0] sel = {muxtst,sel4,sel3,sel2,sel1,sel0}; | |
5209 | ||
5210 | assign out = (sel[4:0] == 5'b00001) ? in0: | |
5211 | (sel[4:0] == 5'b00010) ? in1: | |
5212 | (sel[4:0] == 5'b00100) ? in2: | |
5213 | (sel[4:0] == 5'b01000) ? in3: | |
5214 | (sel[4:0] == 5'b10000) ? in4: | |
5215 | (sel[5:0] == 6'b000000) ? 1'b1: | |
5216 | 1'bx; | |
5217 | `endif | |
5218 | endmodule | |
5219 | ||
5220 | module cl_dp1_mux6_12x( | |
5221 | in0, | |
5222 | in1, | |
5223 | in2, | |
5224 | in3, | |
5225 | in4, | |
5226 | in5, | |
5227 | sel0, | |
5228 | sel1, | |
5229 | sel2, | |
5230 | sel3, | |
5231 | sel4, | |
5232 | sel5, | |
5233 | muxtst, | |
5234 | out | |
5235 | ); | |
5236 | ||
5237 | ||
5238 | ||
5239 | output out; | |
5240 | ||
5241 | input in0; | |
5242 | input in1; | |
5243 | input in2; | |
5244 | input in3; | |
5245 | input in4; | |
5246 | input in5; | |
5247 | input sel0; | |
5248 | input sel1; | |
5249 | input sel2; | |
5250 | input sel3; | |
5251 | input sel4; | |
5252 | input sel5; | |
5253 | input muxtst; | |
5254 | `ifdef LIB | |
5255 | `ifdef MUXOHTEST | |
5256 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5257 | `endif | |
5258 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5259 | ||
5260 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5261 | (sel[5:0] == 6'b000010) ? in1: | |
5262 | (sel[5:0] == 6'b000100) ? in2: | |
5263 | (sel[5:0] == 6'b001000) ? in3: | |
5264 | (sel[5:0] == 6'b010000) ? in4: | |
5265 | (sel[5:0] == 6'b100000) ? in5: | |
5266 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5267 | 1'bx; | |
5268 | `endif | |
5269 | endmodule | |
5270 | ||
5271 | module cl_dp1_mux6_16x( | |
5272 | in0, | |
5273 | in1, | |
5274 | in2, | |
5275 | in3, | |
5276 | in4, | |
5277 | in5, | |
5278 | sel0, | |
5279 | sel1, | |
5280 | sel2, | |
5281 | sel3, | |
5282 | sel4, | |
5283 | sel5, | |
5284 | muxtst, | |
5285 | out | |
5286 | ); | |
5287 | ||
5288 | ||
5289 | ||
5290 | output out; | |
5291 | ||
5292 | input in0; | |
5293 | input in1; | |
5294 | input in2; | |
5295 | input in3; | |
5296 | input in4; | |
5297 | input in5; | |
5298 | input sel0; | |
5299 | input sel1; | |
5300 | input sel2; | |
5301 | input sel3; | |
5302 | input sel4; | |
5303 | input sel5; | |
5304 | input muxtst; | |
5305 | `ifdef LIB | |
5306 | `ifdef MUXOHTEST | |
5307 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5308 | `endif | |
5309 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5310 | ||
5311 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5312 | (sel[5:0] == 6'b000010) ? in1: | |
5313 | (sel[5:0] == 6'b000100) ? in2: | |
5314 | (sel[5:0] == 6'b001000) ? in3: | |
5315 | (sel[5:0] == 6'b010000) ? in4: | |
5316 | (sel[5:0] == 6'b100000) ? in5: | |
5317 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5318 | 1'bx; | |
5319 | `endif | |
5320 | endmodule | |
5321 | ||
5322 | module cl_dp1_mux6_24x( | |
5323 | in0, | |
5324 | in1, | |
5325 | in2, | |
5326 | in3, | |
5327 | in4, | |
5328 | in5, | |
5329 | sel0, | |
5330 | sel1, | |
5331 | sel2, | |
5332 | sel3, | |
5333 | sel4, | |
5334 | sel5, | |
5335 | muxtst, | |
5336 | out | |
5337 | ); | |
5338 | ||
5339 | ||
5340 | ||
5341 | output out; | |
5342 | ||
5343 | input in0; | |
5344 | input in1; | |
5345 | input in2; | |
5346 | input in3; | |
5347 | input in4; | |
5348 | input in5; | |
5349 | input sel0; | |
5350 | input sel1; | |
5351 | input sel2; | |
5352 | input sel3; | |
5353 | input sel4; | |
5354 | input sel5; | |
5355 | input muxtst; | |
5356 | `ifdef LIB | |
5357 | `ifdef MUXOHTEST | |
5358 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5359 | `endif | |
5360 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5361 | ||
5362 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5363 | (sel[5:0] == 6'b000010) ? in1: | |
5364 | (sel[5:0] == 6'b000100) ? in2: | |
5365 | (sel[5:0] == 6'b001000) ? in3: | |
5366 | (sel[5:0] == 6'b010000) ? in4: | |
5367 | (sel[5:0] == 6'b100000) ? in5: | |
5368 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5369 | 1'bx; | |
5370 | `endif | |
5371 | endmodule | |
5372 | ||
5373 | module cl_dp1_mux6_2x( | |
5374 | in0, | |
5375 | in1, | |
5376 | in2, | |
5377 | in3, | |
5378 | in4, | |
5379 | in5, | |
5380 | sel0, | |
5381 | sel1, | |
5382 | sel2, | |
5383 | sel3, | |
5384 | sel4, | |
5385 | sel5, | |
5386 | muxtst, | |
5387 | out | |
5388 | ); | |
5389 | ||
5390 | ||
5391 | ||
5392 | output out; | |
5393 | ||
5394 | input in0; | |
5395 | input in1; | |
5396 | input in2; | |
5397 | input in3; | |
5398 | input in4; | |
5399 | input in5; | |
5400 | input sel0; | |
5401 | input sel1; | |
5402 | input sel2; | |
5403 | input sel3; | |
5404 | input sel4; | |
5405 | input sel5; | |
5406 | input muxtst; | |
5407 | `ifdef LIB | |
5408 | `ifdef MUXOHTEST | |
5409 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5410 | `endif | |
5411 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5412 | ||
5413 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5414 | (sel[5:0] == 6'b000010) ? in1: | |
5415 | (sel[5:0] == 6'b000100) ? in2: | |
5416 | (sel[5:0] == 6'b001000) ? in3: | |
5417 | (sel[5:0] == 6'b010000) ? in4: | |
5418 | (sel[5:0] == 6'b100000) ? in5: | |
5419 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5420 | 1'bx; | |
5421 | `endif | |
5422 | endmodule | |
5423 | ||
5424 | module cl_dp1_mux6_32x( | |
5425 | in0, | |
5426 | in1, | |
5427 | in2, | |
5428 | in3, | |
5429 | in4, | |
5430 | in5, | |
5431 | sel0, | |
5432 | sel1, | |
5433 | sel2, | |
5434 | sel3, | |
5435 | sel4, | |
5436 | sel5, | |
5437 | muxtst, | |
5438 | out | |
5439 | ); | |
5440 | ||
5441 | ||
5442 | ||
5443 | output out; | |
5444 | ||
5445 | input in0; | |
5446 | input in1; | |
5447 | input in2; | |
5448 | input in3; | |
5449 | input in4; | |
5450 | input in5; | |
5451 | input sel0; | |
5452 | input sel1; | |
5453 | input sel2; | |
5454 | input sel3; | |
5455 | input sel4; | |
5456 | input sel5; | |
5457 | input muxtst; | |
5458 | `ifdef LIB | |
5459 | `ifdef MUXOHTEST | |
5460 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5461 | `endif | |
5462 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5463 | ||
5464 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5465 | (sel[5:0] == 6'b000010) ? in1: | |
5466 | (sel[5:0] == 6'b000100) ? in2: | |
5467 | (sel[5:0] == 6'b001000) ? in3: | |
5468 | (sel[5:0] == 6'b010000) ? in4: | |
5469 | (sel[5:0] == 6'b100000) ? in5: | |
5470 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5471 | 1'bx; | |
5472 | `endif | |
5473 | endmodule | |
5474 | ||
5475 | module cl_dp1_mux6_4x( | |
5476 | in0, | |
5477 | in1, | |
5478 | in2, | |
5479 | in3, | |
5480 | in4, | |
5481 | in5, | |
5482 | sel0, | |
5483 | sel1, | |
5484 | sel2, | |
5485 | sel3, | |
5486 | sel4, | |
5487 | sel5, | |
5488 | muxtst, | |
5489 | out | |
5490 | ); | |
5491 | ||
5492 | ||
5493 | ||
5494 | output out; | |
5495 | ||
5496 | input in0; | |
5497 | input in1; | |
5498 | input in2; | |
5499 | input in3; | |
5500 | input in4; | |
5501 | input in5; | |
5502 | input sel0; | |
5503 | input sel1; | |
5504 | input sel2; | |
5505 | input sel3; | |
5506 | input sel4; | |
5507 | input sel5; | |
5508 | input muxtst; | |
5509 | `ifdef LIB | |
5510 | `ifdef MUXOHTEST | |
5511 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5512 | `endif | |
5513 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5514 | ||
5515 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5516 | (sel[5:0] == 6'b000010) ? in1: | |
5517 | (sel[5:0] == 6'b000100) ? in2: | |
5518 | (sel[5:0] == 6'b001000) ? in3: | |
5519 | (sel[5:0] == 6'b010000) ? in4: | |
5520 | (sel[5:0] == 6'b100000) ? in5: | |
5521 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5522 | 1'bx; | |
5523 | `endif | |
5524 | endmodule | |
5525 | ||
5526 | module cl_dp1_mux6_6x( | |
5527 | in0, | |
5528 | in1, | |
5529 | in2, | |
5530 | in3, | |
5531 | in4, | |
5532 | in5, | |
5533 | sel0, | |
5534 | sel1, | |
5535 | sel2, | |
5536 | sel3, | |
5537 | sel4, | |
5538 | sel5, | |
5539 | muxtst, | |
5540 | out | |
5541 | ); | |
5542 | ||
5543 | `ifdef MUXOHTEST | |
5544 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5545 | `endif | |
5546 | ||
5547 | output out; | |
5548 | ||
5549 | input in0; | |
5550 | input in1; | |
5551 | input in2; | |
5552 | input in3; | |
5553 | input in4; | |
5554 | input in5; | |
5555 | input sel0; | |
5556 | input sel1; | |
5557 | input sel2; | |
5558 | input sel3; | |
5559 | input sel4; | |
5560 | input sel5; | |
5561 | input muxtst; | |
5562 | `ifdef LIB | |
5563 | ||
5564 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5565 | ||
5566 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5567 | (sel[5:0] == 6'b000010) ? in1: | |
5568 | (sel[5:0] == 6'b000100) ? in2: | |
5569 | (sel[5:0] == 6'b001000) ? in3: | |
5570 | (sel[5:0] == 6'b010000) ? in4: | |
5571 | (sel[5:0] == 6'b100000) ? in5: | |
5572 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5573 | 1'bx; | |
5574 | `endif | |
5575 | endmodule | |
5576 | ||
5577 | module cl_dp1_mux6_8x( | |
5578 | in0, | |
5579 | in1, | |
5580 | in2, | |
5581 | in3, | |
5582 | in4, | |
5583 | in5, | |
5584 | sel0, | |
5585 | sel1, | |
5586 | sel2, | |
5587 | sel3, | |
5588 | sel4, | |
5589 | sel5, | |
5590 | muxtst, | |
5591 | out | |
5592 | ); | |
5593 | ||
5594 | `ifdef MUXOHTEST | |
5595 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5} | |
5596 | `endif | |
5597 | ||
5598 | output out; | |
5599 | ||
5600 | input in0; | |
5601 | input in1; | |
5602 | input in2; | |
5603 | input in3; | |
5604 | input in4; | |
5605 | input in5; | |
5606 | input sel0; | |
5607 | input sel1; | |
5608 | input sel2; | |
5609 | input sel3; | |
5610 | input sel4; | |
5611 | input sel5; | |
5612 | input muxtst; | |
5613 | `ifdef LIB | |
5614 | ||
5615 | wire [6:0] sel = {muxtst,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5616 | ||
5617 | assign out = (sel[5:0] == 6'b000001) ? in0: | |
5618 | (sel[5:0] == 6'b000010) ? in1: | |
5619 | (sel[5:0] == 6'b000100) ? in2: | |
5620 | (sel[5:0] == 6'b001000) ? in3: | |
5621 | (sel[5:0] == 6'b010000) ? in4: | |
5622 | (sel[5:0] == 6'b100000) ? in5: | |
5623 | (sel[6:0] == 7'b0000000) ? 1'b1: | |
5624 | 1'bx; | |
5625 | `endif | |
5626 | endmodule | |
5627 | ||
5628 | ||
5629 | module cl_dp1_mux7_12x( | |
5630 | in0, | |
5631 | in1, | |
5632 | in2, | |
5633 | in3, | |
5634 | in4, | |
5635 | in5, | |
5636 | in6, | |
5637 | sel0, | |
5638 | sel1, | |
5639 | sel2, | |
5640 | sel3, | |
5641 | sel4, | |
5642 | sel5, | |
5643 | sel6, | |
5644 | muxtst, | |
5645 | out | |
5646 | ); | |
5647 | ||
5648 | ||
5649 | output out; | |
5650 | ||
5651 | input in0; | |
5652 | input in1; | |
5653 | input in2; | |
5654 | input in3; | |
5655 | input in4; | |
5656 | input in5; | |
5657 | input in6; | |
5658 | input sel0; | |
5659 | input sel1; | |
5660 | input sel2; | |
5661 | input sel3; | |
5662 | input sel4; | |
5663 | input sel5; | |
5664 | input sel6; | |
5665 | input muxtst; | |
5666 | ||
5667 | `ifdef LIB | |
5668 | `ifdef MUXOHTEST | |
5669 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5670 | `endif | |
5671 | ||
5672 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5673 | ||
5674 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5675 | (sel[6:0] == 7'b0000010) ? in1: | |
5676 | (sel[6:0] == 7'b0000100) ? in2: | |
5677 | (sel[6:0] == 7'b0001000) ? in3: | |
5678 | (sel[6:0] == 7'b0010000) ? in4: | |
5679 | (sel[6:0] == 7'b0100000) ? in5: | |
5680 | (sel[6:0] == 7'b1000000) ? in6: | |
5681 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5682 | 1'bx; | |
5683 | `endif | |
5684 | endmodule | |
5685 | ||
5686 | module cl_dp1_mux7_16x( | |
5687 | in0, | |
5688 | in1, | |
5689 | in2, | |
5690 | in3, | |
5691 | in4, | |
5692 | in5, | |
5693 | in6, | |
5694 | sel0, | |
5695 | sel1, | |
5696 | sel2, | |
5697 | sel3, | |
5698 | sel4, | |
5699 | sel5, | |
5700 | sel6, | |
5701 | muxtst, | |
5702 | out | |
5703 | ); | |
5704 | ||
5705 | ||
5706 | output out; | |
5707 | ||
5708 | input in0; | |
5709 | input in1; | |
5710 | input in2; | |
5711 | input in3; | |
5712 | input in4; | |
5713 | input in5; | |
5714 | input in6; | |
5715 | input sel0; | |
5716 | input sel1; | |
5717 | input sel2; | |
5718 | input sel3; | |
5719 | input sel4; | |
5720 | input sel5; | |
5721 | input sel6; | |
5722 | input muxtst; | |
5723 | ||
5724 | `ifdef LIB | |
5725 | ||
5726 | `ifdef MUXOHTEST | |
5727 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5728 | `endif | |
5729 | ||
5730 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5731 | ||
5732 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5733 | (sel[6:0] == 7'b0000010) ? in1: | |
5734 | (sel[6:0] == 7'b0000100) ? in2: | |
5735 | (sel[6:0] == 7'b0001000) ? in3: | |
5736 | (sel[6:0] == 7'b0010000) ? in4: | |
5737 | (sel[6:0] == 7'b0100000) ? in5: | |
5738 | (sel[6:0] == 7'b1000000) ? in6: | |
5739 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5740 | 1'bx; | |
5741 | `endif | |
5742 | endmodule | |
5743 | ||
5744 | module cl_dp1_mux7_24x( | |
5745 | in0, | |
5746 | in1, | |
5747 | in2, | |
5748 | in3, | |
5749 | in4, | |
5750 | in5, | |
5751 | in6, | |
5752 | sel0, | |
5753 | sel1, | |
5754 | sel2, | |
5755 | sel3, | |
5756 | sel4, | |
5757 | sel5, | |
5758 | sel6, | |
5759 | muxtst, | |
5760 | out | |
5761 | ); | |
5762 | ||
5763 | ||
5764 | output out; | |
5765 | ||
5766 | input in0; | |
5767 | input in1; | |
5768 | input in2; | |
5769 | input in3; | |
5770 | input in4; | |
5771 | input in5; | |
5772 | input in6; | |
5773 | input sel0; | |
5774 | input sel1; | |
5775 | input sel2; | |
5776 | input sel3; | |
5777 | input sel4; | |
5778 | input sel5; | |
5779 | input sel6; | |
5780 | input muxtst; | |
5781 | ||
5782 | `ifdef LIB | |
5783 | `ifdef MUXOHTEST | |
5784 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5785 | `endif | |
5786 | ||
5787 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5788 | ||
5789 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5790 | (sel[6:0] == 7'b0000010) ? in1: | |
5791 | (sel[6:0] == 7'b0000100) ? in2: | |
5792 | (sel[6:0] == 7'b0001000) ? in3: | |
5793 | (sel[6:0] == 7'b0010000) ? in4: | |
5794 | (sel[6:0] == 7'b0100000) ? in5: | |
5795 | (sel[6:0] == 7'b1000000) ? in6: | |
5796 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5797 | 1'bx; | |
5798 | `endif | |
5799 | endmodule | |
5800 | ||
5801 | module cl_dp1_mux7_2x( | |
5802 | in0, | |
5803 | in1, | |
5804 | in2, | |
5805 | in3, | |
5806 | in4, | |
5807 | in5, | |
5808 | in6, | |
5809 | sel0, | |
5810 | sel1, | |
5811 | sel2, | |
5812 | sel3, | |
5813 | sel4, | |
5814 | sel5, | |
5815 | sel6, | |
5816 | muxtst, | |
5817 | out | |
5818 | ); | |
5819 | ||
5820 | ||
5821 | output out; | |
5822 | ||
5823 | input in0; | |
5824 | input in1; | |
5825 | input in2; | |
5826 | input in3; | |
5827 | input in4; | |
5828 | input in5; | |
5829 | input in6; | |
5830 | input sel0; | |
5831 | input sel1; | |
5832 | input sel2; | |
5833 | input sel3; | |
5834 | input sel4; | |
5835 | input sel5; | |
5836 | input sel6; | |
5837 | input muxtst; | |
5838 | ||
5839 | `ifdef LIB | |
5840 | `ifdef MUXOHTEST | |
5841 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5842 | `endif | |
5843 | ||
5844 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5845 | ||
5846 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5847 | (sel[6:0] == 7'b0000010) ? in1: | |
5848 | (sel[6:0] == 7'b0000100) ? in2: | |
5849 | (sel[6:0] == 7'b0001000) ? in3: | |
5850 | (sel[6:0] == 7'b0010000) ? in4: | |
5851 | (sel[6:0] == 7'b0100000) ? in5: | |
5852 | (sel[6:0] == 7'b1000000) ? in6: | |
5853 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5854 | 1'bx; | |
5855 | `endif | |
5856 | endmodule | |
5857 | ||
5858 | module cl_dp1_mux7_32x( | |
5859 | in0, | |
5860 | in1, | |
5861 | in2, | |
5862 | in3, | |
5863 | in4, | |
5864 | in5, | |
5865 | in6, | |
5866 | sel0, | |
5867 | sel1, | |
5868 | sel2, | |
5869 | sel3, | |
5870 | sel4, | |
5871 | sel5, | |
5872 | sel6, | |
5873 | muxtst, | |
5874 | out | |
5875 | ); | |
5876 | ||
5877 | ||
5878 | output out; | |
5879 | ||
5880 | input in0; | |
5881 | input in1; | |
5882 | input in2; | |
5883 | input in3; | |
5884 | input in4; | |
5885 | input in5; | |
5886 | input in6; | |
5887 | input sel0; | |
5888 | input sel1; | |
5889 | input sel2; | |
5890 | input sel3; | |
5891 | input sel4; | |
5892 | input sel5; | |
5893 | input sel6; | |
5894 | input muxtst; | |
5895 | ||
5896 | `ifdef LIB | |
5897 | `ifdef MUXOHTEST | |
5898 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5899 | `endif | |
5900 | ||
5901 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5902 | ||
5903 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5904 | (sel[6:0] == 7'b0000010) ? in1: | |
5905 | (sel[6:0] == 7'b0000100) ? in2: | |
5906 | (sel[6:0] == 7'b0001000) ? in3: | |
5907 | (sel[6:0] == 7'b0010000) ? in4: | |
5908 | (sel[6:0] == 7'b0100000) ? in5: | |
5909 | (sel[6:0] == 7'b1000000) ? in6: | |
5910 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5911 | 1'bx; | |
5912 | `endif | |
5913 | endmodule | |
5914 | ||
5915 | module cl_dp1_mux7_4x( | |
5916 | in0, | |
5917 | in1, | |
5918 | in2, | |
5919 | in3, | |
5920 | in4, | |
5921 | in5, | |
5922 | in6, | |
5923 | sel0, | |
5924 | sel1, | |
5925 | sel2, | |
5926 | sel3, | |
5927 | sel4, | |
5928 | sel5, | |
5929 | sel6, | |
5930 | muxtst, | |
5931 | out | |
5932 | ); | |
5933 | ||
5934 | ||
5935 | output out; | |
5936 | ||
5937 | input in0; | |
5938 | input in1; | |
5939 | input in2; | |
5940 | input in3; | |
5941 | input in4; | |
5942 | input in5; | |
5943 | input in6; | |
5944 | input sel0; | |
5945 | input sel1; | |
5946 | input sel2; | |
5947 | input sel3; | |
5948 | input sel4; | |
5949 | input sel5; | |
5950 | input sel6; | |
5951 | input muxtst; | |
5952 | ||
5953 | `ifdef LIB | |
5954 | `ifdef MUXOHTEST | |
5955 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
5956 | `endif | |
5957 | ||
5958 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
5959 | ||
5960 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
5961 | (sel[6:0] == 7'b0000010) ? in1: | |
5962 | (sel[6:0] == 7'b0000100) ? in2: | |
5963 | (sel[6:0] == 7'b0001000) ? in3: | |
5964 | (sel[6:0] == 7'b0010000) ? in4: | |
5965 | (sel[6:0] == 7'b0100000) ? in5: | |
5966 | (sel[6:0] == 7'b1000000) ? in6: | |
5967 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
5968 | 1'bx; | |
5969 | `endif | |
5970 | endmodule | |
5971 | ||
5972 | module cl_dp1_mux7_6x( | |
5973 | in0, | |
5974 | in1, | |
5975 | in2, | |
5976 | in3, | |
5977 | in4, | |
5978 | in5, | |
5979 | in6, | |
5980 | sel0, | |
5981 | sel1, | |
5982 | sel2, | |
5983 | sel3, | |
5984 | sel4, | |
5985 | sel5, | |
5986 | sel6, | |
5987 | muxtst, | |
5988 | out | |
5989 | ); | |
5990 | ||
5991 | ||
5992 | output out; | |
5993 | ||
5994 | input in0; | |
5995 | input in1; | |
5996 | input in2; | |
5997 | input in3; | |
5998 | input in4; | |
5999 | input in5; | |
6000 | input in6; | |
6001 | input sel0; | |
6002 | input sel1; | |
6003 | input sel2; | |
6004 | input sel3; | |
6005 | input sel4; | |
6006 | input sel5; | |
6007 | input sel6; | |
6008 | input muxtst; | |
6009 | ||
6010 | `ifdef LIB | |
6011 | `ifdef MUXOHTEST | |
6012 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
6013 | `endif | |
6014 | ||
6015 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6016 | ||
6017 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
6018 | (sel[6:0] == 7'b0000010) ? in1: | |
6019 | (sel[6:0] == 7'b0000100) ? in2: | |
6020 | (sel[6:0] == 7'b0001000) ? in3: | |
6021 | (sel[6:0] == 7'b0010000) ? in4: | |
6022 | (sel[6:0] == 7'b0100000) ? in5: | |
6023 | (sel[6:0] == 7'b1000000) ? in6: | |
6024 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
6025 | 1'bx; | |
6026 | `endif | |
6027 | endmodule | |
6028 | ||
6029 | module cl_dp1_mux7_8x( | |
6030 | in0, | |
6031 | in1, | |
6032 | in2, | |
6033 | in3, | |
6034 | in4, | |
6035 | in5, | |
6036 | in6, | |
6037 | sel0, | |
6038 | sel1, | |
6039 | sel2, | |
6040 | sel3, | |
6041 | sel4, | |
6042 | sel5, | |
6043 | sel6, | |
6044 | muxtst, | |
6045 | out | |
6046 | ); | |
6047 | ||
6048 | ||
6049 | output out; | |
6050 | ||
6051 | input in0; | |
6052 | input in1; | |
6053 | input in2; | |
6054 | input in3; | |
6055 | input in4; | |
6056 | input in5; | |
6057 | input in6; | |
6058 | input sel0; | |
6059 | input sel1; | |
6060 | input sel2; | |
6061 | input sel3; | |
6062 | input sel4; | |
6063 | input sel5; | |
6064 | input sel6; | |
6065 | input muxtst; | |
6066 | ||
6067 | `ifdef LIB | |
6068 | `ifdef MUXOHTEST | |
6069 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6} | |
6070 | `endif | |
6071 | ||
6072 | wire [7:0] sel = {muxtst,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6073 | ||
6074 | assign out = (sel[6:0] == 7'b0000001) ? in0: | |
6075 | (sel[6:0] == 7'b0000010) ? in1: | |
6076 | (sel[6:0] == 7'b0000100) ? in2: | |
6077 | (sel[6:0] == 7'b0001000) ? in3: | |
6078 | (sel[6:0] == 7'b0010000) ? in4: | |
6079 | (sel[6:0] == 7'b0100000) ? in5: | |
6080 | (sel[6:0] == 7'b1000000) ? in6: | |
6081 | (sel[7:0] == 8'b00000000) ? 1'b1: | |
6082 | 1'bx; | |
6083 | `endif | |
6084 | endmodule | |
6085 | ||
6086 | ||
6087 | module cl_dp1_mux8_12x( | |
6088 | in0, | |
6089 | in1, | |
6090 | in2, | |
6091 | in3, | |
6092 | in4, | |
6093 | in5, | |
6094 | in6, | |
6095 | in7, | |
6096 | sel0, | |
6097 | sel1, | |
6098 | sel2, | |
6099 | sel3, | |
6100 | sel4, | |
6101 | sel5, | |
6102 | sel6, | |
6103 | sel7, | |
6104 | muxtst, | |
6105 | out | |
6106 | ); | |
6107 | ||
6108 | ||
6109 | ||
6110 | ||
6111 | input in0; | |
6112 | input in1; | |
6113 | input in2; | |
6114 | input in3; | |
6115 | input in4; | |
6116 | input in5; | |
6117 | input in6; | |
6118 | input in7; | |
6119 | input sel0; | |
6120 | input sel1; | |
6121 | input sel2; | |
6122 | input sel3; | |
6123 | input sel4; | |
6124 | input sel5; | |
6125 | input sel6; | |
6126 | input sel7; | |
6127 | input muxtst; | |
6128 | output out; | |
6129 | ||
6130 | `ifdef LIB | |
6131 | `ifdef MUXOHTEST | |
6132 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6133 | `endif | |
6134 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6135 | ||
6136 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6137 | (sel[7:0] == 8'b00000010) ? in1: | |
6138 | (sel[7:0] == 8'b00000100) ? in2: | |
6139 | (sel[7:0] == 8'b00001000) ? in3: | |
6140 | (sel[7:0] == 8'b00010000) ? in4: | |
6141 | (sel[7:0] == 8'b00100000) ? in5: | |
6142 | (sel[7:0] == 8'b01000000) ? in6: | |
6143 | (sel[7:0] == 8'b10000000) ? in7: | |
6144 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6145 | 1'bx; | |
6146 | `endif | |
6147 | endmodule | |
6148 | ||
6149 | module cl_dp1_mux8_16x( | |
6150 | in0, | |
6151 | in1, | |
6152 | in2, | |
6153 | in3, | |
6154 | in4, | |
6155 | in5, | |
6156 | in6, | |
6157 | in7, | |
6158 | sel0, | |
6159 | sel1, | |
6160 | sel2, | |
6161 | sel3, | |
6162 | sel4, | |
6163 | sel5, | |
6164 | sel6, | |
6165 | sel7, | |
6166 | muxtst, | |
6167 | out | |
6168 | ); | |
6169 | ||
6170 | ||
6171 | ||
6172 | ||
6173 | input in0; | |
6174 | input in1; | |
6175 | input in2; | |
6176 | input in3; | |
6177 | input in4; | |
6178 | input in5; | |
6179 | input in6; | |
6180 | input in7; | |
6181 | input sel0; | |
6182 | input sel1; | |
6183 | input sel2; | |
6184 | input sel3; | |
6185 | input sel4; | |
6186 | input sel5; | |
6187 | input sel6; | |
6188 | input sel7; | |
6189 | input muxtst; | |
6190 | output out; | |
6191 | ||
6192 | `ifdef LIB | |
6193 | `ifdef MUXOHTEST | |
6194 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6195 | `endif | |
6196 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6197 | ||
6198 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6199 | (sel[7:0] == 8'b00000010) ? in1: | |
6200 | (sel[7:0] == 8'b00000100) ? in2: | |
6201 | (sel[7:0] == 8'b00001000) ? in3: | |
6202 | (sel[7:0] == 8'b00010000) ? in4: | |
6203 | (sel[7:0] == 8'b00100000) ? in5: | |
6204 | (sel[7:0] == 8'b01000000) ? in6: | |
6205 | (sel[7:0] == 8'b10000000) ? in7: | |
6206 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6207 | 1'bx; | |
6208 | `endif | |
6209 | endmodule | |
6210 | ||
6211 | module cl_dp1_mux8_24x( | |
6212 | in0, | |
6213 | in1, | |
6214 | in2, | |
6215 | in3, | |
6216 | in4, | |
6217 | in5, | |
6218 | in6, | |
6219 | in7, | |
6220 | sel0, | |
6221 | sel1, | |
6222 | sel2, | |
6223 | sel3, | |
6224 | sel4, | |
6225 | sel5, | |
6226 | sel6, | |
6227 | sel7, | |
6228 | muxtst, | |
6229 | out | |
6230 | ); | |
6231 | ||
6232 | ||
6233 | ||
6234 | ||
6235 | input in0; | |
6236 | input in1; | |
6237 | input in2; | |
6238 | input in3; | |
6239 | input in4; | |
6240 | input in5; | |
6241 | input in6; | |
6242 | input in7; | |
6243 | input sel0; | |
6244 | input sel1; | |
6245 | input sel2; | |
6246 | input sel3; | |
6247 | input sel4; | |
6248 | input sel5; | |
6249 | input sel6; | |
6250 | input sel7; | |
6251 | input muxtst; | |
6252 | output out; | |
6253 | ||
6254 | `ifdef LIB | |
6255 | `ifdef MUXOHTEST | |
6256 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6257 | `endif | |
6258 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6259 | ||
6260 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6261 | (sel[7:0] == 8'b00000010) ? in1: | |
6262 | (sel[7:0] == 8'b00000100) ? in2: | |
6263 | (sel[7:0] == 8'b00001000) ? in3: | |
6264 | (sel[7:0] == 8'b00010000) ? in4: | |
6265 | (sel[7:0] == 8'b00100000) ? in5: | |
6266 | (sel[7:0] == 8'b01000000) ? in6: | |
6267 | (sel[7:0] == 8'b10000000) ? in7: | |
6268 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6269 | 1'bx; | |
6270 | `endif | |
6271 | endmodule | |
6272 | ||
6273 | module cl_dp1_mux8_2x( | |
6274 | in0, | |
6275 | in1, | |
6276 | in2, | |
6277 | in3, | |
6278 | in4, | |
6279 | in5, | |
6280 | in6, | |
6281 | in7, | |
6282 | sel0, | |
6283 | sel1, | |
6284 | sel2, | |
6285 | sel3, | |
6286 | sel4, | |
6287 | sel5, | |
6288 | sel6, | |
6289 | sel7, | |
6290 | muxtst, | |
6291 | out | |
6292 | ); | |
6293 | ||
6294 | ||
6295 | ||
6296 | ||
6297 | input in0; | |
6298 | input in1; | |
6299 | input in2; | |
6300 | input in3; | |
6301 | input in4; | |
6302 | input in5; | |
6303 | input in6; | |
6304 | input in7; | |
6305 | input sel0; | |
6306 | input sel1; | |
6307 | input sel2; | |
6308 | input sel3; | |
6309 | input sel4; | |
6310 | input sel5; | |
6311 | input sel6; | |
6312 | input sel7; | |
6313 | input muxtst; | |
6314 | output out; | |
6315 | ||
6316 | `ifdef LIB | |
6317 | `ifdef MUXOHTEST | |
6318 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6319 | `endif | |
6320 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6321 | ||
6322 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6323 | (sel[7:0] == 8'b00000010) ? in1: | |
6324 | (sel[7:0] == 8'b00000100) ? in2: | |
6325 | (sel[7:0] == 8'b00001000) ? in3: | |
6326 | (sel[7:0] == 8'b00010000) ? in4: | |
6327 | (sel[7:0] == 8'b00100000) ? in5: | |
6328 | (sel[7:0] == 8'b01000000) ? in6: | |
6329 | (sel[7:0] == 8'b10000000) ? in7: | |
6330 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6331 | 1'bx; | |
6332 | `endif | |
6333 | endmodule | |
6334 | ||
6335 | module cl_dp1_mux8_32x( | |
6336 | in0, | |
6337 | in1, | |
6338 | in2, | |
6339 | in3, | |
6340 | in4, | |
6341 | in5, | |
6342 | in6, | |
6343 | in7, | |
6344 | sel0, | |
6345 | sel1, | |
6346 | sel2, | |
6347 | sel3, | |
6348 | sel4, | |
6349 | sel5, | |
6350 | sel6, | |
6351 | sel7, | |
6352 | muxtst, | |
6353 | out | |
6354 | ); | |
6355 | ||
6356 | ||
6357 | ||
6358 | ||
6359 | input in0; | |
6360 | input in1; | |
6361 | input in2; | |
6362 | input in3; | |
6363 | input in4; | |
6364 | input in5; | |
6365 | input in6; | |
6366 | input in7; | |
6367 | input sel0; | |
6368 | input sel1; | |
6369 | input sel2; | |
6370 | input sel3; | |
6371 | input sel4; | |
6372 | input sel5; | |
6373 | input sel6; | |
6374 | input sel7; | |
6375 | input muxtst; | |
6376 | output out; | |
6377 | ||
6378 | `ifdef LIB | |
6379 | `ifdef MUXOHTEST | |
6380 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6381 | `endif | |
6382 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6383 | ||
6384 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6385 | (sel[7:0] == 8'b00000010) ? in1: | |
6386 | (sel[7:0] == 8'b00000100) ? in2: | |
6387 | (sel[7:0] == 8'b00001000) ? in3: | |
6388 | (sel[7:0] == 8'b00010000) ? in4: | |
6389 | (sel[7:0] == 8'b00100000) ? in5: | |
6390 | (sel[7:0] == 8'b01000000) ? in6: | |
6391 | (sel[7:0] == 8'b10000000) ? in7: | |
6392 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6393 | 1'bx; | |
6394 | `endif | |
6395 | endmodule | |
6396 | ||
6397 | module cl_dp1_mux8_4x( | |
6398 | in0, | |
6399 | in1, | |
6400 | in2, | |
6401 | in3, | |
6402 | in4, | |
6403 | in5, | |
6404 | in6, | |
6405 | in7, | |
6406 | sel0, | |
6407 | sel1, | |
6408 | sel2, | |
6409 | sel3, | |
6410 | sel4, | |
6411 | sel5, | |
6412 | sel6, | |
6413 | sel7, | |
6414 | muxtst, | |
6415 | out | |
6416 | ); | |
6417 | ||
6418 | ||
6419 | ||
6420 | ||
6421 | input in0; | |
6422 | input in1; | |
6423 | input in2; | |
6424 | input in3; | |
6425 | input in4; | |
6426 | input in5; | |
6427 | input in6; | |
6428 | input in7; | |
6429 | input sel0; | |
6430 | input sel1; | |
6431 | input sel2; | |
6432 | input sel3; | |
6433 | input sel4; | |
6434 | input sel5; | |
6435 | input sel6; | |
6436 | input sel7; | |
6437 | input muxtst; | |
6438 | output out; | |
6439 | ||
6440 | `ifdef LIB | |
6441 | `ifdef MUXOHTEST | |
6442 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6443 | `endif | |
6444 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6445 | ||
6446 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6447 | (sel[7:0] == 8'b00000010) ? in1: | |
6448 | (sel[7:0] == 8'b00000100) ? in2: | |
6449 | (sel[7:0] == 8'b00001000) ? in3: | |
6450 | (sel[7:0] == 8'b00010000) ? in4: | |
6451 | (sel[7:0] == 8'b00100000) ? in5: | |
6452 | (sel[7:0] == 8'b01000000) ? in6: | |
6453 | (sel[7:0] == 8'b10000000) ? in7: | |
6454 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6455 | 1'bx; | |
6456 | `endif | |
6457 | endmodule | |
6458 | ||
6459 | module cl_dp1_mux8_6x( | |
6460 | in0, | |
6461 | in1, | |
6462 | in2, | |
6463 | in3, | |
6464 | in4, | |
6465 | in5, | |
6466 | in6, | |
6467 | in7, | |
6468 | sel0, | |
6469 | sel1, | |
6470 | sel2, | |
6471 | sel3, | |
6472 | sel4, | |
6473 | sel5, | |
6474 | sel6, | |
6475 | sel7, | |
6476 | muxtst, | |
6477 | out | |
6478 | ); | |
6479 | ||
6480 | ||
6481 | ||
6482 | ||
6483 | input in0; | |
6484 | input in1; | |
6485 | input in2; | |
6486 | input in3; | |
6487 | input in4; | |
6488 | input in5; | |
6489 | input in6; | |
6490 | input in7; | |
6491 | input sel0; | |
6492 | input sel1; | |
6493 | input sel2; | |
6494 | input sel3; | |
6495 | input sel4; | |
6496 | input sel5; | |
6497 | input sel6; | |
6498 | input sel7; | |
6499 | input muxtst; | |
6500 | output out; | |
6501 | ||
6502 | `ifdef LIB | |
6503 | `ifdef MUXOHTEST | |
6504 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6505 | `endif | |
6506 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6507 | ||
6508 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6509 | (sel[7:0] == 8'b00000010) ? in1: | |
6510 | (sel[7:0] == 8'b00000100) ? in2: | |
6511 | (sel[7:0] == 8'b00001000) ? in3: | |
6512 | (sel[7:0] == 8'b00010000) ? in4: | |
6513 | (sel[7:0] == 8'b00100000) ? in5: | |
6514 | (sel[7:0] == 8'b01000000) ? in6: | |
6515 | (sel[7:0] == 8'b10000000) ? in7: | |
6516 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6517 | 1'bx; | |
6518 | `endif | |
6519 | endmodule | |
6520 | ||
6521 | module cl_dp1_mux8_8x( | |
6522 | in0, | |
6523 | in1, | |
6524 | in2, | |
6525 | in3, | |
6526 | in4, | |
6527 | in5, | |
6528 | in6, | |
6529 | in7, | |
6530 | sel0, | |
6531 | sel1, | |
6532 | sel2, | |
6533 | sel3, | |
6534 | sel4, | |
6535 | sel5, | |
6536 | sel6, | |
6537 | sel7, | |
6538 | muxtst, | |
6539 | out | |
6540 | ); | |
6541 | ||
6542 | ||
6543 | ||
6544 | ||
6545 | input in0; | |
6546 | input in1; | |
6547 | input in2; | |
6548 | input in3; | |
6549 | input in4; | |
6550 | input in5; | |
6551 | input in6; | |
6552 | input in7; | |
6553 | input sel0; | |
6554 | input sel1; | |
6555 | input sel2; | |
6556 | input sel3; | |
6557 | input sel4; | |
6558 | input sel5; | |
6559 | input sel6; | |
6560 | input sel7; | |
6561 | input muxtst; | |
6562 | output out; | |
6563 | ||
6564 | `ifdef LIB | |
6565 | `ifdef MUXOHTEST | |
6566 | //0in bits_on -max 1 -name "oh" -var {sel0,sel1,sel2,sel3,sel4,sel5,sel6,sel7} | |
6567 | `endif | |
6568 | wire [8:0] sel = {muxtst,sel7,sel6,sel5,sel4,sel3,sel2,sel1,sel0}; | |
6569 | ||
6570 | assign out = (sel[7:0] == 8'b00000001) ? in0: | |
6571 | (sel[7:0] == 8'b00000010) ? in1: | |
6572 | (sel[7:0] == 8'b00000100) ? in2: | |
6573 | (sel[7:0] == 8'b00001000) ? in3: | |
6574 | (sel[7:0] == 8'b00010000) ? in4: | |
6575 | (sel[7:0] == 8'b00100000) ? in5: | |
6576 | (sel[7:0] == 8'b01000000) ? in6: | |
6577 | (sel[7:0] == 8'b10000000) ? in7: | |
6578 | (sel[8:0] == 9'b000000000) ? 1'b1: | |
6579 | 1'bx; | |
6580 | `endif | |
6581 | endmodule | |
6582 | ||
6583 | ||
6584 | module cl_dp1_muxbuff2_16x ( | |
6585 | in0, | |
6586 | in1, | |
6587 | out0, | |
6588 | out1 | |
6589 | ); | |
6590 | input in0; | |
6591 | input in1; | |
6592 | output out0; | |
6593 | output out1; | |
6594 | ||
6595 | `ifdef LIB | |
6596 | assign {out1,out0} = {in1,in0}; | |
6597 | `endif | |
6598 | ||
6599 | endmodule | |
6600 | module cl_dp1_muxbuff2_32x ( | |
6601 | in0, | |
6602 | in1, | |
6603 | out0, | |
6604 | out1 | |
6605 | ); | |
6606 | input in0; | |
6607 | input in1; | |
6608 | output out0; | |
6609 | output out1; | |
6610 | ||
6611 | `ifdef LIB | |
6612 | assign {out1,out0} = {in1,in0}; | |
6613 | `endif | |
6614 | ||
6615 | endmodule | |
6616 | module cl_dp1_muxbuff2_48x ( | |
6617 | in0, | |
6618 | in1, | |
6619 | out0, | |
6620 | out1 | |
6621 | ); | |
6622 | input in0; | |
6623 | input in1; | |
6624 | output out0; | |
6625 | output out1; | |
6626 | ||
6627 | `ifdef LIB | |
6628 | assign {out1,out0} = {in1,in0}; | |
6629 | `endif | |
6630 | ||
6631 | endmodule | |
6632 | module cl_dp1_muxbuff2_64x ( | |
6633 | in0, | |
6634 | in1, | |
6635 | out0, | |
6636 | out1 | |
6637 | ); | |
6638 | input in0; | |
6639 | input in1; | |
6640 | output out0; | |
6641 | output out1; | |
6642 | ||
6643 | `ifdef LIB | |
6644 | assign {out1,out0} = {in1,in0}; | |
6645 | `endif | |
6646 | ||
6647 | endmodule | |
6648 | ||
6649 | module cl_dp1_muxbuff2_8x ( | |
6650 | in0, | |
6651 | in1, | |
6652 | out0, | |
6653 | out1 | |
6654 | ); | |
6655 | input in0; | |
6656 | input in1; | |
6657 | output out0; | |
6658 | output out1; | |
6659 | ||
6660 | `ifdef LIB | |
6661 | assign {out1,out0} = {in1,in0}; | |
6662 | `endif | |
6663 | ||
6664 | endmodule | |
6665 | module cl_dp1_muxbuff3_16x ( | |
6666 | in0, | |
6667 | in1, | |
6668 | in2, | |
6669 | out0, | |
6670 | out1, | |
6671 | out2 | |
6672 | ); | |
6673 | input in0; | |
6674 | input in1; | |
6675 | input in2; | |
6676 | output out0; | |
6677 | output out1; | |
6678 | output out2; | |
6679 | ||
6680 | `ifdef LIB | |
6681 | assign {out2,out1,out0} = {in2,in1,in0}; | |
6682 | `endif | |
6683 | ||
6684 | endmodule | |
6685 | module cl_dp1_muxbuff3_32x ( | |
6686 | in0, | |
6687 | in1, | |
6688 | in2, | |
6689 | out0, | |
6690 | out1, | |
6691 | out2 | |
6692 | ); | |
6693 | input in0; | |
6694 | input in1; | |
6695 | input in2; | |
6696 | output out0; | |
6697 | output out1; | |
6698 | output out2; | |
6699 | ||
6700 | `ifdef LIB | |
6701 | assign {out2,out1,out0} = {in2,in1,in0}; | |
6702 | `endif | |
6703 | ||
6704 | endmodule | |
6705 | module cl_dp1_muxbuff3_48x ( | |
6706 | in0, | |
6707 | in1, | |
6708 | in2, | |
6709 | out0, | |
6710 | out1, | |
6711 | out2 | |
6712 | ); | |
6713 | input in0; | |
6714 | input in1; | |
6715 | input in2; | |
6716 | output out0; | |
6717 | output out1; | |
6718 | output out2; | |
6719 | ||
6720 | `ifdef LIB | |
6721 | assign {out2,out1,out0} = {in2,in1,in0}; | |
6722 | `endif | |
6723 | ||
6724 | endmodule | |
6725 | module cl_dp1_muxbuff3_64x ( | |
6726 | in0, | |
6727 | in1, | |
6728 | in2, | |
6729 | out0, | |
6730 | out1, | |
6731 | out2 | |
6732 | ); | |
6733 | input in0; | |
6734 | input in1; | |
6735 | input in2; | |
6736 | output out0; | |
6737 | output out1; | |
6738 | output out2; | |
6739 | ||
6740 | `ifdef LIB | |
6741 | assign {out2,out1,out0} = {in2,in1,in0}; | |
6742 | `endif | |
6743 | ||
6744 | endmodule | |
6745 | ||
6746 | module cl_dp1_muxbuff3_8x ( | |
6747 | in0, | |
6748 | in1, | |
6749 | in2, | |
6750 | out0, | |
6751 | out1, | |
6752 | out2 | |
6753 | ); | |
6754 | input in0; | |
6755 | input in1; | |
6756 | input in2; | |
6757 | output out0; | |
6758 | output out1; | |
6759 | output out2; | |
6760 | ||
6761 | `ifdef LIB | |
6762 | assign {out2,out1,out0} = {in2,in1,in0}; | |
6763 | `endif | |
6764 | ||
6765 | endmodule | |
6766 | module cl_dp1_muxbuff4_16x ( | |
6767 | in0, | |
6768 | in1, | |
6769 | in2, | |
6770 | in3, | |
6771 | out0, | |
6772 | out1, | |
6773 | out2, | |
6774 | out3 | |
6775 | ); | |
6776 | input in0; | |
6777 | input in1; | |
6778 | input in2; | |
6779 | input in3; | |
6780 | output out0; | |
6781 | output out1; | |
6782 | output out2; | |
6783 | output out3; | |
6784 | ||
6785 | `ifdef LIB | |
6786 | assign {out3,out2,out1,out0} = {in3,in2,in1,in0}; | |
6787 | `endif | |
6788 | ||
6789 | endmodule | |
6790 | module cl_dp1_muxbuff4_32x ( | |
6791 | in0, | |
6792 | in1, | |
6793 | in2, | |
6794 | in3, | |
6795 | out0, | |
6796 | out1, | |
6797 | out2, | |
6798 | out3 | |
6799 | ); | |
6800 | input in0; | |
6801 | input in1; | |
6802 | input in2; | |
6803 | input in3; | |
6804 | output out0; | |
6805 | output out1; | |
6806 | output out2; | |
6807 | output out3; | |
6808 | ||
6809 | `ifdef LIB | |
6810 | assign {out3,out2,out1,out0} = {in3,in2,in1,in0}; | |
6811 | `endif | |
6812 | ||
6813 | endmodule | |
6814 | module cl_dp1_muxbuff4_48x ( | |
6815 | in0, | |
6816 | in1, | |
6817 | in2, | |
6818 | in3, | |
6819 | out0, | |
6820 | out1, | |
6821 | out2, | |
6822 | out3 | |
6823 | ); | |
6824 | input in0; | |
6825 | input in1; | |
6826 | input in2; | |
6827 | input in3; | |
6828 | output out0; | |
6829 | output out1; | |
6830 | output out2; | |
6831 | output out3; | |
6832 | ||
6833 | `ifdef LIB | |
6834 | assign {out3,out2,out1,out0} = {in3,in2,in1,in0}; | |
6835 | `endif | |
6836 | ||
6837 | endmodule | |
6838 | module cl_dp1_muxbuff4_64x ( | |
6839 | in0, | |
6840 | in1, | |
6841 | in2, | |
6842 | in3, | |
6843 | out0, | |
6844 | out1, | |
6845 | out2, | |
6846 | out3 | |
6847 | ); | |
6848 | input in0; | |
6849 | input in1; | |
6850 | input in2; | |
6851 | input in3; | |
6852 | output out0; | |
6853 | output out1; | |
6854 | output out2; | |
6855 | output out3; | |
6856 | ||
6857 | `ifdef LIB | |
6858 | assign {out3,out2,out1,out0} = {in3,in2,in1,in0}; | |
6859 | `endif | |
6860 | ||
6861 | endmodule | |
6862 | ||
6863 | module cl_dp1_muxbuff4_8x ( | |
6864 | in0, | |
6865 | in1, | |
6866 | in2, | |
6867 | in3, | |
6868 | out0, | |
6869 | out1, | |
6870 | out2, | |
6871 | out3 | |
6872 | ); | |
6873 | input in0; | |
6874 | input in1; | |
6875 | input in2; | |
6876 | input in3; | |
6877 | output out0; | |
6878 | output out1; | |
6879 | output out2; | |
6880 | output out3; | |
6881 | ||
6882 | `ifdef LIB | |
6883 | assign {out3,out2,out1,out0} = {in3,in2,in1,in0}; | |
6884 | `endif | |
6885 | ||
6886 | endmodule | |
6887 | module cl_dp1_muxbuff5_16x ( | |
6888 | in0, | |
6889 | in1, | |
6890 | in2, | |
6891 | in3, | |
6892 | in4, | |
6893 | out0, | |
6894 | out1, | |
6895 | out2, | |
6896 | out3, | |
6897 | out4 | |
6898 | ); | |
6899 | input in0; | |
6900 | input in1; | |
6901 | input in2; | |
6902 | input in3; | |
6903 | input in4; | |
6904 | output out0; | |
6905 | output out1; | |
6906 | output out2; | |
6907 | output out3; | |
6908 | output out4; | |
6909 | ||
6910 | `ifdef LIB | |
6911 | assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0}; | |
6912 | `endif | |
6913 | ||
6914 | endmodule | |
6915 | module cl_dp1_muxbuff5_32x ( | |
6916 | in0, | |
6917 | in1, | |
6918 | in2, | |
6919 | in3, | |
6920 | in4, | |
6921 | out0, | |
6922 | out1, | |
6923 | out2, | |
6924 | out3, | |
6925 | out4 | |
6926 | ); | |
6927 | input in0; | |
6928 | input in1; | |
6929 | input in2; | |
6930 | input in3; | |
6931 | input in4; | |
6932 | output out0; | |
6933 | output out1; | |
6934 | output out2; | |
6935 | output out3; | |
6936 | output out4; | |
6937 | ||
6938 | `ifdef LIB | |
6939 | assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0}; | |
6940 | `endif | |
6941 | ||
6942 | endmodule | |
6943 | module cl_dp1_muxbuff5_48x ( | |
6944 | in0, | |
6945 | in1, | |
6946 | in2, | |
6947 | in3, | |
6948 | in4, | |
6949 | out0, | |
6950 | out1, | |
6951 | out2, | |
6952 | out3, | |
6953 | out4 | |
6954 | ); | |
6955 | input in0; | |
6956 | input in1; | |
6957 | input in2; | |
6958 | input in3; | |
6959 | input in4; | |
6960 | output out0; | |
6961 | output out1; | |
6962 | output out2; | |
6963 | output out3; | |
6964 | output out4; | |
6965 | ||
6966 | `ifdef LIB | |
6967 | assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0}; | |
6968 | `endif | |
6969 | ||
6970 | endmodule | |
6971 | module cl_dp1_muxbuff5_64x ( | |
6972 | in0, | |
6973 | in1, | |
6974 | in2, | |
6975 | in3, | |
6976 | in4, | |
6977 | out0, | |
6978 | out1, | |
6979 | out2, | |
6980 | out3, | |
6981 | out4 | |
6982 | ); | |
6983 | input in0; | |
6984 | input in1; | |
6985 | input in2; | |
6986 | input in3; | |
6987 | input in4; | |
6988 | output out0; | |
6989 | output out1; | |
6990 | output out2; | |
6991 | output out3; | |
6992 | output out4; | |
6993 | ||
6994 | `ifdef LIB | |
6995 | assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0}; | |
6996 | `endif | |
6997 | ||
6998 | endmodule | |
6999 | ||
7000 | module cl_dp1_muxbuff5_8x ( | |
7001 | in0, | |
7002 | in1, | |
7003 | in2, | |
7004 | in3, | |
7005 | in4, | |
7006 | out0, | |
7007 | out1, | |
7008 | out2, | |
7009 | out3, | |
7010 | out4 | |
7011 | ); | |
7012 | input in0; | |
7013 | input in1; | |
7014 | input in2; | |
7015 | input in3; | |
7016 | input in4; | |
7017 | output out0; | |
7018 | output out1; | |
7019 | output out2; | |
7020 | output out3; | |
7021 | output out4; | |
7022 | ||
7023 | `ifdef LIB | |
7024 | assign {out4,out3,out2,out1,out0} = {in4,in3,in2,in1,in0}; | |
7025 | `endif | |
7026 | ||
7027 | endmodule | |
7028 | module cl_dp1_muxbuff6_16x ( | |
7029 | in0, | |
7030 | in1, | |
7031 | in2, | |
7032 | in3, | |
7033 | in4, | |
7034 | in5, | |
7035 | out0, | |
7036 | out1, | |
7037 | out2, | |
7038 | out3, | |
7039 | out4, | |
7040 | out5 | |
7041 | ); | |
7042 | input in0; | |
7043 | input in1; | |
7044 | input in2; | |
7045 | input in3; | |
7046 | input in4; | |
7047 | input in5; | |
7048 | output out0; | |
7049 | output out1; | |
7050 | output out2; | |
7051 | output out3; | |
7052 | output out4; | |
7053 | output out5; | |
7054 | ||
7055 | `ifdef LIB | |
7056 | assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0}; | |
7057 | `endif | |
7058 | ||
7059 | endmodule | |
7060 | module cl_dp1_muxbuff6_32x ( | |
7061 | in0, | |
7062 | in1, | |
7063 | in2, | |
7064 | in3, | |
7065 | in4, | |
7066 | in5, | |
7067 | out0, | |
7068 | out1, | |
7069 | out2, | |
7070 | out3, | |
7071 | out4, | |
7072 | out5 | |
7073 | ); | |
7074 | input in0; | |
7075 | input in1; | |
7076 | input in2; | |
7077 | input in3; | |
7078 | input in4; | |
7079 | input in5; | |
7080 | output out0; | |
7081 | output out1; | |
7082 | output out2; | |
7083 | output out3; | |
7084 | output out4; | |
7085 | output out5; | |
7086 | ||
7087 | `ifdef LIB | |
7088 | assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0}; | |
7089 | `endif | |
7090 | ||
7091 | endmodule | |
7092 | module cl_dp1_muxbuff6_48x ( | |
7093 | in0, | |
7094 | in1, | |
7095 | in2, | |
7096 | in3, | |
7097 | in4, | |
7098 | in5, | |
7099 | out0, | |
7100 | out1, | |
7101 | out2, | |
7102 | out3, | |
7103 | out4, | |
7104 | out5 | |
7105 | ); | |
7106 | input in0; | |
7107 | input in1; | |
7108 | input in2; | |
7109 | input in3; | |
7110 | input in4; | |
7111 | input in5; | |
7112 | output out0; | |
7113 | output out1; | |
7114 | output out2; | |
7115 | output out3; | |
7116 | output out4; | |
7117 | output out5; | |
7118 | ||
7119 | `ifdef LIB | |
7120 | assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0}; | |
7121 | `endif | |
7122 | ||
7123 | endmodule | |
7124 | module cl_dp1_muxbuff6_64x ( | |
7125 | in0, | |
7126 | in1, | |
7127 | in2, | |
7128 | in3, | |
7129 | in4, | |
7130 | in5, | |
7131 | out0, | |
7132 | out1, | |
7133 | out2, | |
7134 | out3, | |
7135 | out4, | |
7136 | out5 | |
7137 | ); | |
7138 | input in0; | |
7139 | input in1; | |
7140 | input in2; | |
7141 | input in3; | |
7142 | input in4; | |
7143 | input in5; | |
7144 | output out0; | |
7145 | output out1; | |
7146 | output out2; | |
7147 | output out3; | |
7148 | output out4; | |
7149 | output out5; | |
7150 | ||
7151 | `ifdef LIB | |
7152 | assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0}; | |
7153 | `endif | |
7154 | ||
7155 | endmodule | |
7156 | ||
7157 | module cl_dp1_muxbuff6_8x ( | |
7158 | in0, | |
7159 | in1, | |
7160 | in2, | |
7161 | in3, | |
7162 | in4, | |
7163 | in5, | |
7164 | out0, | |
7165 | out1, | |
7166 | out2, | |
7167 | out3, | |
7168 | out4, | |
7169 | out5 | |
7170 | ); | |
7171 | input in0; | |
7172 | input in1; | |
7173 | input in2; | |
7174 | input in3; | |
7175 | input in4; | |
7176 | input in5; | |
7177 | output out0; | |
7178 | output out1; | |
7179 | output out2; | |
7180 | output out3; | |
7181 | output out4; | |
7182 | output out5; | |
7183 | ||
7184 | `ifdef LIB | |
7185 | assign {out5,out4,out3,out2,out1,out0} = {in5,in4,in3,in2,in1,in0}; | |
7186 | `endif | |
7187 | ||
7188 | endmodule | |
7189 | module cl_dp1_muxbuff7_16x ( | |
7190 | in0, | |
7191 | in1, | |
7192 | in2, | |
7193 | in3, | |
7194 | in4, | |
7195 | in5, | |
7196 | in6, | |
7197 | out0, | |
7198 | out1, | |
7199 | out2, | |
7200 | out3, | |
7201 | out4, | |
7202 | out5, | |
7203 | out6 | |
7204 | ); | |
7205 | input in0; | |
7206 | input in1; | |
7207 | input in2; | |
7208 | input in3; | |
7209 | input in4; | |
7210 | input in5; | |
7211 | input in6; | |
7212 | output out0; | |
7213 | output out1; | |
7214 | output out2; | |
7215 | output out3; | |
7216 | output out4; | |
7217 | output out5; | |
7218 | output out6; | |
7219 | ||
7220 | `ifdef LIB | |
7221 | assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0}; | |
7222 | `endif | |
7223 | ||
7224 | endmodule | |
7225 | module cl_dp1_muxbuff7_32x ( | |
7226 | in0, | |
7227 | in1, | |
7228 | in2, | |
7229 | in3, | |
7230 | in4, | |
7231 | in5, | |
7232 | in6, | |
7233 | out0, | |
7234 | out1, | |
7235 | out2, | |
7236 | out3, | |
7237 | out4, | |
7238 | out5, | |
7239 | out6 | |
7240 | ); | |
7241 | input in0; | |
7242 | input in1; | |
7243 | input in2; | |
7244 | input in3; | |
7245 | input in4; | |
7246 | input in5; | |
7247 | input in6; | |
7248 | output out0; | |
7249 | output out1; | |
7250 | output out2; | |
7251 | output out3; | |
7252 | output out4; | |
7253 | output out5; | |
7254 | output out6; | |
7255 | ||
7256 | `ifdef LIB | |
7257 | assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0}; | |
7258 | `endif | |
7259 | ||
7260 | endmodule | |
7261 | module cl_dp1_muxbuff7_48x ( | |
7262 | in0, | |
7263 | in1, | |
7264 | in2, | |
7265 | in3, | |
7266 | in4, | |
7267 | in5, | |
7268 | in6, | |
7269 | out0, | |
7270 | out1, | |
7271 | out2, | |
7272 | out3, | |
7273 | out4, | |
7274 | out5, | |
7275 | out6 | |
7276 | ); | |
7277 | input in0; | |
7278 | input in1; | |
7279 | input in2; | |
7280 | input in3; | |
7281 | input in4; | |
7282 | input in5; | |
7283 | input in6; | |
7284 | output out0; | |
7285 | output out1; | |
7286 | output out2; | |
7287 | output out3; | |
7288 | output out4; | |
7289 | output out5; | |
7290 | output out6; | |
7291 | ||
7292 | `ifdef LIB | |
7293 | assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0}; | |
7294 | `endif | |
7295 | ||
7296 | endmodule | |
7297 | module cl_dp1_muxbuff7_64x ( | |
7298 | in0, | |
7299 | in1, | |
7300 | in2, | |
7301 | in3, | |
7302 | in4, | |
7303 | in5, | |
7304 | in6, | |
7305 | out0, | |
7306 | out1, | |
7307 | out2, | |
7308 | out3, | |
7309 | out4, | |
7310 | out5, | |
7311 | out6 | |
7312 | ); | |
7313 | input in0; | |
7314 | input in1; | |
7315 | input in2; | |
7316 | input in3; | |
7317 | input in4; | |
7318 | input in5; | |
7319 | input in6; | |
7320 | output out0; | |
7321 | output out1; | |
7322 | output out2; | |
7323 | output out3; | |
7324 | output out4; | |
7325 | output out5; | |
7326 | output out6; | |
7327 | ||
7328 | `ifdef LIB | |
7329 | assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0}; | |
7330 | `endif | |
7331 | ||
7332 | endmodule | |
7333 | ||
7334 | module cl_dp1_muxbuff7_8x ( | |
7335 | in0, | |
7336 | in1, | |
7337 | in2, | |
7338 | in3, | |
7339 | in4, | |
7340 | in5, | |
7341 | in6, | |
7342 | out0, | |
7343 | out1, | |
7344 | out2, | |
7345 | out3, | |
7346 | out4, | |
7347 | out5, | |
7348 | out6 | |
7349 | ); | |
7350 | input in0; | |
7351 | input in1; | |
7352 | input in2; | |
7353 | input in3; | |
7354 | input in4; | |
7355 | input in5; | |
7356 | input in6; | |
7357 | output out0; | |
7358 | output out1; | |
7359 | output out2; | |
7360 | output out3; | |
7361 | output out4; | |
7362 | output out5; | |
7363 | output out6; | |
7364 | ||
7365 | `ifdef LIB | |
7366 | assign {out6,out5,out4,out3,out2,out1,out0} = {in6,in5,in4,in3,in2,in1,in0}; | |
7367 | `endif | |
7368 | ||
7369 | endmodule | |
7370 | module cl_dp1_muxbuff8_16x ( | |
7371 | in0, | |
7372 | in1, | |
7373 | in2, | |
7374 | in3, | |
7375 | in4, | |
7376 | in5, | |
7377 | in6, | |
7378 | in7, | |
7379 | out0, | |
7380 | out1, | |
7381 | out2, | |
7382 | out3, | |
7383 | out4, | |
7384 | out5, | |
7385 | out6, | |
7386 | out7 | |
7387 | ); | |
7388 | input in0; | |
7389 | input in1; | |
7390 | input in2; | |
7391 | input in3; | |
7392 | input in4; | |
7393 | input in5; | |
7394 | input in6; | |
7395 | input in7; | |
7396 | output out0; | |
7397 | output out1; | |
7398 | output out2; | |
7399 | output out3; | |
7400 | output out4; | |
7401 | output out5; | |
7402 | output out6; | |
7403 | output out7; | |
7404 | ||
7405 | `ifdef LIB | |
7406 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0}; | |
7407 | `endif | |
7408 | ||
7409 | endmodule | |
7410 | module cl_dp1_muxbuff8_32x ( | |
7411 | in0, | |
7412 | in1, | |
7413 | in2, | |
7414 | in3, | |
7415 | in4, | |
7416 | in5, | |
7417 | in6, | |
7418 | in7, | |
7419 | out0, | |
7420 | out1, | |
7421 | out2, | |
7422 | out3, | |
7423 | out4, | |
7424 | out5, | |
7425 | out6, | |
7426 | out7 | |
7427 | ); | |
7428 | input in0; | |
7429 | input in1; | |
7430 | input in2; | |
7431 | input in3; | |
7432 | input in4; | |
7433 | input in5; | |
7434 | input in6; | |
7435 | input in7; | |
7436 | output out0; | |
7437 | output out1; | |
7438 | output out2; | |
7439 | output out3; | |
7440 | output out4; | |
7441 | output out5; | |
7442 | output out6; | |
7443 | output out7; | |
7444 | ||
7445 | `ifdef LIB | |
7446 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0}; | |
7447 | `endif | |
7448 | ||
7449 | endmodule | |
7450 | module cl_dp1_muxbuff8_48x ( | |
7451 | in0, | |
7452 | in1, | |
7453 | in2, | |
7454 | in3, | |
7455 | in4, | |
7456 | in5, | |
7457 | in6, | |
7458 | in7, | |
7459 | out0, | |
7460 | out1, | |
7461 | out2, | |
7462 | out3, | |
7463 | out4, | |
7464 | out5, | |
7465 | out6, | |
7466 | out7 | |
7467 | ); | |
7468 | input in0; | |
7469 | input in1; | |
7470 | input in2; | |
7471 | input in3; | |
7472 | input in4; | |
7473 | input in5; | |
7474 | input in6; | |
7475 | input in7; | |
7476 | output out0; | |
7477 | output out1; | |
7478 | output out2; | |
7479 | output out3; | |
7480 | output out4; | |
7481 | output out5; | |
7482 | output out6; | |
7483 | output out7; | |
7484 | ||
7485 | `ifdef LIB | |
7486 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0}; | |
7487 | `endif | |
7488 | ||
7489 | endmodule | |
7490 | module cl_dp1_muxbuff8_64x ( | |
7491 | in0, | |
7492 | in1, | |
7493 | in2, | |
7494 | in3, | |
7495 | in4, | |
7496 | in5, | |
7497 | in6, | |
7498 | in7, | |
7499 | out0, | |
7500 | out1, | |
7501 | out2, | |
7502 | out3, | |
7503 | out4, | |
7504 | out5, | |
7505 | out6, | |
7506 | out7 | |
7507 | ); | |
7508 | input in0; | |
7509 | input in1; | |
7510 | input in2; | |
7511 | input in3; | |
7512 | input in4; | |
7513 | input in5; | |
7514 | input in6; | |
7515 | input in7; | |
7516 | output out0; | |
7517 | output out1; | |
7518 | output out2; | |
7519 | output out3; | |
7520 | output out4; | |
7521 | output out5; | |
7522 | output out6; | |
7523 | output out7; | |
7524 | ||
7525 | `ifdef LIB | |
7526 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0}; | |
7527 | `endif | |
7528 | ||
7529 | endmodule | |
7530 | ||
7531 | module cl_dp1_muxbuff8_8x ( | |
7532 | in0, | |
7533 | in1, | |
7534 | in2, | |
7535 | in3, | |
7536 | in4, | |
7537 | in5, | |
7538 | in6, | |
7539 | in7, | |
7540 | out0, | |
7541 | out1, | |
7542 | out2, | |
7543 | out3, | |
7544 | out4, | |
7545 | out5, | |
7546 | out6, | |
7547 | out7 | |
7548 | ); | |
7549 | input in0; | |
7550 | input in1; | |
7551 | input in2; | |
7552 | input in3; | |
7553 | input in4; | |
7554 | input in5; | |
7555 | input in6; | |
7556 | input in7; | |
7557 | output out0; | |
7558 | output out1; | |
7559 | output out2; | |
7560 | output out3; | |
7561 | output out4; | |
7562 | output out5; | |
7563 | output out6; | |
7564 | output out7; | |
7565 | ||
7566 | `ifdef LIB | |
7567 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = {in7,in6,in5,in4,in3,in2,in1,in0}; | |
7568 | `endif | |
7569 | ||
7570 | endmodule | |
7571 | module cl_dp1_muxinv2_16x ( | |
7572 | in0, | |
7573 | in1, | |
7574 | out0, | |
7575 | out1 | |
7576 | ); | |
7577 | input in0; | |
7578 | input in1; | |
7579 | output out0; | |
7580 | output out1; | |
7581 | ||
7582 | `ifdef LIB | |
7583 | assign {out1,out0} = ~{in1,in0}; | |
7584 | `endif | |
7585 | ||
7586 | endmodule | |
7587 | module cl_dp1_muxinv2_32x ( | |
7588 | in0, | |
7589 | in1, | |
7590 | out0, | |
7591 | out1 | |
7592 | ); | |
7593 | input in0; | |
7594 | input in1; | |
7595 | output out0; | |
7596 | output out1; | |
7597 | ||
7598 | `ifdef LIB | |
7599 | assign {out1,out0} = ~{in1,in0}; | |
7600 | `endif | |
7601 | ||
7602 | endmodule | |
7603 | module cl_dp1_muxinv2_48x ( | |
7604 | in0, | |
7605 | in1, | |
7606 | out0, | |
7607 | out1 | |
7608 | ); | |
7609 | input in0; | |
7610 | input in1; | |
7611 | output out0; | |
7612 | output out1; | |
7613 | ||
7614 | `ifdef LIB | |
7615 | assign {out1,out0} = ~{in1,in0}; | |
7616 | `endif | |
7617 | ||
7618 | endmodule | |
7619 | module cl_dp1_muxinv2_64x ( | |
7620 | in0, | |
7621 | in1, | |
7622 | out0, | |
7623 | out1 | |
7624 | ); | |
7625 | input in0; | |
7626 | input in1; | |
7627 | output out0; | |
7628 | output out1; | |
7629 | ||
7630 | `ifdef LIB | |
7631 | assign {out1,out0} = ~{in1,in0}; | |
7632 | `endif | |
7633 | ||
7634 | endmodule | |
7635 | ||
7636 | module cl_dp1_muxinv2_8x ( | |
7637 | in0, | |
7638 | in1, | |
7639 | out0, | |
7640 | out1 | |
7641 | ); | |
7642 | input in0; | |
7643 | input in1; | |
7644 | output out0; | |
7645 | output out1; | |
7646 | ||
7647 | `ifdef LIB | |
7648 | assign {out1,out0} = ~{in1,in0}; | |
7649 | `endif | |
7650 | ||
7651 | endmodule | |
7652 | module cl_dp1_muxinv3_16x ( | |
7653 | in0, | |
7654 | in1, | |
7655 | in2, | |
7656 | out0, | |
7657 | out1, | |
7658 | out2 | |
7659 | ); | |
7660 | input in0; | |
7661 | input in1; | |
7662 | input in2; | |
7663 | output out0; | |
7664 | output out1; | |
7665 | output out2; | |
7666 | ||
7667 | `ifdef LIB | |
7668 | assign {out2,out1,out0} = ~{in2,in1,in0}; | |
7669 | `endif | |
7670 | ||
7671 | endmodule | |
7672 | module cl_dp1_muxinv3_32x ( | |
7673 | in0, | |
7674 | in1, | |
7675 | in2, | |
7676 | out0, | |
7677 | out1, | |
7678 | out2 | |
7679 | ); | |
7680 | input in0; | |
7681 | input in1; | |
7682 | input in2; | |
7683 | output out0; | |
7684 | output out1; | |
7685 | output out2; | |
7686 | ||
7687 | `ifdef LIB | |
7688 | assign {out2,out1,out0} = ~{in2,in1,in0}; | |
7689 | `endif | |
7690 | ||
7691 | endmodule | |
7692 | module cl_dp1_muxinv3_48x ( | |
7693 | in0, | |
7694 | in1, | |
7695 | in2, | |
7696 | out0, | |
7697 | out1, | |
7698 | out2 | |
7699 | ); | |
7700 | input in0; | |
7701 | input in1; | |
7702 | input in2; | |
7703 | output out0; | |
7704 | output out1; | |
7705 | output out2; | |
7706 | ||
7707 | `ifdef LIB | |
7708 | assign {out2,out1,out0} = ~{in2,in1,in0}; | |
7709 | `endif | |
7710 | ||
7711 | endmodule | |
7712 | module cl_dp1_muxinv3_64x ( | |
7713 | in0, | |
7714 | in1, | |
7715 | in2, | |
7716 | out0, | |
7717 | out1, | |
7718 | out2 | |
7719 | ); | |
7720 | input in0; | |
7721 | input in1; | |
7722 | input in2; | |
7723 | output out0; | |
7724 | output out1; | |
7725 | output out2; | |
7726 | ||
7727 | `ifdef LIB | |
7728 | assign {out2,out1,out0} = ~{in2,in1,in0}; | |
7729 | `endif | |
7730 | ||
7731 | endmodule | |
7732 | ||
7733 | module cl_dp1_muxinv3_8x ( | |
7734 | in0, | |
7735 | in1, | |
7736 | in2, | |
7737 | out0, | |
7738 | out1, | |
7739 | out2 | |
7740 | ); | |
7741 | input in0; | |
7742 | input in1; | |
7743 | input in2; | |
7744 | output out0; | |
7745 | output out1; | |
7746 | output out2; | |
7747 | ||
7748 | `ifdef LIB | |
7749 | assign {out2,out1,out0} = ~{in2,in1,in0}; | |
7750 | `endif | |
7751 | ||
7752 | endmodule | |
7753 | module cl_dp1_muxinv4_16x ( | |
7754 | in0, | |
7755 | in1, | |
7756 | in2, | |
7757 | in3, | |
7758 | out0, | |
7759 | out1, | |
7760 | out2, | |
7761 | out3 | |
7762 | ); | |
7763 | input in0; | |
7764 | input in1; | |
7765 | input in2; | |
7766 | input in3; | |
7767 | output out0; | |
7768 | output out1; | |
7769 | output out2; | |
7770 | output out3; | |
7771 | ||
7772 | `ifdef LIB | |
7773 | assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0}; | |
7774 | `endif | |
7775 | ||
7776 | endmodule | |
7777 | module cl_dp1_muxinv4_32x ( | |
7778 | in0, | |
7779 | in1, | |
7780 | in2, | |
7781 | in3, | |
7782 | out0, | |
7783 | out1, | |
7784 | out2, | |
7785 | out3 | |
7786 | ); | |
7787 | input in0; | |
7788 | input in1; | |
7789 | input in2; | |
7790 | input in3; | |
7791 | output out0; | |
7792 | output out1; | |
7793 | output out2; | |
7794 | output out3; | |
7795 | ||
7796 | `ifdef LIB | |
7797 | assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0}; | |
7798 | `endif | |
7799 | ||
7800 | endmodule | |
7801 | module cl_dp1_muxinv4_48x ( | |
7802 | in0, | |
7803 | in1, | |
7804 | in2, | |
7805 | in3, | |
7806 | out0, | |
7807 | out1, | |
7808 | out2, | |
7809 | out3 | |
7810 | ); | |
7811 | input in0; | |
7812 | input in1; | |
7813 | input in2; | |
7814 | input in3; | |
7815 | output out0; | |
7816 | output out1; | |
7817 | output out2; | |
7818 | output out3; | |
7819 | ||
7820 | `ifdef LIB | |
7821 | assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0}; | |
7822 | `endif | |
7823 | ||
7824 | endmodule | |
7825 | module cl_dp1_muxinv4_64x ( | |
7826 | in0, | |
7827 | in1, | |
7828 | in2, | |
7829 | in3, | |
7830 | out0, | |
7831 | out1, | |
7832 | out2, | |
7833 | out3 | |
7834 | ); | |
7835 | input in0; | |
7836 | input in1; | |
7837 | input in2; | |
7838 | input in3; | |
7839 | output out0; | |
7840 | output out1; | |
7841 | output out2; | |
7842 | output out3; | |
7843 | ||
7844 | `ifdef LIB | |
7845 | assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0}; | |
7846 | `endif | |
7847 | ||
7848 | endmodule | |
7849 | ||
7850 | module cl_dp1_muxinv4_8x ( | |
7851 | in0, | |
7852 | in1, | |
7853 | in2, | |
7854 | in3, | |
7855 | out0, | |
7856 | out1, | |
7857 | out2, | |
7858 | out3 | |
7859 | ); | |
7860 | input in0; | |
7861 | input in1; | |
7862 | input in2; | |
7863 | input in3; | |
7864 | output out0; | |
7865 | output out1; | |
7866 | output out2; | |
7867 | output out3; | |
7868 | ||
7869 | `ifdef LIB | |
7870 | assign {out3,out2,out1,out0} = ~{in3,in2,in1,in0}; | |
7871 | `endif | |
7872 | ||
7873 | endmodule | |
7874 | module cl_dp1_muxinv5_16x ( | |
7875 | in0, | |
7876 | in1, | |
7877 | in2, | |
7878 | in3, | |
7879 | in4, | |
7880 | out0, | |
7881 | out1, | |
7882 | out2, | |
7883 | out3, | |
7884 | out4 | |
7885 | ); | |
7886 | input in0; | |
7887 | input in1; | |
7888 | input in2; | |
7889 | input in3; | |
7890 | input in4; | |
7891 | output out0; | |
7892 | output out1; | |
7893 | output out2; | |
7894 | output out3; | |
7895 | output out4; | |
7896 | ||
7897 | `ifdef LIB | |
7898 | assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0}; | |
7899 | `endif | |
7900 | ||
7901 | endmodule | |
7902 | module cl_dp1_muxinv5_32x ( | |
7903 | in0, | |
7904 | in1, | |
7905 | in2, | |
7906 | in3, | |
7907 | in4, | |
7908 | out0, | |
7909 | out1, | |
7910 | out2, | |
7911 | out3, | |
7912 | out4 | |
7913 | ); | |
7914 | input in0; | |
7915 | input in1; | |
7916 | input in2; | |
7917 | input in3; | |
7918 | input in4; | |
7919 | output out0; | |
7920 | output out1; | |
7921 | output out2; | |
7922 | output out3; | |
7923 | output out4; | |
7924 | ||
7925 | `ifdef LIB | |
7926 | assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0}; | |
7927 | `endif | |
7928 | ||
7929 | endmodule | |
7930 | module cl_dp1_muxinv5_48x ( | |
7931 | in0, | |
7932 | in1, | |
7933 | in2, | |
7934 | in3, | |
7935 | in4, | |
7936 | out0, | |
7937 | out1, | |
7938 | out2, | |
7939 | out3, | |
7940 | out4 | |
7941 | ); | |
7942 | input in0; | |
7943 | input in1; | |
7944 | input in2; | |
7945 | input in3; | |
7946 | input in4; | |
7947 | output out0; | |
7948 | output out1; | |
7949 | output out2; | |
7950 | output out3; | |
7951 | output out4; | |
7952 | ||
7953 | `ifdef LIB | |
7954 | assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0}; | |
7955 | `endif | |
7956 | ||
7957 | endmodule | |
7958 | module cl_dp1_muxinv5_64x ( | |
7959 | in0, | |
7960 | in1, | |
7961 | in2, | |
7962 | in3, | |
7963 | in4, | |
7964 | out0, | |
7965 | out1, | |
7966 | out2, | |
7967 | out3, | |
7968 | out4 | |
7969 | ); | |
7970 | input in0; | |
7971 | input in1; | |
7972 | input in2; | |
7973 | input in3; | |
7974 | input in4; | |
7975 | output out0; | |
7976 | output out1; | |
7977 | output out2; | |
7978 | output out3; | |
7979 | output out4; | |
7980 | ||
7981 | `ifdef LIB | |
7982 | assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0}; | |
7983 | `endif | |
7984 | ||
7985 | endmodule | |
7986 | ||
7987 | module cl_dp1_muxinv5_8x ( | |
7988 | in0, | |
7989 | in1, | |
7990 | in2, | |
7991 | in3, | |
7992 | in4, | |
7993 | out0, | |
7994 | out1, | |
7995 | out2, | |
7996 | out3, | |
7997 | out4 | |
7998 | ); | |
7999 | input in0; | |
8000 | input in1; | |
8001 | input in2; | |
8002 | input in3; | |
8003 | input in4; | |
8004 | output out0; | |
8005 | output out1; | |
8006 | output out2; | |
8007 | output out3; | |
8008 | output out4; | |
8009 | ||
8010 | `ifdef LIB | |
8011 | assign {out4,out3,out2,out1,out0} = ~{in4,in3,in2,in1,in0}; | |
8012 | `endif | |
8013 | ||
8014 | endmodule | |
8015 | module cl_dp1_muxinv6_16x ( | |
8016 | in0, | |
8017 | in1, | |
8018 | in2, | |
8019 | in3, | |
8020 | in4, | |
8021 | in5, | |
8022 | out0, | |
8023 | out1, | |
8024 | out2, | |
8025 | out3, | |
8026 | out4, | |
8027 | out5 | |
8028 | ); | |
8029 | input in0; | |
8030 | input in1; | |
8031 | input in2; | |
8032 | input in3; | |
8033 | input in4; | |
8034 | input in5; | |
8035 | output out0; | |
8036 | output out1; | |
8037 | output out2; | |
8038 | output out3; | |
8039 | output out4; | |
8040 | output out5; | |
8041 | ||
8042 | `ifdef LIB | |
8043 | assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0}; | |
8044 | `endif | |
8045 | ||
8046 | endmodule | |
8047 | module cl_dp1_muxinv6_32x ( | |
8048 | in0, | |
8049 | in1, | |
8050 | in2, | |
8051 | in3, | |
8052 | in4, | |
8053 | in5, | |
8054 | out0, | |
8055 | out1, | |
8056 | out2, | |
8057 | out3, | |
8058 | out4, | |
8059 | out5 | |
8060 | ); | |
8061 | input in0; | |
8062 | input in1; | |
8063 | input in2; | |
8064 | input in3; | |
8065 | input in4; | |
8066 | input in5; | |
8067 | output out0; | |
8068 | output out1; | |
8069 | output out2; | |
8070 | output out3; | |
8071 | output out4; | |
8072 | output out5; | |
8073 | ||
8074 | `ifdef LIB | |
8075 | assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0}; | |
8076 | `endif | |
8077 | ||
8078 | endmodule | |
8079 | module cl_dp1_muxinv6_48x ( | |
8080 | in0, | |
8081 | in1, | |
8082 | in2, | |
8083 | in3, | |
8084 | in4, | |
8085 | in5, | |
8086 | out0, | |
8087 | out1, | |
8088 | out2, | |
8089 | out3, | |
8090 | out4, | |
8091 | out5 | |
8092 | ); | |
8093 | input in0; | |
8094 | input in1; | |
8095 | input in2; | |
8096 | input in3; | |
8097 | input in4; | |
8098 | input in5; | |
8099 | output out0; | |
8100 | output out1; | |
8101 | output out2; | |
8102 | output out3; | |
8103 | output out4; | |
8104 | output out5; | |
8105 | ||
8106 | `ifdef LIB | |
8107 | assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0}; | |
8108 | `endif | |
8109 | ||
8110 | endmodule | |
8111 | module cl_dp1_muxinv6_64x ( | |
8112 | in0, | |
8113 | in1, | |
8114 | in2, | |
8115 | in3, | |
8116 | in4, | |
8117 | in5, | |
8118 | out0, | |
8119 | out1, | |
8120 | out2, | |
8121 | out3, | |
8122 | out4, | |
8123 | out5 | |
8124 | ); | |
8125 | input in0; | |
8126 | input in1; | |
8127 | input in2; | |
8128 | input in3; | |
8129 | input in4; | |
8130 | input in5; | |
8131 | output out0; | |
8132 | output out1; | |
8133 | output out2; | |
8134 | output out3; | |
8135 | output out4; | |
8136 | output out5; | |
8137 | ||
8138 | `ifdef LIB | |
8139 | assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0}; | |
8140 | `endif | |
8141 | ||
8142 | endmodule | |
8143 | ||
8144 | module cl_dp1_muxinv6_8x ( | |
8145 | in0, | |
8146 | in1, | |
8147 | in2, | |
8148 | in3, | |
8149 | in4, | |
8150 | in5, | |
8151 | out0, | |
8152 | out1, | |
8153 | out2, | |
8154 | out3, | |
8155 | out4, | |
8156 | out5 | |
8157 | ); | |
8158 | input in0; | |
8159 | input in1; | |
8160 | input in2; | |
8161 | input in3; | |
8162 | input in4; | |
8163 | input in5; | |
8164 | output out0; | |
8165 | output out1; | |
8166 | output out2; | |
8167 | output out3; | |
8168 | output out4; | |
8169 | output out5; | |
8170 | ||
8171 | `ifdef LIB | |
8172 | assign {out5,out4,out3,out2,out1,out0} = ~{in5,in4,in3,in2,in1,in0}; | |
8173 | `endif | |
8174 | ||
8175 | endmodule | |
8176 | module cl_dp1_muxinv7_16x ( | |
8177 | in0, | |
8178 | in1, | |
8179 | in2, | |
8180 | in3, | |
8181 | in4, | |
8182 | in5, | |
8183 | in6, | |
8184 | out0, | |
8185 | out1, | |
8186 | out2, | |
8187 | out3, | |
8188 | out4, | |
8189 | out5, | |
8190 | out6 | |
8191 | ); | |
8192 | input in0; | |
8193 | input in1; | |
8194 | input in2; | |
8195 | input in3; | |
8196 | input in4; | |
8197 | input in5; | |
8198 | input in6; | |
8199 | output out0; | |
8200 | output out1; | |
8201 | output out2; | |
8202 | output out3; | |
8203 | output out4; | |
8204 | output out5; | |
8205 | output out6; | |
8206 | ||
8207 | `ifdef LIB | |
8208 | assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0}; | |
8209 | `endif | |
8210 | ||
8211 | endmodule | |
8212 | module cl_dp1_muxinv7_32x ( | |
8213 | in0, | |
8214 | in1, | |
8215 | in2, | |
8216 | in3, | |
8217 | in4, | |
8218 | in5, | |
8219 | in6, | |
8220 | out0, | |
8221 | out1, | |
8222 | out2, | |
8223 | out3, | |
8224 | out4, | |
8225 | out5, | |
8226 | out6 | |
8227 | ); | |
8228 | input in0; | |
8229 | input in1; | |
8230 | input in2; | |
8231 | input in3; | |
8232 | input in4; | |
8233 | input in5; | |
8234 | input in6; | |
8235 | output out0; | |
8236 | output out1; | |
8237 | output out2; | |
8238 | output out3; | |
8239 | output out4; | |
8240 | output out5; | |
8241 | output out6; | |
8242 | ||
8243 | `ifdef LIB | |
8244 | assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0}; | |
8245 | `endif | |
8246 | ||
8247 | endmodule | |
8248 | module cl_dp1_muxinv7_48x ( | |
8249 | in0, | |
8250 | in1, | |
8251 | in2, | |
8252 | in3, | |
8253 | in4, | |
8254 | in5, | |
8255 | in6, | |
8256 | out0, | |
8257 | out1, | |
8258 | out2, | |
8259 | out3, | |
8260 | out4, | |
8261 | out5, | |
8262 | out6 | |
8263 | ); | |
8264 | input in0; | |
8265 | input in1; | |
8266 | input in2; | |
8267 | input in3; | |
8268 | input in4; | |
8269 | input in5; | |
8270 | input in6; | |
8271 | output out0; | |
8272 | output out1; | |
8273 | output out2; | |
8274 | output out3; | |
8275 | output out4; | |
8276 | output out5; | |
8277 | output out6; | |
8278 | ||
8279 | `ifdef LIB | |
8280 | assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0}; | |
8281 | `endif | |
8282 | ||
8283 | endmodule | |
8284 | module cl_dp1_muxinv7_64x ( | |
8285 | in0, | |
8286 | in1, | |
8287 | in2, | |
8288 | in3, | |
8289 | in4, | |
8290 | in5, | |
8291 | in6, | |
8292 | out0, | |
8293 | out1, | |
8294 | out2, | |
8295 | out3, | |
8296 | out4, | |
8297 | out5, | |
8298 | out6 | |
8299 | ); | |
8300 | input in0; | |
8301 | input in1; | |
8302 | input in2; | |
8303 | input in3; | |
8304 | input in4; | |
8305 | input in5; | |
8306 | input in6; | |
8307 | output out0; | |
8308 | output out1; | |
8309 | output out2; | |
8310 | output out3; | |
8311 | output out4; | |
8312 | output out5; | |
8313 | output out6; | |
8314 | ||
8315 | `ifdef LIB | |
8316 | assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0}; | |
8317 | `endif | |
8318 | ||
8319 | endmodule | |
8320 | ||
8321 | module cl_dp1_muxinv7_8x ( | |
8322 | in0, | |
8323 | in1, | |
8324 | in2, | |
8325 | in3, | |
8326 | in4, | |
8327 | in5, | |
8328 | in6, | |
8329 | out0, | |
8330 | out1, | |
8331 | out2, | |
8332 | out3, | |
8333 | out4, | |
8334 | out5, | |
8335 | out6 | |
8336 | ); | |
8337 | input in0; | |
8338 | input in1; | |
8339 | input in2; | |
8340 | input in3; | |
8341 | input in4; | |
8342 | input in5; | |
8343 | input in6; | |
8344 | output out0; | |
8345 | output out1; | |
8346 | output out2; | |
8347 | output out3; | |
8348 | output out4; | |
8349 | output out5; | |
8350 | output out6; | |
8351 | ||
8352 | `ifdef LIB | |
8353 | assign {out6,out5,out4,out3,out2,out1,out0} = ~{in6,in5,in4,in3,in2,in1,in0}; | |
8354 | `endif | |
8355 | ||
8356 | endmodule | |
8357 | module cl_dp1_muxinv8_16x ( | |
8358 | in0, | |
8359 | in1, | |
8360 | in2, | |
8361 | in3, | |
8362 | in4, | |
8363 | in5, | |
8364 | in6, | |
8365 | in7, | |
8366 | out0, | |
8367 | out1, | |
8368 | out2, | |
8369 | out3, | |
8370 | out4, | |
8371 | out5, | |
8372 | out6, | |
8373 | out7 | |
8374 | ); | |
8375 | input in0; | |
8376 | input in1; | |
8377 | input in2; | |
8378 | input in3; | |
8379 | input in4; | |
8380 | input in5; | |
8381 | input in6; | |
8382 | input in7; | |
8383 | output out0; | |
8384 | output out1; | |
8385 | output out2; | |
8386 | output out3; | |
8387 | output out4; | |
8388 | output out5; | |
8389 | output out6; | |
8390 | output out7; | |
8391 | ||
8392 | `ifdef LIB | |
8393 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0}; | |
8394 | `endif | |
8395 | ||
8396 | endmodule | |
8397 | module cl_dp1_muxinv8_32x ( | |
8398 | in0, | |
8399 | in1, | |
8400 | in2, | |
8401 | in3, | |
8402 | in4, | |
8403 | in5, | |
8404 | in6, | |
8405 | in7, | |
8406 | out0, | |
8407 | out1, | |
8408 | out2, | |
8409 | out3, | |
8410 | out4, | |
8411 | out5, | |
8412 | out6, | |
8413 | out7 | |
8414 | ); | |
8415 | input in0; | |
8416 | input in1; | |
8417 | input in2; | |
8418 | input in3; | |
8419 | input in4; | |
8420 | input in5; | |
8421 | input in6; | |
8422 | input in7; | |
8423 | output out0; | |
8424 | output out1; | |
8425 | output out2; | |
8426 | output out3; | |
8427 | output out4; | |
8428 | output out5; | |
8429 | output out6; | |
8430 | output out7; | |
8431 | ||
8432 | `ifdef LIB | |
8433 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0}; | |
8434 | `endif | |
8435 | ||
8436 | endmodule | |
8437 | module cl_dp1_muxinv8_48x ( | |
8438 | in0, | |
8439 | in1, | |
8440 | in2, | |
8441 | in3, | |
8442 | in4, | |
8443 | in5, | |
8444 | in6, | |
8445 | in7, | |
8446 | out0, | |
8447 | out1, | |
8448 | out2, | |
8449 | out3, | |
8450 | out4, | |
8451 | out5, | |
8452 | out6, | |
8453 | out7 | |
8454 | ); | |
8455 | input in0; | |
8456 | input in1; | |
8457 | input in2; | |
8458 | input in3; | |
8459 | input in4; | |
8460 | input in5; | |
8461 | input in6; | |
8462 | input in7; | |
8463 | output out0; | |
8464 | output out1; | |
8465 | output out2; | |
8466 | output out3; | |
8467 | output out4; | |
8468 | output out5; | |
8469 | output out6; | |
8470 | output out7; | |
8471 | ||
8472 | `ifdef LIB | |
8473 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0}; | |
8474 | `endif | |
8475 | ||
8476 | endmodule | |
8477 | module cl_dp1_muxinv8_64x ( | |
8478 | in0, | |
8479 | in1, | |
8480 | in2, | |
8481 | in3, | |
8482 | in4, | |
8483 | in5, | |
8484 | in6, | |
8485 | in7, | |
8486 | out0, | |
8487 | out1, | |
8488 | out2, | |
8489 | out3, | |
8490 | out4, | |
8491 | out5, | |
8492 | out6, | |
8493 | out7 | |
8494 | ); | |
8495 | input in0; | |
8496 | input in1; | |
8497 | input in2; | |
8498 | input in3; | |
8499 | input in4; | |
8500 | input in5; | |
8501 | input in6; | |
8502 | input in7; | |
8503 | output out0; | |
8504 | output out1; | |
8505 | output out2; | |
8506 | output out3; | |
8507 | output out4; | |
8508 | output out5; | |
8509 | output out6; | |
8510 | output out7; | |
8511 | ||
8512 | `ifdef LIB | |
8513 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0}; | |
8514 | `endif | |
8515 | ||
8516 | endmodule | |
8517 | ||
8518 | module cl_dp1_muxinv8_8x ( | |
8519 | in0, | |
8520 | in1, | |
8521 | in2, | |
8522 | in3, | |
8523 | in4, | |
8524 | in5, | |
8525 | in6, | |
8526 | in7, | |
8527 | out0, | |
8528 | out1, | |
8529 | out2, | |
8530 | out3, | |
8531 | out4, | |
8532 | out5, | |
8533 | out6, | |
8534 | out7 | |
8535 | ); | |
8536 | input in0; | |
8537 | input in1; | |
8538 | input in2; | |
8539 | input in3; | |
8540 | input in4; | |
8541 | input in5; | |
8542 | input in6; | |
8543 | input in7; | |
8544 | output out0; | |
8545 | output out1; | |
8546 | output out2; | |
8547 | output out3; | |
8548 | output out4; | |
8549 | output out5; | |
8550 | output out6; | |
8551 | output out7; | |
8552 | ||
8553 | `ifdef LIB | |
8554 | assign {out7,out6,out5,out4,out3,out2,out1,out0} = ~{in7,in6,in5,in4,in3,in2,in1,in0}; | |
8555 | `endif | |
8556 | ||
8557 | endmodule | |
8558 | module cl_dp1_pdec4_16x ( | |
8559 | sel0, | |
8560 | sel1, | |
8561 | test, | |
8562 | psel0, | |
8563 | psel1, | |
8564 | psel2, | |
8565 | psel3 | |
8566 | ); | |
8567 | input sel0; | |
8568 | input sel1; | |
8569 | input test; | |
8570 | output psel0; | |
8571 | output psel1; | |
8572 | output psel2; | |
8573 | output psel3; | |
8574 | ||
8575 | `ifdef LIB | |
8576 | assign psel0 = ~sel1 & ~sel0; | |
8577 | assign psel1 = ~sel1 & sel0; | |
8578 | assign psel2 = sel1 & ~sel0; | |
8579 | assign psel3 = sel1 & sel0 & test; | |
8580 | `endif | |
8581 | endmodule | |
8582 | module cl_dp1_pdec4_32x ( | |
8583 | sel0, | |
8584 | sel1, | |
8585 | test, | |
8586 | psel0, | |
8587 | psel1, | |
8588 | psel2, | |
8589 | psel3 | |
8590 | ); | |
8591 | input sel0; | |
8592 | input sel1; | |
8593 | input test; | |
8594 | output psel0; | |
8595 | output psel1; | |
8596 | output psel2; | |
8597 | output psel3; | |
8598 | ||
8599 | `ifdef LIB | |
8600 | assign psel0 = ~sel1 & ~sel0; | |
8601 | assign psel1 = ~sel1 & sel0; | |
8602 | assign psel2 = sel1 & ~sel0; | |
8603 | assign psel3 = sel1 & sel0 & test; | |
8604 | `endif | |
8605 | endmodule | |
8606 | module cl_dp1_pdec4_48x ( | |
8607 | sel0, | |
8608 | sel1, | |
8609 | test, | |
8610 | psel0, | |
8611 | psel1, | |
8612 | psel2, | |
8613 | psel3 | |
8614 | ); | |
8615 | input sel0; | |
8616 | input sel1; | |
8617 | input test; | |
8618 | output psel0; | |
8619 | output psel1; | |
8620 | output psel2; | |
8621 | output psel3; | |
8622 | ||
8623 | `ifdef LIB | |
8624 | assign psel0 = ~sel1 & ~sel0; | |
8625 | assign psel1 = ~sel1 & sel0; | |
8626 | assign psel2 = sel1 & ~sel0; | |
8627 | assign psel3 = sel1 & sel0 & test; | |
8628 | `endif | |
8629 | endmodule | |
8630 | module cl_dp1_pdec4_64x ( | |
8631 | sel0, | |
8632 | sel1, | |
8633 | test, | |
8634 | psel0, | |
8635 | psel1, | |
8636 | psel2, | |
8637 | psel3 | |
8638 | ); | |
8639 | input sel0; | |
8640 | input sel1; | |
8641 | input test; | |
8642 | output psel0; | |
8643 | output psel1; | |
8644 | output psel2; | |
8645 | output psel3; | |
8646 | ||
8647 | `ifdef LIB | |
8648 | assign psel0 = ~sel1 & ~sel0; | |
8649 | assign psel1 = ~sel1 & sel0; | |
8650 | assign psel2 = sel1 & ~sel0; | |
8651 | assign psel3 = sel1 & sel0 & test; | |
8652 | `endif | |
8653 | endmodule | |
8654 | module cl_dp1_pdec4_8x ( | |
8655 | sel0, | |
8656 | sel1, | |
8657 | test, | |
8658 | psel0, | |
8659 | psel1, | |
8660 | psel2, | |
8661 | psel3 | |
8662 | ); | |
8663 | input sel0; | |
8664 | input sel1; | |
8665 | input test; | |
8666 | output psel0; | |
8667 | output psel1; | |
8668 | output psel2; | |
8669 | output psel3; | |
8670 | ||
8671 | `ifdef LIB | |
8672 | assign psel0 = ~sel1 & ~sel0; | |
8673 | assign psel1 = ~sel1 & sel0; | |
8674 | assign psel2 = sel1 & ~sel0; | |
8675 | assign psel3 = sel1 & sel0 & test; | |
8676 | `endif | |
8677 | endmodule | |
8678 | module cl_dp1_pdec8_16x ( | |
8679 | sel0, | |
8680 | sel1, | |
8681 | sel2, | |
8682 | test, | |
8683 | psel0, | |
8684 | psel1, | |
8685 | psel2, | |
8686 | psel3, | |
8687 | psel4, | |
8688 | psel5, | |
8689 | psel6, | |
8690 | psel7 | |
8691 | ); | |
8692 | input sel0; | |
8693 | input sel1; | |
8694 | input sel2; | |
8695 | input test; | |
8696 | output psel0; | |
8697 | output psel1; | |
8698 | output psel2; | |
8699 | output psel3; | |
8700 | output psel4; | |
8701 | output psel5; | |
8702 | output psel6; | |
8703 | output psel7; | |
8704 | ||
8705 | `ifdef LIB | |
8706 | assign psel0 = ~sel2 & ~sel1 & ~sel0 & test; | |
8707 | assign psel1 = ~sel2 & ~sel1 & sel0; | |
8708 | assign psel2 = ~sel2 & sel1 & ~sel0; | |
8709 | assign psel3 = ~sel2 & sel1 & sel0; | |
8710 | assign psel4 = sel2 & ~sel1 & ~sel0; | |
8711 | assign psel5 = sel2 & ~sel1 & sel0; | |
8712 | assign psel6 = sel2 & sel1 & ~sel0; | |
8713 | assign psel7 = sel2 & sel1 & sel0; | |
8714 | `endif | |
8715 | ||
8716 | endmodule | |
8717 | module cl_dp1_pdec8_32x ( | |
8718 | sel0, | |
8719 | sel1, | |
8720 | sel2, | |
8721 | test, | |
8722 | psel0, | |
8723 | psel1, | |
8724 | psel2, | |
8725 | psel3, | |
8726 | psel4, | |
8727 | psel5, | |
8728 | psel6, | |
8729 | psel7 | |
8730 | ); | |
8731 | input sel0; | |
8732 | input sel1; | |
8733 | input sel2; | |
8734 | input test; | |
8735 | output psel0; | |
8736 | output psel1; | |
8737 | output psel2; | |
8738 | output psel3; | |
8739 | output psel4; | |
8740 | output psel5; | |
8741 | output psel6; | |
8742 | output psel7; | |
8743 | ||
8744 | `ifdef LIB | |
8745 | assign psel0 = ~sel2 & ~sel1 & ~sel0 & test; | |
8746 | assign psel1 = ~sel2 & ~sel1 & sel0; | |
8747 | assign psel2 = ~sel2 & sel1 & ~sel0; | |
8748 | assign psel3 = ~sel2 & sel1 & sel0; | |
8749 | assign psel4 = sel2 & ~sel1 & ~sel0; | |
8750 | assign psel5 = sel2 & ~sel1 & sel0; | |
8751 | assign psel6 = sel2 & sel1 & ~sel0; | |
8752 | assign psel7 = sel2 & sel1 & sel0; | |
8753 | `endif | |
8754 | ||
8755 | endmodule | |
8756 | module cl_dp1_pdec8_48x ( | |
8757 | sel0, | |
8758 | sel1, | |
8759 | sel2, | |
8760 | test, | |
8761 | psel0, | |
8762 | psel1, | |
8763 | psel2, | |
8764 | psel3, | |
8765 | psel4, | |
8766 | psel5, | |
8767 | psel6, | |
8768 | psel7 | |
8769 | ); | |
8770 | input sel0; | |
8771 | input sel1; | |
8772 | input sel2; | |
8773 | input test; | |
8774 | output psel0; | |
8775 | output psel1; | |
8776 | output psel2; | |
8777 | output psel3; | |
8778 | output psel4; | |
8779 | output psel5; | |
8780 | output psel6; | |
8781 | output psel7; | |
8782 | ||
8783 | `ifdef LIB | |
8784 | assign psel0 = ~sel2 & ~sel1 & ~sel0 & test; | |
8785 | assign psel1 = ~sel2 & ~sel1 & sel0; | |
8786 | assign psel2 = ~sel2 & sel1 & ~sel0; | |
8787 | assign psel3 = ~sel2 & sel1 & sel0; | |
8788 | assign psel4 = sel2 & ~sel1 & ~sel0; | |
8789 | assign psel5 = sel2 & ~sel1 & sel0; | |
8790 | assign psel6 = sel2 & sel1 & ~sel0; | |
8791 | assign psel7 = sel2 & sel1 & sel0; | |
8792 | `endif | |
8793 | ||
8794 | endmodule | |
8795 | module cl_dp1_pdec8_64x ( | |
8796 | sel0, | |
8797 | sel1, | |
8798 | sel2, | |
8799 | test, | |
8800 | psel0, | |
8801 | psel1, | |
8802 | psel2, | |
8803 | psel3, | |
8804 | psel4, | |
8805 | psel5, | |
8806 | psel6, | |
8807 | psel7 | |
8808 | ); | |
8809 | input sel0; | |
8810 | input sel1; | |
8811 | input sel2; | |
8812 | input test; | |
8813 | output psel0; | |
8814 | output psel1; | |
8815 | output psel2; | |
8816 | output psel3; | |
8817 | output psel4; | |
8818 | output psel5; | |
8819 | output psel6; | |
8820 | output psel7; | |
8821 | ||
8822 | `ifdef LIB | |
8823 | assign psel0 = ~sel2 & ~sel1 & ~sel0 & test; | |
8824 | assign psel1 = ~sel2 & ~sel1 & sel0; | |
8825 | assign psel2 = ~sel2 & sel1 & ~sel0; | |
8826 | assign psel3 = ~sel2 & sel1 & sel0; | |
8827 | assign psel4 = sel2 & ~sel1 & ~sel0; | |
8828 | assign psel5 = sel2 & ~sel1 & sel0; | |
8829 | assign psel6 = sel2 & sel1 & ~sel0; | |
8830 | assign psel7 = sel2 & sel1 & sel0; | |
8831 | `endif | |
8832 | ||
8833 | endmodule | |
8834 | module cl_dp1_pdec8_8x ( | |
8835 | sel0, | |
8836 | sel1, | |
8837 | sel2, | |
8838 | test, | |
8839 | psel0, | |
8840 | psel1, | |
8841 | psel2, | |
8842 | psel3, | |
8843 | psel4, | |
8844 | psel5, | |
8845 | psel6, | |
8846 | psel7 | |
8847 | ); | |
8848 | input sel0; | |
8849 | input sel1; | |
8850 | input sel2; | |
8851 | input test; | |
8852 | output psel0; | |
8853 | output psel1; | |
8854 | output psel2; | |
8855 | output psel3; | |
8856 | output psel4; | |
8857 | output psel5; | |
8858 | output psel6; | |
8859 | output psel7; | |
8860 | ||
8861 | `ifdef LIB | |
8862 | assign psel0 = ~sel2 & ~sel1 & ~sel0 & test; | |
8863 | assign psel1 = ~sel2 & ~sel1 & sel0; | |
8864 | assign psel2 = ~sel2 & sel1 & ~sel0; | |
8865 | assign psel3 = ~sel2 & sel1 & sel0; | |
8866 | assign psel4 = sel2 & ~sel1 & ~sel0; | |
8867 | assign psel5 = sel2 & ~sel1 & sel0; | |
8868 | assign psel6 = sel2 & sel1 & ~sel0; | |
8869 | assign psel7 = sel2 & sel1 & sel0; | |
8870 | `endif | |
8871 | ||
8872 | endmodule | |
8873 | module cl_dp1_penc2_16x ( | |
8874 | sel0, | |
8875 | psel0, | |
8876 | psel1 | |
8877 | ); | |
8878 | input sel0; | |
8879 | output psel0; | |
8880 | output psel1; | |
8881 | ||
8882 | `ifdef LIB | |
8883 | assign psel0 = sel0; | |
8884 | assign psel1 = ~sel0; | |
8885 | `endif | |
8886 | ||
8887 | endmodule | |
8888 | module cl_dp1_penc2_32x ( | |
8889 | sel0, | |
8890 | psel0, | |
8891 | psel1 | |
8892 | ); | |
8893 | input sel0; | |
8894 | output psel0; | |
8895 | output psel1; | |
8896 | ||
8897 | `ifdef LIB | |
8898 | assign psel0 = sel0; | |
8899 | assign psel1 = ~sel0; | |
8900 | `endif | |
8901 | ||
8902 | endmodule | |
8903 | module cl_dp1_penc2_48x ( | |
8904 | sel0, | |
8905 | psel0, | |
8906 | psel1 | |
8907 | ); | |
8908 | input sel0; | |
8909 | output psel0; | |
8910 | output psel1; | |
8911 | ||
8912 | `ifdef LIB | |
8913 | assign psel0 = sel0; | |
8914 | assign psel1 = ~sel0; | |
8915 | `endif | |
8916 | ||
8917 | endmodule | |
8918 | module cl_dp1_penc2_64x ( | |
8919 | sel0, | |
8920 | psel0, | |
8921 | psel1 | |
8922 | ); | |
8923 | input sel0; | |
8924 | output psel0; | |
8925 | output psel1; | |
8926 | ||
8927 | `ifdef LIB | |
8928 | assign psel0 = sel0; | |
8929 | assign psel1 = ~sel0; | |
8930 | `endif | |
8931 | ||
8932 | endmodule | |
8933 | module cl_dp1_penc2_8x ( | |
8934 | sel0, | |
8935 | psel0, | |
8936 | psel1 | |
8937 | ); | |
8938 | input sel0; | |
8939 | output psel0; | |
8940 | output psel1; | |
8941 | ||
8942 | `ifdef LIB | |
8943 | assign psel0 = sel0; | |
8944 | assign psel1 = ~sel0; | |
8945 | `endif | |
8946 | ||
8947 | endmodule | |
8948 | module cl_dp1_penc3_16x ( | |
8949 | sel0, | |
8950 | sel1, | |
8951 | test, | |
8952 | psel0, | |
8953 | psel1, | |
8954 | psel2 | |
8955 | ); | |
8956 | input sel0; | |
8957 | input sel1; | |
8958 | input test; | |
8959 | output psel0; | |
8960 | output psel1; | |
8961 | output psel2; | |
8962 | ||
8963 | `ifdef LIB | |
8964 | assign psel0 = sel0; | |
8965 | assign psel1 = ~sel0 & sel1; | |
8966 | assign psel2 = ~sel0 & ~sel1 & test; | |
8967 | `endif | |
8968 | ||
8969 | endmodule | |
8970 | module cl_dp1_penc3_32x ( | |
8971 | sel0, | |
8972 | sel1, | |
8973 | test, | |
8974 | psel0, | |
8975 | psel1, | |
8976 | psel2 | |
8977 | ); | |
8978 | input sel0; | |
8979 | input sel1; | |
8980 | input test; | |
8981 | output psel0; | |
8982 | output psel1; | |
8983 | output psel2; | |
8984 | ||
8985 | `ifdef LIB | |
8986 | assign psel0 = sel0; | |
8987 | assign psel1 = ~sel0 & sel1; | |
8988 | assign psel2 = ~sel0 & ~sel1 & test; | |
8989 | `endif | |
8990 | ||
8991 | endmodule | |
8992 | module cl_dp1_penc3_48x ( | |
8993 | sel0, | |
8994 | sel1, | |
8995 | test, | |
8996 | psel0, | |
8997 | psel1, | |
8998 | psel2 | |
8999 | ); | |
9000 | input sel0; | |
9001 | input sel1; | |
9002 | input test; | |
9003 | output psel0; | |
9004 | output psel1; | |
9005 | output psel2; | |
9006 | ||
9007 | `ifdef LIB | |
9008 | assign psel0 = sel0; | |
9009 | assign psel1 = ~sel0 & sel1; | |
9010 | assign psel2 = ~sel0 & ~sel1 & test; | |
9011 | `endif | |
9012 | ||
9013 | endmodule | |
9014 | module cl_dp1_penc3_64x ( | |
9015 | sel0, | |
9016 | sel1, | |
9017 | test, | |
9018 | psel0, | |
9019 | psel1, | |
9020 | psel2 | |
9021 | ); | |
9022 | input sel0; | |
9023 | input sel1; | |
9024 | input test; | |
9025 | output psel0; | |
9026 | output psel1; | |
9027 | output psel2; | |
9028 | ||
9029 | `ifdef LIB | |
9030 | assign psel0 = sel0; | |
9031 | assign psel1 = ~sel0 & sel1; | |
9032 | assign psel2 = ~sel0 & ~sel1 & test; | |
9033 | `endif | |
9034 | ||
9035 | endmodule | |
9036 | module cl_dp1_penc3_8x ( | |
9037 | sel0, | |
9038 | sel1, | |
9039 | test, | |
9040 | psel0, | |
9041 | psel1, | |
9042 | psel2 | |
9043 | ); | |
9044 | input sel0; | |
9045 | input sel1; | |
9046 | input test; | |
9047 | output psel0; | |
9048 | output psel1; | |
9049 | output psel2; | |
9050 | ||
9051 | `ifdef LIB | |
9052 | assign psel0 = sel0; | |
9053 | assign psel1 = ~sel0 & sel1; | |
9054 | assign psel2 = ~sel0 & ~sel1 & test; | |
9055 | `endif | |
9056 | ||
9057 | endmodule | |
9058 | module cl_dp1_penc4_16x ( | |
9059 | sel0, | |
9060 | sel1, | |
9061 | sel2, | |
9062 | test, | |
9063 | psel0, | |
9064 | psel1, | |
9065 | psel2, | |
9066 | psel3 | |
9067 | ); | |
9068 | input sel0; | |
9069 | input sel1; | |
9070 | input sel2; | |
9071 | input test; | |
9072 | output psel0; | |
9073 | output psel1; | |
9074 | output psel2; | |
9075 | output psel3; | |
9076 | ||
9077 | `ifdef LIB | |
9078 | assign psel0 = sel0; | |
9079 | assign psel1 = ~sel0 & sel1 & test; | |
9080 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9081 | assign psel3 = ~sel0 & ~sel1 & ~sel2; | |
9082 | `endif | |
9083 | ||
9084 | endmodule | |
9085 | module cl_dp1_penc4_32x ( | |
9086 | sel0, | |
9087 | sel1, | |
9088 | sel2, | |
9089 | test, | |
9090 | psel0, | |
9091 | psel1, | |
9092 | psel2, | |
9093 | psel3 | |
9094 | ); | |
9095 | input sel0; | |
9096 | input sel1; | |
9097 | input sel2; | |
9098 | input test; | |
9099 | output psel0; | |
9100 | output psel1; | |
9101 | output psel2; | |
9102 | output psel3; | |
9103 | ||
9104 | `ifdef LIB | |
9105 | assign psel0 = sel0; | |
9106 | assign psel1 = ~sel0 & sel1 & test; | |
9107 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9108 | assign psel3 = ~sel0 & ~sel1 & ~sel2; | |
9109 | `endif | |
9110 | ||
9111 | endmodule | |
9112 | module cl_dp1_penc4_48x ( | |
9113 | sel0, | |
9114 | sel1, | |
9115 | sel2, | |
9116 | test, | |
9117 | psel0, | |
9118 | psel1, | |
9119 | psel2, | |
9120 | psel3 | |
9121 | ); | |
9122 | input sel0; | |
9123 | input sel1; | |
9124 | input sel2; | |
9125 | input test; | |
9126 | output psel0; | |
9127 | output psel1; | |
9128 | output psel2; | |
9129 | output psel3; | |
9130 | ||
9131 | `ifdef LIB | |
9132 | assign psel0 = sel0; | |
9133 | assign psel1 = ~sel0 & sel1 & test; | |
9134 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9135 | assign psel3 = ~sel0 & ~sel1 & ~sel2; | |
9136 | `endif | |
9137 | ||
9138 | endmodule | |
9139 | module cl_dp1_penc4_64x ( | |
9140 | sel0, | |
9141 | sel1, | |
9142 | sel2, | |
9143 | test, | |
9144 | psel0, | |
9145 | psel1, | |
9146 | psel2, | |
9147 | psel3 | |
9148 | ); | |
9149 | input sel0; | |
9150 | input sel1; | |
9151 | input sel2; | |
9152 | input test; | |
9153 | output psel0; | |
9154 | output psel1; | |
9155 | output psel2; | |
9156 | output psel3; | |
9157 | ||
9158 | `ifdef LIB | |
9159 | assign psel0 = sel0; | |
9160 | assign psel1 = ~sel0 & sel1 & test; | |
9161 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9162 | assign psel3 = ~sel0 & ~sel1 & ~sel2; | |
9163 | `endif | |
9164 | ||
9165 | endmodule | |
9166 | module cl_dp1_penc4_8x ( | |
9167 | sel0, | |
9168 | sel1, | |
9169 | sel2, | |
9170 | test, | |
9171 | psel0, | |
9172 | psel1, | |
9173 | psel2, | |
9174 | psel3 | |
9175 | ); | |
9176 | input sel0; | |
9177 | input sel1; | |
9178 | input sel2; | |
9179 | input test; | |
9180 | output psel0; | |
9181 | output psel1; | |
9182 | output psel2; | |
9183 | output psel3; | |
9184 | ||
9185 | `ifdef LIB | |
9186 | assign psel0 = sel0; | |
9187 | assign psel1 = ~sel0 & sel1 & test; | |
9188 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9189 | assign psel3 = ~sel0 & ~sel1 & ~sel2; | |
9190 | `endif | |
9191 | ||
9192 | endmodule | |
9193 | module cl_dp1_penc5_16x ( | |
9194 | sel0, | |
9195 | sel1, | |
9196 | sel2, | |
9197 | sel3, | |
9198 | test, | |
9199 | psel0, | |
9200 | psel1, | |
9201 | psel2, | |
9202 | psel3, | |
9203 | psel4 | |
9204 | ); | |
9205 | input sel0; | |
9206 | input sel1; | |
9207 | input sel2; | |
9208 | input sel3; | |
9209 | input test; | |
9210 | output psel0; | |
9211 | output psel1; | |
9212 | output psel2; | |
9213 | output psel3; | |
9214 | output psel4; | |
9215 | ||
9216 | `ifdef LIB | |
9217 | assign psel0 = sel0 & test; | |
9218 | assign psel1 = ~sel0 & sel1; | |
9219 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9220 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9221 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3; | |
9222 | `endif | |
9223 | ||
9224 | endmodule | |
9225 | module cl_dp1_penc5_32x ( | |
9226 | sel0, | |
9227 | sel1, | |
9228 | sel2, | |
9229 | sel3, | |
9230 | test, | |
9231 | psel0, | |
9232 | psel1, | |
9233 | psel2, | |
9234 | psel3, | |
9235 | psel4 | |
9236 | ); | |
9237 | input sel0; | |
9238 | input sel1; | |
9239 | input sel2; | |
9240 | input sel3; | |
9241 | input test; | |
9242 | output psel0; | |
9243 | output psel1; | |
9244 | output psel2; | |
9245 | output psel3; | |
9246 | output psel4; | |
9247 | ||
9248 | `ifdef LIB | |
9249 | assign psel0 = sel0 & test; | |
9250 | assign psel1 = ~sel0 & sel1; | |
9251 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9252 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9253 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3; | |
9254 | `endif | |
9255 | ||
9256 | endmodule | |
9257 | module cl_dp1_penc5_48x ( | |
9258 | sel0, | |
9259 | sel1, | |
9260 | sel2, | |
9261 | sel3, | |
9262 | test, | |
9263 | psel0, | |
9264 | psel1, | |
9265 | psel2, | |
9266 | psel3, | |
9267 | psel4 | |
9268 | ); | |
9269 | input sel0; | |
9270 | input sel1; | |
9271 | input sel2; | |
9272 | input sel3; | |
9273 | input test; | |
9274 | output psel0; | |
9275 | output psel1; | |
9276 | output psel2; | |
9277 | output psel3; | |
9278 | output psel4; | |
9279 | ||
9280 | `ifdef LIB | |
9281 | assign psel0 = sel0 & test; | |
9282 | assign psel1 = ~sel0 & sel1; | |
9283 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9284 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9285 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3; | |
9286 | `endif | |
9287 | ||
9288 | endmodule | |
9289 | module cl_dp1_penc5_64x ( | |
9290 | sel0, | |
9291 | sel1, | |
9292 | sel2, | |
9293 | sel3, | |
9294 | test, | |
9295 | psel0, | |
9296 | psel1, | |
9297 | psel2, | |
9298 | psel3, | |
9299 | psel4 | |
9300 | ); | |
9301 | input sel0; | |
9302 | input sel1; | |
9303 | input sel2; | |
9304 | input sel3; | |
9305 | input test; | |
9306 | output psel0; | |
9307 | output psel1; | |
9308 | output psel2; | |
9309 | output psel3; | |
9310 | output psel4; | |
9311 | ||
9312 | `ifdef LIB | |
9313 | assign psel0 = sel0 & test; | |
9314 | assign psel1 = ~sel0 & sel1; | |
9315 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9316 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9317 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3; | |
9318 | `endif | |
9319 | ||
9320 | endmodule | |
9321 | module cl_dp1_penc5_8x ( | |
9322 | sel0, | |
9323 | sel1, | |
9324 | sel2, | |
9325 | sel3, | |
9326 | test, | |
9327 | psel0, | |
9328 | psel1, | |
9329 | psel2, | |
9330 | psel3, | |
9331 | psel4 | |
9332 | ); | |
9333 | input sel0; | |
9334 | input sel1; | |
9335 | input sel2; | |
9336 | input sel3; | |
9337 | input test; | |
9338 | output psel0; | |
9339 | output psel1; | |
9340 | output psel2; | |
9341 | output psel3; | |
9342 | output psel4; | |
9343 | ||
9344 | `ifdef LIB | |
9345 | assign psel0 = sel0 & test; | |
9346 | assign psel1 = ~sel0 & sel1; | |
9347 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9348 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9349 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3; | |
9350 | `endif | |
9351 | ||
9352 | endmodule | |
9353 | module cl_dp1_penc6_16x ( | |
9354 | sel0, | |
9355 | sel1, | |
9356 | sel2, | |
9357 | sel3, | |
9358 | sel4, | |
9359 | test, | |
9360 | psel0, | |
9361 | psel1, | |
9362 | psel2, | |
9363 | psel3, | |
9364 | psel4, | |
9365 | psel5 | |
9366 | ); | |
9367 | input sel0; | |
9368 | input sel1; | |
9369 | input sel2; | |
9370 | input sel3; | |
9371 | input sel4; | |
9372 | input test; | |
9373 | output psel0; | |
9374 | output psel1; | |
9375 | output psel2; | |
9376 | output psel3; | |
9377 | output psel4; | |
9378 | output psel5; | |
9379 | ||
9380 | `ifdef LIB | |
9381 | assign psel0 = sel0; | |
9382 | assign psel1 = ~sel0 & sel1; | |
9383 | assign psel2 = ~sel0 & ~sel1 & sel2 & test; | |
9384 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9385 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9386 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4; | |
9387 | `endif | |
9388 | ||
9389 | endmodule | |
9390 | module cl_dp1_penc6_32x ( | |
9391 | sel0, | |
9392 | sel1, | |
9393 | sel2, | |
9394 | sel3, | |
9395 | sel4, | |
9396 | test, | |
9397 | psel0, | |
9398 | psel1, | |
9399 | psel2, | |
9400 | psel3, | |
9401 | psel4, | |
9402 | psel5 | |
9403 | ); | |
9404 | input sel0; | |
9405 | input sel1; | |
9406 | input sel2; | |
9407 | input sel3; | |
9408 | input sel4; | |
9409 | input test; | |
9410 | output psel0; | |
9411 | output psel1; | |
9412 | output psel2; | |
9413 | output psel3; | |
9414 | output psel4; | |
9415 | output psel5; | |
9416 | ||
9417 | `ifdef LIB | |
9418 | assign psel0 = sel0; | |
9419 | assign psel1 = ~sel0 & sel1; | |
9420 | assign psel2 = ~sel0 & ~sel1 & sel2 & test; | |
9421 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9422 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9423 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4; | |
9424 | `endif | |
9425 | ||
9426 | endmodule | |
9427 | module cl_dp1_penc6_48x ( | |
9428 | sel0, | |
9429 | sel1, | |
9430 | sel2, | |
9431 | sel3, | |
9432 | sel4, | |
9433 | test, | |
9434 | psel0, | |
9435 | psel1, | |
9436 | psel2, | |
9437 | psel3, | |
9438 | psel4, | |
9439 | psel5 | |
9440 | ); | |
9441 | input sel0; | |
9442 | input sel1; | |
9443 | input sel2; | |
9444 | input sel3; | |
9445 | input sel4; | |
9446 | input test; | |
9447 | output psel0; | |
9448 | output psel1; | |
9449 | output psel2; | |
9450 | output psel3; | |
9451 | output psel4; | |
9452 | output psel5; | |
9453 | ||
9454 | `ifdef LIB | |
9455 | assign psel0 = sel0; | |
9456 | assign psel1 = ~sel0 & sel1; | |
9457 | assign psel2 = ~sel0 & ~sel1 & sel2 & test; | |
9458 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9459 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9460 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4; | |
9461 | `endif | |
9462 | ||
9463 | endmodule | |
9464 | module cl_dp1_penc6_64x ( | |
9465 | sel0, | |
9466 | sel1, | |
9467 | sel2, | |
9468 | sel3, | |
9469 | sel4, | |
9470 | test, | |
9471 | psel0, | |
9472 | psel1, | |
9473 | psel2, | |
9474 | psel3, | |
9475 | psel4, | |
9476 | psel5 | |
9477 | ); | |
9478 | input sel0; | |
9479 | input sel1; | |
9480 | input sel2; | |
9481 | input sel3; | |
9482 | input sel4; | |
9483 | input test; | |
9484 | output psel0; | |
9485 | output psel1; | |
9486 | output psel2; | |
9487 | output psel3; | |
9488 | output psel4; | |
9489 | output psel5; | |
9490 | ||
9491 | `ifdef LIB | |
9492 | assign psel0 = sel0; | |
9493 | assign psel1 = ~sel0 & sel1; | |
9494 | assign psel2 = ~sel0 & ~sel1 & sel2 & test; | |
9495 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9496 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9497 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4; | |
9498 | `endif | |
9499 | ||
9500 | endmodule | |
9501 | module cl_dp1_penc6_8x ( | |
9502 | sel0, | |
9503 | sel1, | |
9504 | sel2, | |
9505 | sel3, | |
9506 | sel4, | |
9507 | test, | |
9508 | psel0, | |
9509 | psel1, | |
9510 | psel2, | |
9511 | psel3, | |
9512 | psel4, | |
9513 | psel5 | |
9514 | ); | |
9515 | input sel0; | |
9516 | input sel1; | |
9517 | input sel2; | |
9518 | input sel3; | |
9519 | input sel4; | |
9520 | input test; | |
9521 | output psel0; | |
9522 | output psel1; | |
9523 | output psel2; | |
9524 | output psel3; | |
9525 | output psel4; | |
9526 | output psel5; | |
9527 | ||
9528 | `ifdef LIB | |
9529 | assign psel0 = sel0; | |
9530 | assign psel1 = ~sel0 & sel1; | |
9531 | assign psel2 = ~sel0 & ~sel1 & sel2 & test; | |
9532 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9533 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9534 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4; | |
9535 | `endif | |
9536 | ||
9537 | endmodule | |
9538 | module cl_dp1_penc7_16x ( | |
9539 | sel0, | |
9540 | sel1, | |
9541 | sel2, | |
9542 | sel3, | |
9543 | sel4, | |
9544 | sel5, | |
9545 | test, | |
9546 | psel0, | |
9547 | psel1, | |
9548 | psel2, | |
9549 | psel3, | |
9550 | psel4, | |
9551 | psel5, | |
9552 | psel6 | |
9553 | ); | |
9554 | input sel0; | |
9555 | input sel1; | |
9556 | input sel2; | |
9557 | input sel3; | |
9558 | input sel4; | |
9559 | input sel5; | |
9560 | input test; | |
9561 | output psel0; | |
9562 | output psel1; | |
9563 | output psel2; | |
9564 | output psel3; | |
9565 | output psel4; | |
9566 | output psel5; | |
9567 | output psel6; | |
9568 | ||
9569 | `ifdef LIB | |
9570 | assign psel0 = sel0; | |
9571 | assign psel1 = ~sel0 & sel1 & test; | |
9572 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9573 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9574 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9575 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9576 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5; | |
9577 | `endif | |
9578 | ||
9579 | endmodule | |
9580 | module cl_dp1_penc7_32x ( | |
9581 | sel0, | |
9582 | sel1, | |
9583 | sel2, | |
9584 | sel3, | |
9585 | sel4, | |
9586 | sel5, | |
9587 | test, | |
9588 | psel0, | |
9589 | psel1, | |
9590 | psel2, | |
9591 | psel3, | |
9592 | psel4, | |
9593 | psel5, | |
9594 | psel6 | |
9595 | ); | |
9596 | input sel0; | |
9597 | input sel1; | |
9598 | input sel2; | |
9599 | input sel3; | |
9600 | input sel4; | |
9601 | input sel5; | |
9602 | input test; | |
9603 | output psel0; | |
9604 | output psel1; | |
9605 | output psel2; | |
9606 | output psel3; | |
9607 | output psel4; | |
9608 | output psel5; | |
9609 | output psel6; | |
9610 | ||
9611 | `ifdef LIB | |
9612 | assign psel0 = sel0; | |
9613 | assign psel1 = ~sel0 & sel1 & test; | |
9614 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9615 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9616 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9617 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9618 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5; | |
9619 | `endif | |
9620 | ||
9621 | endmodule | |
9622 | module cl_dp1_penc7_48x ( | |
9623 | sel0, | |
9624 | sel1, | |
9625 | sel2, | |
9626 | sel3, | |
9627 | sel4, | |
9628 | sel5, | |
9629 | test, | |
9630 | psel0, | |
9631 | psel1, | |
9632 | psel2, | |
9633 | psel3, | |
9634 | psel4, | |
9635 | psel5, | |
9636 | psel6 | |
9637 | ); | |
9638 | input sel0; | |
9639 | input sel1; | |
9640 | input sel2; | |
9641 | input sel3; | |
9642 | input sel4; | |
9643 | input sel5; | |
9644 | input test; | |
9645 | output psel0; | |
9646 | output psel1; | |
9647 | output psel2; | |
9648 | output psel3; | |
9649 | output psel4; | |
9650 | output psel5; | |
9651 | output psel6; | |
9652 | ||
9653 | `ifdef LIB | |
9654 | assign psel0 = sel0; | |
9655 | assign psel1 = ~sel0 & sel1 & test; | |
9656 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9657 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9658 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9659 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9660 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5; | |
9661 | `endif | |
9662 | ||
9663 | endmodule | |
9664 | module cl_dp1_penc7_64x ( | |
9665 | sel0, | |
9666 | sel1, | |
9667 | sel2, | |
9668 | sel3, | |
9669 | sel4, | |
9670 | sel5, | |
9671 | test, | |
9672 | psel0, | |
9673 | psel1, | |
9674 | psel2, | |
9675 | psel3, | |
9676 | psel4, | |
9677 | psel5, | |
9678 | psel6 | |
9679 | ); | |
9680 | input sel0; | |
9681 | input sel1; | |
9682 | input sel2; | |
9683 | input sel3; | |
9684 | input sel4; | |
9685 | input sel5; | |
9686 | input test; | |
9687 | output psel0; | |
9688 | output psel1; | |
9689 | output psel2; | |
9690 | output psel3; | |
9691 | output psel4; | |
9692 | output psel5; | |
9693 | output psel6; | |
9694 | ||
9695 | `ifdef LIB | |
9696 | assign psel0 = sel0; | |
9697 | assign psel1 = ~sel0 & sel1 & test; | |
9698 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9699 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9700 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9701 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9702 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5; | |
9703 | `endif | |
9704 | ||
9705 | endmodule | |
9706 | module cl_dp1_penc7_8x ( | |
9707 | sel0, | |
9708 | sel1, | |
9709 | sel2, | |
9710 | sel3, | |
9711 | sel4, | |
9712 | sel5, | |
9713 | test, | |
9714 | psel0, | |
9715 | psel1, | |
9716 | psel2, | |
9717 | psel3, | |
9718 | psel4, | |
9719 | psel5, | |
9720 | psel6 | |
9721 | ); | |
9722 | input sel0; | |
9723 | input sel1; | |
9724 | input sel2; | |
9725 | input sel3; | |
9726 | input sel4; | |
9727 | input sel5; | |
9728 | input test; | |
9729 | output psel0; | |
9730 | output psel1; | |
9731 | output psel2; | |
9732 | output psel3; | |
9733 | output psel4; | |
9734 | output psel5; | |
9735 | output psel6; | |
9736 | ||
9737 | `ifdef LIB | |
9738 | assign psel0 = sel0; | |
9739 | assign psel1 = ~sel0 & sel1 & test; | |
9740 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9741 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9742 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9743 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9744 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5; | |
9745 | `endif | |
9746 | ||
9747 | endmodule | |
9748 | module cl_dp1_penc8_16x ( | |
9749 | sel0, | |
9750 | sel1, | |
9751 | sel2, | |
9752 | sel3, | |
9753 | sel4, | |
9754 | sel5, | |
9755 | sel6, | |
9756 | test, | |
9757 | psel0, | |
9758 | psel1, | |
9759 | psel2, | |
9760 | psel3, | |
9761 | psel4, | |
9762 | psel5, | |
9763 | psel6, | |
9764 | psel7 | |
9765 | ); | |
9766 | input sel0; | |
9767 | input sel1; | |
9768 | input sel2; | |
9769 | input sel3; | |
9770 | input sel4; | |
9771 | input sel5; | |
9772 | input sel6; | |
9773 | input test; | |
9774 | output psel0; | |
9775 | output psel1; | |
9776 | output psel2; | |
9777 | output psel3; | |
9778 | output psel4; | |
9779 | output psel5; | |
9780 | output psel6; | |
9781 | output psel7; | |
9782 | ||
9783 | `ifdef LIB | |
9784 | assign psel0 = sel0; | |
9785 | assign psel1 = ~sel0 & sel1 & test; | |
9786 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9787 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9788 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9789 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9790 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6; | |
9791 | assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6; | |
9792 | `endif | |
9793 | ||
9794 | endmodule | |
9795 | module cl_dp1_penc8_32x ( | |
9796 | sel0, | |
9797 | sel1, | |
9798 | sel2, | |
9799 | sel3, | |
9800 | sel4, | |
9801 | sel5, | |
9802 | sel6, | |
9803 | test, | |
9804 | psel0, | |
9805 | psel1, | |
9806 | psel2, | |
9807 | psel3, | |
9808 | psel4, | |
9809 | psel5, | |
9810 | psel6, | |
9811 | psel7 | |
9812 | ); | |
9813 | input sel0; | |
9814 | input sel1; | |
9815 | input sel2; | |
9816 | input sel3; | |
9817 | input sel4; | |
9818 | input sel5; | |
9819 | input sel6; | |
9820 | input test; | |
9821 | output psel0; | |
9822 | output psel1; | |
9823 | output psel2; | |
9824 | output psel3; | |
9825 | output psel4; | |
9826 | output psel5; | |
9827 | output psel6; | |
9828 | output psel7; | |
9829 | ||
9830 | `ifdef LIB | |
9831 | assign psel0 = sel0; | |
9832 | assign psel1 = ~sel0 & sel1 & test; | |
9833 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9834 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9835 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9836 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9837 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6; | |
9838 | assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6; | |
9839 | `endif | |
9840 | ||
9841 | endmodule | |
9842 | module cl_dp1_penc8_48x ( | |
9843 | sel0, | |
9844 | sel1, | |
9845 | sel2, | |
9846 | sel3, | |
9847 | sel4, | |
9848 | sel5, | |
9849 | sel6, | |
9850 | test, | |
9851 | psel0, | |
9852 | psel1, | |
9853 | psel2, | |
9854 | psel3, | |
9855 | psel4, | |
9856 | psel5, | |
9857 | psel6, | |
9858 | psel7 | |
9859 | ); | |
9860 | input sel0; | |
9861 | input sel1; | |
9862 | input sel2; | |
9863 | input sel3; | |
9864 | input sel4; | |
9865 | input sel5; | |
9866 | input sel6; | |
9867 | input test; | |
9868 | output psel0; | |
9869 | output psel1; | |
9870 | output psel2; | |
9871 | output psel3; | |
9872 | output psel4; | |
9873 | output psel5; | |
9874 | output psel6; | |
9875 | output psel7; | |
9876 | ||
9877 | `ifdef LIB | |
9878 | assign psel0 = sel0; | |
9879 | assign psel1 = ~sel0 & sel1 & test; | |
9880 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9881 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9882 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9883 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9884 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6; | |
9885 | assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6; | |
9886 | `endif | |
9887 | ||
9888 | endmodule | |
9889 | module cl_dp1_penc8_64x ( | |
9890 | sel0, | |
9891 | sel1, | |
9892 | sel2, | |
9893 | sel3, | |
9894 | sel4, | |
9895 | sel5, | |
9896 | sel6, | |
9897 | test, | |
9898 | psel0, | |
9899 | psel1, | |
9900 | psel2, | |
9901 | psel3, | |
9902 | psel4, | |
9903 | psel5, | |
9904 | psel6, | |
9905 | psel7 | |
9906 | ); | |
9907 | input sel0; | |
9908 | input sel1; | |
9909 | input sel2; | |
9910 | input sel3; | |
9911 | input sel4; | |
9912 | input sel5; | |
9913 | input sel6; | |
9914 | input test; | |
9915 | output psel0; | |
9916 | output psel1; | |
9917 | output psel2; | |
9918 | output psel3; | |
9919 | output psel4; | |
9920 | output psel5; | |
9921 | output psel6; | |
9922 | output psel7; | |
9923 | ||
9924 | `ifdef LIB | |
9925 | assign psel0 = sel0; | |
9926 | assign psel1 = ~sel0 & sel1 & test; | |
9927 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9928 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9929 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9930 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9931 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6; | |
9932 | assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6; | |
9933 | `endif | |
9934 | ||
9935 | endmodule | |
9936 | module cl_dp1_penc8_8x ( | |
9937 | sel0, | |
9938 | sel1, | |
9939 | sel2, | |
9940 | sel3, | |
9941 | sel4, | |
9942 | sel5, | |
9943 | sel6, | |
9944 | test, | |
9945 | psel0, | |
9946 | psel1, | |
9947 | psel2, | |
9948 | psel3, | |
9949 | psel4, | |
9950 | psel5, | |
9951 | psel6, | |
9952 | psel7 | |
9953 | ); | |
9954 | input sel0; | |
9955 | input sel1; | |
9956 | input sel2; | |
9957 | input sel3; | |
9958 | input sel4; | |
9959 | input sel5; | |
9960 | input sel6; | |
9961 | input test; | |
9962 | output psel0; | |
9963 | output psel1; | |
9964 | output psel2; | |
9965 | output psel3; | |
9966 | output psel4; | |
9967 | output psel5; | |
9968 | output psel6; | |
9969 | output psel7; | |
9970 | ||
9971 | `ifdef LIB | |
9972 | assign psel0 = sel0; | |
9973 | assign psel1 = ~sel0 & sel1 & test; | |
9974 | assign psel2 = ~sel0 & ~sel1 & sel2; | |
9975 | assign psel3 = ~sel0 & ~sel1 & ~sel2 & sel3; | |
9976 | assign psel4 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & sel4; | |
9977 | assign psel5 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & sel5; | |
9978 | assign psel6 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & sel6; | |
9979 | assign psel7 = ~sel0 & ~sel1 & ~sel2 & ~sel3 & ~sel4 & ~sel5 & ~sel6; | |
9980 | `endif | |
9981 | ||
9982 | endmodule | |
9983 | module cl_dp1_prty16_8x ( | |
9984 | in, | |
9985 | out | |
9986 | ); | |
9987 | input [15:0] in; | |
9988 | output out; | |
9989 | ||
9990 | ||
9991 | `ifdef LIB | |
9992 | assign out = ^in[15:0]; | |
9993 | `endif | |
9994 | ||
9995 | endmodule | |
9996 | module cl_dp1_prty32_8x ( | |
9997 | in, | |
9998 | out | |
9999 | ); | |
10000 | input [31:0] in; | |
10001 | output out; | |
10002 | ||
10003 | `ifdef LIB | |
10004 | assign out = ^in[31:0]; | |
10005 | `endif | |
10006 | ||
10007 | endmodule | |
10008 | module cl_dp1_prty4_8x ( | |
10009 | in, | |
10010 | out | |
10011 | ); | |
10012 | input [3:0] in; | |
10013 | output out; | |
10014 | ||
10015 | `ifdef LIB | |
10016 | assign out = ^in[3:0]; | |
10017 | `endif | |
10018 | ||
10019 | endmodule | |
10020 | module cl_dp1_prty8_8x ( | |
10021 | in, | |
10022 | out | |
10023 | ); | |
10024 | input [7:0] in; | |
10025 | output out; | |
10026 | ||
10027 | `ifdef LIB | |
10028 | assign out = ^in[7:0]; | |
10029 | `endif | |
10030 | ||
10031 | endmodule | |
10032 | ||
10033 | module cl_dp1_zero12_12x ( | |
10034 | in, | |
10035 | out | |
10036 | ); | |
10037 | ||
10038 | input [11:0] in; | |
10039 | output out; | |
10040 | ||
10041 | `ifdef LIB | |
10042 | ||
10043 | assign out = ( in[11:0] == 12'b0); | |
10044 | ||
10045 | `endif | |
10046 | ||
10047 | ||
10048 | endmodule | |
10049 | module cl_dp1_zero16_12x ( | |
10050 | in, | |
10051 | out | |
10052 | ); | |
10053 | ||
10054 | input [15:0] in; | |
10055 | output out; | |
10056 | ||
10057 | `ifdef LIB | |
10058 | ||
10059 | assign out = ( in[15:0] == 16'b0); | |
10060 | ||
10061 | `endif | |
10062 | ||
10063 | ||
10064 | endmodule | |
10065 | ||
10066 | module cl_dp1_zero32_12x ( | |
10067 | in, | |
10068 | out | |
10069 | ); | |
10070 | ||
10071 | input [31:0] in; | |
10072 | output out; | |
10073 | ||
10074 | `ifdef LIB | |
10075 | ||
10076 | assign out = ( in[31:0] == 32'b0); | |
10077 | ||
10078 | `endif | |
10079 | ||
10080 | ||
10081 | endmodule | |
10082 | ||
10083 | module cl_dp1_zero4_12x ( | |
10084 | in, | |
10085 | out | |
10086 | ); | |
10087 | ||
10088 | input [3:0] in; | |
10089 | output out; | |
10090 | ||
10091 | `ifdef LIB | |
10092 | ||
10093 | assign out = ( in[3:0] == 4'b0); | |
10094 | ||
10095 | `endif | |
10096 | ||
10097 | ||
10098 | endmodule | |
10099 | module cl_dp1_zero64_12x ( | |
10100 | in, | |
10101 | out | |
10102 | ); | |
10103 | ||
10104 | input [63:0] in; | |
10105 | output out; | |
10106 | ||
10107 | `ifdef LIB | |
10108 | ||
10109 | assign out = ( in[63:0] == 64'b0); | |
10110 | ||
10111 | `endif | |
10112 | ||
10113 | ||
10114 | endmodule | |
10115 | ||
10116 | module cl_dp1_zero8_12x ( | |
10117 | in, | |
10118 | out | |
10119 | ); | |
10120 | ||
10121 | input [7:0] in; | |
10122 | output out; | |
10123 | ||
10124 | `ifdef LIB | |
10125 | ||
10126 | assign out = ( in[7:0] == 8'b0); | |
10127 | ||
10128 | `endif | |
10129 | ||
10130 | ||
10131 | endmodule | |
10132 | ||
10133 | ||
10134 | module cl_dp1_zdt64_8x( | |
10135 | din0, | |
10136 | din1, | |
10137 | cin, | |
10138 | zdt_z64_, | |
10139 | zdt_z32_ | |
10140 | ); | |
10141 | ||
10142 | input [63:0] din0; | |
10143 | input [63:0] din1; | |
10144 | input cin; | |
10145 | ||
10146 | output zdt_z64_; | |
10147 | output zdt_z32_; | |
10148 | ||
10149 | wire [63:0] p; | |
10150 | wire [62:0] k; | |
10151 | wire [63:0] z; | |
10152 | wire zero_detect32; | |
10153 | wire zero_detect64; | |
10154 | ||
10155 | `ifdef LIB | |
10156 | ||
10157 | ||
10158 | ||
10159 | assign p[63:0] = din0[63:0] ^ din1[63:0]; | |
10160 | assign k[62:0] = ~din0[62:0] & ~din1[62:0]; | |
10161 | ||
10162 | assign z[63:1] = p[63:1] ^ k[62:0]; | |
10163 | assign z[0] = p[0] ^ ~cin; | |
10164 | ||
10165 | assign zero_detect32 = & z[31:0]; | |
10166 | assign zero_detect64 = & z[63:0]; | |
10167 | ||
10168 | assign zdt_z32_ = ~zero_detect32; | |
10169 | assign zdt_z64_ = ~zero_detect64; | |
10170 | ||
10171 | `endif | |
10172 | ||
10173 | ||
10174 | endmodule | |
10175 | module cl_dp1_ccxhdr ( | |
10176 | l2clk, | |
10177 | pce0, | |
10178 | pce1, | |
10179 | pce_ov, | |
10180 | stop, | |
10181 | siclk_in, | |
10182 | soclk_in, | |
10183 | siclk_out, | |
10184 | soclk_out, | |
10185 | l1clk0, | |
10186 | l1clk1, | |
10187 | se, | |
10188 | si, | |
10189 | so, | |
10190 | l1clk, | |
10191 | grant_a, | |
10192 | grant_x, | |
10193 | qsel0, | |
10194 | qsel0_buf, | |
10195 | shift, | |
10196 | shift_buf | |
10197 | ); | |
10198 | ||
10199 | input l2clk; | |
10200 | input pce0; | |
10201 | input pce1; | |
10202 | input pce_ov; | |
10203 | input stop; | |
10204 | input siclk_in; | |
10205 | input soclk_in; | |
10206 | ||
10207 | output siclk_out; | |
10208 | output soclk_out; | |
10209 | output l1clk0; | |
10210 | output l1clk1; | |
10211 | ||
10212 | input l1clk; | |
10213 | input se; | |
10214 | input si; | |
10215 | input grant_a; | |
10216 | input qsel0; | |
10217 | input shift; | |
10218 | output so; | |
10219 | ||
10220 | output grant_x; | |
10221 | output qsel0_buf; | |
10222 | output shift_buf; | |
10223 | ||
10224 | wire siclk_out_unused; | |
10225 | wire soclk_out_unused; | |
10226 | ||
10227 | cl_dp1_ccx_l1hdr_16x hdr0 ( | |
10228 | .l2clk(l2clk), | |
10229 | .se(se), | |
10230 | .pce(pce0), | |
10231 | .aclk(siclk_in), | |
10232 | .bclk(soclk_in), | |
10233 | .siclk_out(siclk_out), | |
10234 | .soclk_out(soclk_out), | |
10235 | .l1clk(l1clk0), | |
10236 | .pce_ov(pce_ov), | |
10237 | .stop(stop) | |
10238 | ); | |
10239 | ||
10240 | cl_dp1_ccx_l1hdr_16x hdr1 ( | |
10241 | .l2clk(l2clk), | |
10242 | .se(se), | |
10243 | .pce(pce1), | |
10244 | .aclk(siclk_in), | |
10245 | .bclk(soclk_in), | |
10246 | .siclk_out(siclk_out_unused), | |
10247 | .soclk_out(soclk_out_unused), | |
10248 | .l1clk(l1clk1), | |
10249 | .pce_ov(pce_ov), | |
10250 | .stop(stop) | |
10251 | ); | |
10252 | ||
10253 | cl_dp1_ccx_msff_16x msff1 ( | |
10254 | .l1clk(l1clk), | |
10255 | .siclk(siclk_out), | |
10256 | .soclk(soclk_out), | |
10257 | .d(grant_a), | |
10258 | .si(si), | |
10259 | .so(so), | |
10260 | .q(grant_x) | |
10261 | ); | |
10262 | ||
10263 | assign qsel0_buf = qsel0; | |
10264 | assign shift_buf = shift; | |
10265 | ||
10266 | ||
10267 | endmodule // cl_dp1_ccxhdr | |
10268 | ||
10269 | module cl_dp1_ccx_mac_a ( | |
10270 | l1clk0, | |
10271 | l1clk1, | |
10272 | siclk, | |
10273 | soclk, | |
10274 | grant_x, | |
10275 | data_a, | |
10276 | data_x_l, | |
10277 | qsel0_buf, | |
10278 | shift_buf, | |
10279 | si, | |
10280 | so | |
10281 | ); | |
10282 | ||
10283 | input l1clk0; | |
10284 | input l1clk1; | |
10285 | input siclk; | |
10286 | input soclk; | |
10287 | input grant_x; | |
10288 | input data_a; | |
10289 | ||
10290 | input qsel0_buf; | |
10291 | input shift_buf; | |
10292 | ||
10293 | output data_x_l; | |
10294 | ||
10295 | input si; | |
10296 | output so; | |
10297 | ||
10298 | wire so1; | |
10299 | wire q1; | |
10300 | wire q0; | |
10301 | wire q0_in; | |
10302 | ||
10303 | cl_dp1_ccx_msff_4x msff1 ( | |
10304 | .l1clk(l1clk1), | |
10305 | .siclk(siclk), | |
10306 | .soclk(soclk), | |
10307 | .d(data_a), | |
10308 | .si(si), | |
10309 | .so(so1), | |
10310 | .q(q1) | |
10311 | ); | |
10312 | ||
10313 | cl_dp1_ccx_aomux2_4x mux1( | |
10314 | .in0(data_a), | |
10315 | .in1(q1), | |
10316 | .sel0(qsel0_buf), | |
10317 | .sel1(shift_buf), | |
10318 | .out(q0_in) | |
10319 | ); | |
10320 | ||
10321 | cl_dp1_ccx_msff_4x msff0 ( | |
10322 | .l1clk(l1clk0), | |
10323 | .siclk(siclk), | |
10324 | .soclk(soclk), | |
10325 | .d(q0_in), | |
10326 | .si(so1), | |
10327 | .so(so), | |
10328 | .q(q0) | |
10329 | ); | |
10330 | ||
10331 | cl_dp1_ccx_nand2_4x nand0( | |
10332 | .in0(q0), | |
10333 | .in1(grant_x), | |
10334 | .out(data_x_l) | |
10335 | ); | |
10336 | ||
10337 | endmodule // cl_dp1_ccx_mac_a | |
10338 | ||
10339 | module cl_dp1_ccx_mac_b ( | |
10340 | l1clk0, | |
10341 | l1clk1, | |
10342 | siclk, | |
10343 | soclk, | |
10344 | grant_x, | |
10345 | data_a, | |
10346 | data_prev_x_l, | |
10347 | data_x_l, | |
10348 | qsel0_buf, | |
10349 | shift_buf, | |
10350 | si, | |
10351 | so | |
10352 | ); | |
10353 | ||
10354 | input l1clk0; | |
10355 | input l1clk1; | |
10356 | input siclk; | |
10357 | input soclk; | |
10358 | input grant_x; | |
10359 | input data_a; | |
10360 | input data_prev_x_l; | |
10361 | ||
10362 | input qsel0_buf; | |
10363 | input shift_buf; | |
10364 | ||
10365 | output data_x_l; | |
10366 | ||
10367 | input si; | |
10368 | output so; | |
10369 | ||
10370 | wire so1; | |
10371 | wire q1; | |
10372 | wire q0; | |
10373 | wire q0_in; | |
10374 | wire x4; | |
10375 | wire x5; | |
10376 | ||
10377 | ||
10378 | cl_dp1_ccx_msff_4x msff1 ( | |
10379 | .l1clk(l1clk1), | |
10380 | .siclk(siclk), | |
10381 | .soclk(soclk), | |
10382 | .d(data_a), | |
10383 | .si(si), | |
10384 | .so(so1), | |
10385 | .q(q1) | |
10386 | ); | |
10387 | ||
10388 | cl_dp1_ccx_aomux2_4x mux1( | |
10389 | .in0(data_a), | |
10390 | .in1(q1), | |
10391 | .sel0(qsel0_buf), | |
10392 | .sel1(shift_buf), | |
10393 | .out(q0_in) | |
10394 | ); | |
10395 | ||
10396 | cl_dp1_ccx_msff_4x msff0 ( | |
10397 | .l1clk(l1clk0), | |
10398 | .siclk(siclk), | |
10399 | .soclk(soclk), | |
10400 | .d(q0_in), | |
10401 | .si(so1), | |
10402 | .so(so), | |
10403 | .q(q0) | |
10404 | ); | |
10405 | ||
10406 | cl_dp1_ccx_nand2_4x nand0( | |
10407 | .in0(q0), | |
10408 | .in1(grant_x), | |
10409 | .out(x4) | |
10410 | ); | |
10411 | ||
10412 | cl_dp1_ccx_nand2_12x nand1( | |
10413 | .in0(x4), | |
10414 | .in1(data_prev_x_l), | |
10415 | .out(x5) | |
10416 | ); | |
10417 | ||
10418 | cl_dp1_ccx_inv_32x inv0( | |
10419 | .in(x5), | |
10420 | .out(data_x_l) | |
10421 | ); | |
10422 | ||
10423 | endmodule // cl_dp1_ccx_mac_b | |
10424 | ||
10425 | module cl_dp1_ccx_mac_c ( | |
10426 | l1clk0, | |
10427 | l1clk1, | |
10428 | siclk, | |
10429 | soclk, | |
10430 | grant_x, | |
10431 | data_a, | |
10432 | data_crit_x_l, | |
10433 | data_ncrit_x_l, | |
10434 | data_x_l, | |
10435 | qsel0_buf, | |
10436 | shift_buf, | |
10437 | si, | |
10438 | so | |
10439 | ); | |
10440 | ||
10441 | input l1clk0; | |
10442 | input l1clk1; | |
10443 | input siclk; | |
10444 | input soclk; | |
10445 | input grant_x; | |
10446 | input data_a; | |
10447 | input data_crit_x_l; | |
10448 | input data_ncrit_x_l; | |
10449 | ||
10450 | input qsel0_buf; | |
10451 | input shift_buf; | |
10452 | ||
10453 | output data_x_l; | |
10454 | ||
10455 | input si; | |
10456 | output so; | |
10457 | ||
10458 | wire so1; | |
10459 | wire q1; | |
10460 | wire q0; | |
10461 | wire q0_in; | |
10462 | wire x4; | |
10463 | wire x5; | |
10464 | ||
10465 | ||
10466 | cl_dp1_ccx_msff_4x msff1 ( | |
10467 | .l1clk(l1clk1), | |
10468 | .siclk(siclk), | |
10469 | .soclk(soclk), | |
10470 | .d(data_a), | |
10471 | .si(si), | |
10472 | .so(so1), | |
10473 | .q(q1) | |
10474 | ); | |
10475 | ||
10476 | cl_dp1_ccx_aomux2_4x mux1( | |
10477 | .in0(data_a), | |
10478 | .in1(q1), | |
10479 | .sel0(qsel0_buf), | |
10480 | .sel1(shift_buf), | |
10481 | .out(q0_in) | |
10482 | ); | |
10483 | ||
10484 | cl_dp1_ccx_msff_4x msff0 ( | |
10485 | .l1clk(l1clk0), | |
10486 | .siclk(siclk), | |
10487 | .soclk(soclk), | |
10488 | .d(q0_in), | |
10489 | .si(so1), | |
10490 | .so(so), | |
10491 | .q(q0) | |
10492 | ); | |
10493 | ||
10494 | cl_dp1_ccx_nand2_4x nand0( | |
10495 | .in0(q0), | |
10496 | .in1(grant_x), | |
10497 | .out(x4) | |
10498 | ); | |
10499 | ||
10500 | cl_dp1_ccx_nand3_12x nand1( | |
10501 | .in0(x4), | |
10502 | .in1(data_ncrit_x_l), | |
10503 | .in2(data_crit_x_l), | |
10504 | .out(x5) | |
10505 | ); | |
10506 | ||
10507 | cl_dp1_ccx_inva_32x inv0( | |
10508 | .in(x5), | |
10509 | .out(data_x_l) | |
10510 | ); | |
10511 | ||
10512 | endmodule // cl_dp1_ccx_mac_c | |
10513 | ||
10514 | module cl_dp1_ccx_mac_b2 ( | |
10515 | l1clk0, | |
10516 | l1clk1, | |
10517 | siclk, | |
10518 | soclk, | |
10519 | grant_x, | |
10520 | data_a, | |
10521 | data_prev_x_l, | |
10522 | data_x_l, | |
10523 | qsel0_buf, | |
10524 | shift_buf, | |
10525 | si, | |
10526 | so | |
10527 | ); | |
10528 | ||
10529 | input l1clk0; | |
10530 | input l1clk1; | |
10531 | input siclk; | |
10532 | input soclk; | |
10533 | input grant_x; | |
10534 | input data_a; | |
10535 | input data_prev_x_l; | |
10536 | ||
10537 | input qsel0_buf; | |
10538 | input shift_buf; | |
10539 | ||
10540 | output data_x_l; | |
10541 | ||
10542 | input si; | |
10543 | output so; | |
10544 | ||
10545 | wire so1; | |
10546 | wire q1; | |
10547 | wire q0; | |
10548 | wire q0_in; | |
10549 | wire x4; | |
10550 | wire x5; | |
10551 | ||
10552 | ||
10553 | cl_dp1_ccx_msff_4x msff1 ( | |
10554 | .l1clk(l1clk1), | |
10555 | .siclk(siclk), | |
10556 | .soclk(soclk), | |
10557 | .d(data_a), | |
10558 | .si(si), | |
10559 | .so(so1), | |
10560 | .q(q1) | |
10561 | ); | |
10562 | ||
10563 | cl_dp1_ccx_aomux2_4x mux1( | |
10564 | .in0(data_a), | |
10565 | .in1(q1), | |
10566 | .sel0(qsel0_buf), | |
10567 | .sel1(shift_buf), | |
10568 | .out(q0_in) | |
10569 | ); | |
10570 | ||
10571 | cl_dp1_ccx_msff_4x msff0 ( | |
10572 | .l1clk(l1clk0), | |
10573 | .siclk(siclk), | |
10574 | .soclk(soclk), | |
10575 | .d(q0_in), | |
10576 | .si(so1), | |
10577 | .so(so), | |
10578 | .q(q0) | |
10579 | ); | |
10580 | ||
10581 | cl_dp1_ccx_nand2_4x nand0( | |
10582 | .in0(q0), | |
10583 | .in1(grant_x), | |
10584 | .out(x4) | |
10585 | ); | |
10586 | ||
10587 | cl_dp1_ccx_nand2_12x nand1( | |
10588 | .in0(x4), | |
10589 | .in1(data_prev_x_l), | |
10590 | .out(x5) | |
10591 | ); | |
10592 | ||
10593 | cl_dp1_ccx_inva_32x inv0( | |
10594 | .in(x5), | |
10595 | .out(data_x_l) | |
10596 | ); | |
10597 | ||
10598 | endmodule // cl_dp1_ccx_mac_b2 | |
10599 | ||
10600 | module cl_dp1_ccx_mac_c2 ( | |
10601 | l1clk0, | |
10602 | l1clk1, | |
10603 | siclk, | |
10604 | soclk, | |
10605 | grant_x, | |
10606 | data_a, | |
10607 | data_crit_x_l, | |
10608 | data_ncrit_x_l, | |
10609 | data_x_l, | |
10610 | qsel0_buf, | |
10611 | shift_buf, | |
10612 | si, | |
10613 | so | |
10614 | ); | |
10615 | ||
10616 | input l1clk0; | |
10617 | input l1clk1; | |
10618 | input siclk; | |
10619 | input soclk; | |
10620 | input grant_x; | |
10621 | input data_a; | |
10622 | input data_crit_x_l; | |
10623 | input data_ncrit_x_l; | |
10624 | ||
10625 | input qsel0_buf; | |
10626 | input shift_buf; | |
10627 | ||
10628 | output data_x_l; | |
10629 | ||
10630 | input si; | |
10631 | output so; | |
10632 | ||
10633 | wire so1; | |
10634 | wire q1; | |
10635 | wire q0; | |
10636 | wire q0_in; | |
10637 | wire x4; | |
10638 | wire x5; | |
10639 | ||
10640 | ||
10641 | cl_dp1_ccx_msff_4x msff1 ( | |
10642 | .l1clk(l1clk1), | |
10643 | .siclk(siclk), | |
10644 | .soclk(soclk), | |
10645 | .d(data_a), | |
10646 | .si(si), | |
10647 | .so(so1), | |
10648 | .q(q1) | |
10649 | ); | |
10650 | ||
10651 | cl_dp1_ccx_aomux2_4x mux1( | |
10652 | .in0(data_a), | |
10653 | .in1(q1), | |
10654 | .sel0(qsel0_buf), | |
10655 | .sel1(shift_buf), | |
10656 | .out(q0_in) | |
10657 | ); | |
10658 | ||
10659 | cl_dp1_ccx_msff_4x msff0 ( | |
10660 | .l1clk(l1clk0), | |
10661 | .siclk(siclk), | |
10662 | .soclk(soclk), | |
10663 | .d(q0_in), | |
10664 | .si(so1), | |
10665 | .so(so), | |
10666 | .q(q0) | |
10667 | ); | |
10668 | ||
10669 | cl_dp1_ccx_nand2_4x nand0( | |
10670 | .in0(q0), | |
10671 | .in1(grant_x), | |
10672 | .out(x4) | |
10673 | ); | |
10674 | ||
10675 | cl_dp1_ccx_nand3_12x nand1( | |
10676 | .in0(x4), | |
10677 | .in1(data_ncrit_x_l), | |
10678 | .in2(data_crit_x_l), | |
10679 | .out(x5) | |
10680 | ); | |
10681 | ||
10682 | cl_dp1_ccx_inva_32x inv0( | |
10683 | .in(x5), | |
10684 | .out(data_x_l) | |
10685 | ); | |
10686 | ||
10687 | endmodule // cl_dp1_ccx_mac_c2 | |
10688 | ||
10689 | module cl_dp1_ccx_aomux2_4x ( | |
10690 | in0, | |
10691 | in1, | |
10692 | sel0, | |
10693 | sel1, | |
10694 | out | |
10695 | ); | |
10696 | input in0; | |
10697 | input in1; | |
10698 | input sel0; | |
10699 | input sel1; | |
10700 | output out; | |
10701 | ||
10702 | `ifdef LIB | |
10703 | assign out = ((sel0 & in0) | | |
10704 | (sel1 & in1)); | |
10705 | `endif | |
10706 | ||
10707 | ||
10708 | endmodule | |
10709 | ||
10710 | module cl_dp1_ccx_buf_8x ( | |
10711 | in, | |
10712 | out | |
10713 | ); | |
10714 | input in; | |
10715 | output out; | |
10716 | ||
10717 | `ifdef LIB | |
10718 | assign out = in; | |
10719 | `endif | |
10720 | ||
10721 | endmodule | |
10722 | module cl_dp1_ccx_buf_1x ( | |
10723 | in, | |
10724 | out | |
10725 | ); | |
10726 | input in; | |
10727 | output out; | |
10728 | ||
10729 | `ifdef LIB | |
10730 | assign out = in; | |
10731 | `endif | |
10732 | ||
10733 | endmodule | |
10734 | module cl_dp1_ccx_bufmin_1x ( | |
10735 | in, | |
10736 | out | |
10737 | ); | |
10738 | input in; | |
10739 | output out; | |
10740 | ||
10741 | `ifdef LIB | |
10742 | assign out = in; | |
10743 | `endif | |
10744 | ||
10745 | endmodule | |
10746 | module cl_dp1_ccx_inv_12x ( | |
10747 | in, | |
10748 | out | |
10749 | ); | |
10750 | input in; | |
10751 | output out; | |
10752 | ||
10753 | `ifdef LIB | |
10754 | assign out = ~in; | |
10755 | `endif | |
10756 | ||
10757 | endmodule | |
10758 | module cl_dp1_ccx_inv_32x ( | |
10759 | in, | |
10760 | out | |
10761 | ); | |
10762 | input in; | |
10763 | output out; | |
10764 | ||
10765 | `ifdef LIB | |
10766 | assign out = ~in; | |
10767 | `endif | |
10768 | ||
10769 | endmodule | |
10770 | module cl_dp1_ccx_inva_32x ( | |
10771 | in, | |
10772 | out | |
10773 | ); | |
10774 | input in; | |
10775 | output out; | |
10776 | ||
10777 | `ifdef LIB | |
10778 | assign out = ~in; | |
10779 | `endif | |
10780 | ||
10781 | endmodule | |
10782 | ||
10783 | module cl_dp1_ccx_msff_16x ( q, so, d, l1clk, si, siclk, soclk ); | |
10784 | // RFM 05-14-2004 | |
10785 | // Level sensitive in SCAN_MODE | |
10786 | // Edge triggered when not in SCAN_MODE | |
10787 | ||
10788 | ||
10789 | parameter SIZE = 1; | |
10790 | ||
10791 | output q; | |
10792 | output so; | |
10793 | ||
10794 | input d; | |
10795 | input l1clk; | |
10796 | input si; | |
10797 | input siclk; | |
10798 | input soclk; | |
10799 | ||
10800 | reg q; | |
10801 | wire so; | |
10802 | wire l1clk, siclk, soclk; | |
10803 | ||
10804 | `ifdef SCAN_MODE | |
10805 | ||
10806 | reg l1; | |
10807 | `ifdef FAST_FLUSH | |
10808 | always @(posedge l1clk or posedge siclk ) begin | |
10809 | if (siclk) begin | |
10810 | q <= 1'b0; //pseudo flush reset | |
10811 | end else begin | |
10812 | q <= d; | |
10813 | end | |
10814 | end | |
10815 | `else | |
10816 | always @(l1clk or siclk or soclk or d or si) | |
10817 | begin | |
10818 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
10819 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
10820 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
10821 | ||
10822 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
10823 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
10824 | end | |
10825 | `endif | |
10826 | `else | |
10827 | wire si_unused; | |
10828 | wire siclk_unused; | |
10829 | wire soclk_unused; | |
10830 | assign si_unused = si; | |
10831 | assign siclk_unused = siclk; | |
10832 | assign soclk_unused = soclk; | |
10833 | ||
10834 | ||
10835 | `ifdef INITLATZERO | |
10836 | initial q = 1'b0; | |
10837 | `endif | |
10838 | ||
10839 | always @(posedge l1clk) | |
10840 | begin | |
10841 | if (!siclk && !soclk) q <= d; | |
10842 | else q <= 1'bx; | |
10843 | end | |
10844 | `endif | |
10845 | ||
10846 | assign so = q; | |
10847 | ||
10848 | endmodule // dff | |
10849 | module cl_dp1_ccx_msffmin_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
10850 | // RFM 05-14-2004 | |
10851 | // Level sensitive in SCAN_MODE | |
10852 | // Edge triggered when not in SCAN_MODE | |
10853 | ||
10854 | ||
10855 | parameter SIZE = 1; | |
10856 | ||
10857 | output q; | |
10858 | output so; | |
10859 | ||
10860 | input d; | |
10861 | input l1clk; | |
10862 | input si; | |
10863 | input siclk; | |
10864 | input soclk; | |
10865 | ||
10866 | reg q; | |
10867 | wire so; | |
10868 | wire l1clk, siclk, soclk; | |
10869 | ||
10870 | `ifdef SCAN_MODE | |
10871 | ||
10872 | reg l1; | |
10873 | `ifdef FAST_FLUSH | |
10874 | always @(posedge l1clk or posedge siclk ) begin | |
10875 | if (siclk) begin | |
10876 | q <= 1'b0; //pseudo flush reset | |
10877 | end else begin | |
10878 | q <= d; | |
10879 | end | |
10880 | end | |
10881 | `else | |
10882 | always @(l1clk or siclk or soclk or d or si) | |
10883 | begin | |
10884 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
10885 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
10886 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
10887 | ||
10888 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
10889 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
10890 | end | |
10891 | `endif | |
10892 | `else | |
10893 | wire si_unused; | |
10894 | wire siclk_unused; | |
10895 | wire soclk_unused; | |
10896 | assign si_unused = si; | |
10897 | assign siclk_unused = siclk; | |
10898 | assign soclk_unused = soclk; | |
10899 | ||
10900 | ||
10901 | `ifdef INITLATZERO | |
10902 | initial q = 1'b0; | |
10903 | `endif | |
10904 | ||
10905 | always @(posedge l1clk) | |
10906 | begin | |
10907 | if (!siclk && !soclk) q <= d; | |
10908 | else q <= 1'bx; | |
10909 | end | |
10910 | `endif | |
10911 | ||
10912 | assign so = q; | |
10913 | ||
10914 | endmodule // dff | |
10915 | module cl_dp1_ccx_msff_4x ( q, so, d, l1clk, si, siclk, soclk ); | |
10916 | // RFM 05-14-2004 | |
10917 | // Level sensitive in SCAN_MODE | |
10918 | // Edge triggered when not in SCAN_MODE | |
10919 | ||
10920 | ||
10921 | parameter SIZE = 1; | |
10922 | ||
10923 | output q; | |
10924 | output so; | |
10925 | ||
10926 | input d; | |
10927 | input l1clk; | |
10928 | input si; | |
10929 | input siclk; | |
10930 | input soclk; | |
10931 | ||
10932 | reg q; | |
10933 | wire so; | |
10934 | wire l1clk, siclk, soclk; | |
10935 | ||
10936 | `ifdef SCAN_MODE | |
10937 | ||
10938 | reg l1; | |
10939 | `ifdef FAST_FLUSH | |
10940 | always @(posedge l1clk or posedge siclk ) begin | |
10941 | if (siclk) begin | |
10942 | q <= 1'b0; //pseudo flush reset | |
10943 | end else begin | |
10944 | q <= d; | |
10945 | end | |
10946 | end | |
10947 | `else | |
10948 | always @(l1clk or siclk or soclk or d or si) | |
10949 | begin | |
10950 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
10951 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
10952 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
10953 | ||
10954 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
10955 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
10956 | end | |
10957 | `endif | |
10958 | `else | |
10959 | wire si_unused; | |
10960 | wire siclk_unused; | |
10961 | wire soclk_unused; | |
10962 | assign si_unused = si; | |
10963 | assign siclk_unused = siclk; | |
10964 | assign soclk_unused = soclk; | |
10965 | ||
10966 | ||
10967 | `ifdef INITLATZERO | |
10968 | initial q = 1'b0; | |
10969 | `endif | |
10970 | ||
10971 | always @(posedge l1clk) | |
10972 | begin | |
10973 | if (!siclk && !soclk) q <= d; | |
10974 | else q <= 1'bx; | |
10975 | end | |
10976 | `endif | |
10977 | ||
10978 | assign so = q; | |
10979 | ||
10980 | endmodule // dff | |
10981 | module cl_dp1_ccx_msff_8x ( q, so, d, l1clk, si, siclk, soclk ); | |
10982 | // RFM 05-14-2004 | |
10983 | // Level sensitive in SCAN_MODE | |
10984 | // Edge triggered when not in SCAN_MODE | |
10985 | ||
10986 | ||
10987 | parameter SIZE = 1; | |
10988 | ||
10989 | output q; | |
10990 | output so; | |
10991 | ||
10992 | input d; | |
10993 | input l1clk; | |
10994 | input si; | |
10995 | input siclk; | |
10996 | input soclk; | |
10997 | ||
10998 | reg q; | |
10999 | wire so; | |
11000 | wire l1clk, siclk, soclk; | |
11001 | ||
11002 | `ifdef SCAN_MODE | |
11003 | ||
11004 | reg l1; | |
11005 | `ifdef FAST_FLUSH | |
11006 | always @(posedge l1clk or posedge siclk ) begin | |
11007 | if (siclk) begin | |
11008 | q <= 1'b0; //pseudo flush reset | |
11009 | end else begin | |
11010 | q <= d; | |
11011 | end | |
11012 | end | |
11013 | `else | |
11014 | always @(l1clk or siclk or soclk or d or si) | |
11015 | begin | |
11016 | if (!l1clk && !siclk) l1 <= d; // Load master with data | |
11017 | else if ( l1clk && siclk) l1 <= si; // Load master with scan or flush | |
11018 | else if (!l1clk && siclk) l1 <= 1'bx; // Conflict between data and scan | |
11019 | ||
11020 | else if ( l1clk && !siclk && !soclk) q <= l1; // Load slave with master data | |
11021 | if ( l1clk && siclk && !soclk) q <= si; // Flush | |
11022 | end | |
11023 | `endif | |
11024 | `else | |
11025 | wire si_unused; | |
11026 | wire siclk_unused; | |
11027 | wire soclk_unused; | |
11028 | assign si_unused = si; | |
11029 | assign siclk_unused = siclk; | |
11030 | assign soclk_unused = soclk; | |
11031 | ||
11032 | ||
11033 | `ifdef INITLATZERO | |
11034 | initial q = 1'b0; | |
11035 | `endif | |
11036 | ||
11037 | always @(posedge l1clk) | |
11038 | begin | |
11039 | if (!siclk && !soclk) q <= d; | |
11040 | else q <= 1'bx; | |
11041 | end | |
11042 | `endif | |
11043 | ||
11044 | assign so = q; | |
11045 | ||
11046 | endmodule // dff | |
11047 | ||
11048 | module cl_dp1_ccx_nand2_1x ( | |
11049 | in0, | |
11050 | in1, | |
11051 | out | |
11052 | ); | |
11053 | input in0; | |
11054 | input in1; | |
11055 | output out; | |
11056 | ||
11057 | `ifdef LIB | |
11058 | assign out = ~(in0 & in1); | |
11059 | `endif | |
11060 | ||
11061 | endmodule | |
11062 | module cl_dp1_ccx_nand2_12x ( | |
11063 | in0, | |
11064 | in1, | |
11065 | out | |
11066 | ); | |
11067 | input in0; | |
11068 | input in1; | |
11069 | output out; | |
11070 | ||
11071 | `ifdef LIB | |
11072 | assign out = ~(in0 & in1); | |
11073 | `endif | |
11074 | ||
11075 | endmodule | |
11076 | module cl_dp1_ccx_nand2_4x ( | |
11077 | in0, | |
11078 | in1, | |
11079 | out | |
11080 | ); | |
11081 | input in0; | |
11082 | input in1; | |
11083 | output out; | |
11084 | ||
11085 | `ifdef LIB | |
11086 | assign out = ~(in0 & in1); | |
11087 | `endif | |
11088 | ||
11089 | endmodule | |
11090 | module cl_dp1_ccx_nand3_12x ( | |
11091 | in0, | |
11092 | in1, | |
11093 | in2, | |
11094 | out | |
11095 | ); | |
11096 | input in0; | |
11097 | input in1; | |
11098 | input in2; | |
11099 | output out; | |
11100 | ||
11101 | `ifdef LIB | |
11102 | assign out = ~(in0 & in1 & in2); | |
11103 | `endif | |
11104 | ||
11105 | endmodule | |
11106 | module cl_dp1_ccx_l1hdr_16x (l1clk, | |
11107 | l2clk, | |
11108 | se, | |
11109 | pce, | |
11110 | pce_ov, | |
11111 | stop, | |
11112 | aclk, | |
11113 | bclk, | |
11114 | siclk_out, | |
11115 | soclk_out | |
11116 | ); | |
11117 | // RFM 05/21/2004 | |
11118 | ||
11119 | ||
11120 | output l1clk; | |
11121 | input l2clk; // level 2 clock, from clock grid | |
11122 | input se; // Scan Enable | |
11123 | input pce; // Clock enable for local power savings | |
11124 | input pce_ov; // TCU sourced clock enable override for testing | |
11125 | input stop; // TCU/CCU sourced clock stop for debug | |
11126 | input aclk; | |
11127 | input bclk; | |
11128 | output siclk_out; | |
11129 | output soclk_out; | |
11130 | `ifdef FORMAL_TOOL | |
11131 | wire l1en = (~stop & ( pce | pce_ov )); | |
11132 | assign l1clk = (l2clk & l1en) | se; | |
11133 | assign siclk_out = aclk; | |
11134 | assign soclk_out = bclk; | |
11135 | `else | |
11136 | `ifdef LIB | |
11137 | reg l1en; | |
11138 | `ifdef SCAN_MODE | |
11139 | always @ (l2clk or stop or pce or pce_ov) | |
11140 | begin | |
11141 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
11142 | end | |
11143 | `else | |
11144 | ||
11145 | always @ (negedge l2clk ) | |
11146 | begin | |
11147 | l1en <= (~stop & ( pce | pce_ov )); | |
11148 | end | |
11149 | `endif | |
11150 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
11151 | ||
11152 | assign siclk_out = aclk; | |
11153 | assign soclk_out = bclk; | |
11154 | ||
11155 | `endif // `ifdef LIB | |
11156 | `endif // !`ifdef FORMAL_TOOL | |
11157 | ||
11158 | ||
11159 | endmodule | |
11160 | ||
11161 | module cl_dp1_ccx_l1hdr_8x (l1clk, | |
11162 | l2clk, | |
11163 | se, | |
11164 | pce, | |
11165 | pce_ov, | |
11166 | stop, | |
11167 | aclk, | |
11168 | bclk, | |
11169 | siclk_out, | |
11170 | soclk_out | |
11171 | ); | |
11172 | // RFM 05/21/2004 | |
11173 | ||
11174 | ||
11175 | output l1clk; | |
11176 | input l2clk; // level 2 clock, from clock grid | |
11177 | input se; // Scan Enable | |
11178 | input pce; // Clock enable for local power savings | |
11179 | input pce_ov; // TCU sourced clock enable override for testing | |
11180 | input stop; // TCU/CCU sourced clock stop for debug | |
11181 | input aclk; | |
11182 | input bclk; | |
11183 | output siclk_out; | |
11184 | output soclk_out; | |
11185 | `ifdef FORMAL_TOOL | |
11186 | wire l1en = (~stop & ( pce | pce_ov )); | |
11187 | assign l1clk = (l2clk & l1en) | se; | |
11188 | assign siclk_out = aclk; | |
11189 | assign soclk_out = bclk; | |
11190 | `else | |
11191 | `ifdef LIB | |
11192 | reg l1en; | |
11193 | `ifdef SCAN_MODE | |
11194 | always @ (l2clk or stop or pce or pce_ov) | |
11195 | begin | |
11196 | if (~l2clk) l1en <= (~stop & (pce | pce_ov)); | |
11197 | end | |
11198 | `else | |
11199 | ||
11200 | always @ (negedge l2clk ) | |
11201 | begin | |
11202 | l1en <= (~stop & ( pce | pce_ov )); | |
11203 | end | |
11204 | `endif | |
11205 | assign l1clk = (l2clk & l1en) || se; // se is async and highest priority | |
11206 | ||
11207 | assign siclk_out = aclk; | |
11208 | assign soclk_out = bclk; | |
11209 | ||
11210 | `endif // `ifdef LIB | |
11211 | `endif // !`ifdef FORMAL_TOOL | |
11212 | ||
11213 | ||
11214 | endmodule |