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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_sc1gb.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_sc1gb_aomux2_12x ( | |
36 | in0, | |
37 | in1, | |
38 | sel0, | |
39 | sel1, | |
40 | out | |
41 | ); | |
42 | input in0; | |
43 | input in1; | |
44 | input sel0; | |
45 | input sel1; | |
46 | output out; | |
47 | ||
48 | `ifdef LIB | |
49 | assign out = ((sel0 & in0) | | |
50 | (sel1 & in1)); | |
51 | `endif | |
52 | ||
53 | ||
54 | endmodule | |
55 | module cl_sc1gb_aomux2_16x ( | |
56 | in0, | |
57 | in1, | |
58 | sel0, | |
59 | sel1, | |
60 | out | |
61 | ); | |
62 | input in0; | |
63 | input in1; | |
64 | input sel0; | |
65 | input sel1; | |
66 | output out; | |
67 | ||
68 | `ifdef LIB | |
69 | assign out = ((sel0 & in0) | | |
70 | (sel1 & in1)); | |
71 | `endif | |
72 | ||
73 | ||
74 | endmodule | |
75 | module cl_sc1gb_aomux2_1x ( | |
76 | in0, | |
77 | in1, | |
78 | sel0, | |
79 | sel1, | |
80 | out | |
81 | ); | |
82 | input in0; | |
83 | input in1; | |
84 | input sel0; | |
85 | input sel1; | |
86 | output out; | |
87 | ||
88 | `ifdef LIB | |
89 | assign out = ((sel0 & in0) | | |
90 | (sel1 & in1)); | |
91 | `endif | |
92 | ||
93 | ||
94 | endmodule | |
95 | module cl_sc1gb_aomux2_2x ( | |
96 | in0, | |
97 | in1, | |
98 | sel0, | |
99 | sel1, | |
100 | out | |
101 | ); | |
102 | input in0; | |
103 | input in1; | |
104 | input sel0; | |
105 | input sel1; | |
106 | output out; | |
107 | ||
108 | `ifdef LIB | |
109 | assign out = ((sel0 & in0) | | |
110 | (sel1 & in1)); | |
111 | `endif | |
112 | ||
113 | ||
114 | endmodule | |
115 | module cl_sc1gb_aomux2_4x ( | |
116 | in0, | |
117 | in1, | |
118 | sel0, | |
119 | sel1, | |
120 | out | |
121 | ); | |
122 | input in0; | |
123 | input in1; | |
124 | input sel0; | |
125 | input sel1; | |
126 | output out; | |
127 | ||
128 | `ifdef LIB | |
129 | assign out = ((sel0 & in0) | | |
130 | (sel1 & in1)); | |
131 | `endif | |
132 | ||
133 | ||
134 | endmodule | |
135 | module cl_sc1gb_aomux2_6x ( | |
136 | in0, | |
137 | in1, | |
138 | sel0, | |
139 | sel1, | |
140 | out | |
141 | ); | |
142 | input in0; | |
143 | input in1; | |
144 | input sel0; | |
145 | input sel1; | |
146 | output out; | |
147 | ||
148 | `ifdef LIB | |
149 | assign out = ((sel0 & in0) | | |
150 | (sel1 & in1)); | |
151 | `endif | |
152 | ||
153 | ||
154 | endmodule | |
155 | module cl_sc1gb_aomux2_8x ( | |
156 | in0, | |
157 | in1, | |
158 | sel0, | |
159 | sel1, | |
160 | out | |
161 | ); | |
162 | input in0; | |
163 | input in1; | |
164 | input sel0; | |
165 | input sel1; | |
166 | output out; | |
167 | ||
168 | `ifdef LIB | |
169 | assign out = ((sel0 & in0) | | |
170 | (sel1 & in1)); | |
171 | `endif | |
172 | ||
173 | ||
174 | endmodule | |
175 | module cl_sc1gb_aomux3_12x ( | |
176 | in0, | |
177 | in1, | |
178 | in2, | |
179 | sel0, | |
180 | sel1, | |
181 | sel2, | |
182 | out | |
183 | ); | |
184 | input in0; | |
185 | input in1; | |
186 | input in2; | |
187 | input sel0; | |
188 | input sel1; | |
189 | input sel2; | |
190 | output out; | |
191 | ||
192 | `ifdef LIB | |
193 | assign out = ((sel0 & in0) | | |
194 | (sel1 & in1) | | |
195 | (sel2 & in2)); | |
196 | `endif | |
197 | ||
198 | endmodule | |
199 | module cl_sc1gb_aomux3_16x ( | |
200 | in0, | |
201 | in1, | |
202 | in2, | |
203 | sel0, | |
204 | sel1, | |
205 | sel2, | |
206 | out | |
207 | ); | |
208 | input in0; | |
209 | input in1; | |
210 | input in2; | |
211 | input sel0; | |
212 | input sel1; | |
213 | input sel2; | |
214 | output out; | |
215 | ||
216 | `ifdef LIB | |
217 | assign out = ((sel0 & in0) | | |
218 | (sel1 & in1) | | |
219 | (sel2 & in2)); | |
220 | `endif | |
221 | ||
222 | endmodule | |
223 | module cl_sc1gb_aomux3_1x ( | |
224 | in0, | |
225 | in1, | |
226 | in2, | |
227 | sel0, | |
228 | sel1, | |
229 | sel2, | |
230 | out | |
231 | ); | |
232 | input in0; | |
233 | input in1; | |
234 | input in2; | |
235 | input sel0; | |
236 | input sel1; | |
237 | input sel2; | |
238 | output out; | |
239 | ||
240 | `ifdef LIB | |
241 | assign out = ((sel0 & in0) | | |
242 | (sel1 & in1) | | |
243 | (sel2 & in2)); | |
244 | `endif | |
245 | ||
246 | endmodule | |
247 | module cl_sc1gb_aomux3_2x ( | |
248 | in0, | |
249 | in1, | |
250 | in2, | |
251 | sel0, | |
252 | sel1, | |
253 | sel2, | |
254 | out | |
255 | ); | |
256 | input in0; | |
257 | input in1; | |
258 | input in2; | |
259 | input sel0; | |
260 | input sel1; | |
261 | input sel2; | |
262 | output out; | |
263 | ||
264 | `ifdef LIB | |
265 | assign out = ((sel0 & in0) | | |
266 | (sel1 & in1) | | |
267 | (sel2 & in2)); | |
268 | `endif | |
269 | ||
270 | endmodule | |
271 | module cl_sc1gb_aomux3_4x ( | |
272 | in0, | |
273 | in1, | |
274 | in2, | |
275 | sel0, | |
276 | sel1, | |
277 | sel2, | |
278 | out | |
279 | ); | |
280 | input in0; | |
281 | input in1; | |
282 | input in2; | |
283 | input sel0; | |
284 | input sel1; | |
285 | input sel2; | |
286 | output out; | |
287 | ||
288 | `ifdef LIB | |
289 | assign out = ((sel0 & in0) | | |
290 | (sel1 & in1) | | |
291 | (sel2 & in2)); | |
292 | `endif | |
293 | ||
294 | endmodule | |
295 | module cl_sc1gb_aomux3_6x ( | |
296 | in0, | |
297 | in1, | |
298 | in2, | |
299 | sel0, | |
300 | sel1, | |
301 | sel2, | |
302 | out | |
303 | ); | |
304 | input in0; | |
305 | input in1; | |
306 | input in2; | |
307 | input sel0; | |
308 | input sel1; | |
309 | input sel2; | |
310 | output out; | |
311 | ||
312 | `ifdef LIB | |
313 | assign out = ((sel0 & in0) | | |
314 | (sel1 & in1) | | |
315 | (sel2 & in2)); | |
316 | `endif | |
317 | ||
318 | endmodule | |
319 | module cl_sc1gb_aomux3_8x ( | |
320 | in0, | |
321 | in1, | |
322 | in2, | |
323 | sel0, | |
324 | sel1, | |
325 | sel2, | |
326 | out | |
327 | ); | |
328 | input in0; | |
329 | input in1; | |
330 | input in2; | |
331 | input sel0; | |
332 | input sel1; | |
333 | input sel2; | |
334 | output out; | |
335 | ||
336 | `ifdef LIB | |
337 | assign out = ((sel0 & in0) | | |
338 | (sel1 & in1) | | |
339 | (sel2 & in2)); | |
340 | `endif | |
341 | ||
342 | endmodule | |
343 | module cl_sc1gb_aomux4_12x ( | |
344 | in0, | |
345 | in1, | |
346 | in2, | |
347 | in3, | |
348 | sel0, | |
349 | sel1, | |
350 | sel2, | |
351 | sel3, | |
352 | out | |
353 | ); | |
354 | input in0; | |
355 | input in1; | |
356 | input in2; | |
357 | input in3; | |
358 | input sel0; | |
359 | input sel1; | |
360 | input sel2; | |
361 | input sel3; | |
362 | output out; | |
363 | ||
364 | `ifdef LIB | |
365 | assign out = ((sel0 & in0) | | |
366 | (sel1 & in1) | | |
367 | (sel2 & in2) | | |
368 | (sel3 & in3)); | |
369 | `endif | |
370 | ||
371 | endmodule | |
372 | module cl_sc1gb_aomux4_16x ( | |
373 | in0, | |
374 | in1, | |
375 | in2, | |
376 | in3, | |
377 | sel0, | |
378 | sel1, | |
379 | sel2, | |
380 | sel3, | |
381 | out | |
382 | ); | |
383 | input in0; | |
384 | input in1; | |
385 | input in2; | |
386 | input in3; | |
387 | input sel0; | |
388 | input sel1; | |
389 | input sel2; | |
390 | input sel3; | |
391 | output out; | |
392 | ||
393 | `ifdef LIB | |
394 | assign out = ((sel0 & in0) | | |
395 | (sel1 & in1) | | |
396 | (sel2 & in2) | | |
397 | (sel3 & in3)); | |
398 | `endif | |
399 | ||
400 | endmodule | |
401 | module cl_sc1gb_aomux4_1x ( | |
402 | in0, | |
403 | in1, | |
404 | in2, | |
405 | in3, | |
406 | sel0, | |
407 | sel1, | |
408 | sel2, | |
409 | sel3, | |
410 | out | |
411 | ); | |
412 | input in0; | |
413 | input in1; | |
414 | input in2; | |
415 | input in3; | |
416 | input sel0; | |
417 | input sel1; | |
418 | input sel2; | |
419 | input sel3; | |
420 | output out; | |
421 | ||
422 | `ifdef LIB | |
423 | assign out = ((sel0 & in0) | | |
424 | (sel1 & in1) | | |
425 | (sel2 & in2) | | |
426 | (sel3 & in3)); | |
427 | `endif | |
428 | ||
429 | endmodule | |
430 | module cl_sc1gb_aomux4_2x ( | |
431 | in0, | |
432 | in1, | |
433 | in2, | |
434 | in3, | |
435 | sel0, | |
436 | sel1, | |
437 | sel2, | |
438 | sel3, | |
439 | out | |
440 | ); | |
441 | input in0; | |
442 | input in1; | |
443 | input in2; | |
444 | input in3; | |
445 | input sel0; | |
446 | input sel1; | |
447 | input sel2; | |
448 | input sel3; | |
449 | output out; | |
450 | ||
451 | `ifdef LIB | |
452 | assign out = ((sel0 & in0) | | |
453 | (sel1 & in1) | | |
454 | (sel2 & in2) | | |
455 | (sel3 & in3)); | |
456 | `endif | |
457 | ||
458 | endmodule | |
459 | module cl_sc1gb_aomux4_4x ( | |
460 | in0, | |
461 | in1, | |
462 | in2, | |
463 | in3, | |
464 | sel0, | |
465 | sel1, | |
466 | sel2, | |
467 | sel3, | |
468 | out | |
469 | ); | |
470 | input in0; | |
471 | input in1; | |
472 | input in2; | |
473 | input in3; | |
474 | input sel0; | |
475 | input sel1; | |
476 | input sel2; | |
477 | input sel3; | |
478 | output out; | |
479 | ||
480 | `ifdef LIB | |
481 | assign out = ((sel0 & in0) | | |
482 | (sel1 & in1) | | |
483 | (sel2 & in2) | | |
484 | (sel3 & in3)); | |
485 | `endif | |
486 | ||
487 | endmodule | |
488 | module cl_sc1gb_aomux4_6x ( | |
489 | in0, | |
490 | in1, | |
491 | in2, | |
492 | in3, | |
493 | sel0, | |
494 | sel1, | |
495 | sel2, | |
496 | sel3, | |
497 | out | |
498 | ); | |
499 | input in0; | |
500 | input in1; | |
501 | input in2; | |
502 | input in3; | |
503 | input sel0; | |
504 | input sel1; | |
505 | input sel2; | |
506 | input sel3; | |
507 | output out; | |
508 | ||
509 | `ifdef LIB | |
510 | assign out = ((sel0 & in0) | | |
511 | (sel1 & in1) | | |
512 | (sel2 & in2) | | |
513 | (sel3 & in3)); | |
514 | `endif | |
515 | ||
516 | endmodule | |
517 | module cl_sc1gb_aomux4_8x ( | |
518 | in0, | |
519 | in1, | |
520 | in2, | |
521 | in3, | |
522 | sel0, | |
523 | sel1, | |
524 | sel2, | |
525 | sel3, | |
526 | out | |
527 | ); | |
528 | input in0; | |
529 | input in1; | |
530 | input in2; | |
531 | input in3; | |
532 | input sel0; | |
533 | input sel1; | |
534 | input sel2; | |
535 | input sel3; | |
536 | output out; | |
537 | ||
538 | `ifdef LIB | |
539 | assign out = ((sel0 & in0) | | |
540 | (sel1 & in1) | | |
541 | (sel2 & in2) | | |
542 | (sel3 & in3)); | |
543 | `endif | |
544 | ||
545 | endmodule | |
546 | module cl_sc1gb_aomux5_12x ( | |
547 | in0, | |
548 | in1, | |
549 | in2, | |
550 | in3, | |
551 | in4, | |
552 | sel0, | |
553 | sel1, | |
554 | sel2, | |
555 | sel3, | |
556 | sel4, | |
557 | out | |
558 | ); | |
559 | input in0; | |
560 | input in1; | |
561 | input in2; | |
562 | input in3; | |
563 | input in4; | |
564 | input sel0; | |
565 | input sel1; | |
566 | input sel2; | |
567 | input sel3; | |
568 | input sel4; | |
569 | output out; | |
570 | ||
571 | `ifdef LIB | |
572 | assign out = ((sel0 & in0) | | |
573 | (sel1 & in1) | | |
574 | (sel2 & in2) | | |
575 | (sel3 & in3) | | |
576 | (sel4 & in4)); | |
577 | `endif | |
578 | ||
579 | endmodule | |
580 | module cl_sc1gb_aomux5_16x ( | |
581 | in0, | |
582 | in1, | |
583 | in2, | |
584 | in3, | |
585 | in4, | |
586 | sel0, | |
587 | sel1, | |
588 | sel2, | |
589 | sel3, | |
590 | sel4, | |
591 | out | |
592 | ); | |
593 | input in0; | |
594 | input in1; | |
595 | input in2; | |
596 | input in3; | |
597 | input in4; | |
598 | input sel0; | |
599 | input sel1; | |
600 | input sel2; | |
601 | input sel3; | |
602 | input sel4; | |
603 | output out; | |
604 | ||
605 | `ifdef LIB | |
606 | assign out = ((sel0 & in0) | | |
607 | (sel1 & in1) | | |
608 | (sel2 & in2) | | |
609 | (sel3 & in3) | | |
610 | (sel4 & in4)); | |
611 | `endif | |
612 | ||
613 | endmodule | |
614 | module cl_sc1gb_aomux5_1x ( | |
615 | in0, | |
616 | in1, | |
617 | in2, | |
618 | in3, | |
619 | in4, | |
620 | sel0, | |
621 | sel1, | |
622 | sel2, | |
623 | sel3, | |
624 | sel4, | |
625 | out | |
626 | ); | |
627 | input in0; | |
628 | input in1; | |
629 | input in2; | |
630 | input in3; | |
631 | input in4; | |
632 | input sel0; | |
633 | input sel1; | |
634 | input sel2; | |
635 | input sel3; | |
636 | input sel4; | |
637 | output out; | |
638 | ||
639 | `ifdef LIB | |
640 | assign out = ((sel0 & in0) | | |
641 | (sel1 & in1) | | |
642 | (sel2 & in2) | | |
643 | (sel3 & in3) | | |
644 | (sel4 & in4)); | |
645 | `endif | |
646 | ||
647 | endmodule | |
648 | module cl_sc1gb_aomux5_2x ( | |
649 | in0, | |
650 | in1, | |
651 | in2, | |
652 | in3, | |
653 | in4, | |
654 | sel0, | |
655 | sel1, | |
656 | sel2, | |
657 | sel3, | |
658 | sel4, | |
659 | out | |
660 | ); | |
661 | input in0; | |
662 | input in1; | |
663 | input in2; | |
664 | input in3; | |
665 | input in4; | |
666 | input sel0; | |
667 | input sel1; | |
668 | input sel2; | |
669 | input sel3; | |
670 | input sel4; | |
671 | output out; | |
672 | ||
673 | `ifdef LIB | |
674 | assign out = ((sel0 & in0) | | |
675 | (sel1 & in1) | | |
676 | (sel2 & in2) | | |
677 | (sel3 & in3) | | |
678 | (sel4 & in4)); | |
679 | `endif | |
680 | ||
681 | endmodule | |
682 | module cl_sc1gb_aomux5_4x ( | |
683 | in0, | |
684 | in1, | |
685 | in2, | |
686 | in3, | |
687 | in4, | |
688 | sel0, | |
689 | sel1, | |
690 | sel2, | |
691 | sel3, | |
692 | sel4, | |
693 | out | |
694 | ); | |
695 | input in0; | |
696 | input in1; | |
697 | input in2; | |
698 | input in3; | |
699 | input in4; | |
700 | input sel0; | |
701 | input sel1; | |
702 | input sel2; | |
703 | input sel3; | |
704 | input sel4; | |
705 | output out; | |
706 | ||
707 | `ifdef LIB | |
708 | assign out = ((sel0 & in0) | | |
709 | (sel1 & in1) | | |
710 | (sel2 & in2) | | |
711 | (sel3 & in3) | | |
712 | (sel4 & in4)); | |
713 | `endif | |
714 | ||
715 | endmodule | |
716 | module cl_sc1gb_aomux5_6x ( | |
717 | in0, | |
718 | in1, | |
719 | in2, | |
720 | in3, | |
721 | in4, | |
722 | sel0, | |
723 | sel1, | |
724 | sel2, | |
725 | sel3, | |
726 | sel4, | |
727 | out | |
728 | ); | |
729 | input in0; | |
730 | input in1; | |
731 | input in2; | |
732 | input in3; | |
733 | input in4; | |
734 | input sel0; | |
735 | input sel1; | |
736 | input sel2; | |
737 | input sel3; | |
738 | input sel4; | |
739 | output out; | |
740 | ||
741 | `ifdef LIB | |
742 | assign out = ((sel0 & in0) | | |
743 | (sel1 & in1) | | |
744 | (sel2 & in2) | | |
745 | (sel3 & in3) | | |
746 | (sel4 & in4)); | |
747 | `endif | |
748 | ||
749 | endmodule | |
750 | module cl_sc1gb_aomux5_8x ( | |
751 | in0, | |
752 | in1, | |
753 | in2, | |
754 | in3, | |
755 | in4, | |
756 | sel0, | |
757 | sel1, | |
758 | sel2, | |
759 | sel3, | |
760 | sel4, | |
761 | out | |
762 | ); | |
763 | input in0; | |
764 | input in1; | |
765 | input in2; | |
766 | input in3; | |
767 | input in4; | |
768 | input sel0; | |
769 | input sel1; | |
770 | input sel2; | |
771 | input sel3; | |
772 | input sel4; | |
773 | output out; | |
774 | ||
775 | `ifdef LIB | |
776 | assign out = ((sel0 & in0) | | |
777 | (sel1 & in1) | | |
778 | (sel2 & in2) | | |
779 | (sel3 & in3) | | |
780 | (sel4 & in4)); | |
781 | `endif | |
782 | ||
783 | endmodule | |
784 | module cl_sc1gb_aomux6_12x ( | |
785 | in0, | |
786 | in1, | |
787 | in2, | |
788 | in3, | |
789 | in4, | |
790 | in5, | |
791 | sel0, | |
792 | sel1, | |
793 | sel2, | |
794 | sel3, | |
795 | sel4, | |
796 | sel5, | |
797 | out | |
798 | ); | |
799 | input in0; | |
800 | input in1; | |
801 | input in2; | |
802 | input in3; | |
803 | input in4; | |
804 | input in5; | |
805 | input sel0; | |
806 | input sel1; | |
807 | input sel2; | |
808 | input sel3; | |
809 | input sel4; | |
810 | input sel5; | |
811 | output out; | |
812 | ||
813 | `ifdef LIB | |
814 | assign out = ((sel0 & in0) | | |
815 | (sel1 & in1) | | |
816 | (sel2 & in2) | | |
817 | (sel3 & in3) | | |
818 | (sel4 & in4) | | |
819 | (sel5 & in5)); | |
820 | `endif | |
821 | ||
822 | endmodule | |
823 | module cl_sc1gb_aomux6_16x ( | |
824 | in0, | |
825 | in1, | |
826 | in2, | |
827 | in3, | |
828 | in4, | |
829 | in5, | |
830 | sel0, | |
831 | sel1, | |
832 | sel2, | |
833 | sel3, | |
834 | sel4, | |
835 | sel5, | |
836 | out | |
837 | ); | |
838 | input in0; | |
839 | input in1; | |
840 | input in2; | |
841 | input in3; | |
842 | input in4; | |
843 | input in5; | |
844 | input sel0; | |
845 | input sel1; | |
846 | input sel2; | |
847 | input sel3; | |
848 | input sel4; | |
849 | input sel5; | |
850 | output out; | |
851 | ||
852 | `ifdef LIB | |
853 | assign out = ((sel0 & in0) | | |
854 | (sel1 & in1) | | |
855 | (sel2 & in2) | | |
856 | (sel3 & in3) | | |
857 | (sel4 & in4) | | |
858 | (sel5 & in5)); | |
859 | `endif | |
860 | ||
861 | endmodule | |
862 | module cl_sc1gb_aomux6_1x ( | |
863 | in0, | |
864 | in1, | |
865 | in2, | |
866 | in3, | |
867 | in4, | |
868 | in5, | |
869 | sel0, | |
870 | sel1, | |
871 | sel2, | |
872 | sel3, | |
873 | sel4, | |
874 | sel5, | |
875 | out | |
876 | ); | |
877 | input in0; | |
878 | input in1; | |
879 | input in2; | |
880 | input in3; | |
881 | input in4; | |
882 | input in5; | |
883 | input sel0; | |
884 | input sel1; | |
885 | input sel2; | |
886 | input sel3; | |
887 | input sel4; | |
888 | input sel5; | |
889 | output out; | |
890 | ||
891 | `ifdef LIB | |
892 | assign out = ((sel0 & in0) | | |
893 | (sel1 & in1) | | |
894 | (sel2 & in2) | | |
895 | (sel3 & in3) | | |
896 | (sel4 & in4) | | |
897 | (sel5 & in5)); | |
898 | `endif | |
899 | ||
900 | endmodule | |
901 | module cl_sc1gb_aomux6_2x ( | |
902 | in0, | |
903 | in1, | |
904 | in2, | |
905 | in3, | |
906 | in4, | |
907 | in5, | |
908 | sel0, | |
909 | sel1, | |
910 | sel2, | |
911 | sel3, | |
912 | sel4, | |
913 | sel5, | |
914 | out | |
915 | ); | |
916 | input in0; | |
917 | input in1; | |
918 | input in2; | |
919 | input in3; | |
920 | input in4; | |
921 | input in5; | |
922 | input sel0; | |
923 | input sel1; | |
924 | input sel2; | |
925 | input sel3; | |
926 | input sel4; | |
927 | input sel5; | |
928 | output out; | |
929 | ||
930 | `ifdef LIB | |
931 | assign out = ((sel0 & in0) | | |
932 | (sel1 & in1) | | |
933 | (sel2 & in2) | | |
934 | (sel3 & in3) | | |
935 | (sel4 & in4) | | |
936 | (sel5 & in5)); | |
937 | `endif | |
938 | ||
939 | endmodule | |
940 | module cl_sc1gb_aomux6_4x ( | |
941 | in0, | |
942 | in1, | |
943 | in2, | |
944 | in3, | |
945 | in4, | |
946 | in5, | |
947 | sel0, | |
948 | sel1, | |
949 | sel2, | |
950 | sel3, | |
951 | sel4, | |
952 | sel5, | |
953 | out | |
954 | ); | |
955 | input in0; | |
956 | input in1; | |
957 | input in2; | |
958 | input in3; | |
959 | input in4; | |
960 | input in5; | |
961 | input sel0; | |
962 | input sel1; | |
963 | input sel2; | |
964 | input sel3; | |
965 | input sel4; | |
966 | input sel5; | |
967 | output out; | |
968 | ||
969 | `ifdef LIB | |
970 | assign out = ((sel0 & in0) | | |
971 | (sel1 & in1) | | |
972 | (sel2 & in2) | | |
973 | (sel3 & in3) | | |
974 | (sel4 & in4) | | |
975 | (sel5 & in5)); | |
976 | `endif | |
977 | ||
978 | endmodule | |
979 | module cl_sc1gb_aomux6_6x ( | |
980 | in0, | |
981 | in1, | |
982 | in2, | |
983 | in3, | |
984 | in4, | |
985 | in5, | |
986 | sel0, | |
987 | sel1, | |
988 | sel2, | |
989 | sel3, | |
990 | sel4, | |
991 | sel5, | |
992 | out | |
993 | ); | |
994 | input in0; | |
995 | input in1; | |
996 | input in2; | |
997 | input in3; | |
998 | input in4; | |
999 | input in5; | |
1000 | input sel0; | |
1001 | input sel1; | |
1002 | input sel2; | |
1003 | input sel3; | |
1004 | input sel4; | |
1005 | input sel5; | |
1006 | output out; | |
1007 | ||
1008 | `ifdef LIB | |
1009 | assign out = ((sel0 & in0) | | |
1010 | (sel1 & in1) | | |
1011 | (sel2 & in2) | | |
1012 | (sel3 & in3) | | |
1013 | (sel4 & in4) | | |
1014 | (sel5 & in5)); | |
1015 | `endif | |
1016 | ||
1017 | endmodule | |
1018 | module cl_sc1gb_aomux6_8x ( | |
1019 | in0, | |
1020 | in1, | |
1021 | in2, | |
1022 | in3, | |
1023 | in4, | |
1024 | in5, | |
1025 | sel0, | |
1026 | sel1, | |
1027 | sel2, | |
1028 | sel3, | |
1029 | sel4, | |
1030 | sel5, | |
1031 | out | |
1032 | ); | |
1033 | input in0; | |
1034 | input in1; | |
1035 | input in2; | |
1036 | input in3; | |
1037 | input in4; | |
1038 | input in5; | |
1039 | input sel0; | |
1040 | input sel1; | |
1041 | input sel2; | |
1042 | input sel3; | |
1043 | input sel4; | |
1044 | input sel5; | |
1045 | output out; | |
1046 | ||
1047 | `ifdef LIB | |
1048 | assign out = ((sel0 & in0) | | |
1049 | (sel1 & in1) | | |
1050 | (sel2 & in2) | | |
1051 | (sel3 & in3) | | |
1052 | (sel4 & in4) | | |
1053 | (sel5 & in5)); | |
1054 | `endif | |
1055 | ||
1056 | endmodule | |
1057 | module cl_sc1gb_aomux6_by2_1x ( | |
1058 | in0, | |
1059 | in1, | |
1060 | in2, | |
1061 | in3, | |
1062 | in4, | |
1063 | in5, | |
1064 | sel0, | |
1065 | sel1, | |
1066 | sel2, | |
1067 | sel3, | |
1068 | sel4, | |
1069 | sel5, | |
1070 | out | |
1071 | ); | |
1072 | input in0; | |
1073 | input in1; | |
1074 | input in2; | |
1075 | input in3; | |
1076 | input in4; | |
1077 | input in5; | |
1078 | input sel0; | |
1079 | input sel1; | |
1080 | input sel2; | |
1081 | input sel3; | |
1082 | input sel4; | |
1083 | input sel5; | |
1084 | output out; | |
1085 | ||
1086 | `ifdef LIB | |
1087 | assign out = ((sel0 & in0) | | |
1088 | (sel1 & in1) | | |
1089 | (sel2 & in2) | | |
1090 | (sel3 & in3) | | |
1091 | (sel4 & in4) | | |
1092 | (sel5 & in5)); | |
1093 | `endif | |
1094 | ||
1095 | endmodule | |
1096 | module cl_sc1gb_aomux6_by2_2x ( | |
1097 | in0, | |
1098 | in1, | |
1099 | in2, | |
1100 | in3, | |
1101 | in4, | |
1102 | in5, | |
1103 | sel0, | |
1104 | sel1, | |
1105 | sel2, | |
1106 | sel3, | |
1107 | sel4, | |
1108 | sel5, | |
1109 | out | |
1110 | ); | |
1111 | input in0; | |
1112 | input in1; | |
1113 | input in2; | |
1114 | input in3; | |
1115 | input in4; | |
1116 | input in5; | |
1117 | input sel0; | |
1118 | input sel1; | |
1119 | input sel2; | |
1120 | input sel3; | |
1121 | input sel4; | |
1122 | input sel5; | |
1123 | output out; | |
1124 | ||
1125 | `ifdef LIB | |
1126 | assign out = ((sel0 & in0) | | |
1127 | (sel1 & in1) | | |
1128 | (sel2 & in2) | | |
1129 | (sel3 & in3) | | |
1130 | (sel4 & in4) | | |
1131 | (sel5 & in5)); | |
1132 | `endif | |
1133 | ||
1134 | endmodule | |
1135 | module cl_sc1gb_aomux7_12x ( | |
1136 | in0, | |
1137 | in1, | |
1138 | in2, | |
1139 | in3, | |
1140 | in4, | |
1141 | in5, | |
1142 | in6, | |
1143 | sel0, | |
1144 | sel1, | |
1145 | sel2, | |
1146 | sel3, | |
1147 | sel4, | |
1148 | sel5, | |
1149 | sel6, | |
1150 | out | |
1151 | ); | |
1152 | input in0; | |
1153 | input in1; | |
1154 | input in2; | |
1155 | input in3; | |
1156 | input in4; | |
1157 | input in5; | |
1158 | input in6; | |
1159 | input sel0; | |
1160 | input sel1; | |
1161 | input sel2; | |
1162 | input sel3; | |
1163 | input sel4; | |
1164 | input sel5; | |
1165 | input sel6; | |
1166 | output out; | |
1167 | ||
1168 | `ifdef LIB | |
1169 | assign out = ((sel0 & in0) | | |
1170 | (sel1 & in1) | | |
1171 | (sel2 & in2) | | |
1172 | (sel3 & in3) | | |
1173 | (sel4 & in4) | | |
1174 | (sel5 & in5) | | |
1175 | (sel6 & in6)); | |
1176 | `endif | |
1177 | ||
1178 | endmodule | |
1179 | module cl_sc1gb_aomux7_16x ( | |
1180 | in0, | |
1181 | in1, | |
1182 | in2, | |
1183 | in3, | |
1184 | in4, | |
1185 | in5, | |
1186 | in6, | |
1187 | sel0, | |
1188 | sel1, | |
1189 | sel2, | |
1190 | sel3, | |
1191 | sel4, | |
1192 | sel5, | |
1193 | sel6, | |
1194 | out | |
1195 | ); | |
1196 | input in0; | |
1197 | input in1; | |
1198 | input in2; | |
1199 | input in3; | |
1200 | input in4; | |
1201 | input in5; | |
1202 | input in6; | |
1203 | input sel0; | |
1204 | input sel1; | |
1205 | input sel2; | |
1206 | input sel3; | |
1207 | input sel4; | |
1208 | input sel5; | |
1209 | input sel6; | |
1210 | output out; | |
1211 | ||
1212 | `ifdef LIB | |
1213 | assign out = ((sel0 & in0) | | |
1214 | (sel1 & in1) | | |
1215 | (sel2 & in2) | | |
1216 | (sel3 & in3) | | |
1217 | (sel4 & in4) | | |
1218 | (sel5 & in5) | | |
1219 | (sel6 & in6)); | |
1220 | `endif | |
1221 | ||
1222 | endmodule | |
1223 | module cl_sc1gb_aomux7_1x ( | |
1224 | in0, | |
1225 | in1, | |
1226 | in2, | |
1227 | in3, | |
1228 | in4, | |
1229 | in5, | |
1230 | in6, | |
1231 | sel0, | |
1232 | sel1, | |
1233 | sel2, | |
1234 | sel3, | |
1235 | sel4, | |
1236 | sel5, | |
1237 | sel6, | |
1238 | out | |
1239 | ); | |
1240 | input in0; | |
1241 | input in1; | |
1242 | input in2; | |
1243 | input in3; | |
1244 | input in4; | |
1245 | input in5; | |
1246 | input in6; | |
1247 | input sel0; | |
1248 | input sel1; | |
1249 | input sel2; | |
1250 | input sel3; | |
1251 | input sel4; | |
1252 | input sel5; | |
1253 | input sel6; | |
1254 | output out; | |
1255 | ||
1256 | `ifdef LIB | |
1257 | assign out = ((sel0 & in0) | | |
1258 | (sel1 & in1) | | |
1259 | (sel2 & in2) | | |
1260 | (sel3 & in3) | | |
1261 | (sel4 & in4) | | |
1262 | (sel5 & in5) | | |
1263 | (sel6 & in6)); | |
1264 | `endif | |
1265 | ||
1266 | endmodule | |
1267 | module cl_sc1gb_aomux7_2x ( | |
1268 | in0, | |
1269 | in1, | |
1270 | in2, | |
1271 | in3, | |
1272 | in4, | |
1273 | in5, | |
1274 | in6, | |
1275 | sel0, | |
1276 | sel1, | |
1277 | sel2, | |
1278 | sel3, | |
1279 | sel4, | |
1280 | sel5, | |
1281 | sel6, | |
1282 | out | |
1283 | ); | |
1284 | input in0; | |
1285 | input in1; | |
1286 | input in2; | |
1287 | input in3; | |
1288 | input in4; | |
1289 | input in5; | |
1290 | input in6; | |
1291 | input sel0; | |
1292 | input sel1; | |
1293 | input sel2; | |
1294 | input sel3; | |
1295 | input sel4; | |
1296 | input sel5; | |
1297 | input sel6; | |
1298 | output out; | |
1299 | ||
1300 | `ifdef LIB | |
1301 | assign out = ((sel0 & in0) | | |
1302 | (sel1 & in1) | | |
1303 | (sel2 & in2) | | |
1304 | (sel3 & in3) | | |
1305 | (sel4 & in4) | | |
1306 | (sel5 & in5) | | |
1307 | (sel6 & in6)); | |
1308 | `endif | |
1309 | ||
1310 | endmodule | |
1311 | module cl_sc1gb_aomux7_4x ( | |
1312 | in0, | |
1313 | in1, | |
1314 | in2, | |
1315 | in3, | |
1316 | in4, | |
1317 | in5, | |
1318 | in6, | |
1319 | sel0, | |
1320 | sel1, | |
1321 | sel2, | |
1322 | sel3, | |
1323 | sel4, | |
1324 | sel5, | |
1325 | sel6, | |
1326 | out | |
1327 | ); | |
1328 | input in0; | |
1329 | input in1; | |
1330 | input in2; | |
1331 | input in3; | |
1332 | input in4; | |
1333 | input in5; | |
1334 | input in6; | |
1335 | input sel0; | |
1336 | input sel1; | |
1337 | input sel2; | |
1338 | input sel3; | |
1339 | input sel4; | |
1340 | input sel5; | |
1341 | input sel6; | |
1342 | output out; | |
1343 | ||
1344 | `ifdef LIB | |
1345 | assign out = ((sel0 & in0) | | |
1346 | (sel1 & in1) | | |
1347 | (sel2 & in2) | | |
1348 | (sel3 & in3) | | |
1349 | (sel4 & in4) | | |
1350 | (sel5 & in5) | | |
1351 | (sel6 & in6)); | |
1352 | `endif | |
1353 | ||
1354 | endmodule | |
1355 | module cl_sc1gb_aomux7_6x ( | |
1356 | in0, | |
1357 | in1, | |
1358 | in2, | |
1359 | in3, | |
1360 | in4, | |
1361 | in5, | |
1362 | in6, | |
1363 | sel0, | |
1364 | sel1, | |
1365 | sel2, | |
1366 | sel3, | |
1367 | sel4, | |
1368 | sel5, | |
1369 | sel6, | |
1370 | out | |
1371 | ); | |
1372 | input in0; | |
1373 | input in1; | |
1374 | input in2; | |
1375 | input in3; | |
1376 | input in4; | |
1377 | input in5; | |
1378 | input in6; | |
1379 | input sel0; | |
1380 | input sel1; | |
1381 | input sel2; | |
1382 | input sel3; | |
1383 | input sel4; | |
1384 | input sel5; | |
1385 | input sel6; | |
1386 | output out; | |
1387 | ||
1388 | `ifdef LIB | |
1389 | assign out = ((sel0 & in0) | | |
1390 | (sel1 & in1) | | |
1391 | (sel2 & in2) | | |
1392 | (sel3 & in3) | | |
1393 | (sel4 & in4) | | |
1394 | (sel5 & in5) | | |
1395 | (sel6 & in6)); | |
1396 | `endif | |
1397 | ||
1398 | endmodule | |
1399 | module cl_sc1gb_aomux7_8x ( | |
1400 | in0, | |
1401 | in1, | |
1402 | in2, | |
1403 | in3, | |
1404 | in4, | |
1405 | in5, | |
1406 | in6, | |
1407 | sel0, | |
1408 | sel1, | |
1409 | sel2, | |
1410 | sel3, | |
1411 | sel4, | |
1412 | sel5, | |
1413 | sel6, | |
1414 | out | |
1415 | ); | |
1416 | input in0; | |
1417 | input in1; | |
1418 | input in2; | |
1419 | input in3; | |
1420 | input in4; | |
1421 | input in5; | |
1422 | input in6; | |
1423 | input sel0; | |
1424 | input sel1; | |
1425 | input sel2; | |
1426 | input sel3; | |
1427 | input sel4; | |
1428 | input sel5; | |
1429 | input sel6; | |
1430 | output out; | |
1431 | ||
1432 | `ifdef LIB | |
1433 | assign out = ((sel0 & in0) | | |
1434 | (sel1 & in1) | | |
1435 | (sel2 & in2) | | |
1436 | (sel3 & in3) | | |
1437 | (sel4 & in4) | | |
1438 | (sel5 & in5) | | |
1439 | (sel6 & in6)); | |
1440 | `endif | |
1441 | ||
1442 | endmodule | |
1443 | module cl_sc1gb_aomux7_by2_1x ( | |
1444 | in0, | |
1445 | in1, | |
1446 | in2, | |
1447 | in3, | |
1448 | in4, | |
1449 | in5, | |
1450 | in6, | |
1451 | sel0, | |
1452 | sel1, | |
1453 | sel2, | |
1454 | sel3, | |
1455 | sel4, | |
1456 | sel5, | |
1457 | sel6, | |
1458 | out | |
1459 | ); | |
1460 | input in0; | |
1461 | input in1; | |
1462 | input in2; | |
1463 | input in3; | |
1464 | input in4; | |
1465 | input in5; | |
1466 | input in6; | |
1467 | input sel0; | |
1468 | input sel1; | |
1469 | input sel2; | |
1470 | input sel3; | |
1471 | input sel4; | |
1472 | input sel5; | |
1473 | input sel6; | |
1474 | output out; | |
1475 | ||
1476 | `ifdef LIB | |
1477 | assign out = ((sel0 & in0) | | |
1478 | (sel1 & in1) | | |
1479 | (sel2 & in2) | | |
1480 | (sel3 & in3) | | |
1481 | (sel4 & in4) | | |
1482 | (sel5 & in5) | | |
1483 | (sel6 & in6)); | |
1484 | `endif | |
1485 | ||
1486 | endmodule | |
1487 | module cl_sc1gb_aomux7_by2_2x ( | |
1488 | in0, | |
1489 | in1, | |
1490 | in2, | |
1491 | in3, | |
1492 | in4, | |
1493 | in5, | |
1494 | in6, | |
1495 | sel0, | |
1496 | sel1, | |
1497 | sel2, | |
1498 | sel3, | |
1499 | sel4, | |
1500 | sel5, | |
1501 | sel6, | |
1502 | out | |
1503 | ); | |
1504 | input in0; | |
1505 | input in1; | |
1506 | input in2; | |
1507 | input in3; | |
1508 | input in4; | |
1509 | input in5; | |
1510 | input in6; | |
1511 | input sel0; | |
1512 | input sel1; | |
1513 | input sel2; | |
1514 | input sel3; | |
1515 | input sel4; | |
1516 | input sel5; | |
1517 | input sel6; | |
1518 | output out; | |
1519 | ||
1520 | `ifdef LIB | |
1521 | assign out = ((sel0 & in0) | | |
1522 | (sel1 & in1) | | |
1523 | (sel2 & in2) | | |
1524 | (sel3 & in3) | | |
1525 | (sel4 & in4) | | |
1526 | (sel5 & in5) | | |
1527 | (sel6 & in6)); | |
1528 | `endif | |
1529 | ||
1530 | endmodule | |
1531 | module cl_sc1gb_aomux8_12x ( | |
1532 | in0, | |
1533 | in1, | |
1534 | in2, | |
1535 | in3, | |
1536 | in4, | |
1537 | in5, | |
1538 | in6, | |
1539 | in7, | |
1540 | sel0, | |
1541 | sel1, | |
1542 | sel2, | |
1543 | sel3, | |
1544 | sel4, | |
1545 | sel5, | |
1546 | sel6, | |
1547 | sel7, | |
1548 | out | |
1549 | ); | |
1550 | input in0; | |
1551 | input in1; | |
1552 | input in2; | |
1553 | input in3; | |
1554 | input in4; | |
1555 | input in5; | |
1556 | input in6; | |
1557 | input in7; | |
1558 | input sel0; | |
1559 | input sel1; | |
1560 | input sel2; | |
1561 | input sel3; | |
1562 | input sel4; | |
1563 | input sel5; | |
1564 | input sel6; | |
1565 | input sel7; | |
1566 | output out; | |
1567 | ||
1568 | `ifdef LIB | |
1569 | assign out = ((sel0 & in0) | | |
1570 | (sel1 & in1) | | |
1571 | (sel2 & in2) | | |
1572 | (sel3 & in3) | | |
1573 | (sel4 & in4) | | |
1574 | (sel5 & in5) | | |
1575 | (sel6 & in6) | | |
1576 | (sel7 & in7)); | |
1577 | `endif | |
1578 | ||
1579 | ||
1580 | endmodule | |
1581 | module cl_sc1gb_aomux8_16x ( | |
1582 | in0, | |
1583 | in1, | |
1584 | in2, | |
1585 | in3, | |
1586 | in4, | |
1587 | in5, | |
1588 | in6, | |
1589 | in7, | |
1590 | sel0, | |
1591 | sel1, | |
1592 | sel2, | |
1593 | sel3, | |
1594 | sel4, | |
1595 | sel5, | |
1596 | sel6, | |
1597 | sel7, | |
1598 | out | |
1599 | ); | |
1600 | input in0; | |
1601 | input in1; | |
1602 | input in2; | |
1603 | input in3; | |
1604 | input in4; | |
1605 | input in5; | |
1606 | input in6; | |
1607 | input in7; | |
1608 | input sel0; | |
1609 | input sel1; | |
1610 | input sel2; | |
1611 | input sel3; | |
1612 | input sel4; | |
1613 | input sel5; | |
1614 | input sel6; | |
1615 | input sel7; | |
1616 | output out; | |
1617 | ||
1618 | `ifdef LIB | |
1619 | assign out = ((sel0 & in0) | | |
1620 | (sel1 & in1) | | |
1621 | (sel2 & in2) | | |
1622 | (sel3 & in3) | | |
1623 | (sel4 & in4) | | |
1624 | (sel5 & in5) | | |
1625 | (sel6 & in6) | | |
1626 | (sel7 & in7)); | |
1627 | `endif | |
1628 | ||
1629 | ||
1630 | endmodule | |
1631 | module cl_sc1gb_aomux8_1x ( | |
1632 | in0, | |
1633 | in1, | |
1634 | in2, | |
1635 | in3, | |
1636 | in4, | |
1637 | in5, | |
1638 | in6, | |
1639 | in7, | |
1640 | sel0, | |
1641 | sel1, | |
1642 | sel2, | |
1643 | sel3, | |
1644 | sel4, | |
1645 | sel5, | |
1646 | sel6, | |
1647 | sel7, | |
1648 | out | |
1649 | ); | |
1650 | input in0; | |
1651 | input in1; | |
1652 | input in2; | |
1653 | input in3; | |
1654 | input in4; | |
1655 | input in5; | |
1656 | input in6; | |
1657 | input in7; | |
1658 | input sel0; | |
1659 | input sel1; | |
1660 | input sel2; | |
1661 | input sel3; | |
1662 | input sel4; | |
1663 | input sel5; | |
1664 | input sel6; | |
1665 | input sel7; | |
1666 | output out; | |
1667 | ||
1668 | `ifdef LIB | |
1669 | assign out = ((sel0 & in0) | | |
1670 | (sel1 & in1) | | |
1671 | (sel2 & in2) | | |
1672 | (sel3 & in3) | | |
1673 | (sel4 & in4) | | |
1674 | (sel5 & in5) | | |
1675 | (sel6 & in6) | | |
1676 | (sel7 & in7)); | |
1677 | `endif | |
1678 | ||
1679 | ||
1680 | endmodule | |
1681 | module cl_sc1gb_aomux8_2x ( | |
1682 | in0, | |
1683 | in1, | |
1684 | in2, | |
1685 | in3, | |
1686 | in4, | |
1687 | in5, | |
1688 | in6, | |
1689 | in7, | |
1690 | sel0, | |
1691 | sel1, | |
1692 | sel2, | |
1693 | sel3, | |
1694 | sel4, | |
1695 | sel5, | |
1696 | sel6, | |
1697 | sel7, | |
1698 | out | |
1699 | ); | |
1700 | input in0; | |
1701 | input in1; | |
1702 | input in2; | |
1703 | input in3; | |
1704 | input in4; | |
1705 | input in5; | |
1706 | input in6; | |
1707 | input in7; | |
1708 | input sel0; | |
1709 | input sel1; | |
1710 | input sel2; | |
1711 | input sel3; | |
1712 | input sel4; | |
1713 | input sel5; | |
1714 | input sel6; | |
1715 | input sel7; | |
1716 | output out; | |
1717 | ||
1718 | `ifdef LIB | |
1719 | assign out = ((sel0 & in0) | | |
1720 | (sel1 & in1) | | |
1721 | (sel2 & in2) | | |
1722 | (sel3 & in3) | | |
1723 | (sel4 & in4) | | |
1724 | (sel5 & in5) | | |
1725 | (sel6 & in6) | | |
1726 | (sel7 & in7)); | |
1727 | `endif | |
1728 | ||
1729 | ||
1730 | endmodule | |
1731 | module cl_sc1gb_aomux8_4x ( | |
1732 | in0, | |
1733 | in1, | |
1734 | in2, | |
1735 | in3, | |
1736 | in4, | |
1737 | in5, | |
1738 | in6, | |
1739 | in7, | |
1740 | sel0, | |
1741 | sel1, | |
1742 | sel2, | |
1743 | sel3, | |
1744 | sel4, | |
1745 | sel5, | |
1746 | sel6, | |
1747 | sel7, | |
1748 | out | |
1749 | ); | |
1750 | input in0; | |
1751 | input in1; | |
1752 | input in2; | |
1753 | input in3; | |
1754 | input in4; | |
1755 | input in5; | |
1756 | input in6; | |
1757 | input in7; | |
1758 | input sel0; | |
1759 | input sel1; | |
1760 | input sel2; | |
1761 | input sel3; | |
1762 | input sel4; | |
1763 | input sel5; | |
1764 | input sel6; | |
1765 | input sel7; | |
1766 | output out; | |
1767 | ||
1768 | `ifdef LIB | |
1769 | assign out = ((sel0 & in0) | | |
1770 | (sel1 & in1) | | |
1771 | (sel2 & in2) | | |
1772 | (sel3 & in3) | | |
1773 | (sel4 & in4) | | |
1774 | (sel5 & in5) | | |
1775 | (sel6 & in6) | | |
1776 | (sel7 & in7)); | |
1777 | `endif | |
1778 | ||
1779 | ||
1780 | endmodule | |
1781 | module cl_sc1gb_aomux8_6x ( | |
1782 | in0, | |
1783 | in1, | |
1784 | in2, | |
1785 | in3, | |
1786 | in4, | |
1787 | in5, | |
1788 | in6, | |
1789 | in7, | |
1790 | sel0, | |
1791 | sel1, | |
1792 | sel2, | |
1793 | sel3, | |
1794 | sel4, | |
1795 | sel5, | |
1796 | sel6, | |
1797 | sel7, | |
1798 | out | |
1799 | ); | |
1800 | input in0; | |
1801 | input in1; | |
1802 | input in2; | |
1803 | input in3; | |
1804 | input in4; | |
1805 | input in5; | |
1806 | input in6; | |
1807 | input in7; | |
1808 | input sel0; | |
1809 | input sel1; | |
1810 | input sel2; | |
1811 | input sel3; | |
1812 | input sel4; | |
1813 | input sel5; | |
1814 | input sel6; | |
1815 | input sel7; | |
1816 | output out; | |
1817 | ||
1818 | `ifdef LIB | |
1819 | assign out = ((sel0 & in0) | | |
1820 | (sel1 & in1) | | |
1821 | (sel2 & in2) | | |
1822 | (sel3 & in3) | | |
1823 | (sel4 & in4) | | |
1824 | (sel5 & in5) | | |
1825 | (sel6 & in6) | | |
1826 | (sel7 & in7)); | |
1827 | `endif | |
1828 | ||
1829 | ||
1830 | endmodule | |
1831 | module cl_sc1gb_aomux8_8x ( | |
1832 | in0, | |
1833 | in1, | |
1834 | in2, | |
1835 | in3, | |
1836 | in4, | |
1837 | in5, | |
1838 | in6, | |
1839 | in7, | |
1840 | sel0, | |
1841 | sel1, | |
1842 | sel2, | |
1843 | sel3, | |
1844 | sel4, | |
1845 | sel5, | |
1846 | sel6, | |
1847 | sel7, | |
1848 | out | |
1849 | ); | |
1850 | input in0; | |
1851 | input in1; | |
1852 | input in2; | |
1853 | input in3; | |
1854 | input in4; | |
1855 | input in5; | |
1856 | input in6; | |
1857 | input in7; | |
1858 | input sel0; | |
1859 | input sel1; | |
1860 | input sel2; | |
1861 | input sel3; | |
1862 | input sel4; | |
1863 | input sel5; | |
1864 | input sel6; | |
1865 | input sel7; | |
1866 | output out; | |
1867 | ||
1868 | `ifdef LIB | |
1869 | assign out = ((sel0 & in0) | | |
1870 | (sel1 & in1) | | |
1871 | (sel2 & in2) | | |
1872 | (sel3 & in3) | | |
1873 | (sel4 & in4) | | |
1874 | (sel5 & in5) | | |
1875 | (sel6 & in6) | | |
1876 | (sel7 & in7)); | |
1877 | `endif | |
1878 | ||
1879 | ||
1880 | endmodule | |
1881 | module cl_sc1gb_aomux8_by2_1x ( | |
1882 | in0, | |
1883 | in1, | |
1884 | in2, | |
1885 | in3, | |
1886 | in4, | |
1887 | in5, | |
1888 | in6, | |
1889 | in7, | |
1890 | sel0, | |
1891 | sel1, | |
1892 | sel2, | |
1893 | sel3, | |
1894 | sel4, | |
1895 | sel5, | |
1896 | sel6, | |
1897 | sel7, | |
1898 | out | |
1899 | ); | |
1900 | input in0; | |
1901 | input in1; | |
1902 | input in2; | |
1903 | input in3; | |
1904 | input in4; | |
1905 | input in5; | |
1906 | input in6; | |
1907 | input in7; | |
1908 | input sel0; | |
1909 | input sel1; | |
1910 | input sel2; | |
1911 | input sel3; | |
1912 | input sel4; | |
1913 | input sel5; | |
1914 | input sel6; | |
1915 | input sel7; | |
1916 | output out; | |
1917 | ||
1918 | `ifdef LIB | |
1919 | assign out = ((sel0 & in0) | | |
1920 | (sel1 & in1) | | |
1921 | (sel2 & in2) | | |
1922 | (sel3 & in3) | | |
1923 | (sel4 & in4) | | |
1924 | (sel5 & in5) | | |
1925 | (sel6 & in6) | | |
1926 | (sel7 & in7)); | |
1927 | `endif | |
1928 | ||
1929 | ||
1930 | endmodule | |
1931 | module cl_sc1gb_aomux8_by2_2x ( | |
1932 | in0, | |
1933 | in1, | |
1934 | in2, | |
1935 | in3, | |
1936 | in4, | |
1937 | in5, | |
1938 | in6, | |
1939 | in7, | |
1940 | sel0, | |
1941 | sel1, | |
1942 | sel2, | |
1943 | sel3, | |
1944 | sel4, | |
1945 | sel5, | |
1946 | sel6, | |
1947 | sel7, | |
1948 | out | |
1949 | ); | |
1950 | input in0; | |
1951 | input in1; | |
1952 | input in2; | |
1953 | input in3; | |
1954 | input in4; | |
1955 | input in5; | |
1956 | input in6; | |
1957 | input in7; | |
1958 | input sel0; | |
1959 | input sel1; | |
1960 | input sel2; | |
1961 | input sel3; | |
1962 | input sel4; | |
1963 | input sel5; | |
1964 | input sel6; | |
1965 | input sel7; | |
1966 | output out; | |
1967 | ||
1968 | `ifdef LIB | |
1969 | assign out = ((sel0 & in0) | | |
1970 | (sel1 & in1) | | |
1971 | (sel2 & in2) | | |
1972 | (sel3 & in3) | | |
1973 | (sel4 & in4) | | |
1974 | (sel5 & in5) | | |
1975 | (sel6 & in6) | | |
1976 | (sel7 & in7)); | |
1977 | `endif | |
1978 | ||
1979 | ||
1980 | endmodule |