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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_u1gb.behV | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_u1gb_aoi12_12x ( | |
36 | out, | |
37 | in10, | |
38 | in00, | |
39 | in01 ); | |
40 | ||
41 | output out; | |
42 | input in10; | |
43 | input in00; | |
44 | input in01; | |
45 | ||
46 | `ifdef LIB | |
47 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
48 | `endif | |
49 | ||
50 | endmodule | |
51 | // -------------------------------------------------- | |
52 | // File: cl_u1gb_aoi12_16x.behV | |
53 | // Auto generated verilog module by HnBCellAuto | |
54 | // | |
55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
56 | // By: balmiki | |
57 | // -------------------------------------------------- | |
58 | // | |
59 | module cl_u1gb_aoi12_16x ( | |
60 | out, | |
61 | in10, | |
62 | in00, | |
63 | in01 ); | |
64 | ||
65 | output out; | |
66 | input in10; | |
67 | input in00; | |
68 | input in01; | |
69 | ||
70 | `ifdef LIB | |
71 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
72 | `endif | |
73 | ||
74 | endmodule | |
75 | // -------------------------------------------------- | |
76 | // File: cl_u1gb_aoi12_1x.behV | |
77 | // Auto generated verilog module by HnBCellAuto | |
78 | // | |
79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST | |
80 | // By: balmiki | |
81 | // -------------------------------------------------- | |
82 | // | |
83 | module cl_u1gb_aoi12_1x ( | |
84 | out, | |
85 | in10, | |
86 | in00, | |
87 | in01 ); | |
88 | ||
89 | output out; | |
90 | input in10; | |
91 | input in00; | |
92 | input in01; | |
93 | ||
94 | `ifdef LIB | |
95 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
96 | `endif | |
97 | ||
98 | endmodule | |
99 | // -------------------------------------------------- | |
100 | // File: cl_u1gb_aoi12_2x.behV | |
101 | // Auto generated verilog module by HnBCellAuto | |
102 | // | |
103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
104 | // By: balmiki | |
105 | // -------------------------------------------------- | |
106 | // | |
107 | module cl_u1gb_aoi12_2x ( | |
108 | out, | |
109 | in10, | |
110 | in00, | |
111 | in01 ); | |
112 | ||
113 | output out; | |
114 | input in10; | |
115 | input in00; | |
116 | input in01; | |
117 | ||
118 | `ifdef LIB | |
119 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
120 | `endif | |
121 | ||
122 | endmodule | |
123 | // -------------------------------------------------- | |
124 | // File: cl_u1gb_aoi12_4x.behV | |
125 | // Auto generated verilog module by HnBCellAuto | |
126 | // | |
127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
128 | // By: balmiki | |
129 | // -------------------------------------------------- | |
130 | // | |
131 | module cl_u1gb_aoi12_4x ( | |
132 | out, | |
133 | in10, | |
134 | in00, | |
135 | in01 ); | |
136 | ||
137 | output out; | |
138 | input in10; | |
139 | input in00; | |
140 | input in01; | |
141 | ||
142 | `ifdef LIB | |
143 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
144 | `endif | |
145 | ||
146 | endmodule | |
147 | // -------------------------------------------------- | |
148 | // File: cl_u1gb_aoi12_8x.behV | |
149 | // Auto generated verilog module by HnBCellAuto | |
150 | // | |
151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
152 | // By: balmiki | |
153 | // -------------------------------------------------- | |
154 | // | |
155 | module cl_u1gb_aoi12_8x ( | |
156 | out, | |
157 | in10, | |
158 | in00, | |
159 | in01 ); | |
160 | ||
161 | output out; | |
162 | input in10; | |
163 | input in00; | |
164 | input in01; | |
165 | ||
166 | `ifdef LIB | |
167 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
168 | `endif | |
169 | ||
170 | endmodule | |
171 | // -------------------------------------------------- | |
172 | // File: cl_u1gb_aoi21_12x.behV | |
173 | // Auto generated verilog module by HnBCellAuto | |
174 | // | |
175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
176 | // By: balmiki | |
177 | // -------------------------------------------------- | |
178 | // | |
179 | module cl_u1gb_aoi21_12x ( | |
180 | out, | |
181 | in10, | |
182 | in11, | |
183 | in00 ); | |
184 | ||
185 | output out; | |
186 | input in10; | |
187 | input in11; | |
188 | input in00; | |
189 | ||
190 | `ifdef LIB | |
191 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
192 | `endif | |
193 | ||
194 | endmodule | |
195 | // -------------------------------------------------- | |
196 | // File: cl_u1gb_aoi21_16x.behV | |
197 | // Auto generated verilog module by HnBCellAuto | |
198 | // | |
199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
200 | // By: balmiki | |
201 | // -------------------------------------------------- | |
202 | // | |
203 | module cl_u1gb_aoi21_16x ( | |
204 | out, | |
205 | in10, | |
206 | in11, | |
207 | in00 ); | |
208 | ||
209 | output out; | |
210 | input in10; | |
211 | input in11; | |
212 | input in00; | |
213 | ||
214 | `ifdef LIB | |
215 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
216 | `endif | |
217 | ||
218 | endmodule | |
219 | // -------------------------------------------------- | |
220 | // File: cl_u1gb_aoi21_1x.behV | |
221 | // Auto generated verilog module by HnBCellAuto | |
222 | // | |
223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
224 | // By: balmiki | |
225 | // -------------------------------------------------- | |
226 | // | |
227 | module cl_u1gb_aoi21_1x ( | |
228 | out, | |
229 | in10, | |
230 | in11, | |
231 | in00 ); | |
232 | ||
233 | output out; | |
234 | input in10; | |
235 | input in11; | |
236 | input in00; | |
237 | ||
238 | `ifdef LIB | |
239 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
240 | `endif | |
241 | ||
242 | endmodule | |
243 | // -------------------------------------------------- | |
244 | // File: cl_u1gb_aoi21_2x.behV | |
245 | // Auto generated verilog module by HnBCellAuto | |
246 | // | |
247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
248 | // By: balmiki | |
249 | // -------------------------------------------------- | |
250 | // | |
251 | module cl_u1gb_aoi21_2x ( | |
252 | out, | |
253 | in10, | |
254 | in11, | |
255 | in00 ); | |
256 | ||
257 | output out; | |
258 | input in10; | |
259 | input in11; | |
260 | input in00; | |
261 | ||
262 | `ifdef LIB | |
263 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
264 | `endif | |
265 | ||
266 | endmodule | |
267 | // -------------------------------------------------- | |
268 | // File: cl_u1gb_aoi21_4x.behV | |
269 | // Auto generated verilog module by HnBCellAuto | |
270 | // | |
271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
272 | // By: balmiki | |
273 | // -------------------------------------------------- | |
274 | // | |
275 | module cl_u1gb_aoi21_4x ( | |
276 | out, | |
277 | in10, | |
278 | in11, | |
279 | in00 ); | |
280 | ||
281 | output out; | |
282 | input in10; | |
283 | input in11; | |
284 | input in00; | |
285 | ||
286 | `ifdef LIB | |
287 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
288 | `endif | |
289 | ||
290 | endmodule | |
291 | // -------------------------------------------------- | |
292 | // File: cl_u1gb_aoi21_8x.behV | |
293 | // Auto generated verilog module by HnBCellAuto | |
294 | // | |
295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
296 | // By: balmiki | |
297 | // -------------------------------------------------- | |
298 | // | |
299 | module cl_u1gb_aoi21_8x ( | |
300 | out, | |
301 | in10, | |
302 | in11, | |
303 | in00 ); | |
304 | ||
305 | output out; | |
306 | input in10; | |
307 | input in11; | |
308 | input in00; | |
309 | ||
310 | `ifdef LIB | |
311 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
312 | `endif | |
313 | ||
314 | endmodule | |
315 | // -------------------------------------------------- | |
316 | // File: cl_u1gb_aoi22_12x.behV | |
317 | // Auto generated verilog module by HnBCellAuto | |
318 | // | |
319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
320 | // By: balmiki | |
321 | // -------------------------------------------------- | |
322 | // | |
323 | module cl_u1gb_aoi22_12x ( | |
324 | out, | |
325 | in10, | |
326 | in11, | |
327 | in00, | |
328 | in01 ); | |
329 | ||
330 | output out; | |
331 | input in10; | |
332 | input in11; | |
333 | input in00; | |
334 | input in01; | |
335 | ||
336 | `ifdef LIB | |
337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
338 | `endif | |
339 | ||
340 | endmodule | |
341 | ||
342 | // -------------------------------------------------- | |
343 | // File: cl_u1gb_aoi22_1x.behV | |
344 | // Auto generated verilog module by HnBCellAuto | |
345 | // | |
346 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT | |
347 | // By: balmiki | |
348 | // -------------------------------------------------- | |
349 | // | |
350 | module cl_u1gb_aoi22_1x ( | |
351 | out, | |
352 | in10, | |
353 | in11, | |
354 | in00, | |
355 | in01 ); | |
356 | ||
357 | output out; | |
358 | input in10; | |
359 | input in11; | |
360 | input in00; | |
361 | input in01; | |
362 | ||
363 | `ifdef LIB | |
364 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
365 | `endif | |
366 | ||
367 | endmodule | |
368 | // -------------------------------------------------- | |
369 | // File: cl_u1gb_aoi22_2x.behV | |
370 | // Auto generated verilog module by HnBCellAuto | |
371 | // | |
372 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
373 | // By: balmiki | |
374 | // -------------------------------------------------- | |
375 | // | |
376 | module cl_u1gb_aoi22_2x ( | |
377 | out, | |
378 | in10, | |
379 | in11, | |
380 | in00, | |
381 | in01 ); | |
382 | ||
383 | output out; | |
384 | input in10; | |
385 | input in11; | |
386 | input in00; | |
387 | input in01; | |
388 | ||
389 | `ifdef LIB | |
390 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
391 | `endif | |
392 | ||
393 | endmodule | |
394 | // -------------------------------------------------- | |
395 | // File: cl_u1gb_aoi22_4x.behV | |
396 | // Auto generated verilog module by HnBCellAuto | |
397 | // | |
398 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
399 | // By: balmiki | |
400 | // -------------------------------------------------- | |
401 | // | |
402 | module cl_u1gb_aoi22_4x ( | |
403 | out, | |
404 | in10, | |
405 | in11, | |
406 | in00, | |
407 | in01 ); | |
408 | ||
409 | output out; | |
410 | input in10; | |
411 | input in11; | |
412 | input in00; | |
413 | input in01; | |
414 | ||
415 | `ifdef LIB | |
416 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
417 | `endif | |
418 | ||
419 | endmodule | |
420 | // -------------------------------------------------- | |
421 | // File: cl_u1gb_aoi22_8x.behV | |
422 | // Auto generated verilog module by HnBCellAuto | |
423 | // | |
424 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
425 | // By: balmiki | |
426 | // -------------------------------------------------- | |
427 | // | |
428 | module cl_u1gb_aoi22_8x ( | |
429 | out, | |
430 | in10, | |
431 | in11, | |
432 | in00, | |
433 | in01 ); | |
434 | ||
435 | output out; | |
436 | input in10; | |
437 | input in11; | |
438 | input in00; | |
439 | input in01; | |
440 | ||
441 | `ifdef LIB | |
442 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
443 | `endif | |
444 | ||
445 | endmodule | |
446 | ||
447 | ||
448 | // -------------------------------------------------- | |
449 | // File: cl_u1gb_aoi33_1x.behV | |
450 | // Auto generated verilog module by HnBCellAuto | |
451 | // | |
452 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST | |
453 | // By: balmiki | |
454 | // -------------------------------------------------- | |
455 | // | |
456 | module cl_u1gb_aoi33_1x ( | |
457 | out, | |
458 | in10, | |
459 | in11, | |
460 | in12, | |
461 | in00, | |
462 | in01, | |
463 | in02 ); | |
464 | ||
465 | output out; | |
466 | input in10; | |
467 | input in11; | |
468 | input in12; | |
469 | input in00; | |
470 | input in01; | |
471 | input in02; | |
472 | ||
473 | `ifdef LIB | |
474 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
475 | `endif | |
476 | ||
477 | endmodule | |
478 | // -------------------------------------------------- | |
479 | // File: cl_u1gb_aoi33_2x.behV | |
480 | // Auto generated verilog module by HnBCellAuto | |
481 | // | |
482 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
483 | // By: balmiki | |
484 | // -------------------------------------------------- | |
485 | // | |
486 | module cl_u1gb_aoi33_2x ( | |
487 | out, | |
488 | in10, | |
489 | in11, | |
490 | in12, | |
491 | in00, | |
492 | in01, | |
493 | in02 ); | |
494 | ||
495 | output out; | |
496 | input in10; | |
497 | input in11; | |
498 | input in12; | |
499 | input in00; | |
500 | input in01; | |
501 | input in02; | |
502 | ||
503 | `ifdef LIB | |
504 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
505 | `endif | |
506 | ||
507 | endmodule | |
508 | // -------------------------------------------------- | |
509 | // File: cl_u1gb_aoi33_4x.behV | |
510 | // Auto generated verilog module by HnBCellAuto | |
511 | // | |
512 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
513 | // By: balmiki | |
514 | // -------------------------------------------------- | |
515 | // | |
516 | module cl_u1gb_aoi33_4x ( | |
517 | out, | |
518 | in10, | |
519 | in11, | |
520 | in12, | |
521 | in00, | |
522 | in01, | |
523 | in02 ); | |
524 | ||
525 | output out; | |
526 | input in10; | |
527 | input in11; | |
528 | input in12; | |
529 | input in00; | |
530 | input in01; | |
531 | input in02; | |
532 | ||
533 | `ifdef LIB | |
534 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
535 | `endif | |
536 | ||
537 | endmodule | |
538 | // -------------------------------------------------- | |
539 | // File: cl_u1gb_aoi33_8x.behV | |
540 | // Auto generated verilog module by HnBCellAuto | |
541 | // | |
542 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
543 | // By: balmiki | |
544 | // -------------------------------------------------- | |
545 | // | |
546 | module cl_u1gb_aoi33_8x ( | |
547 | out, | |
548 | in10, | |
549 | in11, | |
550 | in12, | |
551 | in00, | |
552 | in01, | |
553 | in02 ); | |
554 | ||
555 | output out; | |
556 | input in10; | |
557 | input in11; | |
558 | input in12; | |
559 | input in00; | |
560 | input in01; | |
561 | input in02; | |
562 | ||
563 | `ifdef LIB | |
564 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
565 | `endif | |
566 | ||
567 | endmodule | |
568 | ||
569 | ||
570 | module cl_u1gb_buf_12x ( | |
571 | in, | |
572 | out | |
573 | ); | |
574 | input in; | |
575 | output out; | |
576 | ||
577 | `ifdef LIB | |
578 | assign out = in; | |
579 | `endif | |
580 | ||
581 | endmodule | |
582 | module cl_u1gb_buf_16x ( | |
583 | in, | |
584 | out | |
585 | ); | |
586 | input in; | |
587 | output out; | |
588 | ||
589 | `ifdef LIB | |
590 | assign out = in; | |
591 | `endif | |
592 | ||
593 | endmodule | |
594 | module cl_u1gb_buf_1x ( | |
595 | in, | |
596 | out | |
597 | ); | |
598 | input in; | |
599 | output out; | |
600 | ||
601 | `ifdef LIB | |
602 | assign out = in; | |
603 | `endif | |
604 | ||
605 | endmodule | |
606 | module cl_u1gb_buf_20x ( | |
607 | in, | |
608 | out | |
609 | ); | |
610 | input in; | |
611 | output out; | |
612 | ||
613 | `ifdef LIB | |
614 | assign out = in; | |
615 | `endif | |
616 | ||
617 | endmodule | |
618 | module cl_u1gb_buf_24x ( | |
619 | in, | |
620 | out | |
621 | ); | |
622 | input in; | |
623 | output out; | |
624 | ||
625 | `ifdef LIB | |
626 | assign out = in; | |
627 | `endif | |
628 | ||
629 | endmodule | |
630 | module cl_u1gb_buf_28x ( | |
631 | in, | |
632 | out | |
633 | ); | |
634 | input in; | |
635 | output out; | |
636 | ||
637 | `ifdef LIB | |
638 | assign out = in; | |
639 | `endif | |
640 | ||
641 | endmodule | |
642 | module cl_u1gb_buf_2x ( | |
643 | in, | |
644 | out | |
645 | ); | |
646 | input in; | |
647 | output out; | |
648 | ||
649 | `ifdef LIB | |
650 | assign out = in; | |
651 | `endif | |
652 | ||
653 | endmodule | |
654 | module cl_u1gb_buf_32x ( | |
655 | in, | |
656 | out | |
657 | ); | |
658 | input in; | |
659 | output out; | |
660 | ||
661 | `ifdef LIB | |
662 | assign out = in; | |
663 | `endif | |
664 | ||
665 | endmodule | |
666 | module cl_u1gb_buf_36x ( | |
667 | in, | |
668 | out | |
669 | ); | |
670 | input in; | |
671 | output out; | |
672 | ||
673 | `ifdef LIB | |
674 | assign out = in; | |
675 | `endif | |
676 | ||
677 | endmodule | |
678 | module cl_u1gb_buf_40x ( | |
679 | in, | |
680 | out | |
681 | ); | |
682 | input in; | |
683 | output out; | |
684 | ||
685 | `ifdef LIB | |
686 | assign out = in; | |
687 | `endif | |
688 | ||
689 | endmodule | |
690 | module cl_u1gb_buf_44x ( | |
691 | in, | |
692 | out | |
693 | ); | |
694 | input in; | |
695 | output out; | |
696 | ||
697 | `ifdef LIB | |
698 | assign out = in; | |
699 | `endif | |
700 | ||
701 | endmodule | |
702 | module cl_u1gb_buf_48x ( | |
703 | in, | |
704 | out | |
705 | ); | |
706 | input in; | |
707 | output out; | |
708 | ||
709 | `ifdef LIB | |
710 | assign out = in; | |
711 | `endif | |
712 | ||
713 | endmodule | |
714 | module cl_u1gb_buf_4x ( | |
715 | in, | |
716 | out | |
717 | ); | |
718 | input in; | |
719 | output out; | |
720 | ||
721 | `ifdef LIB | |
722 | assign out = in; | |
723 | `endif | |
724 | ||
725 | endmodule | |
726 | module cl_u1gb_buf_56x ( | |
727 | in, | |
728 | out | |
729 | ); | |
730 | input in; | |
731 | output out; | |
732 | ||
733 | `ifdef LIB | |
734 | assign out = in; | |
735 | `endif | |
736 | ||
737 | endmodule | |
738 | module cl_u1gb_buf_64x ( | |
739 | in, | |
740 | out | |
741 | ); | |
742 | input in; | |
743 | output out; | |
744 | ||
745 | `ifdef LIB | |
746 | assign out = in; | |
747 | `endif | |
748 | ||
749 | endmodule | |
750 | module cl_u1gb_buf_6x ( | |
751 | in, | |
752 | out | |
753 | ); | |
754 | input in; | |
755 | output out; | |
756 | ||
757 | `ifdef LIB | |
758 | assign out = in; | |
759 | `endif | |
760 | ||
761 | endmodule | |
762 | module cl_u1gb_buf_8x ( | |
763 | in, | |
764 | out | |
765 | ); | |
766 | input in; | |
767 | output out; | |
768 | ||
769 | `ifdef LIB | |
770 | assign out = in; | |
771 | `endif | |
772 | ||
773 | endmodule | |
774 | module cl_u1gb_bufmin_1x ( | |
775 | in, | |
776 | out | |
777 | ); | |
778 | input in; | |
779 | output out; | |
780 | ||
781 | `ifdef LIB | |
782 | assign out = in; | |
783 | `endif | |
784 | ||
785 | endmodule | |
786 | ||
787 | module cl_u1gb_bufmin_16x ( | |
788 | in, | |
789 | out | |
790 | ); | |
791 | input in; | |
792 | output out; | |
793 | ||
794 | `ifdef LIB | |
795 | assign out = in; | |
796 | `endif | |
797 | ||
798 | endmodule | |
799 | module cl_u1gb_bufmin_32x ( | |
800 | in, | |
801 | out | |
802 | ); | |
803 | input in; | |
804 | output out; | |
805 | ||
806 | `ifdef LIB | |
807 | assign out = in; | |
808 | `endif | |
809 | ||
810 | endmodule | |
811 | ||
812 | module cl_u1gb_inv_12x ( | |
813 | in, | |
814 | out | |
815 | ); | |
816 | input in; | |
817 | output out; | |
818 | ||
819 | `ifdef LIB | |
820 | assign out = ~in; | |
821 | `endif | |
822 | ||
823 | endmodule | |
824 | module cl_u1gb_inv_16x ( | |
825 | in, | |
826 | out | |
827 | ); | |
828 | input in; | |
829 | output out; | |
830 | ||
831 | `ifdef LIB | |
832 | assign out = ~in; | |
833 | `endif | |
834 | ||
835 | endmodule | |
836 | module cl_u1gb_inv_1x ( | |
837 | in, | |
838 | out | |
839 | ); | |
840 | input in; | |
841 | output out; | |
842 | ||
843 | `ifdef LIB | |
844 | assign out = ~in; | |
845 | `endif | |
846 | ||
847 | endmodule | |
848 | module cl_u1gb_inv_20x ( | |
849 | in, | |
850 | out | |
851 | ); | |
852 | input in; | |
853 | output out; | |
854 | ||
855 | `ifdef LIB | |
856 | assign out = ~in; | |
857 | `endif | |
858 | ||
859 | endmodule | |
860 | module cl_u1gb_inv_24x ( | |
861 | in, | |
862 | out | |
863 | ); | |
864 | input in; | |
865 | output out; | |
866 | ||
867 | `ifdef LIB | |
868 | assign out = ~in; | |
869 | `endif | |
870 | ||
871 | endmodule | |
872 | module cl_u1gb_inv_28x ( | |
873 | in, | |
874 | out | |
875 | ); | |
876 | input in; | |
877 | output out; | |
878 | ||
879 | `ifdef LIB | |
880 | assign out = ~in; | |
881 | `endif | |
882 | ||
883 | endmodule | |
884 | module cl_u1gb_inv_2x ( | |
885 | in, | |
886 | out | |
887 | ); | |
888 | input in; | |
889 | output out; | |
890 | ||
891 | `ifdef LIB | |
892 | assign out = ~in; | |
893 | `endif | |
894 | ||
895 | endmodule | |
896 | module cl_u1gb_inv_32x ( | |
897 | in, | |
898 | out | |
899 | ); | |
900 | input in; | |
901 | output out; | |
902 | ||
903 | `ifdef LIB | |
904 | assign out = ~in; | |
905 | `endif | |
906 | ||
907 | endmodule | |
908 | module cl_u1gb_inv_36x ( | |
909 | in, | |
910 | out | |
911 | ); | |
912 | input in; | |
913 | output out; | |
914 | ||
915 | `ifdef LIB | |
916 | assign out = ~in; | |
917 | `endif | |
918 | ||
919 | endmodule | |
920 | module cl_u1gb_inv_40x ( | |
921 | in, | |
922 | out | |
923 | ); | |
924 | input in; | |
925 | output out; | |
926 | ||
927 | `ifdef LIB | |
928 | assign out = ~in; | |
929 | `endif | |
930 | ||
931 | endmodule | |
932 | module cl_u1gb_inv_44x ( | |
933 | in, | |
934 | out | |
935 | ); | |
936 | input in; | |
937 | output out; | |
938 | ||
939 | `ifdef LIB | |
940 | assign out = ~in; | |
941 | `endif | |
942 | ||
943 | endmodule | |
944 | module cl_u1gb_inv_48x ( | |
945 | in, | |
946 | out | |
947 | ); | |
948 | input in; | |
949 | output out; | |
950 | ||
951 | `ifdef LIB | |
952 | assign out = ~in; | |
953 | `endif | |
954 | ||
955 | endmodule | |
956 | module cl_u1gb_inv_4x ( | |
957 | in, | |
958 | out | |
959 | ); | |
960 | input in; | |
961 | output out; | |
962 | ||
963 | `ifdef LIB | |
964 | assign out = ~in; | |
965 | `endif | |
966 | ||
967 | endmodule | |
968 | module cl_u1gb_inv_56x ( | |
969 | in, | |
970 | out | |
971 | ); | |
972 | input in; | |
973 | output out; | |
974 | ||
975 | `ifdef LIB | |
976 | assign out = ~in; | |
977 | `endif | |
978 | ||
979 | endmodule | |
980 | module cl_u1gb_inv_64x ( | |
981 | in, | |
982 | out | |
983 | ); | |
984 | input in; | |
985 | output out; | |
986 | ||
987 | `ifdef LIB | |
988 | assign out = ~in; | |
989 | `endif | |
990 | ||
991 | endmodule | |
992 | module cl_u1gb_inv_6x ( | |
993 | in, | |
994 | out | |
995 | ); | |
996 | input in; | |
997 | output out; | |
998 | ||
999 | `ifdef LIB | |
1000 | assign out = ~in; | |
1001 | `endif | |
1002 | ||
1003 | endmodule | |
1004 | module cl_u1gb_inv_8x ( | |
1005 | in, | |
1006 | out | |
1007 | ); | |
1008 | input in; | |
1009 | output out; | |
1010 | ||
1011 | `ifdef LIB | |
1012 | assign out = ~in; | |
1013 | `endif | |
1014 | ||
1015 | endmodule | |
1016 | module cl_u1gb_nand2_12x ( | |
1017 | in0, | |
1018 | in1, | |
1019 | out | |
1020 | ); | |
1021 | input in0; | |
1022 | input in1; | |
1023 | output out; | |
1024 | ||
1025 | `ifdef LIB | |
1026 | assign out = ~(in0 & in1); | |
1027 | `endif | |
1028 | ||
1029 | endmodule | |
1030 | module cl_u1gb_nand2_16x ( | |
1031 | in0, | |
1032 | in1, | |
1033 | out | |
1034 | ); | |
1035 | input in0; | |
1036 | input in1; | |
1037 | output out; | |
1038 | ||
1039 | `ifdef LIB | |
1040 | assign out = ~(in0 & in1); | |
1041 | `endif | |
1042 | ||
1043 | endmodule | |
1044 | module cl_u1gb_nand2_1x ( | |
1045 | in0, | |
1046 | in1, | |
1047 | out | |
1048 | ); | |
1049 | input in0; | |
1050 | input in1; | |
1051 | output out; | |
1052 | ||
1053 | `ifdef LIB | |
1054 | assign out = ~(in0 & in1); | |
1055 | `endif | |
1056 | ||
1057 | endmodule | |
1058 | module cl_u1gb_nand2_20x ( | |
1059 | in0, | |
1060 | in1, | |
1061 | out | |
1062 | ); | |
1063 | input in0; | |
1064 | input in1; | |
1065 | output out; | |
1066 | ||
1067 | `ifdef LIB | |
1068 | assign out = ~(in0 & in1); | |
1069 | `endif | |
1070 | ||
1071 | endmodule | |
1072 | module cl_u1gb_nand2_24x ( | |
1073 | in0, | |
1074 | in1, | |
1075 | out | |
1076 | ); | |
1077 | input in0; | |
1078 | input in1; | |
1079 | output out; | |
1080 | ||
1081 | `ifdef LIB | |
1082 | assign out = ~(in0 & in1); | |
1083 | `endif | |
1084 | ||
1085 | endmodule | |
1086 | module cl_u1gb_nand2_28x ( | |
1087 | in0, | |
1088 | in1, | |
1089 | out | |
1090 | ); | |
1091 | input in0; | |
1092 | input in1; | |
1093 | output out; | |
1094 | ||
1095 | `ifdef LIB | |
1096 | assign out = ~(in0 & in1); | |
1097 | `endif | |
1098 | ||
1099 | endmodule | |
1100 | module cl_u1gb_nand2_2x ( | |
1101 | in0, | |
1102 | in1, | |
1103 | out | |
1104 | ); | |
1105 | input in0; | |
1106 | input in1; | |
1107 | output out; | |
1108 | ||
1109 | `ifdef LIB | |
1110 | assign out = ~(in0 & in1); | |
1111 | `endif | |
1112 | ||
1113 | endmodule | |
1114 | module cl_u1gb_nand2_32x ( | |
1115 | in0, | |
1116 | in1, | |
1117 | out | |
1118 | ); | |
1119 | input in0; | |
1120 | input in1; | |
1121 | output out; | |
1122 | ||
1123 | `ifdef LIB | |
1124 | assign out = ~(in0 & in1); | |
1125 | `endif | |
1126 | ||
1127 | endmodule | |
1128 | module cl_u1gb_nand2_4x ( | |
1129 | in0, | |
1130 | in1, | |
1131 | out | |
1132 | ); | |
1133 | input in0; | |
1134 | input in1; | |
1135 | output out; | |
1136 | ||
1137 | `ifdef LIB | |
1138 | assign out = ~(in0 & in1); | |
1139 | `endif | |
1140 | ||
1141 | endmodule | |
1142 | module cl_u1gb_nand2_6x ( | |
1143 | in0, | |
1144 | in1, | |
1145 | out | |
1146 | ); | |
1147 | input in0; | |
1148 | input in1; | |
1149 | output out; | |
1150 | ||
1151 | `ifdef LIB | |
1152 | assign out = ~(in0 & in1); | |
1153 | `endif | |
1154 | ||
1155 | endmodule | |
1156 | module cl_u1gb_nand2_8x ( | |
1157 | in0, | |
1158 | in1, | |
1159 | out | |
1160 | ); | |
1161 | input in0; | |
1162 | input in1; | |
1163 | output out; | |
1164 | ||
1165 | `ifdef LIB | |
1166 | assign out = ~(in0 & in1); | |
1167 | `endif | |
1168 | ||
1169 | endmodule | |
1170 | module cl_u1gb_nand3_12x ( | |
1171 | in0, | |
1172 | in1, | |
1173 | in2, | |
1174 | out | |
1175 | ); | |
1176 | input in0; | |
1177 | input in1; | |
1178 | input in2; | |
1179 | output out; | |
1180 | ||
1181 | `ifdef LIB | |
1182 | assign out = ~(in0 & in1 & in2); | |
1183 | `endif | |
1184 | ||
1185 | endmodule | |
1186 | module cl_u1gb_nand3_16x ( | |
1187 | in0, | |
1188 | in1, | |
1189 | in2, | |
1190 | out | |
1191 | ); | |
1192 | input in0; | |
1193 | input in1; | |
1194 | input in2; | |
1195 | output out; | |
1196 | ||
1197 | `ifdef LIB | |
1198 | assign out = ~(in0 & in1 & in2); | |
1199 | `endif | |
1200 | ||
1201 | endmodule | |
1202 | module cl_u1gb_nand3_1x ( | |
1203 | in0, | |
1204 | in1, | |
1205 | in2, | |
1206 | out | |
1207 | ); | |
1208 | input in0; | |
1209 | input in1; | |
1210 | input in2; | |
1211 | output out; | |
1212 | ||
1213 | `ifdef LIB | |
1214 | assign out = ~(in0 & in1 & in2); | |
1215 | `endif | |
1216 | ||
1217 | endmodule | |
1218 | module cl_u1gb_nand3_20x ( | |
1219 | in0, | |
1220 | in1, | |
1221 | in2, | |
1222 | out | |
1223 | ); | |
1224 | input in0; | |
1225 | input in1; | |
1226 | input in2; | |
1227 | output out; | |
1228 | ||
1229 | `ifdef LIB | |
1230 | assign out = ~(in0 & in1 & in2); | |
1231 | `endif | |
1232 | ||
1233 | endmodule | |
1234 | module cl_u1gb_nand3_24x ( | |
1235 | in0, | |
1236 | in1, | |
1237 | in2, | |
1238 | out | |
1239 | ); | |
1240 | input in0; | |
1241 | input in1; | |
1242 | input in2; | |
1243 | output out; | |
1244 | ||
1245 | `ifdef LIB | |
1246 | assign out = ~(in0 & in1 & in2); | |
1247 | `endif | |
1248 | ||
1249 | endmodule | |
1250 | ||
1251 | module cl_u1gb_nand3_2x ( | |
1252 | in0, | |
1253 | in1, | |
1254 | in2, | |
1255 | out | |
1256 | ); | |
1257 | input in0; | |
1258 | input in1; | |
1259 | input in2; | |
1260 | output out; | |
1261 | ||
1262 | `ifdef LIB | |
1263 | assign out = ~(in0 & in1 & in2); | |
1264 | `endif | |
1265 | ||
1266 | endmodule | |
1267 | ||
1268 | module cl_u1gb_nand3_4x ( | |
1269 | in0, | |
1270 | in1, | |
1271 | in2, | |
1272 | out | |
1273 | ); | |
1274 | input in0; | |
1275 | input in1; | |
1276 | input in2; | |
1277 | output out; | |
1278 | ||
1279 | `ifdef LIB | |
1280 | assign out = ~(in0 & in1 & in2); | |
1281 | `endif | |
1282 | ||
1283 | endmodule | |
1284 | module cl_u1gb_nand3_6x ( | |
1285 | in0, | |
1286 | in1, | |
1287 | in2, | |
1288 | out | |
1289 | ); | |
1290 | input in0; | |
1291 | input in1; | |
1292 | input in2; | |
1293 | output out; | |
1294 | ||
1295 | `ifdef LIB | |
1296 | assign out = ~(in0 & in1 & in2); | |
1297 | `endif | |
1298 | ||
1299 | endmodule | |
1300 | module cl_u1gb_nand3_8x ( | |
1301 | in0, | |
1302 | in1, | |
1303 | in2, | |
1304 | out | |
1305 | ); | |
1306 | input in0; | |
1307 | input in1; | |
1308 | input in2; | |
1309 | output out; | |
1310 | ||
1311 | `ifdef LIB | |
1312 | assign out = ~(in0 & in1 & in2); | |
1313 | `endif | |
1314 | ||
1315 | endmodule | |
1316 | module cl_u1gb_nand4_12x ( | |
1317 | in0, | |
1318 | in1, | |
1319 | in2, | |
1320 | in3, | |
1321 | out | |
1322 | ); | |
1323 | input in0; | |
1324 | input in1; | |
1325 | input in2; | |
1326 | input in3; | |
1327 | output out; | |
1328 | ||
1329 | `ifdef LIB | |
1330 | assign out = ~(in0 & in1 & in2 & in3); | |
1331 | `endif | |
1332 | ||
1333 | endmodule | |
1334 | module cl_u1gb_nand4_16x ( | |
1335 | in0, | |
1336 | in1, | |
1337 | in2, | |
1338 | in3, | |
1339 | out | |
1340 | ); | |
1341 | input in0; | |
1342 | input in1; | |
1343 | input in2; | |
1344 | input in3; | |
1345 | output out; | |
1346 | ||
1347 | `ifdef LIB | |
1348 | assign out = ~(in0 & in1 & in2 & in3); | |
1349 | `endif | |
1350 | ||
1351 | endmodule | |
1352 | module cl_u1gb_nand4_1x ( | |
1353 | in0, | |
1354 | in1, | |
1355 | in2, | |
1356 | in3, | |
1357 | out | |
1358 | ); | |
1359 | input in0; | |
1360 | input in1; | |
1361 | input in2; | |
1362 | input in3; | |
1363 | output out; | |
1364 | ||
1365 | `ifdef LIB | |
1366 | assign out = ~(in0 & in1 & in2 & in3); | |
1367 | `endif | |
1368 | ||
1369 | endmodule | |
1370 | ||
1371 | ||
1372 | module cl_u1gb_nand4_2x ( | |
1373 | in0, | |
1374 | in1, | |
1375 | in2, | |
1376 | in3, | |
1377 | out | |
1378 | ); | |
1379 | input in0; | |
1380 | input in1; | |
1381 | input in2; | |
1382 | input in3; | |
1383 | output out; | |
1384 | ||
1385 | `ifdef LIB | |
1386 | assign out = ~(in0 & in1 & in2 & in3); | |
1387 | `endif | |
1388 | ||
1389 | endmodule | |
1390 | ||
1391 | module cl_u1gb_nand4_4x ( | |
1392 | in0, | |
1393 | in1, | |
1394 | in2, | |
1395 | in3, | |
1396 | out | |
1397 | ); | |
1398 | input in0; | |
1399 | input in1; | |
1400 | input in2; | |
1401 | input in3; | |
1402 | output out; | |
1403 | ||
1404 | `ifdef LIB | |
1405 | assign out = ~(in0 & in1 & in2 & in3); | |
1406 | `endif | |
1407 | ||
1408 | endmodule | |
1409 | module cl_u1gb_nand4_6x ( | |
1410 | in0, | |
1411 | in1, | |
1412 | in2, | |
1413 | in3, | |
1414 | out | |
1415 | ); | |
1416 | input in0; | |
1417 | input in1; | |
1418 | input in2; | |
1419 | input in3; | |
1420 | output out; | |
1421 | ||
1422 | `ifdef LIB | |
1423 | assign out = ~(in0 & in1 & in2 & in3); | |
1424 | `endif | |
1425 | ||
1426 | endmodule | |
1427 | module cl_u1gb_nand4_8x ( | |
1428 | in0, | |
1429 | in1, | |
1430 | in2, | |
1431 | in3, | |
1432 | out | |
1433 | ); | |
1434 | input in0; | |
1435 | input in1; | |
1436 | input in2; | |
1437 | input in3; | |
1438 | output out; | |
1439 | ||
1440 | `ifdef LIB | |
1441 | assign out = ~(in0 & in1 & in2 & in3); | |
1442 | `endif | |
1443 | ||
1444 | endmodule | |
1445 | module cl_u1gb_nor2_12x ( | |
1446 | in0, | |
1447 | in1, | |
1448 | out | |
1449 | ); | |
1450 | input in0; | |
1451 | input in1; | |
1452 | output out; | |
1453 | ||
1454 | `ifdef LIB | |
1455 | assign out = ~(in0 | in1); | |
1456 | `endif | |
1457 | ||
1458 | endmodule | |
1459 | module cl_u1gb_nor2_16x ( | |
1460 | in0, | |
1461 | in1, | |
1462 | out | |
1463 | ); | |
1464 | input in0; | |
1465 | input in1; | |
1466 | output out; | |
1467 | ||
1468 | `ifdef LIB | |
1469 | assign out = ~(in0 | in1); | |
1470 | `endif | |
1471 | ||
1472 | endmodule | |
1473 | module cl_u1gb_nor2_1x ( | |
1474 | in0, | |
1475 | in1, | |
1476 | out | |
1477 | ); | |
1478 | input in0; | |
1479 | input in1; | |
1480 | output out; | |
1481 | ||
1482 | `ifdef LIB | |
1483 | assign out = ~(in0 | in1); | |
1484 | `endif | |
1485 | ||
1486 | endmodule | |
1487 | module cl_u1gb_nor2_2x ( | |
1488 | in0, | |
1489 | in1, | |
1490 | out | |
1491 | ); | |
1492 | input in0; | |
1493 | input in1; | |
1494 | output out; | |
1495 | ||
1496 | `ifdef LIB | |
1497 | assign out = ~(in0 | in1); | |
1498 | `endif | |
1499 | ||
1500 | endmodule | |
1501 | module cl_u1gb_nor2_4x ( | |
1502 | in0, | |
1503 | in1, | |
1504 | out | |
1505 | ); | |
1506 | input in0; | |
1507 | input in1; | |
1508 | output out; | |
1509 | ||
1510 | `ifdef LIB | |
1511 | assign out = ~(in0 | in1); | |
1512 | `endif | |
1513 | ||
1514 | endmodule | |
1515 | module cl_u1gb_nor2_6x ( | |
1516 | in0, | |
1517 | in1, | |
1518 | out | |
1519 | ); | |
1520 | input in0; | |
1521 | input in1; | |
1522 | output out; | |
1523 | ||
1524 | `ifdef LIB | |
1525 | assign out = ~(in0 | in1); | |
1526 | `endif | |
1527 | ||
1528 | endmodule | |
1529 | module cl_u1gb_nor2_8x ( | |
1530 | in0, | |
1531 | in1, | |
1532 | out | |
1533 | ); | |
1534 | input in0; | |
1535 | input in1; | |
1536 | output out; | |
1537 | ||
1538 | `ifdef LIB | |
1539 | assign out = ~(in0 | in1); | |
1540 | `endif | |
1541 | ||
1542 | endmodule | |
1543 | module cl_u1gb_nor3_1x ( | |
1544 | in0, | |
1545 | in1, | |
1546 | in2, | |
1547 | out | |
1548 | ); | |
1549 | input in0; | |
1550 | input in1; | |
1551 | input in2; | |
1552 | output out; | |
1553 | ||
1554 | `ifdef LIB | |
1555 | assign out = ~(in0 | in1 | in2); | |
1556 | `endif | |
1557 | ||
1558 | endmodule | |
1559 | module cl_u1gb_nor3_2x ( | |
1560 | in0, | |
1561 | in1, | |
1562 | in2, | |
1563 | out | |
1564 | ); | |
1565 | input in0; | |
1566 | input in1; | |
1567 | input in2; | |
1568 | output out; | |
1569 | ||
1570 | `ifdef LIB | |
1571 | assign out = ~(in0 | in1 | in2); | |
1572 | `endif | |
1573 | ||
1574 | endmodule | |
1575 | module cl_u1gb_nor3_4x ( | |
1576 | in0, | |
1577 | in1, | |
1578 | in2, | |
1579 | out | |
1580 | ); | |
1581 | input in0; | |
1582 | input in1; | |
1583 | input in2; | |
1584 | output out; | |
1585 | ||
1586 | `ifdef LIB | |
1587 | assign out = ~(in0 | in1 | in2); | |
1588 | `endif | |
1589 | ||
1590 | endmodule | |
1591 | // -------------------------------------------------- | |
1592 | // File: cl_u1gb_oai12_12x.behV | |
1593 | // Auto generated verilog module by HnBCellAuto | |
1594 | // | |
1595 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1596 | // By: balmiki | |
1597 | // -------------------------------------------------- | |
1598 | // | |
1599 | module cl_u1gb_oai12_12x ( | |
1600 | out, | |
1601 | in10, | |
1602 | in00, | |
1603 | in01 ); | |
1604 | ||
1605 | output out; | |
1606 | input in10; | |
1607 | input in00; | |
1608 | input in01; | |
1609 | ||
1610 | `ifdef LIB | |
1611 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1612 | `endif | |
1613 | ||
1614 | endmodule | |
1615 | // -------------------------------------------------- | |
1616 | // File: cl_u1gb_oai12_16x.behV | |
1617 | // Auto generated verilog module by HnBCellAuto | |
1618 | // | |
1619 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1620 | // By: balmiki | |
1621 | // -------------------------------------------------- | |
1622 | // | |
1623 | module cl_u1gb_oai12_16x ( | |
1624 | out, | |
1625 | in10, | |
1626 | in00, | |
1627 | in01 ); | |
1628 | ||
1629 | output out; | |
1630 | input in10; | |
1631 | input in00; | |
1632 | input in01; | |
1633 | ||
1634 | `ifdef LIB | |
1635 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1636 | `endif | |
1637 | ||
1638 | endmodule | |
1639 | // -------------------------------------------------- | |
1640 | // File: cl_u1gb_oai12_1x.behV | |
1641 | // Auto generated verilog module by HnBCellAuto | |
1642 | // | |
1643 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1644 | // By: balmiki | |
1645 | // -------------------------------------------------- | |
1646 | // | |
1647 | module cl_u1gb_oai12_1x ( | |
1648 | out, | |
1649 | in10, | |
1650 | in00, | |
1651 | in01 ); | |
1652 | ||
1653 | output out; | |
1654 | input in10; | |
1655 | input in00; | |
1656 | input in01; | |
1657 | ||
1658 | `ifdef LIB | |
1659 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1660 | `endif | |
1661 | ||
1662 | endmodule | |
1663 | // -------------------------------------------------- | |
1664 | // File: cl_u1gb_oai12_2x.behV | |
1665 | // Auto generated verilog module by HnBCellAuto | |
1666 | // | |
1667 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1668 | // By: balmiki | |
1669 | // -------------------------------------------------- | |
1670 | // | |
1671 | module cl_u1gb_oai12_2x ( | |
1672 | out, | |
1673 | in10, | |
1674 | in00, | |
1675 | in01 ); | |
1676 | ||
1677 | output out; | |
1678 | input in10; | |
1679 | input in00; | |
1680 | input in01; | |
1681 | ||
1682 | `ifdef LIB | |
1683 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1684 | `endif | |
1685 | ||
1686 | endmodule | |
1687 | // -------------------------------------------------- | |
1688 | // File: cl_u1gb_oai12_4x.behV | |
1689 | // Auto generated verilog module by HnBCellAuto | |
1690 | // | |
1691 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1692 | // By: balmiki | |
1693 | // -------------------------------------------------- | |
1694 | // | |
1695 | module cl_u1gb_oai12_4x ( | |
1696 | out, | |
1697 | in10, | |
1698 | in00, | |
1699 | in01 ); | |
1700 | ||
1701 | output out; | |
1702 | input in10; | |
1703 | input in00; | |
1704 | input in01; | |
1705 | ||
1706 | `ifdef LIB | |
1707 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1708 | `endif | |
1709 | ||
1710 | endmodule | |
1711 | // -------------------------------------------------- | |
1712 | // File: cl_u1gb_oai12_8x.behV | |
1713 | // Auto generated verilog module by HnBCellAuto | |
1714 | // | |
1715 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1716 | // By: balmiki | |
1717 | // -------------------------------------------------- | |
1718 | // | |
1719 | module cl_u1gb_oai12_8x ( | |
1720 | out, | |
1721 | in10, | |
1722 | in00, | |
1723 | in01 ); | |
1724 | ||
1725 | output out; | |
1726 | input in10; | |
1727 | input in00; | |
1728 | input in01; | |
1729 | ||
1730 | `ifdef LIB | |
1731 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1732 | `endif | |
1733 | ||
1734 | endmodule | |
1735 | // -------------------------------------------------- | |
1736 | // File: cl_u1gb_oai21_12x.behV | |
1737 | // Auto generated verilog module by HnBCellAuto | |
1738 | // | |
1739 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1740 | // By: balmiki | |
1741 | // -------------------------------------------------- | |
1742 | // | |
1743 | module cl_u1gb_oai21_12x ( | |
1744 | out, | |
1745 | in10, | |
1746 | in11, | |
1747 | in00 ); | |
1748 | ||
1749 | output out; | |
1750 | input in10; | |
1751 | input in11; | |
1752 | input in00; | |
1753 | ||
1754 | `ifdef LIB | |
1755 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1756 | `endif | |
1757 | ||
1758 | endmodule | |
1759 | // -------------------------------------------------- | |
1760 | // File: cl_u1gb_oai21_16x.behV | |
1761 | // Auto generated verilog module by HnBCellAuto | |
1762 | // | |
1763 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1764 | // By: balmiki | |
1765 | // -------------------------------------------------- | |
1766 | // | |
1767 | module cl_u1gb_oai21_16x ( | |
1768 | out, | |
1769 | in10, | |
1770 | in11, | |
1771 | in00 ); | |
1772 | ||
1773 | output out; | |
1774 | input in10; | |
1775 | input in11; | |
1776 | input in00; | |
1777 | ||
1778 | `ifdef LIB | |
1779 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1780 | `endif | |
1781 | ||
1782 | endmodule | |
1783 | // -------------------------------------------------- | |
1784 | // File: cl_u1gb_oai21_1x.behV | |
1785 | // Auto generated verilog module by HnBCellAuto | |
1786 | // | |
1787 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST | |
1788 | // By: balmiki | |
1789 | // -------------------------------------------------- | |
1790 | // | |
1791 | module cl_u1gb_oai21_1x ( | |
1792 | out, | |
1793 | in10, | |
1794 | in11, | |
1795 | in00 ); | |
1796 | ||
1797 | output out; | |
1798 | input in10; | |
1799 | input in11; | |
1800 | input in00; | |
1801 | ||
1802 | `ifdef LIB | |
1803 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1804 | `endif | |
1805 | ||
1806 | endmodule | |
1807 | // -------------------------------------------------- | |
1808 | // File: cl_u1gb_oai21_2x.behV | |
1809 | // Auto generated verilog module by HnBCellAuto | |
1810 | // | |
1811 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1812 | // By: balmiki | |
1813 | // -------------------------------------------------- | |
1814 | // | |
1815 | module cl_u1gb_oai21_2x ( | |
1816 | out, | |
1817 | in10, | |
1818 | in11, | |
1819 | in00 ); | |
1820 | ||
1821 | output out; | |
1822 | input in10; | |
1823 | input in11; | |
1824 | input in00; | |
1825 | ||
1826 | `ifdef LIB | |
1827 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1828 | `endif | |
1829 | ||
1830 | endmodule | |
1831 | // -------------------------------------------------- | |
1832 | // File: cl_u1gb_oai21_4x.behV | |
1833 | // Auto generated verilog module by HnBCellAuto | |
1834 | // | |
1835 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1836 | // By: balmiki | |
1837 | // -------------------------------------------------- | |
1838 | // | |
1839 | module cl_u1gb_oai21_4x ( | |
1840 | out, | |
1841 | in10, | |
1842 | in11, | |
1843 | in00 ); | |
1844 | ||
1845 | output out; | |
1846 | input in10; | |
1847 | input in11; | |
1848 | input in00; | |
1849 | ||
1850 | `ifdef LIB | |
1851 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1852 | `endif | |
1853 | ||
1854 | endmodule | |
1855 | // -------------------------------------------------- | |
1856 | // File: cl_u1gb_oai21_8x.behV | |
1857 | // Auto generated verilog module by HnBCellAuto | |
1858 | // | |
1859 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1860 | // By: balmiki | |
1861 | // -------------------------------------------------- | |
1862 | // | |
1863 | module cl_u1gb_oai21_8x ( | |
1864 | out, | |
1865 | in10, | |
1866 | in11, | |
1867 | in00 ); | |
1868 | ||
1869 | output out; | |
1870 | input in10; | |
1871 | input in11; | |
1872 | input in00; | |
1873 | ||
1874 | `ifdef LIB | |
1875 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1876 | `endif | |
1877 | ||
1878 | endmodule | |
1879 | // -------------------------------------------------- | |
1880 | // File: cl_u1gb_oai22_12x.behV | |
1881 | // Auto generated verilog module by HnBCellAuto | |
1882 | // | |
1883 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1884 | // By: balmiki | |
1885 | // -------------------------------------------------- | |
1886 | // | |
1887 | module cl_u1gb_oai22_12x ( | |
1888 | out, | |
1889 | in10, | |
1890 | in11, | |
1891 | in00, | |
1892 | in01 ); | |
1893 | ||
1894 | output out; | |
1895 | input in10; | |
1896 | input in11; | |
1897 | input in00; | |
1898 | input in01; | |
1899 | ||
1900 | `ifdef LIB | |
1901 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1902 | `endif | |
1903 | ||
1904 | endmodule | |
1905 | // -------------------------------------------------- | |
1906 | // File: cl_u1gb_oai22_16x.behV | |
1907 | // Auto generated verilog module by HnBCellAuto | |
1908 | // | |
1909 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1910 | // By: balmiki | |
1911 | // -------------------------------------------------- | |
1912 | // | |
1913 | module cl_u1gb_oai22_16x ( | |
1914 | out, | |
1915 | in10, | |
1916 | in11, | |
1917 | in00, | |
1918 | in01 ); | |
1919 | ||
1920 | output out; | |
1921 | input in10; | |
1922 | input in11; | |
1923 | input in00; | |
1924 | input in01; | |
1925 | ||
1926 | `ifdef LIB | |
1927 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1928 | `endif | |
1929 | ||
1930 | endmodule | |
1931 | // -------------------------------------------------- | |
1932 | // File: cl_u1gb_oai22_1x.behV | |
1933 | // Auto generated verilog module by HnBCellAuto | |
1934 | // | |
1935 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1936 | // By: balmiki | |
1937 | // -------------------------------------------------- | |
1938 | // | |
1939 | module cl_u1gb_oai22_1x ( | |
1940 | out, | |
1941 | in10, | |
1942 | in11, | |
1943 | in00, | |
1944 | in01 ); | |
1945 | ||
1946 | output out; | |
1947 | input in10; | |
1948 | input in11; | |
1949 | input in00; | |
1950 | input in01; | |
1951 | ||
1952 | `ifdef LIB | |
1953 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1954 | `endif | |
1955 | ||
1956 | endmodule | |
1957 | // -------------------------------------------------- | |
1958 | // File: cl_u1gb_oai22_2x.behV | |
1959 | // Auto generated verilog module by HnBCellAuto | |
1960 | // | |
1961 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1962 | // By: balmiki | |
1963 | // -------------------------------------------------- | |
1964 | // | |
1965 | module cl_u1gb_oai22_2x ( | |
1966 | out, | |
1967 | in10, | |
1968 | in11, | |
1969 | in00, | |
1970 | in01 ); | |
1971 | ||
1972 | output out; | |
1973 | input in10; | |
1974 | input in11; | |
1975 | input in00; | |
1976 | input in01; | |
1977 | ||
1978 | `ifdef LIB | |
1979 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1980 | `endif | |
1981 | ||
1982 | endmodule | |
1983 | // -------------------------------------------------- | |
1984 | // File: cl_u1gb_oai22_4x.behV | |
1985 | // Auto generated verilog module by HnBCellAuto | |
1986 | // | |
1987 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1988 | // By: balmiki | |
1989 | // -------------------------------------------------- | |
1990 | // | |
1991 | module cl_u1gb_oai22_4x ( | |
1992 | out, | |
1993 | in10, | |
1994 | in11, | |
1995 | in00, | |
1996 | in01 ); | |
1997 | ||
1998 | output out; | |
1999 | input in10; | |
2000 | input in11; | |
2001 | input in00; | |
2002 | input in01; | |
2003 | ||
2004 | `ifdef LIB | |
2005 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
2006 | `endif | |
2007 | ||
2008 | endmodule | |
2009 | // -------------------------------------------------- | |
2010 | // File: cl_u1gb_oai22_8x.behV | |
2011 | // Auto generated verilog module by HnBCellAuto | |
2012 | // | |
2013 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
2014 | // By: balmiki | |
2015 | // -------------------------------------------------- | |
2016 | // | |
2017 | module cl_u1gb_oai22_8x ( | |
2018 | out, | |
2019 | in10, | |
2020 | in11, | |
2021 | in00, | |
2022 | in01 ); | |
2023 | ||
2024 | output out; | |
2025 | input in10; | |
2026 | input in11; | |
2027 | input in00; | |
2028 | input in01; | |
2029 | ||
2030 | `ifdef LIB | |
2031 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
2032 | `endif | |
2033 | ||
2034 | endmodule | |
2035 | module cl_u1gb_xnor2_16x ( | |
2036 | in0, | |
2037 | in1, | |
2038 | out | |
2039 | ); | |
2040 | input in0; | |
2041 | input in1; | |
2042 | output out; | |
2043 | ||
2044 | `ifdef LIB | |
2045 | assign out = ~(in0 ^ in1); | |
2046 | `endif | |
2047 | ||
2048 | endmodule | |
2049 | ||
2050 | module cl_u1gb_xnor2_1x ( | |
2051 | in0, | |
2052 | in1, | |
2053 | out | |
2054 | ); | |
2055 | input in0; | |
2056 | input in1; | |
2057 | output out; | |
2058 | ||
2059 | `ifdef LIB | |
2060 | assign out = ~(in0 ^ in1); | |
2061 | `endif | |
2062 | ||
2063 | endmodule | |
2064 | module cl_u1gb_xnor2_2x ( | |
2065 | in0, | |
2066 | in1, | |
2067 | out | |
2068 | ); | |
2069 | input in0; | |
2070 | input in1; | |
2071 | output out; | |
2072 | ||
2073 | `ifdef LIB | |
2074 | assign out = ~(in0 ^ in1); | |
2075 | `endif | |
2076 | ||
2077 | endmodule | |
2078 | module cl_u1gb_xnor2_4x ( | |
2079 | in0, | |
2080 | in1, | |
2081 | out | |
2082 | ); | |
2083 | input in0; | |
2084 | input in1; | |
2085 | output out; | |
2086 | ||
2087 | `ifdef LIB | |
2088 | assign out = ~(in0 ^ in1); | |
2089 | `endif | |
2090 | ||
2091 | endmodule | |
2092 | module cl_u1gb_xnor2_6x ( | |
2093 | in0, | |
2094 | in1, | |
2095 | out | |
2096 | ); | |
2097 | input in0; | |
2098 | input in1; | |
2099 | output out; | |
2100 | ||
2101 | `ifdef LIB | |
2102 | assign out = ~(in0 ^ in1); | |
2103 | `endif | |
2104 | ||
2105 | endmodule | |
2106 | module cl_u1gb_xnor2_8x ( | |
2107 | in0, | |
2108 | in1, | |
2109 | out | |
2110 | ); | |
2111 | input in0; | |
2112 | input in1; | |
2113 | output out; | |
2114 | ||
2115 | `ifdef LIB | |
2116 | assign out = ~(in0 ^ in1); | |
2117 | `endif | |
2118 | ||
2119 | endmodule | |
2120 | ||
2121 | module cl_u1gb_xnor3_16x ( | |
2122 | in0, | |
2123 | in1, | |
2124 | in2, | |
2125 | out | |
2126 | ); | |
2127 | input in0; | |
2128 | input in1; | |
2129 | input in2; | |
2130 | output out; | |
2131 | ||
2132 | `ifdef LIB | |
2133 | assign out = ~(in0 ^ in1 ^ in2); | |
2134 | `endif | |
2135 | ||
2136 | ||
2137 | ||
2138 | endmodule | |
2139 | module cl_u1gb_xnor3_1x ( | |
2140 | in0, | |
2141 | in1, | |
2142 | in2, | |
2143 | out | |
2144 | ); | |
2145 | input in0; | |
2146 | input in1; | |
2147 | input in2; | |
2148 | output out; | |
2149 | ||
2150 | `ifdef LIB | |
2151 | assign out = ~(in0 ^ in1 ^ in2); | |
2152 | `endif | |
2153 | ||
2154 | ||
2155 | ||
2156 | endmodule | |
2157 | module cl_u1gb_xnor3_2x ( | |
2158 | in0, | |
2159 | in1, | |
2160 | in2, | |
2161 | out | |
2162 | ); | |
2163 | input in0; | |
2164 | input in1; | |
2165 | input in2; | |
2166 | output out; | |
2167 | ||
2168 | `ifdef LIB | |
2169 | assign out = ~(in0 ^ in1 ^ in2); | |
2170 | `endif | |
2171 | ||
2172 | ||
2173 | ||
2174 | endmodule | |
2175 | module cl_u1gb_xnor3_4x ( | |
2176 | in0, | |
2177 | in1, | |
2178 | in2, | |
2179 | out | |
2180 | ); | |
2181 | input in0; | |
2182 | input in1; | |
2183 | input in2; | |
2184 | output out; | |
2185 | ||
2186 | `ifdef LIB | |
2187 | assign out = ~(in0 ^ in1 ^ in2); | |
2188 | `endif | |
2189 | ||
2190 | ||
2191 | ||
2192 | endmodule | |
2193 | module cl_u1gb_xnor3_6x ( | |
2194 | in0, | |
2195 | in1, | |
2196 | in2, | |
2197 | out | |
2198 | ); | |
2199 | input in0; | |
2200 | input in1; | |
2201 | input in2; | |
2202 | output out; | |
2203 | ||
2204 | `ifdef LIB | |
2205 | assign out = ~(in0 ^ in1 ^ in2); | |
2206 | `endif | |
2207 | ||
2208 | ||
2209 | ||
2210 | endmodule | |
2211 | module cl_u1gb_xnor3_8x ( | |
2212 | in0, | |
2213 | in1, | |
2214 | in2, | |
2215 | out | |
2216 | ); | |
2217 | input in0; | |
2218 | input in1; | |
2219 | input in2; | |
2220 | output out; | |
2221 | ||
2222 | `ifdef LIB | |
2223 | assign out = ~(in0 ^ in1 ^ in2); | |
2224 | `endif | |
2225 | ||
2226 | ||
2227 | ||
2228 | endmodule | |
2229 | module cl_u1gb_xor2_16x ( | |
2230 | in0, | |
2231 | in1, | |
2232 | out | |
2233 | ); | |
2234 | input in0; | |
2235 | input in1; | |
2236 | output out; | |
2237 | ||
2238 | `ifdef LIB | |
2239 | assign out = in0 ^ in1; | |
2240 | `endif | |
2241 | ||
2242 | endmodule | |
2243 | ||
2244 | module cl_u1gb_xor2_1x ( | |
2245 | in0, | |
2246 | in1, | |
2247 | out | |
2248 | ); | |
2249 | input in0; | |
2250 | input in1; | |
2251 | output out; | |
2252 | ||
2253 | `ifdef LIB | |
2254 | assign out = in0 ^ in1; | |
2255 | `endif | |
2256 | ||
2257 | endmodule | |
2258 | module cl_u1gb_xor2_2x ( | |
2259 | in0, | |
2260 | in1, | |
2261 | out | |
2262 | ); | |
2263 | input in0; | |
2264 | input in1; | |
2265 | output out; | |
2266 | ||
2267 | `ifdef LIB | |
2268 | assign out = in0 ^ in1; | |
2269 | `endif | |
2270 | ||
2271 | endmodule | |
2272 | module cl_u1gb_xor2_4x ( | |
2273 | in0, | |
2274 | in1, | |
2275 | out | |
2276 | ); | |
2277 | input in0; | |
2278 | input in1; | |
2279 | output out; | |
2280 | ||
2281 | `ifdef LIB | |
2282 | assign out = in0 ^ in1; | |
2283 | `endif | |
2284 | ||
2285 | endmodule | |
2286 | module cl_u1gb_xor2_6x ( | |
2287 | in0, | |
2288 | in1, | |
2289 | out | |
2290 | ); | |
2291 | input in0; | |
2292 | input in1; | |
2293 | output out; | |
2294 | ||
2295 | `ifdef LIB | |
2296 | assign out = in0 ^ in1; | |
2297 | `endif | |
2298 | ||
2299 | endmodule | |
2300 | module cl_u1gb_xor2_8x ( | |
2301 | in0, | |
2302 | in1, | |
2303 | out | |
2304 | ); | |
2305 | input in0; | |
2306 | input in1; | |
2307 | output out; | |
2308 | ||
2309 | `ifdef LIB | |
2310 | assign out = in0 ^ in1; | |
2311 | `endif | |
2312 | ||
2313 | endmodule | |
2314 | module cl_u1gb_xor3_16x ( | |
2315 | in0, | |
2316 | in1, | |
2317 | in2, | |
2318 | out | |
2319 | ); | |
2320 | input in0; | |
2321 | input in1; | |
2322 | input in2; | |
2323 | output out; | |
2324 | ||
2325 | `ifdef LIB | |
2326 | assign out = in0 ^ in1 ^ in2; | |
2327 | `endif | |
2328 | ||
2329 | ||
2330 | endmodule | |
2331 | ||
2332 | module cl_u1gb_xor3_1x ( | |
2333 | in0, | |
2334 | in1, | |
2335 | in2, | |
2336 | out | |
2337 | ); | |
2338 | input in0; | |
2339 | input in1; | |
2340 | input in2; | |
2341 | output out; | |
2342 | ||
2343 | `ifdef LIB | |
2344 | assign out = in0 ^ in1 ^ in2; | |
2345 | `endif | |
2346 | ||
2347 | ||
2348 | endmodule | |
2349 | module cl_u1gb_xor3_2x ( | |
2350 | in0, | |
2351 | in1, | |
2352 | in2, | |
2353 | out | |
2354 | ); | |
2355 | input in0; | |
2356 | input in1; | |
2357 | input in2; | |
2358 | output out; | |
2359 | ||
2360 | `ifdef LIB | |
2361 | assign out = in0 ^ in1 ^ in2; | |
2362 | `endif | |
2363 | ||
2364 | ||
2365 | endmodule | |
2366 | module cl_u1gb_xor3_4x ( | |
2367 | in0, | |
2368 | in1, | |
2369 | in2, | |
2370 | out | |
2371 | ); | |
2372 | input in0; | |
2373 | input in1; | |
2374 | input in2; | |
2375 | output out; | |
2376 | ||
2377 | `ifdef LIB | |
2378 | assign out = in0 ^ in1 ^ in2; | |
2379 | `endif | |
2380 | ||
2381 | ||
2382 | endmodule | |
2383 | module cl_u1gb_xor3_6x ( | |
2384 | in0, | |
2385 | in1, | |
2386 | in2, | |
2387 | out | |
2388 | ); | |
2389 | input in0; | |
2390 | input in1; | |
2391 | input in2; | |
2392 | output out; | |
2393 | ||
2394 | `ifdef LIB | |
2395 | assign out = in0 ^ in1 ^ in2; | |
2396 | `endif | |
2397 | ||
2398 | ||
2399 | endmodule | |
2400 | module cl_u1gb_xor3_8x ( | |
2401 | in0, | |
2402 | in1, | |
2403 | in2, | |
2404 | out | |
2405 | ); | |
2406 | input in0; | |
2407 | input in1; | |
2408 | input in2; | |
2409 | output out; | |
2410 | ||
2411 | `ifdef LIB | |
2412 | assign out = in0 ^ in1 ^ in2; | |
2413 | `endif | |
2414 | ||
2415 | ||
2416 | endmodule | |
2417 | ||
2418 | module cl_u1gb_rep_32x ( | |
2419 | in, | |
2420 | out | |
2421 | ); | |
2422 | input in; | |
2423 | output out; | |
2424 | ||
2425 | `ifdef LIB | |
2426 | assign out = in; | |
2427 | `endif | |
2428 | ||
2429 | endmodule | |
2430 | module cl_u1gb_rep_40x ( | |
2431 | in, | |
2432 | out | |
2433 | ); | |
2434 | input in; | |
2435 | output out; | |
2436 | ||
2437 | `ifdef LIB | |
2438 | assign out = in; | |
2439 | `endif | |
2440 | ||
2441 | endmodule | |
2442 | module cl_u1gb_rep_24x ( | |
2443 | in, | |
2444 | out | |
2445 | ); | |
2446 | input in; | |
2447 | output out; | |
2448 | ||
2449 | `ifdef LIB | |
2450 | assign out = in; | |
2451 | `endif | |
2452 | ||
2453 | endmodule | |
2454 | module cl_u1gb_rep_16x ( | |
2455 | in, | |
2456 | out | |
2457 | ); | |
2458 | input in; | |
2459 | output out; | |
2460 | ||
2461 | `ifdef LIB | |
2462 | assign out = in; | |
2463 | `endif | |
2464 | ||
2465 | endmodule | |
2466 | module cl_u1gb_rep_8x ( | |
2467 | in, | |
2468 | out | |
2469 | ); | |
2470 | input in; | |
2471 | output out; | |
2472 | ||
2473 | `ifdef LIB | |
2474 | assign out = in; | |
2475 | `endif | |
2476 | ||
2477 | endmodule | |
2478 | module cl_u1gb_rep_48x ( | |
2479 | in, | |
2480 | out | |
2481 | ); | |
2482 | input in; | |
2483 | output out; | |
2484 | ||
2485 | `ifdef LIB | |
2486 | assign out = in; | |
2487 | `endif | |
2488 | ||
2489 | endmodule | |
2490 | ||
2491 | ||
2492 |