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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: cl_u1lvt.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module cl_u1lvt_aoi12_12x ( | |
36 | out, | |
37 | in10, | |
38 | in00, | |
39 | in01 ); | |
40 | ||
41 | output out; | |
42 | input in10; | |
43 | input in00; | |
44 | input in01; | |
45 | ||
46 | `ifdef LIB | |
47 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
48 | `endif | |
49 | ||
50 | endmodule | |
51 | // -------------------------------------------------- | |
52 | // File: cl_u1lvt_aoi12_16x.behV | |
53 | // Auto generated verilog module by HnBCellAuto | |
54 | // | |
55 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
56 | // By: balmiki | |
57 | // -------------------------------------------------- | |
58 | // | |
59 | module cl_u1lvt_aoi12_16x ( | |
60 | out, | |
61 | in10, | |
62 | in00, | |
63 | in01 ); | |
64 | ||
65 | output out; | |
66 | input in10; | |
67 | input in00; | |
68 | input in01; | |
69 | ||
70 | `ifdef LIB | |
71 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
72 | `endif | |
73 | ||
74 | endmodule | |
75 | // -------------------------------------------------- | |
76 | // File: cl_u1lvt_aoi12_1x.behV | |
77 | // Auto generated verilog module by HnBCellAuto | |
78 | // | |
79 | // Created: Thursday Dec 6,2001 at 02:09:00 PM PST | |
80 | // By: balmiki | |
81 | // -------------------------------------------------- | |
82 | // | |
83 | module cl_u1lvt_aoi12_1x ( | |
84 | out, | |
85 | in10, | |
86 | in00, | |
87 | in01 ); | |
88 | ||
89 | output out; | |
90 | input in10; | |
91 | input in00; | |
92 | input in01; | |
93 | ||
94 | `ifdef LIB | |
95 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
96 | `endif | |
97 | ||
98 | endmodule | |
99 | // -------------------------------------------------- | |
100 | // File: cl_u1lvt_aoi12_2x.behV | |
101 | // Auto generated verilog module by HnBCellAuto | |
102 | // | |
103 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
104 | // By: balmiki | |
105 | // -------------------------------------------------- | |
106 | // | |
107 | module cl_u1lvt_aoi12_2x ( | |
108 | out, | |
109 | in10, | |
110 | in00, | |
111 | in01 ); | |
112 | ||
113 | output out; | |
114 | input in10; | |
115 | input in00; | |
116 | input in01; | |
117 | ||
118 | `ifdef LIB | |
119 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
120 | `endif | |
121 | ||
122 | endmodule | |
123 | // -------------------------------------------------- | |
124 | // File: cl_u1lvt_aoi12_4x.behV | |
125 | // Auto generated verilog module by HnBCellAuto | |
126 | // | |
127 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
128 | // By: balmiki | |
129 | // -------------------------------------------------- | |
130 | // | |
131 | module cl_u1lvt_aoi12_4x ( | |
132 | out, | |
133 | in10, | |
134 | in00, | |
135 | in01 ); | |
136 | ||
137 | output out; | |
138 | input in10; | |
139 | input in00; | |
140 | input in01; | |
141 | ||
142 | `ifdef LIB | |
143 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
144 | `endif | |
145 | ||
146 | endmodule | |
147 | // -------------------------------------------------- | |
148 | // File: cl_u1lvt_aoi12_8x.behV | |
149 | // Auto generated verilog module by HnBCellAuto | |
150 | // | |
151 | // Created: Thursday Nov 29,2001 at 11:51:25 AM PST | |
152 | // By: balmiki | |
153 | // -------------------------------------------------- | |
154 | // | |
155 | module cl_u1lvt_aoi12_8x ( | |
156 | out, | |
157 | in10, | |
158 | in00, | |
159 | in01 ); | |
160 | ||
161 | output out; | |
162 | input in10; | |
163 | input in00; | |
164 | input in01; | |
165 | ||
166 | `ifdef LIB | |
167 | assign out = ~(( in10 ) | ( in00 & in01 )); | |
168 | `endif | |
169 | ||
170 | endmodule | |
171 | // -------------------------------------------------- | |
172 | // File: cl_u1lvt_aoi21_12x.behV | |
173 | // Auto generated verilog module by HnBCellAuto | |
174 | // | |
175 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
176 | // By: balmiki | |
177 | // -------------------------------------------------- | |
178 | // | |
179 | module cl_u1lvt_aoi21_12x ( | |
180 | out, | |
181 | in10, | |
182 | in11, | |
183 | in00 ); | |
184 | ||
185 | output out; | |
186 | input in10; | |
187 | input in11; | |
188 | input in00; | |
189 | ||
190 | `ifdef LIB | |
191 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
192 | `endif | |
193 | ||
194 | endmodule | |
195 | // -------------------------------------------------- | |
196 | // File: cl_u1lvt_aoi21_16x.behV | |
197 | // Auto generated verilog module by HnBCellAuto | |
198 | // | |
199 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
200 | // By: balmiki | |
201 | // -------------------------------------------------- | |
202 | // | |
203 | module cl_u1lvt_aoi21_16x ( | |
204 | out, | |
205 | in10, | |
206 | in11, | |
207 | in00 ); | |
208 | ||
209 | output out; | |
210 | input in10; | |
211 | input in11; | |
212 | input in00; | |
213 | ||
214 | `ifdef LIB | |
215 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
216 | `endif | |
217 | ||
218 | endmodule | |
219 | // -------------------------------------------------- | |
220 | // File: cl_u1lvt_aoi21_1x.behV | |
221 | // Auto generated verilog module by HnBCellAuto | |
222 | // | |
223 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
224 | // By: balmiki | |
225 | // -------------------------------------------------- | |
226 | // | |
227 | module cl_u1lvt_aoi21_1x ( | |
228 | out, | |
229 | in10, | |
230 | in11, | |
231 | in00 ); | |
232 | ||
233 | output out; | |
234 | input in10; | |
235 | input in11; | |
236 | input in00; | |
237 | ||
238 | `ifdef LIB | |
239 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
240 | `endif | |
241 | ||
242 | endmodule | |
243 | // -------------------------------------------------- | |
244 | // File: cl_u1lvt_aoi21_2x.behV | |
245 | // Auto generated verilog module by HnBCellAuto | |
246 | // | |
247 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
248 | // By: balmiki | |
249 | // -------------------------------------------------- | |
250 | // | |
251 | module cl_u1lvt_aoi21_2x ( | |
252 | out, | |
253 | in10, | |
254 | in11, | |
255 | in00 ); | |
256 | ||
257 | output out; | |
258 | input in10; | |
259 | input in11; | |
260 | input in00; | |
261 | ||
262 | `ifdef LIB | |
263 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
264 | `endif | |
265 | ||
266 | endmodule | |
267 | // -------------------------------------------------- | |
268 | // File: cl_u1lvt_aoi21_4x.behV | |
269 | // Auto generated verilog module by HnBCellAuto | |
270 | // | |
271 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
272 | // By: balmiki | |
273 | // -------------------------------------------------- | |
274 | // | |
275 | module cl_u1lvt_aoi21_4x ( | |
276 | out, | |
277 | in10, | |
278 | in11, | |
279 | in00 ); | |
280 | ||
281 | output out; | |
282 | input in10; | |
283 | input in11; | |
284 | input in00; | |
285 | ||
286 | `ifdef LIB | |
287 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
288 | `endif | |
289 | ||
290 | endmodule | |
291 | // -------------------------------------------------- | |
292 | // File: cl_u1lvt_aoi21_8x.behV | |
293 | // Auto generated verilog module by HnBCellAuto | |
294 | // | |
295 | // Created: Monday Oct 8,2001 at 11:32:15 AM PDT | |
296 | // By: balmiki | |
297 | // -------------------------------------------------- | |
298 | // | |
299 | module cl_u1lvt_aoi21_8x ( | |
300 | out, | |
301 | in10, | |
302 | in11, | |
303 | in00 ); | |
304 | ||
305 | output out; | |
306 | input in10; | |
307 | input in11; | |
308 | input in00; | |
309 | ||
310 | `ifdef LIB | |
311 | assign out = ~(( in10 & in11 ) | ( in00 )); | |
312 | `endif | |
313 | ||
314 | endmodule | |
315 | // -------------------------------------------------- | |
316 | // File: cl_u1lvt_aoi22_12x.behV | |
317 | // Auto generated verilog module by HnBCellAuto | |
318 | // | |
319 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
320 | // By: balmiki | |
321 | // -------------------------------------------------- | |
322 | // | |
323 | module cl_u1lvt_aoi22_12x ( | |
324 | out, | |
325 | in10, | |
326 | in11, | |
327 | in00, | |
328 | in01 ); | |
329 | ||
330 | output out; | |
331 | input in10; | |
332 | input in11; | |
333 | input in00; | |
334 | input in01; | |
335 | ||
336 | `ifdef LIB | |
337 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
338 | `endif | |
339 | ||
340 | endmodule | |
341 | // -------------------------------------------------- | |
342 | // File: cl_u1lvt_aoi22_1x.behV | |
343 | // Auto generated verilog module by HnBCellAuto | |
344 | // | |
345 | // Created: Wednesday May 29,2002 at 04:04:32 PM PDT | |
346 | // By: balmiki | |
347 | // -------------------------------------------------- | |
348 | // | |
349 | module cl_u1lvt_aoi22_1x ( | |
350 | out, | |
351 | in10, | |
352 | in11, | |
353 | in00, | |
354 | in01 ); | |
355 | ||
356 | output out; | |
357 | input in10; | |
358 | input in11; | |
359 | input in00; | |
360 | input in01; | |
361 | ||
362 | `ifdef LIB | |
363 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
364 | `endif | |
365 | ||
366 | endmodule | |
367 | // -------------------------------------------------- | |
368 | // File: cl_u1lvt_aoi22_2x.behV | |
369 | // Auto generated verilog module by HnBCellAuto | |
370 | // | |
371 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
372 | // By: balmiki | |
373 | // -------------------------------------------------- | |
374 | // | |
375 | module cl_u1lvt_aoi22_2x ( | |
376 | out, | |
377 | in10, | |
378 | in11, | |
379 | in00, | |
380 | in01 ); | |
381 | ||
382 | output out; | |
383 | input in10; | |
384 | input in11; | |
385 | input in00; | |
386 | input in01; | |
387 | ||
388 | `ifdef LIB | |
389 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
390 | `endif | |
391 | ||
392 | endmodule | |
393 | // -------------------------------------------------- | |
394 | // File: cl_u1lvt_aoi22_4x.behV | |
395 | // Auto generated verilog module by HnBCellAuto | |
396 | // | |
397 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
398 | // By: balmiki | |
399 | // -------------------------------------------------- | |
400 | // | |
401 | module cl_u1lvt_aoi22_4x ( | |
402 | out, | |
403 | in10, | |
404 | in11, | |
405 | in00, | |
406 | in01 ); | |
407 | ||
408 | output out; | |
409 | input in10; | |
410 | input in11; | |
411 | input in00; | |
412 | input in01; | |
413 | ||
414 | `ifdef LIB | |
415 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
416 | `endif | |
417 | ||
418 | endmodule | |
419 | // -------------------------------------------------- | |
420 | // File: cl_u1lvt_aoi22_8x.behV | |
421 | // Auto generated verilog module by HnBCellAuto | |
422 | // | |
423 | // Created: Monday Oct 8,2001 at 11:32:16 AM PDT | |
424 | // By: balmiki | |
425 | // -------------------------------------------------- | |
426 | // | |
427 | module cl_u1lvt_aoi22_8x ( | |
428 | out, | |
429 | in10, | |
430 | in11, | |
431 | in00, | |
432 | in01 ); | |
433 | ||
434 | output out; | |
435 | input in10; | |
436 | input in11; | |
437 | input in00; | |
438 | input in01; | |
439 | ||
440 | `ifdef LIB | |
441 | assign out = ~(( in10 & in11 ) | ( in00 & in01 )); | |
442 | `endif | |
443 | ||
444 | endmodule | |
445 | // -------------------------------------------------- | |
446 | // File: cl_u1lvt_aoi33_1x.behV | |
447 | // Auto generated verilog module by HnBCellAuto | |
448 | // | |
449 | // Created: Thursday Dec 6,2001 at 02:09:02 PM PST | |
450 | // By: balmiki | |
451 | // -------------------------------------------------- | |
452 | // | |
453 | module cl_u1lvt_aoi33_1x ( | |
454 | out, | |
455 | in10, | |
456 | in11, | |
457 | in12, | |
458 | in00, | |
459 | in01, | |
460 | in02 ); | |
461 | ||
462 | output out; | |
463 | input in10; | |
464 | input in11; | |
465 | input in12; | |
466 | input in00; | |
467 | input in01; | |
468 | input in02; | |
469 | ||
470 | `ifdef LIB | |
471 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
472 | `endif | |
473 | ||
474 | endmodule | |
475 | // -------------------------------------------------- | |
476 | // File: cl_u1lvt_aoi33_2x.behV | |
477 | // Auto generated verilog module by HnBCellAuto | |
478 | // | |
479 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
480 | // By: balmiki | |
481 | // -------------------------------------------------- | |
482 | // | |
483 | module cl_u1lvt_aoi33_2x ( | |
484 | out, | |
485 | in10, | |
486 | in11, | |
487 | in12, | |
488 | in00, | |
489 | in01, | |
490 | in02 ); | |
491 | ||
492 | output out; | |
493 | input in10; | |
494 | input in11; | |
495 | input in12; | |
496 | input in00; | |
497 | input in01; | |
498 | input in02; | |
499 | ||
500 | `ifdef LIB | |
501 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
502 | `endif | |
503 | ||
504 | endmodule | |
505 | // -------------------------------------------------- | |
506 | // File: cl_u1lvt_aoi33_4x.behV | |
507 | // Auto generated verilog module by HnBCellAuto | |
508 | // | |
509 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
510 | // By: balmiki | |
511 | // -------------------------------------------------- | |
512 | // | |
513 | module cl_u1lvt_aoi33_4x ( | |
514 | out, | |
515 | in10, | |
516 | in11, | |
517 | in12, | |
518 | in00, | |
519 | in01, | |
520 | in02 ); | |
521 | ||
522 | output out; | |
523 | input in10; | |
524 | input in11; | |
525 | input in12; | |
526 | input in00; | |
527 | input in01; | |
528 | input in02; | |
529 | ||
530 | `ifdef LIB | |
531 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
532 | `endif | |
533 | ||
534 | endmodule | |
535 | // -------------------------------------------------- | |
536 | // File: cl_u1lvt_aoi33_8x.behV | |
537 | // Auto generated verilog module by HnBCellAuto | |
538 | // | |
539 | // Created: Monday Oct 8,2001 at 11:32:18 AM PDT | |
540 | // By: balmiki | |
541 | // -------------------------------------------------- | |
542 | // | |
543 | module cl_u1lvt_aoi33_8x ( | |
544 | out, | |
545 | in10, | |
546 | in11, | |
547 | in12, | |
548 | in00, | |
549 | in01, | |
550 | in02 ); | |
551 | ||
552 | output out; | |
553 | input in10; | |
554 | input in11; | |
555 | input in12; | |
556 | input in00; | |
557 | input in01; | |
558 | input in02; | |
559 | ||
560 | `ifdef LIB | |
561 | assign out = ~(( in10 & in11 & in12 ) | ( in00 & in01 & in02 )); | |
562 | `endif | |
563 | ||
564 | endmodule | |
565 | module cl_u1lvt_buf_12x ( | |
566 | in, | |
567 | out | |
568 | ); | |
569 | input in; | |
570 | output out; | |
571 | ||
572 | `ifdef LIB | |
573 | //assign out = in; | |
574 | buf (out, in); | |
575 | `endif | |
576 | ||
577 | endmodule | |
578 | module cl_u1lvt_buf_16x ( | |
579 | in, | |
580 | out | |
581 | ); | |
582 | input in; | |
583 | output out; | |
584 | ||
585 | `ifdef LIB | |
586 | //assign out = in; | |
587 | buf (out, in); | |
588 | `endif | |
589 | ||
590 | endmodule | |
591 | module cl_u1lvt_buf_1x ( | |
592 | in, | |
593 | out | |
594 | ); | |
595 | input in; | |
596 | output out; | |
597 | ||
598 | `ifdef LIB | |
599 | //assign out = in; | |
600 | buf (out, in); | |
601 | `endif | |
602 | ||
603 | endmodule | |
604 | module cl_u1lvt_buf_20x ( | |
605 | in, | |
606 | out | |
607 | ); | |
608 | input in; | |
609 | output out; | |
610 | ||
611 | `ifdef LIB | |
612 | //assign out = in; | |
613 | buf (out, in); | |
614 | `endif | |
615 | ||
616 | endmodule | |
617 | module cl_u1lvt_buf_24x ( | |
618 | in, | |
619 | out | |
620 | ); | |
621 | input in; | |
622 | output out; | |
623 | ||
624 | `ifdef LIB | |
625 | //assign out = in; | |
626 | buf (out, in); | |
627 | `endif | |
628 | ||
629 | endmodule | |
630 | module cl_u1lvt_buf_28x ( | |
631 | in, | |
632 | out | |
633 | ); | |
634 | input in; | |
635 | output out; | |
636 | ||
637 | `ifdef LIB | |
638 | //assign out = in; | |
639 | buf (out, in); | |
640 | `endif | |
641 | ||
642 | endmodule | |
643 | module cl_u1lvt_buf_2x ( | |
644 | in, | |
645 | out | |
646 | ); | |
647 | input in; | |
648 | output out; | |
649 | ||
650 | `ifdef LIB | |
651 | //assign out = in; | |
652 | buf (out, in); | |
653 | `endif | |
654 | ||
655 | endmodule | |
656 | module cl_u1lvt_buf_32x ( | |
657 | in, | |
658 | out | |
659 | ); | |
660 | input in; | |
661 | output out; | |
662 | ||
663 | `ifdef LIB | |
664 | //assign out = in; | |
665 | buf (out, in); | |
666 | `endif | |
667 | ||
668 | endmodule | |
669 | module cl_u1lvt_buf_36x ( | |
670 | in, | |
671 | out | |
672 | ); | |
673 | input in; | |
674 | output out; | |
675 | ||
676 | `ifdef LIB | |
677 | //assign out = in; | |
678 | buf (out, in); | |
679 | `endif | |
680 | ||
681 | endmodule | |
682 | module cl_u1lvt_buf_40x ( | |
683 | in, | |
684 | out | |
685 | ); | |
686 | input in; | |
687 | output out; | |
688 | ||
689 | `ifdef LIB | |
690 | //assign out = in; | |
691 | buf (out, in); | |
692 | `endif | |
693 | ||
694 | endmodule | |
695 | module cl_u1lvt_buf_44x ( | |
696 | in, | |
697 | out | |
698 | ); | |
699 | input in; | |
700 | output out; | |
701 | ||
702 | `ifdef LIB | |
703 | //assign out = in; | |
704 | buf (out, in); | |
705 | `endif | |
706 | ||
707 | endmodule | |
708 | module cl_u1lvt_buf_48x ( | |
709 | in, | |
710 | out | |
711 | ); | |
712 | input in; | |
713 | output out; | |
714 | ||
715 | `ifdef LIB | |
716 | //assign out = in; | |
717 | buf (out, in); | |
718 | `endif | |
719 | ||
720 | endmodule | |
721 | module cl_u1lvt_buf_4x ( | |
722 | in, | |
723 | out | |
724 | ); | |
725 | input in; | |
726 | output out; | |
727 | ||
728 | `ifdef LIB | |
729 | //assign out = in; | |
730 | buf (out, in); | |
731 | `endif | |
732 | ||
733 | endmodule | |
734 | module cl_u1lvt_buf_56x ( | |
735 | in, | |
736 | out | |
737 | ); | |
738 | input in; | |
739 | output out; | |
740 | ||
741 | `ifdef LIB | |
742 | //assign out = in; | |
743 | buf (out, in); | |
744 | `endif | |
745 | ||
746 | endmodule | |
747 | module cl_u1lvt_buf_64x ( | |
748 | in, | |
749 | out | |
750 | ); | |
751 | input in; | |
752 | output out; | |
753 | ||
754 | `ifdef LIB | |
755 | //assign out = in; | |
756 | buf (out, in); | |
757 | `endif | |
758 | ||
759 | endmodule | |
760 | module cl_u1lvt_buf_6x ( | |
761 | in, | |
762 | out | |
763 | ); | |
764 | input in; | |
765 | output out; | |
766 | ||
767 | `ifdef LIB | |
768 | //assign out = in; | |
769 | buf (out, in); | |
770 | `endif | |
771 | ||
772 | endmodule | |
773 | module cl_u1lvt_buf_8x ( | |
774 | in, | |
775 | out | |
776 | ); | |
777 | input in; | |
778 | output out; | |
779 | ||
780 | `ifdef LIB | |
781 | //assign out = in; | |
782 | buf (out, in); | |
783 | `endif | |
784 | ||
785 | endmodule | |
786 | module cl_u1lvt_inv_12x ( | |
787 | in, | |
788 | out | |
789 | ); | |
790 | input in; | |
791 | output out; | |
792 | ||
793 | `ifdef LIB | |
794 | //assign out = ~in; | |
795 | not (out, in); | |
796 | `endif | |
797 | ||
798 | endmodule | |
799 | module cl_u1lvt_inv_16x ( | |
800 | in, | |
801 | out | |
802 | ); | |
803 | input in; | |
804 | output out; | |
805 | ||
806 | `ifdef LIB | |
807 | //assign out = ~in; | |
808 | not (out, in); | |
809 | `endif | |
810 | ||
811 | endmodule | |
812 | module cl_u1lvt_inv_1x ( | |
813 | in, | |
814 | out | |
815 | ); | |
816 | input in; | |
817 | output out; | |
818 | ||
819 | `ifdef LIB | |
820 | //assign out = ~in; | |
821 | not (out, in); | |
822 | `endif | |
823 | ||
824 | endmodule | |
825 | module cl_u1lvt_inv_20x ( | |
826 | in, | |
827 | out | |
828 | ); | |
829 | input in; | |
830 | output out; | |
831 | ||
832 | `ifdef LIB | |
833 | //assign out = ~in; | |
834 | not (out, in); | |
835 | `endif | |
836 | ||
837 | endmodule | |
838 | module cl_u1lvt_inv_24x ( | |
839 | in, | |
840 | out | |
841 | ); | |
842 | input in; | |
843 | output out; | |
844 | ||
845 | `ifdef LIB | |
846 | //assign out = ~in; | |
847 | not (out, in); | |
848 | `endif | |
849 | ||
850 | endmodule | |
851 | module cl_u1lvt_inv_28x ( | |
852 | in, | |
853 | out | |
854 | ); | |
855 | input in; | |
856 | output out; | |
857 | ||
858 | `ifdef LIB | |
859 | //assign out = ~in; | |
860 | not (out, in); | |
861 | `endif | |
862 | ||
863 | endmodule | |
864 | module cl_u1lvt_inv_2x ( | |
865 | in, | |
866 | out | |
867 | ); | |
868 | input in; | |
869 | output out; | |
870 | ||
871 | `ifdef LIB | |
872 | //assign out = ~in; | |
873 | not (out, in); | |
874 | `endif | |
875 | ||
876 | endmodule | |
877 | module cl_u1lvt_inv_32x ( | |
878 | in, | |
879 | out | |
880 | ); | |
881 | input in; | |
882 | output out; | |
883 | ||
884 | `ifdef LIB | |
885 | //assign out = ~in; | |
886 | not (out, in); | |
887 | `endif | |
888 | ||
889 | endmodule | |
890 | module cl_u1lvt_inv_36x ( | |
891 | in, | |
892 | out | |
893 | ); | |
894 | input in; | |
895 | output out; | |
896 | ||
897 | `ifdef LIB | |
898 | //assign out = ~in; | |
899 | not (out, in); | |
900 | `endif | |
901 | ||
902 | endmodule | |
903 | module cl_u1lvt_inv_40x ( | |
904 | in, | |
905 | out | |
906 | ); | |
907 | input in; | |
908 | output out; | |
909 | ||
910 | `ifdef LIB | |
911 | //assign out = ~in; | |
912 | not (out, in); | |
913 | `endif | |
914 | ||
915 | endmodule | |
916 | module cl_u1lvt_inv_44x ( | |
917 | in, | |
918 | out | |
919 | ); | |
920 | input in; | |
921 | output out; | |
922 | ||
923 | `ifdef LIB | |
924 | //assign out = ~in; | |
925 | not (out, in); | |
926 | `endif | |
927 | ||
928 | endmodule | |
929 | module cl_u1lvt_inv_48x ( | |
930 | in, | |
931 | out | |
932 | ); | |
933 | input in; | |
934 | output out; | |
935 | ||
936 | `ifdef LIB | |
937 | //assign out = ~in; | |
938 | not (out, in); | |
939 | `endif | |
940 | ||
941 | endmodule | |
942 | module cl_u1lvt_inv_4x ( | |
943 | in, | |
944 | out | |
945 | ); | |
946 | input in; | |
947 | output out; | |
948 | ||
949 | `ifdef LIB | |
950 | //assign out = ~in; | |
951 | not (out, in); | |
952 | `endif | |
953 | ||
954 | endmodule | |
955 | module cl_u1lvt_inv_56x ( | |
956 | in, | |
957 | out | |
958 | ); | |
959 | input in; | |
960 | output out; | |
961 | ||
962 | `ifdef LIB | |
963 | //assign out = ~in; | |
964 | not (out, in); | |
965 | `endif | |
966 | ||
967 | endmodule | |
968 | module cl_u1lvt_inv_64x ( | |
969 | in, | |
970 | out | |
971 | ); | |
972 | input in; | |
973 | output out; | |
974 | ||
975 | `ifdef LIB | |
976 | //assign out = ~in; | |
977 | not (out, in); | |
978 | `endif | |
979 | ||
980 | endmodule | |
981 | module cl_u1lvt_inv_6x ( | |
982 | in, | |
983 | out | |
984 | ); | |
985 | input in; | |
986 | output out; | |
987 | ||
988 | `ifdef LIB | |
989 | //assign out = ~in; | |
990 | not (out, in); | |
991 | `endif | |
992 | ||
993 | endmodule | |
994 | module cl_u1lvt_inv_8x ( | |
995 | in, | |
996 | out | |
997 | ); | |
998 | input in; | |
999 | output out; | |
1000 | ||
1001 | `ifdef LIB | |
1002 | //assign out = ~in; | |
1003 | not (out, in); | |
1004 | `endif | |
1005 | ||
1006 | endmodule | |
1007 | module cl_u1lvt_nand2_12x ( | |
1008 | in0, | |
1009 | in1, | |
1010 | out | |
1011 | ); | |
1012 | input in0; | |
1013 | input in1; | |
1014 | output out; | |
1015 | ||
1016 | `ifdef LIB | |
1017 | assign out = ~(in0 & in1); | |
1018 | `endif | |
1019 | ||
1020 | endmodule | |
1021 | module cl_u1lvt_nand2_16x ( | |
1022 | in0, | |
1023 | in1, | |
1024 | out | |
1025 | ); | |
1026 | input in0; | |
1027 | input in1; | |
1028 | output out; | |
1029 | ||
1030 | `ifdef LIB | |
1031 | assign out = ~(in0 & in1); | |
1032 | `endif | |
1033 | ||
1034 | endmodule | |
1035 | module cl_u1lvt_nand2_1x ( | |
1036 | in0, | |
1037 | in1, | |
1038 | out | |
1039 | ); | |
1040 | input in0; | |
1041 | input in1; | |
1042 | output out; | |
1043 | ||
1044 | `ifdef LIB | |
1045 | assign out = ~(in0 & in1); | |
1046 | `endif | |
1047 | ||
1048 | endmodule | |
1049 | module cl_u1lvt_nand2_20x ( | |
1050 | in0, | |
1051 | in1, | |
1052 | out | |
1053 | ); | |
1054 | input in0; | |
1055 | input in1; | |
1056 | output out; | |
1057 | ||
1058 | `ifdef LIB | |
1059 | assign out = ~(in0 & in1); | |
1060 | `endif | |
1061 | ||
1062 | endmodule | |
1063 | module cl_u1lvt_nand2_24x ( | |
1064 | in0, | |
1065 | in1, | |
1066 | out | |
1067 | ); | |
1068 | input in0; | |
1069 | input in1; | |
1070 | output out; | |
1071 | ||
1072 | `ifdef LIB | |
1073 | assign out = ~(in0 & in1); | |
1074 | `endif | |
1075 | ||
1076 | endmodule | |
1077 | module cl_u1lvt_nand2_28x ( | |
1078 | in0, | |
1079 | in1, | |
1080 | out | |
1081 | ); | |
1082 | input in0; | |
1083 | input in1; | |
1084 | output out; | |
1085 | ||
1086 | `ifdef LIB | |
1087 | assign out = ~(in0 & in1); | |
1088 | `endif | |
1089 | ||
1090 | endmodule | |
1091 | module cl_u1lvt_nand2_2x ( | |
1092 | in0, | |
1093 | in1, | |
1094 | out | |
1095 | ); | |
1096 | input in0; | |
1097 | input in1; | |
1098 | output out; | |
1099 | ||
1100 | `ifdef LIB | |
1101 | assign out = ~(in0 & in1); | |
1102 | `endif | |
1103 | ||
1104 | endmodule | |
1105 | module cl_u1lvt_nand2_32x ( | |
1106 | in0, | |
1107 | in1, | |
1108 | out | |
1109 | ); | |
1110 | input in0; | |
1111 | input in1; | |
1112 | output out; | |
1113 | ||
1114 | `ifdef LIB | |
1115 | assign out = ~(in0 & in1); | |
1116 | `endif | |
1117 | ||
1118 | endmodule | |
1119 | module cl_u1lvt_nand2_4x ( | |
1120 | in0, | |
1121 | in1, | |
1122 | out | |
1123 | ); | |
1124 | input in0; | |
1125 | input in1; | |
1126 | output out; | |
1127 | ||
1128 | `ifdef LIB | |
1129 | assign out = ~(in0 & in1); | |
1130 | `endif | |
1131 | ||
1132 | endmodule | |
1133 | module cl_u1lvt_nand2_6x ( | |
1134 | in0, | |
1135 | in1, | |
1136 | out | |
1137 | ); | |
1138 | input in0; | |
1139 | input in1; | |
1140 | output out; | |
1141 | ||
1142 | `ifdef LIB | |
1143 | assign out = ~(in0 & in1); | |
1144 | `endif | |
1145 | ||
1146 | endmodule | |
1147 | module cl_u1lvt_nand2_8x ( | |
1148 | in0, | |
1149 | in1, | |
1150 | out | |
1151 | ); | |
1152 | input in0; | |
1153 | input in1; | |
1154 | output out; | |
1155 | ||
1156 | `ifdef LIB | |
1157 | assign out = ~(in0 & in1); | |
1158 | `endif | |
1159 | ||
1160 | endmodule | |
1161 | module cl_u1lvt_nand3_12x ( | |
1162 | in0, | |
1163 | in1, | |
1164 | in2, | |
1165 | out | |
1166 | ); | |
1167 | input in0; | |
1168 | input in1; | |
1169 | input in2; | |
1170 | output out; | |
1171 | ||
1172 | `ifdef LIB | |
1173 | assign out = ~(in0 & in1 & in2); | |
1174 | `endif | |
1175 | ||
1176 | endmodule | |
1177 | module cl_u1lvt_nand3_16x ( | |
1178 | in0, | |
1179 | in1, | |
1180 | in2, | |
1181 | out | |
1182 | ); | |
1183 | input in0; | |
1184 | input in1; | |
1185 | input in2; | |
1186 | output out; | |
1187 | ||
1188 | `ifdef LIB | |
1189 | assign out = ~(in0 & in1 & in2); | |
1190 | `endif | |
1191 | ||
1192 | endmodule | |
1193 | module cl_u1lvt_nand3_1x ( | |
1194 | in0, | |
1195 | in1, | |
1196 | in2, | |
1197 | out | |
1198 | ); | |
1199 | input in0; | |
1200 | input in1; | |
1201 | input in2; | |
1202 | output out; | |
1203 | ||
1204 | `ifdef LIB | |
1205 | assign out = ~(in0 & in1 & in2); | |
1206 | `endif | |
1207 | ||
1208 | endmodule | |
1209 | module cl_u1lvt_nand3_20x ( | |
1210 | in0, | |
1211 | in1, | |
1212 | in2, | |
1213 | out | |
1214 | ); | |
1215 | input in0; | |
1216 | input in1; | |
1217 | input in2; | |
1218 | output out; | |
1219 | ||
1220 | `ifdef LIB | |
1221 | assign out = ~(in0 & in1 & in2); | |
1222 | `endif | |
1223 | ||
1224 | endmodule | |
1225 | module cl_u1lvt_nand3_24x ( | |
1226 | in0, | |
1227 | in1, | |
1228 | in2, | |
1229 | out | |
1230 | ); | |
1231 | input in0; | |
1232 | input in1; | |
1233 | input in2; | |
1234 | output out; | |
1235 | ||
1236 | `ifdef LIB | |
1237 | assign out = ~(in0 & in1 & in2); | |
1238 | `endif | |
1239 | ||
1240 | endmodule | |
1241 | module cl_u1lvt_nand3_2x ( | |
1242 | in0, | |
1243 | in1, | |
1244 | in2, | |
1245 | out | |
1246 | ); | |
1247 | input in0; | |
1248 | input in1; | |
1249 | input in2; | |
1250 | output out; | |
1251 | ||
1252 | `ifdef LIB | |
1253 | assign out = ~(in0 & in1 & in2); | |
1254 | `endif | |
1255 | ||
1256 | endmodule | |
1257 | module cl_u1lvt_nand3_4x ( | |
1258 | in0, | |
1259 | in1, | |
1260 | in2, | |
1261 | out | |
1262 | ); | |
1263 | input in0; | |
1264 | input in1; | |
1265 | input in2; | |
1266 | output out; | |
1267 | ||
1268 | `ifdef LIB | |
1269 | assign out = ~(in0 & in1 & in2); | |
1270 | `endif | |
1271 | ||
1272 | endmodule | |
1273 | module cl_u1lvt_nand3_6x ( | |
1274 | in0, | |
1275 | in1, | |
1276 | in2, | |
1277 | out | |
1278 | ); | |
1279 | input in0; | |
1280 | input in1; | |
1281 | input in2; | |
1282 | output out; | |
1283 | ||
1284 | `ifdef LIB | |
1285 | assign out = ~(in0 & in1 & in2); | |
1286 | `endif | |
1287 | ||
1288 | endmodule | |
1289 | module cl_u1lvt_nand3_8x ( | |
1290 | in0, | |
1291 | in1, | |
1292 | in2, | |
1293 | out | |
1294 | ); | |
1295 | input in0; | |
1296 | input in1; | |
1297 | input in2; | |
1298 | output out; | |
1299 | ||
1300 | `ifdef LIB | |
1301 | assign out = ~(in0 & in1 & in2); | |
1302 | `endif | |
1303 | ||
1304 | endmodule | |
1305 | module cl_u1lvt_nand4_12x ( | |
1306 | in0, | |
1307 | in1, | |
1308 | in2, | |
1309 | in3, | |
1310 | out | |
1311 | ); | |
1312 | input in0; | |
1313 | input in1; | |
1314 | input in2; | |
1315 | input in3; | |
1316 | output out; | |
1317 | ||
1318 | `ifdef LIB | |
1319 | assign out = ~(in0 & in1 & in2 & in3); | |
1320 | `endif | |
1321 | ||
1322 | endmodule | |
1323 | module cl_u1lvt_nand4_16x ( | |
1324 | in0, | |
1325 | in1, | |
1326 | in2, | |
1327 | in3, | |
1328 | out | |
1329 | ); | |
1330 | input in0; | |
1331 | input in1; | |
1332 | input in2; | |
1333 | input in3; | |
1334 | output out; | |
1335 | ||
1336 | `ifdef LIB | |
1337 | assign out = ~(in0 & in1 & in2 & in3); | |
1338 | `endif | |
1339 | ||
1340 | endmodule | |
1341 | module cl_u1lvt_nand4_1x ( | |
1342 | in0, | |
1343 | in1, | |
1344 | in2, | |
1345 | in3, | |
1346 | out | |
1347 | ); | |
1348 | input in0; | |
1349 | input in1; | |
1350 | input in2; | |
1351 | input in3; | |
1352 | output out; | |
1353 | ||
1354 | `ifdef LIB | |
1355 | assign out = ~(in0 & in1 & in2 & in3); | |
1356 | `endif | |
1357 | ||
1358 | endmodule | |
1359 | module cl_u1lvt_nand4_2x ( | |
1360 | in0, | |
1361 | in1, | |
1362 | in2, | |
1363 | in3, | |
1364 | out | |
1365 | ); | |
1366 | input in0; | |
1367 | input in1; | |
1368 | input in2; | |
1369 | input in3; | |
1370 | output out; | |
1371 | ||
1372 | `ifdef LIB | |
1373 | assign out = ~(in0 & in1 & in2 & in3); | |
1374 | `endif | |
1375 | ||
1376 | endmodule | |
1377 | module cl_u1lvt_nand4_4x ( | |
1378 | in0, | |
1379 | in1, | |
1380 | in2, | |
1381 | in3, | |
1382 | out | |
1383 | ); | |
1384 | input in0; | |
1385 | input in1; | |
1386 | input in2; | |
1387 | input in3; | |
1388 | output out; | |
1389 | ||
1390 | `ifdef LIB | |
1391 | assign out = ~(in0 & in1 & in2 & in3); | |
1392 | `endif | |
1393 | ||
1394 | endmodule | |
1395 | module cl_u1lvt_nand4_6x ( | |
1396 | in0, | |
1397 | in1, | |
1398 | in2, | |
1399 | in3, | |
1400 | out | |
1401 | ); | |
1402 | input in0; | |
1403 | input in1; | |
1404 | input in2; | |
1405 | input in3; | |
1406 | output out; | |
1407 | ||
1408 | `ifdef LIB | |
1409 | assign out = ~(in0 & in1 & in2 & in3); | |
1410 | `endif | |
1411 | ||
1412 | endmodule | |
1413 | module cl_u1lvt_nand4_8x ( | |
1414 | in0, | |
1415 | in1, | |
1416 | in2, | |
1417 | in3, | |
1418 | out | |
1419 | ); | |
1420 | input in0; | |
1421 | input in1; | |
1422 | input in2; | |
1423 | input in3; | |
1424 | output out; | |
1425 | ||
1426 | `ifdef LIB | |
1427 | assign out = ~(in0 & in1 & in2 & in3); | |
1428 | `endif | |
1429 | ||
1430 | endmodule | |
1431 | module cl_u1lvt_nor2_12x ( | |
1432 | in0, | |
1433 | in1, | |
1434 | out | |
1435 | ); | |
1436 | input in0; | |
1437 | input in1; | |
1438 | output out; | |
1439 | ||
1440 | `ifdef LIB | |
1441 | assign out = ~(in0 | in1); | |
1442 | `endif | |
1443 | ||
1444 | endmodule | |
1445 | module cl_u1lvt_nor2_16x ( | |
1446 | in0, | |
1447 | in1, | |
1448 | out | |
1449 | ); | |
1450 | input in0; | |
1451 | input in1; | |
1452 | output out; | |
1453 | ||
1454 | `ifdef LIB | |
1455 | assign out = ~(in0 | in1); | |
1456 | `endif | |
1457 | ||
1458 | endmodule | |
1459 | module cl_u1lvt_nor2_1x ( | |
1460 | in0, | |
1461 | in1, | |
1462 | out | |
1463 | ); | |
1464 | input in0; | |
1465 | input in1; | |
1466 | output out; | |
1467 | ||
1468 | `ifdef LIB | |
1469 | assign out = ~(in0 | in1); | |
1470 | `endif | |
1471 | ||
1472 | endmodule | |
1473 | module cl_u1lvt_nor2_2x ( | |
1474 | in0, | |
1475 | in1, | |
1476 | out | |
1477 | ); | |
1478 | input in0; | |
1479 | input in1; | |
1480 | output out; | |
1481 | ||
1482 | `ifdef LIB | |
1483 | assign out = ~(in0 | in1); | |
1484 | `endif | |
1485 | ||
1486 | endmodule | |
1487 | module cl_u1lvt_nor2_4x ( | |
1488 | in0, | |
1489 | in1, | |
1490 | out | |
1491 | ); | |
1492 | input in0; | |
1493 | input in1; | |
1494 | output out; | |
1495 | ||
1496 | `ifdef LIB | |
1497 | assign out = ~(in0 | in1); | |
1498 | `endif | |
1499 | ||
1500 | endmodule | |
1501 | module cl_u1lvt_nor2_6x ( | |
1502 | in0, | |
1503 | in1, | |
1504 | out | |
1505 | ); | |
1506 | input in0; | |
1507 | input in1; | |
1508 | output out; | |
1509 | ||
1510 | `ifdef LIB | |
1511 | assign out = ~(in0 | in1); | |
1512 | `endif | |
1513 | ||
1514 | endmodule | |
1515 | module cl_u1lvt_nor2_8x ( | |
1516 | in0, | |
1517 | in1, | |
1518 | out | |
1519 | ); | |
1520 | input in0; | |
1521 | input in1; | |
1522 | output out; | |
1523 | ||
1524 | `ifdef LIB | |
1525 | assign out = ~(in0 | in1); | |
1526 | `endif | |
1527 | ||
1528 | endmodule | |
1529 | module cl_u1lvt_nor3_1x ( | |
1530 | in0, | |
1531 | in1, | |
1532 | in2, | |
1533 | out | |
1534 | ); | |
1535 | input in0; | |
1536 | input in1; | |
1537 | input in2; | |
1538 | output out; | |
1539 | ||
1540 | `ifdef LIB | |
1541 | assign out = ~(in0 | in1 | in2); | |
1542 | `endif | |
1543 | ||
1544 | endmodule | |
1545 | module cl_u1lvt_nor3_2x ( | |
1546 | in0, | |
1547 | in1, | |
1548 | in2, | |
1549 | out | |
1550 | ); | |
1551 | input in0; | |
1552 | input in1; | |
1553 | input in2; | |
1554 | output out; | |
1555 | ||
1556 | `ifdef LIB | |
1557 | assign out = ~(in0 | in1 | in2); | |
1558 | `endif | |
1559 | ||
1560 | endmodule | |
1561 | module cl_u1lvt_nor3_4x ( | |
1562 | in0, | |
1563 | in1, | |
1564 | in2, | |
1565 | out | |
1566 | ); | |
1567 | input in0; | |
1568 | input in1; | |
1569 | input in2; | |
1570 | output out; | |
1571 | ||
1572 | `ifdef LIB | |
1573 | assign out = ~(in0 | in1 | in2); | |
1574 | `endif | |
1575 | ||
1576 | endmodule | |
1577 | // -------------------------------------------------- | |
1578 | // File: cl_u1lvt_oai12_12x.behV | |
1579 | // Auto generated verilog module by HnBCellAuto | |
1580 | // | |
1581 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1582 | // By: balmiki | |
1583 | // -------------------------------------------------- | |
1584 | // | |
1585 | module cl_u1lvt_oai12_12x ( | |
1586 | out, | |
1587 | in10, | |
1588 | in00, | |
1589 | in01 ); | |
1590 | ||
1591 | output out; | |
1592 | input in10; | |
1593 | input in00; | |
1594 | input in01; | |
1595 | ||
1596 | `ifdef LIB | |
1597 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1598 | `endif | |
1599 | ||
1600 | endmodule | |
1601 | // -------------------------------------------------- | |
1602 | // File: cl_u1lvt_oai12_16x.behV | |
1603 | // Auto generated verilog module by HnBCellAuto | |
1604 | // | |
1605 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1606 | // By: balmiki | |
1607 | // -------------------------------------------------- | |
1608 | // | |
1609 | module cl_u1lvt_oai12_16x ( | |
1610 | out, | |
1611 | in10, | |
1612 | in00, | |
1613 | in01 ); | |
1614 | ||
1615 | output out; | |
1616 | input in10; | |
1617 | input in00; | |
1618 | input in01; | |
1619 | ||
1620 | `ifdef LIB | |
1621 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1622 | `endif | |
1623 | ||
1624 | endmodule | |
1625 | // -------------------------------------------------- | |
1626 | // File: cl_u1lvt_oai12_1x.behV | |
1627 | // Auto generated verilog module by HnBCellAuto | |
1628 | // | |
1629 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1630 | // By: balmiki | |
1631 | // -------------------------------------------------- | |
1632 | // | |
1633 | module cl_u1lvt_oai12_1x ( | |
1634 | out, | |
1635 | in10, | |
1636 | in00, | |
1637 | in01 ); | |
1638 | ||
1639 | output out; | |
1640 | input in10; | |
1641 | input in00; | |
1642 | input in01; | |
1643 | ||
1644 | `ifdef LIB | |
1645 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1646 | `endif | |
1647 | ||
1648 | endmodule | |
1649 | // -------------------------------------------------- | |
1650 | // File: cl_u1lvt_oai12_2x.behV | |
1651 | // Auto generated verilog module by HnBCellAuto | |
1652 | // | |
1653 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1654 | // By: balmiki | |
1655 | // -------------------------------------------------- | |
1656 | // | |
1657 | module cl_u1lvt_oai12_2x ( | |
1658 | out, | |
1659 | in10, | |
1660 | in00, | |
1661 | in01 ); | |
1662 | ||
1663 | output out; | |
1664 | input in10; | |
1665 | input in00; | |
1666 | input in01; | |
1667 | ||
1668 | `ifdef LIB | |
1669 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1670 | `endif | |
1671 | ||
1672 | endmodule | |
1673 | // -------------------------------------------------- | |
1674 | // File: cl_u1lvt_oai12_4x.behV | |
1675 | // Auto generated verilog module by HnBCellAuto | |
1676 | // | |
1677 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1678 | // By: balmiki | |
1679 | // -------------------------------------------------- | |
1680 | // | |
1681 | module cl_u1lvt_oai12_4x ( | |
1682 | out, | |
1683 | in10, | |
1684 | in00, | |
1685 | in01 ); | |
1686 | ||
1687 | output out; | |
1688 | input in10; | |
1689 | input in00; | |
1690 | input in01; | |
1691 | ||
1692 | `ifdef LIB | |
1693 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1694 | `endif | |
1695 | ||
1696 | endmodule | |
1697 | // -------------------------------------------------- | |
1698 | // File: cl_u1lvt_oai12_8x.behV | |
1699 | // Auto generated verilog module by HnBCellAuto | |
1700 | // | |
1701 | // Created: Wednesday May 29,2002 at 04:04:34 PM PDT | |
1702 | // By: balmiki | |
1703 | // -------------------------------------------------- | |
1704 | // | |
1705 | module cl_u1lvt_oai12_8x ( | |
1706 | out, | |
1707 | in10, | |
1708 | in00, | |
1709 | in01 ); | |
1710 | ||
1711 | output out; | |
1712 | input in10; | |
1713 | input in00; | |
1714 | input in01; | |
1715 | ||
1716 | `ifdef LIB | |
1717 | assign out = ~(( in10 ) & ( in00 | in01 )); | |
1718 | `endif | |
1719 | ||
1720 | endmodule | |
1721 | // -------------------------------------------------- | |
1722 | // File: cl_u1lvt_oai21_12x.behV | |
1723 | // Auto generated verilog module by HnBCellAuto | |
1724 | // | |
1725 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1726 | // By: balmiki | |
1727 | // -------------------------------------------------- | |
1728 | // | |
1729 | module cl_u1lvt_oai21_12x ( | |
1730 | out, | |
1731 | in10, | |
1732 | in11, | |
1733 | in00 ); | |
1734 | ||
1735 | output out; | |
1736 | input in10; | |
1737 | input in11; | |
1738 | input in00; | |
1739 | ||
1740 | `ifdef LIB | |
1741 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1742 | `endif | |
1743 | ||
1744 | endmodule | |
1745 | // -------------------------------------------------- | |
1746 | // File: cl_u1lvt_oai21_16x.behV | |
1747 | // Auto generated verilog module by HnBCellAuto | |
1748 | // | |
1749 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1750 | // By: balmiki | |
1751 | // -------------------------------------------------- | |
1752 | // | |
1753 | module cl_u1lvt_oai21_16x ( | |
1754 | out, | |
1755 | in10, | |
1756 | in11, | |
1757 | in00 ); | |
1758 | ||
1759 | output out; | |
1760 | input in10; | |
1761 | input in11; | |
1762 | input in00; | |
1763 | ||
1764 | `ifdef LIB | |
1765 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1766 | `endif | |
1767 | ||
1768 | endmodule | |
1769 | // -------------------------------------------------- | |
1770 | // File: cl_u1lvt_oai21_1x.behV | |
1771 | // Auto generated verilog module by HnBCellAuto | |
1772 | // | |
1773 | // Created: Friday Mar 15,2002 at 02:53:58 PM PST | |
1774 | // By: balmiki | |
1775 | // -------------------------------------------------- | |
1776 | // | |
1777 | module cl_u1lvt_oai21_1x ( | |
1778 | out, | |
1779 | in10, | |
1780 | in11, | |
1781 | in00 ); | |
1782 | ||
1783 | output out; | |
1784 | input in10; | |
1785 | input in11; | |
1786 | input in00; | |
1787 | ||
1788 | `ifdef LIB | |
1789 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1790 | `endif | |
1791 | ||
1792 | endmodule | |
1793 | // -------------------------------------------------- | |
1794 | // File: cl_u1lvt_oai21_2x.behV | |
1795 | // Auto generated verilog module by HnBCellAuto | |
1796 | // | |
1797 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1798 | // By: balmiki | |
1799 | // -------------------------------------------------- | |
1800 | // | |
1801 | module cl_u1lvt_oai21_2x ( | |
1802 | out, | |
1803 | in10, | |
1804 | in11, | |
1805 | in00 ); | |
1806 | ||
1807 | output out; | |
1808 | input in10; | |
1809 | input in11; | |
1810 | input in00; | |
1811 | ||
1812 | `ifdef LIB | |
1813 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1814 | `endif | |
1815 | ||
1816 | endmodule | |
1817 | // -------------------------------------------------- | |
1818 | // File: cl_u1lvt_oai21_4x.behV | |
1819 | // Auto generated verilog module by HnBCellAuto | |
1820 | // | |
1821 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1822 | // By: balmiki | |
1823 | // -------------------------------------------------- | |
1824 | // | |
1825 | module cl_u1lvt_oai21_4x ( | |
1826 | out, | |
1827 | in10, | |
1828 | in11, | |
1829 | in00 ); | |
1830 | ||
1831 | output out; | |
1832 | input in10; | |
1833 | input in11; | |
1834 | input in00; | |
1835 | ||
1836 | `ifdef LIB | |
1837 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1838 | `endif | |
1839 | ||
1840 | endmodule | |
1841 | // -------------------------------------------------- | |
1842 | // File: cl_u1lvt_oai21_8x.behV | |
1843 | // Auto generated verilog module by HnBCellAuto | |
1844 | // | |
1845 | // Created: Monday Oct 8,2001 at 11:32:23 AM PDT | |
1846 | // By: balmiki | |
1847 | // -------------------------------------------------- | |
1848 | // | |
1849 | module cl_u1lvt_oai21_8x ( | |
1850 | out, | |
1851 | in10, | |
1852 | in11, | |
1853 | in00 ); | |
1854 | ||
1855 | output out; | |
1856 | input in10; | |
1857 | input in11; | |
1858 | input in00; | |
1859 | ||
1860 | `ifdef LIB | |
1861 | assign out = ~(( in10 | in11 ) & ( in00 )); | |
1862 | `endif | |
1863 | ||
1864 | endmodule | |
1865 | // -------------------------------------------------- | |
1866 | // File: cl_u1lvt_oai22_12x.behV | |
1867 | // Auto generated verilog module by HnBCellAuto | |
1868 | // | |
1869 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1870 | // By: balmiki | |
1871 | // -------------------------------------------------- | |
1872 | // | |
1873 | module cl_u1lvt_oai22_12x ( | |
1874 | out, | |
1875 | in10, | |
1876 | in11, | |
1877 | in00, | |
1878 | in01 ); | |
1879 | ||
1880 | output out; | |
1881 | input in10; | |
1882 | input in11; | |
1883 | input in00; | |
1884 | input in01; | |
1885 | ||
1886 | `ifdef LIB | |
1887 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1888 | `endif | |
1889 | ||
1890 | endmodule | |
1891 | // -------------------------------------------------- | |
1892 | // File: cl_u1lvt_oai22_16x.behV | |
1893 | // Auto generated verilog module by HnBCellAuto | |
1894 | // | |
1895 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1896 | // By: balmiki | |
1897 | // -------------------------------------------------- | |
1898 | // | |
1899 | module cl_u1lvt_oai22_16x ( | |
1900 | out, | |
1901 | in10, | |
1902 | in11, | |
1903 | in00, | |
1904 | in01 ); | |
1905 | ||
1906 | output out; | |
1907 | input in10; | |
1908 | input in11; | |
1909 | input in00; | |
1910 | input in01; | |
1911 | ||
1912 | `ifdef LIB | |
1913 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1914 | `endif | |
1915 | ||
1916 | endmodule | |
1917 | // -------------------------------------------------- | |
1918 | // File: cl_u1lvt_oai22_1x.behV | |
1919 | // Auto generated verilog module by HnBCellAuto | |
1920 | // | |
1921 | // Created: Wednesday May 29,2002 at 04:04:35 PM PDT | |
1922 | // By: balmiki | |
1923 | // -------------------------------------------------- | |
1924 | // | |
1925 | module cl_u1lvt_oai22_1x ( | |
1926 | out, | |
1927 | in10, | |
1928 | in11, | |
1929 | in00, | |
1930 | in01 ); | |
1931 | ||
1932 | output out; | |
1933 | input in10; | |
1934 | input in11; | |
1935 | input in00; | |
1936 | input in01; | |
1937 | ||
1938 | `ifdef LIB | |
1939 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1940 | `endif | |
1941 | ||
1942 | endmodule | |
1943 | // -------------------------------------------------- | |
1944 | // File: cl_u1lvt_oai22_2x.behV | |
1945 | // Auto generated verilog module by HnBCellAuto | |
1946 | // | |
1947 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1948 | // By: balmiki | |
1949 | // -------------------------------------------------- | |
1950 | // | |
1951 | module cl_u1lvt_oai22_2x ( | |
1952 | out, | |
1953 | in10, | |
1954 | in11, | |
1955 | in00, | |
1956 | in01 ); | |
1957 | ||
1958 | output out; | |
1959 | input in10; | |
1960 | input in11; | |
1961 | input in00; | |
1962 | input in01; | |
1963 | ||
1964 | `ifdef LIB | |
1965 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1966 | `endif | |
1967 | ||
1968 | endmodule | |
1969 | // -------------------------------------------------- | |
1970 | // File: cl_u1lvt_oai22_4x.behV | |
1971 | // Auto generated verilog module by HnBCellAuto | |
1972 | // | |
1973 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
1974 | // By: balmiki | |
1975 | // -------------------------------------------------- | |
1976 | // | |
1977 | module cl_u1lvt_oai22_4x ( | |
1978 | out, | |
1979 | in10, | |
1980 | in11, | |
1981 | in00, | |
1982 | in01 ); | |
1983 | ||
1984 | output out; | |
1985 | input in10; | |
1986 | input in11; | |
1987 | input in00; | |
1988 | input in01; | |
1989 | ||
1990 | `ifdef LIB | |
1991 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
1992 | `endif | |
1993 | ||
1994 | endmodule | |
1995 | // -------------------------------------------------- | |
1996 | // File: cl_u1lvt_oai22_8x.behV | |
1997 | // Auto generated verilog module by HnBCellAuto | |
1998 | // | |
1999 | // Created: Monday Oct 8,2001 at 11:32:24 AM PDT | |
2000 | // By: balmiki | |
2001 | // -------------------------------------------------- | |
2002 | // | |
2003 | module cl_u1lvt_oai22_8x ( | |
2004 | out, | |
2005 | in10, | |
2006 | in11, | |
2007 | in00, | |
2008 | in01 ); | |
2009 | ||
2010 | output out; | |
2011 | input in10; | |
2012 | input in11; | |
2013 | input in00; | |
2014 | input in01; | |
2015 | ||
2016 | `ifdef LIB | |
2017 | assign out = ~(( in10 | in11 ) & ( in00 | in01 )); | |
2018 | `endif | |
2019 | ||
2020 | endmodule | |
2021 | module cl_u1lvt_rep_dcp_32x ( | |
2022 | in, | |
2023 | out | |
2024 | ); | |
2025 | input in; | |
2026 | output out; | |
2027 | ||
2028 | `ifdef LIB | |
2029 | //assign out = in; | |
2030 | buf (out, in); | |
2031 | `endif | |
2032 | ||
2033 | endmodule | |
2034 | module cl_u1lvt_rep_dcp_48x ( | |
2035 | in, | |
2036 | out | |
2037 | ); | |
2038 | input in; | |
2039 | output out; | |
2040 | ||
2041 | `ifdef LIB | |
2042 | //assign out = in; | |
2043 | buf (out, in); | |
2044 | `endif | |
2045 | ||
2046 | endmodule | |
2047 | module cl_u1lvt_rep_8x ( | |
2048 | in, | |
2049 | out | |
2050 | ); | |
2051 | input in; | |
2052 | output out; | |
2053 | ||
2054 | `ifdef LIB | |
2055 | //assign out = in; | |
2056 | buf (out, in); | |
2057 | `endif | |
2058 | ||
2059 | endmodule | |
2060 | module cl_u1lvt_rep_16x ( | |
2061 | in, | |
2062 | out | |
2063 | ); | |
2064 | input in; | |
2065 | output out; | |
2066 | ||
2067 | `ifdef LIB | |
2068 | //assign out = in; | |
2069 | buf (out, in); | |
2070 | `endif | |
2071 | ||
2072 | endmodule | |
2073 | module cl_u1lvt_rep_24x ( | |
2074 | in, | |
2075 | out | |
2076 | ); | |
2077 | input in; | |
2078 | output out; | |
2079 | ||
2080 | `ifdef LIB | |
2081 | //assign out = in; | |
2082 | buf (out, in); | |
2083 | `endif | |
2084 | ||
2085 | endmodule | |
2086 | module cl_u1lvt_rep_32x ( | |
2087 | in, | |
2088 | out | |
2089 | ); | |
2090 | input in; | |
2091 | output out; | |
2092 | ||
2093 | `ifdef LIB | |
2094 | //assign out = in; | |
2095 | buf (out, in); | |
2096 | `endif | |
2097 | ||
2098 | endmodule | |
2099 | module cl_u1lvt_rep_40x ( | |
2100 | in, | |
2101 | out | |
2102 | ); | |
2103 | input in; | |
2104 | output out; | |
2105 | ||
2106 | `ifdef LIB | |
2107 | //assign out = in; | |
2108 | buf (out, in); | |
2109 | `endif | |
2110 | ||
2111 | endmodule | |
2112 | module cl_u1lvt_rep_48x ( | |
2113 | in, | |
2114 | out | |
2115 | ); | |
2116 | input in; | |
2117 | output out; | |
2118 | ||
2119 | `ifdef LIB | |
2120 | //assign out = in; | |
2121 | buf (out, in); | |
2122 | `endif | |
2123 | ||
2124 | endmodule | |
2125 | module cl_u1lvt_xnor2_16x ( | |
2126 | in0, | |
2127 | in1, | |
2128 | out | |
2129 | ); | |
2130 | input in0; | |
2131 | input in1; | |
2132 | output out; | |
2133 | ||
2134 | `ifdef LIB | |
2135 | assign out = ~(in0 ^ in1); | |
2136 | `endif | |
2137 | ||
2138 | endmodule | |
2139 | module cl_u1lvt_xnor2_1x ( | |
2140 | in0, | |
2141 | in1, | |
2142 | out | |
2143 | ); | |
2144 | input in0; | |
2145 | input in1; | |
2146 | output out; | |
2147 | ||
2148 | `ifdef LIB | |
2149 | assign out = ~(in0 ^ in1); | |
2150 | `endif | |
2151 | ||
2152 | endmodule | |
2153 | module cl_u1lvt_xnor2_2x ( | |
2154 | in0, | |
2155 | in1, | |
2156 | out | |
2157 | ); | |
2158 | input in0; | |
2159 | input in1; | |
2160 | output out; | |
2161 | ||
2162 | `ifdef LIB | |
2163 | assign out = ~(in0 ^ in1); | |
2164 | `endif | |
2165 | ||
2166 | endmodule | |
2167 | module cl_u1lvt_xnor2_4x ( | |
2168 | in0, | |
2169 | in1, | |
2170 | out | |
2171 | ); | |
2172 | input in0; | |
2173 | input in1; | |
2174 | output out; | |
2175 | ||
2176 | `ifdef LIB | |
2177 | assign out = ~(in0 ^ in1); | |
2178 | `endif | |
2179 | ||
2180 | endmodule | |
2181 | module cl_u1lvt_xnor2_6x ( | |
2182 | in0, | |
2183 | in1, | |
2184 | out | |
2185 | ); | |
2186 | input in0; | |
2187 | input in1; | |
2188 | output out; | |
2189 | ||
2190 | `ifdef LIB | |
2191 | assign out = ~(in0 ^ in1); | |
2192 | `endif | |
2193 | ||
2194 | endmodule | |
2195 | module cl_u1lvt_xnor2_8x ( | |
2196 | in0, | |
2197 | in1, | |
2198 | out | |
2199 | ); | |
2200 | input in0; | |
2201 | input in1; | |
2202 | output out; | |
2203 | ||
2204 | `ifdef LIB | |
2205 | assign out = ~(in0 ^ in1); | |
2206 | `endif | |
2207 | ||
2208 | endmodule | |
2209 | module cl_u1lvt_xnor3_16x ( | |
2210 | in0, | |
2211 | in1, | |
2212 | in2, | |
2213 | out | |
2214 | ); | |
2215 | input in0; | |
2216 | input in1; | |
2217 | input in2; | |
2218 | output out; | |
2219 | ||
2220 | `ifdef LIB | |
2221 | assign out = ~(in0 ^ in1 ^ in2); | |
2222 | `endif | |
2223 | ||
2224 | ||
2225 | ||
2226 | endmodule | |
2227 | module cl_u1lvt_xnor3_1x ( | |
2228 | in0, | |
2229 | in1, | |
2230 | in2, | |
2231 | out | |
2232 | ); | |
2233 | input in0; | |
2234 | input in1; | |
2235 | input in2; | |
2236 | output out; | |
2237 | ||
2238 | `ifdef LIB | |
2239 | assign out = ~(in0 ^ in1 ^ in2); | |
2240 | `endif | |
2241 | ||
2242 | ||
2243 | ||
2244 | endmodule | |
2245 | module cl_u1lvt_xnor3_2x ( | |
2246 | in0, | |
2247 | in1, | |
2248 | in2, | |
2249 | out | |
2250 | ); | |
2251 | input in0; | |
2252 | input in1; | |
2253 | input in2; | |
2254 | output out; | |
2255 | ||
2256 | `ifdef LIB | |
2257 | assign out = ~(in0 ^ in1 ^ in2); | |
2258 | `endif | |
2259 | ||
2260 | ||
2261 | ||
2262 | endmodule | |
2263 | module cl_u1lvt_xnor3_4x ( | |
2264 | in0, | |
2265 | in1, | |
2266 | in2, | |
2267 | out | |
2268 | ); | |
2269 | input in0; | |
2270 | input in1; | |
2271 | input in2; | |
2272 | output out; | |
2273 | ||
2274 | `ifdef LIB | |
2275 | assign out = ~(in0 ^ in1 ^ in2); | |
2276 | `endif | |
2277 | ||
2278 | ||
2279 | ||
2280 | endmodule | |
2281 | module cl_u1lvt_xnor3_6x ( | |
2282 | in0, | |
2283 | in1, | |
2284 | in2, | |
2285 | out | |
2286 | ); | |
2287 | input in0; | |
2288 | input in1; | |
2289 | input in2; | |
2290 | output out; | |
2291 | ||
2292 | `ifdef LIB | |
2293 | assign out = ~(in0 ^ in1 ^ in2); | |
2294 | `endif | |
2295 | ||
2296 | ||
2297 | ||
2298 | endmodule | |
2299 | module cl_u1lvt_xnor3_8x ( | |
2300 | in0, | |
2301 | in1, | |
2302 | in2, | |
2303 | out | |
2304 | ); | |
2305 | input in0; | |
2306 | input in1; | |
2307 | input in2; | |
2308 | output out; | |
2309 | ||
2310 | `ifdef LIB | |
2311 | assign out = ~(in0 ^ in1 ^ in2); | |
2312 | `endif | |
2313 | ||
2314 | ||
2315 | ||
2316 | endmodule | |
2317 | module cl_u1lvt_xor2_16x ( | |
2318 | in0, | |
2319 | in1, | |
2320 | out | |
2321 | ); | |
2322 | input in0; | |
2323 | input in1; | |
2324 | output out; | |
2325 | ||
2326 | `ifdef LIB | |
2327 | assign out = in0 ^ in1; | |
2328 | `endif | |
2329 | ||
2330 | endmodule | |
2331 | module cl_u1lvt_xor2_1x ( | |
2332 | in0, | |
2333 | in1, | |
2334 | out | |
2335 | ); | |
2336 | input in0; | |
2337 | input in1; | |
2338 | output out; | |
2339 | ||
2340 | `ifdef LIB | |
2341 | assign out = in0 ^ in1; | |
2342 | `endif | |
2343 | ||
2344 | endmodule | |
2345 | module cl_u1lvt_xor2_2x ( | |
2346 | in0, | |
2347 | in1, | |
2348 | out | |
2349 | ); | |
2350 | input in0; | |
2351 | input in1; | |
2352 | output out; | |
2353 | ||
2354 | `ifdef LIB | |
2355 | assign out = in0 ^ in1; | |
2356 | `endif | |
2357 | ||
2358 | endmodule | |
2359 | module cl_u1lvt_xor2_4x ( | |
2360 | in0, | |
2361 | in1, | |
2362 | out | |
2363 | ); | |
2364 | input in0; | |
2365 | input in1; | |
2366 | output out; | |
2367 | ||
2368 | `ifdef LIB | |
2369 | assign out = in0 ^ in1; | |
2370 | `endif | |
2371 | ||
2372 | endmodule | |
2373 | module cl_u1lvt_xor2_6x ( | |
2374 | in0, | |
2375 | in1, | |
2376 | out | |
2377 | ); | |
2378 | input in0; | |
2379 | input in1; | |
2380 | output out; | |
2381 | ||
2382 | `ifdef LIB | |
2383 | assign out = in0 ^ in1; | |
2384 | `endif | |
2385 | ||
2386 | endmodule | |
2387 | module cl_u1lvt_xor2_8x ( | |
2388 | in0, | |
2389 | in1, | |
2390 | out | |
2391 | ); | |
2392 | input in0; | |
2393 | input in1; | |
2394 | output out; | |
2395 | ||
2396 | `ifdef LIB | |
2397 | assign out = in0 ^ in1; | |
2398 | `endif | |
2399 | ||
2400 | endmodule | |
2401 | module cl_u1lvt_xor3_16x ( | |
2402 | in0, | |
2403 | in1, | |
2404 | in2, | |
2405 | out | |
2406 | ); | |
2407 | input in0; | |
2408 | input in1; | |
2409 | input in2; | |
2410 | output out; | |
2411 | ||
2412 | `ifdef LIB | |
2413 | assign out = in0 ^ in1 ^ in2; | |
2414 | `endif | |
2415 | ||
2416 | ||
2417 | endmodule | |
2418 | module cl_u1lvt_xor3_1x ( | |
2419 | in0, | |
2420 | in1, | |
2421 | in2, | |
2422 | out | |
2423 | ); | |
2424 | input in0; | |
2425 | input in1; | |
2426 | input in2; | |
2427 | output out; | |
2428 | ||
2429 | `ifdef LIB | |
2430 | assign out = in0 ^ in1 ^ in2; | |
2431 | `endif | |
2432 | ||
2433 | ||
2434 | endmodule | |
2435 | module cl_u1lvt_xor3_2x ( | |
2436 | in0, | |
2437 | in1, | |
2438 | in2, | |
2439 | out | |
2440 | ); | |
2441 | input in0; | |
2442 | input in1; | |
2443 | input in2; | |
2444 | output out; | |
2445 | ||
2446 | `ifdef LIB | |
2447 | assign out = in0 ^ in1 ^ in2; | |
2448 | `endif | |
2449 | ||
2450 | ||
2451 | endmodule | |
2452 | module cl_u1lvt_xor3_4x ( | |
2453 | in0, | |
2454 | in1, | |
2455 | in2, | |
2456 | out | |
2457 | ); | |
2458 | input in0; | |
2459 | input in1; | |
2460 | input in2; | |
2461 | output out; | |
2462 | ||
2463 | `ifdef LIB | |
2464 | assign out = in0 ^ in1 ^ in2; | |
2465 | `endif | |
2466 | ||
2467 | ||
2468 | endmodule | |
2469 | module cl_u1lvt_xor3_6x ( | |
2470 | in0, | |
2471 | in1, | |
2472 | in2, | |
2473 | out | |
2474 | ); | |
2475 | input in0; | |
2476 | input in1; | |
2477 | input in2; | |
2478 | output out; | |
2479 | ||
2480 | `ifdef LIB | |
2481 | assign out = in0 ^ in1 ^ in2; | |
2482 | `endif | |
2483 | ||
2484 | ||
2485 | endmodule | |
2486 | module cl_u1lvt_xor3_8x ( | |
2487 | in0, | |
2488 | in1, | |
2489 | in2, | |
2490 | out | |
2491 | ); | |
2492 | input in0; | |
2493 | input in1; | |
2494 | input in2; | |
2495 | output out; | |
2496 | ||
2497 | `ifdef LIB | |
2498 | assign out = in0 ^ in1 ^ in2; | |
2499 | `endif | |
2500 | ||
2501 | ||
2502 | endmodule |