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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_clk_clstr_hdr_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `timescale 1 ns/1 ns | |
36 | ||
37 | module n2_clk_clstr_hdr_cust ( | |
38 | gclk, | |
39 | l2clk, | |
40 | cluster_arst_l, | |
41 | ccu_div_ph, | |
42 | cluster_div_en, | |
43 | tcu_div_bypass, | |
44 | scan_in, | |
45 | scan_en, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | ccu_cmp_slow_sync_en, | |
49 | ccu_slow_cmp_sync_en, | |
50 | tcu_pce_ov, | |
51 | tcu_clk_stop, | |
52 | rst_por_, | |
53 | rst_wmr_, | |
54 | rst_wmr_protect, | |
55 | tcu_wr_inhibit, | |
56 | tcu_atpg_mode, | |
57 | array_wr_inhibit, | |
58 | aclk_wmr, | |
59 | aclk, | |
60 | bclk, | |
61 | cmp_slow_sync_en, | |
62 | slow_cmp_sync_en, | |
63 | pce_ov, | |
64 | por_, | |
65 | wmr_, | |
66 | wmr_protect, | |
67 | scan_out, | |
68 | cclk | |
69 | ); | |
70 | ||
71 | // ******************************* | |
72 | // port declaration | |
73 | // ******************************* | |
74 | ||
75 | input gclk; | |
76 | input l2clk; | |
77 | input cluster_arst_l; | |
78 | input ccu_div_ph; | |
79 | input cluster_div_en; | |
80 | input tcu_div_bypass; | |
81 | input scan_in; | |
82 | input scan_en; | |
83 | input tcu_aclk; | |
84 | input tcu_bclk; | |
85 | input ccu_cmp_slow_sync_en; | |
86 | input ccu_slow_cmp_sync_en; | |
87 | input tcu_pce_ov; | |
88 | input tcu_clk_stop; | |
89 | input rst_por_; | |
90 | input rst_wmr_; | |
91 | input rst_wmr_protect; | |
92 | input tcu_wr_inhibit; | |
93 | input tcu_atpg_mode; | |
94 | output array_wr_inhibit; | |
95 | output aclk_wmr; | |
96 | output aclk; | |
97 | output bclk; | |
98 | output cmp_slow_sync_en; | |
99 | output slow_cmp_sync_en; | |
100 | output pce_ov; | |
101 | output por_; | |
102 | output wmr_; | |
103 | output wmr_protect; | |
104 | output scan_out; | |
105 | output cclk; | |
106 | ||
107 | ||
108 | // ******************************* | |
109 | // wire declaration | |
110 | // ******************************* | |
111 | ||
112 | wire gclk; | |
113 | wire l2clk; | |
114 | wire cluster_arst_l; | |
115 | wire ccu_div_ph; | |
116 | wire cluster_div_en; | |
117 | wire tcu_div_bypass; | |
118 | wire scan_in; | |
119 | wire scan_en; | |
120 | wire tcu_aclk; | |
121 | wire tcu_bclk; | |
122 | wire ccu_cmp_slow_sync_en; | |
123 | wire ccu_slow_cmp_sync_en; | |
124 | wire tcu_pce_ov; | |
125 | wire tcu_clk_stop; | |
126 | wire rst_por_; | |
127 | wire rst_wmr_; | |
128 | wire rst_wmr_protect; | |
129 | wire tcu_wr_inhibit; // to be made input | |
130 | wire tcu_atpg_mode; // to be made input | |
131 | wire array_wr_inhibit; // to be made output | |
132 | wire aclk_wmr; | |
133 | wire aclk; | |
134 | wire bclk; | |
135 | wire cmp_slow_sync_en; | |
136 | wire slow_cmp_sync_en; | |
137 | wire pce_ov; | |
138 | wire por_; | |
139 | wire wmr_; | |
140 | wire wmr_protect; | |
141 | wire scan_out; | |
142 | wire cclk; | |
143 | ||
144 | ||
145 | // additional internal nets | |
146 | wire div_r; | |
147 | // wire div_f; // vlint | |
148 | ||
149 | wire cluster_div_en_n; | |
150 | wire tcu_div_bypass_n; | |
151 | ||
152 | ||
153 | wire sel0; | |
154 | wire sel1; | |
155 | // wire sel2; // vlint | |
156 | ||
157 | wire div_out; | |
158 | // wire div_r_n; // vlint | |
159 | // wire div_f_n; // vlint | |
160 | ||
161 | // wire gclk_n; // vlint | |
162 | wire array_wr_inhibit_n; | |
163 | ||
164 | ||
165 | wire cclk_n; | |
166 | wire pre_cclk; | |
167 | wire div_clk; | |
168 | ||
169 | wire l1clk; | |
170 | wire l1gclk; | |
171 | ||
172 | wire aclk_gated; | |
173 | wire bclk_gated; | |
174 | wire scan_en_gated; | |
175 | wire scan_out_pre_mux; | |
176 | ||
177 | wire aclk_gated_n; | |
178 | wire bclk_gated_n; | |
179 | wire scan_en_gated_n; | |
180 | wire tcu_atpg_mode_n; | |
181 | ||
182 | wire scan_ch; | |
183 | ||
184 | // wire clk_stop_muxed; // vlint | |
185 | // wire clk_stop_q; // vlint | |
186 | wire clk_stop_synced; | |
187 | ||
188 | wire rst_wmr_protect_n; | |
189 | wire aclk_wmr_n; | |
190 | wire div_r_sync; | |
191 | wire sel0_n; | |
192 | wire sel1_n; | |
193 | wire div_ph_blatch; | |
194 | wire div_r_sync_n; | |
195 | wire div_mux; | |
196 | ||
197 | // ********************************************************** | |
198 | // buffered & gated stuff | |
199 | // ********************************************************** | |
200 | ||
201 | cl_u1_buf_1x aclk_buf ( .in( tcu_aclk ), .out ( aclk ) ); | |
202 | cl_u1_buf_1x bclk_buf ( .in( tcu_bclk ), .out ( bclk ) ); | |
203 | cl_u1_buf_1x pce_ov_buf ( .in( tcu_pce_ov ), .out ( pce_ov ) ); | |
204 | cl_u1_buf_1x wmr_protect_buf ( .in( rst_wmr_protect ), .out ( wmr_protect ) ); | |
205 | ||
206 | // assign aclk_gated = aclk & tcu_atpg_mode; | |
207 | // assign bclk_gated = bclk & tcu_atpg_mode; | |
208 | // assign scan_en_gated = scan_en & tcu_atpg_mode; | |
209 | // implemented right here | |
210 | cl_u1_nand2_1x aclk_gated_nand ( .in0 (aclk), .in1 (tcu_atpg_mode), .out (aclk_gated_n) ); | |
211 | cl_u1_nand2_1x bclk_gated_nand ( .in0 (bclk), .in1 (tcu_atpg_mode), .out (bclk_gated_n) ); | |
212 | cl_u1_nand2_1x scan_en_gated_nand ( .in0 (scan_en), .in1 (tcu_atpg_mode), .out (scan_en_gated_n) ); | |
213 | cl_u1_inv_1x aclk_gated_inv ( .in (aclk_gated_n), .out (aclk_gated) ); | |
214 | cl_u1_inv_1x bclk_gated_inv ( .in (bclk_gated_n), .out (bclk_gated) ); | |
215 | cl_u1_inv_1x scan_en_gated_inv ( .in (scan_en_gated_n), .out (scan_en_gated) ); | |
216 | ||
217 | // assign scan_out = tcu_atpg_mode ? scan_out_pre_mux : scan_in ; | |
218 | // implemented below, and as instance "scan_chain_mux" | |
219 | cl_u1_inv_1x tcu_atpg_mode_inv ( .in (tcu_atpg_mode) , .out (tcu_atpg_mode_n) ); | |
220 | ||
221 | ||
222 | // assign aclk_wmr = ~rst_wmr_protect & tcu_aclk; | |
223 | ||
224 | ||
225 | cl_u1_inv_1x wmr_protect_inv ( .in (rst_wmr_protect) , .out (rst_wmr_protect_n) ); | |
226 | ||
227 | cl_u1_nand2_1x aclk_wmr_gate ( | |
228 | .in0 (aclk), | |
229 | .in1 (rst_wmr_protect_n), | |
230 | .out (aclk_wmr_n) | |
231 | ); | |
232 | ||
233 | cl_u1_inv_1x aclk_wmr_inv ( .in (aclk_wmr_n) , .out (aclk_wmr) ); | |
234 | ||
235 | // cl_u1_inv_1x gclk_inv ( .in (gclk) , .out (gclk_n) ); // vlint | |
236 | ||
237 | // ********************************************************** | |
238 | // l1hdr for scan | |
239 | // ********************************************************** | |
240 | ||
241 | n2_clk_clstr_hdr_l1hdr gclk_header ( | |
242 | .l2clk(gclk), | |
243 | .l1clk(l1gclk), | |
244 | .pce(1'b1), | |
245 | .se(scan_en_gated), | |
246 | .pce_ov(1'b1), | |
247 | .stop(1'b0) // ECO1.2 - not allowed to stop local clocks | |
248 | ); | |
249 | ||
250 | n2_clk_clstr_hdr_l1hdr l1_header ( | |
251 | .l2clk(l2clk), | |
252 | .l1clk(l1clk), | |
253 | .pce(1'b1), | |
254 | .se(scan_en_gated), | |
255 | .pce_ov(1'b1), | |
256 | .stop(1'b0) // ECO1.3 - false info; no action needed | |
257 | ); | |
258 | ||
259 | // ********************************************************** | |
260 | // make observe flops part of scan chain (observe only) | |
261 | // ********************************************************** | |
262 | ||
263 | n2_clk_clstr_hdr_obs_flops observe_flops ( | |
264 | .tcu_clk_stop (tcu_clk_stop), | |
265 | .ccu_div_ph (ccu_div_ph), | |
266 | .array_wr_inhibit (array_wr_inhibit), | |
267 | .l1clk (l1gclk), | |
268 | .aclk (aclk_gated), | |
269 | .bclk (bclk_gated), | |
270 | .scan_in (scan_in), | |
271 | .scan_out (scan_ch) | |
272 | ); | |
273 | ||
274 | cl_sc1_aomux2_1x scan_chain_mux ( | |
275 | .sel0 ( tcu_atpg_mode ), | |
276 | .sel1 ( tcu_atpg_mode_n ), | |
277 | .in0 ( scan_out_pre_mux ), | |
278 | .in1 ( scan_in ), | |
279 | .out ( scan_out ) | |
280 | ); | |
281 | ||
282 | ||
283 | // ********************************************************** | |
284 | // synchronize the control signals | |
285 | // ********************************************************** | |
286 | ||
287 | n2_clk_clstr_hdr_sync control_sig_sync ( | |
288 | .div_r ( div_r_sync ), | |
289 | .gclk ( l1gclk ), | |
290 | .l1clk ( l1clk ), | |
291 | .ccu_slow_cmp_sync_en ( ccu_slow_cmp_sync_en), | |
292 | .ccu_cmp_slow_sync_en ( ccu_cmp_slow_sync_en), | |
293 | .rst_por_ ( rst_por_), | |
294 | .rst_wmr_ ( rst_wmr_), | |
295 | .scan_in ( scan_ch ), | |
296 | .aclk ( aclk_gated ), | |
297 | .bclk ( bclk_gated ), | |
298 | .slow_cmp_sync_en ( slow_cmp_sync_en ), | |
299 | .cmp_slow_sync_en ( cmp_slow_sync_en ), | |
300 | .por_ ( por_ ), | |
301 | .wmr_ ( wmr_ ), | |
302 | .scan_out ( scan_out_pre_mux ) | |
303 | ); | |
304 | ||
305 | ||
306 | // ********************************************************** | |
307 | // divider & mux model | |
308 | // ********************************************************** | |
309 | ||
310 | wire ccu_div_ph_ff; | |
311 | wire ccu_div_ph_flop_unused; | |
312 | ||
313 | // first flop ccu_div_ph | |
314 | cl_sc1_msff_1x ccu_div_ph_flop ( | |
315 | .d ( ccu_div_ph ), | |
316 | .l1clk ( gclk ), | |
317 | .si ( 1'b0 ), | |
318 | .siclk ( 1'b0 ), | |
319 | .soclk ( 1'b0 ), | |
320 | .q ( ccu_div_ph_ff ), | |
321 | .so (ccu_div_ph_flop_unused) | |
322 | ); | |
323 | ||
324 | // div_r = sel1 (ie, ~div_en | tcu_div_bypass ) | div_ph | |
325 | // div_f = sel0 (ie, div_en & ~tcu_div_bypass ) | |
326 | // | |
327 | ||
328 | // sel0 = ~div_bypass & div_en // div_ph select | |
329 | // sel1 = div_bypass | ~div_en // gclk select | |
330 | ||
331 | cl_u1_inv_1x div_bypass_inv ( .in (tcu_div_bypass), .out (tcu_div_bypass_n) ); | |
332 | cl_u1_inv_1x cluster_div_inv ( .in (cluster_div_en), .out (cluster_div_en_n) ); | |
333 | ||
334 | // | |
335 | // generate sel0 - div_ph sel | |
336 | // | |
337 | ||
338 | cl_u1_nand2_1x sel0_n_gen ( | |
339 | .in0 (tcu_div_bypass_n), | |
340 | .in1 (cluster_div_en), | |
341 | .out (sel0_n) | |
342 | ); | |
343 | ||
344 | cl_u1_inv_1x sel0_gen ( .in (sel0_n), .out (sel0) ); | |
345 | ||
346 | ||
347 | // | |
348 | // generate sel1 - gclk sel | |
349 | // | |
350 | ||
351 | cl_u1_nor2_1x sel2_n_gen ( | |
352 | .in0 (cluster_div_en_n), | |
353 | .in1 (tcu_div_bypass), | |
354 | .out (sel1_n) | |
355 | ); | |
356 | ||
357 | cl_u1_inv_1x sel1_gen ( .in (sel1_n), .out (sel1) ); | |
358 | ||
359 | ||
360 | // gate off div_r | |
361 | //cl_u1_nor2_1x div_r_gate ( | |
362 | // .in0 (sel1), | |
363 | // .in1 (div_ph_blatch), | |
364 | // .out (div_r_n) | |
365 | //); | |
366 | wire blatch_divr_unused; | |
367 | cl_sc1_blatch_4x blatch_divr ( | |
368 | .latout(div_ph_blatch), .d(ccu_div_ph_ff), .l1clk (gclk), | |
369 | .so (blatch_divr_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
370 | ||
371 | //cl_u1_nor2_1x div_r_gate ( | |
372 | // .in0 (sel1), | |
373 | // .in1 (div_ph_blatch), | |
374 | // .out (div_r_n) | |
375 | //); | |
376 | ||
377 | cl_u1_buf_1x div_r_buf ( .in (div_ph_blatch), .out (div_r ) ); | |
378 | ||
379 | ||
380 | // | |
381 | // divider model | |
382 | // | |
383 | ||
384 | // creating the div_r_to_syncronizer to mimic generation of | |
385 | //div_r in schematic. | |
386 | ||
387 | cl_u1_nor2_1x div_r_sync_gen_nor ( | |
388 | .in0 (sel0_n), | |
389 | .in1 (ccu_div_ph_ff), | |
390 | .out (div_r_sync_n) | |
391 | ); | |
392 | ||
393 | cl_u1_inv_1x div_r_sync_gen_inv ( .in (div_r_sync_n), .out (div_r_sync) ); | |
394 | ||
395 | cl_sc1_aomux2_1x alatch_in ( | |
396 | .sel0 (~sel1 ), | |
397 | .sel1 ( sel1 ), | |
398 | .in0 ( div_r ), | |
399 | .in1 ( div_clk ), | |
400 | .out ( div_mux ) | |
401 | ); | |
402 | ||
403 | wire gclk_reset; | |
404 | wire gclk_reset_n; | |
405 | cl_u1_nor2_1x nor_gclk_reset ( .in0 (sel1), .in1 (gclk), .out (gclk_reset_n)); | |
406 | cl_u1_inv_1x inv_gclk_reset ( .in (gclk_reset_n), .out (gclk_reset)); | |
407 | ||
408 | ||
409 | wire alatch_unused; | |
410 | cl_sc1_alatch_4x alatch ( | |
411 | .q(div_out), .d(div_mux), .l1clk (gclk_reset), | |
412 | .so (alatch_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0), .se(1'b0) ); | |
413 | ||
414 | // muxed clock out | |
415 | cl_sc1_aomux2_1x final_mux ( | |
416 | .sel0 ( sel0 ), | |
417 | .sel1 ( sel1 ), | |
418 | .in0 ( div_out ), | |
419 | .in1 ( gclk ), | |
420 | .out ( div_clk ) | |
421 | ); | |
422 | ||
423 | // ********************************************************** | |
424 | // clkstop for l2clk (via control of cclk) | |
425 | // ********************************************************** | |
426 | ||
427 | // 1. sync up clock stop (these are non-scanned) | |
428 | n2_clk_clstr_hdr_clk_stop_syncff clk_stop_syncff ( | |
429 | .din ( tcu_clk_stop ), | |
430 | .synced ( clk_stop_synced ), | |
431 | .clkin ( gclk ), | |
432 | .sync_clk ( div_clk ), | |
433 | .sel ( div_r_sync ) | |
434 | ||
435 | ); | |
436 | ||
437 | wire clk_stop_synced_stg1; | |
438 | wire clk_stop_synced_stg2; | |
439 | wire clk_stop_del_stg1_unused; | |
440 | wire clk_stop_del_stg2_unused; | |
441 | // 2. now delay sync'd up clock stop (these are non-scanned) | |
442 | cl_sc1_msff_1x clk_stop_del_stg1 ( | |
443 | .d (clk_stop_synced), .q (clk_stop_synced_stg1), .l1clk (div_clk), | |
444 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg1_unused) | |
445 | ); | |
446 | ||
447 | cl_sc1_msff_1x clk_stop_del_stg2 ( | |
448 | .d (clk_stop_synced_stg1), .q (clk_stop_synced_stg2), .l1clk (div_clk), | |
449 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg2_unused) | |
450 | ); | |
451 | ||
452 | wire clk_stop_synced_stg2_gated; | |
453 | wire clk_stop_synced_stg2_n; | |
454 | ||
455 | cl_u1_inv_1x clk_stop_stg2_inv ( .in (clk_stop_synced_stg2), .out (clk_stop_synced_stg2_n) ); | |
456 | ||
457 | // ECO1.5 - pushed the gate after the latch in the clk-stop instance "clk_stopper" | |
458 | // cl_u1_nor2_1x clk_stop_stg2_nor ( .in0 (clk_stop_synced_stg2_n), .in1 (tcu_atpg_mode), .out (clk_stop_synced_stg2_gated) ); | |
459 | // | |
460 | // 3. use blatch & and-gate for controlling clock | |
461 | n2_clk_clstr_hdr_clkgate clk_stopper ( | |
462 | .l2clk(div_clk), | |
463 | .l1clk(pre_cclk), | |
464 | .atpg_mode(tcu_atpg_mode), | |
465 | .clken(clk_stop_synced_stg2_n) | |
466 | ); | |
467 | ||
468 | // 4. finally gate-off with async reset | |
469 | // assign cclk = pre_cclk & cluster_arst_l; | |
470 | ||
471 | cl_u1_nand2_1x cclk_nand ( .in0 (pre_cclk), .in1 (cluster_arst_l), .out (cclk_n) ); | |
472 | cl_u1_inv_1x cclk_inv ( .in (cclk_n), .out (cclk) ); | |
473 | ||
474 | ||
475 | // ********************************************************** | |
476 | // array write inhibit operation | |
477 | // ********************************************************** | |
478 | ||
479 | wire clk_stop_synced_n; | |
480 | ||
481 | wire clk_stop_synced_stg3; | |
482 | wire clk_stop_synced_stg4; | |
483 | wire clk_stop_synced_stg5; | |
484 | ||
485 | wire array_wr_inhibit1; | |
486 | wire array_wr_inhibit2; | |
487 | ||
488 | wire array_wr_inhibit1_n; | |
489 | wire array_wr_inhibit2_n; | |
490 | wire cluster_arst; | |
491 | wire clk_stop_del_stg3_unused; | |
492 | wire clk_stop_del_stg4_unused; | |
493 | wire clk_stop_del_stg5_unused; | |
494 | ||
495 | cl_sc1_msff_1x clk_stop_del_stg3 ( | |
496 | .d (clk_stop_synced_stg2), .q (clk_stop_synced_stg3), .l1clk (div_clk), | |
497 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg3_unused) | |
498 | ); | |
499 | ||
500 | cl_sc1_msff_1x clk_stop_del_stg4 ( | |
501 | .d (clk_stop_synced_stg3), .q (clk_stop_synced_stg4), .l1clk (div_clk), | |
502 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg4_unused) | |
503 | ); | |
504 | ||
505 | cl_sc1_msff_1x clk_stop_del_stg5 ( | |
506 | .d (clk_stop_synced_stg4), .q (clk_stop_synced_stg5), .l1clk (div_clk), | |
507 | .siclk (1'b0), .soclk (1'b0), .si (1'b0), .so (clk_stop_del_stg5_unused) | |
508 | ); | |
509 | ||
510 | ||
511 | // assign array_wr_inhibit1 = clk_stop_synced & clk_stop_synced_stg5; | |
512 | ||
513 | cl_u1_nand3_1x clk_stop_and_delayed ( // ECO1.4 - changed cl_u1_nand2_1x | |
514 | .in0 (clk_stop_synced), | |
515 | .in1 (clk_stop_synced_stg5), | |
516 | .in2 (tcu_atpg_mode_n), | |
517 | .out (array_wr_inhibit1_n) | |
518 | ); | |
519 | ||
520 | cl_u1_inv_1x array_wr_inhibit1_inv ( .in(array_wr_inhibit1_n), .out(array_wr_inhibit1) ); | |
521 | ||
522 | ||
523 | // assign array_wr_inhibit2 = (~clk_stop_synced) & wr_inhibit_q2; | |
524 | cl_u1_inv_1x clk_stop_synced_inv ( .in(clk_stop_synced), .out(clk_stop_synced_n) ); | |
525 | ||
526 | // ECO1.1 - removed nand gate from path of tcu_wr_inhibit | |
527 | // and replaced with buffer | |
528 | // | |
529 | // cl_u1_nand2_1x clk_stop_synced_and_wr_inhibit_q2 ( | |
530 | // .in0 (clk_stop_synced_n), | |
531 | // .in1 (tcu_wr_inhibit), // (wr_inhibit_q2), | |
532 | // .out (array_wr_inhibit2_n) | |
533 | // ); | |
534 | // | |
535 | // cl_u1_inv_1x array_wr_inhibit2_inv ( .in(array_wr_inhibit2_n), .out(array_wr_inhibit2) ); | |
536 | cl_u1_buf_1x array_wr_inhibit2_buf ( .in(tcu_wr_inhibit), .out(array_wr_inhibit2) ); | |
537 | ||
538 | ||
539 | // assign array_wr_inhibit = array_wr_inhibit1 | array_wr_inhibit2 | (~cluster_arst_l); | |
540 | ||
541 | cl_u1_inv_1x cluster_arst_inv (.in (cluster_arst_l), .out (cluster_arst)); | |
542 | ||
543 | cl_u1_nor3_1x array_wr_inhibit_nor ( | |
544 | .in0 (array_wr_inhibit1), | |
545 | .in1 (array_wr_inhibit2), | |
546 | .in2 (cluster_arst), | |
547 | .out (array_wr_inhibit_n) | |
548 | ); | |
549 | ||
550 | cl_u1_inv_1x array_wr_inhibit_inv (.in (array_wr_inhibit_n), .out (array_wr_inhibit)); | |
551 | ||
552 | endmodule // n2_clk_clstr_hdr_cust | |
553 | ||
554 | ||
555 | ||
556 | ||
557 | // ********************************************************** | |
558 | // (fictitous) observe flop module for ATPG purposes | |
559 | // ********************************************************** | |
560 | ||
561 | module n2_clk_clstr_hdr_obs_flops ( | |
562 | tcu_clk_stop, | |
563 | ccu_div_ph, | |
564 | array_wr_inhibit, | |
565 | l1clk, | |
566 | aclk, | |
567 | bclk, | |
568 | scan_in, | |
569 | scan_out | |
570 | ); | |
571 | ||
572 | input tcu_clk_stop; | |
573 | input ccu_div_ph; | |
574 | input array_wr_inhibit; | |
575 | input l1clk; | |
576 | input aclk; | |
577 | input bclk; | |
578 | input scan_in; | |
579 | output scan_out; | |
580 | ||
581 | wire tcu_clk_stop; | |
582 | wire ccu_div_ph; | |
583 | wire array_wr_inhibit; | |
584 | wire l1clk; | |
585 | wire aclk; | |
586 | wire bclk; | |
587 | wire scan_in; | |
588 | wire scan_out; | |
589 | ||
590 | wire scan_ch1; | |
591 | wire scan_ch2; | |
592 | wire obs_ff1_unused; | |
593 | wire obs_ff2_unused; | |
594 | wire obs_ff3_unused; | |
595 | ||
596 | cl_sc1_msff_1x obs_ff1 ( | |
597 | .d ( tcu_clk_stop ), | |
598 | .l1clk ( l1clk ), | |
599 | .si ( scan_in ), | |
600 | .siclk ( aclk ), | |
601 | .soclk ( bclk ), | |
602 | .q (obs_ff1_unused ), | |
603 | .so ( scan_ch1 ) | |
604 | ); | |
605 | ||
606 | cl_sc1_msff_1x obs_ff2 ( | |
607 | .d ( ccu_div_ph ), | |
608 | .l1clk ( l1clk ), | |
609 | .si ( scan_ch1 ), | |
610 | .siclk ( aclk ), | |
611 | .soclk ( bclk ), | |
612 | .q (obs_ff2_unused ), | |
613 | .so ( scan_ch2 ) | |
614 | ); | |
615 | ||
616 | cl_sc1_msff_1x obs_ff3 ( | |
617 | .d ( array_wr_inhibit ), | |
618 | .l1clk ( l1clk ), | |
619 | .si ( scan_ch2 ), | |
620 | .siclk ( aclk ), | |
621 | .soclk ( bclk ), | |
622 | .q (obs_ff3_unused ), | |
623 | .so ( scan_out ) | |
624 | ); | |
625 | endmodule // n2_clk_clstr_hdr_obs_flops | |
626 | ||
627 | ||
628 | // ********************************************************** | |
629 | // (fictitous) synchronizer module for ATPG purposes | |
630 | // ********************************************************** | |
631 | ||
632 | module n2_clk_clstr_hdr_sync ( | |
633 | div_r, | |
634 | gclk, | |
635 | l1clk, | |
636 | ccu_slow_cmp_sync_en , | |
637 | ccu_cmp_slow_sync_en , | |
638 | rst_por_ , | |
639 | rst_wmr_ , | |
640 | scan_in, | |
641 | aclk, | |
642 | bclk, | |
643 | slow_cmp_sync_en, | |
644 | cmp_slow_sync_en, | |
645 | por_, | |
646 | wmr_, | |
647 | scan_out | |
648 | ); | |
649 | ||
650 | ||
651 | input div_r; | |
652 | input gclk; | |
653 | input l1clk; | |
654 | input ccu_slow_cmp_sync_en ; | |
655 | input ccu_cmp_slow_sync_en ; | |
656 | input rst_por_ ; | |
657 | input rst_wmr_ ; | |
658 | input scan_in; | |
659 | input aclk; | |
660 | input bclk; | |
661 | ||
662 | output slow_cmp_sync_en; | |
663 | output cmp_slow_sync_en; | |
664 | output por_; | |
665 | output wmr_; | |
666 | output scan_out; | |
667 | ||
668 | wire div_r; | |
669 | // wire div_r_n; // vlint | |
670 | wire gclk; | |
671 | // wire gclk_n; // vlint | |
672 | wire l1clk; | |
673 | ||
674 | wire ccu_slow_cmp_sync_en ; | |
675 | wire slow_cmp_sync_en; | |
676 | wire ccu_cmp_slow_sync_en ; | |
677 | wire cmp_slow_sync_en; | |
678 | wire rst_por_ ; | |
679 | wire por_; | |
680 | ||
681 | wire rst_wmr_ ; | |
682 | wire wmr_; | |
683 | ||
684 | wire scan_in; | |
685 | wire scan_out; | |
686 | wire aclk; | |
687 | wire bclk; | |
688 | ||
689 | wire scan_ch1; | |
690 | wire scan_ch2; | |
691 | wire scan_ch3; | |
692 | ||
693 | ||
694 | // slow_cmp_sync_en | |
695 | n2_clk_clstr_hdr_sync_ff slow_cmp_sync_en_syncff ( | |
696 | .din ( ccu_slow_cmp_sync_en ), | |
697 | .synced ( slow_cmp_sync_en ), | |
698 | .clkin ( gclk ), | |
699 | .sync_clk ( l1clk ), | |
700 | .sel ( div_r ), | |
701 | .siclk ( aclk ), | |
702 | .soclk ( bclk ), | |
703 | .si ( scan_in ), | |
704 | .so ( scan_ch1 ) | |
705 | ); | |
706 | ||
707 | // cmp_slow_sync_en | |
708 | n2_clk_clstr_hdr_sync_ff cmp_slow_sync_en_syncff ( | |
709 | .din ( ccu_cmp_slow_sync_en ), | |
710 | .synced ( cmp_slow_sync_en ), | |
711 | .clkin ( gclk ), | |
712 | .sync_clk ( l1clk ), | |
713 | .sel ( div_r ), | |
714 | .siclk ( aclk ), | |
715 | .soclk ( bclk ), | |
716 | .si ( scan_ch1 ), | |
717 | .so ( scan_ch2 ) | |
718 | ); | |
719 | ||
720 | // por_ | |
721 | n2_clk_clstr_hdr_sync_ff por_syncff ( | |
722 | .din ( rst_por_ ), | |
723 | .synced ( por_ ), | |
724 | .clkin ( gclk ), | |
725 | .sync_clk ( l1clk ), | |
726 | .sel ( div_r ), | |
727 | .siclk ( aclk ), | |
728 | .soclk ( bclk ), | |
729 | .si ( scan_ch2 ), | |
730 | .so ( scan_ch3 ) | |
731 | ); | |
732 | ||
733 | // wmr_ | |
734 | n2_clk_clstr_hdr_sync_ff wmr_syncff ( | |
735 | .din ( rst_wmr_ ), | |
736 | .synced ( wmr_ ), | |
737 | .clkin ( gclk ), | |
738 | .sync_clk ( l1clk ), | |
739 | .sel ( div_r ), | |
740 | .siclk ( aclk ), | |
741 | .soclk ( bclk ), | |
742 | .si ( scan_ch3 ), | |
743 | .so ( scan_out ) | |
744 | ); | |
745 | ||
746 | endmodule // n2_clk_clstr_hdr_sync | |
747 | ||
748 | ||
749 | // ********************************************************** | |
750 | // (fictitous) 1-bit synchronizer for ATPG purposes | |
751 | // ********************************************************** | |
752 | ||
753 | module n2_clk_clstr_hdr_sync_ff ( | |
754 | din, | |
755 | synced, | |
756 | clkin, | |
757 | sync_clk, | |
758 | sel, | |
759 | siclk, | |
760 | soclk, | |
761 | si, | |
762 | so | |
763 | ); | |
764 | ||
765 | input din; | |
766 | output synced; | |
767 | input clkin; | |
768 | input sync_clk; | |
769 | input siclk; | |
770 | input soclk; | |
771 | input si; | |
772 | output so; | |
773 | input sel; | |
774 | ||
775 | wire din; | |
776 | wire synced; | |
777 | wire clkin; | |
778 | wire sync_clk; | |
779 | wire siclk; | |
780 | wire soclk; | |
781 | wire si; | |
782 | wire so; | |
783 | wire sel; | |
784 | ||
785 | wire so_tmp; | |
786 | wire sel_n; | |
787 | wire din_q1; | |
788 | wire din_muxed; | |
789 | ||
790 | cl_u1_inv_1x sel_inv ( .in ( sel ), .out ( sel_n ) ); | |
791 | ||
792 | cl_sc1_aomux2_1x sync_mux1 ( | |
793 | .sel0 ( sel_n ), | |
794 | .sel1 ( sel ), | |
795 | .in0 ( din_q1 ), | |
796 | .in1 ( din ), | |
797 | .out ( din_muxed ) | |
798 | ); | |
799 | ||
800 | cl_sc1_msff_1x din_stg1 ( | |
801 | .d ( din_muxed ), | |
802 | .l1clk ( clkin ), | |
803 | .si ( si ), | |
804 | .siclk ( siclk ), | |
805 | .soclk ( soclk ), | |
806 | .q ( din_q1 ), | |
807 | .so ( so_tmp ) | |
808 | ); | |
809 | ||
810 | cl_sc1_msff_1x din_stg2 ( | |
811 | .d ( din_q1 ), | |
812 | .l1clk ( sync_clk ), | |
813 | .si ( so_tmp ), | |
814 | .siclk ( siclk ), | |
815 | .soclk ( soclk ), | |
816 | .q ( synced ), | |
817 | .so ( so ) | |
818 | ); | |
819 | endmodule // n2_clk_clstr_hdr_sync_ff | |
820 | ||
821 | ||
822 | // ********************************************************** | |
823 | // (fictitous) module for clock stop sync. | |
824 | // ********************************************************** | |
825 | module n2_clk_clstr_hdr_clk_stop_syncff ( | |
826 | din, | |
827 | synced, | |
828 | clkin, | |
829 | sync_clk, | |
830 | sel | |
831 | ); | |
832 | ||
833 | input din; | |
834 | output synced; | |
835 | input clkin; | |
836 | input sync_clk; | |
837 | input sel; | |
838 | ||
839 | wire din; | |
840 | wire synced; | |
841 | wire clkin; | |
842 | wire sync_clk; | |
843 | wire sel; | |
844 | ||
845 | wire [2:0] so_unused; | |
846 | ||
847 | wire sel_n; | |
848 | wire din_q1_lat; | |
849 | wire din_q1; | |
850 | wire din_muxed; | |
851 | ||
852 | cl_u1_inv_1x sel_inv ( .in(sel), .out(sel_n) ); | |
853 | ||
854 | cl_sc1_aomux2_1x sync_mux1 ( | |
855 | .sel0 ( sel_n ), .sel1 ( sel ), | |
856 | .in0 ( din_q1 ), .in1 ( din ), | |
857 | .out ( din_muxed ) | |
858 | ); | |
859 | ||
860 | cl_sc1_msff_1x din_stg1 ( | |
861 | .d ( din_muxed ), .l1clk ( clkin ), .q ( din_q1 ), | |
862 | .si ( 1'b0 ), .siclk ( 1'b0 ), .soclk ( 1'b0 ), | |
863 | .so (so_unused[0])); | |
864 | ||
865 | cl_sc1_blatch_4x blatch ( | |
866 | .latout(din_q1_lat), .d(din_q1), .l1clk (clkin), | |
867 | .so (so_unused[1]), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
868 | ||
869 | cl_sc1_msff_1x din_stg2 ( | |
870 | .d ( din_q1_lat ), .l1clk ( sync_clk ), .q ( synced ), | |
871 | .siclk ( 1'b0 ), .soclk ( 1'b0 ), .si ( 1'b0 ), .so (so_unused[2] ) ); | |
872 | ||
873 | endmodule // n2_clk_clstr_hdr_clk_stop_sync_ff | |
874 | ||
875 | ||
876 | ||
877 | module n2_clk_clstr_hdr_clkgate ( | |
878 | atpg_mode, | |
879 | clken, | |
880 | l2clk, | |
881 | l1clk | |
882 | ); | |
883 | ||
884 | input atpg_mode; | |
885 | input clken; // clken, active high | |
886 | input l2clk; // level 2 clock, from clock grid | |
887 | output l1clk; | |
888 | ||
889 | wire atpg_mode, clken, l2clk, l1clk; | |
890 | ||
891 | wire clken_gated; | |
892 | wire clken_gated_n; | |
893 | wire l1clk_n; | |
894 | wire clken_lat; | |
895 | wire so_unused; | |
896 | ||
897 | cl_sc1_blatch_4x blatch ( | |
898 | .latout(clken_lat), .d(clken), .l1clk (l2clk), | |
899 | .so (so_unused), .si (1'b0), .siclk(1'b0), .soclk(1'b0) ); | |
900 | ||
901 | cl_u1_nor2_1x clken_nor ( .in0(clken_lat), .in1(atpg_mode), .out(clken_gated_n) ); | |
902 | cl_u1_inv_1x clken_gated_inv ( .in(clken_gated_n), .out(clken_gated) ); | |
903 | ||
904 | cl_u1_nand2_1x clk_nand ( .in0(clken_gated), .in1(l2clk), .out(l1clk_n) ); | |
905 | cl_u1_inv_1x clk_inv ( .in(l1clk_n), .out(l1clk) ); | |
906 | ||
907 | endmodule // n2_clk_clstr_hdr_clkgate | |
908 | ||
909 | module n2_clk_clstr_hdr_l1hdr ( | |
910 | l2clk, | |
911 | se, | |
912 | pce, | |
913 | pce_ov, | |
914 | stop, | |
915 | l1clk | |
916 | ); | |
917 | ||
918 | input l2clk; // level 2 clock, from clock grid | |
919 | input se; // Scan Enable | |
920 | input pce; // Clock enable for local power savings | |
921 | input pce_ov; // TCU sourced clock enable override for testing | |
922 | input stop; // TCU/CCU sourced clock stop for debug | |
923 | output l1clk; | |
924 | ||
925 | reg l1en; | |
926 | ||
927 | always @ (l2clk or stop or pce or pce_ov ) begin // vlint fix - latch model | |
928 | if (!l2clk) | |
929 | l1en = (~stop & ( pce | pce_ov )); // vlint fix - replaced w/blocking | |
930 | end | |
931 | ||
932 | assign l1clk = (l2clk & l1en) | se; // se is async and highest priority | |
933 | ||
934 | endmodule // n2_clk_clstr_hdr_l1hdr | |
935 | ||
936 |