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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: clkgen_peu_pc.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module clkgen_peu_pc ( | |
36 | l2clk, | |
37 | aclk, | |
38 | bclk, | |
39 | scan_out, | |
40 | pce_ov, | |
41 | aclk_wmr, | |
42 | wmr_protect, | |
43 | wmr_, | |
44 | por_, | |
45 | // cmp_slow_sync_en, | |
46 | // slow_cmp_sync_en, | |
47 | tcu_clk_stop, | |
48 | tcu_pce_ov, | |
49 | rst_wmr_protect, | |
50 | rst_wmr_, | |
51 | rst_por_, | |
52 | // ccu_cmp_slow_sync_en, | |
53 | // ccu_slow_cmp_sync_en, | |
54 | // tcu_div_bypass, | |
55 | array_wr_inhibit, | |
56 | tcu_wr_inhibit, | |
57 | tcu_atpg_mode, | |
58 | test_clk_sel, | |
59 | test_clk, | |
60 | pc_clk_sel, | |
61 | pc_clk, | |
62 | ccu_div_ph, | |
63 | cluster_div_en, | |
64 | gclk, | |
65 | cluster_arst_l, | |
66 | // clk_ext, | |
67 | // ccu_serdes_dtm, | |
68 | tcu_aclk, | |
69 | tcu_bclk, | |
70 | scan_en, | |
71 | scan_in | |
72 | ); | |
73 | ||
74 | ||
75 | // ************************** | |
76 | // port declaration | |
77 | // ************************** | |
78 | ||
79 | // clock & test out | |
80 | output l2clk; // assume we do not need aclk, bclk outputs | |
81 | output aclk; // buffered version of aclk | |
82 | output bclk; // buffered version of bclk | |
83 | output scan_out; // unused as of today - feb 10, 05 | |
84 | output aclk_wmr; | |
85 | ||
86 | // pipelined out | |
87 | output pce_ov; // pce override to l1 header | |
88 | output wmr_protect; // warm reset protect | |
89 | output wmr_; // warm reset (active low) | |
90 | output por_; // power-on-reset | |
91 | // output cmp_slow_sync_en; // cmp->slow clk sync pulse | |
92 | // output slow_cmp_sync_en; // slow->cmp clk sync pulse | |
93 | ||
94 | output array_wr_inhibit; | |
95 | input tcu_wr_inhibit; | |
96 | input tcu_atpg_mode; | |
97 | // ctrl in (for pipelining) | |
98 | input tcu_clk_stop; | |
99 | input tcu_pce_ov; | |
100 | input rst_wmr_protect; | |
101 | input rst_wmr_; | |
102 | input rst_por_; | |
103 | // input ccu_cmp_slow_sync_en; | |
104 | // input ccu_slow_cmp_sync_en; | |
105 | ||
106 | // ctrl in (for clock gen) | |
107 | // input tcu_div_bypass; // bypasses clk divider to mux in ext clk | |
108 | input ccu_div_ph; // phase signal from ccu (div/4 or div/2) | |
109 | input cluster_div_en; // if enabled, l2clk is divided down | |
110 | ||
111 | // clock & test in | |
112 | input gclk; // global clk - this is either cmp or dr | |
113 | input cluster_arst_l; | |
114 | // input ccu_serdes_dtm; | |
115 | // input clk_ext; // external clk muxed in for ioclk bypass | |
116 | input scan_en; // unused as of today - feb 10, 05 | |
117 | input scan_in; // unused as of today - feb 10, 05 | |
118 | input tcu_aclk; | |
119 | input tcu_bclk; | |
120 | ||
121 | input test_clk_sel; | |
122 | input test_clk; | |
123 | input pc_clk_sel; | |
124 | input pc_clk; | |
125 | ||
126 | // ************************** | |
127 | // wire declaration | |
128 | // ************************** | |
129 | wire l2clk; | |
130 | wire aclk; | |
131 | wire bclk; | |
132 | wire scan_out; | |
133 | wire aclk_wmr; | |
134 | wire pce_ov; | |
135 | wire wmr_protect; | |
136 | wire wmr_; | |
137 | wire por_; | |
138 | // wire cmp_slow_sync_en; | |
139 | // wire slow_cmp_sync_en; | |
140 | // wire io2x_sync_en; | |
141 | // wire dr_sync_en; | |
142 | wire tcu_clk_stop; | |
143 | wire tcu_pce_ov; | |
144 | wire rst_wmr_protect; | |
145 | wire rst_wmr_; | |
146 | wire rst_por_; | |
147 | // wire ccu_cmp_slow_sync_en; | |
148 | // wire ccu_slow_cmp_sync_en; | |
149 | // wire ccu_io2x_sync_en; | |
150 | // wire ccu_dr_sync_en; | |
151 | wire tcu_div_bypass; | |
152 | wire ccu_div_ph; | |
153 | wire cluster_div_en; | |
154 | wire gclk; | |
155 | wire cluster_arst_l; | |
156 | wire clk_ext; | |
157 | wire ccu_serdes_dtm; | |
158 | wire scan_en; | |
159 | wire scan_in; | |
160 | wire tcu_aclk; | |
161 | wire tcu_bclk; | |
162 | ||
163 | wire cclk; | |
164 | ||
165 | wire test_clk_sel; | |
166 | wire test_clk; | |
167 | wire pc_clk_sel; | |
168 | wire pc_clk; | |
169 | ||
170 | wire array_wr_inhibit; | |
171 | wire tcu_wr_inhibit; | |
172 | wire tcu_atpg_mode; | |
173 | ||
174 | // ************************** | |
175 | // instantiations | |
176 | // ************************** | |
177 | ||
178 | // needs a few edits to cluster header def - mahmud.hassan | |
179 | // modified custom cell name for avoiding | |
180 | // collision with sparc core and other clusters - mhassan | |
181 | n2_clk_clstr_hdr2_cust xcluster_header ( | |
182 | .gclk (gclk), | |
183 | .l2clk (l2clk), | |
184 | .cluster_arst_l (cluster_arst_l), | |
185 | .ccu_div_ph (ccu_div_ph), | |
186 | // .cluster_div_en (cluster_div_en), | |
187 | // .tcu_div_bypass (tcu_div_bypass), | |
188 | // .clk_ext (clk_ext), | |
189 | // .ccu_serdes_dtm (ccu_serdes_dtm), | |
190 | .test_clk_sel (test_clk_sel), | |
191 | .test_clk (test_clk), | |
192 | .pc_clk_sel (pc_clk_sel), | |
193 | .pc_clk (pc_clk), | |
194 | .scan_in (scan_in), | |
195 | .scan_en (scan_en), | |
196 | .tcu_aclk (tcu_aclk), | |
197 | .tcu_bclk (tcu_bclk), | |
198 | // .ccu_cmp_slow_sync_en (ccu_cmp_slow_sync_en), | |
199 | // .ccu_slow_cmp_sync_en (ccu_slow_cmp_sync_en), | |
200 | .tcu_pce_ov (tcu_pce_ov), | |
201 | .tcu_clk_stop (tcu_clk_stop), | |
202 | .rst_por_ (rst_por_), | |
203 | .rst_wmr_ (rst_wmr_), | |
204 | .rst_wmr_protect (rst_wmr_protect), | |
205 | .aclk_wmr (aclk_wmr), | |
206 | .aclk (aclk), | |
207 | .bclk (bclk), | |
208 | // .cmp_slow_sync_en (cmp_slow_sync_en), | |
209 | // .slow_cmp_sync_en (slow_cmp_sync_en), | |
210 | .pce_ov (pce_ov), | |
211 | .por_ (por_), | |
212 | .wmr_ (wmr_), | |
213 | .wmr_protect (wmr_protect), | |
214 | .scan_out (scan_out), | |
215 | .array_wr_inhibit (array_wr_inhibit), | |
216 | .tcu_wr_inhibit (tcu_wr_inhibit) , | |
217 | .tcu_atpg_mode (tcu_atpg_mode), | |
218 | .cclk (cclk) | |
219 | ); | |
220 | ||
221 | ||
222 | ||
223 | // cclk -> l2clk from right | |
224 | n2_clk_peu_pc_cust xright ( | |
225 | .l2clk (l2clk), | |
226 | .cclk (cclk) | |
227 | ); | |
228 | ||
229 | ||
230 | ||
231 | // cclk -> l2clk from left | |
232 | n2_clk_peu_pc_cust xleft ( | |
233 | .l2clk (l2clk), | |
234 | .cclk (cclk) | |
235 | ); | |
236 | ||
237 | endmodule | |
238 |