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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_clk_clhdr_sync.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_clk_clhdr_sync(se ,g_clk_stop ,g_pce_ov ,g_dbg_init , | |
36 | g_wmr_reset ,wmr_reset ,dbg_init ,so ,si ,siclk ,soclk ,gclk , | |
37 | pce_ov ,clk_stop ,l2clk ); | |
38 | output wmr_reset ; | |
39 | output dbg_init ; | |
40 | output so ; | |
41 | output pce_ov ; | |
42 | output clk_stop ; | |
43 | input se ; | |
44 | input g_clk_stop ; | |
45 | input g_pce_ov ; | |
46 | input g_dbg_init ; | |
47 | input g_wmr_reset ; | |
48 | input si ; | |
49 | input siclk ; | |
50 | input soclk ; | |
51 | input gclk ; | |
52 | input l2clk ; | |
53 | ||
54 | wire net70 ; | |
55 | wire scan_wmr ; | |
56 | wire scan_pceov ; | |
57 | wire scan_stop_l ; | |
58 | wire net91 ; | |
59 | wire scan_pceov_l ; | |
60 | wire scan_dbg ; | |
61 | wire net42 ; | |
62 | wire l1clk ; | |
63 | wire net56 ; | |
64 | wire scan_wmr_l ; | |
65 | wire scan_stop ; | |
66 | ||
67 | ||
68 | cl_sc1_l1hdr_8x x5 ( | |
69 | .se (se ), | |
70 | .l1clk (l1clk ), | |
71 | .l2clk (l2clk ), | |
72 | .stop (clk_stop ), | |
73 | .pce_ov (1'b1 ), | |
74 | .pce (1'b1 ) ); | |
75 | cl_dp1_msff_4x xstop_g ( | |
76 | .q (net42 ), | |
77 | .so (scan_stop ), | |
78 | .soclk (soclk ), | |
79 | .siclk (siclk ), | |
80 | .si (si ), | |
81 | .l1clk (gclk ), | |
82 | .d (g_clk_stop ) ); | |
83 | cl_dp1_msff_4x xstop_l ( | |
84 | .q (clk_stop ), | |
85 | .so (scan_stop_l ), | |
86 | .soclk (soclk ), | |
87 | .siclk (siclk ), | |
88 | .si (scan_stop ), | |
89 | .l1clk (l1clk ), | |
90 | .d (net42 ) ); | |
91 | cl_dp1_msff_4x xdbg_g ( | |
92 | .q (net70 ), | |
93 | .so (scan_dbg ), | |
94 | .soclk (soclk ), | |
95 | .siclk (siclk ), | |
96 | .si (scan_wmr_l ), | |
97 | .l1clk (gclk ), | |
98 | .d (g_dbg_init ) ); | |
99 | cl_dp1_msff_4x xdbg_l ( | |
100 | .q (dbg_init ), | |
101 | .so (so ), | |
102 | .soclk (soclk ), | |
103 | .siclk (siclk ), | |
104 | .si (scan_dbg ), | |
105 | .l1clk (l1clk ), | |
106 | .d (net70 ) ); | |
107 | cl_dp1_msff_4x xpceov_g ( | |
108 | .q (net91 ), | |
109 | .so (scan_pceov ), | |
110 | .soclk (soclk ), | |
111 | .siclk (siclk ), | |
112 | .si (scan_stop_l ), | |
113 | .l1clk (gclk ), | |
114 | .d (g_pce_ov ) ); | |
115 | cl_dp1_msff_4x xpceov_l ( | |
116 | .q (pce_ov ), | |
117 | .so (scan_pceov_l ), | |
118 | .soclk (soclk ), | |
119 | .siclk (siclk ), | |
120 | .si (scan_pceov ), | |
121 | .l1clk (l1clk ), | |
122 | .d (net91 ) ); | |
123 | cl_dp1_msff_4x xwmr_g ( | |
124 | .q (net56 ), | |
125 | .so (scan_wmr ), | |
126 | .soclk (soclk ), | |
127 | .siclk (siclk ), | |
128 | .si (scan_pceov_l ), | |
129 | .l1clk (gclk ), | |
130 | .d (g_wmr_reset ) ); | |
131 | cl_dp1_msff_4x xwmr_l ( | |
132 | .q (wmr_reset ), | |
133 | .so (scan_wmr_l ), | |
134 | .soclk (soclk ), | |
135 | .siclk (siclk ), | |
136 | .si (scan_wmr ), | |
137 | .l1clk (l1clk ), | |
138 | .d (net56 ) ); | |
139 | endmodule |