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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_com_64x132async_dp_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_com_64x132async_dp_cust ( | |
36 | // clocks, scan | |
37 | wr_clk, | |
38 | rd_clk, | |
39 | wr_pce, | |
40 | rd_pce, | |
41 | scan_in, | |
42 | tcu_se_scancollar_in, | |
43 | tcu_scan_en, | |
44 | tcu_pce_ov, | |
45 | tcu_aclk, | |
46 | tcu_bclk, | |
47 | tcu_array_wr_inhibit, | |
48 | bist_clk_mux_sel , | |
49 | bist_clk , | |
50 | scan_out, | |
51 | ||
52 | // ram control | |
53 | rd_addr, | |
54 | wr_addr, | |
55 | rd, | |
56 | wr_en, | |
57 | din, | |
58 | dout | |
59 | ||
60 | ); | |
61 | ||
62 | // clocks, scan | |
63 | input wr_clk; // write clock | |
64 | input rd_clk; // read clock | |
65 | input wr_pce ; // Write Clk Enable for pwr saving | |
66 | input rd_pce ; // Read Clk Enable for pwr saving | |
67 | input scan_in; // | |
68 | input tcu_se_scancollar_in; // scan enable to l1clk hdrs | |
69 | input tcu_scan_en; // scan enable to and_clk hdrs | |
70 | input tcu_pce_ov; // scan signals | |
71 | input tcu_aclk; // | |
72 | input tcu_bclk; // | |
73 | input tcu_array_wr_inhibit; // Array write/read inhibit during scan | |
74 | input bist_clk_mux_sel ; // Clk Hdr Mux Select for MBIST | |
75 | input bist_clk ; // BIST Clk, connect to pcl2clk | |
76 | output scan_out; // | |
77 | ||
78 | ||
79 | input [5:0] wr_addr; // wr port address in | |
80 | input wr_en; // wr port enable | |
81 | input [131:0] din; // data in | |
82 | ||
83 | input [5:0] rd_addr; // rd port address in | |
84 | input rd; // rd port enable | |
85 | output [131:0] dout; // rd port data out | |
86 | ||
87 | ||
88 | //------------------------------------------------------------------------ | |
89 | // scan chain connections | |
90 | //------------------------------------------------------------------------ | |
91 | wire [5:0] rd_addr_so ; | |
92 | wire [5:0] wr_addr_so ; | |
93 | wire rd_so ; | |
94 | wire wr_en_so ; | |
95 | wire [131:1] din_so ; | |
96 | ||
97 | //------------------------------------------------------------------------ | |
98 | // clock headers | |
99 | //------------------------------------------------------------------------ | |
100 | ||
101 | wire wr_l1clk ; | |
102 | wire siclk ; | |
103 | wire soclk ; | |
104 | wire rd_l1clk ; | |
105 | wire wr_array_l1clk ; // Free running write l1clk | |
106 | wire rd_and_l1clk ; | |
107 | ||
108 | wire rd_lce_0, rd_lce_1 ; | |
109 | wire wr_lce_0, wr_lce_1 ; | |
110 | ||
111 | assign siclk = tcu_aclk ; | |
112 | assign soclk = tcu_bclk ; | |
113 | ||
114 | ||
115 | cl_mc1_bistl1hdr_8x wr_collar_clk_hdr_mux ( | |
116 | .l2clk (wr_clk) , | |
117 | .se (tcu_se_scancollar_in) , | |
118 | .clksel (bist_clk_mux_sel) , | |
119 | .bistclk(bist_clk) , | |
120 | .lce (wr_lce_0), | |
121 | .l1clk (wr_l1clk) | |
122 | ); | |
123 | ||
124 | cl_mc1_bistlatch_4x wr_collar_clk_hdr_latch ( | |
125 | .l2clk (wr_clk) , | |
126 | .pce (wr_pce) , | |
127 | .pce_ov (tcu_pce_ov) , | |
128 | .lce (wr_lce_0) | |
129 | ); | |
130 | ||
131 | // L1 Hdr for Free Running Write L1 clk, which allows writing into the array | |
132 | // in low phase, when tcu_se_scancollar_in is high, which pulls the wr_l1clk | |
133 | // high. Similar to rd_and_l1clk, wr_array_l1clk is free running as long | |
134 | // as tcu_scan_en is not asserted. | |
135 | cl_mc1_bistl1hdr_8x wr_array_clk_hdr_mux ( | |
136 | .l2clk (wr_clk) , | |
137 | .se (tcu_scan_en) , | |
138 | .clksel (bist_clk_mux_sel) , | |
139 | .bistclk(bist_clk) , | |
140 | .lce (wr_lce_1), | |
141 | .l1clk (wr_array_l1clk) | |
142 | ); | |
143 | ||
144 | cl_mc1_bistlatch_4x wr_array_clk_hdr_latch ( | |
145 | .l2clk (wr_clk) , | |
146 | .pce (wr_pce) , | |
147 | .pce_ov (tcu_pce_ov) , | |
148 | .lce (wr_lce_1) | |
149 | ); | |
150 | ||
151 | ||
152 | cl_mc1_bistl1hdr_8x rd_collar_clk_hdr_mux ( | |
153 | .l2clk (rd_clk) , | |
154 | .se (tcu_se_scancollar_in) , | |
155 | .clksel (bist_clk_mux_sel) , | |
156 | .bistclk(bist_clk) , | |
157 | .lce (rd_lce_0), | |
158 | .l1clk (rd_l1clk) | |
159 | ); | |
160 | ||
161 | cl_mc1_bistlatch_4x rd_collar_clk_hdr_latch ( | |
162 | .l2clk (rd_clk) , | |
163 | .pce (rd_pce) , | |
164 | .pce_ov (tcu_pce_ov) , | |
165 | .lce (rd_lce_0) | |
166 | ); | |
167 | ||
168 | ||
169 | cl_mc1_bistl1hdr_8x rd_and_clk_hdr_mux ( | |
170 | .l2clk (rd_clk) , | |
171 | .se (tcu_scan_en) , | |
172 | .clksel (bist_clk_mux_sel) , | |
173 | .bistclk(bist_clk) , | |
174 | .lce (rd_lce_1), | |
175 | .l1clk (rd_and_l1clk) | |
176 | ); | |
177 | ||
178 | cl_mc1_bistlatch_4x rd_and_clk_hdr_latch ( | |
179 | .l2clk (rd_clk) , | |
180 | .pce (rd_pce) , | |
181 | .pce_ov (tcu_pce_ov) , | |
182 | .lce (rd_lce_1) | |
183 | ); | |
184 | ||
185 | ||
186 | //------------------------------------------------------------------------ | |
187 | // input flops | |
188 | //------------------------------------------------------------------------ | |
189 | wire [5:0] rd_addr_array ; | |
190 | wire [5:0] wr_addr_array ; | |
191 | wire rd_en_d1 ; | |
192 | wire wr_en_d1 ; | |
193 | wire rd_en_array ; | |
194 | wire wr_en_array ; | |
195 | wire [131:0] din_array ; | |
196 | ||
197 | cl_a1_msff_4x ff_din_131 ( .si(scan_in), .so(din_so[131]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[131]), .q(din_array[131]) ); | |
198 | cl_a1_msff_4x ff_din_130 ( .si(din_so[131]), .so(din_so[130]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[130]), .q(din_array[130]) ); | |
199 | ||
200 | cl_a1_msff_4x ff_din_129 ( .si(din_so[128]), .so(din_so[129]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[129]), .q(din_array[129]) ); | |
201 | cl_a1_msff_4x ff_din_128 ( .si(din_so[130]), .so(din_so[128]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[128]), .q(din_array[128]) ); | |
202 | cl_a1_msff_4x ff_din_127 ( .si(din_so[129]), .so(din_so[127]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[127]), .q(din_array[127]) ); | |
203 | cl_a1_msff_4x ff_din_126 ( .si(din_so[127]), .so(din_so[126]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[126]), .q(din_array[126]) ); | |
204 | ||
205 | cl_a1_msff_4x ff_din_125 ( .si(din_so[124]), .so(din_so[125]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[125]), .q(din_array[125]) ); | |
206 | cl_a1_msff_4x ff_din_124 ( .si(din_so[126]), .so(din_so[124]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[124]), .q(din_array[124]) ); | |
207 | cl_a1_msff_4x ff_din_123 ( .si(din_so[125]), .so(din_so[123]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[123]), .q(din_array[123]) ); | |
208 | cl_a1_msff_4x ff_din_122 ( .si(din_so[123]), .so(din_so[122]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[122]), .q(din_array[122]) ); | |
209 | ||
210 | cl_a1_msff_4x ff_din_121 ( .si(din_so[120]), .so(din_so[121]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[121]), .q(din_array[121]) ); | |
211 | cl_a1_msff_4x ff_din_120 ( .si(din_so[122]), .so(din_so[120]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[120]), .q(din_array[120]) ); | |
212 | cl_a1_msff_4x ff_din_119 ( .si(din_so[121]), .so(din_so[119]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[119]), .q(din_array[119]) ); | |
213 | cl_a1_msff_4x ff_din_118 ( .si(din_so[119]), .so(din_so[118]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[118]), .q(din_array[118]) ); | |
214 | ||
215 | cl_a1_msff_4x ff_din_117 ( .si(din_so[116]), .so(din_so[117]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[117]), .q(din_array[117]) ); | |
216 | cl_a1_msff_4x ff_din_116 ( .si(din_so[118]), .so(din_so[116]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[116]), .q(din_array[116]) ); | |
217 | cl_a1_msff_4x ff_din_115 ( .si(din_so[117]), .so(din_so[115]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[115]), .q(din_array[115]) ); | |
218 | cl_a1_msff_4x ff_din_114 ( .si(din_so[115]), .so(din_so[114]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[114]), .q(din_array[114]) ); | |
219 | ||
220 | cl_a1_msff_4x ff_din_113 ( .si(din_so[112]), .so(din_so[113]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[113]), .q(din_array[113]) ); | |
221 | cl_a1_msff_4x ff_din_112 ( .si(din_so[114]), .so(din_so[112]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[112]), .q(din_array[112]) ); | |
222 | cl_a1_msff_4x ff_din_111 ( .si(din_so[113]), .so(din_so[111]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[111]), .q(din_array[111]) ); | |
223 | cl_a1_msff_4x ff_din_110 ( .si(din_so[111]), .so(din_so[110]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[110]), .q(din_array[110]) ); | |
224 | ||
225 | cl_a1_msff_4x ff_din_109 ( .si(din_so[108]), .so(din_so[109]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[109]), .q(din_array[109]) ); | |
226 | cl_a1_msff_4x ff_din_108 ( .si(din_so[110]), .so(din_so[108]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[108]), .q(din_array[108]) ); | |
227 | cl_a1_msff_4x ff_din_107 ( .si(din_so[109]), .so(din_so[107]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[107]), .q(din_array[107]) ); | |
228 | cl_a1_msff_4x ff_din_106 ( .si(din_so[107]), .so(din_so[106]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[106]), .q(din_array[106]) ); | |
229 | ||
230 | cl_a1_msff_4x ff_din_105 ( .si(din_so[104]), .so(din_so[105]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[105]), .q(din_array[105]) ); | |
231 | cl_a1_msff_4x ff_din_104 ( .si(din_so[106]), .so(din_so[104]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[104]), .q(din_array[104]) ); | |
232 | cl_a1_msff_4x ff_din_103 ( .si(din_so[105]), .so(din_so[103]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[103]), .q(din_array[103]) ); | |
233 | cl_a1_msff_4x ff_din_102 ( .si(din_so[103]), .so(din_so[102]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[102]), .q(din_array[102]) ); | |
234 | ||
235 | cl_a1_msff_4x ff_din_101 ( .si(din_so[100]), .so(din_so[101]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[101]), .q(din_array[101]) ); | |
236 | cl_a1_msff_4x ff_din_100 ( .si(din_so[102]), .so(din_so[100]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[100]), .q(din_array[100]) ); | |
237 | cl_a1_msff_4x ff_din_99 ( .si(din_so[101]), .so(din_so[99]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[99]), .q(din_array[99]) ); | |
238 | cl_a1_msff_4x ff_din_98 ( .si(din_so[99]), .so(din_so[98]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[98]), .q(din_array[98]) ); | |
239 | ||
240 | cl_a1_msff_4x ff_din_97 ( .si(din_so[96]), .so(din_so[97]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[97]), .q(din_array[97]) ); | |
241 | cl_a1_msff_4x ff_din_96 ( .si(din_so[98]), .so(din_so[96]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[96]), .q(din_array[96]) ); | |
242 | cl_a1_msff_4x ff_din_95 ( .si(din_so[97]), .so(din_so[95]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[95]), .q(din_array[95]) ); | |
243 | cl_a1_msff_4x ff_din_94 ( .si(din_so[95]), .so(din_so[94]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[94]), .q(din_array[94]) ); | |
244 | ||
245 | cl_a1_msff_4x ff_din_93 ( .si(din_so[92]), .so(din_so[93]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[93]), .q(din_array[93]) ); | |
246 | cl_a1_msff_4x ff_din_92 ( .si(din_so[94]), .so(din_so[92]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[92]), .q(din_array[92]) ); | |
247 | cl_a1_msff_4x ff_din_91 ( .si(din_so[93]), .so(din_so[91]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[91]), .q(din_array[91]) ); | |
248 | cl_a1_msff_4x ff_din_90 ( .si(din_so[91]), .so(din_so[90]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[90]), .q(din_array[90]) ); | |
249 | ||
250 | cl_a1_msff_4x ff_din_89 ( .si(din_so[88]), .so(din_so[89]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[89]), .q(din_array[89]) ); | |
251 | cl_a1_msff_4x ff_din_88 ( .si(din_so[90]), .so(din_so[88]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[88]), .q(din_array[88]) ); | |
252 | cl_a1_msff_4x ff_din_87 ( .si(din_so[89]), .so(din_so[87]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[87]), .q(din_array[87]) ); | |
253 | cl_a1_msff_4x ff_din_86 ( .si(din_so[87]), .so(din_so[86]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[86]), .q(din_array[86]) ); | |
254 | ||
255 | cl_a1_msff_4x ff_din_85 ( .si(din_so[84]), .so(din_so[85]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[85]), .q(din_array[85]) ); | |
256 | cl_a1_msff_4x ff_din_84 ( .si(din_so[86]), .so(din_so[84]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[84]), .q(din_array[84]) ); | |
257 | cl_a1_msff_4x ff_din_83 ( .si(din_so[85]), .so(din_so[83]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[83]), .q(din_array[83]) ); | |
258 | cl_a1_msff_4x ff_din_82 ( .si(din_so[83]), .so(din_so[82]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[82]), .q(din_array[82]) ); | |
259 | ||
260 | cl_a1_msff_4x ff_din_81 ( .si(din_so[80]), .so(din_so[81]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[81]), .q(din_array[81]) ); | |
261 | cl_a1_msff_4x ff_din_80 ( .si(din_so[82]), .so(din_so[80]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[80]), .q(din_array[80]) ); | |
262 | cl_a1_msff_4x ff_din_79 ( .si(din_so[81]), .so(din_so[79]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[79]), .q(din_array[79]) ); | |
263 | cl_a1_msff_4x ff_din_78 ( .si(din_so[79]), .so(din_so[78]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[78]), .q(din_array[78]) ); | |
264 | ||
265 | cl_a1_msff_4x ff_din_77 ( .si(din_so[76]), .so(din_so[77]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[77]), .q(din_array[77]) ); | |
266 | cl_a1_msff_4x ff_din_76 ( .si(din_so[78]), .so(din_so[76]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[76]), .q(din_array[76]) ); | |
267 | cl_a1_msff_4x ff_din_75 ( .si(din_so[77]), .so(din_so[75]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[75]), .q(din_array[75]) ); | |
268 | cl_a1_msff_4x ff_din_74 ( .si(din_so[75]), .so(din_so[74]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[74]), .q(din_array[74]) ); | |
269 | ||
270 | cl_a1_msff_4x ff_din_73 ( .si(din_so[72]), .so(din_so[73]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[73]), .q(din_array[73]) ); | |
271 | cl_a1_msff_4x ff_din_72 ( .si(din_so[74]), .so(din_so[72]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[72]), .q(din_array[72]) ); | |
272 | cl_a1_msff_4x ff_din_71 ( .si(din_so[73]), .so(din_so[71]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[71]), .q(din_array[71]) ); | |
273 | cl_a1_msff_4x ff_din_70 ( .si(din_so[71]), .so(din_so[70]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[70]), .q(din_array[70]) ); | |
274 | ||
275 | cl_a1_msff_4x ff_din_69 ( .si(din_so[68]), .so(din_so[69]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[69]), .q(din_array[69]) ); | |
276 | cl_a1_msff_4x ff_din_68 ( .si(din_so[70]), .so(din_so[68]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[68]), .q(din_array[68]) ); | |
277 | cl_a1_msff_4x ff_din_67 ( .si(din_so[69]), .so(din_so[67]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[67]), .q(din_array[67]) ); | |
278 | cl_a1_msff_4x ff_din_66 ( .si(din_so[67]), .so(din_so[66]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[66]), .q(din_array[66]) ); | |
279 | ||
280 | ||
281 | cl_mc1_sram_msff_mo_8x ff_rd ( .si(din_so[66]), .so(rd_so), | |
282 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
283 | .siclk(siclk), .soclk(soclk), | |
284 | .d(rd), .mq(rd_en_d1) ); | |
285 | ||
286 | cl_mc1_sram_msff_mo_8x ff_rd_addr_5 ( .si(rd_so), .so(rd_addr_so[5]), | |
287 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
288 | .siclk(siclk), .soclk(soclk), | |
289 | .d(rd_addr[5]), .mq(rd_addr_array[5]) ); | |
290 | cl_mc1_sram_msff_mo_8x ff_rd_addr_4 ( .si(rd_addr_so[5]), .so(rd_addr_so[4]), | |
291 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
292 | .siclk(siclk), .soclk(soclk), | |
293 | .d(rd_addr[4]), .mq(rd_addr_array[4]) ); | |
294 | cl_mc1_sram_msff_mo_8x ff_rd_addr_3 ( .si(rd_addr_so[4]), .so(rd_addr_so[3]), | |
295 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
296 | .siclk(siclk), .soclk(soclk), | |
297 | .d(rd_addr[3]), .mq(rd_addr_array[3]) ); | |
298 | cl_mc1_sram_msff_mo_8x ff_rd_addr_2 ( .si(rd_addr_so[3]), .so(rd_addr_so[2]), | |
299 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
300 | .siclk(siclk), .soclk(soclk), | |
301 | .d(rd_addr[2]), .mq(rd_addr_array[2]) ); | |
302 | cl_mc1_sram_msff_mo_8x ff_rd_addr_1 ( .si(rd_addr_so[2]), .so(rd_addr_so[1]), | |
303 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
304 | .siclk(siclk), .soclk(soclk), | |
305 | .d(rd_addr[1]), .mq(rd_addr_array[1]) ); | |
306 | cl_mc1_sram_msff_mo_8x ff_rd_addr_0 ( .si(rd_addr_so[1]), .so(rd_addr_so[0]), | |
307 | .l1clk(rd_l1clk), .and_clk(rd_and_l1clk), | |
308 | .siclk(siclk), .soclk(soclk), | |
309 | .d(rd_addr[0]), .mq(rd_addr_array[0]) ); | |
310 | ||
311 | ||
312 | cl_a1_msff_4x ff_wr_en ( .si(rd_addr_so[0]), .so(wr_en_so), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
313 | .d(wr_en), .q(wr_en_d1) ); | |
314 | ||
315 | cl_a1_msff_4x ff_wr_addr_5 ( .si(wr_en_so), .so(wr_addr_so[5]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
316 | .d(wr_addr[5]), .q(wr_addr_array[5]) ); | |
317 | cl_a1_msff_4x ff_wr_addr_4 ( .si(wr_addr_so[5]), .so(wr_addr_so[4]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
318 | .d(wr_addr[4]), .q(wr_addr_array[4]) ); | |
319 | cl_a1_msff_4x ff_wr_addr_3 ( .si(wr_addr_so[4]), .so(wr_addr_so[3]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
320 | .d(wr_addr[3]), .q(wr_addr_array[3]) ); | |
321 | cl_a1_msff_4x ff_wr_addr_2 ( .si(wr_addr_so[3]), .so(wr_addr_so[2]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
322 | .d(wr_addr[2]), .q(wr_addr_array[2]) ); | |
323 | cl_a1_msff_4x ff_wr_addr_1 ( .si(wr_addr_so[2]), .so(wr_addr_so[1]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
324 | .d(wr_addr[1]), .q(wr_addr_array[1]) ); | |
325 | cl_a1_msff_4x ff_wr_addr_0 ( .si(wr_addr_so[1]), .so(wr_addr_so[0]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), | |
326 | .d(wr_addr[0]), .q(wr_addr_array[0]) ); | |
327 | ||
328 | ||
329 | cl_a1_msff_4x ff_din_65 ( .si(wr_addr_so[0]), .so(din_so[65]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[65]), .q(din_array[65]) ); | |
330 | cl_a1_msff_4x ff_din_64 ( .si(din_so[65]), .so(din_so[64]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[64]), .q(din_array[64]) ); | |
331 | ||
332 | cl_a1_msff_4x ff_din_63 ( .si(din_so[62]), .so(din_so[63]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[63]), .q(din_array[63]) ); | |
333 | cl_a1_msff_4x ff_din_62 ( .si(din_so[64]), .so(din_so[62]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[62]), .q(din_array[62]) ); | |
334 | cl_a1_msff_4x ff_din_61 ( .si(din_so[63]), .so(din_so[61]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[61]), .q(din_array[61]) ); | |
335 | cl_a1_msff_4x ff_din_60 ( .si(din_so[61]), .so(din_so[60]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[60]), .q(din_array[60]) ); | |
336 | ||
337 | cl_a1_msff_4x ff_din_59 ( .si(din_so[58]), .so(din_so[59]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[59]), .q(din_array[59]) ); | |
338 | cl_a1_msff_4x ff_din_58 ( .si(din_so[60]), .so(din_so[58]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[58]), .q(din_array[58]) ); | |
339 | cl_a1_msff_4x ff_din_57 ( .si(din_so[59]), .so(din_so[57]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[57]), .q(din_array[57]) ); | |
340 | cl_a1_msff_4x ff_din_56 ( .si(din_so[57]), .so(din_so[56]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[56]), .q(din_array[56]) ); | |
341 | ||
342 | cl_a1_msff_4x ff_din_55 ( .si(din_so[54]), .so(din_so[55]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[55]), .q(din_array[55]) ); | |
343 | cl_a1_msff_4x ff_din_54 ( .si(din_so[56]), .so(din_so[54]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[54]), .q(din_array[54]) ); | |
344 | cl_a1_msff_4x ff_din_53 ( .si(din_so[55]), .so(din_so[53]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[53]), .q(din_array[53]) ); | |
345 | cl_a1_msff_4x ff_din_52 ( .si(din_so[53]), .so(din_so[52]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[52]), .q(din_array[52]) ); | |
346 | ||
347 | cl_a1_msff_4x ff_din_51 ( .si(din_so[50]), .so(din_so[51]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[51]), .q(din_array[51]) ); | |
348 | cl_a1_msff_4x ff_din_50 ( .si(din_so[52]), .so(din_so[50]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[50]), .q(din_array[50]) ); | |
349 | cl_a1_msff_4x ff_din_49 ( .si(din_so[51]), .so(din_so[49]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[49]), .q(din_array[49]) ); | |
350 | cl_a1_msff_4x ff_din_48 ( .si(din_so[49]), .so(din_so[48]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[48]), .q(din_array[48]) ); | |
351 | ||
352 | cl_a1_msff_4x ff_din_47 ( .si(din_so[46]), .so(din_so[47]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[47]), .q(din_array[47]) ); | |
353 | cl_a1_msff_4x ff_din_46 ( .si(din_so[48]), .so(din_so[46]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[46]), .q(din_array[46]) ); | |
354 | cl_a1_msff_4x ff_din_45 ( .si(din_so[47]), .so(din_so[45]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[45]), .q(din_array[45]) ); | |
355 | cl_a1_msff_4x ff_din_44 ( .si(din_so[45]), .so(din_so[44]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[44]), .q(din_array[44]) ); | |
356 | ||
357 | cl_a1_msff_4x ff_din_43 ( .si(din_so[42]), .so(din_so[43]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[43]), .q(din_array[43]) ); | |
358 | cl_a1_msff_4x ff_din_42 ( .si(din_so[44]), .so(din_so[42]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[42]), .q(din_array[42]) ); | |
359 | cl_a1_msff_4x ff_din_41 ( .si(din_so[43]), .so(din_so[41]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[41]), .q(din_array[41]) ); | |
360 | cl_a1_msff_4x ff_din_40 ( .si(din_so[41]), .so(din_so[40]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[40]), .q(din_array[40]) ); | |
361 | ||
362 | cl_a1_msff_4x ff_din_39 ( .si(din_so[38]), .so(din_so[39]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[39]), .q(din_array[39]) ); | |
363 | cl_a1_msff_4x ff_din_38 ( .si(din_so[40]), .so(din_so[38]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[38]), .q(din_array[38]) ); | |
364 | cl_a1_msff_4x ff_din_37 ( .si(din_so[39]), .so(din_so[37]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[37]), .q(din_array[37]) ); | |
365 | cl_a1_msff_4x ff_din_36 ( .si(din_so[37]), .so(din_so[36]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[36]), .q(din_array[36]) ); | |
366 | ||
367 | cl_a1_msff_4x ff_din_35 ( .si(din_so[34]), .so(din_so[35]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[35]), .q(din_array[35]) ); | |
368 | cl_a1_msff_4x ff_din_34 ( .si(din_so[36]), .so(din_so[34]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[34]), .q(din_array[34]) ); | |
369 | cl_a1_msff_4x ff_din_33 ( .si(din_so[35]), .so(din_so[33]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[33]), .q(din_array[33]) ); | |
370 | cl_a1_msff_4x ff_din_32 ( .si(din_so[33]), .so(din_so[32]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[32]), .q(din_array[32]) ); | |
371 | ||
372 | cl_a1_msff_4x ff_din_31 ( .si(din_so[30]), .so(din_so[31]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[31]), .q(din_array[31]) ); | |
373 | cl_a1_msff_4x ff_din_30 ( .si(din_so[32]), .so(din_so[30]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[30]), .q(din_array[30]) ); | |
374 | cl_a1_msff_4x ff_din_29 ( .si(din_so[31]), .so(din_so[29]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[29]), .q(din_array[29]) ); | |
375 | cl_a1_msff_4x ff_din_28 ( .si(din_so[29]), .so(din_so[28]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[28]), .q(din_array[28]) ); | |
376 | ||
377 | cl_a1_msff_4x ff_din_27 ( .si(din_so[26]), .so(din_so[27]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[27]), .q(din_array[27]) ); | |
378 | cl_a1_msff_4x ff_din_26 ( .si(din_so[28]), .so(din_so[26]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[26]), .q(din_array[26]) ); | |
379 | cl_a1_msff_4x ff_din_25 ( .si(din_so[27]), .so(din_so[25]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[25]), .q(din_array[25]) ); | |
380 | cl_a1_msff_4x ff_din_24 ( .si(din_so[25]), .so(din_so[24]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[24]), .q(din_array[24]) ); | |
381 | ||
382 | cl_a1_msff_4x ff_din_23 ( .si(din_so[22]), .so(din_so[23]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[23]), .q(din_array[23]) ); | |
383 | cl_a1_msff_4x ff_din_22 ( .si(din_so[24]), .so(din_so[22]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[22]), .q(din_array[22]) ); | |
384 | cl_a1_msff_4x ff_din_21 ( .si(din_so[23]), .so(din_so[21]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[21]), .q(din_array[21]) ); | |
385 | cl_a1_msff_4x ff_din_20 ( .si(din_so[21]), .so(din_so[20]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[20]), .q(din_array[20]) ); | |
386 | ||
387 | cl_a1_msff_4x ff_din_19 ( .si(din_so[18]), .so(din_so[19]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[19]), .q(din_array[19]) ); | |
388 | cl_a1_msff_4x ff_din_18 ( .si(din_so[20]), .so(din_so[18]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[18]), .q(din_array[18]) ); | |
389 | cl_a1_msff_4x ff_din_17 ( .si(din_so[19]), .so(din_so[17]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[17]), .q(din_array[17]) ); | |
390 | cl_a1_msff_4x ff_din_16 ( .si(din_so[17]), .so(din_so[16]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[16]), .q(din_array[16]) ); | |
391 | ||
392 | cl_a1_msff_4x ff_din_15 ( .si(din_so[14]), .so(din_so[15]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[15]), .q(din_array[15]) ); | |
393 | cl_a1_msff_4x ff_din_14 ( .si(din_so[16]), .so(din_so[14]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[14]), .q(din_array[14]) ); | |
394 | cl_a1_msff_4x ff_din_13 ( .si(din_so[15]), .so(din_so[13]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[13]), .q(din_array[13]) ); | |
395 | cl_a1_msff_4x ff_din_12 ( .si(din_so[13]), .so(din_so[12]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[12]), .q(din_array[12]) ); | |
396 | ||
397 | cl_a1_msff_4x ff_din_11 ( .si(din_so[10]), .so(din_so[11]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[11]), .q(din_array[11]) ); | |
398 | cl_a1_msff_4x ff_din_10 ( .si(din_so[12]), .so(din_so[10]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[10]), .q(din_array[10]) ); | |
399 | cl_a1_msff_4x ff_din_9 ( .si(din_so[11]), .so(din_so[9]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[9]), .q(din_array[9]) ); | |
400 | cl_a1_msff_4x ff_din_8 ( .si(din_so[9]), .so(din_so[8]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[8]), .q(din_array[8]) ); | |
401 | ||
402 | cl_a1_msff_4x ff_din_7 ( .si(din_so[6]), .so(din_so[7]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[7]), .q(din_array[7]) ); | |
403 | cl_a1_msff_4x ff_din_6 ( .si(din_so[8]), .so(din_so[6]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[6]), .q(din_array[6]) ); | |
404 | cl_a1_msff_4x ff_din_5 ( .si(din_so[7]), .so(din_so[5]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[5]), .q(din_array[5]) ); | |
405 | cl_a1_msff_4x ff_din_4 ( .si(din_so[5]), .so(din_so[4]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[4]), .q(din_array[4]) ); | |
406 | ||
407 | cl_a1_msff_4x ff_din_3 ( .si(din_so[2]), .so(din_so[3]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[3]), .q(din_array[3]) ); | |
408 | cl_a1_msff_4x ff_din_2 ( .si(din_so[4]), .so(din_so[2]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[2]), .q(din_array[2]) ); | |
409 | cl_a1_msff_4x ff_din_1 ( .si(din_so[3]), .so(din_so[1]), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[1]), .q(din_array[1]) ); | |
410 | cl_a1_msff_4x ff_din_0 ( .si(din_so[1]), .so(scan_out), .l1clk(wr_l1clk), .siclk(siclk), .soclk(soclk), .d(din[0]), .q(din_array[0]) ); | |
411 | ||
412 | ||
413 | //------------------------------------------------------------------------ | |
414 | // instantiate the array | |
415 | //------------------------------------------------------------------------ | |
416 | ||
417 | n2_com_64x132async_dp_cust_array ptl_hb_async_ram( | |
418 | .wr_clk (wr_array_l1clk), | |
419 | .wr_addr_array (wr_addr_array[5:0]), | |
420 | .wr_en_array (wr_en_array), | |
421 | .din_array (din_array[131:0]), | |
422 | .rd_clk (rd_and_l1clk), | |
423 | .rd_addr_array (rd_addr_array[5:0]), | |
424 | .rd_en_array (rd_en_array), | |
425 | .dout_array (dout[131:0]) | |
426 | ); | |
427 | ||
428 | assign wr_en_array = wr_en_d1 & ! tcu_array_wr_inhibit ; | |
429 | assign rd_en_array = rd_en_d1 & ! tcu_array_wr_inhibit ; | |
430 | ||
431 | endmodule //n2_com_64x132async_dp_cust | |
432 | ||
433 |