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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_com_dp_128x42s_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_com_dp_128x42s_cust ( | |
36 | wr_adr, | |
37 | wr_en, | |
38 | rd_adr, | |
39 | rd_en, | |
40 | din, | |
41 | dout, | |
42 | rdclk, | |
43 | wrclk, | |
44 | scan_in, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | tcu_array_wr_inhibit, | |
49 | tcu_se_scancollar_in, | |
50 | bist_clk_mux_sel, | |
51 | rd_pce, | |
52 | wr_pce, | |
53 | scan_out); | |
54 | wire rd_lce; | |
55 | wire wr_lce; | |
56 | wire rdclk_in; | |
57 | wire wrclk_in; | |
58 | wire rdclk_free; | |
59 | wire wrclk_free; | |
60 | wire dff_wr_addr_scanin; | |
61 | wire dff_wr_addr_scanout; | |
62 | wire [6:0] wr_adr_d1; | |
63 | wire [6:1] dff_rd_addr_scan; | |
64 | wire dff_rd_addr_scanin; | |
65 | wire dff_rd_addr_scanout; | |
66 | wire [6:0] rd_adr_d1; | |
67 | wire [6:0] rd_adr_mq_l_unused; | |
68 | wire [6:0] rd_adr_q_unused; | |
69 | wire [6:0] rd_adr_q_l_unused; | |
70 | wire dff_rd_en_scanin; | |
71 | wire dff_rd_en_scanout; | |
72 | wire rd_en_d1; | |
73 | wire rd_en_mq_l_unused; | |
74 | wire rd_en_q_unused; | |
75 | wire rd_en_q_l_unused; | |
76 | wire dff_wr_en_scanin; | |
77 | wire dff_wr_en_scanout; | |
78 | wire wr_en_d1; | |
79 | wire [20:1] dff_din_hi_scan; | |
80 | wire dff_din_hi_scanin; | |
81 | wire dff_din_hi_scanout; | |
82 | wire [41:0] din_d1; | |
83 | wire [20:1] dff_din_lo_scan; | |
84 | wire dff_din_lo_scanin; | |
85 | wire dff_din_lo_scanout; | |
86 | wire wr_inh_; | |
87 | wire rd_en_d1_qual; | |
88 | wire wr_en_d1_qual; | |
89 | wire [41:0] local_dout; | |
90 | wire dff_dout_scanout; | |
91 | wire dff_dout_scanin; | |
92 | ||
93 | input [6:0] wr_adr; | |
94 | input wr_en; | |
95 | input [6:0] rd_adr; | |
96 | input rd_en; | |
97 | input [41:0] din; | |
98 | output [41:0] dout; | |
99 | input rdclk; | |
100 | input wrclk; | |
101 | input scan_in; | |
102 | input tcu_pce_ov; | |
103 | input tcu_aclk; | |
104 | input tcu_bclk; | |
105 | input tcu_array_wr_inhibit; | |
106 | input tcu_se_scancollar_in; | |
107 | ||
108 | ||
109 | input bist_clk_mux_sel; | |
110 | input rd_pce; | |
111 | input wr_pce; | |
112 | output scan_out; | |
113 | wire pce_ov = tcu_pce_ov; | |
114 | wire siclk = tcu_aclk; | |
115 | wire soclk = tcu_bclk; | |
116 | //================================================ | |
117 | // Clock headers | |
118 | //================================================ | |
119 | cl_mc1_bistlatch_4x rd_pce_lat ( | |
120 | .l2clk (rdclk), | |
121 | .pce (rd_pce), | |
122 | .pce_ov (pce_ov), | |
123 | .lce (rd_lce) | |
124 | ); | |
125 | cl_mc1_bistlatch_4x wr_pce_lat ( | |
126 | .l2clk (wrclk), | |
127 | .pce (wr_pce), | |
128 | .pce_ov (pce_ov), | |
129 | .lce (wr_lce) | |
130 | ); | |
131 | cl_mc1_bistl1hdr_8x rch_in ( | |
132 | .l2clk (rdclk), | |
133 | .se (tcu_se_scancollar_in), | |
134 | .clksel (bist_clk_mux_sel), | |
135 | .bistclk(rdclk), | |
136 | .lce (rd_lce), | |
137 | .l1clk (rdclk_in) | |
138 | ); | |
139 | cl_mc1_bistl1hdr_8x wch_in ( | |
140 | .l2clk (wrclk), | |
141 | .se (tcu_se_scancollar_in), | |
142 | .clksel (bist_clk_mux_sel), | |
143 | .bistclk(rdclk), | |
144 | .lce (wr_lce), | |
145 | .l1clk (wrclk_in) | |
146 | ); | |
147 | cl_mc1_bistl1hdr_8x rch_free ( | |
148 | .l2clk (rdclk), | |
149 | .se (1'b0), | |
150 | .clksel (bist_clk_mux_sel), | |
151 | .bistclk(rdclk), | |
152 | .lce (rd_lce), | |
153 | .l1clk (rdclk_free) | |
154 | ); | |
155 | cl_mc1_bistl1hdr_8x wch_free ( | |
156 | .l2clk (wrclk), | |
157 | .se (1'b0), | |
158 | .clksel (bist_clk_mux_sel), | |
159 | .bistclk(rdclk), | |
160 | .lce (wr_lce), | |
161 | .l1clk (wrclk_free) | |
162 | ); | |
163 | ||
164 | ||
165 | /////////////////////////////////////////////////////////////// | |
166 | // Flop the inputs // | |
167 | /////////////////////////////////////////////////////////////// | |
168 | n2_com_dp_128x42s_cust_msff_ctl_macro__width_7 dff_wr_addr ( | |
169 | .scan_in (dff_wr_addr_scanin), | |
170 | .scan_out (dff_wr_addr_scanout), | |
171 | .l1clk (wrclk_in), | |
172 | .din (wr_adr[6:0]), | |
173 | .dout (wr_adr_d1[6:0]), | |
174 | .siclk(siclk), | |
175 | .soclk(soclk) | |
176 | ); | |
177 | n2_com_dp_128x42s_cust_sram_msff_mo_macro__fs_1__width_7 dff_rd_addr ( | |
178 | .scan_in ({dff_rd_addr_scan[6:1],dff_rd_addr_scanin}), | |
179 | .scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[6:1]}), | |
180 | .l1clk (rdclk_in), | |
181 | .and_clk (rdclk_in), | |
182 | .d (rd_adr[6:0]), | |
183 | .mq (rd_adr_d1[6:0]), | |
184 | .mq_l (rd_adr_mq_l_unused[6:0]), | |
185 | .q (rd_adr_q_unused[6:0]), | |
186 | .q_l (rd_adr_q_l_unused[6:0]), | |
187 | .siclk(siclk), | |
188 | .soclk(soclk) | |
189 | ); | |
190 | n2_com_dp_128x42s_cust_sram_msff_mo_macro__width_1 dff_rd_en ( | |
191 | .scan_in (dff_rd_en_scanin), | |
192 | .scan_out (dff_rd_en_scanout), | |
193 | .l1clk (rdclk_in), | |
194 | .and_clk (rdclk_in), | |
195 | .d (rd_en), | |
196 | .mq (rd_en_d1), | |
197 | .mq_l (rd_en_mq_l_unused), | |
198 | .q (rd_en_q_unused), | |
199 | .q_l (rd_en_q_l_unused), | |
200 | .siclk(siclk), | |
201 | .soclk(soclk) | |
202 | ); | |
203 | n2_com_dp_128x42s_cust_msff_ctl_macro__width_1 dff_wr_en ( | |
204 | .scan_in (dff_wr_en_scanin), | |
205 | .scan_out (dff_wr_en_scanout), | |
206 | .l1clk (wrclk_in), | |
207 | .din (wr_en), | |
208 | .dout (wr_en_d1), | |
209 | .siclk(siclk), | |
210 | .soclk(soclk) | |
211 | ); | |
212 | n2_com_dp_128x42s_cust_msff_ctl_macro__fs_1__width_21 dff_din_hi ( | |
213 | .scan_in ({dff_din_hi_scan[20:1],dff_din_hi_scanin}), | |
214 | .scan_out ({dff_din_hi_scanout,dff_din_hi_scan[20:1]}), | |
215 | .l1clk (wrclk_in), | |
216 | .din (din[41:21]), | |
217 | .dout (din_d1[41:21]), | |
218 | .siclk(siclk), | |
219 | .soclk(soclk) | |
220 | ); | |
221 | n2_com_dp_128x42s_cust_msff_ctl_macro__fs_1__width_21 dff_din_lo ( | |
222 | .scan_in ({dff_din_lo_scan[20:1],dff_din_lo_scanin}), | |
223 | .scan_out ({dff_din_lo_scanout,dff_din_lo_scan[20:1]}), | |
224 | .l1clk (wrclk_in), | |
225 | .din (din[20:0]), | |
226 | .dout (din_d1[20:0]), | |
227 | .siclk(siclk), | |
228 | .soclk(soclk) | |
229 | ); | |
230 | n2_com_dp_128x42s_cust_inv_macro__width_1 wr_inh_inv ( | |
231 | .din (tcu_array_wr_inhibit), | |
232 | .dout (wr_inh_) | |
233 | ); | |
234 | n2_com_dp_128x42s_cust_and_macro__width_2 enable_qual ( | |
235 | .din0 ({2{wr_inh_}}), | |
236 | .din1 ({rd_en_d1,wr_en_d1}), | |
237 | .dout ({rd_en_d1_qual,wr_en_d1_qual}) | |
238 | ); | |
239 | n2_com_dp_128x42s_cust_n2_com_array_macro__rows_128__width_42__z_array array ( | |
240 | .rclk (rdclk_free), | |
241 | .wclk (wrclk_free), | |
242 | .wr_adr (wr_adr_d1[6:0]), | |
243 | .wr_en (wr_en_d1_qual), | |
244 | .rd_adr (rd_adr_d1[6:0]), | |
245 | .rd_en (rd_en_d1_qual), | |
246 | .din (din_d1[41:0]), | |
247 | .dout (local_dout[41:0]) | |
248 | ); | |
249 | ||
250 | ||
251 | assign dout[41:0] = local_dout[41:0]; | |
252 | assign dff_dout_scanout = dff_dout_scanin; | |
253 | ||
254 | supply0 vss; | |
255 | supply1 vdd; | |
256 | ||
257 | // fixscan start: | |
258 | assign dff_wr_addr_scanin = scan_in ; | |
259 | assign dff_rd_addr_scanin = dff_wr_addr_scanout ; | |
260 | assign dff_wr_en_scanin = dff_rd_addr_scanout ; | |
261 | assign dff_rd_en_scanin = dff_wr_en_scanout ; | |
262 | assign dff_din_lo_scanin = dff_rd_en_scanout ; | |
263 | assign dff_din_hi_scanin = dff_din_lo_scanout ; | |
264 | assign dff_dout_scanin = dff_din_hi_scanout ; | |
265 | assign scan_out = dff_dout_scanout ; | |
266 | // fixscan end: | |
267 | ||
268 | ||
269 | endmodule | |
270 | ||
271 | ||
272 | ||
273 | ||
274 | ||
275 | ||
276 | ||
277 | // any PARAMS parms go into naming of macro | |
278 | ||
279 | module n2_com_dp_128x42s_cust_msff_ctl_macro__width_7 ( | |
280 | din, | |
281 | l1clk, | |
282 | scan_in, | |
283 | siclk, | |
284 | soclk, | |
285 | dout, | |
286 | scan_out); | |
287 | wire [6:0] fdin; | |
288 | wire [5:0] so; | |
289 | ||
290 | input [6:0] din; | |
291 | input l1clk; | |
292 | input scan_in; | |
293 | ||
294 | ||
295 | input siclk; | |
296 | input soclk; | |
297 | ||
298 | output [6:0] dout; | |
299 | output scan_out; | |
300 | assign fdin[6:0] = din[6:0]; | |
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | ||
307 | dff #(7) d0_0 ( | |
308 | .l1clk(l1clk), | |
309 | .siclk(siclk), | |
310 | .soclk(soclk), | |
311 | .d(fdin[6:0]), | |
312 | .si({scan_in,so[5:0]}), | |
313 | .so({so[5:0],scan_out}), | |
314 | .q(dout[6:0]) | |
315 | ); | |
316 | ||
317 | ||
318 | ||
319 | ||
320 | ||
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | endmodule | |
329 | ||
330 | ||
331 | ||
332 | ||
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | // | |
339 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
340 | // | |
341 | // | |
342 | ||
343 | ||
344 | ||
345 | ||
346 | ||
347 | module n2_com_dp_128x42s_cust_sram_msff_mo_macro__fs_1__width_7 ( | |
348 | d, | |
349 | scan_in, | |
350 | l1clk, | |
351 | and_clk, | |
352 | siclk, | |
353 | soclk, | |
354 | mq, | |
355 | mq_l, | |
356 | scan_out, | |
357 | q, | |
358 | q_l); | |
359 | input [6:0] d; | |
360 | input [6:0] scan_in; | |
361 | input l1clk; | |
362 | input and_clk; | |
363 | input siclk; | |
364 | input soclk; | |
365 | output [6:0] mq; | |
366 | output [6:0] mq_l; | |
367 | output [6:0] scan_out; | |
368 | output [6:0] q; | |
369 | output [6:0] q_l; | |
370 | ||
371 | ||
372 | ||
373 | ||
374 | ||
375 | ||
376 | new_dlata #(7) d0_0 ( | |
377 | .d(d[6:0]), | |
378 | .si(scan_in[6:0]), | |
379 | .so(scan_out[6:0]), | |
380 | .l1clk(l1clk), | |
381 | .and_clk(and_clk), | |
382 | .siclk(siclk), | |
383 | .soclk(soclk), | |
384 | .q(q[6:0]), | |
385 | .q_l(q_l[6:0]), | |
386 | .mq(mq[6:0]), | |
387 | .mq_l(mq_l[6:0]) | |
388 | ); | |
389 | ||
390 | ||
391 | ||
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 | ||
399 | //place::generic_place($width,$stack,$left); | |
400 | ||
401 | endmodule | |
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | // | |
408 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
409 | // | |
410 | // | |
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | module n2_com_dp_128x42s_cust_sram_msff_mo_macro__width_1 ( | |
417 | d, | |
418 | scan_in, | |
419 | l1clk, | |
420 | and_clk, | |
421 | siclk, | |
422 | soclk, | |
423 | mq, | |
424 | mq_l, | |
425 | scan_out, | |
426 | q, | |
427 | q_l); | |
428 | input [0:0] d; | |
429 | input scan_in; | |
430 | input l1clk; | |
431 | input and_clk; | |
432 | input siclk; | |
433 | input soclk; | |
434 | output [0:0] mq; | |
435 | output [0:0] mq_l; | |
436 | output scan_out; | |
437 | output [0:0] q; | |
438 | output [0:0] q_l; | |
439 | ||
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | new_dlata #(1) d0_0 ( | |
446 | .d(d[0:0]), | |
447 | .si(scan_in), | |
448 | .so(scan_out), | |
449 | .l1clk(l1clk), | |
450 | .and_clk(and_clk), | |
451 | .siclk(siclk), | |
452 | .soclk(soclk), | |
453 | .q(q[0:0]), | |
454 | .q_l(q_l[0:0]), | |
455 | .mq(mq[0:0]), | |
456 | .mq_l(mq_l[0:0]) | |
457 | ); | |
458 | ||
459 | ||
460 | ||
461 | ||
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | //place::generic_place($width,$stack,$left); | |
469 | ||
470 | endmodule | |
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | // any PARAMS parms go into naming of macro | |
481 | ||
482 | module n2_com_dp_128x42s_cust_msff_ctl_macro__width_1 ( | |
483 | din, | |
484 | l1clk, | |
485 | scan_in, | |
486 | siclk, | |
487 | soclk, | |
488 | dout, | |
489 | scan_out); | |
490 | wire [0:0] fdin; | |
491 | ||
492 | input [0:0] din; | |
493 | input l1clk; | |
494 | input scan_in; | |
495 | ||
496 | ||
497 | input siclk; | |
498 | input soclk; | |
499 | ||
500 | output [0:0] dout; | |
501 | output scan_out; | |
502 | assign fdin[0:0] = din[0:0]; | |
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | dff #(1) d0_0 ( | |
510 | .l1clk(l1clk), | |
511 | .siclk(siclk), | |
512 | .soclk(soclk), | |
513 | .d(fdin[0:0]), | |
514 | .si(scan_in), | |
515 | .so(scan_out), | |
516 | .q(dout[0:0]) | |
517 | ); | |
518 | ||
519 | ||
520 | ||
521 | ||
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | endmodule | |
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | // any PARAMS parms go into naming of macro | |
545 | ||
546 | module n2_com_dp_128x42s_cust_msff_ctl_macro__fs_1__width_21 ( | |
547 | din, | |
548 | l1clk, | |
549 | scan_in, | |
550 | siclk, | |
551 | soclk, | |
552 | dout, | |
553 | scan_out); | |
554 | wire [20:0] fdin; | |
555 | ||
556 | input [20:0] din; | |
557 | input l1clk; | |
558 | input [20:0] scan_in; | |
559 | ||
560 | ||
561 | input siclk; | |
562 | input soclk; | |
563 | ||
564 | output [20:0] dout; | |
565 | output [20:0] scan_out; | |
566 | assign fdin[20:0] = din[20:0]; | |
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | dff #(21) d0_0 ( | |
574 | .l1clk(l1clk), | |
575 | .siclk(siclk), | |
576 | .soclk(soclk), | |
577 | .d(fdin[20:0]), | |
578 | .si(scan_in[20:0]), | |
579 | .so(scan_out[20:0]), | |
580 | .q(dout[20:0]) | |
581 | ); | |
582 | ||
583 | ||
584 | ||
585 | ||
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | endmodule | |
595 | ||
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | // | |
605 | // invert macro | |
606 | // | |
607 | // | |
608 | ||
609 | ||
610 | ||
611 | ||
612 | ||
613 | module n2_com_dp_128x42s_cust_inv_macro__width_1 ( | |
614 | din, | |
615 | dout); | |
616 | input [0:0] din; | |
617 | output [0:0] dout; | |
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | inv #(1) d0_0 ( | |
625 | .in(din[0:0]), | |
626 | .out(dout[0:0]) | |
627 | ); | |
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | endmodule | |
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | // | |
644 | // and macro for ports = 2,3,4 | |
645 | // | |
646 | // | |
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | module n2_com_dp_128x42s_cust_and_macro__width_2 ( | |
653 | din0, | |
654 | din1, | |
655 | dout); | |
656 | input [1:0] din0; | |
657 | input [1:0] din1; | |
658 | output [1:0] dout; | |
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | and2 #(2) d0_0 ( | |
666 | .in0(din0[1:0]), | |
667 | .in1(din1[1:0]), | |
668 | .out(dout[1:0]) | |
669 | ); | |
670 | ||
671 | ||
672 | ||
673 | ||
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | endmodule | |
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | module n2_com_dp_128x42s_cust_n2_com_array_macro__rows_128__width_42__z_array ( | |
691 | rclk, | |
692 | wclk, | |
693 | rd_adr, | |
694 | rd_en, | |
695 | wr_en, | |
696 | wr_adr, | |
697 | din, | |
698 | dout); | |
699 | ||
700 | input rclk; | |
701 | input wclk; | |
702 | input [6:0] rd_adr; | |
703 | input rd_en; | |
704 | input wr_en; | |
705 | input [6:0] wr_adr; | |
706 | input [42-1:0] din; | |
707 | output [42-1:0] dout; | |
708 | ||
709 | ||
710 | ||
711 | reg [42-1:0] mem[128-1:0]; | |
712 | reg [42-1:0] local_dout; | |
713 | ||
714 | `ifndef NOINITMEM | |
715 | // Emulate reset | |
716 | integer i; | |
717 | initial begin | |
718 | for (i=0; i<128; i=i+1) begin | |
719 | mem[i] = 42'b0; | |
720 | end | |
721 | local_dout = 42'b0; | |
722 | end | |
723 | `endif | |
724 | ////////////////////// | |
725 | // Read/write array | |
726 | ////////////////////// | |
727 | always @(negedge wclk) begin | |
728 | if (wr_en) begin | |
729 | mem[wr_adr] <= din; | |
730 | ||
731 | ||
732 | end | |
733 | end | |
734 | always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin | |
735 | if (rclk) begin | |
736 | if (rd_en) begin | |
737 | if (wr_en & (wr_adr[6:0] == rd_adr[6:0])) | |
738 | local_dout[42-1:0] <= 42'hx; | |
739 | else | |
740 | local_dout[42-1:0] <= mem[rd_adr] ; | |
741 | end | |
742 | else | |
743 | local_dout[42-1:0] <= ~(42'h0); | |
744 | end | |
745 | end | |
746 | assign dout[42-1:0] = local_dout[42-1:0]; | |
747 | supply0 vss; | |
748 | supply1 vdd; | |
749 | ||
750 | ||
751 | ||
752 | ||
753 | endmodule | |
754 |