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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_com_dp_16x32s_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_com_dp_16x32s_cust ( | |
36 | wr_adr, | |
37 | wr_en, | |
38 | rd_adr, | |
39 | rd_en, | |
40 | din, | |
41 | dout, | |
42 | rdclk, | |
43 | wrclk, | |
44 | scan_in, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | tcu_array_wr_inhibit, | |
49 | tcu_se_scancollar_in, | |
50 | bist_clk_mux_sel, | |
51 | rd_pce, | |
52 | wr_pce, | |
53 | scan_out); | |
54 | wire rd_lce; | |
55 | wire wr_lce; | |
56 | wire rdclk_in; | |
57 | wire wrclk_in; | |
58 | wire rdclk_free; | |
59 | wire wrclk_free; | |
60 | wire dff_wr_addr_scanin; | |
61 | wire dff_wr_addr_scanout; | |
62 | wire [3:0] wr_adr_d1; | |
63 | wire [3:1] dff_rd_addr_scan; | |
64 | wire dff_rd_addr_scanin; | |
65 | wire dff_rd_addr_scanout; | |
66 | wire [3:0] rd_adr_d1; | |
67 | wire [3:0] rd_adr_mq_l_unused; | |
68 | wire [3:0] rd_adr_q_unused; | |
69 | wire [3:0] rd_adr_q_l_unused; | |
70 | wire dff_rd_en_scanin; | |
71 | wire dff_rd_en_scanout; | |
72 | wire rd_en_d1; | |
73 | wire rd_en_mq_l_unused; | |
74 | wire rd_en_q_unused; | |
75 | wire rd_en_q_l_unused; | |
76 | wire dff_wr_en_scanin; | |
77 | wire dff_wr_en_scanout; | |
78 | wire wr_en_d1; | |
79 | wire [15:1] dff_din_hi_scan; | |
80 | wire dff_din_hi_scanin; | |
81 | wire dff_din_hi_scanout; | |
82 | wire [31:0] din_d1; | |
83 | wire [15:1] dff_din_lo_scan; | |
84 | wire dff_din_lo_scanin; | |
85 | wire dff_din_lo_scanout; | |
86 | wire wr_inh_; | |
87 | wire rd_en_d1_qual; | |
88 | wire wr_en_d1_qual; | |
89 | wire [31:0] local_dout; | |
90 | wire dff_dout_scanout; | |
91 | wire dff_dout_scanin; | |
92 | ||
93 | input [3:0] wr_adr; | |
94 | input wr_en; | |
95 | input [3:0] rd_adr; | |
96 | input rd_en; | |
97 | input [31:0] din; | |
98 | output [31:0] dout; | |
99 | input rdclk; | |
100 | input wrclk; | |
101 | input scan_in; | |
102 | input tcu_pce_ov; | |
103 | input tcu_aclk; | |
104 | input tcu_bclk; | |
105 | input tcu_array_wr_inhibit; | |
106 | input tcu_se_scancollar_in; | |
107 | ||
108 | ||
109 | input bist_clk_mux_sel; | |
110 | input rd_pce; | |
111 | input wr_pce; | |
112 | output scan_out; | |
113 | ||
114 | // synopsys translate_off | |
115 | ||
116 | wire pce_ov = tcu_pce_ov; | |
117 | wire siclk = tcu_aclk; | |
118 | wire soclk = tcu_bclk; | |
119 | //================================================ | |
120 | // Clock headers | |
121 | //================================================ | |
122 | cl_mc1_bistlatch_4x rd_pce_lat ( | |
123 | .l2clk (rdclk), | |
124 | .pce (rd_pce), | |
125 | .pce_ov (pce_ov), | |
126 | .lce (rd_lce) | |
127 | ); | |
128 | cl_mc1_bistlatch_4x wr_pce_lat ( | |
129 | .l2clk (wrclk), | |
130 | .pce (wr_pce), | |
131 | .pce_ov (pce_ov), | |
132 | .lce (wr_lce) | |
133 | ); | |
134 | cl_mc1_bistl1hdr_8x rch_in ( | |
135 | .l2clk (rdclk), | |
136 | .se (tcu_se_scancollar_in), | |
137 | .clksel (bist_clk_mux_sel), | |
138 | .bistclk(rdclk), | |
139 | .lce (rd_lce), | |
140 | .l1clk (rdclk_in) | |
141 | ); | |
142 | cl_mc1_bistl1hdr_8x wch_in ( | |
143 | .l2clk (wrclk), | |
144 | .se (tcu_se_scancollar_in), | |
145 | .clksel (bist_clk_mux_sel), | |
146 | .bistclk(rdclk), | |
147 | .lce (wr_lce), | |
148 | .l1clk (wrclk_in) | |
149 | ); | |
150 | cl_mc1_bistl1hdr_8x rch_free ( | |
151 | .l2clk (rdclk), | |
152 | .se (1'b0), | |
153 | .clksel (bist_clk_mux_sel), | |
154 | .bistclk(rdclk), | |
155 | .lce (rd_lce), | |
156 | .l1clk (rdclk_free) | |
157 | ); | |
158 | cl_mc1_bistl1hdr_8x wch_free ( | |
159 | .l2clk (wrclk), | |
160 | .se (1'b0), | |
161 | .clksel (bist_clk_mux_sel), | |
162 | .bistclk(rdclk), | |
163 | .lce (wr_lce), | |
164 | .l1clk (wrclk_free) | |
165 | ); | |
166 | ||
167 | ||
168 | /////////////////////////////////////////////////////////////// | |
169 | // Flop the inputs // | |
170 | /////////////////////////////////////////////////////////////// | |
171 | n2_com_dp_16x32s_cust_msff_ctl_macro__width_4 dff_wr_addr ( | |
172 | .scan_in (dff_wr_addr_scanin), | |
173 | .scan_out (dff_wr_addr_scanout), | |
174 | .l1clk (wrclk_in), | |
175 | .din (wr_adr[3:0]), | |
176 | .dout (wr_adr_d1[3:0]), | |
177 | .siclk(siclk), | |
178 | .soclk(soclk) | |
179 | ); | |
180 | n2_com_dp_16x32s_cust_sram_msff_mo_macro__fs_1__width_4 dff_rd_addr ( | |
181 | .scan_in ({dff_rd_addr_scan[3:1],dff_rd_addr_scanin}), | |
182 | .scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[3:1]}), | |
183 | .l1clk (rdclk_in), | |
184 | .and_clk (rdclk_in), | |
185 | .d (rd_adr[3:0]), | |
186 | .mq (rd_adr_d1[3:0]), | |
187 | .mq_l (rd_adr_mq_l_unused[3:0]), | |
188 | .q (rd_adr_q_unused[3:0]), | |
189 | .q_l (rd_adr_q_l_unused[3:0]), | |
190 | .siclk(siclk), | |
191 | .soclk(soclk) | |
192 | ); | |
193 | n2_com_dp_16x32s_cust_sram_msff_mo_macro__width_1 dff_rd_en ( | |
194 | .scan_in (dff_rd_en_scanin), | |
195 | .scan_out (dff_rd_en_scanout), | |
196 | .l1clk (rdclk_in), | |
197 | .and_clk (rdclk_in), | |
198 | .d (rd_en), | |
199 | .mq (rd_en_d1), | |
200 | .mq_l (rd_en_mq_l_unused), | |
201 | .q (rd_en_q_unused), | |
202 | .q_l (rd_en_q_l_unused), | |
203 | .siclk(siclk), | |
204 | .soclk(soclk) | |
205 | ); | |
206 | n2_com_dp_16x32s_cust_msff_ctl_macro__width_1 dff_wr_en ( | |
207 | .scan_in (dff_wr_en_scanin), | |
208 | .scan_out (dff_wr_en_scanout), | |
209 | .l1clk (wrclk_in), | |
210 | .din (wr_en), | |
211 | .dout (wr_en_d1), | |
212 | .siclk(siclk), | |
213 | .soclk(soclk) | |
214 | ); | |
215 | n2_com_dp_16x32s_cust_msff_ctl_macro__fs_1__width_16 dff_din_hi ( | |
216 | .scan_in ({dff_din_hi_scan[15:1],dff_din_hi_scanin}), | |
217 | .scan_out ({dff_din_hi_scanout,dff_din_hi_scan[15:1]}), | |
218 | .l1clk (wrclk_in), | |
219 | .din (din[31:16]), | |
220 | .dout (din_d1[31:16]), | |
221 | .siclk(siclk), | |
222 | .soclk(soclk) | |
223 | ); | |
224 | n2_com_dp_16x32s_cust_msff_ctl_macro__fs_1__width_16 dff_din_lo ( | |
225 | .scan_in ({dff_din_lo_scan[15:1],dff_din_lo_scanin}), | |
226 | .scan_out ({dff_din_lo_scanout,dff_din_lo_scan[15:1]}), | |
227 | .l1clk (wrclk_in), | |
228 | .din (din[15:0]), | |
229 | .dout (din_d1[15:0]), | |
230 | .siclk(siclk), | |
231 | .soclk(soclk) | |
232 | ); | |
233 | n2_com_dp_16x32s_cust_inv_macro__width_1 wr_inh_inv ( | |
234 | .din (tcu_array_wr_inhibit), | |
235 | .dout (wr_inh_) | |
236 | ); | |
237 | n2_com_dp_16x32s_cust_and_macro__width_2 enable_qual ( | |
238 | .din0 ({2{wr_inh_}}), | |
239 | .din1 ({rd_en_d1,wr_en_d1}), | |
240 | .dout ({rd_en_d1_qual,wr_en_d1_qual}) | |
241 | ); | |
242 | n2_com_dp_16x32s_cust_n2_com_array_macro__rows_16__width_32__z_array array ( | |
243 | .rclk (rdclk_free), | |
244 | .wclk (wrclk_free), | |
245 | .wr_adr (wr_adr_d1[3:0]), | |
246 | .wr_en (wr_en_d1_qual), | |
247 | .rd_adr (rd_adr_d1[3:0]), | |
248 | .rd_en (rd_en_d1_qual), | |
249 | .din (din_d1[31:0]), | |
250 | .dout (local_dout[31:0]) | |
251 | ); | |
252 | ||
253 | ||
254 | assign dout[31:0] = local_dout[31:0]; | |
255 | assign dff_dout_scanout = dff_dout_scanin; | |
256 | ||
257 | supply0 vss; | |
258 | supply1 vdd; | |
259 | ||
260 | // fixscan start: | |
261 | assign dff_wr_addr_scanin = scan_in ; | |
262 | assign dff_rd_addr_scanin = dff_wr_addr_scanout ; | |
263 | assign dff_wr_en_scanin = dff_rd_addr_scanout ; | |
264 | assign dff_rd_en_scanin = dff_wr_en_scanout ; | |
265 | assign dff_din_lo_scanin = dff_rd_en_scanout ; | |
266 | assign dff_din_hi_scanin = dff_din_lo_scanout ; | |
267 | assign dff_dout_scanin = dff_din_hi_scanout ; | |
268 | assign scan_out = dff_dout_scanout ; | |
269 | // fixscan end: | |
270 | ||
271 | // synopsys translate_on | |
272 | ||
273 | endmodule | |
274 | ||
275 | ||
276 | ||
277 | ||
278 | ||
279 | ||
280 | ||
281 | // any PARAMS parms go into naming of macro | |
282 | ||
283 | module n2_com_dp_16x32s_cust_msff_ctl_macro__width_4 ( | |
284 | din, | |
285 | l1clk, | |
286 | scan_in, | |
287 | siclk, | |
288 | soclk, | |
289 | dout, | |
290 | scan_out); | |
291 | wire [3:0] fdin; | |
292 | wire [2:0] so; | |
293 | ||
294 | input [3:0] din; | |
295 | input l1clk; | |
296 | input scan_in; | |
297 | ||
298 | ||
299 | input siclk; | |
300 | input soclk; | |
301 | ||
302 | output [3:0] dout; | |
303 | output scan_out; | |
304 | assign fdin[3:0] = din[3:0]; | |
305 | ||
306 | ||
307 | ||
308 | ||
309 | ||
310 | ||
311 | dff #(4) d0_0 ( | |
312 | .l1clk(l1clk), | |
313 | .siclk(siclk), | |
314 | .soclk(soclk), | |
315 | .d(fdin[3:0]), | |
316 | .si({scan_in,so[2:0]}), | |
317 | .so({so[2:0],scan_out}), | |
318 | .q(dout[3:0]) | |
319 | ); | |
320 | ||
321 | ||
322 | ||
323 | ||
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | ||
330 | ||
331 | ||
332 | endmodule | |
333 | ||
334 | ||
335 | ||
336 | ||
337 | ||
338 | ||
339 | ||
340 | ||
341 | ||
342 | // | |
343 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
344 | // | |
345 | // | |
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | module n2_com_dp_16x32s_cust_sram_msff_mo_macro__fs_1__width_4 ( | |
352 | d, | |
353 | scan_in, | |
354 | l1clk, | |
355 | and_clk, | |
356 | siclk, | |
357 | soclk, | |
358 | mq, | |
359 | mq_l, | |
360 | scan_out, | |
361 | q, | |
362 | q_l); | |
363 | input [3:0] d; | |
364 | input [3:0] scan_in; | |
365 | input l1clk; | |
366 | input and_clk; | |
367 | input siclk; | |
368 | input soclk; | |
369 | output [3:0] mq; | |
370 | output [3:0] mq_l; | |
371 | output [3:0] scan_out; | |
372 | output [3:0] q; | |
373 | output [3:0] q_l; | |
374 | ||
375 | ||
376 | ||
377 | ||
378 | ||
379 | ||
380 | new_dlata #(4) d0_0 ( | |
381 | .d(d[3:0]), | |
382 | .si(scan_in[3:0]), | |
383 | .so(scan_out[3:0]), | |
384 | .l1clk(l1clk), | |
385 | .and_clk(and_clk), | |
386 | .siclk(siclk), | |
387 | .soclk(soclk), | |
388 | .q(q[3:0]), | |
389 | .q_l(q_l[3:0]), | |
390 | .mq(mq[3:0]), | |
391 | .mq_l(mq_l[3:0]) | |
392 | ); | |
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | ||
403 | //place::generic_place($width,$stack,$left); | |
404 | ||
405 | endmodule | |
406 | ||
407 | ||
408 | ||
409 | ||
410 | ||
411 | // | |
412 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
413 | // | |
414 | // | |
415 | ||
416 | ||
417 | ||
418 | ||
419 | ||
420 | module n2_com_dp_16x32s_cust_sram_msff_mo_macro__width_1 ( | |
421 | d, | |
422 | scan_in, | |
423 | l1clk, | |
424 | and_clk, | |
425 | siclk, | |
426 | soclk, | |
427 | mq, | |
428 | mq_l, | |
429 | scan_out, | |
430 | q, | |
431 | q_l); | |
432 | input [0:0] d; | |
433 | input scan_in; | |
434 | input l1clk; | |
435 | input and_clk; | |
436 | input siclk; | |
437 | input soclk; | |
438 | output [0:0] mq; | |
439 | output [0:0] mq_l; | |
440 | output scan_out; | |
441 | output [0:0] q; | |
442 | output [0:0] q_l; | |
443 | ||
444 | ||
445 | ||
446 | ||
447 | ||
448 | ||
449 | new_dlata #(1) d0_0 ( | |
450 | .d(d[0:0]), | |
451 | .si(scan_in), | |
452 | .so(scan_out), | |
453 | .l1clk(l1clk), | |
454 | .and_clk(and_clk), | |
455 | .siclk(siclk), | |
456 | .soclk(soclk), | |
457 | .q(q[0:0]), | |
458 | .q_l(q_l[0:0]), | |
459 | .mq(mq[0:0]), | |
460 | .mq_l(mq_l[0:0]) | |
461 | ); | |
462 | ||
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | //place::generic_place($width,$stack,$left); | |
473 | ||
474 | endmodule | |
475 | ||
476 | ||
477 | ||
478 | ||
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | // any PARAMS parms go into naming of macro | |
485 | ||
486 | module n2_com_dp_16x32s_cust_msff_ctl_macro__width_1 ( | |
487 | din, | |
488 | l1clk, | |
489 | scan_in, | |
490 | siclk, | |
491 | soclk, | |
492 | dout, | |
493 | scan_out); | |
494 | wire [0:0] fdin; | |
495 | ||
496 | input [0:0] din; | |
497 | input l1clk; | |
498 | input scan_in; | |
499 | ||
500 | ||
501 | input siclk; | |
502 | input soclk; | |
503 | ||
504 | output [0:0] dout; | |
505 | output scan_out; | |
506 | assign fdin[0:0] = din[0:0]; | |
507 | ||
508 | ||
509 | ||
510 | ||
511 | ||
512 | ||
513 | dff #(1) d0_0 ( | |
514 | .l1clk(l1clk), | |
515 | .siclk(siclk), | |
516 | .soclk(soclk), | |
517 | .d(fdin[0:0]), | |
518 | .si(scan_in), | |
519 | .so(scan_out), | |
520 | .q(dout[0:0]) | |
521 | ); | |
522 | ||
523 | ||
524 | ||
525 | ||
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | endmodule | |
535 | ||
536 | ||
537 | ||
538 | ||
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | // any PARAMS parms go into naming of macro | |
549 | ||
550 | module n2_com_dp_16x32s_cust_msff_ctl_macro__fs_1__width_16 ( | |
551 | din, | |
552 | l1clk, | |
553 | scan_in, | |
554 | siclk, | |
555 | soclk, | |
556 | dout, | |
557 | scan_out); | |
558 | wire [15:0] fdin; | |
559 | ||
560 | input [15:0] din; | |
561 | input l1clk; | |
562 | input [15:0] scan_in; | |
563 | ||
564 | ||
565 | input siclk; | |
566 | input soclk; | |
567 | ||
568 | output [15:0] dout; | |
569 | output [15:0] scan_out; | |
570 | assign fdin[15:0] = din[15:0]; | |
571 | ||
572 | ||
573 | ||
574 | ||
575 | ||
576 | ||
577 | dff #(16) d0_0 ( | |
578 | .l1clk(l1clk), | |
579 | .siclk(siclk), | |
580 | .soclk(soclk), | |
581 | .d(fdin[15:0]), | |
582 | .si(scan_in[15:0]), | |
583 | .so(scan_out[15:0]), | |
584 | .q(dout[15:0]) | |
585 | ); | |
586 | ||
587 | ||
588 | ||
589 | ||
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | ||
598 | endmodule | |
599 | ||
600 | ||
601 | ||
602 | ||
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | // | |
609 | // invert macro | |
610 | // | |
611 | // | |
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | module n2_com_dp_16x32s_cust_inv_macro__width_1 ( | |
618 | din, | |
619 | dout); | |
620 | input [0:0] din; | |
621 | output [0:0] dout; | |
622 | ||
623 | ||
624 | ||
625 | ||
626 | ||
627 | ||
628 | inv #(1) d0_0 ( | |
629 | .in(din[0:0]), | |
630 | .out(dout[0:0]) | |
631 | ); | |
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | endmodule | |
642 | ||
643 | ||
644 | ||
645 | ||
646 | ||
647 | // | |
648 | // and macro for ports = 2,3,4 | |
649 | // | |
650 | // | |
651 | ||
652 | ||
653 | ||
654 | ||
655 | ||
656 | module n2_com_dp_16x32s_cust_and_macro__width_2 ( | |
657 | din0, | |
658 | din1, | |
659 | dout); | |
660 | input [1:0] din0; | |
661 | input [1:0] din1; | |
662 | output [1:0] dout; | |
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | ||
669 | and2 #(2) d0_0 ( | |
670 | .in0(din0[1:0]), | |
671 | .in1(din1[1:0]), | |
672 | .out(dout[1:0]) | |
673 | ); | |
674 | ||
675 | ||
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | endmodule | |
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | module n2_com_dp_16x32s_cust_n2_com_array_macro__rows_16__width_32__z_array ( | |
695 | rclk, | |
696 | wclk, | |
697 | rd_adr, | |
698 | rd_en, | |
699 | wr_en, | |
700 | wr_adr, | |
701 | din, | |
702 | dout); | |
703 | ||
704 | input rclk; | |
705 | input wclk; | |
706 | input [3:0] rd_adr; | |
707 | input rd_en; | |
708 | input wr_en; | |
709 | input [3:0] wr_adr; | |
710 | input [32-1:0] din; | |
711 | output [32-1:0] dout; | |
712 | ||
713 | ||
714 | ||
715 | reg [32-1:0] mem[16-1:0]; | |
716 | reg [32-1:0] local_dout; | |
717 | ||
718 | `ifndef NOINITMEM | |
719 | // Emulate reset | |
720 | integer i; | |
721 | initial begin | |
722 | for (i=0; i<16; i=i+1) begin | |
723 | mem[i] = 32'b0; | |
724 | end | |
725 | local_dout = 32'b0; | |
726 | end | |
727 | `endif | |
728 | ////////////////////// | |
729 | // Read/write array | |
730 | ////////////////////// | |
731 | always @(negedge wclk) begin | |
732 | if (wr_en) begin | |
733 | mem[wr_adr] <= din; | |
734 | ||
735 | ||
736 | end | |
737 | end | |
738 | always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin | |
739 | if (rclk) begin | |
740 | if (rd_en) begin | |
741 | if (wr_en & (wr_adr[3:0] == rd_adr[3:0])) | |
742 | local_dout[32-1:0] <= 32'hx; | |
743 | else | |
744 | local_dout[32-1:0] <= mem[rd_adr] ; | |
745 | end | |
746 | else | |
747 | local_dout[32-1:0] <= ~(32'h0); | |
748 | end | |
749 | end | |
750 | assign dout[32-1:0] = local_dout[32-1:0]; | |
751 | supply0 vss; | |
752 | supply1 vdd; | |
753 | ||
754 | ||
755 | ||
756 | ||
757 | endmodule | |
758 |