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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_com_dp_32x152_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_com_dp_32x152_cust ( | |
36 | wr_adr, | |
37 | wr_en, | |
38 | rd_adr, | |
39 | rd_en, | |
40 | din, | |
41 | dout, | |
42 | rdclk, | |
43 | wrclk, | |
44 | scan_in, | |
45 | tcu_pce_ov, | |
46 | tcu_aclk, | |
47 | tcu_bclk, | |
48 | tcu_array_wr_inhibit, | |
49 | tcu_se_scancollar_in, | |
50 | bist_clk_mux_sel, | |
51 | rd_pce, | |
52 | wr_pce, | |
53 | scan_out); | |
54 | wire rd_lce; | |
55 | wire wr_lce; | |
56 | wire rdclk_in; | |
57 | wire wrclk_in; | |
58 | wire rdclk_free; | |
59 | wire wrclk_free; | |
60 | wire dff_wr_addr_scanin; | |
61 | wire dff_wr_addr_scanout; | |
62 | wire [4:0] wr_adr_d1; | |
63 | wire [4:1] dff_rd_addr_scan; | |
64 | wire dff_rd_addr_scanin; | |
65 | wire dff_rd_addr_scanout; | |
66 | wire [4:0] rd_adr_d1; | |
67 | wire [4:0] rd_adr_mq_l_unused; | |
68 | wire [4:0] rd_adr_q_unused; | |
69 | wire [4:0] rd_adr_q_l_unused; | |
70 | wire dff_rd_en_scanin; | |
71 | wire dff_rd_en_scanout; | |
72 | wire rd_en_d1; | |
73 | wire rd_en_mq_l_unused; | |
74 | wire rd_en_q_unused; | |
75 | wire rd_en_q_l_unused; | |
76 | wire dff_wr_en_scanin; | |
77 | wire dff_wr_en_scanout; | |
78 | wire wr_en_d1; | |
79 | wire [75:1] dff_din_hi_scan; | |
80 | wire dff_din_hi_scanin; | |
81 | wire dff_din_hi_scanout; | |
82 | wire [151:0] din_d1; | |
83 | wire [75:1] dff_din_lo_scan; | |
84 | wire dff_din_lo_scanin; | |
85 | wire dff_din_lo_scanout; | |
86 | wire wr_inh_; | |
87 | wire rd_en_d1_qual; | |
88 | wire wr_en_d1_qual; | |
89 | wire [151:0] local_dout; | |
90 | wire dff_dout_scanout; | |
91 | wire dff_dout_scanin; | |
92 | ||
93 | input [4:0] wr_adr; | |
94 | input wr_en; | |
95 | input [4:0] rd_adr; | |
96 | input rd_en; | |
97 | input [151:0] din; | |
98 | output [151:0] dout; | |
99 | input rdclk; | |
100 | input wrclk; | |
101 | input scan_in; | |
102 | input tcu_pce_ov; | |
103 | input tcu_aclk; | |
104 | input tcu_bclk; | |
105 | input tcu_array_wr_inhibit; | |
106 | input tcu_se_scancollar_in; | |
107 | ||
108 | ||
109 | input bist_clk_mux_sel; | |
110 | input rd_pce; | |
111 | input wr_pce; | |
112 | output scan_out; | |
113 | ||
114 | `ifndef FPGA | |
115 | // synopsys translate_off | |
116 | `endif | |
117 | ||
118 | wire pce_ov = tcu_pce_ov; | |
119 | wire siclk = tcu_aclk; | |
120 | wire soclk = tcu_bclk; | |
121 | //================================================ | |
122 | // Clock headers | |
123 | //================================================ | |
124 | cl_mc1_bistlatch_4x rd_pce_lat ( | |
125 | .l2clk (rdclk), | |
126 | .pce (rd_pce), | |
127 | .pce_ov (pce_ov), | |
128 | .lce (rd_lce) | |
129 | ); | |
130 | cl_mc1_bistlatch_4x wr_pce_lat ( | |
131 | .l2clk (wrclk), | |
132 | .pce (wr_pce), | |
133 | .pce_ov (pce_ov), | |
134 | .lce (wr_lce) | |
135 | ); | |
136 | cl_mc1_bistl1hdr_8x rch_in ( | |
137 | .l2clk (rdclk), | |
138 | .se (tcu_se_scancollar_in), | |
139 | .clksel (bist_clk_mux_sel), | |
140 | .bistclk(rdclk), | |
141 | .lce (rd_lce), | |
142 | .l1clk (rdclk_in) | |
143 | ); | |
144 | cl_mc1_bistl1hdr_8x wch_in ( | |
145 | .l2clk (wrclk), | |
146 | .se (tcu_se_scancollar_in), | |
147 | .clksel (bist_clk_mux_sel), | |
148 | .bistclk(rdclk), | |
149 | .lce (wr_lce), | |
150 | .l1clk (wrclk_in) | |
151 | ); | |
152 | cl_mc1_bistl1hdr_8x rch_free ( | |
153 | .l2clk (rdclk), | |
154 | .se (1'b0), | |
155 | .clksel (bist_clk_mux_sel), | |
156 | .bistclk(rdclk), | |
157 | .lce (rd_lce), | |
158 | .l1clk (rdclk_free) | |
159 | ); | |
160 | cl_mc1_bistl1hdr_8x wch_free ( | |
161 | .l2clk (wrclk), | |
162 | .se (1'b0), | |
163 | .clksel (bist_clk_mux_sel), | |
164 | .bistclk(rdclk), | |
165 | .lce (wr_lce), | |
166 | .l1clk (wrclk_free) | |
167 | ); | |
168 | ||
169 | ||
170 | /////////////////////////////////////////////////////////////// | |
171 | // Flop the inputs // | |
172 | /////////////////////////////////////////////////////////////// | |
173 | n2_com_dp_32x152_cust_msff_ctl_macro__width_5 dff_wr_addr ( | |
174 | .scan_in (dff_wr_addr_scanin), | |
175 | .scan_out (dff_wr_addr_scanout), | |
176 | .l1clk (wrclk_in), | |
177 | .din (wr_adr[4:0]), | |
178 | .dout (wr_adr_d1[4:0]), | |
179 | .siclk(siclk), | |
180 | .soclk(soclk) | |
181 | ); | |
182 | n2_com_dp_32x152_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr ( | |
183 | .scan_in ({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}), | |
184 | .scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}), | |
185 | .l1clk (rdclk_in), | |
186 | .and_clk (rdclk_in), | |
187 | .d (rd_adr[4:0]), | |
188 | .mq (rd_adr_d1[4:0]), | |
189 | .mq_l (rd_adr_mq_l_unused[4:0]), | |
190 | .q (rd_adr_q_unused[4:0]), | |
191 | .q_l (rd_adr_q_l_unused[4:0]), | |
192 | .siclk(siclk), | |
193 | .soclk(soclk) | |
194 | ); | |
195 | n2_com_dp_32x152_cust_sram_msff_mo_macro__width_1 dff_rd_en ( | |
196 | .scan_in (dff_rd_en_scanin), | |
197 | .scan_out (dff_rd_en_scanout), | |
198 | .l1clk (rdclk_in), | |
199 | .and_clk (rdclk_in), | |
200 | .d (rd_en), | |
201 | .mq (rd_en_d1), | |
202 | .mq_l (rd_en_mq_l_unused), | |
203 | .q (rd_en_q_unused), | |
204 | .q_l (rd_en_q_l_unused), | |
205 | .siclk(siclk), | |
206 | .soclk(soclk) | |
207 | ); | |
208 | n2_com_dp_32x152_cust_msff_ctl_macro__width_1 dff_wr_en ( | |
209 | .scan_in (dff_wr_en_scanin), | |
210 | .scan_out (dff_wr_en_scanout), | |
211 | .l1clk (wrclk_in), | |
212 | .din (wr_en), | |
213 | .dout (wr_en_d1), | |
214 | .siclk(siclk), | |
215 | .soclk(soclk) | |
216 | ); | |
217 | n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 dff_din_hi ( | |
218 | .scan_in ({dff_din_hi_scan[75:1],dff_din_hi_scanin}), | |
219 | .scan_out ({dff_din_hi_scanout,dff_din_hi_scan[75:1]}), | |
220 | .l1clk (wrclk_in), | |
221 | .din (din[151:76]), | |
222 | .dout (din_d1[151:76]), | |
223 | .siclk(siclk), | |
224 | .soclk(soclk) | |
225 | ); | |
226 | n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 dff_din_lo ( | |
227 | .scan_in ({dff_din_lo_scan[75:1],dff_din_lo_scanin}), | |
228 | .scan_out ({dff_din_lo_scanout,dff_din_lo_scan[75:1]}), | |
229 | .l1clk (wrclk_in), | |
230 | .din (din[75:0]), | |
231 | .dout (din_d1[75:0]), | |
232 | .siclk(siclk), | |
233 | .soclk(soclk) | |
234 | ); | |
235 | n2_com_dp_32x152_cust_inv_macro__width_1 wr_inh_inv ( | |
236 | .din (tcu_array_wr_inhibit), | |
237 | .dout (wr_inh_) | |
238 | ); | |
239 | n2_com_dp_32x152_cust_and_macro__width_2 enable_qual ( | |
240 | .din0 ({2{wr_inh_}}), | |
241 | .din1 ({rd_en_d1,wr_en_d1}), | |
242 | .dout ({rd_en_d1_qual,wr_en_d1_qual}) | |
243 | ); | |
244 | n2_com_dp_32x152_cust_n2_com_array_macro__rows_32__width_152__z_array array ( | |
245 | .rclk (rdclk_free), | |
246 | .wclk (wrclk_free), | |
247 | .wr_adr (wr_adr_d1[4:0]), | |
248 | .wr_en (wr_en_d1_qual), | |
249 | .rd_adr (rd_adr_d1[4:0]), | |
250 | .rd_en (rd_en_d1_qual), | |
251 | .din (din_d1[151:0]), | |
252 | .dout (local_dout[151:0]) | |
253 | ); | |
254 | ||
255 | ||
256 | assign dout[151:0] = local_dout[151:0]; | |
257 | assign dff_dout_scanout = dff_dout_scanin; | |
258 | ||
259 | supply0 vss; | |
260 | supply1 vdd; | |
261 | ||
262 | // fixscan start: | |
263 | assign dff_din_lo_scanin = scan_in ; | |
264 | assign dff_wr_addr_scanin = dff_din_lo_scanout ; | |
265 | assign dff_rd_addr_scanin = dff_wr_addr_scanout ; | |
266 | assign dff_wr_en_scanin = dff_rd_addr_scanout ; | |
267 | assign dff_rd_en_scanin = dff_wr_en_scanout ; | |
268 | assign dff_din_hi_scanin = dff_rd_en_scanout ; | |
269 | assign dff_dout_scanin = dff_din_hi_scanout ; | |
270 | assign scan_out = dff_dout_scanout ; | |
271 | // fixscan end: | |
272 | ||
273 | `ifndef FPGA | |
274 | // synopsys translate_on | |
275 | `endif | |
276 | ||
277 | endmodule | |
278 | ||
279 | ||
280 | ||
281 | ||
282 | ||
283 | ||
284 | ||
285 | // any PARAMS parms go into naming of macro | |
286 | ||
287 | module n2_com_dp_32x152_cust_msff_ctl_macro__width_5 ( | |
288 | din, | |
289 | l1clk, | |
290 | scan_in, | |
291 | siclk, | |
292 | soclk, | |
293 | dout, | |
294 | scan_out); | |
295 | wire [4:0] fdin; | |
296 | wire [3:0] so; | |
297 | ||
298 | input [4:0] din; | |
299 | input l1clk; | |
300 | input scan_in; | |
301 | ||
302 | ||
303 | input siclk; | |
304 | input soclk; | |
305 | ||
306 | output [4:0] dout; | |
307 | output scan_out; | |
308 | assign fdin[4:0] = din[4:0]; | |
309 | ||
310 | ||
311 | ||
312 | ||
313 | ||
314 | ||
315 | dff #(5) d0_0 ( | |
316 | .l1clk(l1clk), | |
317 | .siclk(siclk), | |
318 | .soclk(soclk), | |
319 | .d(fdin[4:0]), | |
320 | .si({scan_in,so[3:0]}), | |
321 | .so({so[3:0],scan_out}), | |
322 | .q(dout[4:0]) | |
323 | ); | |
324 | ||
325 | ||
326 | ||
327 | ||
328 | ||
329 | ||
330 | ||
331 | ||
332 | ||
333 | ||
334 | ||
335 | ||
336 | endmodule | |
337 | ||
338 | ||
339 | ||
340 | ||
341 | ||
342 | ||
343 | ||
344 | ||
345 | ||
346 | // | |
347 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
348 | // | |
349 | // | |
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | module n2_com_dp_32x152_cust_sram_msff_mo_macro__fs_1__width_5 ( | |
356 | d, | |
357 | scan_in, | |
358 | l1clk, | |
359 | and_clk, | |
360 | siclk, | |
361 | soclk, | |
362 | mq, | |
363 | mq_l, | |
364 | scan_out, | |
365 | q, | |
366 | q_l); | |
367 | input [4:0] d; | |
368 | input [4:0] scan_in; | |
369 | input l1clk; | |
370 | input and_clk; | |
371 | input siclk; | |
372 | input soclk; | |
373 | output [4:0] mq; | |
374 | output [4:0] mq_l; | |
375 | output [4:0] scan_out; | |
376 | output [4:0] q; | |
377 | output [4:0] q_l; | |
378 | ||
379 | ||
380 | ||
381 | ||
382 | ||
383 | ||
384 | new_dlata #(5) d0_0 ( | |
385 | .d(d[4:0]), | |
386 | .si(scan_in[4:0]), | |
387 | .so(scan_out[4:0]), | |
388 | .l1clk(l1clk), | |
389 | .and_clk(and_clk), | |
390 | .siclk(siclk), | |
391 | .soclk(soclk), | |
392 | .q(q[4:0]), | |
393 | .q_l(q_l[4:0]), | |
394 | .mq(mq[4:0]), | |
395 | .mq_l(mq_l[4:0]) | |
396 | ); | |
397 | ||
398 | ||
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | ||
406 | ||
407 | //place::generic_place($width,$stack,$left); | |
408 | ||
409 | endmodule | |
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | // | |
416 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
417 | // | |
418 | // | |
419 | ||
420 | ||
421 | ||
422 | ||
423 | ||
424 | module n2_com_dp_32x152_cust_sram_msff_mo_macro__width_1 ( | |
425 | d, | |
426 | scan_in, | |
427 | l1clk, | |
428 | and_clk, | |
429 | siclk, | |
430 | soclk, | |
431 | mq, | |
432 | mq_l, | |
433 | scan_out, | |
434 | q, | |
435 | q_l); | |
436 | input [0:0] d; | |
437 | input scan_in; | |
438 | input l1clk; | |
439 | input and_clk; | |
440 | input siclk; | |
441 | input soclk; | |
442 | output [0:0] mq; | |
443 | output [0:0] mq_l; | |
444 | output scan_out; | |
445 | output [0:0] q; | |
446 | output [0:0] q_l; | |
447 | ||
448 | ||
449 | ||
450 | ||
451 | ||
452 | ||
453 | new_dlata #(1) d0_0 ( | |
454 | .d(d[0:0]), | |
455 | .si(scan_in), | |
456 | .so(scan_out), | |
457 | .l1clk(l1clk), | |
458 | .and_clk(and_clk), | |
459 | .siclk(siclk), | |
460 | .soclk(soclk), | |
461 | .q(q[0:0]), | |
462 | .q_l(q_l[0:0]), | |
463 | .mq(mq[0:0]), | |
464 | .mq_l(mq_l[0:0]) | |
465 | ); | |
466 | ||
467 | ||
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | ||
475 | ||
476 | //place::generic_place($width,$stack,$left); | |
477 | ||
478 | endmodule | |
479 | ||
480 | ||
481 | ||
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | // any PARAMS parms go into naming of macro | |
489 | ||
490 | module n2_com_dp_32x152_cust_msff_ctl_macro__width_1 ( | |
491 | din, | |
492 | l1clk, | |
493 | scan_in, | |
494 | siclk, | |
495 | soclk, | |
496 | dout, | |
497 | scan_out); | |
498 | wire [0:0] fdin; | |
499 | ||
500 | input [0:0] din; | |
501 | input l1clk; | |
502 | input scan_in; | |
503 | ||
504 | ||
505 | input siclk; | |
506 | input soclk; | |
507 | ||
508 | output [0:0] dout; | |
509 | output scan_out; | |
510 | assign fdin[0:0] = din[0:0]; | |
511 | ||
512 | ||
513 | ||
514 | ||
515 | ||
516 | ||
517 | dff #(1) d0_0 ( | |
518 | .l1clk(l1clk), | |
519 | .siclk(siclk), | |
520 | .soclk(soclk), | |
521 | .d(fdin[0:0]), | |
522 | .si(scan_in), | |
523 | .so(scan_out), | |
524 | .q(dout[0:0]) | |
525 | ); | |
526 | ||
527 | ||
528 | ||
529 | ||
530 | ||
531 | ||
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | endmodule | |
539 | ||
540 | ||
541 | ||
542 | ||
543 | ||
544 | ||
545 | ||
546 | ||
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | // any PARAMS parms go into naming of macro | |
553 | ||
554 | module n2_com_dp_32x152_cust_msff_ctl_macro__fs_1__width_76 ( | |
555 | din, | |
556 | l1clk, | |
557 | scan_in, | |
558 | siclk, | |
559 | soclk, | |
560 | dout, | |
561 | scan_out); | |
562 | wire [75:0] fdin; | |
563 | ||
564 | input [75:0] din; | |
565 | input l1clk; | |
566 | input [75:0] scan_in; | |
567 | ||
568 | ||
569 | input siclk; | |
570 | input soclk; | |
571 | ||
572 | output [75:0] dout; | |
573 | output [75:0] scan_out; | |
574 | assign fdin[75:0] = din[75:0]; | |
575 | ||
576 | ||
577 | ||
578 | ||
579 | ||
580 | ||
581 | dff #(76) d0_0 ( | |
582 | .l1clk(l1clk), | |
583 | .siclk(siclk), | |
584 | .soclk(soclk), | |
585 | .d(fdin[75:0]), | |
586 | .si(scan_in[75:0]), | |
587 | .so(scan_out[75:0]), | |
588 | .q(dout[75:0]) | |
589 | ); | |
590 | ||
591 | ||
592 | ||
593 | ||
594 | ||
595 | ||
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | endmodule | |
603 | ||
604 | ||
605 | ||
606 | ||
607 | ||
608 | ||
609 | ||
610 | ||
611 | ||
612 | // | |
613 | // invert macro | |
614 | // | |
615 | // | |
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | module n2_com_dp_32x152_cust_inv_macro__width_1 ( | |
622 | din, | |
623 | dout); | |
624 | input [0:0] din; | |
625 | output [0:0] dout; | |
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | inv #(1) d0_0 ( | |
633 | .in(din[0:0]), | |
634 | .out(dout[0:0]) | |
635 | ); | |
636 | ||
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | ||
643 | ||
644 | ||
645 | endmodule | |
646 | ||
647 | ||
648 | ||
649 | ||
650 | ||
651 | // | |
652 | // and macro for ports = 2,3,4 | |
653 | // | |
654 | // | |
655 | ||
656 | ||
657 | ||
658 | ||
659 | ||
660 | module n2_com_dp_32x152_cust_and_macro__width_2 ( | |
661 | din0, | |
662 | din1, | |
663 | dout); | |
664 | input [1:0] din0; | |
665 | input [1:0] din1; | |
666 | output [1:0] dout; | |
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | ||
673 | and2 #(2) d0_0 ( | |
674 | .in0(din0[1:0]), | |
675 | .in1(din1[1:0]), | |
676 | .out(dout[1:0]) | |
677 | ); | |
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | endmodule | |
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | module n2_com_dp_32x152_cust_n2_com_array_macro__rows_32__width_152__z_array ( | |
699 | rclk, | |
700 | wclk, | |
701 | rd_adr, | |
702 | rd_en, | |
703 | wr_en, | |
704 | wr_adr, | |
705 | din, | |
706 | dout); | |
707 | ||
708 | input rclk; | |
709 | input wclk; | |
710 | input [4:0] rd_adr; | |
711 | input rd_en; | |
712 | input wr_en; | |
713 | input [4:0] wr_adr; | |
714 | input [152-1:0] din; | |
715 | output [152-1:0] dout; | |
716 | ||
717 | ||
718 | ||
719 | reg [152-1:0] mem[32-1:0]; | |
720 | reg [152-1:0] local_dout; | |
721 | ||
722 | `ifndef NOINITMEM | |
723 | // Emulate reset | |
724 | integer i; | |
725 | initial begin | |
726 | for (i=0; i<32; i=i+1) begin | |
727 | mem[i] = 152'b0; | |
728 | end | |
729 | local_dout = 152'b0; | |
730 | end | |
731 | `endif | |
732 | ////////////////////// | |
733 | // Read/write array | |
734 | ////////////////////// | |
735 | always @(negedge wclk) begin | |
736 | if (wr_en) begin | |
737 | mem[wr_adr] <= din; | |
738 | ||
739 | ||
740 | end | |
741 | end | |
742 | always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin | |
743 | if (rclk) begin | |
744 | if (rd_en) begin | |
745 | if (wr_en & (wr_adr[4:0] == rd_adr[4:0])) | |
746 | local_dout[152-1:0] <= 152'hx; | |
747 | else | |
748 | local_dout[152-1:0] <= mem[rd_adr] ; | |
749 | end | |
750 | else | |
751 | local_dout[152-1:0] <= ~(152'h0); | |
752 | end | |
753 | end | |
754 | assign dout[152-1:0] = local_dout[152-1:0]; | |
755 | supply0 vss; | |
756 | supply1 vdd; | |
757 | ||
758 | ||
759 | ||
760 | ||
761 | endmodule | |
762 |