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1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_com_dp_32x82_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | `define OUTFLOP_n2_com_dp_32x82_cust TRUE | |
36 | ||
37 | ||
38 | ||
39 | // define module name here | |
40 | // ********* DON'T TOUCH NEXT LINE ********* | |
41 | module n2_com_dp_32x82_cust ( | |
42 | wr_adr, | |
43 | wr_en, | |
44 | rd_adr, | |
45 | rd_en, | |
46 | din, | |
47 | dout, | |
48 | rdclk, | |
49 | wrclk, | |
50 | scan_in, | |
51 | tcu_pce_ov, | |
52 | tcu_aclk, | |
53 | tcu_bclk, | |
54 | tcu_array_wr_inhibit, | |
55 | tcu_se_scancollar_in, | |
56 | tcu_se_scancollar_out, | |
57 | bist_clk_mux_sel, | |
58 | rd_pce, | |
59 | wr_pce, | |
60 | scan_out); | |
61 | wire rd_lce; | |
62 | wire wr_lce; | |
63 | wire rdclk_in; | |
64 | wire wrclk_in; | |
65 | wire rdclk_free; | |
66 | wire wrclk_free; | |
67 | wire rdclk_out; | |
68 | wire dff_wr_addr_scanin; | |
69 | wire dff_wr_addr_scanout; | |
70 | wire [4:0] wr_adr_d1; | |
71 | wire [4:1] dff_rd_addr_scan; | |
72 | wire dff_rd_addr_scanin; | |
73 | wire dff_rd_addr_scanout; | |
74 | wire [4:0] rd_adr_d1; | |
75 | wire [4:0] rd_adr_mq_l_unused; | |
76 | wire [4:0] rd_adr_q_unused; | |
77 | wire [4:0] rd_adr_q_l_unused; | |
78 | wire dff_rd_en_scanin; | |
79 | wire dff_rd_en_scanout; | |
80 | wire rd_en_d1; | |
81 | wire rd_en_mq_l_unused; | |
82 | wire rd_en_q_unused; | |
83 | wire rd_en_q_l_unused; | |
84 | wire dff_wr_en_scanin; | |
85 | wire dff_wr_en_scanout; | |
86 | wire wr_en_d1; | |
87 | wire [40:1] dff_din_hi_scan; | |
88 | wire dff_din_hi_scanin; | |
89 | wire dff_din_hi_scanout; | |
90 | wire [81:0] din_d1; | |
91 | wire [40:1] dff_din_lo_scan; | |
92 | wire dff_din_lo_scanin; | |
93 | wire dff_din_lo_scanout; | |
94 | wire wr_inh_; | |
95 | wire rd_en_d1_qual; | |
96 | wire wr_en_d1_qual; | |
97 | wire [81:0] local_dout; | |
98 | wire dff_dout_scanin; | |
99 | wire dff_dout_scanout; | |
100 | ||
101 | input [4:0] wr_adr; | |
102 | input wr_en; | |
103 | input [4:0] rd_adr; | |
104 | input rd_en; | |
105 | input [81:0] din; | |
106 | output [81:0] dout; | |
107 | input rdclk; | |
108 | input wrclk; | |
109 | input scan_in; | |
110 | input tcu_pce_ov; | |
111 | input tcu_aclk; | |
112 | input tcu_bclk; | |
113 | input tcu_array_wr_inhibit; | |
114 | input tcu_se_scancollar_in; | |
115 | ||
116 | input tcu_se_scancollar_out; | |
117 | ||
118 | input bist_clk_mux_sel; | |
119 | input rd_pce; | |
120 | input wr_pce; | |
121 | output scan_out; | |
122 | ||
123 | // synopsys translate_off | |
124 | ||
125 | wire pce_ov = tcu_pce_ov; | |
126 | wire siclk = tcu_aclk; | |
127 | wire soclk = tcu_bclk; | |
128 | //================================================ | |
129 | // Clock headers | |
130 | //================================================ | |
131 | cl_mc1_bistlatch_4x rd_pce_lat ( | |
132 | .l2clk (rdclk), | |
133 | .pce (rd_pce), | |
134 | .pce_ov (pce_ov), | |
135 | .lce (rd_lce) | |
136 | ); | |
137 | cl_mc1_bistlatch_4x wr_pce_lat ( | |
138 | .l2clk (wrclk), | |
139 | .pce (wr_pce), | |
140 | .pce_ov (pce_ov), | |
141 | .lce (wr_lce) | |
142 | ); | |
143 | cl_mc1_bistl1hdr_8x rch_in ( | |
144 | .l2clk (rdclk), | |
145 | .se (tcu_se_scancollar_in), | |
146 | .clksel (bist_clk_mux_sel), | |
147 | .bistclk(rdclk), | |
148 | .lce (rd_lce), | |
149 | .l1clk (rdclk_in) | |
150 | ); | |
151 | cl_mc1_bistl1hdr_8x wch_in ( | |
152 | .l2clk (wrclk), | |
153 | .se (tcu_se_scancollar_in), | |
154 | .clksel (bist_clk_mux_sel), | |
155 | .bistclk(rdclk), | |
156 | .lce (wr_lce), | |
157 | .l1clk (wrclk_in) | |
158 | ); | |
159 | cl_mc1_bistl1hdr_8x rch_free ( | |
160 | .l2clk (rdclk), | |
161 | .se (1'b0), | |
162 | .clksel (bist_clk_mux_sel), | |
163 | .bistclk(rdclk), | |
164 | .lce (rd_lce), | |
165 | .l1clk (rdclk_free) | |
166 | ); | |
167 | cl_mc1_bistl1hdr_8x wch_free ( | |
168 | .l2clk (wrclk), | |
169 | .se (1'b0), | |
170 | .clksel (bist_clk_mux_sel), | |
171 | .bistclk(rdclk), | |
172 | .lce (wr_lce), | |
173 | .l1clk (wrclk_free) | |
174 | ); | |
175 | ||
176 | cl_mc1_bistl1hdr_8x rch_out ( | |
177 | .l2clk (rdclk), | |
178 | .se (tcu_se_scancollar_out), | |
179 | .clksel (bist_clk_mux_sel), | |
180 | .bistclk(rdclk), | |
181 | .lce (rd_lce), | |
182 | .l1clk (rdclk_out) | |
183 | ); | |
184 | ||
185 | /////////////////////////////////////////////////////////////// | |
186 | // Flop the inputs // | |
187 | /////////////////////////////////////////////////////////////// | |
188 | n2_com_dp_32x82_cust_msff_ctl_macro__width_5 dff_wr_addr ( | |
189 | .scan_in (dff_wr_addr_scanin), | |
190 | .scan_out (dff_wr_addr_scanout), | |
191 | .l1clk (wrclk_in), | |
192 | .din (wr_adr[4:0]), | |
193 | .dout (wr_adr_d1[4:0]), | |
194 | .siclk(siclk), | |
195 | .soclk(soclk) | |
196 | ); | |
197 | n2_com_dp_32x82_cust_sram_msff_mo_macro__fs_1__width_5 dff_rd_addr ( | |
198 | .scan_in ({dff_rd_addr_scan[4:1],dff_rd_addr_scanin}), | |
199 | .scan_out ({dff_rd_addr_scanout,dff_rd_addr_scan[4:1]}), | |
200 | .l1clk (rdclk_in), | |
201 | .and_clk (rdclk_in), | |
202 | .d (rd_adr[4:0]), | |
203 | .mq (rd_adr_d1[4:0]), | |
204 | .mq_l (rd_adr_mq_l_unused[4:0]), | |
205 | .q (rd_adr_q_unused[4:0]), | |
206 | .q_l (rd_adr_q_l_unused[4:0]), | |
207 | .siclk(siclk), | |
208 | .soclk(soclk) | |
209 | ); | |
210 | n2_com_dp_32x82_cust_sram_msff_mo_macro__width_1 dff_rd_en ( | |
211 | .scan_in (dff_rd_en_scanin), | |
212 | .scan_out (dff_rd_en_scanout), | |
213 | .l1clk (rdclk_in), | |
214 | .and_clk (rdclk_in), | |
215 | .d (rd_en), | |
216 | .mq (rd_en_d1), | |
217 | .mq_l (rd_en_mq_l_unused), | |
218 | .q (rd_en_q_unused), | |
219 | .q_l (rd_en_q_l_unused), | |
220 | .siclk(siclk), | |
221 | .soclk(soclk) | |
222 | ); | |
223 | n2_com_dp_32x82_cust_msff_ctl_macro__width_1 dff_wr_en ( | |
224 | .scan_in (dff_wr_en_scanin), | |
225 | .scan_out (dff_wr_en_scanout), | |
226 | .l1clk (wrclk_in), | |
227 | .din (wr_en), | |
228 | .dout (wr_en_d1), | |
229 | .siclk(siclk), | |
230 | .soclk(soclk) | |
231 | ); | |
232 | n2_com_dp_32x82_cust_msff_ctl_macro__fs_1__width_41 dff_din_hi ( | |
233 | .scan_in ({dff_din_hi_scan[40:1],dff_din_hi_scanin}), | |
234 | .scan_out ({dff_din_hi_scanout,dff_din_hi_scan[40:1]}), | |
235 | .l1clk (wrclk_in), | |
236 | .din (din[81:41]), | |
237 | .dout (din_d1[81:41]), | |
238 | .siclk(siclk), | |
239 | .soclk(soclk) | |
240 | ); | |
241 | n2_com_dp_32x82_cust_msff_ctl_macro__fs_1__width_41 dff_din_lo ( | |
242 | .scan_in ({dff_din_lo_scan[40:1],dff_din_lo_scanin}), | |
243 | .scan_out ({dff_din_lo_scanout,dff_din_lo_scan[40:1]}), | |
244 | .l1clk (wrclk_in), | |
245 | .din (din[40:0]), | |
246 | .dout (din_d1[40:0]), | |
247 | .siclk(siclk), | |
248 | .soclk(soclk) | |
249 | ); | |
250 | n2_com_dp_32x82_cust_inv_macro__width_1 wr_inh_inv ( | |
251 | .din (tcu_array_wr_inhibit), | |
252 | .dout (wr_inh_) | |
253 | ); | |
254 | n2_com_dp_32x82_cust_and_macro__width_2 enable_qual ( | |
255 | .din0 ({2{wr_inh_}}), | |
256 | .din1 ({rd_en_d1,wr_en_d1}), | |
257 | .dout ({rd_en_d1_qual,wr_en_d1_qual}) | |
258 | ); | |
259 | n2_com_dp_32x82_cust_n2_com_array_macro__rows_32__width_82__z_array array ( | |
260 | .rclk (rdclk_free), | |
261 | .wclk (wrclk_free), | |
262 | .wr_adr (wr_adr_d1[4:0]), | |
263 | .wr_en (wr_en_d1_qual), | |
264 | .rd_adr (rd_adr_d1[4:0]), | |
265 | .rd_en (rd_en_d1_qual), | |
266 | .din (din_d1[81:0]), | |
267 | .dout (local_dout[81:0]) | |
268 | ); | |
269 | ||
270 | n2_com_dp_32x82_cust_msff_ctl_macro__width_82 dff_dout ( | |
271 | .scan_in (dff_dout_scanin), | |
272 | .scan_out (dff_dout_scanout), | |
273 | .l1clk (rdclk_out), | |
274 | .din (local_dout[81:0]), | |
275 | .dout (dout[81:0]), | |
276 | .siclk(siclk), | |
277 | .soclk(soclk) | |
278 | ); | |
279 | ||
280 | ||
281 | supply0 vss; | |
282 | supply1 vdd; | |
283 | ||
284 | // fixscan start: | |
285 | assign dff_wr_addr_scanin = scan_in ; | |
286 | assign dff_rd_addr_scanin = dff_wr_addr_scanout ; | |
287 | assign dff_wr_en_scanin = dff_rd_addr_scanout ; | |
288 | assign dff_rd_en_scanin = dff_wr_en_scanout ; | |
289 | assign dff_din_lo_scanin = dff_rd_en_scanout ; | |
290 | assign dff_din_hi_scanin = dff_din_lo_scanout ; | |
291 | assign dff_dout_scanin = dff_din_hi_scanout ; | |
292 | assign scan_out = dff_dout_scanout ; | |
293 | // fixscan end: | |
294 | ||
295 | ||
296 | // synopsys translate_on | |
297 | ||
298 | endmodule | |
299 | ||
300 | ||
301 | ||
302 | ||
303 | ||
304 | ||
305 | ||
306 | // any PARAMS parms go into naming of macro | |
307 | ||
308 | module n2_com_dp_32x82_cust_msff_ctl_macro__width_5 ( | |
309 | din, | |
310 | l1clk, | |
311 | scan_in, | |
312 | siclk, | |
313 | soclk, | |
314 | dout, | |
315 | scan_out); | |
316 | wire [4:0] fdin; | |
317 | wire [3:0] so; | |
318 | ||
319 | input [4:0] din; | |
320 | input l1clk; | |
321 | input scan_in; | |
322 | ||
323 | ||
324 | input siclk; | |
325 | input soclk; | |
326 | ||
327 | output [4:0] dout; | |
328 | output scan_out; | |
329 | assign fdin[4:0] = din[4:0]; | |
330 | ||
331 | ||
332 | ||
333 | ||
334 | ||
335 | ||
336 | dff #(5) d0_0 ( | |
337 | .l1clk(l1clk), | |
338 | .siclk(siclk), | |
339 | .soclk(soclk), | |
340 | .d(fdin[4:0]), | |
341 | .si({scan_in,so[3:0]}), | |
342 | .so({so[3:0],scan_out}), | |
343 | .q(dout[4:0]) | |
344 | ); | |
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | ||
356 | ||
357 | endmodule | |
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | // | |
368 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
369 | // | |
370 | // | |
371 | ||
372 | ||
373 | ||
374 | ||
375 | ||
376 | module n2_com_dp_32x82_cust_sram_msff_mo_macro__fs_1__width_5 ( | |
377 | d, | |
378 | scan_in, | |
379 | l1clk, | |
380 | and_clk, | |
381 | siclk, | |
382 | soclk, | |
383 | mq, | |
384 | mq_l, | |
385 | scan_out, | |
386 | q, | |
387 | q_l); | |
388 | input [4:0] d; | |
389 | input [4:0] scan_in; | |
390 | input l1clk; | |
391 | input and_clk; | |
392 | input siclk; | |
393 | input soclk; | |
394 | output [4:0] mq; | |
395 | output [4:0] mq_l; | |
396 | output [4:0] scan_out; | |
397 | output [4:0] q; | |
398 | output [4:0] q_l; | |
399 | ||
400 | ||
401 | ||
402 | ||
403 | ||
404 | ||
405 | new_dlata #(5) d0_0 ( | |
406 | .d(d[4:0]), | |
407 | .si(scan_in[4:0]), | |
408 | .so(scan_out[4:0]), | |
409 | .l1clk(l1clk), | |
410 | .and_clk(and_clk), | |
411 | .siclk(siclk), | |
412 | .soclk(soclk), | |
413 | .q(q[4:0]), | |
414 | .q_l(q_l[4:0]), | |
415 | .mq(mq[4:0]), | |
416 | .mq_l(mq_l[4:0]) | |
417 | ); | |
418 | ||
419 | ||
420 | ||
421 | ||
422 | ||
423 | ||
424 | ||
425 | ||
426 | ||
427 | ||
428 | //place::generic_place($width,$stack,$left); | |
429 | ||
430 | endmodule | |
431 | ||
432 | ||
433 | ||
434 | ||
435 | ||
436 | // | |
437 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
438 | // | |
439 | // | |
440 | ||
441 | ||
442 | ||
443 | ||
444 | ||
445 | module n2_com_dp_32x82_cust_sram_msff_mo_macro__width_1 ( | |
446 | d, | |
447 | scan_in, | |
448 | l1clk, | |
449 | and_clk, | |
450 | siclk, | |
451 | soclk, | |
452 | mq, | |
453 | mq_l, | |
454 | scan_out, | |
455 | q, | |
456 | q_l); | |
457 | input [0:0] d; | |
458 | input scan_in; | |
459 | input l1clk; | |
460 | input and_clk; | |
461 | input siclk; | |
462 | input soclk; | |
463 | output [0:0] mq; | |
464 | output [0:0] mq_l; | |
465 | output scan_out; | |
466 | output [0:0] q; | |
467 | output [0:0] q_l; | |
468 | ||
469 | ||
470 | ||
471 | ||
472 | ||
473 | ||
474 | new_dlata #(1) d0_0 ( | |
475 | .d(d[0:0]), | |
476 | .si(scan_in), | |
477 | .so(scan_out), | |
478 | .l1clk(l1clk), | |
479 | .and_clk(and_clk), | |
480 | .siclk(siclk), | |
481 | .soclk(soclk), | |
482 | .q(q[0:0]), | |
483 | .q_l(q_l[0:0]), | |
484 | .mq(mq[0:0]), | |
485 | .mq_l(mq_l[0:0]) | |
486 | ); | |
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | ||
493 | ||
494 | ||
495 | ||
496 | ||
497 | //place::generic_place($width,$stack,$left); | |
498 | ||
499 | endmodule | |
500 | ||
501 | ||
502 | ||
503 | ||
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | // any PARAMS parms go into naming of macro | |
510 | ||
511 | module n2_com_dp_32x82_cust_msff_ctl_macro__width_1 ( | |
512 | din, | |
513 | l1clk, | |
514 | scan_in, | |
515 | siclk, | |
516 | soclk, | |
517 | dout, | |
518 | scan_out); | |
519 | wire [0:0] fdin; | |
520 | ||
521 | input [0:0] din; | |
522 | input l1clk; | |
523 | input scan_in; | |
524 | ||
525 | ||
526 | input siclk; | |
527 | input soclk; | |
528 | ||
529 | output [0:0] dout; | |
530 | output scan_out; | |
531 | assign fdin[0:0] = din[0:0]; | |
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | dff #(1) d0_0 ( | |
539 | .l1clk(l1clk), | |
540 | .siclk(siclk), | |
541 | .soclk(soclk), | |
542 | .d(fdin[0:0]), | |
543 | .si(scan_in), | |
544 | .so(scan_out), | |
545 | .q(dout[0:0]) | |
546 | ); | |
547 | ||
548 | ||
549 | ||
550 | ||
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | endmodule | |
560 | ||
561 | ||
562 | ||
563 | ||
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | // any PARAMS parms go into naming of macro | |
574 | ||
575 | module n2_com_dp_32x82_cust_msff_ctl_macro__fs_1__width_41 ( | |
576 | din, | |
577 | l1clk, | |
578 | scan_in, | |
579 | siclk, | |
580 | soclk, | |
581 | dout, | |
582 | scan_out); | |
583 | wire [40:0] fdin; | |
584 | ||
585 | input [40:0] din; | |
586 | input l1clk; | |
587 | input [40:0] scan_in; | |
588 | ||
589 | ||
590 | input siclk; | |
591 | input soclk; | |
592 | ||
593 | output [40:0] dout; | |
594 | output [40:0] scan_out; | |
595 | assign fdin[40:0] = din[40:0]; | |
596 | ||
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | dff #(41) d0_0 ( | |
603 | .l1clk(l1clk), | |
604 | .siclk(siclk), | |
605 | .soclk(soclk), | |
606 | .d(fdin[40:0]), | |
607 | .si(scan_in[40:0]), | |
608 | .so(scan_out[40:0]), | |
609 | .q(dout[40:0]) | |
610 | ); | |
611 | ||
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | endmodule | |
624 | ||
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | // | |
634 | // invert macro | |
635 | // | |
636 | // | |
637 | ||
638 | ||
639 | ||
640 | ||
641 | ||
642 | module n2_com_dp_32x82_cust_inv_macro__width_1 ( | |
643 | din, | |
644 | dout); | |
645 | input [0:0] din; | |
646 | output [0:0] dout; | |
647 | ||
648 | ||
649 | ||
650 | ||
651 | ||
652 | ||
653 | inv #(1) d0_0 ( | |
654 | .in(din[0:0]), | |
655 | .out(dout[0:0]) | |
656 | ); | |
657 | ||
658 | ||
659 | ||
660 | ||
661 | ||
662 | ||
663 | ||
664 | ||
665 | ||
666 | endmodule | |
667 | ||
668 | ||
669 | ||
670 | ||
671 | ||
672 | // | |
673 | // and macro for ports = 2,3,4 | |
674 | // | |
675 | // | |
676 | ||
677 | ||
678 | ||
679 | ||
680 | ||
681 | module n2_com_dp_32x82_cust_and_macro__width_2 ( | |
682 | din0, | |
683 | din1, | |
684 | dout); | |
685 | input [1:0] din0; | |
686 | input [1:0] din1; | |
687 | output [1:0] dout; | |
688 | ||
689 | ||
690 | ||
691 | ||
692 | ||
693 | ||
694 | and2 #(2) d0_0 ( | |
695 | .in0(din0[1:0]), | |
696 | .in1(din1[1:0]), | |
697 | .out(dout[1:0]) | |
698 | ); | |
699 | ||
700 | ||
701 | ||
702 | ||
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | endmodule | |
709 | ||
710 | ||
711 | ||
712 | ||
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | module n2_com_dp_32x82_cust_n2_com_array_macro__rows_32__width_82__z_array ( | |
720 | rclk, | |
721 | wclk, | |
722 | rd_adr, | |
723 | rd_en, | |
724 | wr_en, | |
725 | wr_adr, | |
726 | din, | |
727 | dout); | |
728 | ||
729 | input rclk; | |
730 | input wclk; | |
731 | input [4:0] rd_adr; | |
732 | input rd_en; | |
733 | input wr_en; | |
734 | input [4:0] wr_adr; | |
735 | input [82-1:0] din; | |
736 | output [82-1:0] dout; | |
737 | ||
738 | ||
739 | ||
740 | reg [82-1:0] mem[32-1:0]; | |
741 | reg [82-1:0] local_dout; | |
742 | ||
743 | `ifndef NOINITMEM | |
744 | // Emulate reset | |
745 | integer i; | |
746 | initial begin | |
747 | for (i=0; i<32; i=i+1) begin | |
748 | mem[i] = 82'b0; | |
749 | end | |
750 | local_dout = 82'b0; | |
751 | end | |
752 | `endif | |
753 | ////////////////////// | |
754 | // Read/write array | |
755 | ////////////////////// | |
756 | always @(negedge wclk) begin | |
757 | if (wr_en) begin | |
758 | mem[wr_adr] <= din; | |
759 | ||
760 | ||
761 | end | |
762 | end | |
763 | always @(rclk or rd_en or wr_en or rd_adr or wr_adr) begin | |
764 | if (rclk) begin | |
765 | if (rd_en) begin | |
766 | if (wr_en & (wr_adr[4:0] == rd_adr[4:0])) | |
767 | local_dout[82-1:0] <= 82'hx; | |
768 | else | |
769 | local_dout[82-1:0] <= mem[rd_adr] ; | |
770 | end | |
771 | else | |
772 | local_dout[82-1:0] <= ~(82'h0); | |
773 | end | |
774 | end | |
775 | assign dout[82-1:0] = local_dout[82-1:0]; | |
776 | supply0 vss; | |
777 | supply1 vdd; | |
778 | ||
779 | ||
780 | ||
781 | ||
782 | endmodule | |
783 | ||
784 | ||
785 | ||
786 | ||
787 | ||
788 | ||
789 | // any PARAMS parms go into naming of macro | |
790 | ||
791 | module n2_com_dp_32x82_cust_msff_ctl_macro__width_82 ( | |
792 | din, | |
793 | l1clk, | |
794 | scan_in, | |
795 | siclk, | |
796 | soclk, | |
797 | dout, | |
798 | scan_out); | |
799 | wire [81:0] fdin; | |
800 | wire [80:0] so; | |
801 | ||
802 | input [81:0] din; | |
803 | input l1clk; | |
804 | input scan_in; | |
805 | ||
806 | ||
807 | input siclk; | |
808 | input soclk; | |
809 | ||
810 | output [81:0] dout; | |
811 | output scan_out; | |
812 | assign fdin[81:0] = din[81:0]; | |
813 | ||
814 | ||
815 | ||
816 | ||
817 | ||
818 | ||
819 | dff #(82) d0_0 ( | |
820 | .l1clk(l1clk), | |
821 | .siclk(siclk), | |
822 | .soclk(soclk), | |
823 | .d(fdin[81:0]), | |
824 | .si({scan_in,so[80:0]}), | |
825 | .so({so[80:0],scan_out}), | |
826 | .q(dout[81:0]) | |
827 | ); | |
828 | ||
829 | ||
830 | ||
831 | ||
832 | ||
833 | ||
834 | ||
835 | ||
836 | ||
837 | ||
838 | ||
839 | ||
840 | endmodule | |
841 | ||
842 | ||
843 | ||
844 | ||
845 | ||
846 | ||
847 | ||
848 |