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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_dmu_dp_128x132s_cust_l / n2_dmu_dp_128x132s_cust / rtl / n2_dmu_dp_128x132s_cust.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_dmu_dp_128x132s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_dmu_dp_128x132s_cust (
36 // clocks, scan
37 clk,
38 scan_in,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_pce_ov,
42 pce,
43 tcu_aclk,
44 tcu_bclk,
45 tcu_array_wr_inhibit,
46 scan_out,
47
48 // ram control
49 rd_addr,
50 wr_addr,
51 rd_en,
52 wr_en,
53 din,
54 dout
55
56);
57
58
59
60
61 // clocks, scan
62 input clk; // io clock
63 input scan_in; //
64 input tcu_scan_en; //
65 input tcu_se_scancollar_in; //
66 input tcu_pce_ov; // scan signals
67 input pce; //
68 input tcu_aclk; //
69 input tcu_bclk; //
70 input tcu_array_wr_inhibit; //
71 output scan_out; //
72
73
74 //
75 input [6:0] rd_addr; // a port address in
76 input [6:0] wr_addr; // b port address in
77 input rd_en; // a port enable
78 input wr_en; // b port write enable
79 input [131:0] din; // data in
80 output [131:0] dout; // data out
81
82
83 //------------------------------------------------------------------------
84 // scan chain connections
85 //------------------------------------------------------------------------
86// scan renames
87wire [3:0] siclk,soclk;
88wire se,wr_inhibit_array,and_clk;
89assign wr_inhibit_array = tcu_array_wr_inhibit;
90// end scan
91 //------------------------------------------------------------------------
92 // instantiate clock headers
93 //------------------------------------------------------------------------
94wire [3:0] collar_clk;
95wire pce_ov = tcu_pce_ov;
96wire stop = 1'b0;
97wire aclk = tcu_aclk;
98wire bclk = tcu_bclk;
99assign se = tcu_se_scancollar_in; // TEMP
100
101cl_dp1_l1hdr_8x clk_hdr_cntl (
102 .l2clk(clk),
103 .pce (pce),
104 .l1clk(collar_clk[0]),
105 .siclk_out(siclk[0]),
106 .soclk_out(soclk[0]),
107 .se(se),
108 .pce_ov(pce_ov),
109 .stop(stop),
110 .aclk(aclk),
111 .bclk(bclk)
112);
113
114cl_dp1_l1hdr_8x clk_hdr_data1 (
115 .l2clk(clk),
116 .pce (pce),
117 .l1clk(collar_clk[1]),
118 .siclk_out(siclk[1]),
119 .soclk_out(soclk[1]),
120 .se(se),
121 .pce_ov(pce_ov),
122 .stop(stop),
123 .aclk(aclk),
124 .bclk(bclk)
125);
126
127cl_dp1_l1hdr_8x clk_hdr_data2 (
128 .l2clk(clk),
129 .pce (pce),
130 .l1clk(collar_clk[2]),
131 .siclk_out(siclk[2]),
132 .soclk_out(soclk[2]),
133 .se(se),
134 .pce_ov(pce_ov),
135 .stop(stop),
136 .aclk(aclk),
137 .bclk(bclk)
138);
139
140cl_dp1_l1hdr_8x clk_hdr_data3 (
141 .l2clk(clk),
142 .pce (pce),
143 .l1clk(collar_clk[3]),
144 .siclk_out(siclk[3]),
145 .soclk_out(soclk[3]),
146 .se(se),
147 .pce_ov(pce_ov),
148 .stop(stop),
149 .aclk(aclk),
150 .bclk(bclk)
151);
152
153cl_dp1_l1hdr_8x scan_dn_hdr (
154 .l2clk(clk),
155 .pce (pce),
156 .l1clk(and_clk),
157 .siclk_out(),
158 .soclk_out(),
159 .se(tcu_scan_en),
160 .pce_ov(pce_ov),
161 .stop(stop),
162 .aclk(aclk),
163 .bclk(bclk)
164);
165
166 //------------------------------------------------------------------------
167 // input flops
168 //------------------------------------------------------------------------
169
170wire [6:0] rd_addr_array,rd_addr_so;
171wire [6:0] wr_addr_array,wr_addr_so;
172wire rd_en_array,wr_en_array;
173wire rd_en_so;
174wire wr_en_so;
175wire [131:0] din_array,din_so;
176wire [131:0] s_int;
177
178
179
180cl_sc1_msff_4x din_131 ( .si(scan_in), .so(s_int[131]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[131]), .q(din_array[131]) );
181cl_sc1_msff_4x din_130 ( .si(s_int[131]), .so(s_int[130]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[130]), .q(din_array[130]) );
182
183cl_sc1_msff_4x din_129 ( .si(s_int[130]), .so(s_int[129]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[129]), .q(din_array[129]) );
184cl_sc1_msff_4x din_128 ( .si(s_int[129]), .so(s_int[128]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[128]), .q(din_array[128]) );
185cl_sc1_msff_4x din_127 ( .si(s_int[128]), .so(s_int[127]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[127]), .q(din_array[127]) );
186cl_sc1_msff_4x din_126 ( .si(s_int[127]), .so(s_int[126]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[126]), .q(din_array[126]) );
187cl_sc1_msff_4x din_125 ( .si(s_int[126]), .so(s_int[125]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[125]), .q(din_array[125]) );
188cl_sc1_msff_4x din_124 ( .si(s_int[125]), .so(s_int[124]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[124]), .q(din_array[124]) );
189cl_sc1_msff_4x din_123 ( .si(s_int[124]), .so(s_int[123]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[123]), .q(din_array[123]) );
190cl_sc1_msff_4x din_122 ( .si(s_int[123]), .so(s_int[122]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[122]), .q(din_array[122]) );
191cl_sc1_msff_4x din_121 ( .si(s_int[122]), .so(s_int[121]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[121]), .q(din_array[121]) );
192cl_sc1_msff_4x din_120 ( .si(s_int[121]), .so(s_int[120]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[120]), .q(din_array[120]) );
193
194cl_sc1_msff_4x din_119 ( .si(s_int[120]), .so(s_int[119]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[119]), .q(din_array[119]) );
195cl_sc1_msff_4x din_118 ( .si(s_int[119]), .so(s_int[118]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[118]), .q(din_array[118]) );
196cl_sc1_msff_4x din_117 ( .si(s_int[118]), .so(s_int[117]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[117]), .q(din_array[117]) );
197cl_sc1_msff_4x din_116 ( .si(s_int[117]), .so(s_int[116]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[116]), .q(din_array[116]) );
198cl_sc1_msff_4x din_115 ( .si(s_int[116]), .so(s_int[115]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[115]), .q(din_array[115]) );
199cl_sc1_msff_4x din_114 ( .si(s_int[115]), .so(s_int[114]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[114]), .q(din_array[114]) );
200cl_sc1_msff_4x din_113 ( .si(s_int[114]), .so(s_int[113]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[113]), .q(din_array[113]) );
201cl_sc1_msff_4x din_112 ( .si(s_int[113]), .so(s_int[112]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[112]), .q(din_array[112]) );
202cl_sc1_msff_4x din_111 ( .si(s_int[112]), .so(s_int[111]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[111]), .q(din_array[111]) );
203cl_sc1_msff_4x din_110 ( .si(s_int[111]), .so(s_int[110]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[110]), .q(din_array[110]) );
204
205cl_sc1_msff_4x din_109 ( .si(s_int[110]), .so(s_int[109]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[109]), .q(din_array[109]) );
206cl_sc1_msff_4x din_108 ( .si(s_int[109]), .so(s_int[108]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[108]), .q(din_array[108]) );
207cl_sc1_msff_4x din_107 ( .si(s_int[108]), .so(s_int[107]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[107]), .q(din_array[107]) );
208cl_sc1_msff_4x din_106 ( .si(s_int[107]), .so(s_int[106]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[106]), .q(din_array[106]) );
209cl_sc1_msff_4x din_105 ( .si(s_int[106]), .so(s_int[105]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[105]), .q(din_array[105]) );
210cl_sc1_msff_4x din_104 ( .si(s_int[105]), .so(s_int[104]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[104]), .q(din_array[104]) );
211cl_sc1_msff_4x din_103 ( .si(s_int[104]), .so(s_int[103]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[103]), .q(din_array[103]) );
212cl_sc1_msff_4x din_102 ( .si(s_int[103]), .so(s_int[102]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[102]), .q(din_array[102]) );
213cl_sc1_msff_4x din_101 ( .si(s_int[102]), .so(s_int[101]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[101]), .q(din_array[101]) );
214cl_sc1_msff_4x din_100 ( .si(s_int[101]), .so(s_int[100]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[100]), .q(din_array[100]) );
215
216cl_sc1_msff_4x din_99 ( .si(s_int[100]), .so(s_int[99]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[99]), .q(din_array[99]) );
217cl_sc1_msff_4x din_98 ( .si(s_int[99]), .so(s_int[98]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[98]), .q(din_array[98]) );
218cl_sc1_msff_4x din_97 ( .si(s_int[98]), .so(s_int[97]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[97]), .q(din_array[97]) );
219cl_sc1_msff_4x din_96 ( .si(s_int[97]), .so(s_int[96]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[96]), .q(din_array[96]) );
220cl_sc1_msff_4x din_95 ( .si(s_int[96]), .so(s_int[95]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[95]), .q(din_array[95]) );
221cl_sc1_msff_4x din_94 ( .si(s_int[95]), .so(s_int[94]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[94]), .q(din_array[94]) );
222cl_sc1_msff_4x din_93 ( .si(s_int[94]), .so(s_int[93]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[93]), .q(din_array[93]) );
223cl_sc1_msff_4x din_92 ( .si(s_int[93]), .so(s_int[92]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[92]), .q(din_array[92]) );
224cl_sc1_msff_4x din_91 ( .si(s_int[92]), .so(s_int[91]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[91]), .q(din_array[91]) );
225cl_sc1_msff_4x din_90 ( .si(s_int[91]), .so(s_int[90]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[90]), .q(din_array[90]) );
226
227cl_sc1_msff_4x din_89 ( .si(s_int[90]), .so(s_int[89]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[89]), .q(din_array[89]) );
228cl_sc1_msff_4x din_88 ( .si(s_int[89]), .so(s_int[88]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[88]), .q(din_array[88]) );
229cl_sc1_msff_4x din_87 ( .si(s_int[88]), .so(s_int[87]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[87]), .q(din_array[87]) );
230cl_sc1_msff_4x din_86 ( .si(s_int[87]), .so(s_int[86]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[86]), .q(din_array[86]) );
231cl_sc1_msff_4x din_85 ( .si(s_int[86]), .so(s_int[85]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[85]), .q(din_array[85]) );
232cl_sc1_msff_4x din_84 ( .si(s_int[85]), .so(s_int[84]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[84]), .q(din_array[84]) );
233cl_sc1_msff_4x din_83 ( .si(s_int[84]), .so(s_int[83]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[83]), .q(din_array[83]) );
234cl_sc1_msff_4x din_82 ( .si(s_int[83]), .so(s_int[82]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[82]), .q(din_array[82]) );
235cl_sc1_msff_4x din_81 ( .si(s_int[82]), .so(s_int[81]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[81]), .q(din_array[81]) );
236cl_sc1_msff_4x din_80 ( .si(s_int[81]), .so(s_int[80]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[80]), .q(din_array[80]) );
237
238cl_sc1_msff_4x din_79 ( .si(s_int[80]), .so(s_int[79]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[79]), .q(din_array[79]) );
239cl_sc1_msff_4x din_78 ( .si(s_int[79]), .so(s_int[78]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[78]), .q(din_array[78]) );
240cl_sc1_msff_4x din_77 ( .si(s_int[78]), .so(s_int[77]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[77]), .q(din_array[77]) );
241cl_sc1_msff_4x din_76 ( .si(s_int[77]), .so(s_int[76]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[76]), .q(din_array[76]) );
242cl_sc1_msff_4x din_75 ( .si(s_int[76]), .so(s_int[75]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[75]), .q(din_array[75]) );
243cl_sc1_msff_4x din_74 ( .si(s_int[75]), .so(s_int[74]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[74]), .q(din_array[74]) );
244cl_sc1_msff_4x din_73 ( .si(s_int[74]), .so(s_int[73]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[73]), .q(din_array[73]) );
245cl_sc1_msff_4x din_72 ( .si(s_int[73]), .so(s_int[72]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[72]), .q(din_array[72]) );
246cl_sc1_msff_4x din_71 ( .si(s_int[72]), .so(s_int[71]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[71]), .q(din_array[71]) );
247cl_sc1_msff_4x din_70 ( .si(s_int[71]), .so(s_int[70]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[70]), .q(din_array[70]) );
248
249cl_sc1_msff_4x din_69 ( .si(s_int[70]), .so(s_int[69]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[69]), .q(din_array[69]) );
250cl_sc1_msff_4x din_68 ( .si(s_int[69]), .so(s_int[68]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[68]), .q(din_array[68]) );
251cl_sc1_msff_4x din_67 ( .si(s_int[68]), .so(s_int[67]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[67]), .q(din_array[67]) );
252cl_sc1_msff_4x din_66 ( .si(s_int[67]), .so(s_int[66]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[66]), .q(din_array[66]) );
253
254
255cl_mc1_sram_msff_mo_8x ff_rd_en ( .si(s_int[66]), .so(rd_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
256 .d(rd_en), .mq(rd_en_array), .and_clk(and_clk) );
257
258
259
260
261cl_mc1_sram_msff_mo_8x rd_addr_so_6 ( .si(rd_en_so), .so(rd_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
262 .d(rd_addr[6]), .mq(rd_addr_array[6]), .and_clk(and_clk) );
263
264cl_mc1_sram_msff_mo_8x rd_addr_so_5 ( .si(rd_addr_so[6]), .so(rd_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
265 .d(rd_addr[5]), .mq(rd_addr_array[5]), .and_clk(and_clk) );
266cl_mc1_sram_msff_mo_8x rd_addr_so_4 ( .si(rd_addr_so[5]), .so(rd_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
267 .d(rd_addr[4]), .mq(rd_addr_array[4]), .and_clk(and_clk) );
268cl_mc1_sram_msff_mo_8x rd_addr_so_3 ( .si(rd_addr_so[4]), .so(rd_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
269 .d(rd_addr[3]), .mq(rd_addr_array[3]),.and_clk(and_clk) );
270cl_mc1_sram_msff_mo_8x rd_addr_so_2 ( .si(rd_addr_so[3]), .so(rd_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
271 .d(rd_addr[2]), .mq(rd_addr_array[2]),.and_clk(and_clk) );
272cl_mc1_sram_msff_mo_8x rd_addr_so_1 ( .si(rd_addr_so[2]), .so(rd_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
273 .d(rd_addr[1]), .mq(rd_addr_array[1]),.and_clk(and_clk) );
274cl_mc1_sram_msff_mo_8x rd_addr_so_0 ( .si(rd_addr_so[1]), .so(rd_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
275 .d(rd_addr[0]), .mq(rd_addr_array[0]),.and_clk(and_clk) );
276
277
278
279
280
281cl_sc1_msff_8x ff_wr_en ( .si(rd_addr_so[0]), .so(wr_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
282 .d(wr_en), .q(wr_en_array) );
283
284cl_sc1_msff_8x wr_addr_so_6 ( .si(wr_en_so), .so(wr_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
285 .d(wr_addr[6]), .q(wr_addr_array[6]) );
286cl_sc1_msff_8x wr_addr_so_5 ( .si(wr_addr_so[6]), .so(wr_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
287 .d(wr_addr[5]), .q(wr_addr_array[5]) );
288cl_sc1_msff_8x wr_addr_so_4 ( .si(wr_addr_so[5]), .so(wr_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
289 .d(wr_addr[4]), .q(wr_addr_array[4]) );
290cl_sc1_msff_8x wr_addr_so_3 ( .si(wr_addr_so[4]), .so(wr_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
291 .d(wr_addr[3]), .q(wr_addr_array[3]) );
292cl_sc1_msff_8x wr_addr_so_2 ( .si(wr_addr_so[3]), .so(wr_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
293 .d(wr_addr[2]), .q(wr_addr_array[2]) );
294cl_sc1_msff_8x wr_addr_so_1 ( .si(wr_addr_so[2]), .so(wr_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
295 .d(wr_addr[1]), .q(wr_addr_array[1]) );
296cl_sc1_msff_8x wr_addr_so_0 ( .si(wr_addr_so[1]), .so(si_din), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
297 .d(wr_addr[0]), .q(wr_addr_array[0]) );
298
299
300
301
302
303
304
305
306
307
308cl_sc1_msff_4x din_65 ( .si(si_din), .so(s_int[65]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[65]), .q(din_array[65]) );
309cl_sc1_msff_4x din_64 ( .si(s_int[65]), .so(s_int[64]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[64]), .q(din_array[64]) );
310cl_sc1_msff_4x din_63 ( .si(s_int[64]), .so(s_int[63]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[63]), .q(din_array[63]) );
311cl_sc1_msff_4x din_62 ( .si(s_int[63]), .so(s_int[62]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[62]), .q(din_array[62]) );
312cl_sc1_msff_4x din_61 ( .si(s_int[62]), .so(s_int[61]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[61]), .q(din_array[61]) );
313cl_sc1_msff_4x din_60 ( .si(s_int[61]), .so(s_int[60]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[60]), .q(din_array[60]) );
314
315cl_sc1_msff_4x din_59 ( .si(s_int[60]), .so(s_int[59]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[59]), .q(din_array[59]) );
316cl_sc1_msff_4x din_58 ( .si(s_int[59]), .so(s_int[58]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[58]), .q(din_array[58]) );
317cl_sc1_msff_4x din_57 ( .si(s_int[58]), .so(s_int[57]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[57]), .q(din_array[57]) );
318cl_sc1_msff_4x din_56 ( .si(s_int[57]), .so(s_int[56]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[56]), .q(din_array[56]) );
319cl_sc1_msff_4x din_55 ( .si(s_int[56]), .so(s_int[55]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[55]), .q(din_array[55]) );
320cl_sc1_msff_4x din_54 ( .si(s_int[55]), .so(s_int[54]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[54]), .q(din_array[54]) );
321cl_sc1_msff_4x din_53 ( .si(s_int[54]), .so(s_int[53]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[53]), .q(din_array[53]) );
322cl_sc1_msff_4x din_52 ( .si(s_int[53]), .so(s_int[52]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[52]), .q(din_array[52]) );
323cl_sc1_msff_4x din_51 ( .si(s_int[52]), .so(s_int[51]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[51]), .q(din_array[51]) );
324cl_sc1_msff_4x din_50 ( .si(s_int[51]), .so(s_int[50]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[50]), .q(din_array[50]) );
325
326cl_sc1_msff_4x din_49 ( .si(s_int[50]), .so(s_int[49]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[49]), .q(din_array[49]) );
327cl_sc1_msff_4x din_48 ( .si(s_int[49]), .so(s_int[48]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[48]), .q(din_array[48]) );
328cl_sc1_msff_4x din_47 ( .si(s_int[48]), .so(s_int[47]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[47]), .q(din_array[47]) );
329cl_sc1_msff_4x din_46 ( .si(s_int[47]), .so(s_int[46]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[46]), .q(din_array[46]) );
330cl_sc1_msff_4x din_45 ( .si(s_int[46]), .so(s_int[45]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[45]), .q(din_array[45]) );
331cl_sc1_msff_4x din_44 ( .si(s_int[45]), .so(s_int[44]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[44]), .q(din_array[44]) );
332cl_sc1_msff_4x din_43 ( .si(s_int[44]), .so(s_int[43]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[43]), .q(din_array[43]) );
333cl_sc1_msff_4x din_42 ( .si(s_int[43]), .so(s_int[42]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[42]), .q(din_array[42]) );
334cl_sc1_msff_4x din_41 ( .si(s_int[42]), .so(s_int[41]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[41]), .q(din_array[41]) );
335cl_sc1_msff_4x din_40 ( .si(s_int[41]), .so(s_int[40]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[40]), .q(din_array[40]) );
336
337cl_sc1_msff_4x din_39 ( .si(s_int[40]), .so(s_int[39]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[39]), .q(din_array[39]) );
338cl_sc1_msff_4x din_38 ( .si(s_int[39]), .so(s_int[38]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[38]), .q(din_array[38]) );
339cl_sc1_msff_4x din_37 ( .si(s_int[38]), .so(s_int[37]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[37]), .q(din_array[37]) );
340cl_sc1_msff_4x din_36 ( .si(s_int[37]), .so(s_int[36]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[36]), .q(din_array[36]) );
341cl_sc1_msff_4x din_35 ( .si(s_int[36]), .so(s_int[35]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[35]), .q(din_array[35]) );
342cl_sc1_msff_4x din_34 ( .si(s_int[35]), .so(s_int[34]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[34]), .q(din_array[34]) );
343cl_sc1_msff_4x din_33 ( .si(s_int[34]), .so(s_int[33]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[33]), .q(din_array[33]) );
344cl_sc1_msff_4x din_32 ( .si(s_int[33]), .so(s_int[32]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[32]), .q(din_array[32]) );
345cl_sc1_msff_4x din_31 ( .si(s_int[32]), .so(s_int[31]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[31]), .q(din_array[31]) );
346cl_sc1_msff_4x din_30 ( .si(s_int[31]), .so(s_int[30]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[30]), .q(din_array[30]) );
347
348cl_sc1_msff_4x din_29 ( .si(s_int[30]), .so(s_int[29]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[29]), .q(din_array[29]) );
349cl_sc1_msff_4x din_28 ( .si(s_int[29]), .so(s_int[28]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[28]), .q(din_array[28]) );
350cl_sc1_msff_4x din_27 ( .si(s_int[28]), .so(s_int[27]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[27]), .q(din_array[27]) );
351cl_sc1_msff_4x din_26 ( .si(s_int[27]), .so(s_int[26]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[26]), .q(din_array[26]) );
352cl_sc1_msff_4x din_25 ( .si(s_int[26]), .so(s_int[25]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[25]), .q(din_array[25]) );
353cl_sc1_msff_4x din_24 ( .si(s_int[25]), .so(s_int[24]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[24]), .q(din_array[24]) );
354cl_sc1_msff_4x din_23 ( .si(s_int[24]), .so(s_int[23]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[23]), .q(din_array[23]) );
355cl_sc1_msff_4x din_22 ( .si(s_int[23]), .so(s_int[22]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[22]), .q(din_array[22]) );
356cl_sc1_msff_4x din_21 ( .si(s_int[22]), .so(s_int[21]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[21]), .q(din_array[21]) );
357cl_sc1_msff_4x din_20 ( .si(s_int[21]), .so(s_int[20]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[20]), .q(din_array[20]) );
358
359cl_sc1_msff_4x din_19 ( .si(s_int[20]), .so(s_int[19]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[19]), .q(din_array[19]) );
360cl_sc1_msff_4x din_18 ( .si(s_int[19]), .so(s_int[18]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[18]), .q(din_array[18]) );
361cl_sc1_msff_4x din_17 ( .si(s_int[18]), .so(s_int[17]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[17]), .q(din_array[17]) );
362cl_sc1_msff_4x din_16 ( .si(s_int[17]), .so(s_int[16]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[16]), .q(din_array[16]) );
363cl_sc1_msff_4x din_15 ( .si(s_int[16]), .so(s_int[15]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[15]), .q(din_array[15]) );
364cl_sc1_msff_4x din_14 ( .si(s_int[15]), .so(s_int[14]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[14]), .q(din_array[14]) );
365cl_sc1_msff_4x din_13 ( .si(s_int[14]), .so(s_int[13]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[13]), .q(din_array[13]) );
366cl_sc1_msff_4x din_12 ( .si(s_int[13]), .so(s_int[12]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[12]), .q(din_array[12]) );
367cl_sc1_msff_4x din_11 ( .si(s_int[12]), .so(s_int[11]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[11]), .q(din_array[11]) );
368cl_sc1_msff_4x din_10 ( .si(s_int[11]), .so(s_int[10]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[10]), .q(din_array[10]) );
369
370cl_sc1_msff_4x din_9 ( .si(s_int[10]), .so(s_int[9]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[9]), .q(din_array[9]) );
371cl_sc1_msff_4x din_8 ( .si(s_int[9]), .so(s_int[8]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[8]), .q(din_array[8]) );
372cl_sc1_msff_4x din_7 ( .si(s_int[8]), .so(s_int[7]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[7]), .q(din_array[7]) );
373cl_sc1_msff_4x din_6 ( .si(s_int[7]), .so(s_int[6]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[6]), .q(din_array[6]) );
374cl_sc1_msff_4x din_5 ( .si(s_int[6]), .so(s_int[5]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[5]), .q(din_array[5]) );
375cl_sc1_msff_4x din_4 ( .si(s_int[5]), .so(s_int[4]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[4]), .q(din_array[4]) );
376cl_sc1_msff_4x din_3 ( .si(s_int[4]), .so(s_int[3]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[3]), .q(din_array[3]) );
377cl_sc1_msff_4x din_2 ( .si(s_int[3]), .so(s_int[2]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[2]), .q(din_array[2]) );
378cl_sc1_msff_4x din_1 ( .si(s_int[2]), .so(s_int[1]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[1]), .q(din_array[1]) );
379cl_sc1_msff_4x din_0 ( .si(s_int[1]), .so(scan_out), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[0]), .q(din_array[0]) );
380
381//
382
383
384
385
386
387
388
389
390
391
392//assign rd_array = !wr_inhibit_array && rd_en_array;
393//assign wr_array = !wr_inhibit_array && wr_en_array;
394
395wire x1_,wr_array, rd_array;
396not rd2 (x1_,wr_inhibit_array);
397and rd1 (rd_array,rd_en_array,x1_);
398
399and wr1 (wr_array,wr_en_array,x1_);
400
401
402 //------------------------------------------------------------------------
403 // instantiate the clock-less ram
404 //------------------------------------------------------------------------
405wire [131:0] dout_array;
406n2_dmu_dp_128x132s_cust_array dmu_dou_dma_ram(
407 .clk (and_clk),
408 .rd_addr_array (rd_addr_array[6:0]),
409 .wr_addr_array (wr_addr_array[6:0]),
410 .rd_array (rd_array),
411 .wr_array (wr_array),
412 .din_array (din_array[131:0]),
413 .dout_array (dout_array[131:0])
414 );
415
416assign dout[131:0] = dout_array[131:0];
417
418
419
420endmodule //n2_dmu_dp_128x132s_cust
421
422
423module n2_dmu_dp_128x132s_cust_array (
424
425 // ram control
426 clk,
427 rd_addr_array,
428 wr_addr_array,
429 rd_array,
430 wr_array,
431 din_array,
432 dout_array
433
434);
435
436
437
438
439 //
440 input clk; // clk
441 input [6:0] rd_addr_array; // read port address in
442 input [6:0] wr_addr_array; // write port address in
443 input rd_array; // read port enable
444 input wr_array; // write port enable
445 input [131:0] din_array; // data in
446 output [131:0] dout_array; // data out
447
448
449// ----------------------------------------------------------------------------
450// Zero In Checkers
451// ----------------------------------------------------------------------------
452// checker to verify on accesses's that no bits are x
453/* //BP 0in assert -var (((|rd_addr_array[6:0] ) == 1'bx)
454 || ((|wr_addr_array[6:0] ) == 1'bx)
455 || ((rd_en_array ) == 1'bx)
456 || ((wr_en_array ) == 1'bx)
457 -active (rd_en_array )
458 -module dmu_ram128x132_array
459 -name dmu_ram128x132_array_x
460*/
461 // 0in kndr -var rd_addr_array
462 // 0in kndr -var wr_addr_array
463 // 0in kndr -var rd_array
464 // 0in kndr -var wr_array
465 // 0in kndr -var din_array -active (wr_array )
466
467
468/* RAM Array: =128 - 1 -> 127 */
469
470reg [131:0] array_ram [0:127];
471reg [131:0] dout_array;
472
473// Initialize the array
474`ifndef NOINITMEM
475integer i;
476
477initial begin
478 for (i=0; i<128; i=i+1) begin
479 array_ram[i] = 132'b0;
480 end
481end
482`endif
483
484
485// ----------------------------------------------------------------------------
486// Read the array
487// ----------------------------------------------------------------------------
488//assign dout_array[131:0] = array_ram[rd_addr_array[6:0]];
489always @(clk or rd_array or rd_addr_array or wr_array or wr_addr_array ) begin
490 if (clk) begin
491 if (rd_array) begin
492 if (wr_array & (rd_addr_array == wr_addr_array)) begin
493 dout_array[131:0] <= {132{1'bx}}; //0in <fire -severity 1 -message " got x's in dmu/dou" -group mbist_mode
494 end
495 else begin
496 dout_array[131:0] <= array_ram[rd_addr_array[6:0]];
497 end
498 end
499 else begin
500 dout_array[131:0] <= {132{1'b0}};
501 end
502 end
503end
504
505
506
507// ----------------------------------------------------------------------------
508// Write the array, note: it is written when the clock is low
509// ----------------------------------------------------------------------------
510always @(wr_array or wr_addr_array or clk or din_array ) begin
511 if(~clk) begin
512 if(wr_array ) begin
513 array_ram[wr_addr_array[6:0]] <= din_array[131:0];
514 end
515 end
516end
517
518
519
520endmodule // n2_dmu_dp_128x132s_cust_array
521
522
Full OpenSPARC design & verification tarball including full HDL.