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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_dmu_dp_144x149s_cust_l / n2_dmu_dp_144x149s_cust / rtl / n2_dmu_dp_144x149s_cust.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_dmu_dp_144x149s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_dmu_dp_144x149s_cust (
36 // clocks, scan
37 clk,
38 scan_in,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_pce_ov,
42 pce,
43 tcu_aclk,
44 tcu_bclk,
45 tcu_array_wr_inhibit,
46 scan_out,
47
48 // ram control
49 rd_addr,
50 wr_addr,
51 rd_en,
52 wr_en,
53 din,
54 dout
55
56);
57
58
59
60
61 // clocks, scan
62 input clk; // io clock
63 input scan_in; //
64 input tcu_scan_en; //
65 input tcu_se_scancollar_in; //
66 input tcu_pce_ov; // scan signals
67 input pce; //
68 input tcu_aclk; //
69 input tcu_bclk; //
70 input tcu_array_wr_inhibit; //
71 output scan_out; //
72
73
74 //
75 input [7:0] rd_addr; // a port address in
76 input [7:0] wr_addr; // b port address in
77 input rd_en; // a port enable
78 input wr_en; // a port enable
79 input [148:0] din; // data in
80 output [148:0] dout; // data out
81
82
83 //------------------------------------------------------------------------
84 // scan chain connections
85 //------------------------------------------------------------------------
86// scan renames
87wire [3:0] siclk,soclk;
88wire se,wr_inhibit_array,and_clk;
89assign wr_inhibit_array = tcu_array_wr_inhibit;
90// end scan
91
92 //------------------------------------------------------------------------
93 // instantiate clock headers
94 //------------------------------------------------------------------------
95wire [3:0] collar_clk;
96wire pce_ov = tcu_pce_ov;
97wire stop = 1'b0;
98wire aclk = tcu_aclk;
99wire bclk = tcu_bclk;
100assign se = tcu_se_scancollar_in; // TEMP
101
102cl_dp1_l1hdr_8x clk_hdr_ctrl (
103 .l2clk(clk),
104 .pce (pce),
105 .l1clk(collar_clk[0]),
106 .siclk_out(siclk[0]),
107 .soclk_out(soclk[0]),
108 .se(se),
109 .pce_ov(pce_ov),
110 .stop(stop),
111 .aclk(aclk),
112 .bclk(bclk)
113);
114
115cl_dp1_l1hdr_8x clk_hdr_data1 (
116 .l2clk(clk),
117 .pce (pce),
118 .l1clk(collar_clk[1]),
119 .siclk_out(siclk[1]),
120 .soclk_out(soclk[1]),
121 .se(se),
122 .pce_ov(pce_ov),
123 .stop(stop),
124 .aclk(aclk),
125 .bclk(bclk)
126);
127
128cl_dp1_l1hdr_8x clk_hdr_data2 (
129 .l2clk(clk),
130 .pce (pce),
131 .l1clk(collar_clk[2]),
132 .siclk_out(siclk[2]),
133 .soclk_out(soclk[2]),
134 .se(se),
135 .pce_ov(pce_ov),
136 .stop(stop),
137 .aclk(aclk),
138 .bclk(bclk)
139);
140
141cl_dp1_l1hdr_8x clk_hdr_data3 (
142 .l2clk(clk),
143 .pce (pce),
144 .l1clk(collar_clk[3]),
145 .siclk_out(siclk[3]),
146 .soclk_out(soclk[3]),
147 .se(se),
148 .pce_ov(pce_ov),
149 .stop(stop),
150 .aclk(aclk),
151 .bclk(bclk)
152);
153
154cl_dp1_l1hdr_8x scan_en_hdr (
155 .l2clk(clk),
156 .pce (pce),
157 .l1clk(and_clk),
158 .siclk_out(),
159 .soclk_out(),
160 .se(tcu_scan_en),
161 .pce_ov(pce_ov),
162 .stop(stop),
163 .aclk(aclk),
164 .bclk(bclk)
165);
166
167 //------------------------------------------------------------------------
168 // input flops
169 //------------------------------------------------------------------------
170wire [7:0] rd_addr_array,rd_addr_so;
171wire [7:0] wr_addr_array,wr_addr_so;
172wire rd_en_array,wr_en_array;
173wire rd_en_so,wr_en_so;
174wire [148:0] din_array,din_so;
175
176cl_mc1_sram_msff_mo_8x rd_addr_so_7 ( .si(scan_in), .so(rd_addr_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
177 .d(rd_addr[7]), .mq(rd_addr_array[7]), .and_clk(and_clk) );
178cl_mc1_sram_msff_mo_8x rd_addr_so_6 ( .si(rd_addr_so[7]), .so(rd_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
179 .d(rd_addr[6]), .mq(rd_addr_array[6]), .and_clk(and_clk) );
180cl_mc1_sram_msff_mo_8x rd_addr_so_5 ( .si(rd_addr_so[6]), .so(rd_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
181 .d(rd_addr[5]), .mq(rd_addr_array[5]), .and_clk(and_clk) );
182cl_mc1_sram_msff_mo_8x rd_addr_so_4 ( .si(rd_addr_so[5]), .so(rd_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
183 .d(rd_addr[4]), .mq(rd_addr_array[4]), .and_clk(and_clk) );
184cl_mc1_sram_msff_mo_8x rd_addr_so_3 ( .si(rd_addr_so[4]), .so(rd_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
185 .d(rd_addr[3]), .mq(rd_addr_array[3]), .and_clk(and_clk) );
186cl_mc1_sram_msff_mo_8x rd_addr_so_2 ( .si(rd_addr_so[3]), .so(rd_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
187 .d(rd_addr[2]), .mq(rd_addr_array[2]), .and_clk(and_clk) );
188cl_mc1_sram_msff_mo_8x rd_addr_so_1 ( .si(rd_addr_so[2]), .so(rd_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
189 .d(rd_addr[1]), .mq(rd_addr_array[1]), .and_clk(and_clk) );
190cl_mc1_sram_msff_mo_8x rd_addr_so_0 ( .si(rd_addr_so[1]), .so(rd_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
191 .d(rd_addr[0]), .mq(rd_addr_array[0]), .and_clk(and_clk) );
192
193cl_sc1_msff_8x wr_addr_so_7 ( .si(rd_addr_so[0]), .so(wr_addr_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
194 .d(wr_addr[7]), .q(wr_addr_array[7]) );
195cl_sc1_msff_8x wr_addr_so_6 ( .si(wr_addr_so[7]), .so(wr_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
196 .d(wr_addr[6]), .q(wr_addr_array[6]) );
197cl_sc1_msff_8x wr_addr_so_5 ( .si(wr_addr_so[6]), .so(wr_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
198 .d(wr_addr[5]), .q(wr_addr_array[5]) );
199cl_sc1_msff_8x wr_addr_so_4 ( .si(wr_addr_so[5]), .so(wr_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
200 .d(wr_addr[4]), .q(wr_addr_array[4]) );
201cl_sc1_msff_8x wr_addr_so_3 ( .si(wr_addr_so[4]), .so(wr_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
202 .d(wr_addr[3]), .q(wr_addr_array[3]) );
203cl_sc1_msff_8x wr_addr_so_2 ( .si(wr_addr_so[3]), .so(wr_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
204 .d(wr_addr[2]), .q(wr_addr_array[2]) );
205cl_sc1_msff_8x wr_addr_so_1 ( .si(wr_addr_so[2]), .so(wr_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
206 .d(wr_addr[1]), .q(wr_addr_array[1]) );
207cl_sc1_msff_8x wr_addr_so_0 ( .si(wr_addr_so[1]), .so(wr_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
208 .d(wr_addr[0]), .q(wr_addr_array[0]) );
209
210cl_mc1_sram_msff_mo_8x ff_rd_en ( .si(wr_addr_so[0]), .so(rd_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
211 .d(rd_en), .mq(rd_en_array), .and_clk(and_clk) );
212
213cl_sc1_msff_8x ff_wr_en ( .si(rd_en_so), .so(wr_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
214 .d(wr_en), .q(wr_en_array) );
215
216
217cl_sc1_msff_8x din_148 ( .si(wr_en_so), .so(din_so[148]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[148]), .q(din_array[148]) );
218cl_sc1_msff_8x din_147 ( .si(din_so[148]), .so(din_so[147]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[147]), .q(din_array[147]) );
219cl_sc1_msff_8x din_146 ( .si(din_so[147]), .so(din_so[146]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[146]), .q(din_array[146]) );
220cl_sc1_msff_8x din_145 ( .si(din_so[146]), .so(din_so[145]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[145]), .q(din_array[145]) );
221cl_sc1_msff_8x din_144 ( .si(din_so[145]), .so(din_so[144]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[144]), .q(din_array[144]) );
222cl_sc1_msff_8x din_143 ( .si(din_so[144]), .so(din_so[143]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[143]), .q(din_array[143]) );
223cl_sc1_msff_8x din_142 ( .si(din_so[143]), .so(din_so[142]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[142]), .q(din_array[142]) );
224cl_sc1_msff_8x din_141 ( .si(din_so[142]), .so(din_so[141]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[141]), .q(din_array[141]) );
225cl_sc1_msff_8x din_140 ( .si(din_so[141]), .so(din_so[140]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[140]), .q(din_array[140]) );
226
227cl_sc1_msff_8x din_139 ( .si(din_so[140]), .so(din_so[139]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[139]), .q(din_array[139]) );
228cl_sc1_msff_8x din_138 ( .si(din_so[139]), .so(din_so[138]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[138]), .q(din_array[138]) );
229cl_sc1_msff_8x din_137 ( .si(din_so[138]), .so(din_so[137]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[137]), .q(din_array[137]) );
230cl_sc1_msff_8x din_136 ( .si(din_so[137]), .so(din_so[136]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[136]), .q(din_array[136]) );
231cl_sc1_msff_8x din_135 ( .si(din_so[136]), .so(din_so[135]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[135]), .q(din_array[135]) );
232cl_sc1_msff_8x din_134 ( .si(din_so[135]), .so(din_so[134]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[134]), .q(din_array[134]) );
233cl_sc1_msff_8x din_133 ( .si(din_so[134]), .so(din_so[133]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[133]), .q(din_array[133]) );
234cl_sc1_msff_8x din_132 ( .si(din_so[133]), .so(din_so[132]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[132]), .q(din_array[132]) );
235cl_sc1_msff_8x din_131 ( .si(din_so[132]), .so(din_so[131]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[131]), .q(din_array[131]) );
236cl_sc1_msff_8x din_130 ( .si(din_so[131]), .so(din_so[130]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[130]), .q(din_array[130]) );
237
238cl_sc1_msff_8x din_129 ( .si(din_so[130]), .so(din_so[129]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[129]), .q(din_array[129]) );
239cl_sc1_msff_8x din_128 ( .si(din_so[129]), .so(din_so[128]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[128]), .q(din_array[128]) );
240cl_sc1_msff_8x din_127 ( .si(din_so[128]), .so(din_so[127]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[127]), .q(din_array[127]) );
241cl_sc1_msff_8x din_126 ( .si(din_so[127]), .so(din_so[126]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[126]), .q(din_array[126]) );
242cl_sc1_msff_8x din_125 ( .si(din_so[126]), .so(din_so[125]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[125]), .q(din_array[125]) );
243cl_sc1_msff_8x din_124 ( .si(din_so[125]), .so(din_so[124]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[124]), .q(din_array[124]) );
244cl_sc1_msff_8x din_123 ( .si(din_so[124]), .so(din_so[123]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[123]), .q(din_array[123]) );
245cl_sc1_msff_8x din_122 ( .si(din_so[123]), .so(din_so[122]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[122]), .q(din_array[122]) );
246cl_sc1_msff_8x din_121 ( .si(din_so[122]), .so(din_so[121]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[121]), .q(din_array[121]) );
247cl_sc1_msff_8x din_120 ( .si(din_so[121]), .so(din_so[120]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[120]), .q(din_array[120]) );
248
249cl_sc1_msff_8x din_119 ( .si(din_so[120]), .so(din_so[119]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[119]), .q(din_array[119]) );
250cl_sc1_msff_8x din_118 ( .si(din_so[119]), .so(din_so[118]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[118]), .q(din_array[118]) );
251cl_sc1_msff_8x din_117 ( .si(din_so[118]), .so(din_so[117]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[117]), .q(din_array[117]) );
252cl_sc1_msff_8x din_116 ( .si(din_so[117]), .so(din_so[116]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[116]), .q(din_array[116]) );
253cl_sc1_msff_8x din_115 ( .si(din_so[116]), .so(din_so[115]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[115]), .q(din_array[115]) );
254cl_sc1_msff_8x din_114 ( .si(din_so[115]), .so(din_so[114]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[114]), .q(din_array[114]) );
255cl_sc1_msff_8x din_113 ( .si(din_so[114]), .so(din_so[113]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[113]), .q(din_array[113]) );
256cl_sc1_msff_8x din_112 ( .si(din_so[113]), .so(din_so[112]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[112]), .q(din_array[112]) );
257cl_sc1_msff_8x din_111 ( .si(din_so[112]), .so(din_so[111]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[111]), .q(din_array[111]) );
258cl_sc1_msff_8x din_110 ( .si(din_so[111]), .so(din_so[110]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[110]), .q(din_array[110]) );
259
260cl_sc1_msff_8x din_109 ( .si(din_so[110]), .so(din_so[109]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[109]), .q(din_array[109]) );
261cl_sc1_msff_8x din_108 ( .si(din_so[109]), .so(din_so[108]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[108]), .q(din_array[108]) );
262cl_sc1_msff_8x din_107 ( .si(din_so[108]), .so(din_so[107]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[107]), .q(din_array[107]) );
263cl_sc1_msff_8x din_106 ( .si(din_so[107]), .so(din_so[106]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[106]), .q(din_array[106]) );
264cl_sc1_msff_8x din_105 ( .si(din_so[106]), .so(din_so[105]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[105]), .q(din_array[105]) );
265cl_sc1_msff_8x din_104 ( .si(din_so[105]), .so(din_so[104]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[104]), .q(din_array[104]) );
266cl_sc1_msff_8x din_103 ( .si(din_so[104]), .so(din_so[103]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[103]), .q(din_array[103]) );
267cl_sc1_msff_8x din_102 ( .si(din_so[103]), .so(din_so[102]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[102]), .q(din_array[102]) );
268cl_sc1_msff_8x din_101 ( .si(din_so[102]), .so(din_so[101]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[101]), .q(din_array[101]) );
269cl_sc1_msff_8x din_100 ( .si(din_so[101]), .so(din_so[100]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[100]), .q(din_array[100]) );
270
271cl_sc1_msff_8x din_99 ( .si(din_so[100]), .so(din_so[99]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[99]), .q(din_array[99]) );
272cl_sc1_msff_8x din_98 ( .si(din_so[99]), .so(din_so[98]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[98]), .q(din_array[98]) );
273cl_sc1_msff_8x din_97 ( .si(din_so[98]), .so(din_so[97]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[97]), .q(din_array[97]) );
274cl_sc1_msff_8x din_96 ( .si(din_so[97]), .so(din_so[96]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[96]), .q(din_array[96]) );
275cl_sc1_msff_8x din_95 ( .si(din_so[96]), .so(din_so[95]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[95]), .q(din_array[95]) );
276cl_sc1_msff_8x din_94 ( .si(din_so[95]), .so(din_so[94]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[94]), .q(din_array[94]) );
277cl_sc1_msff_8x din_93 ( .si(din_so[94]), .so(din_so[93]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]), .d(din[93]), .q(din_array[93]) );
278cl_sc1_msff_8x din_92 ( .si(din_so[93]), .so(din_so[92]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[92]), .q(din_array[92]) );
279cl_sc1_msff_8x din_91 ( .si(din_so[92]), .so(din_so[91]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[91]), .q(din_array[91]) );
280cl_sc1_msff_8x din_90 ( .si(din_so[91]), .so(din_so[90]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[90]), .q(din_array[90]) );
281
282cl_sc1_msff_8x din_89 ( .si(din_so[90]), .so(din_so[89]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[89]), .q(din_array[89]) );
283cl_sc1_msff_8x din_88 ( .si(din_so[89]), .so(din_so[88]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[88]), .q(din_array[88]) );
284cl_sc1_msff_8x din_87 ( .si(din_so[88]), .so(din_so[87]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[87]), .q(din_array[87]) );
285cl_sc1_msff_8x din_86 ( .si(din_so[87]), .so(din_so[86]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[86]), .q(din_array[86]) );
286cl_sc1_msff_8x din_85 ( .si(din_so[86]), .so(din_so[85]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[85]), .q(din_array[85]) );
287cl_sc1_msff_8x din_84 ( .si(din_so[85]), .so(din_so[84]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[84]), .q(din_array[84]) );
288cl_sc1_msff_8x din_83 ( .si(din_so[84]), .so(din_so[83]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[83]), .q(din_array[83]) );
289cl_sc1_msff_8x din_82 ( .si(din_so[83]), .so(din_so[82]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[82]), .q(din_array[82]) );
290cl_sc1_msff_8x din_81 ( .si(din_so[82]), .so(din_so[81]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[81]), .q(din_array[81]) );
291cl_sc1_msff_8x din_80 ( .si(din_so[81]), .so(din_so[80]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[80]), .q(din_array[80]) );
292
293cl_sc1_msff_8x din_79 ( .si(din_so[80]), .so(din_so[79]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[79]), .q(din_array[79]) );
294cl_sc1_msff_8x din_78 ( .si(din_so[79]), .so(din_so[78]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[78]), .q(din_array[78]) );
295cl_sc1_msff_8x din_77 ( .si(din_so[78]), .so(din_so[77]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[77]), .q(din_array[77]) );
296cl_sc1_msff_8x din_76 ( .si(din_so[77]), .so(din_so[76]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[76]), .q(din_array[76]) );
297cl_sc1_msff_8x din_75 ( .si(din_so[76]), .so(din_so[75]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[75]), .q(din_array[75]) );
298cl_sc1_msff_8x din_74 ( .si(din_so[75]), .so(din_so[74]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[74]), .q(din_array[74]) );
299cl_sc1_msff_8x din_73 ( .si(din_so[74]), .so(din_so[73]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[73]), .q(din_array[73]) );
300cl_sc1_msff_8x din_72 ( .si(din_so[73]), .so(din_so[72]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[72]), .q(din_array[72]) );
301cl_sc1_msff_8x din_71 ( .si(din_so[72]), .so(din_so[71]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[71]), .q(din_array[71]) );
302cl_sc1_msff_8x din_70 ( .si(din_so[71]), .so(din_so[70]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[70]), .q(din_array[70]) );
303
304cl_sc1_msff_8x din_69 ( .si(din_so[70]), .so(din_so[69]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[69]), .q(din_array[69]) );
305cl_sc1_msff_8x din_68 ( .si(din_so[69]), .so(din_so[68]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[68]), .q(din_array[68]) );
306cl_sc1_msff_8x din_67 ( .si(din_so[68]), .so(din_so[67]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[67]), .q(din_array[67]) );
307cl_sc1_msff_8x din_66 ( .si(din_so[67]), .so(din_so[66]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[66]), .q(din_array[66]) );
308cl_sc1_msff_8x din_65 ( .si(din_so[66]), .so(din_so[65]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[65]), .q(din_array[65]) );
309cl_sc1_msff_8x din_64 ( .si(din_so[65]), .so(din_so[64]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[64]), .q(din_array[64]) );
310cl_sc1_msff_8x din_63 ( .si(din_so[64]), .so(din_so[63]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[63]), .q(din_array[63]) );
311cl_sc1_msff_8x din_62 ( .si(din_so[63]), .so(din_so[62]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[62]), .q(din_array[62]) );
312cl_sc1_msff_8x din_61 ( .si(din_so[62]), .so(din_so[61]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[61]), .q(din_array[61]) );
313cl_sc1_msff_8x din_60 ( .si(din_so[61]), .so(din_so[60]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[60]), .q(din_array[60]) );
314
315cl_sc1_msff_8x din_59 ( .si(din_so[60]), .so(din_so[59]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[59]), .q(din_array[59]) );
316cl_sc1_msff_8x din_58 ( .si(din_so[59]), .so(din_so[58]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[58]), .q(din_array[58]) );
317cl_sc1_msff_8x din_57 ( .si(din_so[58]), .so(din_so[57]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[57]), .q(din_array[57]) );
318cl_sc1_msff_8x din_56 ( .si(din_so[57]), .so(din_so[56]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[56]), .q(din_array[56]) );
319cl_sc1_msff_8x din_55 ( .si(din_so[56]), .so(din_so[55]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[55]), .q(din_array[55]) );
320cl_sc1_msff_8x din_54 ( .si(din_so[55]), .so(din_so[54]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[54]), .q(din_array[54]) );
321cl_sc1_msff_8x din_53 ( .si(din_so[54]), .so(din_so[53]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[53]), .q(din_array[53]) );
322cl_sc1_msff_8x din_52 ( .si(din_so[53]), .so(din_so[52]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[52]), .q(din_array[52]) );
323cl_sc1_msff_8x din_51 ( .si(din_so[52]), .so(din_so[51]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[51]), .q(din_array[51]) );
324cl_sc1_msff_8x din_50 ( .si(din_so[51]), .so(din_so[50]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[50]), .q(din_array[50]) );
325
326cl_sc1_msff_8x din_49 ( .si(din_so[50]), .so(din_so[49]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[49]), .q(din_array[49]) );
327cl_sc1_msff_8x din_48 ( .si(din_so[49]), .so(din_so[48]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[48]), .q(din_array[48]) );
328cl_sc1_msff_8x din_47 ( .si(din_so[48]), .so(din_so[47]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[47]), .q(din_array[47]) );
329cl_sc1_msff_8x din_46 ( .si(din_so[47]), .so(din_so[46]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[46]), .q(din_array[46]) );
330cl_sc1_msff_8x din_45 ( .si(din_so[46]), .so(din_so[45]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[45]), .q(din_array[45]) );
331cl_sc1_msff_8x din_44 ( .si(din_so[45]), .so(din_so[44]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[44]), .q(din_array[44]) );
332cl_sc1_msff_8x din_43 ( .si(din_so[44]), .so(din_so[43]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[43]), .q(din_array[43]) );
333cl_sc1_msff_8x din_42 ( .si(din_so[43]), .so(din_so[42]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[42]), .q(din_array[42]) );
334cl_sc1_msff_8x din_41 ( .si(din_so[42]), .so(din_so[41]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[41]), .q(din_array[41]) );
335cl_sc1_msff_8x din_40 ( .si(din_so[41]), .so(din_so[40]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[40]), .q(din_array[40]) );
336
337cl_sc1_msff_8x din_39 ( .si(din_so[40]), .so(din_so[39]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[39]), .q(din_array[39]) );
338cl_sc1_msff_8x din_38 ( .si(din_so[39]), .so(din_so[38]), .l1clk(collar_clk[2]), .siclk(siclk[2]), .soclk(soclk[2]), .d(din[38]), .q(din_array[38]) );
339cl_sc1_msff_8x din_37 ( .si(din_so[38]), .so(din_so[37]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[37]), .q(din_array[37]) );
340cl_sc1_msff_8x din_36 ( .si(din_so[37]), .so(din_so[36]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[36]), .q(din_array[36]) );
341cl_sc1_msff_8x din_35 ( .si(din_so[36]), .so(din_so[35]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[35]), .q(din_array[35]) );
342cl_sc1_msff_8x din_34 ( .si(din_so[35]), .so(din_so[34]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[34]), .q(din_array[34]) );
343cl_sc1_msff_8x din_33 ( .si(din_so[34]), .so(din_so[33]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[33]), .q(din_array[33]) );
344cl_sc1_msff_8x din_32 ( .si(din_so[33]), .so(din_so[32]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[32]), .q(din_array[32]) );
345cl_sc1_msff_8x din_31 ( .si(din_so[32]), .so(din_so[31]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[31]), .q(din_array[31]) );
346cl_sc1_msff_8x din_30 ( .si(din_so[31]), .so(din_so[30]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[30]), .q(din_array[30]) );
347
348cl_sc1_msff_8x din_29 ( .si(din_so[30]), .so(din_so[29]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[29]), .q(din_array[29]) );
349cl_sc1_msff_8x din_28 ( .si(din_so[29]), .so(din_so[28]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[28]), .q(din_array[28]) );
350cl_sc1_msff_8x din_27 ( .si(din_so[28]), .so(din_so[27]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[27]), .q(din_array[27]) );
351cl_sc1_msff_8x din_26 ( .si(din_so[27]), .so(din_so[26]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[26]), .q(din_array[26]) );
352cl_sc1_msff_8x din_25 ( .si(din_so[26]), .so(din_so[25]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[25]), .q(din_array[25]) );
353cl_sc1_msff_8x din_24 ( .si(din_so[25]), .so(din_so[24]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[24]), .q(din_array[24]) );
354cl_sc1_msff_8x din_23 ( .si(din_so[24]), .so(din_so[23]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[23]), .q(din_array[23]) );
355cl_sc1_msff_8x din_22 ( .si(din_so[23]), .so(din_so[22]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[22]), .q(din_array[22]) );
356cl_sc1_msff_8x din_21 ( .si(din_so[22]), .so(din_so[21]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[21]), .q(din_array[21]) );
357cl_sc1_msff_8x din_20 ( .si(din_so[21]), .so(din_so[20]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[20]), .q(din_array[20]) );
358
359cl_sc1_msff_8x din_19 ( .si(din_so[20]), .so(din_so[19]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[19]), .q(din_array[19]) );
360cl_sc1_msff_8x din_18 ( .si(din_so[19]), .so(din_so[18]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[18]), .q(din_array[18]) );
361cl_sc1_msff_8x din_17 ( .si(din_so[18]), .so(din_so[17]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[17]), .q(din_array[17]) );
362cl_sc1_msff_8x din_16 ( .si(din_so[17]), .so(din_so[16]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[16]), .q(din_array[16]) );
363cl_sc1_msff_8x din_15 ( .si(din_so[16]), .so(din_so[15]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[15]), .q(din_array[15]) );
364cl_sc1_msff_8x din_14 ( .si(din_so[15]), .so(din_so[14]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[14]), .q(din_array[14]) );
365cl_sc1_msff_8x din_13 ( .si(din_so[14]), .so(din_so[13]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[13]), .q(din_array[13]) );
366cl_sc1_msff_8x din_12 ( .si(din_so[13]), .so(din_so[12]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[12]), .q(din_array[12]) );
367cl_sc1_msff_8x din_11 ( .si(din_so[12]), .so(din_so[11]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[11]), .q(din_array[11]) );
368cl_sc1_msff_8x din_10 ( .si(din_so[11]), .so(din_so[10]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[10]), .q(din_array[10]) );
369
370cl_sc1_msff_8x din_9 ( .si(din_so[10]), .so(din_so[9]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[9]), .q(din_array[9]) );
371cl_sc1_msff_8x din_8 ( .si(din_so[9]), .so(din_so[8]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[8]), .q(din_array[8]) );
372cl_sc1_msff_8x din_7 ( .si(din_so[8]), .so(din_so[7]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[7]), .q(din_array[7]) );
373cl_sc1_msff_8x din_6 ( .si(din_so[7]), .so(din_so[6]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[6]), .q(din_array[6]) );
374cl_sc1_msff_8x din_5 ( .si(din_so[6]), .so(din_so[5]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[5]), .q(din_array[5]) );
375cl_sc1_msff_8x din_4 ( .si(din_so[5]), .so(din_so[4]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[4]), .q(din_array[4]) );
376cl_sc1_msff_8x din_3 ( .si(din_so[4]), .so(din_so[3]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[3]), .q(din_array[3]) );
377cl_sc1_msff_8x din_2 ( .si(din_so[3]), .so(din_so[2]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[2]), .q(din_array[2]) );
378cl_sc1_msff_8x din_1 ( .si(din_so[2]), .so(din_so[1]), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[1]), .q(din_array[1]) );
379cl_sc1_msff_8x din_0 ( .si(din_so[1]), .so(scan_out), .l1clk(collar_clk[3]), .siclk(siclk[3]), .soclk(soclk[3]), .d(din[0]), .q(din_array[0]) );
380
381//assign rd_array = !wr_inhibit_array && rd_en_array;
382//assign wr_array = !wr_inhibit_array && wr_en_array;
383
384wire x1_,wr_array, rd_array;
385not rd2 (x1_,wr_inhibit_array);
386and rd1 (rd_array,rd_en_array,x1_);
387
388and wr1 (wr_array,wr_en_array,x1_);
389
390
391 //------------------------------------------------------------------------
392 // instantiate the clock-less ram
393 //------------------------------------------------------------------------
394wire [148:0] dout_array;
395n2_dmu_dp_144x149s_cust_array dmu_diu_ram(
396 .clk (and_clk),
397 .rd_addr_array (rd_addr_array[7:0]),
398 .wr_addr_array (wr_addr_array[7:0]),
399 .rd_array (rd_array),
400 .wr_array (wr_array),
401 .din_array (din_array[148:0]),
402 .dout_array (dout_array[148:0])
403 );
404
405assign dout[148:0] = dout_array[148:0];
406
407
408
409endmodule //n2_dmu_dp_144x149s_cust
410
411
412
413module n2_dmu_dp_144x149s_cust_array (
414
415 // ram control
416 clk,
417 rd_addr_array,
418 wr_addr_array,
419 rd_array,
420 wr_array,
421 din_array,
422 dout_array
423
424);
425
426
427
428
429 //
430 input clk; // clk
431 input [7:0] rd_addr_array; // read port address in
432 input [7:0] wr_addr_array; // write port address in
433 input rd_array; // read port enable
434 input wr_array; // write port enable
435 input [148:0] din_array; // data in
436 output [148:0] dout_array; // data out
437
438
439// ----------------------------------------------------------------------------
440// Zero In Checkers
441// ----------------------------------------------------------------------------
442// checker to verify on accesses's that no bits are x
443/* //BP0in assert -var (((|rd_addr_array[7:0] ) == 1'bx)
444 || ((|wr_addr_array[7:0] ) == 1'bx)
445 || ((rd_en_array ) == 1'bx)
446 || ((wr_en_array ) == 1'bx)
447 -active (rd_en_array )
448 -module dmu_ram144x149_array
449 -name dmu_ram144x149_array_x
450*/
451 // 0in kndr -var rd_addr_array
452 // 0in kndr -var wr_addr_array
453 // 0in kndr -var rd_array
454 // 0in kndr -var wr_array
455 // 0in kndr -var din_array -active (wr_array )
456
457
458
459
460/* RAM Array: =144 - 1 -> 143 */
461
462reg [148:0] array_ram [0:143];
463//reg [148:0] array_ram [0:191];
464reg [148:0] dout_array;
465
466// Initialize the array
467`ifndef NOINITMEM
468integer i;
469
470initial begin
471 for (i=0; i<144; i=i+1) begin
472 array_ram[i] = 149'b0;
473 end
474end
475`endif
476
477// ----------------------------------------------------------------------------
478// Read the array
479// ----------------------------------------------------------------------------
480//assign dout_array[148:0] = array_ram[rd_addr_array[7:0]];
481always @(clk or rd_array or rd_addr_array or wr_array or wr_addr_array ) begin
482 if (clk) begin
483 if (rd_array) begin
484 if ( (wr_array & (rd_addr_array == wr_addr_array)) ||
485 (rd_addr_array >= 144) ) begin
486 dout_array[148:0] <= {149{1'bx}}; //0in <fire -severity 1 -message " got x's in dmu/dou" -group mbist_mode
487 end
488 else begin
489 dout_array[148:0] <= array_ram[rd_addr_array[7:0]];
490 end
491 end
492 else begin
493 dout_array[148:0] <= {149{1'b1}};
494 end
495 end
496end
497
498
499
500
501// ----------------------------------------------------------------------------
502// Write the array, note: it is written when the clock is low
503// ----------------------------------------------------------------------------
504always @(wr_array or wr_addr_array or clk or din_array ) begin
505 if(~clk) begin
506 if(wr_array ) begin
507 array_ram[wr_addr_array[7:0]] <= din_array[148:0];
508 end
509 end
510end
511
512
513
514endmodule // n2_dmu_dp_144x149s_cust_array
515
516
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