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Initial commit of OpenSPARC T2 design and verification files.
[OpenSPARC-T2-DV] / libs / n2sram / dp / n2_dmu_dp_512x60s_cust_l / n2_dmu_dp_512x60s_cust / rtl / n2_dmu_dp_512x60s_cust.v
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86530b38
AT		 1// ========== Copyright Header Begin ==========================================
2//
3// OpenSPARC T2 Processor File: n2_dmu_dp_512x60s_cust.v
4// Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved
5// 4150 Network Circle, Santa Clara, California 95054, U.S.A.
6//
7// * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER.
8//
9// This program is free software; you can redistribute it and/or modify
10// it under the terms of the GNU General Public License as published by
11// the Free Software Foundation; version 2 of the License.
12//
13// This program is distributed in the hope that it will be useful,
14// but WITHOUT ANY WARRANTY; without even the implied warranty of
15// MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
16// GNU General Public License for more details.
17//
18// You should have received a copy of the GNU General Public License
19// along with this program; if not, write to the Free Software
20// Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
21//
22// For the avoidance of doubt, and except that if any non-GPL license
23// choice is available it will apply instead, Sun elects to use only
24// the General Public License version 2 (GPLv2) at this time for any
25// software where a choice of GPL license versions is made
26// available with the language indicating that GPLv2 or any later version
27// may be used, or where a choice of which version of the GPL is applied is
28// otherwise unspecified.
29//
30// Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara,
31// CA 95054 USA or visit www.sun.com if you need additional information or
32// have any questions.
33//
34// ========== Copyright Header End ============================================
35module n2_dmu_dp_512x60s_cust (
36 // clocks, scan
37 clk,
38 scan_in,
39 tcu_scan_en,
40 tcu_se_scancollar_in,
41 tcu_pce_ov,
42 pce,
43 tcu_aclk,
44 tcu_bclk,
45 tcu_array_wr_inhibit,
46 scan_out,
47
48 // ram control
49 rd_addr,
50 wr_addr,
51 rd_en,
52 wr_en,
53 din,
54 dout
55
56);
57
58
59
60
61 // clocks, scan
62 input clk; // io clock
63 input scan_in; //
64 input tcu_scan_en; //
65 input tcu_se_scancollar_in; //
66 input tcu_pce_ov; // scan signals
67 input pce; //
68 input tcu_aclk; //
69 input tcu_bclk; //
70 input tcu_array_wr_inhibit; //
71 output scan_out; //
72
73
74 //
75 input [8:0] rd_addr; // a port address in
76 input [8:0] wr_addr; // b port address in
77 input rd_en; // a port enable
78 input wr_en; // a write port enable
79 input [59:0] din; // data in
80 output [59:0] dout; // data out
81
82
83 //------------------------------------------------------------------------
84 // scan chain connections
85 //------------------------------------------------------------------------
86// scan renames
87wire [1:0] siclk,soclk;
88wire se,wr_inhibit,and_clk;
89assign wr_inhibit = tcu_array_wr_inhibit;
90// end scan
91 //------------------------------------------------------------------------
92 // instantiate clock headers
93 //------------------------------------------------------------------------
94wire [1:0] collar_clk;
95wire pce_ov = tcu_pce_ov;
96wire stop = 1'b0;
97wire aclk = tcu_aclk;
98wire bclk = tcu_bclk;
99assign se = tcu_se_scancollar_in; // TEMP
100
101cl_dp1_l1hdr_8x clk_hdr_ctrl (
102 .l2clk(clk),
103 .pce (pce),
104 .l1clk(collar_clk[0]),
105 .siclk_out(siclk[0]),
106 .soclk_out(soclk[0]),
107 .se(se),
108 .pce_ov(pce_ov),
109 .stop(stop),
110 .aclk(aclk),
111 .bclk(bclk)
112);
113
114cl_dp1_l1hdr_8x clk_hdr_din (
115 .l2clk(clk),
116 .pce (pce),
117 .l1clk(collar_clk[1]),
118 .siclk_out(siclk[1]),
119 .soclk_out(soclk[1]),
120 .se(se),
121 .pce_ov(pce_ov),
122 .stop(stop),
123 .aclk(aclk),
124 .bclk(bclk)
125);
126
127cl_dp1_l1hdr_8x scan_en_hdr (
128 .l2clk(clk),
129 .pce (pce),
130 .l1clk(and_clk),
131 .siclk_out(),
132 .soclk_out(),
133 .se(tcu_scan_en),
134 .pce_ov(pce_ov),
135 .stop(stop),
136 .aclk(aclk),
137 .bclk(bclk)
138);
139
140
141 //------------------------------------------------------------------------
142 // input flops
143 //------------------------------------------------------------------------
144
145wire [8:0] rd_addr_array,rd_addr_so;
146wire [8:0] wr_addr_array,wr_addr_so;
147wire rd_en_array,wr_en_array;
148wire rd_en_so,wr_en_so;
149wire [59:0] din_array;
150wire [59:1] din_so;
151
152cl_sc1_msff_4x din_59 ( .si(scan_in), .so(din_so[59]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
153 .d(din[59]), .q(din_array[59]) );
154cl_sc1_msff_4x din_58 ( .si(din_so[59]), .so(din_so[58]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
155 .d(din[58]), .q(din_array[58]) );
156cl_sc1_msff_4x din_57 ( .si(din_so[58]), .so(din_so[57]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
157 .d(din[57]), .q(din_array[57]) );
158cl_sc1_msff_4x din_56 ( .si(din_so[57]), .so(din_so[56]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
159 .d(din[56]), .q(din_array[56]) );
160cl_sc1_msff_4x din_55 ( .si(din_so[56]), .so(din_so[55]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
161 .d(din[55]), .q(din_array[55]) );
162cl_sc1_msff_4x din_54 ( .si(din_so[55]), .so(din_so[54]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
163 .d(din[54]), .q(din_array[54]) );
164cl_sc1_msff_4x din_53 ( .si(din_so[54]), .so(din_so[53]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
165 .d(din[53]), .q(din_array[53]) );
166cl_sc1_msff_4x din_52 ( .si(din_so[53]), .so(din_so[52]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
167 .d(din[52]), .q(din_array[52]) );
168cl_sc1_msff_4x din_51 ( .si(din_so[52]), .so(din_so[51]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
169 .d(din[51]), .q(din_array[51]) );
170cl_sc1_msff_4x din_50 ( .si(din_so[51]), .so(din_so[50]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
171 .d(din[50]), .q(din_array[50]) );
172
173cl_sc1_msff_4x din_49 ( .si(din_so[50]), .so(din_so[49]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
174 .d(din[49]), .q(din_array[49]) );
175cl_sc1_msff_4x din_48 ( .si(din_so[49]), .so(din_so[48]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
176 .d(din[48]), .q(din_array[48]) );
177cl_sc1_msff_4x din_47 ( .si(din_so[48]), .so(din_so[47]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
178 .d(din[47]), .q(din_array[47]) );
179cl_sc1_msff_4x din_46 ( .si(din_so[47]), .so(din_so[46]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
180 .d(din[46]), .q(din_array[46]) );
181cl_sc1_msff_4x din_45 ( .si(din_so[46]), .so(din_so[45]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
182 .d(din[45]), .q(din_array[45]) );
183cl_sc1_msff_4x din_44 ( .si(din_so[45]), .so(din_so[44]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
184 .d(din[44]), .q(din_array[44]) );
185cl_sc1_msff_4x din_43 ( .si(din_so[44]), .so(din_so[43]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
186 .d(din[43]), .q(din_array[43]) );
187cl_sc1_msff_4x din_42 ( .si(din_so[43]), .so(din_so[42]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
188 .d(din[42]), .q(din_array[42]) );
189cl_sc1_msff_4x din_41 ( .si(din_so[42]), .so(din_so[41]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
190 .d(din[41]), .q(din_array[41]) );
191cl_sc1_msff_4x din_40 ( .si(din_so[41]), .so(din_so[40]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
192 .d(din[40]), .q(din_array[40]) );
193
194cl_sc1_msff_4x din_39 ( .si(din_so[40]), .so(din_so[39]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
195 .d(din[39]), .q(din_array[39]) );
196cl_sc1_msff_4x din_38 ( .si(din_so[39]), .so(din_so[38]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
197 .d(din[38]), .q(din_array[38]) );
198cl_sc1_msff_4x din_37 ( .si(din_so[38]), .so(din_so[37]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
199 .d(din[37]), .q(din_array[37]) );
200cl_sc1_msff_4x din_36 ( .si(din_so[37]), .so(din_so[36]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
201 .d(din[36]), .q(din_array[36]) );
202cl_sc1_msff_4x din_35 ( .si(din_so[36]), .so(din_so[35]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
203 .d(din[35]), .q(din_array[35]) );
204cl_sc1_msff_4x din_34 ( .si(din_so[35]), .so(din_so[34]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
205 .d(din[34]), .q(din_array[34]) );
206cl_sc1_msff_4x din_33 ( .si(din_so[34]), .so(din_so[33]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
207 .d(din[33]), .q(din_array[33]) );
208cl_sc1_msff_4x din_32 ( .si(din_so[33]), .so(din_so[32]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
209 .d(din[32]), .q(din_array[32]) );
210cl_sc1_msff_4x din_31 ( .si(din_so[32]), .so(din_so[31]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
211 .d(din[31]), .q(din_array[31]) );
212cl_sc1_msff_4x din_30 ( .si(din_so[31]), .so(din_so[30]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
213 .d(din[30]), .q(din_array[30]) );
214
215
216cl_mc1_sram_msff_mo_8x ff_rd_en ( .si(din_so[30]), .so(rd_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
217 .d(rd_en), .mq(rd_en_array), .and_clk(and_clk) );
218
219
220
221
222cl_mc1_sram_msff_mo_8x rd_addr_so_8 ( .si(rd_en_so), .so(rd_addr_so[8]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
223 .d(rd_addr[8]), .mq(rd_addr_array[8]), .and_clk(and_clk) );
224cl_mc1_sram_msff_mo_8x rd_addr_so_7 ( .si(rd_addr_so[8]), .so(rd_addr_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
225 .d(rd_addr[7]), .mq(rd_addr_array[7]), .and_clk(and_clk) );
226cl_mc1_sram_msff_mo_8x rd_addr_so_6 ( .si(rd_addr_so[7]), .so(rd_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
227 .d(rd_addr[6]), .mq(rd_addr_array[6]), .and_clk(and_clk) );
228cl_mc1_sram_msff_mo_8x rd_addr_so_5 ( .si(rd_addr_so[6]), .so(rd_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
229 .d(rd_addr[5]), .mq(rd_addr_array[5]), .and_clk(and_clk) );
230cl_mc1_sram_msff_mo_8x rd_addr_so_4 ( .si(rd_addr_so[5]), .so(rd_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
231 .d(rd_addr[4]), .mq(rd_addr_array[4]), .and_clk(and_clk) );
232cl_mc1_sram_msff_mo_8x rd_addr_so_3 ( .si(rd_addr_so[4]), .so(rd_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
233 .d(rd_addr[3]), .mq(rd_addr_array[3]), .and_clk(and_clk) );
234cl_mc1_sram_msff_mo_8x rd_addr_so_2 ( .si(rd_addr_so[3]), .so(rd_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
235 .d(rd_addr[2]), .mq(rd_addr_array[2]), .and_clk(and_clk) );
236cl_mc1_sram_msff_mo_8x rd_addr_so_1 ( .si(rd_addr_so[2]), .so(rd_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
237 .d(rd_addr[1]), .mq(rd_addr_array[1]), .and_clk(and_clk) );
238cl_mc1_sram_msff_mo_8x rd_addr_so_0 ( .si(rd_addr_so[1]), .so(rd_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
239 .d(rd_addr[0]), .mq(rd_addr_array[0]), .and_clk(and_clk) );
240
241
242cl_sc1_msff_8x ff_wr_en ( .si(rd_addr_so[0]), .so(wr_en_so), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
243 .d(wr_en), .q(wr_en_array) );
244
245
246
247cl_sc1_msff_4x wr_addr_so_8 ( .si(wr_en_so), .so(wr_addr_so[8]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
248 .d(wr_addr[8]), .q(wr_addr_array[8]) );
249cl_sc1_msff_4x wr_addr_so_7 ( .si(wr_addr_so[8]), .so(wr_addr_so[7]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
250 .d(wr_addr[7]), .q(wr_addr_array[7]) );
251cl_sc1_msff_4x wr_addr_so_6 ( .si(wr_addr_so[7]), .so(wr_addr_so[6]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
252 .d(wr_addr[6]), .q(wr_addr_array[6]) );
253cl_sc1_msff_4x wr_addr_so_5 ( .si(wr_addr_so[6]), .so(wr_addr_so[5]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
254 .d(wr_addr[5]), .q(wr_addr_array[5]) );
255cl_sc1_msff_4x wr_addr_so_4 ( .si(wr_addr_so[5]), .so(wr_addr_so[4]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
256 .d(wr_addr[4]), .q(wr_addr_array[4]) );
257cl_sc1_msff_4x wr_addr_so_3 ( .si(wr_addr_so[4]), .so(wr_addr_so[3]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
258 .d(wr_addr[3]), .q(wr_addr_array[3]) );
259cl_sc1_msff_4x wr_addr_so_2 ( .si(wr_addr_so[3]), .so(wr_addr_so[2]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
260 .d(wr_addr[2]), .q(wr_addr_array[2]) );
261cl_sc1_msff_4x wr_addr_so_1 ( .si(wr_addr_so[2]), .so(wr_addr_so[1]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
262 .d(wr_addr[1]), .q(wr_addr_array[1]) );
263cl_sc1_msff_4x wr_addr_so_0 ( .si(wr_addr_so[1]), .so(wr_addr_so[0]), .l1clk(collar_clk[0]), .siclk(siclk[0]), .soclk(soclk[0]),
264 .d(wr_addr[0]), .q(wr_addr_array[0]) );
265
266
267
268
269
270cl_sc1_msff_4x din_29 ( .si(wr_addr_so[0]), .so(din_so[29]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
271 .d(din[29]), .q(din_array[29]) );
272cl_sc1_msff_4x din_28 ( .si(din_so[29]), .so(din_so[28]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
273 .d(din[28]), .q(din_array[28]) );
274cl_sc1_msff_4x din_27 ( .si(din_so[28]), .so(din_so[27]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
275 .d(din[27]), .q(din_array[27]) );
276cl_sc1_msff_4x din_26 ( .si(din_so[27]), .so(din_so[26]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
277 .d(din[26]), .q(din_array[26]) );
278cl_sc1_msff_4x din_25 ( .si(din_so[26]), .so(din_so[25]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
279 .d(din[25]), .q(din_array[25]) );
280cl_sc1_msff_4x din_24 ( .si(din_so[25]), .so(din_so[24]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
281 .d(din[24]), .q(din_array[24]) );
282cl_sc1_msff_4x din_23 ( .si(din_so[24]), .so(din_so[23]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
283 .d(din[23]), .q(din_array[23]) );
284cl_sc1_msff_4x din_22 ( .si(din_so[23]), .so(din_so[22]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
285 .d(din[22]), .q(din_array[22]) );
286cl_sc1_msff_4x din_21 ( .si(din_so[22]), .so(din_so[21]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
287 .d(din[21]), .q(din_array[21]) );
288cl_sc1_msff_4x din_20 ( .si(din_so[21]), .so(din_so[20]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
289 .d(din[20]), .q(din_array[20]) );
290
291cl_sc1_msff_4x din_19 ( .si(din_so[20]), .so(din_so[19]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
292 .d(din[19]), .q(din_array[19]) );
293cl_sc1_msff_4x din_18 ( .si(din_so[19]), .so(din_so[18]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
294 .d(din[18]), .q(din_array[18]) );
295cl_sc1_msff_4x din_17 ( .si(din_so[18]), .so(din_so[17]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
296 .d(din[17]), .q(din_array[17]) );
297cl_sc1_msff_4x din_16 ( .si(din_so[17]), .so(din_so[16]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
298 .d(din[16]), .q(din_array[16]) );
299cl_sc1_msff_4x din_15 ( .si(din_so[16]), .so(din_so[15]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
300 .d(din[15]), .q(din_array[15]) );
301cl_sc1_msff_4x din_14 ( .si(din_so[15]), .so(din_so[14]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
302 .d(din[14]), .q(din_array[14]) );
303cl_sc1_msff_4x din_13 ( .si(din_so[14]), .so(din_so[13]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
304 .d(din[13]), .q(din_array[13]) );
305cl_sc1_msff_4x din_12 ( .si(din_so[13]), .so(din_so[12]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
306 .d(din[12]), .q(din_array[12]) );
307cl_sc1_msff_4x din_11 ( .si(din_so[12]), .so(din_so[11]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
308 .d(din[11]), .q(din_array[11]) );
309cl_sc1_msff_4x din_10 ( .si(din_so[11]), .so(din_so[10]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
310 .d(din[10]), .q(din_array[10]) );
311
312cl_sc1_msff_4x din_9 ( .si(din_so[10]), .so(din_so[9]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
313 .d(din[9]), .q(din_array[9]) );
314cl_sc1_msff_4x din_8 ( .si(din_so[9]), .so(din_so[8]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
315 .d(din[8]), .q(din_array[8]) );
316cl_sc1_msff_4x din_7 ( .si(din_so[8]), .so(din_so[7]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
317 .d(din[7]), .q(din_array[7]) );
318cl_sc1_msff_4x din_6 ( .si(din_so[7]), .so(din_so[6]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
319 .d(din[6]), .q(din_array[6]) );
320cl_sc1_msff_4x din_5 ( .si(din_so[6]), .so(din_so[5]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
321 .d(din[5]), .q(din_array[5]) );
322cl_sc1_msff_4x din_4 ( .si(din_so[5]), .so(din_so[4]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
323 .d(din[4]), .q(din_array[4]) );
324cl_sc1_msff_4x din_3 ( .si(din_so[4]), .so(din_so[3]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
325 .d(din[3]), .q(din_array[3]) );
326cl_sc1_msff_4x din_2 ( .si(din_so[3]), .so(din_so[2]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
327 .d(din[2]), .q(din_array[2]) );
328cl_sc1_msff_4x din_1 ( .si(din_so[2]), .so(din_so[1]), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
329 .d(din[1]), .q(din_array[1]) );
330cl_sc1_msff_4x din_0 ( .si(din_so[1]), .so(scan_out), .l1clk(collar_clk[1]), .siclk(siclk[1]), .soclk(soclk[1]),
331 .d(din[0]), .q(din_array[0]) );
332
333
334
335
336//assign rd_array = !wr_inhibit && rd_en_array;
337//assign wr_array = !wr_inhibit && wr_en_array;
338
339wire x1_,wr_array, rd_array;
340not rd2 (x1_,wr_inhibit);
341and rd1 (rd_array,rd_en_array,x1_);
342
343and wr1 (wr_array,wr_en_array,x1_);
344
345
346 //------------------------------------------------------------------------
347 // instantiate the clock-less ram
348 //------------------------------------------------------------------------
349wire [59:0] dout_array;
350n2_dmu_dp_512x60s_cust_array dmu_tdb_ram(
351 .clk (and_clk),
352 .rd_addr_array (rd_addr_array[8:0]),
353 .wr_addr_array (wr_addr_array[8:0]),
354 .rd_array (rd_array),
355 .wr_array (wr_array),
356 .din_array (din_array[59:0]),
357 .dout_array (dout_array[59:0])
358 );
359
360assign dout[59:0] = dout_array[59:0];
361
362
363
364endmodule //n2_dmu_dp_512x60s_cust
365
366
367
368module n2_dmu_dp_512x60s_cust_array (
369
370 // ram control
371 clk,
372 rd_addr_array,
373 wr_addr_array,
374 rd_array,
375 wr_array,
376 din_array,
377 dout_array
378
379);
380
381
382
383
384 //
385 input clk; // clk
386 input [8:0] rd_addr_array; // read port address in
387 input [8:0] wr_addr_array; // write port address in
388 input rd_array; // read port enable
389 input wr_array; // write port enable
390 input [59:0] din_array; // data in
391 output [59:0] dout_array; // data out
392
393
394// ----------------------------------------------------------------------------
395// Zero In Checkers
396// ----------------------------------------------------------------------------
397// checker to verify on accesses's that no bits are x
398/* //BP 0in assert -var (((|rd_addr_array[8:0] ) == 1'bx)
399 || ((|wr_addr_array[8:0] ) == 1'bx)
400 || ((rd_en_array ) == 1'bx)
401 || ((wr_en_array ) == 1'bx)
402 -active (rd_en_array )
403 -module dmu_ram512x36_array
404 -name dmu_ram512x36_array_x
405*/
406 // 0in kndr -var rd_addr_array
407 // 0in kndr -var wr_addr_array
408 // 0in kndr -var rd_array
409 // 0in kndr -var wr_array
410 // 0in kndr -var din_array -active (wr_array )
411
412
413/* RAM Array: =512 - 1 -> 511 */
414
415reg [59:0] array_ram [0:511];
416reg [59:0] dout_array;
417
418`ifndef NOINITMEM
419integer i;
420
421initial begin
422 for (i=0; i<512; i=i+1) begin
423 array_ram[i] = 60'b0;
424 end
425 dout_array = 60'b0;
426end
427`endif
428
429
430// ----------------------------------------------------------------------------
431// Read the array
432// ----------------------------------------------------------------------------
433//assign dout_array[35:0] = array_ram[rd_addr_array[8:0]];
434always @(clk or rd_array or rd_addr_array or wr_addr_array or wr_array ) begin
435 if (clk) begin
436 if (rd_array) begin
437 if (wr_array & (rd_addr_array == wr_addr_array)) begin
438 dout_array[59:0] <= {60{1'bx}}; //0in < fire -severity 1 -message " got x's in dmu/tdb" -group mbist_mode
439 end
440 else begin
441 dout_array[59:0] <= array_ram[rd_addr_array[8:0]];
442 end
443 end
444 else begin
445 dout_array[59:0] <= {60{1'b0}};
446 end
447 end
448end
449
450
451
452
453
454// ----------------------------------------------------------------------------
455// Write the array, note: it is written when the clock is low
456// ----------------------------------------------------------------------------
457always @(wr_array or wr_addr_array or clk or din_array ) begin
458 if(~clk) begin
459 if(wr_array ) begin
460 array_ram[wr_addr_array[8:0]] <= din_array[59:0];
461 end
462 end
463end
464
465
466
467endmodule // n2_dmu_dp_512x60s_cust_array
468
469
Full OpenSPARC design & verification tarball including full HDL.