Commit | Line | Data |
---|---|---|
86530b38 AT |
1 | // ========== Copyright Header Begin ========================================== |
2 | // | |
3 | // OpenSPARC T2 Processor File: n2_dva_dp_32x32_cust.v | |
4 | // Copyright (C) 1995-2007 Sun Microsystems, Inc. All Rights Reserved | |
5 | // 4150 Network Circle, Santa Clara, California 95054, U.S.A. | |
6 | // | |
7 | // * DO NOT ALTER OR REMOVE COPYRIGHT NOTICES OR THIS FILE HEADER. | |
8 | // | |
9 | // This program is free software; you can redistribute it and/or modify | |
10 | // it under the terms of the GNU General Public License as published by | |
11 | // the Free Software Foundation; version 2 of the License. | |
12 | // | |
13 | // This program is distributed in the hope that it will be useful, | |
14 | // but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | // MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | // GNU General Public License for more details. | |
17 | // | |
18 | // You should have received a copy of the GNU General Public License | |
19 | // along with this program; if not, write to the Free Software | |
20 | // Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA | |
21 | // | |
22 | // For the avoidance of doubt, and except that if any non-GPL license | |
23 | // choice is available it will apply instead, Sun elects to use only | |
24 | // the General Public License version 2 (GPLv2) at this time for any | |
25 | // software where a choice of GPL license versions is made | |
26 | // available with the language indicating that GPLv2 or any later version | |
27 | // may be used, or where a choice of which version of the GPL is applied is | |
28 | // otherwise unspecified. | |
29 | // | |
30 | // Please contact Sun Microsystems, Inc., 4150 Network Circle, Santa Clara, | |
31 | // CA 95054 USA or visit www.sun.com if you need additional information or | |
32 | // have any questions. | |
33 | // | |
34 | // ========== Copyright Header End ============================================ | |
35 | module n2_dva_dp_32x32_cust ( | |
36 | l2clk, | |
37 | tcu_pce_ov, | |
38 | tcu_se_scancollar_in, | |
39 | tcu_scan_en, | |
40 | tcu_array_wr_inhibit, | |
41 | tcu_aclk, | |
42 | tcu_bclk, | |
43 | pce, | |
44 | scan_in, | |
45 | rd_addr, | |
46 | wr_addr, | |
47 | din, | |
48 | bit_wen, | |
49 | rd_en, | |
50 | wr_en, | |
51 | dout, | |
52 | scan_out); | |
53 | wire pce_ov; | |
54 | wire stop; | |
55 | wire siclk; | |
56 | wire soclk; | |
57 | wire l1clk_in; | |
58 | wire l1clk_free; | |
59 | wire dff_bit_en_scanin; | |
60 | wire dff_bit_en_scanout; | |
61 | wire [31:0] bit_wen_d1; | |
62 | wire dff_wr_en_scanin; | |
63 | wire dff_wr_en_scanout; | |
64 | wire wr_en_d1; | |
65 | wire dff_rd_addr_scanin; | |
66 | wire dff_rd_addr_scanout; | |
67 | wire [4:0] rd_addr_d1; | |
68 | wire [4:0] mq_l_rd_addr_unused; | |
69 | wire [4:0] q_rd_addr_unused; | |
70 | wire [4:0] q_l_rd_addr_unused; | |
71 | wire dff_rd_en_scanin; | |
72 | wire dff_rd_en_scanout; | |
73 | wire rd_en_d1; | |
74 | wire mq_l_rd_en_unused; | |
75 | wire q_rd_en_unused; | |
76 | wire q_l_rd_en_unused; | |
77 | wire dff_wr_addr_scanin; | |
78 | wire dff_wr_addr_scanout; | |
79 | wire [4:0] wr_addr_d1; | |
80 | wire dff_din_scanin; | |
81 | wire dff_din_scanout; | |
82 | wire [31:0] din_d1; | |
83 | wire wr_inhibit_; | |
84 | wire wr_en_qual; | |
85 | wire rd_en_qual; | |
86 | ||
87 | ||
88 | input l2clk; | |
89 | input tcu_pce_ov; | |
90 | input tcu_se_scancollar_in; | |
91 | input tcu_scan_en; | |
92 | input tcu_array_wr_inhibit; | |
93 | input tcu_aclk; | |
94 | input tcu_bclk; | |
95 | input pce; | |
96 | ||
97 | ||
98 | input scan_in; | |
99 | input [4:0] rd_addr; | |
100 | input [4:0] wr_addr; | |
101 | input [31:0] din; | |
102 | input [31:0] bit_wen; | |
103 | input rd_en; | |
104 | input wr_en; | |
105 | ||
106 | output [31:0] dout; | |
107 | output scan_out; | |
108 | ||
109 | `ifndef FPGA | |
110 | // synopsys translate_off | |
111 | `endif | |
112 | ||
113 | assign pce_ov = tcu_pce_ov; | |
114 | assign stop = 1'b0; | |
115 | assign siclk = tcu_aclk ; | |
116 | assign soclk = tcu_bclk; | |
117 | ||
118 | //================================================ | |
119 | // Clock headers | |
120 | //================================================ | |
121 | n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro l1ch_in ( | |
122 | .l2clk (l2clk), | |
123 | .l1en (pce), | |
124 | .se (tcu_se_scancollar_in), | |
125 | .l1clk (l1clk_in), | |
126 | .pce_ov(pce_ov), | |
127 | .stop(stop) | |
128 | ); | |
129 | ||
130 | n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro l1ch_free ( | |
131 | .l2clk (l2clk), | |
132 | .l1en (pce), | |
133 | .se (tcu_scan_en), | |
134 | .l1clk (l1clk_free), | |
135 | .pce_ov(pce_ov), | |
136 | .stop(stop) | |
137 | ); | |
138 | ||
139 | /////////////////////////////////////////////////////////////// | |
140 | // Flop the inputs // | |
141 | /////////////////////////////////////////////////////////////// | |
142 | n2_dva_dp_32x32_cust_msff_ctl_macro__scanreverse_1__width_32 dff_bit_en ( | |
143 | .scan_in(dff_bit_en_scanin), | |
144 | .scan_out(dff_bit_en_scanout), | |
145 | .l1clk(l1clk_in), | |
146 | .din(bit_wen[31:0]), | |
147 | .dout(bit_wen_d1[31:0]), | |
148 | .siclk(siclk), | |
149 | .soclk(soclk) | |
150 | ); | |
151 | ||
152 | n2_dva_dp_32x32_cust_msff_ctl_macro__width_1 dff_wr_en ( | |
153 | .scan_in(dff_wr_en_scanin), | |
154 | .scan_out(dff_wr_en_scanout), | |
155 | .l1clk(l1clk_in), | |
156 | .din(wr_en), | |
157 | .dout(wr_en_d1), | |
158 | .siclk(siclk), | |
159 | .soclk(soclk) | |
160 | ); | |
161 | ||
162 | n2_dva_dp_32x32_cust_sram_msff_mo_macro__scanreverse_1__width_5 dff_rd_addr ( | |
163 | .scan_in(dff_rd_addr_scanin), | |
164 | .scan_out(dff_rd_addr_scanout), | |
165 | .l1clk(l1clk_in), | |
166 | .and_clk(l1clk_free), | |
167 | .d(rd_addr[4:0]), | |
168 | .mq(rd_addr_d1[4:0]), | |
169 | .mq_l(mq_l_rd_addr_unused[4:0]), | |
170 | .q(q_rd_addr_unused[4:0]), | |
171 | .q_l(q_l_rd_addr_unused[4:0]), | |
172 | .siclk(siclk), | |
173 | .soclk(soclk) | |
174 | ); | |
175 | ||
176 | n2_dva_dp_32x32_cust_sram_msff_mo_macro__width_1 dff_rd_en ( | |
177 | .scan_in(dff_rd_en_scanin), | |
178 | .scan_out(dff_rd_en_scanout), | |
179 | .l1clk(l1clk_in), | |
180 | .and_clk(l1clk_free), | |
181 | .d(rd_en), | |
182 | .mq(rd_en_d1), | |
183 | .mq_l(mq_l_rd_en_unused), | |
184 | .q(q_rd_en_unused), | |
185 | .q_l(q_l_rd_en_unused), | |
186 | .siclk(siclk), | |
187 | .soclk(soclk) | |
188 | ); | |
189 | ||
190 | n2_dva_dp_32x32_cust_msff_ctl_macro__width_5 dff_wr_addr ( | |
191 | .scan_in(dff_wr_addr_scanin), | |
192 | .scan_out(dff_wr_addr_scanout), | |
193 | .l1clk(l1clk_in), | |
194 | .din(wr_addr[4:0]), | |
195 | .dout(wr_addr_d1[4:0]), | |
196 | .siclk(siclk), | |
197 | .soclk(soclk) | |
198 | ); | |
199 | ||
200 | n2_dva_dp_32x32_cust_msff_ctl_macro__width_32 dff_din ( | |
201 | .scan_in(dff_din_scanin), | |
202 | .scan_out(dff_din_scanout), | |
203 | .l1clk(l1clk_in), | |
204 | .din(din[31:0]), | |
205 | .dout(din_d1[31:0]), | |
206 | .siclk(siclk), | |
207 | .soclk(soclk) | |
208 | ); | |
209 | ||
210 | n2_dva_dp_32x32_cust_inv_macro__width_1 wr_inh_inv ( | |
211 | .din (tcu_array_wr_inhibit), | |
212 | .dout (wr_inhibit_) | |
213 | ); | |
214 | n2_dva_dp_32x32_cust_and_macro__width_2 wr_and ( | |
215 | .din0 ({wr_en_d1 ,rd_en_d1}), | |
216 | .din1 ({wr_inhibit_,wr_inhibit_}), | |
217 | .dout ({wr_en_qual ,rd_en_qual}) | |
218 | ); | |
219 | ||
220 | n2_dva_dp_32x32_array array ( | |
221 | .clk (l1clk_free), | |
222 | .rd_addr (rd_addr_d1[4:0]), | |
223 | .wr_addr (wr_addr_d1[4:0]), | |
224 | .din (din_d1[31:0]), | |
225 | .bit_wen (bit_wen_d1[31:0]), | |
226 | .rd_en (rd_en_qual), | |
227 | .wr_en (wr_en_qual), | |
228 | .dout (dout[31:0]) | |
229 | ); | |
230 | ||
231 | supply0 vss; | |
232 | supply1 vdd; | |
233 | ||
234 | // fixscan start: | |
235 | assign dff_bit_en_scanin = scan_in ; | |
236 | assign dff_wr_en_scanin = dff_bit_en_scanout ; | |
237 | assign dff_rd_addr_scanin = dff_wr_en_scanout ; | |
238 | assign dff_rd_en_scanin = dff_rd_addr_scanout ; | |
239 | assign dff_wr_addr_scanin = dff_rd_en_scanout ; | |
240 | assign dff_din_scanin = dff_wr_addr_scanout ; | |
241 | assign scan_out = dff_din_scanout ; | |
242 | // fixscan end: | |
243 | ||
244 | `ifndef FPGA | |
245 | // synopsys translate_on | |
246 | `endif | |
247 | ||
248 | endmodule | |
249 | ||
250 | ||
251 | ||
252 | ||
253 | ||
254 | ||
255 | // any PARAMS parms go into naming of macro | |
256 | ||
257 | module n2_dva_dp_32x32_cust_l1clkhdr_ctl_macro ( | |
258 | l2clk, | |
259 | l1en, | |
260 | pce_ov, | |
261 | stop, | |
262 | se, | |
263 | l1clk); | |
264 | ||
265 | ||
266 | input l2clk; | |
267 | input l1en; | |
268 | input pce_ov; | |
269 | input stop; | |
270 | input se; | |
271 | output l1clk; | |
272 | ||
273 | ||
274 | ||
275 | ||
276 | ||
277 | cl_sc1_l1hdr_8x c_0 ( | |
278 | ||
279 | ||
280 | .l2clk(l2clk), | |
281 | .pce(l1en), | |
282 | .l1clk(l1clk), | |
283 | .se(se), | |
284 | .pce_ov(pce_ov), | |
285 | .stop(stop) | |
286 | ); | |
287 | ||
288 | ||
289 | ||
290 | endmodule | |
291 | ||
292 | ||
293 | ||
294 | ||
295 | ||
296 | ||
297 | ||
298 | ||
299 | ||
300 | ||
301 | ||
302 | ||
303 | ||
304 | // any PARAMS parms go into naming of macro | |
305 | ||
306 | module n2_dva_dp_32x32_cust_msff_ctl_macro__scanreverse_1__width_32 ( | |
307 | din, | |
308 | l1clk, | |
309 | scan_in, | |
310 | siclk, | |
311 | soclk, | |
312 | dout, | |
313 | scan_out); | |
314 | wire [31:0] fdin; | |
315 | wire [0:30] so; | |
316 | ||
317 | input [31:0] din; | |
318 | input l1clk; | |
319 | input scan_in; | |
320 | ||
321 | ||
322 | input siclk; | |
323 | input soclk; | |
324 | ||
325 | output [31:0] dout; | |
326 | output scan_out; | |
327 | assign fdin[31:0] = din[31:0]; | |
328 | ||
329 | ||
330 | ||
331 | ||
332 | ||
333 | ||
334 | dff #(32) d0_0 ( | |
335 | .l1clk(l1clk), | |
336 | .siclk(siclk), | |
337 | .soclk(soclk), | |
338 | .d(fdin[31:0]), | |
339 | .si({so[0:30],scan_in}), | |
340 | .so({scan_out,so[0:30]}), | |
341 | .q(dout[31:0]) | |
342 | ); | |
343 | ||
344 | ||
345 | ||
346 | ||
347 | ||
348 | ||
349 | ||
350 | ||
351 | ||
352 | ||
353 | ||
354 | ||
355 | endmodule | |
356 | ||
357 | ||
358 | ||
359 | ||
360 | ||
361 | ||
362 | ||
363 | ||
364 | ||
365 | ||
366 | ||
367 | ||
368 | ||
369 | // any PARAMS parms go into naming of macro | |
370 | ||
371 | module n2_dva_dp_32x32_cust_msff_ctl_macro__width_1 ( | |
372 | din, | |
373 | l1clk, | |
374 | scan_in, | |
375 | siclk, | |
376 | soclk, | |
377 | dout, | |
378 | scan_out); | |
379 | wire [0:0] fdin; | |
380 | ||
381 | input [0:0] din; | |
382 | input l1clk; | |
383 | input scan_in; | |
384 | ||
385 | ||
386 | input siclk; | |
387 | input soclk; | |
388 | ||
389 | output [0:0] dout; | |
390 | output scan_out; | |
391 | assign fdin[0:0] = din[0:0]; | |
392 | ||
393 | ||
394 | ||
395 | ||
396 | ||
397 | ||
398 | dff #(1) d0_0 ( | |
399 | .l1clk(l1clk), | |
400 | .siclk(siclk), | |
401 | .soclk(soclk), | |
402 | .d(fdin[0:0]), | |
403 | .si(scan_in), | |
404 | .so(scan_out), | |
405 | .q(dout[0:0]) | |
406 | ); | |
407 | ||
408 | ||
409 | ||
410 | ||
411 | ||
412 | ||
413 | ||
414 | ||
415 | ||
416 | ||
417 | ||
418 | ||
419 | endmodule | |
420 | ||
421 | ||
422 | ||
423 | ||
424 | ||
425 | ||
426 | ||
427 | ||
428 | ||
429 | // | |
430 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
431 | // | |
432 | // | |
433 | ||
434 | ||
435 | ||
436 | ||
437 | ||
438 | module n2_dva_dp_32x32_cust_sram_msff_mo_macro__scanreverse_1__width_5 ( | |
439 | d, | |
440 | scan_in, | |
441 | l1clk, | |
442 | and_clk, | |
443 | siclk, | |
444 | soclk, | |
445 | mq, | |
446 | mq_l, | |
447 | scan_out, | |
448 | q, | |
449 | q_l); | |
450 | wire [0:3] so; | |
451 | ||
452 | input [4:0] d; | |
453 | input scan_in; | |
454 | input l1clk; | |
455 | input and_clk; | |
456 | input siclk; | |
457 | input soclk; | |
458 | output [4:0] mq; | |
459 | output [4:0] mq_l; | |
460 | output scan_out; | |
461 | output [4:0] q; | |
462 | output [4:0] q_l; | |
463 | ||
464 | ||
465 | ||
466 | ||
467 | ||
468 | ||
469 | new_dlata #(5) d0_0 ( | |
470 | .d(d[4:0]), | |
471 | .si({so[0:3],scan_in}), | |
472 | .so({scan_out,so[0:3]}), | |
473 | .l1clk(l1clk), | |
474 | .and_clk(and_clk), | |
475 | .siclk(siclk), | |
476 | .soclk(soclk), | |
477 | .q(q[4:0]), | |
478 | .q_l(q_l[4:0]), | |
479 | .mq(mq[4:0]), | |
480 | .mq_l(mq_l[4:0]) | |
481 | ); | |
482 | ||
483 | ||
484 | ||
485 | ||
486 | ||
487 | ||
488 | ||
489 | ||
490 | ||
491 | ||
492 | //place::generic_place($width,$stack,$left); | |
493 | ||
494 | endmodule | |
495 | ||
496 | ||
497 | ||
498 | ||
499 | ||
500 | // | |
501 | // macro for cl_mc1_sram_msff_mo_{16,8,4}x flops | |
502 | // | |
503 | // | |
504 | ||
505 | ||
506 | ||
507 | ||
508 | ||
509 | module n2_dva_dp_32x32_cust_sram_msff_mo_macro__width_1 ( | |
510 | d, | |
511 | scan_in, | |
512 | l1clk, | |
513 | and_clk, | |
514 | siclk, | |
515 | soclk, | |
516 | mq, | |
517 | mq_l, | |
518 | scan_out, | |
519 | q, | |
520 | q_l); | |
521 | input [0:0] d; | |
522 | input scan_in; | |
523 | input l1clk; | |
524 | input and_clk; | |
525 | input siclk; | |
526 | input soclk; | |
527 | output [0:0] mq; | |
528 | output [0:0] mq_l; | |
529 | output scan_out; | |
530 | output [0:0] q; | |
531 | output [0:0] q_l; | |
532 | ||
533 | ||
534 | ||
535 | ||
536 | ||
537 | ||
538 | new_dlata #(1) d0_0 ( | |
539 | .d(d[0:0]), | |
540 | .si(scan_in), | |
541 | .so(scan_out), | |
542 | .l1clk(l1clk), | |
543 | .and_clk(and_clk), | |
544 | .siclk(siclk), | |
545 | .soclk(soclk), | |
546 | .q(q[0:0]), | |
547 | .q_l(q_l[0:0]), | |
548 | .mq(mq[0:0]), | |
549 | .mq_l(mq_l[0:0]) | |
550 | ); | |
551 | ||
552 | ||
553 | ||
554 | ||
555 | ||
556 | ||
557 | ||
558 | ||
559 | ||
560 | ||
561 | //place::generic_place($width,$stack,$left); | |
562 | ||
563 | endmodule | |
564 | ||
565 | ||
566 | ||
567 | ||
568 | ||
569 | ||
570 | ||
571 | ||
572 | ||
573 | // any PARAMS parms go into naming of macro | |
574 | ||
575 | module n2_dva_dp_32x32_cust_msff_ctl_macro__width_5 ( | |
576 | din, | |
577 | l1clk, | |
578 | scan_in, | |
579 | siclk, | |
580 | soclk, | |
581 | dout, | |
582 | scan_out); | |
583 | wire [4:0] fdin; | |
584 | wire [3:0] so; | |
585 | ||
586 | input [4:0] din; | |
587 | input l1clk; | |
588 | input scan_in; | |
589 | ||
590 | ||
591 | input siclk; | |
592 | input soclk; | |
593 | ||
594 | output [4:0] dout; | |
595 | output scan_out; | |
596 | assign fdin[4:0] = din[4:0]; | |
597 | ||
598 | ||
599 | ||
600 | ||
601 | ||
602 | ||
603 | dff #(5) d0_0 ( | |
604 | .l1clk(l1clk), | |
605 | .siclk(siclk), | |
606 | .soclk(soclk), | |
607 | .d(fdin[4:0]), | |
608 | .si({scan_in,so[3:0]}), | |
609 | .so({so[3:0],scan_out}), | |
610 | .q(dout[4:0]) | |
611 | ); | |
612 | ||
613 | ||
614 | ||
615 | ||
616 | ||
617 | ||
618 | ||
619 | ||
620 | ||
621 | ||
622 | ||
623 | ||
624 | endmodule | |
625 | ||
626 | ||
627 | ||
628 | ||
629 | ||
630 | ||
631 | ||
632 | ||
633 | ||
634 | ||
635 | ||
636 | ||
637 | ||
638 | // any PARAMS parms go into naming of macro | |
639 | ||
640 | module n2_dva_dp_32x32_cust_msff_ctl_macro__width_32 ( | |
641 | din, | |
642 | l1clk, | |
643 | scan_in, | |
644 | siclk, | |
645 | soclk, | |
646 | dout, | |
647 | scan_out); | |
648 | wire [31:0] fdin; | |
649 | wire [30:0] so; | |
650 | ||
651 | input [31:0] din; | |
652 | input l1clk; | |
653 | input scan_in; | |
654 | ||
655 | ||
656 | input siclk; | |
657 | input soclk; | |
658 | ||
659 | output [31:0] dout; | |
660 | output scan_out; | |
661 | assign fdin[31:0] = din[31:0]; | |
662 | ||
663 | ||
664 | ||
665 | ||
666 | ||
667 | ||
668 | dff #(32) d0_0 ( | |
669 | .l1clk(l1clk), | |
670 | .siclk(siclk), | |
671 | .soclk(soclk), | |
672 | .d(fdin[31:0]), | |
673 | .si({scan_in,so[30:0]}), | |
674 | .so({so[30:0],scan_out}), | |
675 | .q(dout[31:0]) | |
676 | ); | |
677 | ||
678 | ||
679 | ||
680 | ||
681 | ||
682 | ||
683 | ||
684 | ||
685 | ||
686 | ||
687 | ||
688 | ||
689 | endmodule | |
690 | ||
691 | ||
692 | ||
693 | ||
694 | ||
695 | ||
696 | ||
697 | ||
698 | ||
699 | // | |
700 | // invert macro | |
701 | // | |
702 | // | |
703 | ||
704 | ||
705 | ||
706 | ||
707 | ||
708 | module n2_dva_dp_32x32_cust_inv_macro__width_1 ( | |
709 | din, | |
710 | dout); | |
711 | input [0:0] din; | |
712 | output [0:0] dout; | |
713 | ||
714 | ||
715 | ||
716 | ||
717 | ||
718 | ||
719 | inv #(1) d0_0 ( | |
720 | .in(din[0:0]), | |
721 | .out(dout[0:0]) | |
722 | ); | |
723 | ||
724 | ||
725 | ||
726 | ||
727 | ||
728 | ||
729 | ||
730 | ||
731 | ||
732 | endmodule | |
733 | ||
734 | ||
735 | ||
736 | ||
737 | ||
738 | // | |
739 | // and macro for ports = 2,3,4 | |
740 | // | |
741 | // | |
742 | ||
743 | ||
744 | ||
745 | ||
746 | ||
747 | module n2_dva_dp_32x32_cust_and_macro__width_2 ( | |
748 | din0, | |
749 | din1, | |
750 | dout); | |
751 | input [1:0] din0; | |
752 | input [1:0] din1; | |
753 | output [1:0] dout; | |
754 | ||
755 | ||
756 | ||
757 | ||
758 | ||
759 | ||
760 | and2 #(2) d0_0 ( | |
761 | .in0(din0[1:0]), | |
762 | .in1(din1[1:0]), | |
763 | .out(dout[1:0]) | |
764 | ); | |
765 | ||
766 | ||
767 | ||
768 | ||
769 | ||
770 | ||
771 | ||
772 | ||
773 | ||
774 | endmodule | |
775 | ||
776 | ||
777 | ||
778 | ||
779 | ||
780 | ||
781 | module n2_dva_dp_32x32_array ( | |
782 | clk, | |
783 | rd_addr, | |
784 | wr_addr, | |
785 | din, | |
786 | bit_wen, | |
787 | rd_en, | |
788 | wr_en, | |
789 | dout); | |
790 | wire [31:0] temp; | |
791 | wire [31:0] vbit_sa; | |
792 | wire [31:0] wt_data; | |
793 | wire [31:0] vbit; | |
794 | ||
795 | ||
796 | input clk; | |
797 | input [4:0] rd_addr; | |
798 | input [4:0] wr_addr; | |
799 | input [31:0] din; | |
800 | input [31:0] bit_wen; | |
801 | input rd_en; | |
802 | input wr_en; | |
803 | ||
804 | output [31:0] dout; | |
805 | ||
806 | reg [31:0] mem [31:0]; | |
807 | reg [31:0] dout ; | |
808 | ||
809 | `ifndef NOINITMEM | |
810 | // Initialize the arrays. | |
811 | integer i; | |
812 | initial begin | |
813 | for (i=0;i<32;i=i+1) begin | |
814 | mem[i] = 32'b0 ; | |
815 | end | |
816 | end | |
817 | `endif | |
818 | ||
819 | ///////////// | |
820 | // Write on negedge | |
821 | ///////////// | |
822 | ||
823 | assign temp[31:0] = mem[wr_addr[4:0]]; | |
824 | ||
825 | always @(negedge clk) begin | |
826 | if (wr_en) begin | |
827 | mem[wr_addr[4:0]] <= (bit_wen[31:0] & din[31:0]) | (~bit_wen[31:0] & temp[31:0]); | |
828 | ||
829 | ||
830 | ||
831 | ||
832 | end | |
833 | end | |
834 | ||
835 | ///////////// | |
836 | // Read | |
837 | ///////////// | |
838 | ||
839 | assign vbit_sa[31:0] = mem[rd_addr[4:0]] & {32{rd_en}}; | |
840 | ||
841 | // Handle write-through case. | |
842 | // Read result is the AND of the previous and new values. | |
843 | // wt_data represents the precharged write bit line | |
844 | // It is high when writing a '1' or when not writing. | |
845 | ||
846 | assign wt_data[31:0] = {32{rd_addr[4:0] != wr_addr[4:0]}} | ~bit_wen[31:0] | din[31:0] | {32{~wr_en}}; | |
847 | ||
848 | assign vbit[31:0] = vbit_sa[31:0] & wt_data[31:0]; | |
849 | ||
850 | always @(clk or vbit) begin | |
851 | if (clk) | |
852 | dout[31:0] <= vbit[31:0]; | |
853 | end | |
854 | ||
855 | ||
856 | supply0 vss; | |
857 | supply1 vdd; | |
858 | ||
859 | endmodule | |
860 |